1/* 2 * Copyright (c) 2021 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8 9/* Macros for device tree declarations of npcx soc family */ 10#include <zephyr/dt-bindings/adc/adc.h> 11#include <zephyr/dt-bindings/clock/npcx_clock.h> 12#include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h> 13#include <zephyr/dt-bindings/gpio/gpio.h> 14#include <zephyr/dt-bindings/i2c/i2c.h> 15#include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h> 16#include <zephyr/dt-bindings/pwm/pwm.h> 17#include <zephyr/dt-bindings/sensor/npcx_tach.h> 18#include <freq.h> 19 20/ { 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-m4f"; 28 reg = <0>; 29 }; 30 }; 31 32 def-io-conf-list { 33 compatible = "nuvoton,npcx-pinctrl-def"; 34 /* Change default functional pads to GPIOs 35 * no_spip - PIN95.97.A1.A3 36 * no_fpip - PIN96.A0.A2.A4 - Internal flash only 37 * no_pwrgd - PIN72 38 * no_lpc_espi - PIN46.47.51.52.53.54.55.57 39 * no_peci_en - PIN81 40 * npsl_in1_sl - PIND2 41 * npsl_in2_sl - PIN00 42 * no_ksi0-7 - PIN31.30.27.26.25.24.23.22 43 * no_ks000-17 - PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04. 44 * 82.83.03.B1 45 */ 46 pinmux = <>; 47 }; 48 49 /** Dummy pinctrl node. It will be initialized with defaults based on the SoC series. 50 * Then, the user can override the pin control options at the board level. 51 */ 52 pinctrl: pinctrl { 53 compatible = "nuvoton,npcx-pinctrl"; 54 status = "okay"; 55 }; 56 57 /* Dummy node of IOs that have leakage current. The user can override 58 * 'leak-gpios' prop. at board DT file to save more power consumption. 59 */ 60 power_leakage_io: power-leakage-io { 61 compatible = "nuvoton,npcx-leakage-io"; 62 status = "okay"; 63 }; 64 65 soc { 66 pcc: clock-controller@4000d000 { 67 compatible = "nuvoton,npcx-pcc"; 68 /* Cells for bus type, clock control reg and bit */ 69 #clock-cells = <3>; 70 /* First reg region is Power Management Controller */ 71 /* Second reg region is Core Domain Clock Generator */ 72 reg = <0x4000d000 0x2000 73 0x400b5000 0x2000>; 74 reg-names = "pmc", "cdcg"; 75 }; 76 77 scfg: scfg@400c3000 { 78 compatible = "nuvoton,npcx-scfg"; 79 /* First reg region is System Configuration Device */ 80 /* Second reg region is Debugger Interface Device */ 81 /* Third reg region is System Glue Device */ 82 reg = <0x400c3000 0x70 83 0x400c3070 0x30 84 0x400a5000 0x2000>; 85 reg-names = "scfg", "dbg", "glue"; 86 #alt-cells = <3>; 87 #lvol-cells = <2>; 88 }; 89 90 mdc: mdc@4000c000 { 91 compatible = "syscon"; 92 reg = <0x4000c000 0xa>; 93 reg-io-width = <1>; 94 }; 95 96 mdc_header: mdc@4000c00a { 97 compatible = "syscon"; 98 reg = <0x4000c00a 0x4>; 99 reg-io-width = <2>; 100 }; 101 102 miwu0: miwu@400bb000 { 103 compatible = "nuvoton,npcx-miwu"; 104 reg = <0x400bb000 0x2000>; 105 index = <0>; 106 #miwu-cells = <2>; 107 }; 108 109 miwu1: miwu@400bd000 { 110 compatible = "nuvoton,npcx-miwu"; 111 reg = <0x400bd000 0x2000>; 112 index = <1>; 113 #miwu-cells = <2>; 114 }; 115 116 miwu2: miwu@400bf000 { 117 compatible = "nuvoton,npcx-miwu"; 118 reg = <0x400bf000 0x2000>; 119 index = <2>; 120 #miwu-cells = <2>; 121 }; 122 123 gpio0: gpio@40081000 { 124 compatible = "nuvoton,npcx-gpio"; 125 reg = <0x40081000 0x2000>; 126 gpio-controller; 127 index = <0x0>; 128 #gpio-cells=<2>; 129 }; 130 131 gpio1: gpio@40083000 { 132 compatible = "nuvoton,npcx-gpio"; 133 reg = <0x40083000 0x2000>; 134 gpio-controller; 135 index = <0x1>; 136 #gpio-cells=<2>; 137 }; 138 139 gpio2: gpio@40085000 { 140 compatible = "nuvoton,npcx-gpio"; 141 reg = <0x40085000 0x2000>; 142 gpio-controller; 143 index = <0x2>; 144 #gpio-cells=<2>; 145 }; 146 147 gpio3: gpio@40087000 { 148 compatible = "nuvoton,npcx-gpio"; 149 reg = <0x40087000 0x2000>; 150 gpio-controller; 151 index = <0x3>; 152 #gpio-cells=<2>; 153 }; 154 155 gpio4: gpio@40089000 { 156 compatible = "nuvoton,npcx-gpio"; 157 reg = <0x40089000 0x2000>; 158 gpio-controller; 159 index = <0x4>; 160 #gpio-cells=<2>; 161 }; 162 163 gpio5: gpio@4008b000 { 164 compatible = "nuvoton,npcx-gpio"; 165 reg = <0x4008b000 0x2000>; 166 gpio-controller; 167 index = <0x5>; 168 #gpio-cells=<2>; 169 }; 170 171 gpio6: gpio@4008d000 { 172 compatible = "nuvoton,npcx-gpio"; 173 reg = <0x4008d000 0x2000>; 174 gpio-controller; 175 index = <0x6>; 176 #gpio-cells=<2>; 177 }; 178 179 gpio7: gpio@4008f000 { 180 compatible = "nuvoton,npcx-gpio"; 181 reg = <0x4008f000 0x2000>; 182 gpio-controller; 183 index = <0x7>; 184 #gpio-cells=<2>; 185 }; 186 187 gpio8: gpio@40091000 { 188 compatible = "nuvoton,npcx-gpio"; 189 reg = <0x40091000 0x2000>; 190 gpio-controller; 191 index = <0x8>; 192 #gpio-cells=<2>; 193 }; 194 195 gpio9: gpio@40093000 { 196 compatible = "nuvoton,npcx-gpio"; 197 reg = <0x40093000 0x2000>; 198 gpio-controller; 199 index = <0x9>; 200 #gpio-cells=<2>; 201 }; 202 203 gpioa: gpio@40095000 { 204 compatible = "nuvoton,npcx-gpio"; 205 reg = <0x40095000 0x2000>; 206 gpio-controller; 207 index = <0xA>; 208 #gpio-cells=<2>; 209 }; 210 211 gpiob: gpio@40097000 { 212 compatible = "nuvoton,npcx-gpio"; 213 reg = <0x40097000 0x2000>; 214 gpio-controller; 215 index = <0xB>; 216 #gpio-cells=<2>; 217 }; 218 219 gpioc: gpio@40099000 { 220 compatible = "nuvoton,npcx-gpio"; 221 reg = <0x40099000 0x2000>; 222 gpio-controller; 223 index = <0xC>; 224 #gpio-cells=<2>; 225 }; 226 227 gpiod: gpio@4009b000 { 228 compatible = "nuvoton,npcx-gpio"; 229 reg = <0x4009b000 0x2000>; 230 gpio-controller; 231 index = <0xD>; 232 #gpio-cells=<2>; 233 }; 234 235 gpioe: gpio@4009d000 { 236 compatible = "nuvoton,npcx-gpio"; 237 reg = <0x4009d000 0x2000>; 238 gpio-controller; 239 index = <0xE>; 240 #gpio-cells=<2>; 241 }; 242 243 gpiof: gpio@4009f000 { 244 compatible = "nuvoton,npcx-gpio"; 245 reg = <0x4009f000 0x2000>; 246 gpio-controller; 247 index = <0xF>; 248 #gpio-cells=<2>; 249 }; 250 251 pwm0: pwm@40080000 { 252 compatible = "nuvoton,npcx-pwm"; 253 reg = <0x40080000 0x2000>; 254 pwm-channel = <0>; 255 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 0>; 256 #pwm-cells = <3>; 257 status = "disabled"; 258 }; 259 260 pwm1: pwm@40082000 { 261 compatible = "nuvoton,npcx-pwm"; 262 reg = <0x40082000 0x2000>; 263 pwm-channel = <1>; 264 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 1>; 265 #pwm-cells = <3>; 266 status = "disabled"; 267 }; 268 269 pwm2: pwm@40084000 { 270 compatible = "nuvoton,npcx-pwm"; 271 reg = <0x40084000 0x2000>; 272 pwm-channel = <2>; 273 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 2>; 274 #pwm-cells = <3>; 275 status = "disabled"; 276 }; 277 278 pwm3: pwm@40086000 { 279 compatible = "nuvoton,npcx-pwm"; 280 reg = <0x40086000 0x2000>; 281 pwm-channel = <3>; 282 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 3>; 283 #pwm-cells = <3>; 284 status = "disabled"; 285 }; 286 287 pwm4: pwm@40088000 { 288 compatible = "nuvoton,npcx-pwm"; 289 reg = <0x40088000 0x2000>; 290 pwm-channel = <4>; 291 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 4>; 292 #pwm-cells = <3>; 293 status = "disabled"; 294 }; 295 296 pwm5: pwm@4008a000 { 297 compatible = "nuvoton,npcx-pwm"; 298 reg = <0x4008a000 0x2000>; 299 pwm-channel = <5>; 300 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 5>; 301 #pwm-cells = <3>; 302 status = "disabled"; 303 }; 304 305 pwm6: pwm@4008c000 { 306 compatible = "nuvoton,npcx-pwm"; 307 reg = <0x4008c000 0x2000>; 308 pwm-channel = <6>; 309 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 6>; 310 #pwm-cells = <3>; 311 status = "disabled"; 312 }; 313 314 pwm7: pwm@4008e000 { 315 compatible = "nuvoton,npcx-pwm"; 316 reg = <0x4008e000 0x2000>; 317 pwm-channel = <7>; 318 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 7>; 319 #pwm-cells = <3>; 320 status = "disabled"; 321 }; 322 323 adc0: adc@400d1000 { 324 compatible = "nuvoton,npcx-adc"; 325 #io-channel-cells = <1>; 326 reg = <0x400d1000 0x2000>; 327 interrupts = <10 3>; 328 clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 4>; 329 vref-mv = <2816>; 330 status = "disabled"; 331 }; 332 333 twd0: watchdog@400d8000 { 334 compatible = "nuvoton,npcx-watchdog"; 335 reg = <0x400d8000 0x2000>; 336 t0-out = <&wui_t0out>; 337 }; 338 339 espi0: espi@4000a000 { 340 compatible = "nuvoton,npcx-espi"; 341 reg = <0x4000a000 0x2000>; 342 interrupts = <18 3>; /* Interrupt for eSPI Bus */ 343 344 /* clocks for eSPI modules */ 345 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL6 7>; 346 /* WUI maps for eSPI signals */ 347 espi-rst-wui = <&wui_espi_rst>; 348 349 #address-cells = <1>; 350 #size-cells = <0>; 351 #vw-cells = <3>; 352 status = "disabled"; 353 }; 354 355 host_sub: lpc@400c1000 { 356 compatible = "nuvoton,npcx-host-sub"; 357 /* host sub-module register address & size */ 358 reg = <0x400c1000 0x2000 359 0x40010000 0x2000 360 0x4000e000 0x2000 361 0x400c7000 0x2000 362 0x400c9000 0x2000 363 0x400cb000 0x2000>; 364 reg-names = "mswc", "shm", "c2h", "kbc", "pm_acpi", 365 "pm_hcmd"; 366 367 /* host sub-module IRQ and priority */ 368 interrupts = <25 3>, /* KBC Input-Buf-Full (IBF) */ 369 <56 3>, /* KBC Output-Buf-Empty (OBE) */ 370 <26 3>, /* PMCH Input-Buf-Full (IBF) */ 371 <3 3>, /* PMCH Output-Buf-Empty (OBE) */ 372 <6 3>; /* Port80 FIFO Not Empty */ 373 interrupt-names = "kbc_ibf", "kbc_obe", "pmch_ibf", 374 "pmch_obe", "p80_fifo"; 375 376 /* WUI map for accessing host sub-modules */ 377 host-acc-wui = <&wui_host_acc>; 378 379 /* clocks for host sub-modules */ 380 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 3>, 381 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>, 382 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>, 383 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>, 384 <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 7>; 385 }; 386 387 /* I2c Controllers - Do not use them as i2c node directly */ 388 i2c_ctrl0: i2c@40009000 { 389 compatible = "nuvoton,npcx-i2c-ctrl"; 390 reg = <0x40009000 0x1000>; 391 interrupts = <13 3>; 392 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>; 393 status = "disabled"; 394 }; 395 396 i2c_ctrl1: i2c@4000b000 { 397 compatible = "nuvoton,npcx-i2c-ctrl"; 398 reg = <0x4000b000 0x1000>; 399 interrupts = <14 3>; 400 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>; 401 status = "disabled"; 402 }; 403 404 i2c_ctrl2: i2c@400c0000 { 405 compatible = "nuvoton,npcx-i2c-ctrl"; 406 reg = <0x400c0000 0x1000>; 407 interrupts = <36 3>; 408 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>; 409 status = "disabled"; 410 }; 411 412 i2c_ctrl3: i2c@400c2000 { 413 compatible = "nuvoton,npcx-i2c-ctrl"; 414 reg = <0x400c2000 0x1000>; 415 interrupts = <37 3>; 416 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>; 417 status = "disabled"; 418 }; 419 420 i2c_ctrl4: i2c@40008000 { 421 compatible = "nuvoton,npcx-i2c-ctrl"; 422 reg = <0x40008000 0x1000>; 423 interrupts = <19 3>; 424 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>; 425 status = "disabled"; 426 }; 427 428 i2c_ctrl5: i2c@40017000 { 429 compatible = "nuvoton,npcx-i2c-ctrl"; 430 reg = <0x40017000 0x1000>; 431 interrupts = <20 3>; 432 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>; 433 status = "disabled"; 434 }; 435 436 i2c_ctrl6: i2c@40018000 { 437 compatible = "nuvoton,npcx-i2c-ctrl"; 438 reg = <0x40018000 0x1000>; 439 interrupts = <16 3>; 440 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>; 441 status = "disabled"; 442 }; 443 444 i2c_ctrl7: i2c@40019000 { 445 compatible = "nuvoton,npcx-i2c-ctrl"; 446 reg = <0x40019000 0x1000>; 447 interrupts = <8 3>; 448 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>; 449 status = "disabled"; 450 }; 451 452 tach1: tach@400e1000 { 453 compatible = "nuvoton,npcx-tach"; 454 reg = <0x400e1000 0x2000>; 455 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 5>; 456 status = "disabled"; 457 }; 458 459 tach2: tach@400e3000 { 460 compatible = "nuvoton,npcx-tach"; 461 reg = <0x400e3000 0x2000>; 462 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 6>; 463 status = "disabled"; 464 }; 465 466 ps2_ctrl0: ps2@400b1000 { 467 compatible = "nuvoton,npcx-ps2-ctrl"; 468 reg = <0x400b1000 0x1000>; 469 interrupts = <21 4>; 470 clocks = <&pcc NPCX_CLOCK_BUS_FREERUN NPCX_PWDWN_CTL1 3>; 471 472 /* PS2 Channels - Please use them as PS2 node */ 473 ps2_channel0: io_ps2_channel0 { 474 compatible = "nuvoton,npcx-ps2-channel"; 475 channel = <0x00>; 476 status = "disabled"; 477 }; 478 479 ps2_channel1: io_ps2_channel1 { 480 compatible = "nuvoton,npcx-ps2-channel"; 481 channel = <0x01>; 482 status = "disabled"; 483 }; 484 485 ps2_channel2: io_ps2_channel2 { 486 compatible = "nuvoton,npcx-ps2-channel"; 487 channel = <0x02>; 488 status = "disabled"; 489 }; 490 491 ps2_channel3: io_ps2_channel3 { 492 compatible = "nuvoton,npcx-ps2-channel"; 493 channel = <0x03>; 494 status = "disabled"; 495 }; 496 }; 497 498 /* Dedicated Quad-SPI interface to access SPI flashes */ 499 qspi_fiu0: quadspi@40020000 { 500 compatible = "nuvoton,npcx-fiu-qspi"; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 reg = <0x40020000 0x2000>; 504 }; 505 506 peci0: peci@400d4000 { 507 compatible = "nuvoton,npcx-peci"; 508 reg = <0x400d4000 0x1000>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 interrupts = <4 4>; 512 clocks = <&pcc NPCX_CLOCK_BUS_FMCLK NPCX_PWDWN_CTL4 5>; 513 status = "disabled"; 514 }; 515 516 kbd: kbd@400a3000 { 517 compatible = "nuvoton,npcx-kbd"; 518 reg = <0x400a3000 0x2000>; 519 interrupts = <49 4>; 520 clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>; 521 wui-maps = <&wui_io31 &wui_io30 &wui_io27 &wui_io26 522 &wui_io25 &wui_io24 &wui_io23 &wui_io22>; 523 status = "disabled"; 524 }; 525 526 spip0: spi@400d2000 { 527 compatible = "nuvoton,npcx-spip"; 528 reg = <0x400d2000 0x1000>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 interrupts = <57 3>; 532 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL4 7>; 533 status = "disabled"; 534 535 }; 536 }; 537 538 soc-if { 539 /* Soc specific peripheral interface phandles which don't contain 540 * 'reg' prop. Please overwrite 'status' prop. to 'okay' if you 541 * want to switch the interface from io to specific peripheral. 542 */ 543 host_uart: io_host_uart { 544 compatible = "nuvoton,npcx-host-uart"; 545 status = "disabled"; 546 }; 547 548 i2c0_0: io_i2c_ctrl0_port0 { 549 compatible = "nuvoton,npcx-i2c-port"; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 port = <0x00>; 553 controller = <&i2c_ctrl0>; 554 status = "disabled"; 555 }; 556 557 i2c1_0: io_i2c_ctrl1_port0 { 558 compatible = "nuvoton,npcx-i2c-port"; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 port = <0x10>; 562 controller = <&i2c_ctrl1>; 563 status = "disabled"; 564 }; 565 566 i2c2_0: io_i2c_ctrl2_port0 { 567 compatible = "nuvoton,npcx-i2c-port"; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 port = <0x20>; 571 controller = <&i2c_ctrl2>; 572 status = "disabled"; 573 }; 574 575 i2c3_0: io_i2c_ctrl3_port0 { 576 compatible = "nuvoton,npcx-i2c-port"; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 port = <0x30>; 580 controller = <&i2c_ctrl3>; 581 status = "disabled"; 582 }; 583 584 i2c4_1: io_i2c_ctrl4_port1 { 585 compatible = "nuvoton,npcx-i2c-port"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 port = <0x41>; 589 controller = <&i2c_ctrl4>; 590 status = "disabled"; 591 }; 592 593 i2c5_0: io_i2c_ctrl5_port0 { 594 compatible = "nuvoton,npcx-i2c-port"; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 port = <0x50>; 598 controller = <&i2c_ctrl5>; 599 status = "disabled"; 600 }; 601 602 i2c5_1: io_i2c_ctrl5_port1 { 603 compatible = "nuvoton,npcx-i2c-port"; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 port = <0x51>; 607 controller = <&i2c_ctrl5>; 608 status = "disabled"; 609 }; 610 611 i2c6_0: io_i2c_ctrl6_port0 { 612 compatible = "nuvoton,npcx-i2c-port"; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 port = <0x60>; 616 controller = <&i2c_ctrl6>; 617 status = "disabled"; 618 }; 619 620 i2c6_1: io_i2c_ctrl6_port1 { 621 compatible = "nuvoton,npcx-i2c-port"; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 port = <0x61>; 625 controller = <&i2c_ctrl6>; 626 status = "disabled"; 627 }; 628 629 i2c7_0: io_i2c_ctrl7_port0 { 630 compatible = "nuvoton,npcx-i2c-port"; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 port = <0x70>; 634 controller = <&i2c_ctrl7>; 635 status = "disabled"; 636 }; 637 638 power_ctrl_psl: power-ctrl-psl { 639 compatible = "nuvoton,npcx-power-psl"; 640 status = "disabled"; 641 }; 642 }; 643 644 soc-id { 645 compatible = "nuvoton,npcx-soc-id"; 646 family-id = <0x20>; 647 }; 648 649 booter-variant { 650 compatible = "nuvoton,npcx-booter-variant"; 651 }; 652}; 653 654&nvic { 655 arm,num-irq-priority-bits = <3>; 656}; 657
