Searched refs:CCR (Results 1 – 19 of 19) sorted by relevance
| /Zephyr-latest/soc/nxp/imxrt/imxrt7xx/cm33/ |
| D | flash_clock_setup.c | 16 cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | in enable_xspi_cache()
18 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) { in enable_xspi_cache()
21 cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in enable_xspi_cache()
23 cache->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK; in enable_xspi_cache()
28 cache->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | in disable_xspi_cache()
30 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) { in disable_xspi_cache()
33 cache->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK); in disable_xspi_cache()
36 cache->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK; in disable_xspi_cache()
50 if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U) { in flash_deinit()
105 if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0x00U) { in flash_init()
|
| /Zephyr-latest/soc/nordic/nrf54h/ |
| D | pm_s2ram.c | 48 uint32_t CCR; member
133 backup->CCR = SCB->CCR; in scb_suspend()
150 SCB->CCR = backup->CCR; in scb_resume()
|
| /Zephyr-latest/soc/infineon/cat3/xmc4xxx/ |
| D | soc.c | 26 SCB->CCR &= ~SCB_CCR_UNALIGN_TRP_Msk; in soc_reset_hook()
|
| /Zephyr-latest/arch/arm/include/cortex_m/ |
| D | stack.h | 60 SCB->CCR |= SCB_CCR_STKALIGN_Msk; in z_arm_interrupt_stack_setup()
|
| /Zephyr-latest/soc/renesas/ra/ra8d1/ |
| D | soc.c | 48 SCB->CCR = (uint32_t)CCR_CACHE_ENABLE; in soc_early_init_hook()
|
| /Zephyr-latest/boards/nxp/frdm_mcxn947/ |
| D | board.c | 64 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in enable_cache64()
65 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in enable_cache64()
67 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) { in enable_cache64()
70 CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK); in enable_cache64()
|
| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | scb.c | 122 if (SCB->CCR & SCB_CCR_DC_Msk) { in z_arm_init_arch_hw_at_boot()
|
| D | fault.c | 650 SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk; in z_arm_is_synchronous_svc()
656 SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk; in z_arm_is_synchronous_svc()
1094 SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
1114 SCB->CCR |= SCB_CCR_STKOFHFNMIGN_Msk;
1117 SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
1119 SCB->CCR &= ~SCB_CCR_UNALIGN_TRP_Msk;
|
| /Zephyr-latest/drivers/dma/ |
| D | dma_pl330.h | 118 CCR, enumerator
|
| D | dma_pl330.c | 184 CCR, ccr); in dma_pl330_setup_ch()
240 CCR, ccr); in dma_pl330_setup_ch()
|
| /Zephyr-latest/tests/arch/arm/arm_thread_swap/src/ |
| D | arm_syscalls.c | 213 SCB->CCR |= SCB_CCR_USERSETMPEND_Msk; in ZTEST()
|
| /Zephyr-latest/drivers/flash/ |
| D | flash_stm32h7x.c | 725 if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
837 SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
844 SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
|
| D | flash_stm32_qspi.c | 226 LOG_DBG("CCR 0x%x", dev_cfg->regs->CCR); in qspi_send_cmd()
303 LOG_DBG("CCR 0x%x", dev_cfg->regs->CCR); in qspi_write_access()
470 return READ_BIT(dev_data->hqspi.Instance->CCR, QUADSPI_CCR_FMODE) == QUADSPI_CCR_FMODE; in stm32_qspi_is_memory_mapped()
|
| D | flash_stm32_xspi.c | 85 LOG_DBG("CCR 0x%x", dev_data->hxspi.Instance->CCR); in xspi_send_cmd()
|
| D | flash_stm32_ospi.c | 214 LOG_DBG("CCR 0x%x", dev_cfg->regs->CCR); in ospi_send_cmd()
|
| /Zephyr-latest/arch/arm/core/mpu/ |
| D | arm_mpu.c | 445 if (SCB->CCR & SCB_CCR_DC_Msk) { in z_arm_mpu_init()
|
| /Zephyr-latest/soc/nxp/imxrt/imxrt10xx/ |
| D | lpm_rt1064.c | 169 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) { in flexspi_exit_critical()
|
| /Zephyr-latest/drivers/i2c/ |
| D | i2c_ll_stm32_v1.c | 96 ccr = LL_I2C_ReadReg(i2c, CCR); in stm32_i2c_reset()
114 LL_I2C_WriteReg(i2c, CCR, ccr); in stm32_i2c_reset()
|
| /Zephyr-latest/drivers/ethernet/ |
| D | eth_sam_gmac.c | 67 dcache_enabled = (SCB->CCR & SCB_CCR_DC_Msk); in dcache_is_enabled()
|
