1 /* 2 * Copyright (c) 2013-2014 Wind River Systems, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief Stack helpers for Cortex-M CPUs 10 * 11 * Stack helper functions. 12 */ 13 14 #ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_STACK_H_ 15 #define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_STACK_H_ 16 17 #ifdef _ASMLANGUAGE 18 19 /* nothing */ 20 21 #else 22 23 #include <cmsis_core.h> 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, 30 CONFIG_ISR_STACK_SIZE); 31 32 /** 33 * 34 * @brief Setup interrupt stack 35 * 36 * On Cortex-M, the interrupt stack is registered in the MSP (main stack 37 * pointer) register, and switched to automatically when taking an exception. 38 * 39 */ z_arm_interrupt_stack_setup(void)40static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void) 41 { 42 uint32_t msp = 43 (uint32_t)(K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) + 44 K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]); 45 46 __set_MSP(msp); 47 #if defined(CONFIG_BUILTIN_STACK_GUARD) 48 #if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM) 49 __set_MSPLIM((uint32_t)z_interrupt_stacks[0]); 50 #else 51 #error "Built-in MSP limit checks not supported by HW" 52 #endif 53 #endif /* CONFIG_BUILTIN_STACK_GUARD */ 54 55 #if defined(CONFIG_STACK_ALIGN_DOUBLE_WORD) 56 /* Enforce double-word stack alignment on exception entry 57 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest 58 * of ARM Cortex-M processors this setting is enforced by 59 * default and it is not configurable. 60 */ 61 #if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4) 62 SCB->CCR |= SCB_CCR_STKALIGN_Msk; 63 #endif 64 #endif /* CONFIG_STACK_ALIGN_DOUBLE_WORD */ 65 } 66 67 #ifdef __cplusplus 68 } 69 #endif 70 71 #endif /* _ASMLANGUAGE */ 72 73 #endif /* ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_STACK_H_ */ 74
