Home
last modified time | relevance | path

Searched refs:w3 (Results 1 – 25 of 27) sorted by relevance

12

/trusted-firmware-a-latest/drivers/st/uart/aarch64/
Dstm32_console.S54 ldr w3, [x0, #USART_CR1]
55 tst w3, #USART_CR1_UE
63 ldr w3, [x0, #USART_CR1]
65 bic w3, w3, w4
66 str w3, [x0, #USART_CR1]
70 orr w3, w3, w4
71 str w3, [x0, #USART_CR1]
72 ldr w3, [x0, #USART_CR2]
74 bic w3, w3, w4
75 str w3, [x0, #USART_CR2]
[all …]
/trusted-firmware-a-latest/drivers/marvell/uart/
Da3700_console.S54 ldr w3, [x0, #UART_STATUS_REG]
55 and w3, w3, #UARTLSR_TXEMPTY
56 cmp w3, #0
60 mov w3, #60000 /* 60000 cycles of below 3 instructions on 1200 MHz CPU ~~ 100 us */
62 sub w3, w3, #1
63 cmp w3, #0
74 ldr w3, [x4]
75 bic w3, w3, #MVEBU_NB_RESET_UART_N
76 str w3, [x4]
77 orr w3, w3, #MVEBU_NB_RESET_UART_N
[all …]
/trusted-firmware-a-latest/drivers/amlogic/console/aarch64/
Dmeson_console.S95 mov_imm w3, 24000000 /* TODO: This only works with a 24 MHz clock. */
96 cmp w1, w3
101 mov w3, #3
102 udiv w3, w1, w3
103 udiv w3, w3, w2
104 sub w3, w3, #1
105 orr w3, w3, #((1 << MESON_REG5_USE_XTAL_CLK_BIT) | \
107 str w3, [x0, #MESON_REG5_OFFSET]
109 ldr w3, [x0, #MESON_CONTROL_OFFSET]
110 orr w3, w3, #((1 << MESON_CONTROL_CLR_ERROR_BIT) | \
[all …]
/trusted-firmware-a-latest/plat/mediatek/drivers/uart/
D8250_console.S39 mov w3, #(UART_MCR_DTR | UART_MCR_RTS)
40 str w3, [x0, #UART_MCR]
43 movz w3, #:abs_g1:115200
44 movk w3, #:abs_g0_nc:115200
45 cmp w2, w3
50 mov w3, wzr
55 mov w3, #2
58 2: str w3, [x0, #UART_HIGHSPEED]
61 udiv w3, w1, w2 /* divisor = uartclk / (quot * baudrate) */
62 msub w1, w3, w2, w1 /* remainder = uartclk % (quot * baudrate) */
[all …]
/trusted-firmware-a-latest/drivers/ti/uart/aarch64/
D16550_console.S54 ldr w3, [x0, #UARTLCR]
55 orr w3, w3, #UARTLCR_DLAB
56 str w3, [x0, #UARTLCR] /* enable DLL, DLLM programming */
60 and w3, w3, w2
61 str w3, [x0, #UARTLCR] /* disable DLL, DLLM programming */
64 mov w3, #3
65 str w3, [x0, #UARTLCR]
67 mov w3, #0
68 str w3, [x0, #UARTIER]
71 str w3, [x0, #UARTMDR1]
[all …]
/trusted-firmware-a-latest/plat/qti/msm8916/aarch64/
Duartdm_console.S76 ldr w3, [x1, #UART_DM_SR]
77 tbnz w3, #UART_DM_SR_TXEMT_BIT, 2f
83 mov w3, #UART_DM_CR_RESET_RX
84 str w3, [x1, #UART_DM_CR]
87 mov w3, #UART_DM_CR_RESET_TX
88 str w3, [x1, #UART_DM_CR]
96 mov w3, #UART_DM_DMEN_TX_SC
97 str w3, [x1, #UART_DM_DMEN]
100 mov w3, #UART_DM_CR_TX_ENABLE
101 str w3, [x1, #UART_DM_CR]
/trusted-firmware-a-latest/drivers/nxp/console/
D16550_console.S107 ldrb w3, [x0, #UARTLCR]
108 orr w3, w3, #UARTLCR_DLAB
109 strb w3, [x0, #UARTLCR] /* enable DLL, DLLM programming */
113 and w3, w3, w2
114 strb w3, [x0, #UARTLCR] /* disable DLL, DLLM programming */
117 mov w3, #3
118 strb w3, [x0, #UARTLCR]
120 mov w3, #0
121 strb w3, [x0, #UARTIER]
123 mov w3, #(UARTFCR_FIFOEN |UARTFCR_TXCLR | UARTFCR_RXCLR)
[all …]
/trusted-firmware-a-latest/plat/nxp/soc-ls1046a/aarch64/
Dls1046a.S100 rev w3, w2
101 str w3, [x1, #SCFG_COREBCR_OFFSET]
107 rev w3, w2
108 orr w3, w3, w0
109 rev w2, w3
136 rev w2, w3
160 lsl w1, w3, #16
292 rev w3, w1
293 str w3, [x2, x0]
320 rev w3, w1
[all …]
/trusted-firmware-a-latest/plat/nxp/soc-ls1043a/aarch64/
Dls1043a.S123 CoreMaskMsb w2, w3
130 rev w3, w2
131 str w3, [x1, #SCFG_COREBCR_OFFSET]
137 rev w3, w2
138 orr w3, w3, w0
139 rev w2, w3
180 lsl w1, w3, #16
590 ldr w3, [x4, #GICC_CTLR_OFFSET]
591 bic w3, w3, #GICC_CTLR_EN_GRP0
592 bic w3, w3, #GICC_CTLR_EN_GRP1
[all …]
/trusted-firmware-a-latest/drivers/arm/css/sds/aarch64/
Dsds_helpers.S36 mov w3, #0
47 add w3, w3, #0x1
48 cmp w1, w3
/trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/pmu/
Dplat_pmu_macros.S44 ldr w3, [x4, x5]
46 cmp w3, #PMU_CLST_RET
98 and w3, w1, #DDRC1_SREF_DONE_EXT
99 orr w2, w2, w3
125 and w3, w1, #DDRC1_SREF_DONE_EXT
126 orr w2, w2, w3
/trusted-firmware-a-latest/plat/nvidia/tegra/drivers/spe/
Dshared_console.S104 mov w3, #(CONSOLE_RING_DOORBELL | (1 << CONSOLE_NUM_BYTES_SHIFT))
105 orr w2, w2, w3
114 mov w3, #(CONSOLE_RING_DOORBELL | (1 << CONSOLE_NUM_BYTES_SHIFT))
115 orr w2, w2, w3
/trusted-firmware-a-latest/drivers/arm/pl011/aarch64/
Dpl011_console.S47 ldr w3, [x0, #UARTCR]
49 bic w3, w3, w4
50 str w3, [x0, #UARTCR]
/trusted-firmware-a-latest/plat/nxp/soc-ls1088a/aarch64/
Dls1088a.S366 mov w3, #GICR_ICENABLER0_SGI15
367 str w3, [x5, #GICR_ICENABLER0_OFFSET]
388 ldr w3, [x5, #GICR_IGRPMODR0_OFFSET]
389 bic w3, w3, #GICR_IGRPMODR0_SGI15
390 str w3, [x5, #GICR_IGRPMODR0_OFFSET]
398 mov w3, #GICR_ISENABLER0_SGI15
399 str w3, [x5, #GICR_ISENABLER0_OFFSET]
897 cmp w1, w3
1677 ldr w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]
1678 orr w3, w3, w2
[all …]
/trusted-firmware-a-latest/drivers/cadence/uart/aarch64/
Dcdns_console.S44 mov w3, #(R_UART_CR_TX_EN | R_UART_CR_RX_EN | R_UART_CR_TXRST | R_UART_CR_RXRST)
45 str w3, [x0, #R_UART_CR]
/trusted-firmware-a-latest/plat/nxp/soc-lx2160a/aarch64/
Dlx2160a.S356 mov w3, #GICR_ICENABLER0_SGI15
357 str w3, [x5, #GICR_ICENABLER0_OFFSET]
378 ldr w3, [x5, #GICR_IGRPMODR0_OFFSET]
379 bic w3, w3, #GICR_IGRPMODR0_SGI15
380 str w3, [x5, #GICR_IGRPMODR0_OFFSET]
388 mov w3, #GICR_ISENABLER0_SGI15
389 str w3, [x5, #GICR_ISENABLER0_OFFSET]
1000 bic w7, w3, w4
1017 bic w9, w3, w4
1036 bic w3, w3, w6
[all …]
/trusted-firmware-a-latest/plat/nvidia/tegra/soc/t194/
Dplat_trampoline.S56 ldrb w3, [x1], #1
57 strb w3, [x0], #1
/trusted-firmware-a-latest/plat/nxp/soc-ls1028a/aarch64/
Dls1028a.S323 mov w3, #GICR_ICENABLER0_SGI15
324 str w3, [x5, #GICR_ICENABLER0_OFFSET]
345 ldr w3, [x5, #GICR_IGRPMODR0_OFFSET]
346 bic w3, w3, #GICR_IGRPMODR0_SGI15
347 str w3, [x5, #GICR_IGRPMODR0_OFFSET]
355 mov w3, #GICR_ISENABLER0_SGI15
356 str w3, [x5, #GICR_ISENABLER0_OFFSET]
/trusted-firmware-a-latest/lib/cpus/aarch64/
Dcpu_helpers.S165 and w2, w2, w3
183 and w1, w1, w3
Dcortex_a76.S255 orr w3, wzr, #SMCCC_ARCH_WORKAROUND_2
259 ccmp w2, w3, #0, eq
/trusted-firmware-a-latest/plat/ti/k3/common/
Dk3_helpers.S150 mov w3, #0x0
/trusted-firmware-a-latest/plat/nvidia/tegra/common/aarch64/
Dtegra_helpers.S233 ldrb w3, [x1], #1
234 strb w3, [x0], #1
/trusted-firmware-a-latest/lib/aarch64/
Dmisc_helpers.S407 ldrb w3, [x1], #1
408 strb w3, [x0], #1
/trusted-firmware-a-latest/plat/common/aarch64/
Dcrash_console_helpers.S87 stlrb w3, [x1]
/trusted-firmware-a-latest/services/std_svc/spmd/
Dspmd_logical_sp.c413 uint32_t w3; in spmd_el3_populate_logical_partition_info() local
427 w3 = (uint32_t)(x2 >> 32); in spmd_el3_populate_logical_partition_info()
432 target_uuid[3] = w3; in spmd_el3_populate_logical_partition_info()

12