Lines Matching refs:w3
123 CoreMaskMsb w2, w3
130 rev w3, w2
131 str w3, [x1, #SCFG_COREBCR_OFFSET]
137 rev w3, w2
138 orr w3, w3, w0
139 rev w2, w3
180 lsl w1, w3, #16
590 ldr w3, [x4, #GICC_CTLR_OFFSET]
591 bic w3, w3, #GICC_CTLR_EN_GRP0
592 bic w3, w3, #GICC_CTLR_EN_GRP1
593 str w3, [x4, #GICC_CTLR_OFFSET]
609 bic w3, w3, #GICC_CTLR_ACKCTL_MASK
610 orr w3, w3, #GICC_CTLR_FIQ_EN_MASK
611 orr w3, w3, #GICC_CTLR_EOImodeS_MASK
612 orr w3, w3, #GICC_CTLR_CBPR_MASK
613 str w3, [x4, #GICC_CTLR_OFFSET]
644 orr w3, w3, #GICC_CTLR_EN_GRP0
645 str w3, [x4, #GICC_CTLR_OFFSET]
758 rev w3, w1
759 str w3, [x2, #SCFG_BOOTLOCPTRL_OFFSET]
763 rev w3, w1
764 str w3, [x2, #SCFG_BOOTLOCPTRH_OFFSET]
1283 rev w3, w1
1284 str w3, [x2, x0]
1308 rev w3, w1
1309 str w3, [x2, x0]
1334 rev w3, w1
1335 str w3, [x2, x0]
1360 rev w3, w1
1361 str w3, [x2, x0]
1491 ldr w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]
1492 rev w4, w3
1494 rev w3, w4
1495 str w3, [x6, #DDR_SDRAM_CFG_2_OFFSET] /* put ddr in self refresh - end */
1496 orr w3, w5, #DEVDISR5_MEM /* quiesce ddr clocks - start */
1497 rev w4, w3
1500 mov w3, #DEVDISR5_MEM
1501 rev w3, w3 /* polling mask */
1508 tst w1, w3
1532 tst w1, w3
1538 ldr w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]
1539 rev w4, w3
1541 rev w3, w4
1546 str w3, [x6, #DDR_SDRAM_CFG_2_OFFSET] /* take ddr out-of self refresh - end */
1603 ldr w3, [x6, #DDR_SDRAM_CFG_2_OFFSET]
1604 rev w4, w3
1606 rev w3, w4
1607 str w3, [x6, #DDR_SDRAM_CFG_2_OFFSET] /* put ddr in self refresh - end */
1608 orr w3, w5, #DEVDISR5_MEM /* quiesce ddr clocks - start */
1609 rev w4, w3
1612 mov w3, #DEVDISR5_MEM
1613 rev w3, w3 /* polling mask */
1620 tst w1, w3