Lines Matching refs:w3
100 rev w3, w2
101 str w3, [x1, #SCFG_COREBCR_OFFSET]
107 rev w3, w2
108 orr w3, w3, w0
109 rev w2, w3
136 rev w2, w3
160 lsl w1, w3, #16
292 rev w3, w1
293 str w3, [x2, x0]
320 rev w3, w1
321 str w3, [x2, x0]
374 ldr w3, [x5, #GICC_CTLR_OFFSET]
375 bic w3, w3, #GICC_CTLR_EN_GRP0
376 bic w3, w3, #GICC_CTLR_EN_GRP1
377 str w3, [x5, #GICC_CTLR_OFFSET]
400 bic w3, w3, #GICC_CTLR_ACKCTL_MASK
401 orr w3, w3, #GICC_CTLR_FIQ_EN_MASK
402 orr w3, w3, #GICC_CTLR_EOImodeS_MASK
403 orr w3, w3, #GICC_CTLR_CBPR_MASK
404 str w3, [x5, #GICC_CTLR_OFFSET]
428 orr w3, w3, #GICC_CTLR_EN_GRP0
429 str w3, [x2, #GICC_CTLR_OFFSET]
522 ldr w3, [x1, #GICC_CTLR_OFFSET]
523 bic w3, w3, #GICC_CTLR_EN_GRP0
524 str w3, [x1, #GICC_CTLR_OFFSET]
564 rev w3, w1
565 str w3, [x2, #SCFG_BOOTLOCPTRL_OFFSET]
569 rev w3, w1
570 str w3, [x2, #SCFG_BOOTLOCPTRH_OFFSET]