Searched refs:L1 (Results 1 – 25 of 33) sorted by relevance
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| /Zephyr-latest/samples/subsys/zbus/priority_boost/ |
| D | README.rst | 63 I: 0 ---> L1: T1 prio 5
72 I: 1 ---> L1: T1 prio 5
81 I: 2 ---> L1: T1 prio 5
88 I: 3 ---> L1: T1 prio 5
95 I: 4 ---> L1: T1 prio 5
101 I: 5 ---> L1: T1 prio 5
107 I: 6 ---> L1: T1 prio 5
144 I: 0 ---> L1: T1 prio 1
153 I: 1 ---> L1: T1 prio 1
162 I: 2 ---> L1: T1 prio 2
[all …]
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| /Zephyr-latest/scripts/coccinelle/ |
| D | ms_timeout.cocci | 89 expression L1;
92 fn(..., T, L1)
147 expression L1;
151 fn(..., T, L2, L1)
167 , L2, L1)
194 , L2, L1)
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| /Zephyr-latest/drivers/cache/ |
| D | Kconfig.andes | 19 When L2 cache is inclusive of L1, CPU only needs to perform operations
20 on L2 cache, instead of on both L1 and L2 caches.
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| /Zephyr-latest/drivers/dma/ |
| D | Kconfig.intel_adsp_hda | 46 bool "Intel ADSP HDA Host L1 Exit Interrupt"
50 Intel ADSP HDA Host Interrupt for L1 exit.
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| /Zephyr-latest/drivers/eeprom/ |
| D | Kconfig.stm32 | 11 Enable EEPROM support on the STM32 L0, L1 family of processors.
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| /Zephyr-latest/arch/arm/core/cortex_a_r/ |
| D | Kconfig | 115 bool "Control segregation of L1 I/D-Cache ways between Flash and AXIM"
118 Control segregation of L1 I/D-Cache ways between Flash and AXIM.
123 int "L1 I-Cache Flash way"
128 Configure L1 I-Cache ways for Flash interface. Default is reset value, all
132 int "L1 D-Cache Flash way"
137 Configure L1 D-Cache ways for Flash interface. Default is reset value,
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| /Zephyr-latest/doc/connectivity/networking/api/ |
| D | net_l2.rst | 148 - L2 -> L1: Methods as :c:func:`ieee802154_send` and several IEEE 802.15.4 net
153 - L1 -> L2: There are several situations in which the driver needs to initiate
154 calls into the L2/MAC layer. Zephyr's IEEE 802.15.4 L1 -> L2 adaptation API
158 MAC (L2) and PHY (L1) whenever reverse information transfer or close co-operation
164 from L1 into L2 are not implemented as methods in :c:struct:`ieee802154_radio_api`
168 of the L1 -> L2 "inversion-of-control" adaptation API.
172 within the PHY (L1) layer implemented independently of any specific L2 stack, see for
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| /Zephyr-latest/drivers/counter/ |
| D | Kconfig.stm32_rtc | 16 Tested on STM32 C0, F0, F2, F3, F4, F7, G0, G4, H7, L1, L4, L5, U5 series
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| /Zephyr-latest/boards/shields/adafruit_data_logger/ |
| D | adafruit_data_logger.overlay | 16 * pins "L1" and "Digital I/O 3".
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| /Zephyr-latest/arch/xtensa/core/ |
| D | README_MMU.txt | 20 Like the L1 cache, the TLB is split into separate instruction and data
162 top-level "L1" page containing the mappings for the page table
171 2. Pin the L1 page table PTE into the data TLB. This creates a double
232 the statically allocated array of L1 page table pages.
246 the L1 data cache on the CPU. If the physical memory storing page
252 lets the L1 data cache act as a "L2 TLB" for applications with a lot
257 But it is also important to note that the L1 data cache on Xtensa is
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| /Zephyr-latest/soc/nxp/imxrt/ |
| D | Kconfig.defconfig | 97 # have L1 instruction and data caches that should be enabled at boot
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| /Zephyr-latest/boards/shields/adafruit_data_logger/doc/ |
| D | index.rst | 47 connections must be established between the ``L1`` and ``Digital I/O 3`` pins for ``LED1``
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| /Zephyr-latest/boards/toradex/verdin_imx8mp/doc/ |
| D | index.rst | 35 energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1
47 master interface. The Arm Cortex-M7 Platform boasts features like a 32 KB L1 Instruction Cache, 32
48 KB L1 Data Cache, Floating Point Unit (FPU) with FPv5 architecture support, and an Internal Trace
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| /Zephyr-latest/doc/hardware/arch/ |
| D | arc-support-status.rst | 36 | Execution with caches - Instruction/Data, L1/L2 caches | Y | Y | …
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| /Zephyr-latest/boards/beagle/beaglebone_ai64/doc/ |
| D | index.rst | 16 L1 Memory System
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| /Zephyr-latest/boards/arduino/portenta_h7/doc/ |
| D | index.rst | 14 with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory inte…
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| /Zephyr-latest/dts/riscv/ite/ |
| D | it8xxx2-wuc-map.dtsi | 336 wucs = <&wuc15 BIT(1)>; /* GPIO L1 */
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| /Zephyr-latest/doc/services/zbus/ |
| D | index.rst | 163 ``L1`` and ``L2``; and channel A. Supposing ``L1``, ``L2``, ``MS1``, ``MS2``, and ``S1`` observer
182 ZBUS_OBSERVERS(L1, L2, MS1, MS2, S1), /* observers */
221 - The VDED executes L1 and L2 in the respective sequence. Inside the listeners, usually, there
278 - The VDED executes L1 and L2 in the respective sequence. Inside the listeners, usually, there
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| /Zephyr-latest/arch/xtensa/ |
| D | Kconfig | 205 int "Number of L1 page tables"
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| /Zephyr-latest/boards/96boards/avenger96/doc/ |
| D | index.rst | 60 - L1 32-Kbyte I / 32-Kbyte D for each core
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| /Zephyr-latest/soc/intel/intel_adsp/cavs/include/ |
| D | xtensa-cavs-linker.ld | 28 * mapping is set up to bypass the L1 cache, so it must be used when
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| /Zephyr-latest/boards/st/stm32mp157c_dk2/doc/ |
| D | stm32mp157_dk2.rst | 58 - L1 32-Kbyte I / 32-Kbyte D for each core
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| /Zephyr-latest/modules/ |
| D | Kconfig.mcux | 44 Set if the L1 or L2 cache is present in the SoC.
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| /Zephyr-latest/boards/st/stm32h747i_disco/doc/ |
| D | index.rst | 11 with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory inte…
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| /Zephyr-latest/soc/intel/intel_adsp/ace/ |
| D | ace-link.ld | 28 * mapping is set up to bypass the L1 cache, so it must be used when
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