1# Copyright 2017-2024 NXP 2# SPDX-License-Identifier: Apache-2.0 3 4if SOC_FAMILY_NXP_IMXRT 5 6# Source series Kconfig files first, so SOCs 7# can override the defaults given here 8rsource "*/Kconfig.defconfig" 9 10if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X 11 12config ROM_START_OFFSET 13 default 0x400 if BOOTLOADER_MCUBOOT 14 default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR 15 16config ADC_MCUX_12B1MSPS_SAR 17 default y if HAS_MCUX_12B1MSPS_SAR 18 depends on ADC 19 20config LOG_BACKEND_SWO_FREQ_HZ 21 default 7500000 22 depends on LOG_BACKEND_SWO 23 24# set the tick per sec as a divider of the GPT clock source 25config SYS_CLOCK_TICKS_PER_SEC 26 default 4096 if MCUX_GPT_TIMER 27 28DT_SYSCLK_PATH := $(dt_nodelabel_path,sysclk) 29 30config SYS_CLOCK_HW_CYCLES_PER_SEC 31 default $(dt_node_int_prop_int,$(DT_SYSCLK_PATH),clock-frequency) if SOC_SERIES_IMXRT10XX && CORTEX_M_SYSTICK 32 default 32768 if MCUX_GPT_TIMER 33 34# Disable systick if using MCUX_GPT_TIMER, as they will conflict 35config CORTEX_M_SYSTICK 36 default n if MCUX_GPT_TIMER 37 38config PM_MCUX_GPC 39 default y if HAS_MCUX_GPC 40 depends on SOC_SERIES_IMXRT11XX && PM 41 42# Don't allow SOC to sleep after tests complete when PM is enabled 43config ZTEST_NO_YIELD 44 default y if (ZTEST && PM) 45 46if SOC_SERIES_IMXRT10XX && PM 47 48config CODE_DATA_RELOCATION 49 default y 50 51config PM_MCUX_GPC 52 default y if HAS_MCUX_GPC 53 54config PM_MCUX_DCDC 55 default y if HAS_MCUX_DCDC 56 57config PM_MCUX_PMU 58 default y if HAS_MCUX_PMU 59 60endif # SOC_SERIES_IMXRT10XX && PM 61 62if ETH_NXP_ENET || ETH_NXP_IMX_NETC 63 64config SYSTEM_WORKQUEUE_STACK_SIZE 65 default 1560 66 67endif # ETH_NXP_ENET 68 69config MEMC 70 default y if !SOC_SERIES_IMXRT118X # RT118X lacks FLEXRAM 71 72DT_CHOSEN_Z_DTCM := zephyr,dtcm 73 74choice SEGGER_RTT_SECTION 75 default SEGGER_RTT_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) 76 depends on USE_SEGGER_RTT 77endchoice 78 79choice SEGGER_SYSVIEW_SECTION 80 default SEGGER_SYSVIEW_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) 81 depends on SEGGER_SYSTEMVIEW 82endchoice 83 84if MBEDTLS 85# 86# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than 87# what the ztest_thread_stack defaults to. 88# 89config TEST_EXTRA_STACK_SIZE 90 default 1024 91endif # MBEDTLS 92 93if CPU_CORTEX_M7 94# defaults specific for the M7 core 95 96# Enable cache management features when using M7 core, since these parts 97# have L1 instruction and data caches that should be enabled at boot 98config CACHE_MANAGEMENT 99 default y 100 101config FLASH_MCUX_FLEXSPI_XIP_MEM 102 default "ITCM" 103 104endif # CPU_CORTEX_M7 105 106endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X 107 108endif # SOC_FAMILY_NXP_IMXRT 109
