1# Copyright 2017-2024 NXP 2# SPDX-License-Identifier: Apache-2.0 3 4if SOC_FAMILY_NXP_IMXRT 5 6# Source series Kconfig files first, so SOCs 7# can override the defaults given here 8rsource "*/Kconfig.defconfig" 9 10if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X 11 12config ROM_START_OFFSET 13 default 0x400 if BOOTLOADER_MCUBOOT 14 default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR 15 16config LOG_BACKEND_SWO_FREQ_HZ 17 default 7500000 18 depends on LOG_BACKEND_SWO 19 20# set the tick per sec as a divider of the GPT clock source 21config SYS_CLOCK_TICKS_PER_SEC 22 default 4096 if MCUX_GPT_TIMER 23 24DT_SYSCLK_PATH := $(dt_nodelabel_path,sysclk) 25 26config SYS_CLOCK_HW_CYCLES_PER_SEC 27 default $(dt_node_int_prop_int,$(DT_SYSCLK_PATH),clock-frequency) if SOC_SERIES_IMXRT10XX && CORTEX_M_SYSTICK 28 default 32768 if MCUX_GPT_TIMER 29 30# Disable systick if using MCUX_GPT_TIMER, as they will conflict 31config CORTEX_M_SYSTICK 32 default n if MCUX_GPT_TIMER 33 34config PM_MCUX_GPC 35 default y if HAS_MCUX_GPC 36 depends on SOC_SERIES_IMXRT11XX && PM 37 38# Don't allow SOC to sleep after tests complete when PM is enabled 39config ZTEST_NO_YIELD 40 default y if (ZTEST && PM) 41 42if SOC_SERIES_IMXRT10XX && PM 43 44config CODE_DATA_RELOCATION 45 default y 46 47config PM_MCUX_GPC 48 default y if HAS_MCUX_GPC 49 50config PM_MCUX_DCDC 51 default y if HAS_MCUX_DCDC 52 53config PM_MCUX_PMU 54 default y if HAS_MCUX_PMU 55 56endif # SOC_SERIES_IMXRT10XX && PM 57 58if ETH_NXP_ENET || ETH_NXP_IMX_NETC 59 60config SYSTEM_WORKQUEUE_STACK_SIZE 61 default 1560 62 63endif # ETH_NXP_ENET 64 65config MEMC 66 default y if !SOC_SERIES_IMXRT118X # RT118X lacks FLEXRAM 67 68DT_CHOSEN_Z_DTCM := zephyr,dtcm 69 70choice SEGGER_RTT_SECTION 71 default SEGGER_RTT_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) 72 depends on USE_SEGGER_RTT 73endchoice 74 75choice SEGGER_SYSVIEW_SECTION 76 default SEGGER_SYSVIEW_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) 77 depends on SEGGER_SYSTEMVIEW 78endchoice 79 80if MBEDTLS 81# 82# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than 83# what the ztest_thread_stack defaults to. 84# 85config TEST_EXTRA_STACK_SIZE 86 default 1024 87endif # MBEDTLS 88 89if CPU_CORTEX_M7 90# defaults specific for the M7 core 91 92# Enable cache management features when using M7 core, since these parts 93# have L1 instruction and data caches that should be enabled at boot 94config CACHE_MANAGEMENT 95 default y 96 97config FLASH_MCUX_FLEXSPI_XIP_MEM 98 default "ITCM" 99 100endif # CPU_CORTEX_M7 101 102endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X 103 104endif # SOC_FAMILY_NXP_IMXRT 105
