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Searched refs:PLL (Results 1 – 25 of 207) sorted by relevance

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/Zephyr-latest/drivers/clock_control/
DKconfig.nrf_auxpll5 bool "nRF Auxiliary PLL driver"
9 Driver for nRF Auxiliary PLL.
DKconfig.lpc11u6x28 prompt "LPC11U6X PLL Clock source"
33 Use the internal oscillator as the clock source for the PLL
38 Use the system oscillator as the clock source for the PLL
DKconfig.beetle19 bool "PLL on Beetle"
22 Enable PLL on Beetle.
DKconfig.si326 bool "SI32 PLL clock control"
/Zephyr-latest/soc/atmel/sam/common/
DKconfig24 The main clock is being used to drive the PLL, and thus driving the
35 menu "PLL A"
38 int "PLL MULA"
44 This is the multiplier (MULA) used by the PLL.
49 With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times
53 int "PLL DIVA"
57 This is the divider (DIVA) used by the PLL.
63 With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times
76 endmenu # PLL A
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt1160.dtsi7 /* Configure ARM PLL to 600MHz */
Dnxp_rt1170.dtsi7 /* Configure ARM PLL to 996MHz */
/Zephyr-latest/soc/nxp/imxrt/imxrt6xx/
DKconfig41 bool "Initialize SYS PLL"
44 bool "Initialize Audio PLL"
/Zephyr-latest/boards/google/dragonclaw/
Dgoogle_dragonclaw.dts38 div-p = <4>; /* 96MHz PLL general clock output */
39 div-q = <8>; /* 48MHz PLL output for USB, SDIO, RNG */
46 clocks = <&pll>; /* Select PLL as SYSCLK source (96MHz) */
/Zephyr-latest/soc/intel/apollo_lake/doc/
Dsupported_features.txt19 configuration. The UARTs are fed a master clock which is fed into a PLL which
20 in turn outputs the baud master clock. The PLL is controlled by a per-UART
/Zephyr-latest/soc/nxp/imxrt/
DKconfig142 bool "Initialize ARM PLL"
145 bool "Initialize Video PLL"
150 If y, the Ethernet PLL is initialized. Always enabled on e.g.
155 bool "Initialize System PLL"
/Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/boards/
Dstm32h747i_disco_stm32h747xx_m7.overlay34 /* DSI HOST dedicated PLL
/Zephyr-latest/soc/atmel/sam/sam4l/
Dsoc.c213 SCIF_UNLOCK_ADDR((uint32_t)&SCIF->PLL[0] - in clock_init()
215 SCIF->PLL[0] = pll_config | SCIF_PLL_PLLEN; in clock_init()
/Zephyr-latest/boards/vcc-gnd/yd_stm32h750vb/doc/
Dindex.rst59 as well as by the main PLL clock. By default, the System clock
60 is driven by the PLL clock at 480MHz. PLL clock is feed by a 25MHz high speed external clock.
/Zephyr-latest/boards/st/nucleo_f303k8/doc/
Dindex.rst121 external oscillator, as well as by the main PLL clock. By default the
122 System Clock is driven by the PLL clock at 72 MHz. The input to the
123 PLL is an 8 MHz internal clock supply.
/Zephyr-latest/soc/nxp/kinetis/
DKconfig55 hex "PLL external reference divider"
59 Selects the amount to divide down the external reference clock for the PLL.
67 Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
/Zephyr-latest/soc/st/stm32/stm32u5x/
DKconfig30 The PLL, MSIS, MSIK, HSI16, and HSE oscillators are disabled.
/Zephyr-latest/boards/st/nucleo_f302r8/doc/
Dindex.rst129 external oscillator, as well as by the main PLL clock. By default the
130 System Clock is driven by the PLL clock at 72 MHz. The input to the
131 PLL is an 8 MHz external clock supplied by the processor of the
/Zephyr-latest/boards/st/nucleo_f303re/doc/
Dindex.rst124 external oscillator, as well as by the main PLL clock. By default the
125 System Clock is driven by the PLL clock at 72 MHz. The input to the
126 PLL is an 8 MHz external clock supplied by the processor of the
/Zephyr-latest/boards/st/stm32l4r9i_disco/doc/
Dindex.rst73 as well as by the main PLL clock. By default, the System clock is driven by
74 the PLL clock at 120MHz. PLL clock is driven by a 4MHz medium speed internal clock.
/Zephyr-latest/soc/ite/ec/it8xxx2/
DKconfig109 Change frequency of PLL, CPU, and flash to 48MHz during initialization.
112 (PLL and CPU run at 48MHz, flash frequency is 16MHz)
164 calibrating the frequency shift of the PLL. Enabling this
169 prompt "Clock source for PLL reference clock"
/Zephyr-latest/boards/st/nucleo_g431kb/doc/
Dindex.rst82 as well as main PLL clock. By default the external oscillator is not connected to the board. Theref…
83 High Speed oscillator is supported. By default System clock is driven by PLL clock at 170 MHz,
84 the PLL is driven by the 16 MHz high speed internal oscillator.
/Zephyr-latest/boards/st/stm32h735g_disco/doc/
Dindex.rst96 as well as by the main PLL clock. By default, the System clock
97 is driven by the PLL clock at 550MHz. PLL clock is feed by a 25MHz high speed external clock.
/Zephyr-latest/boards/st/stm32h750b_dk/doc/
Dindex.rst86 as well as by the main PLL clock. By default, the System clock
87 is driven by the PLL clock at 480MHz. PLL clock is feed by a 25MHz high speed external clock.
/Zephyr-latest/boards/makerbase/mks_canable_v20/
Dmks_canable_v20.dts39 /* Internal 16 MHz clock used to drive PLL */

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