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Searched refs:HWREGBITW (Results 1 – 25 of 36) sorted by relevance

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/hal_ti-latest/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/
Daon_rtc.h175 HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 1; in AONRTCEnable()
196 HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 0; in AONRTCDisable()
212 HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_RESET_BITN) = 1; in AONRTCReset()
228 return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN)); in AONRTCActive()
253 uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN); in AONRTCChannelActive()
258 uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN); in AONRTCChannelActive()
263 uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN); in AONRTCChannelActive()
418 uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH0_BITN); in AONRTCEventGet()
423 uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH1_BITN); in AONRTCEventGet()
428 uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH2_BITN); in AONRTCEventGet()
[all …]
Dwatchdog.h137 HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTEN_BITN) = 1; in WatchdogEnable()
158 HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 1; in WatchdogResetEnable()
179 HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 0; in WatchdogResetDisable()
459 …HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTTYPE_BITN) = (ui32Type == WATCHDOG_INT_TYPE_INT)? 0 : 1; in WatchdogIntTypeSet()
480 HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 1; in WatchdogStallEnable()
498 HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 0; in WatchdogStallDisable()
Dsetup.c132 HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; in SetupTrimDevice()
150 if( ! ( HWREGBITW( AON_IOC_BASE + AON_IOC_O_IOCLATCH, AON_IOC_IOCLATCH_EN_BITN ))) in SetupTrimDevice()
163 …else if( ! ( HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL, AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS… in SetupTrimDevice()
222 while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { in SetupTrimDevice()
341 HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1; in TrimAfterColdResetWakeupFromShutDown()
Dsys_ctrl.h466 HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_SYSRESET_BITN ) = 1; in SysCtrlSystemReset()
494 HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 1; in SysCtrlClockLossResetEnable()
514 HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 0; in SysCtrlClockLossResetDisable()
Daux_adc.c99 HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) in AUXADCDisable()
100 HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) in AUXADCDisable()
233 HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) in AUXADCFlushFifo()
234 HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) in AUXADCFlushFifo()
Dtrng.h152 HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 1; in TRNGEnable()
166 HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 0; in TRNGDisable()
Di2c.h294 HWREGBITW(ui32Base + I2C_O_MCR, I2C_MCR_MFE_BITN) = 1; in I2CMasterEnable()
321 HWREGBITW(ui32Base + I2C_O_MCR, I2C_MCR_MFE_BITN) = 0; in I2CMasterDisable()
583 HWREGBITW(ui32Base + I2C_O_MCR, I2C_MCR_SFE_BITN) = 1; in I2CSlaveEnable()
664 HWREGBITW(ui32Base + I2C_O_MCR, I2C_MCR_SFE_BITN) = 0; in I2CSlaveDisable()
Dcpu.h395 HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1; in CPU_WriteBufferDisable()
413 HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0; in CPU_WriteBufferEnable()
Dflash.c400 HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; in FlashSectorErase()
427 HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; in FlashProgram()
680 HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; in MemBusWrkAroundHapiProgramFlash()
704 HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; in MemBusWrkAroundHapiEraseSector()
Dsetup_rom.c201 … HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0; in SetupAfterColdResetWakeupFromShutDownCfg1()
206 HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_EN_BITN ) = in SetupAfterColdResetWakeupFromShutDownCfg1()
211 HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN ) = in SetupAfterColdResetWakeupFromShutDownCfg1()
895 while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { in SetupSetCacheModeAccordingToCcfgSetting()
939 …while( ! ( HWREGBITW( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL, AUX_SYSIF_RTCSUBSECINCCTL_UPD_… in SetupSetAonRtcSubSecInc()
Dsha2.c79 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; in SHA2StartDMAOperation()
89 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; in SHA2StartDMAOperation()
/hal_ti-latest/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/
Daon_rtc.h176 HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 1; in AONRTCEnable()
197 HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 0; in AONRTCDisable()
213 HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_RESET_BITN) = 1; in AONRTCReset()
229 return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN)); in AONRTCActive()
254 uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN); in AONRTCChannelActive()
259 uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN); in AONRTCChannelActive()
264 uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN); in AONRTCChannelActive()
419 uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH0_BITN); in AONRTCEventGet()
424 uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH1_BITN); in AONRTCEventGet()
429 uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH2_BITN); in AONRTCEventGet()
[all …]
Dwatchdog.h139 HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTEN_BITN) = 1; in WatchdogEnable()
160 HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 1; in WatchdogResetEnable()
181 HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 0; in WatchdogResetDisable()
461 …HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTTYPE_BITN) = (ui32Type == WATCHDOG_INT_TYPE_INT)? 0 : 1; in WatchdogIntTypeSet()
482 HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 1; in WatchdogStallEnable()
500 HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 0; in WatchdogStallDisable()
Dsetup.c130 HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; in SetupTrimDevice()
148 if( ! ( HWREGBITW( AON_IOC_BASE + AON_IOC_O_IOCLATCH, AON_IOC_IOCLATCH_EN_BITN ))) in SetupTrimDevice()
161 …else if( ! ( HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL, AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS… in SetupTrimDevice()
212 while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { in SetupTrimDevice()
329 HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1; in TrimAfterColdResetWakeupFromShutDown()
Dcrypto.c110 HWREGBITW(CRYPTO_BASE + CRYPTO_O_ALGSEL, CRYPTO_ALGSEL_KEY_STORE_BITN) = 1; in CRYPTOAesLoadKey()
127 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; in CRYPTOAesLoadKey()
243 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; in CRYPTOAesCbc()
252 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; in CRYPTOAesCbc()
337 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; in CRYPTOAesEcb()
346 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; in CRYPTOAesEcb()
492 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; in CRYPTOCcmAuthEncrypt()
540 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; in CRYPTOCcmAuthEncrypt()
547 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; in CRYPTOCcmAuthEncrypt()
740 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; in CRYPTOCcmInvAuthDecrypt()
[all …]
Dsys_ctrl.h467 HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_SYSRESET_BITN ) = 1; in SysCtrlSystemReset()
495 HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 1; in SysCtrlClockLossResetEnable()
515 HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 0; in SysCtrlClockLossResetDisable()
Daux_adc.c101 HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) in AUXADCDisable()
102 HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) in AUXADCDisable()
235 HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) in AUXADCFlushFifo()
236 HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) in AUXADCFlushFifo()
Dtrng.h154 HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 1; in TRNGEnable()
168 HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 0; in TRNGDisable()
Di2c.h296 HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 1; in I2CMasterEnable()
323 HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 0; in I2CMasterDisable()
585 HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 1; in I2CSlaveEnable()
666 HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 0; in I2CSlaveDisable()
Dcpu.h398 HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1; in CPU_WriteBufferDisable()
416 HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0; in CPU_WriteBufferEnable()
Dflash.c345 HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; in FlashSectorErase()
372 HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; in FlashProgram()
637 HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; in MemBusWrkAroundHapiProgramFlash()
661 HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; in MemBusWrkAroundHapiEraseSector()
Dsetup_rom.c202 … HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0; in SetupAfterColdResetWakeupFromShutDownCfg1()
207 HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_EN_BITN ) = in SetupAfterColdResetWakeupFromShutDownCfg1()
212 HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN ) = in SetupAfterColdResetWakeupFromShutDownCfg1()
897 while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { in SetupSetCacheModeAccordingToCcfgSetting()
941 …while( ! ( HWREGBITW( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL, AUX_SYSIF_RTCSUBSECINCCTL_UPD_… in SetupSetAonRtcSubSecInc()
/hal_ti-latest/simplelink/source/ti/devices/cc32xx/inc/
Dhw_types.h63 #define HWREGBITW(x, b) \ macro
/hal_ti-latest/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/inc/
Dhw_types.h106 #define HWREGBITW(x, b) \ macro
/hal_ti-latest/simplelink/source/ti/devices/cc13x2_cc26x2/inc/
Dhw_types.h108 #define HWREGBITW(x, b) \ macro

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