1 /******************************************************************************
2 * Filename: setup_rom.c
3 *
4 * Description: Setup file for CC13xx/CC26xx devices.
5 *
6 * Copyright (c) 2015 - 2022, Texas Instruments Incorporated
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are met:
11 *
12 * 1) Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * 2) Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
20 * be used to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************/
36
37 // Hardware headers
38 #include "../inc/hw_types.h"
39 #include "../inc/hw_memmap.h"
40 #include "../inc/hw_adi.h"
41 #include "../inc/hw_adi_2_refsys.h"
42 #include "../inc/hw_adi_3_refsys.h"
43 #include "../inc/hw_adi_4_aux.h"
44 #include "../inc/hw_aon_batmon.h"
45 #include "../inc/hw_aux_sysif.h"
46 #include "../inc/hw_ccfg.h"
47 #include "../inc/hw_ddi_0_osc.h"
48 #include "../inc/hw_fcfg1.h"
49 // Driverlib headers
50 #include "ddi.h"
51 #include "ioc.h"
52 #include "osc.h"
53 #include "sys_ctrl.h"
54 #include "setup_rom.h"
55
56 //*****************************************************************************
57 //
58 // Handle support for DriverLib in ROM:
59 // This section will undo prototype renaming made in the header file
60 //
61 //*****************************************************************************
62 #if !defined(DOXYGEN)
63 #undef SetupAfterColdResetWakeupFromShutDownCfg1
64 #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1
65 #undef SetupAfterColdResetWakeupFromShutDownCfg2
66 #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2
67 #undef SetupAfterColdResetWakeupFromShutDownCfg3
68 #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3
69 #undef SetupGetTrimForAdcShModeEn
70 #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn
71 #undef SetupGetTrimForAdcShVbufEn
72 #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn
73 #undef SetupGetTrimForAmpcompCtrl
74 #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl
75 #undef SetupGetTrimForAmpcompTh1
76 #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1
77 #undef SetupGetTrimForAmpcompTh2
78 #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2
79 #undef SetupGetTrimForAnabypassValue1
80 #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1
81 #undef SetupGetTrimForDblrLoopFilterResetVoltage
82 #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage
83 #undef SetupGetTrimForRadcExtCfg
84 #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg
85 #undef SetupGetTrimForRcOscLfIBiasTrim
86 #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim
87 #undef SetupGetTrimForRcOscLfRtuneCtuneTrim
88 #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim
89 #undef SetupGetTrimForXoscHfCtl
90 #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl
91 #undef SetupGetTrimForXoscHfFastStart
92 #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart
93 #undef SetupGetTrimForXoscHfIbiastherm
94 #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm
95 #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
96 #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
97 #undef SetupSetCacheModeAccordingToCcfgSetting
98 #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting
99 #undef SetupSetAonRtcSubSecInc
100 #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc
101 #undef SetupStepVddrTrimTo
102 #define SetupStepVddrTrimTo NOROM_SetupStepVddrTrimTo
103 #endif
104
105 //*****************************************************************************
106 //
107 // Function declarations
108 //
109 //*****************************************************************************
110
111
112 //*****************************************************************************
113 //
114 // SetupStepVddrTrimTo
115 //
116 //*****************************************************************************
117 void
SetupStepVddrTrimTo(uint32_t toCode)118 SetupStepVddrTrimTo( uint32_t toCode )
119 {
120 uint32_t pmctlResetctl_reg ;
121 int32_t targetTrim ;
122 int32_t currentTrim ;
123
124 targetTrim = SetupSignExtendVddrTrimValue( toCode & ( ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M >> ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ));
125 currentTrim = SetupSignExtendVddrTrimValue((
126 HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) &
127 ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >>
128 ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) ;
129
130 if ( targetTrim != currentTrim ) {
131 pmctlResetctl_reg = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M );
132 if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) {
133 HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ( pmctlResetctl_reg & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M );
134 HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for VDDR_LOSS_EN setting to propagate
135 }
136
137 while ( targetTrim != currentTrim ) {
138 HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
139
140 if ( targetTrim > currentTrim ) currentTrim++;
141 else currentTrim--;
142
143 HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) = (
144 ( HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & ~ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) |
145 ((((uint32_t)currentTrim) << ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) &
146 ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) );
147 }
148
149 HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
150
151 if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) {
152 HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
153 HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
154 HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = pmctlResetctl_reg;
155 HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // And finally wait for VDDR_LOSS_EN setting to propagate
156 }
157 }
158 }
159
160 //*****************************************************************************
161 //
162 // SetupAfterColdResetWakeupFromShutDownCfg1
163 //
164 //*****************************************************************************
165 void
SetupAfterColdResetWakeupFromShutDownCfg1(uint32_t ccfg_ModeConfReg)166 SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg )
167 {
168 // Check for CC1352 boost mode
169 // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode
170 if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) &&
171 (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) )
172 {
173 // Set VDDS_BOD trim - using masked write {MASK8:DATA8}
174 // - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1
175 // - Needs a positive transition on BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to
176 // latch new VDDS BOD. Set to 0 first to guarantee a positive transition.
177 HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
178 //
179 // VDDS_BOD_LEVEL = 1 means that boost mode is selected
180 // - Max out the VDDS_BOD trim (=VDDS_BOD_POS_31)
181 HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) =
182 ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) |
183 ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 ) ;
184 HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
185
186 SetupStepVddrTrimTo(( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) &
187 FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >>
188 FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ;
189 }
190
191 // 1.
192 // Do not allow DCDC to be enabled if in external regulator mode.
193 // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg).
194 //
195 // 2.
196 // Adjusted battery monitor low limit in internal regulator mode.
197 // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode.
198 if ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) {
199 ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M );
200 } else {
201 HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0;
202 }
203
204 // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE
205 // Note: Inverse polarity
206 HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_EN_BITN ) =
207 ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 );
208
209 // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE
210 // Note: Inverse polarity
211 HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN ) =
212 ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 );
213 }
214
215 //*****************************************************************************
216 //
217 // SetupAfterColdResetWakeupFromShutDownCfg2
218 //
219 //*****************************************************************************
220 void
SetupAfterColdResetWakeupFromShutDownCfg2(uint32_t ui32Fcfg1Revision,uint32_t ccfg_ModeConfReg)221 SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg )
222 {
223 uint32_t ui32Trim;
224
225 // Following sequence is required for using XOSCHF, if not included
226 // devices crashes when trying to switch to XOSCHF.
227 //
228 // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1
229 // register
230 ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg );
231 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim);
232
233 // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and
234 // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register.
235 ui32Trim = SetupGetTrimForRcOscLfRtuneCtuneTrim();
236 DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL,
237 (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M |
238 DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M),
239 DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S,
240 ui32Trim);
241
242 // Trim XOSCHF IBIAS THERM. Get and set trim value for the
243 // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other
244 // register bit fields are set to 0.
245 ui32Trim = SetupGetTrimForXoscHfIbiastherm();
246 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2,
247 ui32Trim<<DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S);
248
249 // Trim AMPCOMP settings required before switch to XOSCHF
250 ui32Trim = SetupGetTrimForAmpcompTh2();
251 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH2, ui32Trim);
252 ui32Trim = SetupGetTrimForAmpcompTh1();
253 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH1, ui32Trim);
254 #if ( CCFG_BASE == CCFG_BASE_DEFAULT )
255 ui32Trim = SetupGetTrimForAmpcompCtrl( ui32Fcfg1Revision );
256 #else
257 ui32Trim = NOROM_SetupGetTrimForAmpcompCtrl( ui32Fcfg1Revision );
258 #endif
259 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPCTL, ui32Trim);
260
261 // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN in accordance to FCFG1 setting
262 // This is bit[5] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register
263 // Using MASK4 write + 1 => writing to bits[7:4]
264 ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision );
265 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) =
266 ( 0x20 | ( ui32Trim << 1 ));
267
268 // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting
269 // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register
270 // Using MASK4 write + 1 => writing to bits[7:4]
271 ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision );
272 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) =
273 ( 0x10 | ( ui32Trim ));
274
275 // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields
276 // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting.
277 // Remaining register bit fields are set to their reset values of 0.
278 ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision);
279 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim);
280
281 // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting
282 // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL)
283 // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4))
284 // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and
285 // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000)
286 ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision );
287 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) =
288 ( 0x60 | ( ui32Trim << 1 ));
289
290 // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from
291 // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM
292 // This is DDI_0_OSC_O_ATESTCTL bit[7]
293 // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020))
294 // Using MASK4 write + 1 => writing to bits[7:4]
295 ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision );
296 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) =
297 ( 0x80 | ( ui32Trim << 3 ));
298
299 // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and
300 // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write
301 // This can be simplified since the registers are packed together in the same
302 // order both in FCFG1 and in the HW register.
303 // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18]
304 // Using MASK8 write + 4 => writing to bits[23:16]
305 ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision );
306 HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) =
307 ( 0xFC00 | ( ui32Trim << 2 ));
308
309 // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit
310 // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting.
311 // Remaining register bit fields are set to their reset values of 0.
312 ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision);
313 DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim);
314 }
315
316 //*****************************************************************************
317 //
318 // SetupAfterColdResetWakeupFromShutDownCfg3
319 //
320 //*****************************************************************************
321 void
SetupAfterColdResetWakeupFromShutDownCfg3(uint32_t ccfg_ModeConfReg)322 SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg )
323 {
324 uint32_t fcfg1OscConf;
325 uint32_t ui32Trim;
326 uint32_t currentHfClock;
327 uint32_t ccfgExtLfClk;
328
329 // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC
330 switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) {
331 case 2 :
332 // XOSC source is a 48 MHz crystal
333 // Do nothing (since this is the reset setting)
334 break;
335 case 1 :
336 // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC)
337
338 fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF );
339
340 if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) {
341 // This is a HPOSC chip, apply HPOSC settings
342 // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0)
343 HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN;
344
345 // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit)
346 // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits)
347 // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits)
348 // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit)
349 // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits)
350 // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits)
351 // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit)
352
353 HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) &
354 ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) |
355 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) |
356 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) );
357 HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) |
358 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) );
359 HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) &
360 ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) |
361 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) |
362 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) |
363 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) |
364 ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) );
365 break;
366 }
367 // Not a HPOSC chip - fall through to default
368 default :
369 // XOSC source is a 24 MHz crystal (default)
370 // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0)
371 HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M;
372 break;
373 }
374
375 // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO
376 // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used.
377 if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) {
378 HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS;
379 }
380
381 // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0.
382 // This is typically already 0 except on Lizard where it is set in ROM-boot
383 HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN;
384
385 // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1
386 ui32Trim = SetupGetTrimForXoscHfFastStart();
387 HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim );
388
389 // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION
390 switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) {
391 case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz)
392 OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF );
393 SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency
394 break;
395 case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT)
396 // Set SCLK_LF to use the same source as SCLK_HF
397 // Can be simplified a bit since possible return values for HF matches LF settings
398 currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF );
399 OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock );
400 while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) {
401 // Wait until switched
402 }
403 ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK );
404 SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S );
405 IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S,
406 IOC_PORT_AON_CLK32K,
407 IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis
408 // Set XOSC_LF in bypass mode to allow external 32 kHz clock
409 HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS;
410 // Fall through to set XOSC_LF as SCLK_LF source
411 case 2 : // XOSC_LF -> SLCK_LF (32768 Hz)
412 OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF );
413 break;
414 default : // (=3) RCOSC_LF
415 OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF );
416 break;
417 }
418
419 // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1
420 HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) =
421 ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >>
422 FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) <<
423 ADI_4_AUX_ADCREF1_VTRIM_S ) &
424 ADI_4_AUX_ADCREF1_VTRIM_M );
425
426 // Sync with AON
427 SysCtrlAonSync();
428 }
429
430 //*****************************************************************************
431 //
432 // SetupGetTrimForAnabypassValue1
433 //
434 //*****************************************************************************
435 uint32_t
SetupGetTrimForAnabypassValue1(uint32_t ccfg_ModeConfReg)436 SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg )
437 {
438 uint32_t ui32Fcfg1Value ;
439 uint32_t ui32XoscHfRow ;
440 uint32_t ui32XoscHfCol ;
441 uint32_t ui32TrimValue ;
442
443 // Use device specific trim values located in factory configuration
444 // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in
445 // the ANABYPASS_VALUE1 register. Value for the other bit fields
446 // are set to 0.
447
448 ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP);
449 ui32XoscHfRow = (( ui32Fcfg1Value &
450 FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >>
451 FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S );
452 ui32XoscHfCol = (( ui32Fcfg1Value &
453 FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >>
454 FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S );
455
456 if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) {
457 // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation
458 // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg
459 // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by
460 // a define and sign extension must therefore be hard coded.
461 // ( A small test program is created verifying the code lines below:
462 // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c)
463 int32_t i32CustomerDeltaAdjust =
464 (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S )))
465 >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W ));
466
467 while ( i32CustomerDeltaAdjust < 0 ) {
468 ui32XoscHfCol >>= 1; // COL 1 step down
469 if ( ui32XoscHfCol == 0 ) { // if COL below minimum
470 ui32XoscHfCol = 0xFFFF; // Set COL to maximum
471 ui32XoscHfRow >>= 1; // ROW 1 step down
472 if ( ui32XoscHfRow == 0 ) { // if ROW below minimum
473 ui32XoscHfRow = 1; // Set both ROW and COL
474 ui32XoscHfCol = 1; // to minimum
475 }
476 }
477 i32CustomerDeltaAdjust++;
478 }
479 while ( i32CustomerDeltaAdjust > 0 ) {
480 ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up
481 if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum
482 ui32XoscHfCol = 1; // Set COL to minimum
483 ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up
484 if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum
485 ui32XoscHfRow = 0xF; // Set both ROW and COL
486 ui32XoscHfCol = 0xFFFF; // to maximum
487 }
488 }
489 i32CustomerDeltaAdjust--;
490 }
491 }
492
493 ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) |
494 ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) );
495
496 return (ui32TrimValue);
497 }
498
499 //*****************************************************************************
500 //
501 // SetupGetTrimForRcOscLfRtuneCtuneTrim
502 //
503 //*****************************************************************************
504 uint32_t
SetupGetTrimForRcOscLfRtuneCtuneTrim(void)505 SetupGetTrimForRcOscLfRtuneCtuneTrim( void )
506 {
507 uint32_t ui32TrimValue;
508
509 // Use device specific trim values located in factory configuration
510 // area
511 ui32TrimValue =
512 ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) &
513 FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>>
514 FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<<
515 DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S;
516
517 ui32TrimValue |=
518 ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) &
519 FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>>
520 FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<<
521 DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S;
522
523 return(ui32TrimValue);
524 }
525
526 //*****************************************************************************
527 //
528 // SetupGetTrimForXoscHfIbiastherm
529 //
530 //*****************************************************************************
531 uint32_t
SetupGetTrimForXoscHfIbiastherm(void)532 SetupGetTrimForXoscHfIbiastherm( void )
533 {
534 uint32_t ui32TrimValue;
535
536 // Use device specific trim value located in factory configuration
537 // area
538 ui32TrimValue =
539 (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) &
540 FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>>
541 FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S;
542
543 return(ui32TrimValue);
544 }
545
546 //*****************************************************************************
547 //
548 // SetupGetTrimForAmpcompTh2
549 //
550 //*****************************************************************************
551 uint32_t
SetupGetTrimForAmpcompTh2(void)552 SetupGetTrimForAmpcompTh2( void )
553 {
554 uint32_t ui32TrimValue;
555 uint32_t ui32Fcfg1Value;
556
557 // Use device specific trim value located in factory configuration
558 // area. All defined register bit fields have corresponding trim
559 // value in the factory configuration area
560 ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2);
561 ui32TrimValue = ((ui32Fcfg1Value &
562 FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>>
563 FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<<
564 DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S;
565 ui32TrimValue |= (((ui32Fcfg1Value &
566 FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>>
567 FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<<
568 DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S);
569 ui32TrimValue |= (((ui32Fcfg1Value &
570 FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>>
571 FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<<
572 DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S);
573 ui32TrimValue |= (((ui32Fcfg1Value &
574 FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>>
575 FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<<
576 DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S);
577
578 return(ui32TrimValue);
579 }
580
581 //*****************************************************************************
582 //
583 // SetupGetTrimForAmpcompTh1
584 //
585 //*****************************************************************************
586 uint32_t
SetupGetTrimForAmpcompTh1(void)587 SetupGetTrimForAmpcompTh1( void )
588 {
589 uint32_t ui32TrimValue;
590 uint32_t ui32Fcfg1Value;
591
592 // Use device specific trim values located in factory configuration
593 // area. All defined register bit fields have a corresponding trim
594 // value in the factory configuration area
595 ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1);
596 ui32TrimValue = (((ui32Fcfg1Value &
597 FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>>
598 FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<<
599 DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S);
600 ui32TrimValue |= (((ui32Fcfg1Value &
601 FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>>
602 FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<<
603 DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S);
604 ui32TrimValue |= (((ui32Fcfg1Value &
605 FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>>
606 FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<<
607 DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S);
608 ui32TrimValue |= (((ui32Fcfg1Value &
609 FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>>
610 FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<<
611 DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S);
612
613 return(ui32TrimValue);
614 }
615
616 //*****************************************************************************
617 //
618 // SetupGetTrimForAmpcompCtrl
619 //
620 //*****************************************************************************
621 uint32_t
SetupGetTrimForAmpcompCtrl(uint32_t ui32Fcfg1Revision)622 SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision )
623 {
624 uint32_t ui32TrimValue ;
625 uint32_t ui32Fcfg1Value ;
626 uint32_t ibiasOffset ;
627 uint32_t ibiasInit ;
628 uint32_t modeConf1 ;
629 int32_t deltaAdjust ;
630
631 // Use device specific trim values located in factory configuration
632 // area. Register bit fields without trim values in the factory
633 // configuration area will be set to the value of 0.
634 ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 );
635
636 ibiasOffset = ( ui32Fcfg1Value &
637 FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >>
638 FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ;
639 ibiasInit = ( ui32Fcfg1Value &
640 FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >>
641 FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ;
642
643 if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) {
644 // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG
645 modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 );
646
647 // Both fields are signed 4-bit values. This is an assumption when doing the sign extension.
648 deltaAdjust =
649 (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S )))
650 >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W ));
651 deltaAdjust += (int32_t)ibiasOffset;
652 if ( deltaAdjust < 0 ) {
653 deltaAdjust = 0;
654 }
655 if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) {
656 deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S );
657 }
658 ibiasOffset = (uint32_t)deltaAdjust;
659
660 deltaAdjust =
661 (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S )))
662 >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W ));
663 deltaAdjust += (int32_t)ibiasInit;
664 if ( deltaAdjust < 0 ) {
665 deltaAdjust = 0;
666 }
667 if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) {
668 deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S );
669 }
670 ibiasInit = (uint32_t)deltaAdjust;
671 }
672 ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) |
673 ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ;
674
675 ui32TrimValue |= (((ui32Fcfg1Value &
676 FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>>
677 FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<<
678 DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S);
679 ui32TrimValue |= (((ui32Fcfg1Value &
680 FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>>
681 FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<<
682 DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S);
683 ui32TrimValue |= (((ui32Fcfg1Value &
684 FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>>
685 FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<<
686 DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S);
687
688 if ( ui32Fcfg1Revision >= 0x00000022 ) {
689 ui32TrimValue |= ((( ui32Fcfg1Value &
690 FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >>
691 FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) <<
692 DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S );
693 }
694
695 return(ui32TrimValue);
696 }
697
698 //*****************************************************************************
699 //
700 // SetupGetTrimForDblrLoopFilterResetVoltage
701 //
702 //*****************************************************************************
703 uint32_t
SetupGetTrimForDblrLoopFilterResetVoltage(uint32_t ui32Fcfg1Revision)704 SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision )
705 {
706 uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value
707
708 if ( ui32Fcfg1Revision >= 0x00000020 ) {
709 dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) &
710 FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >>
711 FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S;
712 }
713
714 return ( dblrLoopFilterResetVoltageValue );
715 }
716
717 //*****************************************************************************
718 //
719 // SetupGetTrimForAdcShModeEn
720 //
721 //*****************************************************************************
722 uint32_t
SetupGetTrimForAdcShModeEn(uint32_t ui32Fcfg1Revision)723 SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision )
724 {
725 uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting
726
727 if ( ui32Fcfg1Revision >= 0x00000022 ) {
728 getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
729 FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >>
730 FCFG1_OSC_CONF_ADC_SH_MODE_EN_S;
731 }
732
733 return ( getTrimForAdcShModeEnValue );
734 }
735
736 //*****************************************************************************
737 //
738 // SetupGetTrimForAdcShVbufEn
739 //
740 //*****************************************************************************
741 uint32_t
SetupGetTrimForAdcShVbufEn(uint32_t ui32Fcfg1Revision)742 SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision )
743 {
744 uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting
745
746 if ( ui32Fcfg1Revision >= 0x00000022 ) {
747 getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
748 FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >>
749 FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S;
750 }
751
752 return ( getTrimForAdcShVbufEnValue );
753 }
754
755 //*****************************************************************************
756 //
757 // SetupGetTrimForXoscHfCtl
758 //
759 //*****************************************************************************
760 uint32_t
SetupGetTrimForXoscHfCtl(uint32_t ui32Fcfg1Revision)761 SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision )
762 {
763 uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting
764 uint32_t fcfg1Data;
765
766 if ( ui32Fcfg1Revision >= 0x00000020 ) {
767 fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 );
768 getTrimForXoschfCtlValue =
769 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >>
770 FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) <<
771 DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S);
772
773 getTrimForXoschfCtlValue |=
774 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >>
775 FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) <<
776 DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S);
777
778 getTrimForXoschfCtlValue |=
779 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >>
780 FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) <<
781 DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S);
782 }
783
784 return ( getTrimForXoschfCtlValue );
785 }
786
787 //*****************************************************************************
788 //
789 // SetupGetTrimForXoscHfFastStart
790 //
791 //*****************************************************************************
792 uint32_t
SetupGetTrimForXoscHfFastStart(void)793 SetupGetTrimForXoscHfFastStart( void )
794 {
795 uint32_t ui32XoscHfFastStartValue ;
796
797 // Get value from FCFG1
798 ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
799 FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >>
800 FCFG1_OSC_CONF_XOSC_HF_FAST_START_S;
801
802 return ( ui32XoscHfFastStartValue );
803 }
804
805 //*****************************************************************************
806 //
807 // SetupGetTrimForRadcExtCfg
808 //
809 //*****************************************************************************
810 uint32_t
SetupGetTrimForRadcExtCfg(uint32_t ui32Fcfg1Revision)811 SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision )
812 {
813 uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting
814 uint32_t fcfg1Data;
815
816 if ( ui32Fcfg1Revision >= 0x00000020 ) {
817 fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 );
818 getTrimForRadcExtCfgValue =
819 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >>
820 FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) <<
821 DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S);
822
823 getTrimForRadcExtCfgValue |=
824 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >>
825 FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) <<
826 DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S);
827
828 getTrimForRadcExtCfgValue |=
829 ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >>
830 FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) <<
831 DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S);
832 }
833
834 return ( getTrimForRadcExtCfgValue );
835 }
836
837 //*****************************************************************************
838 //
839 // SetupGetTrimForRcOscLfIBiasTrim
840 //
841 //*****************************************************************************
842 uint32_t
SetupGetTrimForRcOscLfIBiasTrim(uint32_t ui32Fcfg1Revision)843 SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision )
844 {
845 uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value
846
847 if ( ui32Fcfg1Revision >= 0x00000022 ) {
848 trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
849 FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >>
850 FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ;
851 }
852
853 return ( trimForRcOscLfIBiasTrimValue );
854 }
855
856 //*****************************************************************************
857 //
858 // SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
859 //
860 //*****************************************************************************
861 uint32_t
SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio(uint32_t ui32Fcfg1Revision)862 SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision )
863 {
864 uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields
865
866 if ( ui32Fcfg1Revision >= 0x00000022 ) {
867 trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
868 ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M |
869 FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >>
870 FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ;
871 }
872
873 return ( trimForXoscLfRegulatorAndCmirrwrRatioValue );
874 }
875
876 //*****************************************************************************
877 //
878 // SetupSetCacheModeAccordingToCcfgSetting
879 //
880 //*****************************************************************************
881 void
SetupSetCacheModeAccordingToCcfgSetting(void)882 SetupSetCacheModeAccordingToCcfgSetting( void )
883 {
884 // - Make sure to enable aggressive VIMS clock gating for power optimization
885 // Only for PG2 devices.
886 // - Enable cache prefetch enable as default setting
887 // (Slightly higher power consumption, but higher CPU performance)
888 // - IF ( CCFG_..._DIS_GPRAM == 1 )
889 // then: Enable cache (set cache mode = 1), even if set by ROM boot code
890 // (This is done because it's not set by boot code when running inside
891 // a debugger supporting the Halt In Boot (HIB) functionality).
892 // else: Set MODE_GPRAM if not already set (see inline comments as well)
893 uint32_t vimsCtlMode0 ;
894
895 while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) {
896 // Do nothing - wait for an eventual ongoing mode change to complete.
897 // (There should typically be no wait time here, but need to be sure)
898 }
899
900 // Note that Mode=0 is equal to MODE_GPRAM
901 vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M );
902
903
904 if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) {
905 // Enable cache (and hence disable GPRAM)
906 HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE );
907 } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) {
908 // GPRAM is enabled in CCFG but not selected
909 // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM
910 HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF );
911 while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) {
912 // Do nothing - wait for an eventual mode change to complete (This goes fast).
913 }
914 HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0;
915 } else {
916 // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set
917 HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0;
918 }
919 }
920
921 //*****************************************************************************
922 //
923 // SetupSetAonRtcSubSecInc
924 //
925 //*****************************************************************************
926 void
SetupSetAonRtcSubSecInc(uint32_t subSecInc)927 SetupSetAonRtcSubSecInc( uint32_t subSecInc )
928 {
929 // Loading a new RTCSUBSECINC value is done in 5 steps:
930 // 1. Write bit[15:0] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC0
931 // 2. Write bit[23:16] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC1
932 // 3. Set AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ
933 // 4. Wait for AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK
934 // 5. Clear AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ
935 HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_SYSIF_RTCSUBSECINC0_INC15_0_M );
936 HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_SYSIF_RTCSUBSECINC1_INC23_16_M );
937
938 HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ;
939 while( ! ( HWREGBITW( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL, AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN )));
940 HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = 0;
941
942 }
943
