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Searched refs:tmpccmr2 (Results 1 – 25 of 49) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l0xx/drivers/src/
Dstm32l0xx_ll_tim.c595 uint32_t tmpccmr2; in OC3Config() local
615 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
618 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
621 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
633 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
654 uint32_t tmpccmr2; in OC4Config() local
674 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
677 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
680 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
692 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_tim.c618 uint32_t tmpccmr2; in OC3Config() local
638 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
641 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
644 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
656 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
677 uint32_t tmpccmr2; in OC4Config() local
697 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
700 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
703 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
715 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_hal_lptim.c4071 uint32_t tmpccmr2; in LPTIM_OC3_SetConfig() local
4073 tmpccmr2 = hlptim->Instance->CCMR2; in LPTIM_OC3_SetConfig()
4074 tmpccmr2 &= ~(LPTIM_CCMR2_CC3P_Msk | LPTIM_CCMR2_CC3SEL_Msk); in LPTIM_OC3_SetConfig()
4076 tmpccmr2 |= sConfig->OCPolarity << LPTIM_CCMR2_CC3P_Pos; in LPTIM_OC3_SetConfig()
4097 hlptim->Instance->CCMR2 = tmpccmr2; in LPTIM_OC3_SetConfig()
4111 uint32_t tmpccmr2; in LPTIM_OC4_SetConfig() local
4113 tmpccmr2 = hlptim->Instance->CCMR2; in LPTIM_OC4_SetConfig()
4114 tmpccmr2 &= ~(LPTIM_CCMR2_CC4P_Msk | LPTIM_CCMR2_CC4SEL_Msk); in LPTIM_OC4_SetConfig()
4116 tmpccmr2 |= sConfig->OCPolarity << LPTIM_CCMR2_CC4P_Pos; in LPTIM_OC4_SetConfig()
4137 hlptim->Instance->CCMR2 = tmpccmr2; in LPTIM_OC4_SetConfig()
[all …]
Dstm32u0xx_ll_tim.c934 uint32_t tmpccmr2; in OC3Config() local
954 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
957 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
960 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
992 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1013 uint32_t tmpccmr2; in OC4Config() local
1033 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1036 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1039 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1059 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_tim.c900 uint32_t tmpccmr2; in OC3Config() local
920 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
923 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
926 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
958 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
979 uint32_t tmpccmr2; in OC4Config() local
999 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1002 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1005 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1025 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_tim.c900 uint32_t tmpccmr2; in OC3Config() local
920 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
923 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
926 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
958 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
979 uint32_t tmpccmr2; in OC4Config() local
999 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1002 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1005 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1025 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/src/
Dstm32f0xx_ll_tim.c879 uint32_t tmpccmr2; in OC3Config() local
899 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
902 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
905 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
937 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
958 uint32_t tmpccmr2; in OC4Config() local
978 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
981 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
984 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1004 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_tim.c918 uint32_t tmpccmr2; in OC3Config() local
938 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
941 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
944 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
976 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
997 uint32_t tmpccmr2; in OC4Config() local
1017 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1020 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1023 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1043 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/src/
Dstm32wb0x_ll_tim.c839 uint32_t tmpccmr2; in OC3Config() local
859 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
862 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
865 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
899 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
920 uint32_t tmpccmr2; in OC4Config() local
940 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
943 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
946 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
968 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_tim.c975 uint32_t tmpccmr2; in OC3Config() local
995 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
998 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
1001 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1033 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1054 uint32_t tmpccmr2; in OC4Config() local
1074 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1077 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1080 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1100 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_ll_tim.c914 uint32_t tmpccmr2; in OC3Config() local
936 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
939 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
942 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
972 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
993 uint32_t tmpccmr2; in OC4Config() local
1015 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1018 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1021 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1042 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_tim.c930 uint32_t tmpccmr2; in OC3Config() local
950 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
953 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
956 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
988 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1009 uint32_t tmpccmr2; in OC4Config() local
1029 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1032 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1035 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1067 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_ll_tim.c925 uint32_t tmpccmr2; in OC3Config() local
945 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
948 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
951 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
983 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1004 uint32_t tmpccmr2; in OC4Config() local
1024 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1027 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1030 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1050 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_ll_tim.c917 uint32_t tmpccmr2; in OC3Config() local
937 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
940 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
943 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
975 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
996 uint32_t tmpccmr2; in OC4Config() local
1016 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1019 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1022 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1042 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_tim.c948 uint32_t tmpccmr2; in OC3Config() local
968 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
971 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
974 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1006 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1027 uint32_t tmpccmr2; in OC4Config() local
1047 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1050 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1053 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1073 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_tim.c948 uint32_t tmpccmr2; in OC3Config() local
968 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
971 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
974 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1006 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1027 uint32_t tmpccmr2; in OC4Config() local
1047 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1050 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1053 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1073 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_ll_tim.c957 uint32_t tmpccmr2; in OC3Config() local
977 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
980 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
983 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1015 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1036 uint32_t tmpccmr2; in OC4Config() local
1056 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1059 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1062 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1082 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_tim.c971 uint32_t tmpccmr2; in OC3Config() local
991 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
994 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
997 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1029 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1050 uint32_t tmpccmr2; in OC4Config() local
1070 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1073 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1076 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1108 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_tim.c1039 uint32_t tmpccmr2; in OC3Config() local
1059 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
1062 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
1065 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1100 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1121 uint32_t tmpccmr2; in OC4Config() local
1141 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1144 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1147 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1170 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_tim.c967 uint32_t tmpccmr2; in OC3Config() local
987 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
990 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
993 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1025 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1046 uint32_t tmpccmr2; in OC4Config() local
1066 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1069 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1072 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1104 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_tim.c984 uint32_t tmpccmr2; in OC3Config() local
1006 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
1009 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
1012 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1042 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1063 uint32_t tmpccmr2; in OC4Config() local
1085 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1088 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1091 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1112 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_tim.c1008 uint32_t tmpccmr2; in OC3Config() local
1028 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
1031 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
1034 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1066 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1087 uint32_t tmpccmr2; in OC4Config() local
1107 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1110 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1113 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1145 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_tim.c1005 uint32_t tmpccmr2; in OC3Config() local
1025 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
1028 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
1031 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1063 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1084 uint32_t tmpccmr2; in OC4Config() local
1104 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1107 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1110 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1130 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_tim.c965 uint32_t tmpccmr2; in OC3Config() local
985 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
988 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
991 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1023 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1044 uint32_t tmpccmr2; in OC4Config() local
1064 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1067 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1070 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1102 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_tim.c1002 uint32_t tmpccmr2; in OC3Config() local
1022 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
1025 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
1028 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1060 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1081 uint32_t tmpccmr2; in OC4Config() local
1101 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1104 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1107 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1139 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()

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