1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32l0xx_ll_tim.h"
22 #include "stm32l0xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32L0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM2) || defined (TIM3) || defined (TIM21) || defined (TIM22) || defined (TIM6) || defined (TIM7)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
65
66 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
67 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
68
69 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
70 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
71
72 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
73 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
74 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
75
76 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
77 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
78 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
79 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
80
81 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
82 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
83 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
84 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
85 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
86 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
87 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
88 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
89 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
90 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
97
98 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
99 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
100 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
101
102 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
103 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
104 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
105
106 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
107 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
108 /**
109 * @}
110 */
111
112
113 /* Private function prototypes -----------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
115 * @{
116 */
117 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
118 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
119 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
120 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
121 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
122 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
123 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
124 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
125 /**
126 * @}
127 */
128
129 /* Exported functions --------------------------------------------------------*/
130 /** @addtogroup TIM_LL_Exported_Functions
131 * @{
132 */
133
134 /** @addtogroup TIM_LL_EF_Init
135 * @{
136 */
137
138 /**
139 * @brief Set TIMx registers to their reset values.
140 * @param TIMx Timer instance
141 * @retval An ErrorStatus enumeration value:
142 * - SUCCESS: TIMx registers are de-initialized
143 * - ERROR: invalid TIMx instance
144 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)145 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
146 {
147 ErrorStatus result = SUCCESS;
148
149 /* Check the parameters */
150 assert_param(IS_TIM_INSTANCE(TIMx));
151
152 if (TIMx == TIM2)
153 {
154 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
155 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
156 }
157 #if defined(TIM3)
158 else if (TIMx == TIM3)
159 {
160 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
161 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
162 }
163 #endif /* TIM3 */
164 #if defined(TIM6)
165 else if (TIMx == TIM6)
166 {
167 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
168 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
169 }
170 #endif /* TIM6 */
171 #if defined(TIM7)
172 else if (TIMx == TIM7)
173 {
174 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
175 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
176 }
177 #endif /* TIM7 */
178 else if (TIMx == TIM21)
179 {
180 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM21);
181 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM21);
182 }
183 #if defined(TIM22)
184 else if (TIMx == TIM22)
185 {
186 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM22);
187 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM22);
188 }
189 #endif /* TIM22 */
190 else
191 {
192 result = ERROR;
193 }
194
195 return result;
196 }
197
198 /**
199 * @brief Set the fields of the time base unit configuration data structure
200 * to their default values.
201 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
202 * @retval None
203 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)204 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
205 {
206 /* Set the default configuration */
207 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
208 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
209 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
210 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
211 }
212
213 /**
214 * @brief Configure the TIMx time base unit.
215 * @param TIMx Timer Instance
216 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
217 * (TIMx time base unit configuration data structure)
218 * @retval An ErrorStatus enumeration value:
219 * - SUCCESS: TIMx registers are de-initialized
220 * - ERROR: not applicable
221 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)222 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
223 {
224 uint32_t tmpcr1;
225
226 /* Check the parameters */
227 assert_param(IS_TIM_INSTANCE(TIMx));
228 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
229 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
230
231 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
232
233 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
234 {
235 /* Select the Counter Mode */
236 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
237 }
238
239 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
240 {
241 /* Set the clock division */
242 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
243 }
244
245 /* Write to TIMx CR1 */
246 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
247
248 /* Set the Autoreload value */
249 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
250
251 /* Set the Prescaler value */
252 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
253 /* Generate an update event to reload the Prescaler
254 and the repetition counter value (if applicable) immediately */
255 LL_TIM_GenerateEvent_UPDATE(TIMx);
256
257 return SUCCESS;
258 }
259
260 /**
261 * @brief Set the fields of the TIMx output channel configuration data
262 * structure to their default values.
263 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
264 * (the output channel configuration data structure)
265 * @retval None
266 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)267 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
268 {
269 /* Set the default configuration */
270 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
271 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
272 TIM_OC_InitStruct->CompareValue = 0x00000000U;
273 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
274 }
275
276 /**
277 * @brief Configure the TIMx output channel.
278 * @param TIMx Timer Instance
279 * @param Channel This parameter can be one of the following values:
280 * @arg @ref LL_TIM_CHANNEL_CH1
281 * @arg @ref LL_TIM_CHANNEL_CH2
282 * @arg @ref LL_TIM_CHANNEL_CH3
283 * @arg @ref LL_TIM_CHANNEL_CH4
284 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
285 * data structure)
286 * @retval An ErrorStatus enumeration value:
287 * - SUCCESS: TIMx output channel is initialized
288 * - ERROR: TIMx output channel is not initialized
289 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)290 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
291 {
292 ErrorStatus result = ERROR;
293
294 switch (Channel)
295 {
296 case LL_TIM_CHANNEL_CH1:
297 result = OC1Config(TIMx, TIM_OC_InitStruct);
298 break;
299 case LL_TIM_CHANNEL_CH2:
300 result = OC2Config(TIMx, TIM_OC_InitStruct);
301 break;
302 case LL_TIM_CHANNEL_CH3:
303 result = OC3Config(TIMx, TIM_OC_InitStruct);
304 break;
305 case LL_TIM_CHANNEL_CH4:
306 result = OC4Config(TIMx, TIM_OC_InitStruct);
307 break;
308 default:
309 break;
310 }
311
312 return result;
313 }
314
315 /**
316 * @brief Set the fields of the TIMx input channel configuration data
317 * structure to their default values.
318 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
319 * data structure)
320 * @retval None
321 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)322 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
323 {
324 /* Set the default configuration */
325 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
326 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
327 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
328 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
329 }
330
331 /**
332 * @brief Configure the TIMx input channel.
333 * @param TIMx Timer Instance
334 * @param Channel This parameter can be one of the following values:
335 * @arg @ref LL_TIM_CHANNEL_CH1
336 * @arg @ref LL_TIM_CHANNEL_CH2
337 * @arg @ref LL_TIM_CHANNEL_CH3
338 * @arg @ref LL_TIM_CHANNEL_CH4
339 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
340 * structure)
341 * @retval An ErrorStatus enumeration value:
342 * - SUCCESS: TIMx output channel is initialized
343 * - ERROR: TIMx output channel is not initialized
344 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)345 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
346 {
347 ErrorStatus result = ERROR;
348
349 switch (Channel)
350 {
351 case LL_TIM_CHANNEL_CH1:
352 result = IC1Config(TIMx, TIM_IC_InitStruct);
353 break;
354 case LL_TIM_CHANNEL_CH2:
355 result = IC2Config(TIMx, TIM_IC_InitStruct);
356 break;
357 case LL_TIM_CHANNEL_CH3:
358 result = IC3Config(TIMx, TIM_IC_InitStruct);
359 break;
360 case LL_TIM_CHANNEL_CH4:
361 result = IC4Config(TIMx, TIM_IC_InitStruct);
362 break;
363 default:
364 break;
365 }
366
367 return result;
368 }
369
370 /**
371 * @brief Fills each TIM_EncoderInitStruct field with its default value
372 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
373 * configuration data structure)
374 * @retval None
375 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)376 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
377 {
378 /* Set the default configuration */
379 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
380 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
381 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
382 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
383 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
384 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
385 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
386 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
387 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
388 }
389
390 /**
391 * @brief Configure the encoder interface of the timer instance.
392 * @param TIMx Timer Instance
393 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
394 * configuration data structure)
395 * @retval An ErrorStatus enumeration value:
396 * - SUCCESS: TIMx registers are de-initialized
397 * - ERROR: not applicable
398 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)399 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
400 {
401 uint32_t tmpccmr1;
402 uint32_t tmpccer;
403
404 /* Check the parameters */
405 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
406 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
407 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
408 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
409 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
410 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
411 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
412 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
413 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
414 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
415
416 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
417 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
418
419 /* Get the TIMx CCMR1 register value */
420 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
421
422 /* Get the TIMx CCER register value */
423 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
424
425 /* Configure TI1 */
426 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
427 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
428 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
429 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
430
431 /* Configure TI2 */
432 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
433 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
434 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
435 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
436
437 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
438 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
439 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
440 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
441 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
442
443 /* Set encoder mode */
444 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
445
446 /* Write to TIMx CCMR1 */
447 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
448
449 /* Write to TIMx CCER */
450 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
451
452 return SUCCESS;
453 }
454
455 /**
456 * @}
457 */
458
459 /**
460 * @}
461 */
462
463 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
464 * @brief Private functions
465 * @{
466 */
467 /**
468 * @brief Configure the TIMx output channel 1.
469 * @param TIMx Timer Instance
470 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
471 * @retval An ErrorStatus enumeration value:
472 * - SUCCESS: TIMx registers are de-initialized
473 * - ERROR: not applicable
474 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)475 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
476 {
477 uint32_t tmpccmr1;
478 uint32_t tmpccer;
479 uint32_t tmpcr2;
480
481 /* Check the parameters */
482 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
483 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
484 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
485 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
486
487 /* Disable the Channel 1: Reset the CC1E Bit */
488 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
489
490 /* Get the TIMx CCER register value */
491 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
492
493 /* Get the TIMx CR2 register value */
494 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
495
496 /* Get the TIMx CCMR1 register value */
497 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
498
499 /* Reset Capture/Compare selection Bits */
500 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
501
502 /* Set the Output Compare Mode */
503 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
504
505 /* Set the Output Compare Polarity */
506 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
507
508 /* Set the Output State */
509 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
510
511 /* Write to TIMx CR2 */
512 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
513
514 /* Write to TIMx CCMR1 */
515 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
516
517 /* Set the Capture Compare Register value */
518 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
519
520 /* Write to TIMx CCER */
521 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
522
523 return SUCCESS;
524 }
525
526 /**
527 * @brief Configure the TIMx output channel 2.
528 * @param TIMx Timer Instance
529 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
530 * @retval An ErrorStatus enumeration value:
531 * - SUCCESS: TIMx registers are de-initialized
532 * - ERROR: not applicable
533 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)534 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
535 {
536 uint32_t tmpccmr1;
537 uint32_t tmpccer;
538 uint32_t tmpcr2;
539
540 /* Check the parameters */
541 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
542 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
543 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
544 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
545
546 /* Disable the Channel 2: Reset the CC2E Bit */
547 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
548
549 /* Get the TIMx CCER register value */
550 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
551
552 /* Get the TIMx CR2 register value */
553 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
554
555 /* Get the TIMx CCMR1 register value */
556 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
557
558 /* Reset Capture/Compare selection Bits */
559 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
560
561 /* Select the Output Compare Mode */
562 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
563
564 /* Set the Output Compare Polarity */
565 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
566
567 /* Set the Output State */
568 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
569
570 /* Write to TIMx CR2 */
571 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
572
573 /* Write to TIMx CCMR1 */
574 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
575
576 /* Set the Capture Compare Register value */
577 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
578
579 /* Write to TIMx CCER */
580 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
581
582 return SUCCESS;
583 }
584
585 /**
586 * @brief Configure the TIMx output channel 3.
587 * @param TIMx Timer Instance
588 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
589 * @retval An ErrorStatus enumeration value:
590 * - SUCCESS: TIMx registers are de-initialized
591 * - ERROR: not applicable
592 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)593 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
594 {
595 uint32_t tmpccmr2;
596 uint32_t tmpccer;
597 uint32_t tmpcr2;
598
599 /* Check the parameters */
600 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
601 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
602 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
603 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
604
605 /* Disable the Channel 3: Reset the CC3E Bit */
606 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
607
608 /* Get the TIMx CCER register value */
609 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
610
611 /* Get the TIMx CR2 register value */
612 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
613
614 /* Get the TIMx CCMR2 register value */
615 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
616
617 /* Reset Capture/Compare selection Bits */
618 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
619
620 /* Select the Output Compare Mode */
621 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
622
623 /* Set the Output Compare Polarity */
624 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
625
626 /* Set the Output State */
627 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
628
629 /* Write to TIMx CR2 */
630 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
631
632 /* Write to TIMx CCMR2 */
633 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
634
635 /* Set the Capture Compare Register value */
636 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
637
638 /* Write to TIMx CCER */
639 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
640
641 return SUCCESS;
642 }
643
644 /**
645 * @brief Configure the TIMx output channel 4.
646 * @param TIMx Timer Instance
647 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
648 * @retval An ErrorStatus enumeration value:
649 * - SUCCESS: TIMx registers are de-initialized
650 * - ERROR: not applicable
651 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)652 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
653 {
654 uint32_t tmpccmr2;
655 uint32_t tmpccer;
656 uint32_t tmpcr2;
657
658 /* Check the parameters */
659 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
660 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
661 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
662 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
663
664 /* Disable the Channel 4: Reset the CC4E Bit */
665 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
666
667 /* Get the TIMx CCER register value */
668 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
669
670 /* Get the TIMx CR2 register value */
671 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
672
673 /* Get the TIMx CCMR2 register value */
674 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
675
676 /* Reset Capture/Compare selection Bits */
677 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
678
679 /* Select the Output Compare Mode */
680 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
681
682 /* Set the Output Compare Polarity */
683 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
684
685 /* Set the Output State */
686 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
687
688 /* Write to TIMx CR2 */
689 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
690
691 /* Write to TIMx CCMR2 */
692 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
693
694 /* Set the Capture Compare Register value */
695 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
696
697 /* Write to TIMx CCER */
698 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
699
700 return SUCCESS;
701 }
702
703
704 /**
705 * @brief Configure the TIMx input channel 1.
706 * @param TIMx Timer Instance
707 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
708 * @retval An ErrorStatus enumeration value:
709 * - SUCCESS: TIMx registers are de-initialized
710 * - ERROR: not applicable
711 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)712 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
713 {
714 /* Check the parameters */
715 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
716 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
717 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
718 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
719 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
720
721 /* Disable the Channel 1: Reset the CC1E Bit */
722 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
723
724 /* Select the Input and set the filter and the prescaler value */
725 MODIFY_REG(TIMx->CCMR1,
726 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
727 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
728
729 /* Select the Polarity and set the CC1E Bit */
730 MODIFY_REG(TIMx->CCER,
731 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
732 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
733
734 return SUCCESS;
735 }
736
737 /**
738 * @brief Configure the TIMx input channel 2.
739 * @param TIMx Timer Instance
740 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
741 * @retval An ErrorStatus enumeration value:
742 * - SUCCESS: TIMx registers are de-initialized
743 * - ERROR: not applicable
744 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)745 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
746 {
747 /* Check the parameters */
748 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
749 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
750 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
751 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
752 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
753
754 /* Disable the Channel 2: Reset the CC2E Bit */
755 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
756
757 /* Select the Input and set the filter and the prescaler value */
758 MODIFY_REG(TIMx->CCMR1,
759 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
760 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
761
762 /* Select the Polarity and set the CC2E Bit */
763 MODIFY_REG(TIMx->CCER,
764 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
765 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
766
767 return SUCCESS;
768 }
769
770 /**
771 * @brief Configure the TIMx input channel 3.
772 * @param TIMx Timer Instance
773 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
774 * @retval An ErrorStatus enumeration value:
775 * - SUCCESS: TIMx registers are de-initialized
776 * - ERROR: not applicable
777 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)778 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
779 {
780 /* Check the parameters */
781 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
782 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
783 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
784 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
785 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
786
787 /* Disable the Channel 3: Reset the CC3E Bit */
788 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
789
790 /* Select the Input and set the filter and the prescaler value */
791 MODIFY_REG(TIMx->CCMR2,
792 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
793 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
794
795 /* Select the Polarity and set the CC3E Bit */
796 MODIFY_REG(TIMx->CCER,
797 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
798 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
799
800 return SUCCESS;
801 }
802
803 /**
804 * @brief Configure the TIMx input channel 4.
805 * @param TIMx Timer Instance
806 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
807 * @retval An ErrorStatus enumeration value:
808 * - SUCCESS: TIMx registers are de-initialized
809 * - ERROR: not applicable
810 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)811 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
812 {
813 /* Check the parameters */
814 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
815 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
816 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
817 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
818 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
819
820 /* Disable the Channel 4: Reset the CC4E Bit */
821 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
822
823 /* Select the Input and set the filter and the prescaler value */
824 MODIFY_REG(TIMx->CCMR2,
825 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
826 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
827
828 /* Select the Polarity and set the CC2E Bit */
829 MODIFY_REG(TIMx->CCER,
830 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
831 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
832
833 return SUCCESS;
834 }
835
836
837 /**
838 * @}
839 */
840
841 /**
842 * @}
843 */
844
845 #endif /* TIM1 || TIM3 || TIM21 || TIM22 || TIM6 || TIM7 */
846
847 /**
848 * @}
849 */
850
851 #endif /* USE_FULL_LL_DRIVER */
852
853
