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Searched refs:XSPI_DCR1_MTYP_1 (Results 1 – 25 of 29) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_xspi.h332 #define HAL_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory…
333 #define HAL_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix …
335 #define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory…
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_xspi.h364 #define HAL_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory…
365 #define HAL_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix …
367 #define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_xspi.h373 #define HAL_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory…
374 #define HAL_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix …
376 #define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory…
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_xspi.h384 #define HAL_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory…
385 #define HAL_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix …
387 #define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory…
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u595xx.h12915 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02… macro
13367 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
13781 #define HSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32u5a5xx.h13364 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02… macro
13816 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
14230 #define HSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32u5f7xx.h14413 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02… macro
14865 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
15279 #define HSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32u599xx.h16634 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02… macro
17086 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
17500 #define HSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32u5g7xx.h14862 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02… macro
15314 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
15728 #define HSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32u5f9xx.h17539 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02… macro
17991 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
18405 #define HSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32u5a9xx.h17083 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02… macro
17535 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
17949 #define HSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32u5g9xx.h17988 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02… macro
18440 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
18854 #define HSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32u545xx.h11965 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02… macro
12383 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32u535xx.h11565 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02… macro
11983 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32u575xx.h12600 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02… macro
13018 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32u585xx.h13049 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02… macro
13467 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h10875 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x020… macro
11287 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32h562xx.h11601 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x020… macro
12013 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32h533xx.h11284 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x020… macro
11696 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32h573xx.h14094 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x020… macro
14506 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
Dstm32h563xx.h13685 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x020… macro
14097 #define OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 /*!< 0x02…
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13210 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */ macro
Dstm32h7s7xx.h14244 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */ macro
Dstm32h7s3xx.h13842 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */ macro
Dstm32h7r7xx.h13610 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */ macro

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