1 /**
2   ******************************************************************************
3   * @file    stm32h7rsxx_hal_xspi.h
4   * @author  MCD Application Team
5   * @brief   Header file of XSPI HAL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2022 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7RSxx_HAL_XSPI_H
21 #define STM32H7RSxx_HAL_XSPI_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7rsxx_hal_def.h"
29 
30 #if defined(XSPI) || defined(XSPI1) || defined(XSPI2)
31 
32 /** @addtogroup STM32H7RSxx_HAL_Driver
33   * @{
34   */
35 
36 /** @addtogroup XSPI
37   * @{
38   */
39 
40 /* Exported types ------------------------------------------------------------*/
41 /** @defgroup XSPI_Exported_Types XSPI Exported Types
42   * @{
43   */
44 
45 /**
46   * @brief XSPI Init structure definition
47   */
48 typedef struct
49 {
50   uint32_t FifoThresholdByte;         /*!< This is the threshold used by the Peripheral to generate the interrupt
51                                            indicating that data are available in reception or free place
52                                            is available in transmission.
53                                            For XSPI, this parameter can be a value between 1 and 32 */
54   uint32_t MemoryMode;                /*!< It Specifies the memory mode.
55                                            This parameter can be a value of @ref XSPI_MemoryMode */
56   uint32_t MemoryType;                /*!< It indicates the external device type connected to the XSPI.
57                                            This parameter can be a value of @ref XSPI_MemoryType */
58   uint32_t MemorySize;                /*!< It defines the size of the external device connected to the XSPI,
59                                            it corresponds to the number of address bits required to access
60                                            the external device.
61                                            This parameter can be a value of @ref XSPI_MemorySize*/
62   uint32_t ChipSelectHighTimeCycle;   /*!< It defines the minimum number of clocks which the chip select
63                                            must remain high between commands.
64                                            This parameter can be a value between 1 and 64U */
65   uint32_t FreeRunningClock;          /*!< It enables or not the free running clock.
66                                            This parameter can be a value of @ref XSPI_FreeRunningClock */
67   uint32_t ClockMode;                 /*!< It indicates the level of clock when the chip select is released.
68                                            This parameter can be a value of @ref XSPI_ClockMode */
69   uint32_t WrapSize;                  /*!< It indicates the wrap-size corresponding the external device configuration.
70                                            This parameter can be a value of @ref XSPI_WrapSize */
71   uint32_t ClockPrescaler;            /*!< It specifies the prescaler factor used for generating
72                                            the external clock based on the AHB clock.
73                                            This parameter can be a value between 0 and 255U */
74   uint32_t SampleShifting;            /*!< It allows to delay to 1/2 cycle the data sampling in order
75                                            to take in account external signal delays.
76                                            This parameter can be a value of @ref XSPI_SampleShifting */
77   uint32_t DelayHoldQuarterCycle;     /*!< It allows to hold to 1/4 cycle the data.
78                                            This parameter can be a value of @ref XSPI_DelayHoldQuarterCycle */
79   uint32_t ChipSelectBoundary;        /*!< It enables the transaction boundary feature and
80                                            defines the boundary of bytes to release the chip select.
81                                            This parameter can be a value of @ref XSPI_ChipSelectBoundary  */
82   uint32_t MaxTran;                   /*!< It enables the communication regulation feature. The chip select is
83                                            released every MaxTran+1 bytes when the other XSPI request the access
84                                            to the bus.
85                                            This parameter can be a value between 0 and 255U */
86   uint32_t Refresh;                   /*!< It enables the refresh rate feature. The chip select is released every
87                                            Refresh+1 clock cycles.
88                                            This parameter can be a value between 0 and 0xFFFFFFFF */
89   uint32_t MemorySelect;              /*!< It indicates if the output of nCS.
90                                            This parameter can be a value of @ref XSPI_MemorySelect  */
91 } XSPI_InitTypeDef;
92 
93 /**
94   * @brief  HAL XSPI Handle Structure definition
95   */
96 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
97 typedef struct __XSPI_HandleTypeDef
98 #else
99 typedef struct
100 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
101 {
102   XSPI_TypeDef               *Instance;     /*!< XSPI registers base address                           */
103   XSPI_InitTypeDef           Init;          /*!< XSPI initialization parameters                        */
104   uint8_t                    *pBuffPtr;     /*!< Address of the XSPI buffer for transfer               */
105   __IO uint32_t              XferSize;      /*!< Number of data to transfer                            */
106   __IO uint32_t              XferCount;     /*!< Counter of data transferred                           */
107   DMA_HandleTypeDef          *hdmatx;       /*!< Handle of the DMA channel used for transmit           */
108   DMA_HandleTypeDef          *hdmarx;       /*!< Handle of the DMA channel used for receive            */
109   __IO uint32_t              State;         /*!< Internal state of the XSPI HAL driver                 */
110   __IO uint32_t              ErrorCode;     /*!< Error code in case of HAL driver internal error       */
111   uint32_t                   Timeout;       /*!< Timeout used for the XSPI external device access      */
112 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
113   void (* ErrorCallback)(struct __XSPI_HandleTypeDef *hxspi);
114   void (* AbortCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
115   void (* FifoThresholdCallback)(struct __XSPI_HandleTypeDef *hxspi);
116   void (* CmdCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
117   void (* RxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
118   void (* TxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
119   void (* RxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
120   void (* TxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
121   void (* StatusMatchCallback)(struct __XSPI_HandleTypeDef *hxspi);
122   void (* TimeOutCallback)(struct __XSPI_HandleTypeDef *hxspi);
123 
124   void (* MspInitCallback)(struct __XSPI_HandleTypeDef *hxspi);
125   void (* MspDeInitCallback)(struct __XSPI_HandleTypeDef *hxspi);
126 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
127 } XSPI_HandleTypeDef;
128 
129 /**
130   * @brief  HAL XSPI Regular Command Structure definition
131   */
132 typedef struct
133 {
134   uint32_t OperationType;             /*!< It indicates if the configuration applies to the common registers or
135                                            to the registers for the write operation (these registers are only
136                                            used for memory-mapped mode).
137                                            This parameter can be a value of @ref XSPI_OperationType */
138   uint32_t IOSelect;                  /*!< It indicates the IOs used to exchange data with external memory.
139                                            This parameter can be a value of @ref XSPI_IOSelect */
140   uint32_t Instruction;               /*!< It contains the instruction to be sent to the device.
141                                            This parameter can be a value between 0 and 0xFFFFFFFFU */
142   uint32_t InstructionMode;           /*!< It indicates the mode of the instruction.
143                                            This parameter can be a value of @ref XSPI_InstructionMode */
144   uint32_t InstructionWidth;          /*!< It indicates the width of the instruction.
145                                            This parameter can be a value of @ref XSPI_InstructionWidth */
146   uint32_t InstructionDTRMode;        /*!< It enables or not the DTR mode for the instruction phase.
147                                            This parameter can be a value of @ref XSPI_InstructionDTRMode */
148   uint32_t Address;                   /*!< It contains the address to be sent to the device.
149                                            This parameter can be a value between 0 and 0xFFFFFFFF */
150   uint32_t AddressMode;               /*!< It indicates the address mode. Address mode precises number of lines
151                                            for address (except no address).
152                                            This parameter can be a value of @ref XSPI_AddressMode */
153   uint32_t AddressWidth;              /*!< It indicates the width of the address.
154                                            This parameter can be a value of @ref XSPI_AddressWidth */
155   uint32_t AddressDTRMode;            /*!< It enables or not the DTR mode for the address phase.
156                                            This parameter can be a value of @ref XSPI_AddressDTRMode */
157   uint32_t AlternateBytes;            /*!< It contains the alternate bytes to be sent to the device.
158                                            This parameter can be a value between 0 and 0xFFFFFFFF */
159   uint32_t AlternateBytesMode;        /*!< It indicates the mode of the alternate bytes.
160                                            This parameter can be a value of @ref XSPI_AlternateBytesMode */
161   uint32_t AlternateBytesWidth;       /*!< It indicates the width of the alternate bytes.
162                                            This parameter can be a value of @ref XSPI_AlternateBytesWidth */
163   uint32_t AlternateBytesDTRMode;     /*!< It enables or not the DTR mode for the alternate bytes phase.
164                                            This parameter can be a value of @ref XSPI_AlternateBytesDTRMode */
165   uint32_t DataMode;                  /*!< It indicates the data mode. Data mode precises number of lines
166                                            for data exchange (except no data).
167                                            This parameter can be a value of @ref XSPI_DataMode */
168   uint32_t DataLength;                /*!< It indicates the number of data transferred with this command.
169                                            This field is only used for indirect mode.
170                                            This parameter can be a value between 1 and 0xFFFFFFFFU */
171   uint32_t DataDTRMode;               /*!< It enables or not the DTR mode for the data phase.
172                                            This parameter can be a value of @ref XSPI_DataDTRMode */
173   uint32_t DummyCycles;               /*!< It indicates the number of dummy cycles inserted before data phase.
174                                            This parameter can be a value between 0 and 31U */
175   uint32_t DQSMode;                   /*!< It enables or not the data strobe management.
176                                            This parameter can be a value of @ref XSPI_DQSMode */
177 } XSPI_RegularCmdTypeDef;
178 /**
179   * @brief  HAL XSPI Hyperbus Configuration Structure definition
180   */
181 typedef struct
182 {
183   uint32_t RWRecoveryTimeCycle;       /*!< It indicates the number of cycles for the device read write recovery time.
184                                            This parameter can be a value between 0 and 255U */
185   uint32_t AccessTimeCycle;           /*!< It indicates the number of cycles for the device access time.
186                                            This parameter can be a value between 0 and 255U */
187   uint32_t WriteZeroLatency;          /*!< It enables or not the latency for the write access.
188                                            This parameter can be a value of @ref XSPI_WriteZeroLatency */
189   uint32_t LatencyMode;               /*!< It configures the latency mode.
190                                            This parameter can be a value of @ref XSPI_LatencyMode */
191 } XSPI_HyperbusCfgTypeDef;
192 
193 /**
194   * @brief  HAL XSPI Hyperbus Command Structure definition
195   */
196 typedef struct
197 {
198   uint32_t AddressSpace;              /*!< It indicates the address space accessed by the command.
199                                            This parameter can be a value of @ref XSPI_AddressSpace */
200   uint32_t Address;                   /*!< It contains the address to be sent to the device.
201                                            This parameter can be a value between 0 and 0xFFFFFFFF */
202   uint32_t AddressWidth;              /*!< It indicates the width of the address.
203                                            This parameter can be a value of @ref XSPI_AddressWidth */
204   uint32_t DataLength;                /*!< It indicates the number of data transferred with this command.
205                                            This field is only used for indirect mode.
206                                            This parameter can be a value between 1 and 0xFFFFFFFF
207                                            In case of autopolling mode, this parameter can be
208                                            any value between 1 and 4 */
209   uint32_t DQSMode;                   /*!< It enables or not the data strobe management.
210                                            This parameter can be a value of @ref XSPI_DQSMode */
211   uint32_t DataMode;                  /*!< It indicates the data mode. Data mode precises number of lines
212                                            for data exchange (except no data).
213                                            This parameter can be a value of @ref XSPI_DataMode */
214 } XSPI_HyperbusCmdTypeDef;
215 
216 /**
217   * @brief  HAL XSPI Auto Polling mode configuration structure definition
218   */
219 typedef struct
220 {
221   uint32_t MatchValue;                /*!< Specifies the value to be compared with the masked status register to get
222                                            a match.
223                                            This parameter can be any value between 0 and 0xFFFFFFFFU */
224   uint32_t MatchMask;                 /*!< Specifies the mask to be applied to the status bytes received.
225                                            This parameter can be any value between 0 and 0xFFFFFFFFU */
226   uint32_t MatchMode;                 /*!< Specifies the method used for determining a match.
227                                            This parameter can be a value of @ref XSPI_MatchMode */
228   uint32_t AutomaticStop;             /*!< Specifies if automatic polling is stopped after a match.
229                                            This parameter can be a value of @ref XSPI_AutomaticStop */
230   uint32_t IntervalTime;              /*!< Specifies the number of clock cycles between two read during automatic
231                                            polling phases.
232                                            This parameter can be any value between 0 and 0xFFFFU */
233 } XSPI_AutoPollingTypeDef;
234 
235 /**
236   * @brief  HAL XSPI Memory Mapped mode configuration structure definition
237   */
238 typedef struct
239 {
240   uint32_t TimeOutActivation;         /*!< Specifies if the timeout counter is enabled to release the chip select.
241                                            This parameter can be a value of @ref XSPI_TimeOutActivation */
242   uint32_t TimeoutPeriodClock;        /*!< Specifies the number of clock to wait when the FIFO is full before to
243                                            release the chip select.
244                                            This parameter can be any value between 0 and 0xFFFFU */
245 } XSPI_MemoryMappedTypeDef;
246 
247 /**
248   * @brief HAL XSPI IO Manager Configuration structure definition
249   */
250 typedef struct
251 {
252   uint32_t nCSOverride;               /*!< It indicates Chip select selector override setting for XSPI.
253                                            This parameter can be a value @ref XSPIM_MemorySelect_Override */
254   uint32_t IOPort;                    /*!< It indicates which port of the XSPI IO Manager is used for the instance.
255                                            This parameter can be a value of @ref XSPI_IO_Manger_IOPort */
256   uint32_t Req2AckTime;               /*!< It indicates the minimum switching duration (in number of clock cycles)
257                                            expected if some signals are multiplexed in the XSPI IO Manager with the
258                                            other XSPI.
259                                            This parameter can be a value between 1 and 256 */
260 } XSPIM_CfgTypeDef;
261 
262 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
263 /**
264   * @brief  HAL XSPI Callback ID enumeration definition
265   */
266 typedef enum
267 {
268   HAL_XSPI_ERROR_CB_ID          = 0x00U,  /*!< XSPI Error Callback ID            */
269   HAL_XSPI_ABORT_CB_ID          = 0x01U,  /*!< XSPI Abort Callback ID            */
270   HAL_XSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< XSPI FIFO Threshold Callback ID   */
271   HAL_XSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< XSPI Command Complete Callback ID */
272   HAL_XSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< XSPI Rx Complete Callback ID      */
273   HAL_XSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< XSPI Tx Complete Callback ID      */
274   HAL_XSPI_RX_HALF_CPLT_CB_ID   = 0x06U,  /*!< XSPI Rx Half Complete Callback ID */
275   HAL_XSPI_TX_HALF_CPLT_CB_ID   = 0x07U,  /*!< XSPI Tx Half Complete Callback ID */
276   HAL_XSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< XSPI Status Match Callback ID     */
277   HAL_XSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< XSPI Timeout Callback ID          */
278   HAL_XSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< XSPI MspInit Callback ID          */
279   HAL_XSPI_MSP_DEINIT_CB_ID     = 0x0BU   /*!< XSPI MspDeInit Callback ID        */
280 } HAL_XSPI_CallbackIDTypeDef;
281 
282 /**
283   * @brief  HAL XSPI Callback pointer definition
284   */
285 typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi);
286 
287 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
288 /**
289   * @brief  HAL XSPI High-speed interface calibration structure definition
290   */
291 typedef struct
292 {
293   uint32_t DelayValueType;            /*!< It indicates which calibration is concerned by the configuration.
294                                            This parameter can be a value of @ref XSPI_DelayType */
295   uint32_t FineCalibrationUnit;       /*!< It indicates the fine calibration value of the delay.
296                                            This parameter can be a value between 0 and 0x7FU */
297   uint32_t CoarseCalibrationUnit;     /*!< It indicates the coarse calibration value of the delay.
298                                            This parameter can be a value between 0 and 0x1FU */
299   uint32_t MaxCalibration;            /*!< It indicates that the calibration is outside the range of DLL master.
300                                            It applies only when the DelayValueType is HAL_XSPI_CAL_FULL_CYCLE_DELAY.
301                                            This parameter can be a value of @ref XSPI_MaxCal */
302 } XSPI_HSCalTypeDef;
303 
304 /**
305   * @}
306   */
307 
308 /* Exported constants --------------------------------------------------------*/
309 /** @defgroup XSPI_Exported_Constants XSPI Exported Constants
310   * @{
311   */
312 
313 /** @defgroup XSPI_State XSPI State
314   * @{
315   */
316 #define HAL_XSPI_STATE_RESET                 (0x00000000U)  /*!< Initial state                                                          */
317 #define HAL_XSPI_STATE_READY                 (0x00000002U)  /*!< Driver ready to be used                                                */
318 #define HAL_XSPI_STATE_HYPERBUS_INIT         (0x00000001U)  /*!< Initialization done in hyperbus mode but timing configuration not done */
319 #define HAL_XSPI_STATE_CMD_CFG               (0x00000004U)  /*!< Command (regular or hyperbus) configured, ready for an action          */
320 #define HAL_XSPI_STATE_READ_CMD_CFG          (0x00000014U)  /*!< Read command configuration done, not the write command configuration   */
321 #define HAL_XSPI_STATE_WRITE_CMD_CFG         (0x00000024U)  /*!< Write command configuration done, not the read command configuration   */
322 #define HAL_XSPI_STATE_BUSY_CMD              (0x00000008U)  /*!< Command without data on-going                                          */
323 #define HAL_XSPI_STATE_BUSY_TX               (0x00000018U)  /*!< Indirect Tx on-going                                                   */
324 #define HAL_XSPI_STATE_BUSY_RX               (0x00000028U)  /*!< Indirect Rx on-going                                                   */
325 #define HAL_XSPI_STATE_BUSY_AUTO_POLLING     (0x00000048U)  /*!< Auto-polling on-going                                                  */
326 #define HAL_XSPI_STATE_BUSY_MEM_MAPPED       (0x00000088U)  /*!< Memory-mapped on-going                                                 */
327 #define HAL_XSPI_STATE_ABORT                 (0x00000100U)  /*!< Abort on-going                                                         */
328 #define HAL_XSPI_STATE_ERROR                 (0x00000200U)  /*!< Blocking error, driver should be re-initialized                        */
329 /**
330   * @}
331   */
332 
333 /** @defgroup XSPI_ErrorCode XSPI Error Code
334   * @{
335   */
336 #define HAL_XSPI_ERROR_NONE                  (0x00000000U)  /*!< No error                         */
337 #define HAL_XSPI_ERROR_TIMEOUT               (0x00000001U)  /*!< Timeout error                    */
338 #define HAL_XSPI_ERROR_TRANSFER              (0x00000002U)  /*!< Transfer error                   */
339 #define HAL_XSPI_ERROR_DMA                   (0x00000004U)  /*!< DMA transfer error               */
340 #define HAL_XSPI_ERROR_INVALID_PARAM         (0x00000008U)  /*!< Invalid parameters error         */
341 #define HAL_XSPI_ERROR_INVALID_SEQUENCE      (0x00000010U)  /*!< Sequence is incorrect            */
342 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
343 #define HAL_XSPI_ERROR_INVALID_CALLBACK      (0x00000020U)  /*!< Invalid callback error           */
344 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
345 /**
346   * @}
347   */
348 
349 /** @defgroup XSPI_MemoryMode XSPI Memory Mode
350   * @{
351   */
352 #define HAL_XSPI_SINGLE_MEM                  (0x00000000U)  /*!< Dual-memory mode disabled        */
353 #define HAL_XSPI_DUAL_MEM                    (XSPI_CR_DMM)  /*!< Dual mode enabled                */
354 
355 /**
356   * @}
357   */
358 
359 /** @defgroup XSPI_MemoryType XSPI Memory Type
360   * @{
361   */
362 #define HAL_XSPI_MEMTYPE_MICRON              (0x00000000U)                           /*!< Micron mode      */
363 #define HAL_XSPI_MEMTYPE_MACRONIX            (XSPI_DCR1_MTYP_0)                      /*!< Macronix mode    */
364 #define HAL_XSPI_MEMTYPE_APMEM               (XSPI_DCR1_MTYP_1)                      /*!< AP Memory mode   */
365 #define HAL_XSPI_MEMTYPE_MACRONIX_RAM        ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/
366 #define HAL_XSPI_MEMTYPE_HYPERBUS            (XSPI_DCR1_MTYP_2)                      /*!< Hyperbus mode    */
367 #define HAL_XSPI_MEMTYPE_APMEM_16BITS        ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode   */
368 
369 /**
370   * @}
371   */
372 
373 /** @defgroup XSPI_MemorySize XSPI Memory Size
374   * @{
375   */
376 #define HAL_XSPI_SIZE_16B                    (0x00000000U)  /*!<  16 bits  (  2  Byte = 2^( 0+1)) */
377 #define HAL_XSPI_SIZE_32B                    (0x00000001U)  /*!<  32 bits  (  4  Byte = 2^( 1+1)) */
378 #define HAL_XSPI_SIZE_64B                    (0x00000002U)  /*!<  64 bits  (  8  Byte = 2^( 2+1)) */
379 #define HAL_XSPI_SIZE_128B                   (0x00000003U)  /*!< 128 bits  ( 16  Byte = 2^( 3+1)) */
380 #define HAL_XSPI_SIZE_256B                   (0x00000004U)  /*!< 256 bits  ( 32  Byte = 2^( 4+1)) */
381 #define HAL_XSPI_SIZE_512B                   (0x00000005U)  /*!< 512 bits  ( 64  Byte = 2^( 5+1)) */
382 #define HAL_XSPI_SIZE_1KB                    (0x00000006U)  /*!<   1 Kbits (128  Byte = 2^( 6+1)) */
383 #define HAL_XSPI_SIZE_2KB                    (0x00000007U)  /*!<   2 Kbits (256  Byte = 2^( 7+1)) */
384 #define HAL_XSPI_SIZE_4KB                    (0x00000008U)  /*!<   4 Kbits (512  Byte = 2^( 8+1)) */
385 #define HAL_XSPI_SIZE_8KB                    (0x00000009U)  /*!<   8 Kbits (  1 KByte = 2^( 9+1)) */
386 #define HAL_XSPI_SIZE_16KB                   (0x0000000AU)  /*!<  16 Kbits (  2 KByte = 2^(10+1)) */
387 #define HAL_XSPI_SIZE_32KB                   (0x0000000BU)  /*!<  32 Kbits (  4 KByte = 2^(11+1)) */
388 #define HAL_XSPI_SIZE_64KB                   (0x0000000CU)  /*!<  64 Kbits (  8 KByte = 2^(12+1)) */
389 #define HAL_XSPI_SIZE_128KB                  (0x0000000DU)  /*!< 128 Kbits ( 16 KByte = 2^(13+1)) */
390 #define HAL_XSPI_SIZE_256KB                  (0x0000000EU)  /*!< 256 Kbits ( 32 KByte = 2^(14+1)) */
391 #define HAL_XSPI_SIZE_512KB                  (0x0000000FU)  /*!< 512 Kbits ( 64 KByte = 2^(15+1)) */
392 #define HAL_XSPI_SIZE_1MB                    (0x00000010U)  /*!<   1 Mbits (128 KByte = 2^(16+1)) */
393 #define HAL_XSPI_SIZE_2MB                    (0x00000011U)  /*!<   2 Mbits (256 KByte = 2^(17+1)) */
394 #define HAL_XSPI_SIZE_4MB                    (0x00000012U)  /*!<   4 Mbits (512 KByte = 2^(18+1)) */
395 #define HAL_XSPI_SIZE_8MB                    (0x00000013U)  /*!<   8 Mbits (  1 MByte = 2^(19+1)) */
396 #define HAL_XSPI_SIZE_16MB                   (0x00000014U)  /*!<  16 Mbits (  2 MByte = 2^(20+1)) */
397 #define HAL_XSPI_SIZE_32MB                   (0x00000015U)  /*!<  32 Mbits (  4 MByte = 2^(21+1)) */
398 #define HAL_XSPI_SIZE_64MB                   (0x00000016U)  /*!<  64 Mbits (  8 MByte = 2^(22+1)) */
399 #define HAL_XSPI_SIZE_128MB                  (0x00000017U)  /*!< 128 Mbits ( 16 MByte = 2^(23+1)) */
400 #define HAL_XSPI_SIZE_256MB                  (0x00000018U)  /*!< 256 Mbits ( 32 MByte = 2^(24+1)) */
401 #define HAL_XSPI_SIZE_512MB                  (0x00000019U)  /*!< 512 Mbits ( 64 MByte = 2^(25+1)) */
402 #define HAL_XSPI_SIZE_1GB                    (0x0000001AU)  /*!<   1 Gbits (128 MByte = 2^(26+1)) */
403 #define HAL_XSPI_SIZE_2GB                    (0x0000001BU)  /*!<   2 Gbits (256 MByte = 2^(27+1)) */
404 #define HAL_XSPI_SIZE_4GB                    (0x0000001CU)  /*!<   4 Gbits (256 MByte = 2^(28+1)) */
405 #define HAL_XSPI_SIZE_8GB                    (0x0000001DU)  /*!<   8 Gbits (256 MByte = 2^(29+1)) */
406 #define HAL_XSPI_SIZE_16GB                   (0x0000001EU)  /*!<  16 Gbits (256 MByte = 2^(30+1)) */
407 #define HAL_XSPI_SIZE_32GB                   (0x0000001FU)  /*!<  32 Gbits (256 MByte = 2^(31+1)) */
408 /**
409   * @}
410   */
411 
412 /** @defgroup XSPI_FreeRunningClock XSPI Free Running Clock
413   * @{
414   */
415 #define HAL_XSPI_FREERUNCLK_DISABLE          (0x00000000U)               /*!< CLK is not free running            */
416 #define HAL_XSPI_FREERUNCLK_ENABLE           ((uint32_t)XSPI_DCR1_FRCK)  /*!< CLK is always provided (running)   */
417 /**
418   * @}
419   */
420 
421 /** @defgroup XSPI_ClockMode XSPI Clock Mode
422   * @{
423   */
424 #define HAL_XSPI_CLOCK_MODE_0                (0x00000000U)                 /*!< CLK must stay low while nCS is high  */
425 #define HAL_XSPI_CLOCK_MODE_3                ((uint32_t)XSPI_DCR1_CKMODE)  /*!< CLK must stay high while nCS is high */
426 /**
427   * @}
428   */
429 
430 /** @defgroup XSPI_WrapSize XSPI Wrap-Size
431   * @{
432   */
433 #define HAL_XSPI_WRAP_NOT_SUPPORTED          (0x00000000U)                                             /*!< wrapped reads are not supported by the memory   */
434 #define HAL_XSPI_WRAP_16_BYTES               ((uint32_t)XSPI_DCR2_WRAPSIZE_1)                          /*!< external memory supports wrap size of 16 bytes  */
435 #define HAL_XSPI_WRAP_32_BYTES               ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes  */
436 #define HAL_XSPI_WRAP_64_BYTES               ((uint32_t)XSPI_DCR2_WRAPSIZE_2)                          /*!< external memory supports wrap size of 64 bytes  */
437 #define HAL_XSPI_WRAP_128_BYTES              ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */
438 /**
439   * @}
440   */
441 
442 /** @defgroup XSPI_SampleShifting XSPI Sample Shifting
443   * @{
444   */
445 #define HAL_XSPI_SAMPLE_SHIFT_NONE           (0x00000000U)                /*!< No shift                         */
446 #define HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE      ((uint32_t)XSPI_TCR_SSHIFT)  /*!< 1/2 cycle shift                  */
447 /**
448   * @}
449   */
450 
451 /** @defgroup XSPI_DelayHoldQuarterCycle XSPI Delay Hold Quarter Cycle
452   * @{
453   */
454 #define HAL_XSPI_DHQC_DISABLE                (0x00000000U)              /*!< No Delay                         */
455 #define HAL_XSPI_DHQC_ENABLE                 ((uint32_t)XSPI_TCR_DHQC)  /*!< Delay Hold 1/4 cycle             */
456 /**
457   * @}
458   */
459 
460 /** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary
461   * @{
462   */
463 #define HAL_XSPI_BONDARYOF_NONE              (0x00000000U)  /*!     CS boundary disabled        */
464 #define HAL_XSPI_BONDARYOF_16B               (0x00000001U)  /*!<  16 bits  (  2  Byte = 2^(1))  */
465 #define HAL_XSPI_BONDARYOF_32B               (0x00000002U)  /*!<  32 bits  (  4  Byte = 2^(2))  */
466 #define HAL_XSPI_BONDARYOF_64B               (0x00000003U)  /*!<  64 bits  (  8  Byte = 2^(3))  */
467 #define HAL_XSPI_BONDARYOF_128B              (0x00000004U)  /*!< 128 bits  ( 16  Byte = 2^(4))  */
468 #define HAL_XSPI_BONDARYOF_256B              (0x00000005U)  /*!< 256 bits  ( 32  Byte = 2^(5))  */
469 #define HAL_XSPI_BONDARYOF_512B              (0x00000006U)  /*!< 512 bits  ( 64  Byte = 2^(6))  */
470 #define HAL_XSPI_BONDARYOF_1KB               (0x00000007U)  /*!<   1 Kbits (128  Byte = 2^(7))  */
471 #define HAL_XSPI_BONDARYOF_2KB               (0x00000008U)  /*!<   2 Kbits (256  Byte = 2^(8))  */
472 #define HAL_XSPI_BONDARYOF_4KB               (0x00000009U)  /*!<   4 Kbits (512  Byte = 2^(9))  */
473 #define HAL_XSPI_BONDARYOF_8KB               (0x0000000AU)  /*!<   8 Kbits (  1 KByte = 2^(10)) */
474 #define HAL_XSPI_BONDARYOF_16KB              (0x0000000BU)  /*!<  16 Kbits (  2 KByte = 2^(11)) */
475 #define HAL_XSPI_BONDARYOF_32KB              (0x0000000CU)  /*!<  32 Kbits (  4 KByte = 2^(12)) */
476 #define HAL_XSPI_BONDARYOF_64KB              (0x0000000DU)  /*!< 64 Kbits  (  8 KByte = 2^(13)) */
477 #define HAL_XSPI_BONDARYOF_128KB             (0x0000000EU)  /*!< 128 Kbits ( 16 KByte = 2^(14)) */
478 #define HAL_XSPI_BONDARYOF_256KB             (0x0000000FU)  /*!< 256 Kbits ( 32 KByte = 2^(15)) */
479 #define HAL_XSPI_BONDARYOF_512KB             (0x00000010U)  /*!< 512 Kbits ( 64 KByte = 2^(16)) */
480 #define HAL_XSPI_BONDARYOF_1MB               (0x00000011U)  /*!<   1 Mbits (128 KByte = 2^(17)) */
481 #define HAL_XSPI_BONDARYOF_2MB               (0x00000012U)  /*!<   2 Mbits (256 KByte = 2^(18)) */
482 #define HAL_XSPI_BONDARYOF_4MB               (0x00000013U)  /*!<   4 Mbits (512 KByte = 2^(19)) */
483 #define HAL_XSPI_BONDARYOF_8MB               (0x00000014U)  /*!<   8 Mbits (  1 MByte = 2^(20)) */
484 #define HAL_XSPI_BONDARYOF_16MB              (0x00000015U)  /*!<  16 Mbits (  2 MByte = 2^(21)) */
485 #define HAL_XSPI_BONDARYOF_32MB              (0x00000016U)  /*!<  32 Mbits (  4 MByte = 2^(22)) */
486 #define HAL_XSPI_BONDARYOF_64MB              (0x00000017U)  /*!<  64 Mbits (  8 MByte = 2^(23)) */
487 #define HAL_XSPI_BONDARYOF_128MB             (0x00000018U)  /*!< 128 Mbits ( 16 MByte = 2^(24)) */
488 #define HAL_XSPI_BONDARYOF_256MB             (0x00000019U)  /*!< 256 Mbits ( 32 MByte = 2^(25)) */
489 #define HAL_XSPI_BONDARYOF_512MB             (0x0000001AU)  /*!< 512 Mbits ( 64 MByte = 2^(26)) */
490 #define HAL_XSPI_BONDARYOF_1GB               (0x0000001BU)  /*!<   1 Gbits (128 MByte = 2^(27)) */
491 #define HAL_XSPI_BONDARYOF_2GB               (0x0000001CU)  /*!<   2 Gbits (256 MByte = 2^(28)) */
492 #define HAL_XSPI_BONDARYOF_4GB               (0x0000001DU)  /*!<   4 Gbits (512 MByte = 2^(29)) */
493 #define HAL_XSPI_BONDARYOF_8GB               (0x0000001EU)  /*!<   8 Gbits (  1 GByte = 2^(30)) */
494 #define HAL_XSPI_BONDARYOF_16GB              (0x0000001FU)  /*!<  16 Gbits (  2 GByte = 2^(31)) */
495 /**
496   * @}
497   */
498 
499 /** @defgroup XSPI_MemorySelect XSPI Memory Select
500   * @{
501   */
502 #define HAL_XSPI_CSSEL_NCS1                  (0x00000000U)             /*!<  The output of nCS is nCS1       */
503 #define HAL_XSPI_CSSEL_NCS2                  ((uint32_t)XSPI_CR_CSSEL) /*!<  The output of nCS is nCS2       */
504 /**
505   * @}
506   */
507 
508 /** @defgroup XSPI_OperationType XSPI Operation Type
509   * @{
510   */
511 #define HAL_XSPI_OPTYPE_COMMON_CFG           (0x00000000U)  /*!< Common configuration (indirect or auto-polling mode) */
512 #define HAL_XSPI_OPTYPE_READ_CFG             (0x00000001U)  /*!< Read configuration (memory-mapped mode)              */
513 #define HAL_XSPI_OPTYPE_WRITE_CFG            (0x00000002U)  /*!< Write configuration (memory-mapped mode)             */
514 #define HAL_XSPI_OPTYPE_WRAP_CFG             (0x00000003U)  /*!< Wrap configuration (memory-mapped mode)              */
515 
516 /**
517   * @}
518   */
519 
520 /** @defgroup XSPI_IOSelect XSPI IO Select
521   * @{
522   */
523 #define HAL_XSPI_SELECT_IO_3_0               (0x00000000U)                                /*!< Data exchanged over IO[3:0]   */
524 #define HAL_XSPI_SELECT_IO_7_4               ((uint32_t)XSPI_CR_MSEL_0)                               /*!< Data exchanged over IO[7:4]   */
525 #define HAL_XSPI_SELECT_IO_11_8              ((uint32_t)XSPI_CR_MSEL_1)                               /*!< Data exchanged over IO[11:8]  */
526 #define HAL_XSPI_SELECT_IO_15_12             ((uint32_t)XSPI_CR_MSEL )                                /*!< Data exchanged over IO[15:12] */
527 #define HAL_XSPI_SELECT_IO_7_0               (0x00000000U)                                                            /*!< Data exchanged over IO[7:0]   */
528 #define HAL_XSPI_SELECT_IO_15_8              ((uint32_t)XSPI_CR_MSEL_1)                               /*!< Data exchanged over IO[15:8]  */
529 /**
530   * @}
531   */
532 
533 /** @defgroup XSPI_InstructionMode XSPI Instruction Mode
534   * @{
535   */
536 #define HAL_XSPI_INSTRUCTION_NONE            (0x00000000U)                                     /*!< No instruction               */
537 #define HAL_XSPI_INSTRUCTION_1_LINE          ((uint32_t)XSPI_CCR_IMODE_0)                      /*!< Instruction on a single line */
538 #define HAL_XSPI_INSTRUCTION_2_LINES         ((uint32_t)XSPI_CCR_IMODE_1)                      /*!< Instruction on two lines     */
539 #define HAL_XSPI_INSTRUCTION_4_LINES         ((uint32_t)(XSPI_CCR_IMODE_0 | XSPI_CCR_IMODE_1)) /*!< Instruction on four lines    */
540 #define HAL_XSPI_INSTRUCTION_8_LINES         ((uint32_t)XSPI_CCR_IMODE_2)                      /*!< Instruction on eight lines   */
541 /**
542   * @}
543   */
544 
545 /** @defgroup XSPI_InstructionWidth XSPI Instruction Width
546   * @{
547   */
548 #define HAL_XSPI_INSTRUCTION_8_BITS          (0x00000000U)                 /*!< 8-bit instruction  */
549 #define HAL_XSPI_INSTRUCTION_16_BITS         ((uint32_t)XSPI_CCR_ISIZE_0)  /*!< 16-bit instruction */
550 #define HAL_XSPI_INSTRUCTION_24_BITS         ((uint32_t)XSPI_CCR_ISIZE_1)  /*!< 24-bit instruction */
551 #define HAL_XSPI_INSTRUCTION_32_BITS         ((uint32_t)XSPI_CCR_ISIZE)    /*!< 32-bit instruction */
552 /**
553   * @}
554   */
555 
556 /** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode
557   * @{
558   */
559 #define HAL_XSPI_INSTRUCTION_DTR_DISABLE     (0x00000000U)              /*!< DTR mode disabled for instruction phase */
560 #define HAL_XSPI_INSTRUCTION_DTR_ENABLE      ((uint32_t)XSPI_CCR_IDTR)  /*!< DTR mode enabled for instruction phase  */
561 /**
562   * @}
563   */
564 
565 /** @defgroup XSPI_AddressMode XSPI Address Mode
566   * @{
567   */
568 #define HAL_XSPI_ADDRESS_NONE                (0x00000000U)                                        /*!< No address               */
569 #define HAL_XSPI_ADDRESS_1_LINE              ((uint32_t)XSPI_CCR_ADMODE_0)                        /*!< Address on a single line */
570 #define HAL_XSPI_ADDRESS_2_LINES             ((uint32_t)XSPI_CCR_ADMODE_1)                        /*!< Address on two lines     */
571 #define HAL_XSPI_ADDRESS_4_LINES             ((uint32_t)(XSPI_CCR_ADMODE_0 | XSPI_CCR_ADMODE_1))  /*!< Address on four lines    */
572 #define HAL_XSPI_ADDRESS_8_LINES             ((uint32_t)XSPI_CCR_ADMODE_2)                        /*!< Address on eight lines   */
573 /**
574   * @}
575   */
576 
577 /** @defgroup XSPI_AddressWidth XSPI Address width
578   * @{
579   */
580 #define HAL_XSPI_ADDRESS_8_BITS              (0x00000000U)                  /*!< 8-bit address  */
581 #define HAL_XSPI_ADDRESS_16_BITS             ((uint32_t)XSPI_CCR_ADSIZE_0)  /*!< 16-bit address */
582 #define HAL_XSPI_ADDRESS_24_BITS             ((uint32_t)XSPI_CCR_ADSIZE_1)  /*!< 24-bit address */
583 #define HAL_XSPI_ADDRESS_32_BITS             ((uint32_t)XSPI_CCR_ADSIZE)    /*!< 32-bit address */
584 /**
585   * @}
586   */
587 
588 /** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode
589   * @{
590   */
591 #define HAL_XSPI_ADDRESS_DTR_DISABLE         (0x00000000U)               /*!< DTR mode disabled for address phase */
592 #define HAL_XSPI_ADDRESS_DTR_ENABLE          ((uint32_t)XSPI_CCR_ADDTR)  /*!< DTR mode enabled for address phase  */
593 /**
594   * @}
595   */
596 
597 /** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode
598   * @{
599   */
600 #define HAL_XSPI_ALT_BYTES_NONE              (0x00000000U)                                        /*!< No alternate bytes               */
601 #define HAL_XSPI_ALT_BYTES_1_LINE            ((uint32_t)XSPI_CCR_ABMODE_0)                        /*!< Alternate bytes on a single line */
602 #define HAL_XSPI_ALT_BYTES_2_LINES           ((uint32_t)XSPI_CCR_ABMODE_1)                        /*!< Alternate bytes on two lines     */
603 #define HAL_XSPI_ALT_BYTES_4_LINES           ((uint32_t)(XSPI_CCR_ABMODE_0 | XSPI_CCR_ABMODE_1))  /*!< Alternate bytes on four lines    */
604 #define HAL_XSPI_ALT_BYTES_8_LINES           ((uint32_t)XSPI_CCR_ABMODE_2)                        /*!< Alternate bytes on eight lines   */
605 /**
606   * @}
607   */
608 
609 /** @defgroup XSPI_AlternateBytesWidth XSPI Alternate Bytes Width
610   * @{
611   */
612 #define HAL_XSPI_ALT_BYTES_8_BITS            (0x00000000U)                  /*!< 8-bit alternate bytes  */
613 #define HAL_XSPI_ALT_BYTES_16_BITS           ((uint32_t)XSPI_CCR_ABSIZE_0)  /*!< 16-bit alternate bytes */
614 #define HAL_XSPI_ALT_BYTES_24_BITS           ((uint32_t)XSPI_CCR_ABSIZE_1)  /*!< 24-bit alternate bytes */
615 #define HAL_XSPI_ALT_BYTES_32_BITS           ((uint32_t)XSPI_CCR_ABSIZE)    /*!< 32-bit alternate bytes */
616 /**
617   * @}
618   */
619 
620 /** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode
621   * @{
622   */
623 #define HAL_XSPI_ALT_BYTES_DTR_DISABLE       (0x00000000U)               /*!< DTR mode disabled for alternate bytes phase */
624 #define HAL_XSPI_ALT_BYTES_DTR_ENABLE        ((uint32_t)XSPI_CCR_ABDTR)  /*!< DTR mode enabled for alternate bytes phase  */
625 /**
626   * @}
627   */
628 
629 /** @defgroup XSPI_DataMode XSPI Data Mode
630   * @{
631   */
632 #define HAL_XSPI_DATA_NONE                   (0x00000000U)                                      /*!< No data                                   */
633 #define HAL_XSPI_DATA_1_LINE                 ((uint32_t)XSPI_CCR_DMODE_0)                       /*!< Data on a single line                     */
634 #define HAL_XSPI_DATA_2_LINES                ((uint32_t)XSPI_CCR_DMODE_1)                       /*!< Data on two lines                         */
635 #define HAL_XSPI_DATA_4_LINES                ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_1))  /*!< Data on four lines                        */
636 #define HAL_XSPI_DATA_8_LINES                ((uint32_t)XSPI_CCR_DMODE_2)                       /*!< Data on eight lines                       */
637 #define HAL_XSPI_DATA_16_LINES               ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_2))  /*!< Data on sixteen lines valid for HSPI only */
638 /**
639   * @}
640   */
641 
642 /** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode
643   * @{
644   */
645 #define HAL_XSPI_DATA_DTR_DISABLE            (0x00000000U)              /*!< DTR mode disabled for data phase */
646 #define HAL_XSPI_DATA_DTR_ENABLE             ((uint32_t)XSPI_CCR_DDTR)  /*!< DTR mode enabled for data phase  */
647 /**
648   * @}
649   */
650 
651 /** @defgroup XSPI_DQSMode XSPI DQS Mode
652   * @{
653   */
654 #define HAL_XSPI_DQS_DISABLE                 (0x00000000U)              /*!< DQS disabled */
655 #define HAL_XSPI_DQS_ENABLE                  ((uint32_t)XSPI_CCR_DQSE)  /*!< DQS enabled  */
656 /**
657   * @}
658   */
659 
660 /** @defgroup XSPI_WriteZeroLatency XSPI Hyperbus Write Zero Latency Activation
661   * @{
662   */
663 #define HAL_XSPI_LATENCY_ON_WRITE            (0x00000000U)              /*!< Latency on write accesses    */
664 #define HAL_XSPI_NO_LATENCY_ON_WRITE         ((uint32_t)XSPI_HLCR_WZL)  /*!< No latency on write accesses */
665 /**
666   * @}
667   */
668 
669 /** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode
670   * @{
671   */
672 #define HAL_XSPI_VARIABLE_LATENCY            (0x00000000U)             /*!< Variable initial latency */
673 #define HAL_XSPI_FIXED_LATENCY               ((uint32_t)XSPI_HLCR_LM)  /*!< Fixed latency            */
674 /**
675   * @}
676   */
677 
678 /** @defgroup XSPI_AddressSpace XSPI Hyperbus Address Space
679   * @{
680   */
681 #define HAL_XSPI_MEMORY_ADDRESS_SPACE        (0x00000000U)                 /*!< HyperBus memory mode   */
682 #define HAL_XSPI_REGISTER_ADDRESS_SPACE      ((uint32_t)XSPI_DCR1_MTYP_0)  /*!< HyperBus register mode */
683 /**
684   * @}
685   */
686 
687 /** @defgroup XSPI_MatchMode XSPI Match Mode
688   * @{
689   */
690 #define HAL_XSPI_MATCH_MODE_AND              (0x00000000U)            /*!< AND match mode between unmasked bits */
691 #define HAL_XSPI_MATCH_MODE_OR               ((uint32_t)XSPI_CR_PMM)  /*!< OR match mode between unmasked bits  */
692 /**
693   * @}
694   */
695 
696 /** @defgroup XSPI_AutomaticStop XSPI Automatic Stop
697   * @{
698   */
699 #define HAL_XSPI_AUTOMATIC_STOP_DISABLE      (0x00000000U)             /*!< AutoPolling stops only with abort or XSPI disabling */
700 #define HAL_XSPI_AUTOMATIC_STOP_ENABLE       ((uint32_t)XSPI_CR_APMS)  /*!< AutoPolling stops as soon as there is a match       */
701 /**
702   * @}
703   */
704 
705 /** @defgroup XSPI_TimeOutActivation XSPI Timeout Activation
706   * @{
707   */
708 #define HAL_XSPI_TIMEOUT_COUNTER_DISABLE     (0x00000000U)             /*!< Timeout counter disabled, nCS remains active               */
709 #define HAL_XSPI_TIMEOUT_COUNTER_ENABLE      ((uint32_t)XSPI_CR_TCEN)  /*!< Timeout counter enabled, nCS released when timeout expires */
710 /**
711   * @}
712   */
713 
714 /** @defgroup XSPI_Flags XSPI Flags
715   * @{
716   */
717 #define HAL_XSPI_FLAG_BUSY                   XSPI_SR_BUSY  /*!< Busy flag: operation is ongoing                                                                          */
718 #define HAL_XSPI_FLAG_TO                     XSPI_SR_TOF   /*!< Timeout flag: timeout occurs in memory-mapped mode                                                       */
719 #define HAL_XSPI_FLAG_SM                     XSPI_SR_SMF   /*!< Status match flag: received data matches in autopolling mode                                             */
720 #define HAL_XSPI_FLAG_FT                     XSPI_SR_FTF   /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete              */
721 #define HAL_XSPI_FLAG_TC                     XSPI_SR_TCF   /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */
722 #define HAL_XSPI_FLAG_TE                     XSPI_SR_TEF   /*!< Transfer error flag: invalid address is being accessed                                                   */
723 /**
724   * @}
725   */
726 
727 /** @defgroup XSPI_Interrupts XSPI Interrupts
728   * @{
729   */
730 #define HAL_XSPI_IT_TO                       XSPI_CR_TOIE  /*!< Interrupt on the timeout flag           */
731 #define HAL_XSPI_IT_SM                       XSPI_CR_SMIE  /*!< Interrupt on the status match flag      */
732 #define HAL_XSPI_IT_FT                       XSPI_CR_FTIE  /*!< Interrupt on the fifo threshold flag    */
733 #define HAL_XSPI_IT_TC                       XSPI_CR_TCIE  /*!< Interrupt on the transfer complete flag */
734 #define HAL_XSPI_IT_TE                       XSPI_CR_TEIE  /*!< Interrupt on the transfer error flag    */
735 /**
736   * @}
737   */
738 
739 /** @defgroup XSPI_Timeout_definition XSPI Timeout definition
740   * @{
741   */
742 #define HAL_XSPI_TIMEOUT_DEFAULT_VALUE       (5000U)  /* 5 s */
743 /**
744   * @}
745   */
746 
747 /** @defgroup XSPI_IO_Manger_IOPort XSPI IO Port
748   * @{
749   */
750 #define HAL_XSPIM_IOPORT_1                 (0x00000000U)   /*!< Port 1 */
751 #define HAL_XSPIM_IOPORT_2                 (0x00000001U)   /*!< Port 2 */
752 /**
753   * @}
754   */
755 
756 
757 /** @defgroup XSPI_DelayType XSPI Calibration Delay Type
758   * @{
759   */
760 #define HAL_XSPI_CAL_FULL_CYCLE_DELAY      (0x00000000U)  /*!< Delay value equivalent to full memory-clock cycle                */
761 #define HAL_XSPI_CAL_FEEDBACK_CLK_DELAY    (0x00000001U)  /*!< Delay value for the feedback clock when reading without DQS      */
762 #define HAL_XSPI_CAL_DATA_OUTPUT_DELAY     (0x00000002U)  /*!< Delay value for output data in DDR mode for write operations     */
763 #define HAL_XSPI_CAL_DQS_INPUT_DELAY       (0x00000003U)  /*!< Delay value for DQS input when sampling data for read operations */
764 /**
765   * @}
766   */
767 
768 /** @defgroup XSPIM_MemorySelect_Override XSPIM Memory Select Override
769   * @{
770   */
771 #define HAL_XSPI_CSSEL_OVR_DISABLED         (0x00000000U)
772 #define HAL_XSPI_CSSEL_OVR_NCS1             (0x00000010U)             /*!< The chip select signal from XSPI is sent to NCS1 */
773 #define HAL_XSPI_CSSEL_OVR_NCS2             (0x00000070U)             /*!< The chip select signal from XSPI is sent to NCS2 */
774 /**
775   * @}
776   */
777 
778 /** @defgroup XSPI_MaxCal XSPI Calibration Maximal Value
779   * @{
780   */
781 #define HAL_XSPI_MAXCAL_NOT_REACHED        (0x00000000U)                   /*!< Memory-clock perido inside the range of DLL master                          */
782 #define HAL_XSPI_MAXCAL_REACHED            ((uint32_t)XSPI_CALFCR_CALMAX)  /*!< Memory-clock period outside the range of DLL master (max delay values used) */
783 /**
784   * @}
785   */
786 
787 /**
788   * @}
789   */
790 
791 /* Exported macros -----------------------------------------------------------*/
792 /** @defgroup XSPI_Exported_Macros XSPI Exported Macros
793   * @{
794   */
795 /** @brief Reset XSPI handle state.
796   * @param  __HANDLE__ specifies the XSPI Handle.
797   * @retval None
798   */
799 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
800 #define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
801                                                                   (__HANDLE__)->State = HAL_XSPI_STATE_RESET; \
802                                                                   (__HANDLE__)->MspInitCallback = NULL;       \
803                                                                   (__HANDLE__)->MspDeInitCallback = NULL;     \
804                                                                } while(0)
805 #else
806 #define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_XSPI_STATE_RESET)
807 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
808 
809 /** @brief  Enable the XSPI peripheral.
810   * @param  __HANDLE__ specifies the XSPI Handle.
811   * @retval None
812   */
813 #define HAL_XSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN)
814 
815 /** @brief  Disable the XSPI peripheral.
816   * @param  __HANDLE__ specifies the XSPI Handle.
817   * @retval None
818   */
819 #define HAL_XSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN)
820 
821 /** @brief  Enable the specified XSPI interrupt.
822   * @param  __HANDLE__ specifies the XSPI Handle.
823   * @param  __INTERRUPT__ specifies the XSPI interrupt source to enable.
824   *          This parameter can be one of the following values:
825   *            @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt
826   *            @arg HAL_XSPI_IT_SM: XSPI Status match interrupt
827   *            @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt
828   *            @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt
829   *            @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt
830   * @retval None
831   */
832 #define HAL_XSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
833 
834 /** @brief  Disable the specified XSPI interrupt.
835   * @param  __HANDLE__ specifies the XSPI Handle.
836   * @param  __INTERRUPT__ specifies the XSPI interrupt source to disable.
837   *          This parameter can be one of the following values:
838   *            @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt
839   *            @arg HAL_XSPI_IT_SM: XSPI Status match interrupt
840   *            @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt
841   *            @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt
842   *            @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt
843   * @retval None
844   */
845 #define HAL_XSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
846 
847 /** @brief  Check whether the specified XSPI interrupt source is enabled or not.
848   * @param  __HANDLE__ specifies the XSPI Handle.
849   * @param  __INTERRUPT__ specifies the XSPI interrupt source to check.
850   *          This parameter can be one of the following values:
851   *            @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt
852   *            @arg HAL_XSPI_IT_SM: XSPI Status match interrupt
853   *            @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt
854   *            @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt
855   *            @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt
856   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
857   */
858 #define HAL_XSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\
859                                                            == (__INTERRUPT__))
860 
861 /**
862   * @brief  Check whether the selected XSPI flag is set or not.
863   * @param  __HANDLE__ specifies the XSPI Handle.
864   * @param  __FLAG__ specifies the XSPI flag to check.
865   *          This parameter can be one of the following values:
866   *            @arg HAL_XSPI_FLAG_BUSY: XSPI Busy flag
867   *            @arg HAL_XSPI_FLAG_TO:   XSPI Timeout flag
868   *            @arg HAL_XSPI_FLAG_SM:   XSPI Status match flag
869   *            @arg HAL_XSPI_FLAG_FT:   XSPI FIFO threshold flag
870   *            @arg HAL_XSPI_FLAG_TC:   XSPI Transfer complete flag
871   *            @arg HAL_XSPI_FLAG_TE:   XSPI Transfer error flag
872   * @retval None
873   */
874 #define HAL_XSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \
875                                                             != 0U) ? SET : RESET)
876 
877 /** @brief  Clears the specified XSPI's flag status.
878   * @param  __HANDLE__ specifies the XSPI Handle.
879   * @param  __FLAG__ specifies the XSPI clear register flag that needs to be set
880   *          This parameter can be one of the following values:
881   *            @arg HAL_XSPI_FLAG_TO:   XSPI Timeout flag
882   *            @arg HAL_XSPI_FLAG_SM:   XSPI Status match flag
883   *            @arg HAL_XSPI_FLAG_TC:   XSPI Transfer complete flag
884   *            @arg HAL_XSPI_FLAG_TE:   XSPI Transfer error flag
885   * @retval None
886   */
887 #define HAL_XSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
888 
889 /**
890   * @}
891   */
892 
893 /* Exported functions --------------------------------------------------------*/
894 /** @addtogroup XSPI_Exported_Functions XSPI Exported Functions
895   * @{
896   */
897 
898 /* Initialization/de-initialization functions  ********************************/
899 /** @addtogroup XSPI_Exported_Functions_Group1 Initialization/de-initialization functions
900   * @{
901   */
902 HAL_StatusTypeDef     HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi);
903 void                  HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi);
904 HAL_StatusTypeDef     HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi);
905 void                  HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi);
906 
907 /**
908   * @}
909   */
910 
911 /* IO operation functions *****************************************************/
912 /** @addtogroup XSPI_Exported_Functions_Group2 Input and Output operation functions
913   * @{
914   */
915 /* XSPI IRQ handler function */
916 void                  HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi);
917 
918 /* XSPI command configuration functions */
919 HAL_StatusTypeDef     HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd,
920                                        uint32_t Timeout);
921 HAL_StatusTypeDef     HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd);
922 HAL_StatusTypeDef     HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg,
923                                            uint32_t Timeout);
924 HAL_StatusTypeDef     HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd,
925                                            uint32_t Timeout);
926 
927 /* XSPI indirect mode functions */
928 HAL_StatusTypeDef     HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout);
929 HAL_StatusTypeDef     HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout);
930 HAL_StatusTypeDef     HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData);
931 HAL_StatusTypeDef     HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData);
932 HAL_StatusTypeDef     HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData);
933 HAL_StatusTypeDef     HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData);
934 
935 /* XSPI status flag polling mode functions */
936 HAL_StatusTypeDef     HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg,
937                                            uint32_t Timeout);
938 HAL_StatusTypeDef     HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg);
939 
940 /* XSPI memory-mapped mode functions */
941 HAL_StatusTypeDef     HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi,  XSPI_MemoryMappedTypeDef *const pCfg);
942 
943 /* Callback functions in non-blocking modes ***********************************/
944 void                  HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi);
945 void                  HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi);
946 void                  HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi);
947 
948 /* XSPI indirect mode Callback functions */
949 void                  HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi);
950 void                  HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi);
951 void                  HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi);
952 void                  HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi);
953 void                  HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi);
954 
955 /* XSPI status flag polling mode functions */
956 void                  HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi);
957 
958 /* XSPI memory-mapped mode functions */
959 void                  HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi);
960 
961 #if defined(USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
962 /* XSPI callback registering/unregistering */
963 HAL_StatusTypeDef     HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID,
964                                                 pXSPI_CallbackTypeDef pCallback);
965 HAL_StatusTypeDef     HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID);
966 #endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
967 
968 /**
969   * @}
970   */
971 
972 /* Peripheral Control and State functions  ************************************/
973 /** @addtogroup XSPI_Exported_Functions_Group3 Peripheral Control and State functions
974   * @{
975   */
976 HAL_StatusTypeDef     HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi);
977 HAL_StatusTypeDef     HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi);
978 HAL_StatusTypeDef     HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold);
979 uint32_t              HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi);
980 HAL_StatusTypeDef     HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type);
981 HAL_StatusTypeDef     HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size);
982 HAL_StatusTypeDef     HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler);
983 HAL_StatusTypeDef     HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout);
984 uint32_t              HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi);
985 uint32_t              HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi);
986 
987 /**
988   * @}
989   */
990 
991 /* XSPI IO Manager configuration function  ************************************/
992 /** @addtogroup XSPI_Exported_Functions_Group4  IO Manager configuration function
993   * @{
994   */
995 HAL_StatusTypeDef     HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout);
996 
997 /**
998   * @}
999   */
1000 
1001 /* XSPI high-speed interface and calibration functions  ***********************/
1002 /** @addtogroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions
1003   * @{
1004   */
1005 HAL_StatusTypeDef     HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg);
1006 HAL_StatusTypeDef     HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg);
1007 
1008 /**
1009   * @}
1010   */
1011 
1012 /**
1013   * @}
1014   */
1015 /* End of exported functions -------------------------------------------------*/
1016 
1017 /* Private macros ------------------------------------------------------------*/
1018 /**
1019   @cond 0
1020   */
1021 #define IS_XSPI_FIFO_THRESHOLD_BYTE(THRESHOLD)    (((THRESHOLD) >= 1U) &&\
1022                                                    ((THRESHOLD) <= ((XSPI_CR_FTHRES >> XSPI_CR_FTHRES_Pos)+1U)))
1023 #define IS_XSPI_MEMORY_MODE(MODE)                 (((MODE) == HAL_XSPI_SINGLE_MEM) || \
1024                                                    ((MODE) == HAL_XSPI_DUAL_MEM))
1025 
1026 #define IS_XSPI_MEMORY_TYPE(TYPE)                 (((TYPE) == HAL_XSPI_MEMTYPE_MICRON)       || \
1027                                                    ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX)     || \
1028                                                    ((TYPE) == HAL_XSPI_MEMTYPE_APMEM)     || \
1029                                                    ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \
1030                                                    ((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS)     || \
1031                                                    ((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS))
1032 
1033 #define IS_XSPI_MEMORY_SIZE(SIZE)                 (((SIZE) == HAL_XSPI_SIZE_16B)      || \
1034                                                    ((SIZE) == HAL_XSPI_SIZE_32B)      || \
1035                                                    ((SIZE) == HAL_XSPI_SIZE_64B)      || \
1036                                                    ((SIZE) == HAL_XSPI_SIZE_128B)     || \
1037                                                    ((SIZE) == HAL_XSPI_SIZE_256B)     || \
1038                                                    ((SIZE) == HAL_XSPI_SIZE_512B)     || \
1039                                                    ((SIZE) == HAL_XSPI_SIZE_1KB)      || \
1040                                                    ((SIZE) == HAL_XSPI_SIZE_2KB)      || \
1041                                                    ((SIZE) == HAL_XSPI_SIZE_4KB)      || \
1042                                                    ((SIZE) == HAL_XSPI_SIZE_8KB)      || \
1043                                                    ((SIZE) == HAL_XSPI_SIZE_16KB)     || \
1044                                                    ((SIZE) == HAL_XSPI_SIZE_32KB)     || \
1045                                                    ((SIZE) == HAL_XSPI_SIZE_64KB)     || \
1046                                                    ((SIZE) == HAL_XSPI_SIZE_128KB)    || \
1047                                                    ((SIZE) == HAL_XSPI_SIZE_256KB)    || \
1048                                                    ((SIZE) == HAL_XSPI_SIZE_512KB)    || \
1049                                                    ((SIZE) == HAL_XSPI_SIZE_1MB)      || \
1050                                                    ((SIZE) == HAL_XSPI_SIZE_2MB)      || \
1051                                                    ((SIZE) == HAL_XSPI_SIZE_4MB)      || \
1052                                                    ((SIZE) == HAL_XSPI_SIZE_8MB)      || \
1053                                                    ((SIZE) == HAL_XSPI_SIZE_16MB)     || \
1054                                                    ((SIZE) == HAL_XSPI_SIZE_32MB)     || \
1055                                                    ((SIZE) == HAL_XSPI_SIZE_64MB)     || \
1056                                                    ((SIZE) == HAL_XSPI_SIZE_128MB)    || \
1057                                                    ((SIZE) == HAL_XSPI_SIZE_256MB)    || \
1058                                                    ((SIZE) == HAL_XSPI_SIZE_512MB)    || \
1059                                                    ((SIZE) == HAL_XSPI_SIZE_1GB)      || \
1060                                                    ((SIZE) == HAL_XSPI_SIZE_2GB)      || \
1061                                                    ((SIZE) == HAL_XSPI_SIZE_4GB)      || \
1062                                                    ((SIZE) == HAL_XSPI_SIZE_8GB)      || \
1063                                                    ((SIZE) == HAL_XSPI_SIZE_16GB)     || \
1064                                                    ((SIZE) == HAL_XSPI_SIZE_32GB))
1065 
1066 #define IS_XSPI_CS_HIGH_TIME_CYCLE(TIME)          (((TIME) >= 1U) && ((TIME) <= 64U))
1067 
1068 #define IS_XSPI_FREE_RUN_CLK(CLK)                 (((CLK) == HAL_XSPI_FREERUNCLK_DISABLE) || \
1069                                                    ((CLK) == HAL_XSPI_FREERUNCLK_ENABLE))
1070 
1071 #define IS_XSPI_CLOCK_MODE(MODE)                  (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \
1072                                                    ((MODE) == HAL_XSPI_CLOCK_MODE_3))
1073 
1074 #define IS_XSPI_WRAP_SIZE(SIZE)                   (((SIZE) == HAL_XSPI_WRAP_NOT_SUPPORTED) || \
1075                                                    ((SIZE) == HAL_XSPI_WRAP_16_BYTES)      || \
1076                                                    ((SIZE) == HAL_XSPI_WRAP_32_BYTES)      || \
1077                                                    ((SIZE) == HAL_XSPI_WRAP_64_BYTES)      || \
1078                                                    ((SIZE) == HAL_XSPI_WRAP_128_BYTES))
1079 
1080 #define IS_XSPI_CLK_PRESCALER(PRESCALER)          ((PRESCALER) <= 255U)
1081 
1082 #define IS_XSPI_SAMPLE_SHIFTING(CYCLE)            (((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_NONE)      || \
1083                                                    ((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE))
1084 
1085 #define IS_XSPI_DHQC(CYCLE)                       (((CYCLE) == HAL_XSPI_DHQC_DISABLE) || \
1086                                                    ((CYCLE) == HAL_XSPI_DHQC_ENABLE))
1087 
1088 #define IS_XSPI_CS_BOUND(SIZE)                    (((SIZE) == HAL_XSPI_BONDARYOF_NONE)     || \
1089                                                    ((SIZE) == HAL_XSPI_BONDARYOF_16B)      || \
1090                                                    ((SIZE) == HAL_XSPI_BONDARYOF_32B)      || \
1091                                                    ((SIZE) == HAL_XSPI_BONDARYOF_64B)      || \
1092                                                    ((SIZE) == HAL_XSPI_BONDARYOF_128B)     || \
1093                                                    ((SIZE) == HAL_XSPI_BONDARYOF_256B)     || \
1094                                                    ((SIZE) == HAL_XSPI_BONDARYOF_512B)     || \
1095                                                    ((SIZE) == HAL_XSPI_BONDARYOF_1KB)      || \
1096                                                    ((SIZE) == HAL_XSPI_BONDARYOF_2KB)      || \
1097                                                    ((SIZE) == HAL_XSPI_BONDARYOF_4KB)      || \
1098                                                    ((SIZE) == HAL_XSPI_BONDARYOF_8KB)      || \
1099                                                    ((SIZE) == HAL_XSPI_BONDARYOF_16KB)     || \
1100                                                    ((SIZE) == HAL_XSPI_BONDARYOF_32KB)     || \
1101                                                    ((SIZE) == HAL_XSPI_BONDARYOF_64KB)     || \
1102                                                    ((SIZE) == HAL_XSPI_BONDARYOF_128KB)    || \
1103                                                    ((SIZE) == HAL_XSPI_BONDARYOF_256KB)    || \
1104                                                    ((SIZE) == HAL_XSPI_BONDARYOF_512KB)    || \
1105                                                    ((SIZE) == HAL_XSPI_BONDARYOF_1MB)      || \
1106                                                    ((SIZE) == HAL_XSPI_BONDARYOF_2MB)      || \
1107                                                    ((SIZE) == HAL_XSPI_BONDARYOF_4MB)      || \
1108                                                    ((SIZE) == HAL_XSPI_BONDARYOF_8MB)      || \
1109                                                    ((SIZE) == HAL_XSPI_BONDARYOF_16MB)     || \
1110                                                    ((SIZE) == HAL_XSPI_BONDARYOF_32MB)     || \
1111                                                    ((SIZE) == HAL_XSPI_BONDARYOF_64MB)     || \
1112                                                    ((SIZE) == HAL_XSPI_BONDARYOF_128MB)    || \
1113                                                    ((SIZE) == HAL_XSPI_BONDARYOF_256MB)    || \
1114                                                    ((SIZE) == HAL_XSPI_BONDARYOF_512MB)    || \
1115                                                    ((SIZE) == HAL_XSPI_BONDARYOF_1GB)      || \
1116                                                    ((SIZE) == HAL_XSPI_BONDARYOF_2GB)      || \
1117                                                    ((SIZE) == HAL_XSPI_BONDARYOF_4GB)      || \
1118                                                    ((SIZE) == HAL_XSPI_BONDARYOF_8GB)      || \
1119                                                    ((SIZE) == HAL_XSPI_BONDARYOF_16GB))
1120 
1121 
1122 #define IS_XSPI_MAXTRAN(NB_BYTES)                 ((NB_BYTES) <= 255U)
1123 
1124 #define IS_XSPI_CSSEL(CSSEL)                      (((CSSEL) == HAL_XSPI_CSSEL_NCS1) || \
1125                                                    ((CSSEL) == HAL_XSPI_CSSEL_NCS2))
1126 
1127 #define IS_XSPI_OPERATION_TYPE(TYPE)              (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \
1128                                                    ((TYPE) == HAL_XSPI_OPTYPE_READ_CFG)   || \
1129                                                    ((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG)  || \
1130                                                    ((TYPE) == HAL_XSPI_OPTYPE_WRAP_CFG))
1131 
1132 #define IS_XSPI_IO_SELECT(MEMSEL)                 (((MEMSEL) == HAL_XSPI_SELECT_IO_3_0)   || \
1133                                                    ((MEMSEL) == HAL_XSPI_SELECT_IO_7_4)   || \
1134                                                    ((MEMSEL) == HAL_XSPI_SELECT_IO_11_8)  || \
1135                                                    ((MEMSEL) == HAL_XSPI_SELECT_IO_15_12) || \
1136                                                    ((MEMSEL) == HAL_XSPI_SELECT_IO_7_0)   || \
1137                                                    ((MEMSEL) == HAL_XSPI_SELECT_IO_15_8))
1138 
1139 #define IS_XSPI_INSTRUCTION(OPCODE)               ((OPCODE) <= 0xFFFFFFFFU)
1140 
1141 #define IS_XSPI_INSTRUCTION_MODE(MODE)            (((MODE) == HAL_XSPI_INSTRUCTION_NONE)    || \
1142                                                    ((MODE) == HAL_XSPI_INSTRUCTION_1_LINE)  || \
1143                                                    ((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \
1144                                                    ((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \
1145                                                    ((MODE) == HAL_XSPI_INSTRUCTION_8_LINES))
1146 
1147 #define IS_XSPI_INSTRUCTION_WIDTH(WIDTH)          (((WIDTH) == HAL_XSPI_INSTRUCTION_8_BITS)  || \
1148                                                    ((WIDTH) == HAL_XSPI_INSTRUCTION_16_BITS) || \
1149                                                    ((WIDTH) == HAL_XSPI_INSTRUCTION_24_BITS) || \
1150                                                    ((WIDTH) == HAL_XSPI_INSTRUCTION_32_BITS))
1151 
1152 #define IS_XSPI_INSTRUCTION_DTR_MODE(MODE)        (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \
1153                                                    ((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE))
1154 
1155 #define IS_XSPI_ADDRESS_MODE(MODE)                (((MODE) == HAL_XSPI_ADDRESS_NONE)    || \
1156                                                    ((MODE) == HAL_XSPI_ADDRESS_1_LINE)  || \
1157                                                    ((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \
1158                                                    ((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \
1159                                                    ((MODE) == HAL_XSPI_ADDRESS_8_LINES))
1160 
1161 #define IS_XSPI_ADDRESS_WIDTH(WIDTH)              (((WIDTH) == HAL_XSPI_ADDRESS_8_BITS)  || \
1162                                                    ((WIDTH) == HAL_XSPI_ADDRESS_16_BITS) || \
1163                                                    ((WIDTH) == HAL_XSPI_ADDRESS_24_BITS) || \
1164                                                    ((WIDTH) == HAL_XSPI_ADDRESS_32_BITS))
1165 
1166 #define IS_XSPI_ADDRESS_DTR_MODE(MODE)            (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \
1167                                                    ((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE))
1168 
1169 #define IS_XSPI_ALT_BYTES_MODE(MODE)              (((MODE) == HAL_XSPI_ALT_BYTES_NONE)    || \
1170                                                    ((MODE) == HAL_XSPI_ALT_BYTES_1_LINE)  || \
1171                                                    ((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \
1172                                                    ((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \
1173                                                    ((MODE) == HAL_XSPI_ALT_BYTES_8_LINES))
1174 
1175 #define IS_XSPI_ALT_BYTES_WIDTH(WIDTH)            (((WIDTH) == HAL_XSPI_ALT_BYTES_8_BITS)  || \
1176                                                    ((WIDTH) == HAL_XSPI_ALT_BYTES_16_BITS) || \
1177                                                    ((WIDTH) == HAL_XSPI_ALT_BYTES_24_BITS) || \
1178                                                    ((WIDTH) == HAL_XSPI_ALT_BYTES_32_BITS))
1179 
1180 #define IS_XSPI_ALT_BYTES_DTR_MODE(MODE)          (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \
1181                                                    ((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE))
1182 
1183 #define IS_XSPI_DATA_MODE(TYPE,MODE)              (((TYPE) == (HAL_XSPI_MEMTYPE_HYPERBUS)) ? \
1184                                                    (((MODE) == HAL_XSPI_DATA_NONE)    || \
1185                                                     ((MODE) == HAL_XSPI_DATA_8_LINES) || \
1186                                                     ((MODE) == HAL_XSPI_DATA_16_LINES)): \
1187                                                    (((MODE) == HAL_XSPI_DATA_NONE)    || \
1188                                                     ((MODE) == HAL_XSPI_DATA_1_LINE)  || \
1189                                                     ((MODE) == HAL_XSPI_DATA_2_LINES) || \
1190                                                     ((MODE) == HAL_XSPI_DATA_4_LINES) || \
1191                                                     ((MODE) == HAL_XSPI_DATA_8_LINES) || \
1192                                                     ((MODE) == HAL_XSPI_DATA_16_LINES)))
1193 #define IS_XSPI_DATA_LENGTH(NUMBER)               ((NUMBER) >= 1U)
1194 
1195 #define IS_XSPI_DATA_DTR_MODE(MODE)               (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \
1196                                                    ((MODE) == HAL_XSPI_DATA_DTR_ENABLE))
1197 
1198 #define IS_XSPI_DUMMY_CYCLES(NUMBER)              ((NUMBER) <= 31U)
1199 
1200 #define IS_XSPI_DQS_MODE(MODE)                    (((MODE) == HAL_XSPI_DQS_DISABLE) || \
1201                                                    ((MODE) == HAL_XSPI_DQS_ENABLE))
1202 
1203 #define IS_XSPI_RW_RECOVERY_TIME_CYCLE(CYCLE)     ((CYCLE) <= 255U)
1204 
1205 #define IS_XSPI_ACCESS_TIME_CYCLE(CYCLE)          ((CYCLE) <= 255U)
1206 
1207 #define IS_XSPI_WRITE_ZERO_LATENCY(MODE)          (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \
1208                                                    ((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE))
1209 
1210 #define IS_XSPI_LATENCY_MODE(MODE)                (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \
1211                                                    ((MODE) == HAL_XSPI_FIXED_LATENCY))
1212 
1213 #define IS_XSPI_ADDRESS_SPACE(SPACE)              (((SPACE) == HAL_XSPI_MEMORY_ADDRESS_SPACE) || \
1214                                                    ((SPACE) == HAL_XSPI_REGISTER_ADDRESS_SPACE))
1215 
1216 #define IS_XSPI_MATCH_MODE(MODE)                  (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \
1217                                                    ((MODE) == HAL_XSPI_MATCH_MODE_OR))
1218 
1219 #define IS_XSPI_AUTOMATIC_STOP(MODE)              (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \
1220                                                    ((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE))
1221 
1222 #define IS_XSPI_INTERVAL(INTERVAL)                ((INTERVAL) <= 0xFFFFU)
1223 
1224 #define IS_XSPI_STATUS_BYTES_SIZE(SIZE)           (((SIZE) >= 1U) && ((SIZE) <= 4U))
1225 
1226 #define IS_XSPI_TIMEOUT_ACTIVATION(MODE)          (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \
1227                                                    ((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE))
1228 
1229 #define IS_XSPI_TIMEOUT_PERIOD(PERIOD)            ((PERIOD) <= 0xFFFFU)
1230 
1231 #define IS_XSPIM_IO_PORT(PORT)                    (((PORT) == HAL_XSPIM_IOPORT_1)   || \
1232                                                    ((PORT) == HAL_XSPIM_IOPORT_2))
1233 
1234 #define IS_XSPIM_NCS_OVR(PORT)                    (((PORT) == HAL_XSPI_CSSEL_OVR_DISABLED) || \
1235                                                    ((PORT) == HAL_XSPI_CSSEL_OVR_NCS1)     || \
1236                                                    ((PORT) == HAL_XSPI_CSSEL_OVR_NCS2))
1237 
1238 #define IS_XSPIM_REQ2ACKTIME(TIME)                (((TIME) >= 1U) && ((TIME) <= 256U))
1239 
1240 #define IS_XSPI_DELAY_TYPE(TYPE)                  (((TYPE) == HAL_XSPI_CAL_FULL_CYCLE_DELAY)   || \
1241                                                    ((TYPE) == HAL_XSPI_CAL_FEEDBACK_CLK_DELAY) || \
1242                                                    ((TYPE) == HAL_XSPI_CAL_DATA_OUTPUT_DELAY)  || \
1243                                                    ((TYPE) == HAL_XSPI_CAL_DQS_INPUT_DELAY))
1244 
1245 #define IS_XSPI_FINECAL_VALUE(VALUE)              ((VALUE) <= 0x7FU)
1246 
1247 #define IS_XSPI_COARSECAL_VALUE(VALUE)            ((VALUE) <= 0x1FU)
1248 
1249 /**
1250   @endcond
1251   */
1252 
1253 /* End of private macros -----------------------------------------------------*/
1254 
1255 /**
1256   * @}
1257   */
1258 
1259 /**
1260   * @}
1261   */
1262 
1263 #endif /* XSPI || XSPI1 || XSPI2 */
1264 
1265 #ifdef __cplusplus
1266 }
1267 #endif
1268 
1269 #endif /* STM32H7RSxx_HAL_XSPI_H */
1270