1 /**
2   ******************************************************************************
3   * @file    stm32u5g9xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32U5G9xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2023 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 #ifndef STM32U5G9xx_H
26 #define STM32U5G9xx_H
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 /** @addtogroup ST
33   * @{
34   */
35 
36 
37 /** @addtogroup STM32U5G9xx
38   * @{
39   */
40 
41 
42 /** @addtogroup Configuration_of_CMSIS
43   * @{
44   */
45 
46 
47 /* =========================================================================================================================== */
48 /* ================                                Interrupt Number Definition                                ================ */
49 /* =========================================================================================================================== */
50 
51 typedef enum
52 {
53 /* =======================================  ARM Cortex-M33 Specific Interrupt Numbers  ======================================= */
54   Reset_IRQn                = -15,    /*!< -15 Reset Vector, invoked on Power up and warm reset              */
55   NonMaskableInt_IRQn       = -14,    /*!< -14 Non maskable Interrupt, cannot be stopped or preempted        */
56   HardFault_IRQn            = -13,    /*!< -13 Hard Fault, all classes of Fault                              */
57   MemoryManagement_IRQn     = -12,    /*!< -12 Memory Management, MPU mismatch, including Access Violation
58                                                and No Match                                                  */
59   BusFault_IRQn             = -11,    /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
60                                                related Fault                                                 */
61   UsageFault_IRQn           = -10,    /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
62   SecureFault_IRQn          =  -9,    /*!< -9  Secure Fault                                                  */
63   SVCall_IRQn               =  -5,    /*!< -5  System Service Call via SVC instruction                       */
64   DebugMonitor_IRQn         =  -4,    /*!< -4  Debug Monitor                                                 */
65   PendSV_IRQn               =  -2,    /*!< -2  Pendable request for system service                           */
66   SysTick_IRQn              =  -1,    /*!< -1  System Tick Timer                                             */
67 
68 /* ===========================================  STM32U5G9xx Specific Interrupt Numbers  ================================= */
69   WWDG_IRQn                 = 0,      /*!< Window WatchDog interrupt                                         */
70   PVD_PVM_IRQn              = 1,      /*!< PVD/PVM through EXTI Line detection Interrupt                     */
71   RTC_IRQn                  = 2,      /*!< RTC non-secure interrupt                                          */
72   RTC_S_IRQn                = 3,      /*!< RTC secure interrupt                                              */
73   TAMP_IRQn                 = 4,      /*!< Tamper global interrupt                                           */
74   RAMCFG_IRQn               = 5,      /*!< RAMCFG global interrupt                                           */
75   FLASH_IRQn                = 6,      /*!< FLASH non-secure global interrupt                                 */
76   FLASH_S_IRQn              = 7,      /*!< FLASH secure global interrupt                                     */
77   GTZC_IRQn                 = 8,      /*!< Global TrustZone Controller interrupt                             */
78   RCC_IRQn                  = 9,      /*!< RCC non secure global interrupt                                   */
79   RCC_S_IRQn                = 10,     /*!< RCC secure global interrupt                                       */
80   EXTI0_IRQn                = 11,     /*!< EXTI Line0 interrupt                                              */
81   EXTI1_IRQn                = 12,     /*!< EXTI Line1 interrupt                                              */
82   EXTI2_IRQn                = 13,     /*!< EXTI Line2 interrupt                                              */
83   EXTI3_IRQn                = 14,     /*!< EXTI Line3 interrupt                                              */
84   EXTI4_IRQn                = 15,     /*!< EXTI Line4 interrupt                                              */
85   EXTI5_IRQn                = 16,     /*!< EXTI Line5 interrupt                                              */
86   EXTI6_IRQn                = 17,     /*!< EXTI Line6 interrupt                                              */
87   EXTI7_IRQn                = 18,     /*!< EXTI Line7 interrupt                                              */
88   EXTI8_IRQn                = 19,     /*!< EXTI Line8 interrupt                                              */
89   EXTI9_IRQn                = 20,     /*!< EXTI Line9 interrupt                                              */
90   EXTI10_IRQn               = 21,     /*!< EXTI Line10 interrupt                                             */
91   EXTI11_IRQn               = 22,     /*!< EXTI Line11 interrupt                                             */
92   EXTI12_IRQn               = 23,     /*!< EXTI Line12 interrupt                                             */
93   EXTI13_IRQn               = 24,     /*!< EXTI Line13 interrupt                                             */
94   EXTI14_IRQn               = 25,     /*!< EXTI Line14 interrupt                                             */
95   EXTI15_IRQn               = 26,     /*!< EXTI Line15 interrupt                                             */
96   IWDG_IRQn                 = 27,     /*!< IWDG global interrupt                                             */
97   SAES_IRQn                 = 28,     /*!< Secure AES global interrupt                                       */
98   GPDMA1_Channel0_IRQn      = 29,     /*!< GPDMA1 Channel 0 global interrupt                                 */
99   GPDMA1_Channel1_IRQn      = 30,     /*!< GPDMA1 Channel 1 global interrupt                                 */
100   GPDMA1_Channel2_IRQn      = 31,     /*!< GPDMA1 Channel 2 global interrupt                                 */
101   GPDMA1_Channel3_IRQn      = 32,     /*!< GPDMA1 Channel 3 global interrupt                                 */
102   GPDMA1_Channel4_IRQn      = 33,     /*!< GPDMA1 Channel 4 global interrupt                                 */
103   GPDMA1_Channel5_IRQn      = 34,     /*!< GPDMA1 Channel 5 global interrupt                                 */
104   GPDMA1_Channel6_IRQn      = 35,     /*!< GPDMA1 Channel 6 global interrupt                                 */
105   GPDMA1_Channel7_IRQn      = 36,     /*!< GPDMA1 Channel 7 global interrupt                                 */
106   ADC1_2_IRQn               = 37,     /*!< ADC1_2 global interrupt                                           */
107   DAC1_IRQn                 = 38,     /*!< DAC1 global interrupt                                             */
108   FDCAN1_IT0_IRQn           = 39,     /*!< FDCAN1 interrupt 0                                                */
109   FDCAN1_IT1_IRQn           = 40,     /*!< FDCAN1 interrupt 1                                                */
110   TIM1_BRK_IRQn             = 41,     /*!< TIM1 Break interrupt                                              */
111   TIM1_UP_IRQn              = 42,     /*!< TIM1 Update interrupt                                             */
112   TIM1_TRG_COM_IRQn         = 43,     /*!< TIM1 Trigger and Commutation interrupt                            */
113   TIM1_CC_IRQn              = 44,     /*!< TIM1 Capture Compare interrupt                                    */
114   TIM2_IRQn                 = 45,     /*!< TIM2 global interrupt                                             */
115   TIM3_IRQn                 = 46,     /*!< TIM3 global interrupt                                             */
116   TIM4_IRQn                 = 47,     /*!< TIM4 global interrupt                                             */
117   TIM5_IRQn                 = 48,     /*!< TIM5 global interrupt                                             */
118   TIM6_IRQn                 = 49,     /*!< TIM6 global interrupt                                             */
119   TIM7_IRQn                 = 50,     /*!< TIM7 global interrupt                                             */
120   TIM8_BRK_IRQn             = 51,     /*!< TIM8 Break interrupt                                              */
121   TIM8_UP_IRQn              = 52,     /*!< TIM8 Update interrupt                                             */
122   TIM8_TRG_COM_IRQn         = 53,     /*!< TIM8 Trigger and Commutation interrupt                            */
123   TIM8_CC_IRQn              = 54,     /*!< TIM8 Capture Compare interrupt                                    */
124   I2C1_EV_IRQn              = 55,     /*!< I2C1 Event interrupt                                              */
125   I2C1_ER_IRQn              = 56,     /*!< I2C1 Error interrupt                                              */
126   I2C2_EV_IRQn              = 57,     /*!< I2C2 Event interrupt                                              */
127   I2C2_ER_IRQn              = 58,     /*!< I2C2 Error interrupt                                              */
128   SPI1_IRQn                 = 59,     /*!< SPI1 global interrupt                                             */
129   SPI2_IRQn                 = 60,     /*!< SPI2 global interrupt                                             */
130   USART1_IRQn               = 61,     /*!< USART1 global interrupt                                           */
131   USART2_IRQn               = 62,     /*!< USART2 global interrupt                                           */
132   USART3_IRQn               = 63,     /*!< USART3 global interrupt                                           */
133   UART4_IRQn                = 64,     /*!< UART4 global interrupt                                            */
134   UART5_IRQn                = 65,     /*!< UART5 global interrupt                                            */
135   LPUART1_IRQn              = 66,     /*!< LPUART1 global interrupt                                          */
136   LPTIM1_IRQn               = 67,     /*!< LPTIM1 global interrupt                                           */
137   LPTIM2_IRQn               = 68,     /*!< LPTIM2 global interrupt                                           */
138   TIM15_IRQn                = 69,     /*!< TIM15 global interrupt                                            */
139   TIM16_IRQn                = 70,     /*!< TIM16 global interrupt                                            */
140   TIM17_IRQn                = 71,     /*!< TIM17 global interrupt                                            */
141   COMP_IRQn                 = 72,     /*!< COMP1 and COMP2 through EXTI Lines interrupts                     */
142   OTG_HS_IRQn               = 73,     /*!< USB OTG HS global interrupt                                       */
143   CRS_IRQn                  = 74,     /*!< CRS global interrupt                                              */
144   FMC_IRQn                  = 75,     /*!< FSMC global interrupt                                             */
145   OCTOSPI1_IRQn             = 76,     /*!< OctoSPI1 global interrupt                                         */
146   PWR_S3WU_IRQn             = 77,     /*!< PWR wake up from Stop3 interrupt                                  */
147   SDMMC1_IRQn               = 78,     /*!< SDMMC1 global interrupt                                           */
148   SDMMC2_IRQn               = 79,     /*!< SDMMC2 global interrupt                                           */
149   GPDMA1_Channel8_IRQn      = 80,     /*!< GPDMA1 Channel 8 global interrupt                                 */
150   GPDMA1_Channel9_IRQn      = 81,     /*!< GPDMA1 Channel 9 global interrupt                                 */
151   GPDMA1_Channel10_IRQn     = 82,     /*!< GPDMA1 Channel 10 global interrupt                                */
152   GPDMA1_Channel11_IRQn     = 83,     /*!< GPDMA1 Channel 11 global interrupt                                */
153   GPDMA1_Channel12_IRQn     = 84,     /*!< GPDMA1 Channel 12 global interrupt                                */
154   GPDMA1_Channel13_IRQn     = 85,     /*!< GPDMA1 Channel 13 global interrupt                                */
155   GPDMA1_Channel14_IRQn     = 86,     /*!< GPDMA1 Channel 14 global interrupt                                */
156   GPDMA1_Channel15_IRQn     = 87,     /*!< GPDMA1 Channel 15 global interrupt                                */
157   I2C3_EV_IRQn              = 88,     /*!< I2C3 event interrupt                                              */
158   I2C3_ER_IRQn              = 89,     /*!< I2C3 error interrupt                                              */
159   SAI1_IRQn                 = 90,     /*!< Serial Audio Interface 1 global interrupt                         */
160   SAI2_IRQn                 = 91,     /*!< Serial Audio Interface 2 global interrupt                         */
161   TSC_IRQn                  = 92,     /*!< Touch Sense Controller global interrupt                           */
162   AES_IRQn                  = 93,     /*!< AES global interrupt                                              */
163   RNG_IRQn                  = 94,     /*!< RNG global interrupt                                              */
164   FPU_IRQn                  = 95,     /*!< FPU global interrupt                                              */
165   HASH_IRQn                 = 96,     /*!< HASH global interrupt                                             */
166   PKA_IRQn                  = 97,     /*!< PKA global interrupt                                              */
167   LPTIM3_IRQn               = 98,     /*!< LPTIM3 global interrupt                                           */
168   SPI3_IRQn                 = 99,     /*!< SPI3 global interrupt                                             */
169   I2C4_ER_IRQn              = 100,    /*!< I2C4 Error interrupt                                              */
170   I2C4_EV_IRQn              = 101,    /*!< I2C4 Event interrupt                                              */
171   MDF1_FLT0_IRQn            = 102,    /*!< MDF1 Filter 0 global interrupt                                    */
172   MDF1_FLT1_IRQn            = 103,    /*!< MDF1 Filter 1 global interrupt                                    */
173   MDF1_FLT2_IRQn            = 104,    /*!< MDF1 Filter 2 global interrupt                                    */
174   MDF1_FLT3_IRQn            = 105,    /*!< MDF1 Filter 3 global interrupt                                    */
175   UCPD1_IRQn                = 106,    /*!< UCPD1 global interrupt                                            */
176   ICACHE_IRQn               = 107,    /*!< Instruction cache global interrupt                                */
177   OTFDEC1_IRQn              = 108,    /*!< OTFDEC1 global interrupt                                          */
178   OTFDEC2_IRQn              = 109,    /*!< OTFDEC2 global interrupt                                          */
179   LPTIM4_IRQn               = 110,    /*!< LPTIM4 global interrupt                                           */
180   DCACHE1_IRQn              = 111,    /*!< Data cache global interrupt                                       */
181   ADF1_IRQn                 = 112,    /*!< ADF interrupt                                                     */
182   ADC4_IRQn                 = 113,    /*!< ADC4 (12bits) global interrupt                                    */
183   LPDMA1_Channel0_IRQn      = 114,    /*!< LPDMA1 SmartRun Channel 0 global interrupt                        */
184   LPDMA1_Channel1_IRQn      = 115,    /*!< LPDMA1 SmartRun Channel 1 global interrupt                        */
185   LPDMA1_Channel2_IRQn      = 116,    /*!< LPDMA1 SmartRun Channel 2 global interrupt                        */
186   LPDMA1_Channel3_IRQn      = 117,    /*!< LPDMA1 SmartRun Channel 3 global interrupt                        */
187   DMA2D_IRQn                = 118,    /*!< DMA2D global interrupt                                            */
188   DCMI_PSSI_IRQn            = 119,    /*!< DCMI/PSSI global interrupt                                        */
189   OCTOSPI2_IRQn             = 120,    /*!< OCTOSPI2 global interrupt                                         */
190   MDF1_FLT4_IRQn            = 121,    /*!< MDF1 Filter 4 global interrupt                                    */
191   MDF1_FLT5_IRQn            = 122,    /*!< MDF1 Filter 5 global interrupt                                    */
192   CORDIC_IRQn               = 123,    /*!< CORDIC global interrupt                                           */
193   FMAC_IRQn                 = 124,    /*!< FMAC global interrupt                                             */
194   LSECSSD_IRQn              = 125,    /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts                      */
195   USART6_IRQn               = 126,    /*!< USART6 global interrupt                                           */
196   I2C5_ER_IRQn              = 127,    /*!< I2C5 Error interrupt                                              */
197   I2C5_EV_IRQn              = 128,    /*!< I2C5 Event interrupt                                              */
198   I2C6_ER_IRQn              = 129,    /*!< I2C6 Error interrupt                                              */
199   I2C6_EV_IRQn              = 130,    /*!< I2C6 Error interrupt                                              */
200   HSPI1_IRQn                = 131,    /*!< HSPI1 global interrupt                                            */
201   GPU2D_IRQn                = 132,    /*!< GPU2D global interrupt                                            */
202   GPU2D_ER_IRQn             = 133,    /*!< GPU2D Error interrupt                                             */
203   GFXMMU_IRQn               = 134,    /*!< GFXMMU global interrupt                                           */
204   LTDC_IRQn                 = 135,    /*!< LCD-TFT global interrupt                                          */
205   LTDC_ER_IRQn              = 136,    /*!< LCD-TFT Error interrupt                                           */
206   DSI_IRQn                  = 137,    /*!< DSIHOST global interrupt                                          */
207   DCACHE2_IRQn              = 138,    /*!< DCACHE2 Data cache global interrupt                               */
208   GFXTIM_IRQn               = 139,    /*!< GFXTIM global interrupt                                           */
209   JPEG_IRQn                 = 140     /*!< JPEG sync interrupt                                               */
210 } IRQn_Type;
211 
212 /* =========================================================================================================================== */
213 /* ================                           Processor and Core Peripheral Section                           ================ */
214 /* =========================================================================================================================== */
215 
216 /* -------  Start of section using anonymous unions and disabling warnings  ------- */
217 #if   defined (__CC_ARM)
218   #pragma push
219   #pragma anon_unions
220 #elif defined (__ICCARM__)
221   #pragma language=extended
222 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
223   #pragma clang diagnostic push
224   #pragma clang diagnostic ignored "-Wc11-extensions"
225   #pragma clang diagnostic ignored "-Wreserved-id-macro"
226 #elif defined (__GNUC__)
227   /* anonymous unions are enabled by default */
228 #elif defined (__TMS470__)
229   /* anonymous unions are enabled by default */
230 #elif defined (__TASKING__)
231   #pragma warning 586
232 #elif defined (__CSMC__)
233   /* anonymous unions are enabled by default */
234 #else
235   #warning Not supported compiler type
236 #endif
237 
238 /* --------  Configuration of the Cortex-M33 Processor and Core Peripherals  ------ */
239 #define __CM33_REV                0x0000U   /* Core revision r0p1 */
240 #define __SAUREGION_PRESENT       1U        /* SAU regions present */
241 #define __MPU_PRESENT             1U        /* MPU present */
242 #define __VTOR_PRESENT            1U        /* VTOR present */
243 #define __NVIC_PRIO_BITS          4U        /* Number of Bits used for Priority Levels */
244 #define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */
245 #define __FPU_PRESENT             1U        /* FPU present */
246 #define __DSP_PRESENT             1U        /* DSP extension present */
247 
248 /** @} */ /* End of group Configuration_of_CMSIS */
249 
250 #include "core_cm33.h"                       /*!< ARM Cortex-M33 processor and core peripherals */
251 #include "system_stm32u5xx.h"                /*!< STM32U5xx System */
252 
253 
254 /* =========================================================================================================================== */
255 /* ================                            Device Specific Peripheral Section                             ================ */
256 /* =========================================================================================================================== */
257 
258 
259 /** @addtogroup STM32U5xx_peripherals
260   * @{
261   */
262 
263 /**
264   * @brief CRC calculation unit
265   */
266 typedef struct
267 {
268   __IO uint32_t DR;             /*!< CRC Data register,                           Address offset: 0x00 */
269   __IO uint32_t IDR;            /*!< CRC Independent data register,               Address offset: 0x04 */
270   __IO uint32_t CR;             /*!< CRC Control register,                        Address offset: 0x08 */
271        uint32_t RESERVED2;      /*!< Reserved,                                                    0x0C */
272   __IO uint32_t INIT;           /*!< Initial CRC value register,                  Address offset: 0x10 */
273   __IO uint32_t POL;            /*!< CRC polynomial register,                     Address offset: 0x14 */
274        uint32_t RESERVED3[246]; /*!< Reserved,                                                         */
275   __IO uint32_t HWCFGR;         /*!< CRC IP HWCFGR register,                     Address offset: 0x3F0 */
276   __IO uint32_t VERR;           /*!< CRC IP version register,                    Address offset: 0x3F4 */
277   __IO uint32_t PIDR;           /*!< CRC IP type identification register,        Address offset: 0x3F8 */
278   __IO uint32_t SIDR;           /*!< CRC IP map Size ID register,                Address offset: 0x3FC */
279 } CRC_TypeDef;
280 
281 /**
282   * @brief Inter-integrated Circuit Interface
283   */
284 typedef struct
285 {
286   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
287   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
288   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
289   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
290   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
291   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
292   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
293   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
294   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
295   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
296   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
297   __IO uint32_t AUTOCR;
298 } I2C_TypeDef;
299 
300 /**
301   * @brief DAC
302   */
303 typedef struct
304 {
305   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
306   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
307   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
308   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
309   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
310   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
311   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
312   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
313   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
314   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
315   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
316   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
317   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
318   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
319   __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */
320   __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */
321   __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
322   __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
323   __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
324   __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
325   __IO uint32_t RESERVED[1];
326   __IO uint32_t AUTOCR;      /*!< DAC Autonomous mode register,                         Address offset: 0x54 */
327 } DAC_TypeDef;
328 
329 /**
330   * @brief Clock Recovery System
331   */
332 typedef struct
333 {
334 __IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
335 __IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
336 __IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
337 __IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
338 } CRS_TypeDef;
339 
340 /**
341   * @brief AES hardware accelerator
342   */
343 typedef struct
344 {
345   __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
346   __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
347   __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
348   __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
349   __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
350   __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
351   __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
352   __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
353   __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
354   __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
355   __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
356   __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
357   __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
358   __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
359   __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
360   __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
361   __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
362   __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
363   __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
364   __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
365   __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
366   __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
367   __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
368   __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x5C */
369        uint32_t RESERVED1[168];/*!< Reserved,                                   Address offset: 0x60 -- 0x2FC */
370   __IO uint32_t IER;          /*!< AES Interrupt Enable Register,              Address offset: 0x300 */
371   __IO uint32_t ISR;          /*!< AES Interrupt Status Register,              Address offset: 0x304 */
372   __IO uint32_t ICR;          /*!< AES Interrupt Clear Register,               Address offset: 0x308 */
373 } AES_TypeDef;
374 
375 /**
376   * @brief HASH
377   */
378 typedef struct
379 {
380   __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
381   __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
382   __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
383   __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
384   __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
385   __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
386        uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
387   __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
388 } HASH_TypeDef;
389 
390 /**
391   * @brief HASH_DIGEST
392   */
393 typedef struct
394 {
395   __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */
396 } HASH_DIGEST_TypeDef;
397 
398 /**
399   * @brief RNG
400   */
401 typedef struct
402 {
403   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
404   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
405   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
406   __IO uint32_t NSCR;  /*!< RNG noise source control register ,     Address offset: 0x0C */
407   __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
408 } RNG_TypeDef;
409 
410 /**
411   * @brief Debug MCU
412   */
413 typedef struct
414 {
415   __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
416   __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
417   __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
418   __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
419   __IO uint32_t APB2FZR;     /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
420   __IO uint32_t APB3FZR;     /*!< Debug MCU APB3 freeze register,     Address offset: 0x14 */
421        uint32_t RESERVED1[2];/*!< Reserved,                                    0x18 - 0x1C */
422   __IO uint32_t AHB1FZR;     /*!< Debug MCU AHB1 freeze register,     Address offset: 0x20 */
423        uint32_t RESERVED2;   /*!< Reserved,                                           0x24 */
424   __IO uint32_t AHB3FZR;     /*!< Debug MCU AHB3 freeze register,     Address offset: 0x28 */
425 } DBGMCU_TypeDef;
426 
427 /**
428   * @brief DCMI
429   */
430 typedef struct
431 {
432   __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
433   __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
434   __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
435   __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
436   __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
437   __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
438   __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
439   __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
440   __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
441   __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
442   __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
443 } DCMI_TypeDef;
444 
445 /**
446   * @brief DMA Controller
447   */
448 typedef struct
449 {
450   __IO uint32_t SECCFGR;     /*!< DMA secure configuration register,               Address offset: 0x00  */
451   __IO uint32_t PRIVCFGR;    /*!< DMA privileged configuration register,           Address offset: 0x04  */
452   __IO uint32_t RCFGLOCKR;   /*!< DMA lock configuration register,                 Address offset: 0x08  */
453   __IO uint32_t MISR;        /*!< DMA non secure masked interrupt status register, Address offset: 0x0C  */
454   __IO uint32_t SMISR;       /*!< DMA secure masked interrupt status register,     Address offset: 0x10  */
455 } DMA_TypeDef;
456 
457 typedef struct
458 {
459   __IO uint32_t CLBAR;        /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
460        uint32_t RESERVED1[2]; /*!< Reserved 1,                                      Address offset: 0x54 -- 0x58      */
461   __IO uint32_t CFCR;         /*!< DMA channel x flag clear register,               Address offset: 0x5C + (x * 0x80) */
462   __IO uint32_t CSR;          /*!< DMA channel x flag status register,              Address offset: 0x60 + (x * 0x80) */
463   __IO uint32_t CCR;          /*!< DMA channel x control register,                  Address offset: 0x64 + (x * 0x80) */
464        uint32_t RESERVED2[10];/*!< Reserved 2,                                      Address offset: 0x68 -- 0x8C      */
465   __IO uint32_t CTR1;         /*!< DMA channel x transfer register 1,               Address offset: 0x90 + (x * 0x80) */
466   __IO uint32_t CTR2;         /*!< DMA channel x transfer register 2,               Address offset: 0x94 + (x * 0x80) */
467   __IO uint32_t CBR1;         /*!< DMA channel x block register 1,                  Address offset: 0x98 + (x * 0x80) */
468   __IO uint32_t CSAR;         /*!< DMA channel x source address register,           Address offset: 0x9C + (x * 0x80) */
469   __IO uint32_t CDAR;         /*!< DMA channel x destination address register,      Address offset: 0xA0 + (x * 0x80) */
470   __IO uint32_t CTR3;         /*!< DMA channel x transfer register 3,               Address offset: 0xA4 + (x * 0x80) */
471   __IO uint32_t CBR2;         /*!< DMA channel x block register 2,                  Address offset: 0xA8 + (x * 0x80) */
472        uint32_t RESERVED3[8]; /*!< Reserved 3,                                      Address offset: 0xAC -- 0xC8      */
473   __IO uint32_t CLLR;         /*!< DMA channel x linked-list address register,      Address offset: 0xCC + (x * 0x80) */
474 } DMA_Channel_TypeDef;
475 
476 /**
477   * @brief DMA2D Controller
478   */
479 typedef struct
480 {
481   __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
482   __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
483   __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
484   __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
485   __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
486   __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
487   __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
488   __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
489   __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
490   __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
491   __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
492   __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
493   __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
494   __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
495   __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
496   __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
497   __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
498   __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
499   __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
500   __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
501   uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FC */
502   __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FC */
503   __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFC */
504 } DMA2D_TypeDef;
505 
506 /**
507   * @brief DSI Controller
508   */
509 typedef struct
510 {
511   __IO uint32_t VR;             /*!< DSI Host Version Register,                                 Address offset: 0x00      */
512   __IO uint32_t CR;             /*!< DSI Host Control Register,                                 Address offset: 0x04      */
513   __IO uint32_t CCR;            /*!< DSI HOST Clock Control Register,                           Address offset: 0x08      */
514   __IO uint32_t LVCIDR;         /*!< DSI Host LTDC VCID Register,                               Address offset: 0x0C      */
515   __IO uint32_t LCOLCR;         /*!< DSI Host LTDC Color Coding Register,                       Address offset: 0x10      */
516   __IO uint32_t LPCR;           /*!< DSI Host LTDC Polarity Configuration Register,             Address offset: 0x14      */
517   __IO uint32_t LPMCR;          /*!< DSI Host Low-Power Mode Configuration Register,            Address offset: 0x18      */
518   uint32_t      RESERVED0[4];   /*!< Reserved, 0x1C - 0x2B                                                                */
519   __IO uint32_t PCR;            /*!< DSI Host Protocol Configuration Register,                  Address offset: 0x2C      */
520   __IO uint32_t GVCIDR;         /*!< DSI Host Generic VCID Register,                            Address offset: 0x30      */
521   __IO uint32_t MCR;            /*!< DSI Host Mode Configuration Register,                      Address offset: 0x34      */
522   __IO uint32_t VMCR;           /*!< DSI Host Video Mode Configuration Register,                Address offset: 0x38      */
523   __IO uint32_t VPCR;           /*!< DSI Host Video Packet Configuration Register,              Address offset: 0x3C      */
524   __IO uint32_t VCCR;           /*!< DSI Host Video Chunks Configuration Register,              Address offset: 0x40      */
525   __IO uint32_t VNPCR;          /*!< DSI Host Video Null Packet Configuration Register,         Address offset: 0x44      */
526   __IO uint32_t VHSACR;         /*!< DSI Host Video HSA Configuration Register,                 Address offset: 0x48      */
527   __IO uint32_t VHBPCR;         /*!< DSI Host Video HBP Configuration Register,                 Address offset: 0x4C      */
528   __IO uint32_t VLCR;           /*!< DSI Host Video Line Configuration Register,                Address offset: 0x50      */
529   __IO uint32_t VVSACR;         /*!< DSI Host Video VSA Configuration Register,                 Address offset: 0x54      */
530   __IO uint32_t VVBPCR;         /*!< DSI Host Video VBP Configuration Register,                 Address offset: 0x58      */
531   __IO uint32_t VVFPCR;         /*!< DSI Host Video VFP Configuration Register,                 Address offset: 0x5C      */
532   __IO uint32_t VVACR;          /*!< DSI Host Video VA Configuration Register,                  Address offset: 0x60      */
533   __IO uint32_t LCCR;           /*!< DSI Host LTDC Command Configuration Register,              Address offset: 0x64      */
534   __IO uint32_t CMCR;           /*!< DSI Host Command Mode Configuration Register,              Address offset: 0x68      */
535   __IO uint32_t GHCR;           /*!< DSI Host Generic Header Configuration Register,            Address offset: 0x6C      */
536   __IO uint32_t GPDR;           /*!< DSI Host Generic Payload Data Register,                    Address offset: 0x70      */
537   __IO uint32_t GPSR;           /*!< DSI Host Generic Packet Status Register,                   Address offset: 0x74      */
538   __IO uint32_t TCCR[6];        /*!< DSI Host Timeout Counter Configuration Register,           Address offset: 0x78-0x8F */
539   uint32_t      RESERVED1;      /*!< Reserved, 0x90                                                                       */
540   __IO uint32_t CLCR;           /*!< DSI Host Clock Lane Configuration Register,                Address offset: 0x94      */
541   __IO uint32_t CLTCR;          /*!< DSI Host Clock Lane Timer Configuration Register,          Address offset: 0x98      */
542   __IO uint32_t DLTCR;          /*!< DSI Host Data Lane Timer Configuration Register,           Address offset: 0x9C      */
543   __IO uint32_t PCTLR;          /*!< DSI Host PHY Control Register,                             Address offset: 0xA0      */
544   __IO uint32_t PCONFR;         /*!< DSI Host PHY Configuration Register,                       Address offset: 0xA4      */
545   __IO uint32_t PUCR;           /*!< DSI Host PHY ULPS Control Register,                        Address offset: 0xA8      */
546   __IO uint32_t PTTCR;          /*!< DSI Host PHY TX Triggers Configuration Register,           Address offset: 0xAC      */
547   __IO uint32_t PSR;            /*!< DSI Host PHY Status Register,                              Address offset: 0xB0      */
548   uint32_t      RESERVED2[2];   /*!< Reserved, 0xB4 - 0xBB                                                                */
549   __IO uint32_t ISR[2];         /*!< DSI Host Interrupt & Status Register,                      Address offset: 0xBC-0xC3 */
550   __IO uint32_t IER[2];         /*!< DSI Host Interrupt Enable Register,                        Address offset: 0xC4-0xCB */
551   uint32_t      RESERVED3[3];   /*!< Reserved, 0xD0 - 0xD7                                                                */
552   __IO uint32_t FIR[2];         /*!< DSI Host Force Interrupt Register,                         Address offset: 0xD8-0xDF */
553   uint32_t      RESERVED4[5];   /*!< Reserved, 0xE0 - 0xF3                                                                */
554   __IO uint32_t DLTRCR;         /*!< DSI Host Data Lane Timer Read Configuration Register,      Address offset: 0xF4      */
555   uint32_t      RESERVED5[2];   /*!< Reserved, 0xF8 - 0xFF                                                                */
556   __IO uint32_t VSCR;           /*!< DSI Host Video Shadow Control Register,                    Address offset: 0x100     */
557   uint32_t      RESERVED6[2];   /*!< Reserved, 0x104 - 0x10B                                                              */
558   __IO uint32_t LCVCIDR;        /*!< DSI Host LTDC Current VCID Register,                       Address offset: 0x10C     */
559   __IO uint32_t LCCCR;          /*!< DSI Host LTDC Current Color Coding Register,               Address offset: 0x110     */
560   uint32_t      RESERVED7;      /*!< Reserved, 0x114                                                                      */
561   __IO uint32_t LPMCCR;         /*!< DSI Host Low-power Mode Current Configuration Register,    Address offset: 0x118     */
562   uint32_t      RESERVED8[7];   /*!< Reserved, 0x11C - 0x137                                                              */
563   __IO uint32_t VMCCR;          /*!< DSI Host Video Mode Current Configuration Register,        Address offset: 0x138     */
564   __IO uint32_t VPCCR;          /*!< DSI Host Video Packet Current Configuration Register,      Address offset: 0x13C     */
565   __IO uint32_t VCCCR;          /*!< DSI Host Video Chunks Current Configuration Register,      Address offset: 0x140     */
566   __IO uint32_t VNPCCR;         /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144     */
567   __IO uint32_t VHSACCR;        /*!< DSI Host Video HSA Current Configuration Register,         Address offset: 0x148     */
568   __IO uint32_t VHBPCCR;        /*!< DSI Host Video HBP Current Configuration Register,         Address offset: 0x14C     */
569   __IO uint32_t VLCCR;          /*!< DSI Host Video Line Current Configuration Register,        Address offset: 0x150     */
570   __IO uint32_t VVSACCR;        /*!< DSI Host Video VSA Current Configuration Register,         Address offset: 0x154     */
571   __IO uint32_t VVBPCCR;        /*!< DSI Host Video VBP Current Configuration Register,         Address offset: 0x158     */
572   __IO uint32_t VVFPCCR;        /*!< DSI Host Video VFP Current Configuration Register,         Address offset: 0x15C     */
573   __IO uint32_t VVACCR;         /*!< DSI Host Video VA Current Configuration Register,          Address offset: 0x160     */
574   uint32_t      RESERVED9;      /*!< Reserved, 0x164                                                                      */
575   __IO uint32_t FBSR;           /*!< DSI Host FIFO and Buffer Status Register,                  Address offset: 0x168     */
576   uint32_t      RESERVED10[165];/*!< Reserved, 0x16C - 0x3FF                                                              */
577   __IO uint32_t WCFGR;          /*!< DSI Wrapper Configuration Register,                        Address offset: 0x400     */
578   __IO uint32_t WCR;            /*!< DSI Wrapper Control Register,                              Address offset: 0x404     */
579   __IO uint32_t WIER;           /*!< DSI Wrapper Interrupt Enable Register,                     Address offset: 0x408     */
580   __IO uint32_t WISR;           /*!< DSI Wrapper Interrupt and Status Register,                 Address offset: 0x40C     */
581   __IO uint32_t WIFCR;          /*!< DSI Wrapper Interrupt Flag Clear Register,                 Address offset: 0x410     */
582   uint32_t      RESERVED11;     /*!< Reserved, 0x414                                                                      */
583   __IO uint32_t WPCR[1];        /*!< DSI Wrapper PHY Configuration Register 0,                  Address offset: 0x418     */
584   uint32_t      RESERVED12[5];  /*!< Reserved, 0x41C - 0x42F                                                              */
585   __IO uint32_t WRPCR;          /*!< DSI Wrapper Regulator and PLL Control Register,            Address offset: 0x430     */
586   uint32_t      WPTR;           /*!< DSI Wrapper PLL tuning register,                           Address offset: 0x434     */
587   uint32_t      RESERVED13[244];/*!< Reserved, 0x43C - 0x804                                                              */
588   __IO uint32_t BCFGR;          /*!< DSI Bias Configuration Register,                           Address offset: 0x808     */
589   uint32_t      RESERVED14[254];/*!< Reserved, 0x80C - 0xC00                                                              */
590   __IO uint32_t DPCBCR;         /*!< D-PHY clock band control register,                         Address offset: 0xC04     */
591   uint32_t      RESERVED15[11]; /*!< Reserved, 0xC08 - 0xC30                                                              */
592   __IO uint32_t DPCSRCR;        /*!< D-PHY clock slew rate control register,                    Address offset: 0xC34     */
593    uint32_t     RESERVED16[9];  /*!< Reserved, 0xC38 - 0xC58                                                              */
594   __IO uint32_t DPDL0HSOCR;     /*!< D-PHY data Lane 0 HS offset control register,              Address offset: 0x0C5C    */
595   __IO uint32_t DPDL0LPXOCR;    /*!< D-PHY data Lane 0 HS LPX offset control register,          Address offset: 0x0C60    */
596   uint32_t      RESERVED17[3];  /*!< Reserved, 0xC64-0xC6C                                                                */
597   __IO uint32_t DPDL0BCR;       /*!< D-PHY data Lane0 band control register,                    Address offset: 0x0C70    */
598   uint32_t      RESERVED18[11]; /*!< Reserved, 0xC74 - 0xC9C                                                              */
599   __IO uint32_t DPDL0SRCR;      /*!< D-PHY data Lane0 slew rate control register,               Address offset: 0x0CA0    */
600   uint32_t      RESERVED19[20]; /*!< Reserved, 0xCA4 - 0xD04                                                              */
601  __IO uint32_t  DPDL1HSOCR;     /*!< D-PHY data Lane 1 HS offset control register,              Address offset: 0x0CF4    */
602   __IO uint32_t DPDL1LPXOCR;    /*!< D-PHY data Lane 1 HS LPX offset control register,          Address offset: 0x0CF8    */
603   uint32_t      RESERVED20[3];  /*!< Reserved, 0xCF8 - 0xD04                                                              */
604   __IO uint32_t DPDL1BCR;       /*!< D-PHY data Lane1 band control register,                    Address offset: 0x0D08    */
605   uint32_t      RESERVED21[11]; /*!< Reserved, 0xD0C - 0xD34                                                              */
606   __IO uint32_t DPDL1SRCR;      /*!< D-PHY data Lane1 slew rate control register,               Address Offset: 0x0D38    */
607 } DSI_TypeDef;
608 
609 /**
610   * @brief Asynch Interrupt/Event Controller (EXTI)
611   */
612 typedef struct
613 {
614   __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
615   __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
616   __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
617   __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
618   __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
619   __IO uint32_t SECCFGR1;       /*!< EXTI Security Configuration Register 1,          Address offset:   0x14 */
620   __IO uint32_t PRIVCFGR1;      /*!< EXTI Privilege Configuration Register 1,         Address offset:   0x18 */
621        uint32_t RESERVED1[17];  /*!< Reserved 1,                                                0x1C -- 0x5C */
622   __IO uint32_t EXTICR[4];      /*!< EXIT External Interrupt Configuration Register,            0x60 -- 0x6C */
623   __IO uint32_t LOCKR;          /*!< EXTI Lock Register,                              Address offset:   0x70 */
624        uint32_t RESERVED2[3];   /*!< Reserved 2,                                                0x74 -- 0x7C */
625   __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
626   __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
627 } EXTI_TypeDef;
628 
629 /**
630   * @brief FLASH Registers
631   */
632 typedef struct
633 {
634   __IO uint32_t ACR;              /*!< FLASH access control register,                  Address offset: 0x00 */
635        uint32_t RESERVED1;        /*!< Reserved1,                                      Address offset: 0x04 */
636   __IO uint32_t NSKEYR;           /*!< FLASH non-secure key register,                  Address offset: 0x08 */
637   __IO uint32_t SECKEYR;          /*!< FLASH secure key register,                      Address offset: 0x0C */
638   __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                      Address offset: 0x10 */
639   __IO uint32_t RESERVED2;        /*!< Reserved2,                                      Address offset: 0x14 */
640   __IO uint32_t PDKEY1R;          /*!< FLASH Bank 1 power-down key register,           Address offset: 0x18 */
641   __IO uint32_t PDKEY2R;          /*!< FLASH Bank 2 power-down key register,           Address offset: 0x1C */
642   __IO uint32_t NSSR;             /*!< FLASH non-secure status register,               Address offset: 0x20 */
643   __IO uint32_t SECSR;            /*!< FLASH secure status register,                   Address offset: 0x24 */
644   __IO uint32_t NSCR;             /*!< FLASH non-secure control register,              Address offset: 0x28 */
645   __IO uint32_t SECCR;            /*!< FLASH secure control register,                  Address offset: 0x2C */
646   __IO uint32_t ECCR;             /*!< FLASH ECC register,                             Address offset: 0x30 */
647   __IO uint32_t OPSR;             /*!< FLASH OPSR register,                            Address offset: 0x34 */
648        uint32_t RESERVED3[2];     /*!< Reserved3,                                      Address offset: 0x38-0x3C */
649   __IO uint32_t OPTR;             /*!< FLASH option control register,                  Address offset: 0x40 */
650   __IO uint32_t NSBOOTADD0R;      /*!< FLASH non-secure boot address 0 register,       Address offset: 0x44 */
651   __IO uint32_t NSBOOTADD1R;      /*!< FLASH non-secure boot address 1 register,       Address offset: 0x48 */
652   __IO uint32_t SECBOOTADD0R;     /*!< FLASH secure boot address 0 register,           Address offset: 0x4C */
653   __IO uint32_t SECWM1R1;         /*!< FLASH secure watermark1 register 1,             Address offset: 0x50 */
654   __IO uint32_t SECWM1R2;         /*!< FLASH secure watermark1 register 2,             Address offset: 0x54 */
655   __IO uint32_t WRP1AR;           /*!< FLASH WRP1 area A address register,             Address offset: 0x58 */
656   __IO uint32_t WRP1BR;           /*!< FLASH WRP1 area B address register,             Address offset: 0x5C */
657   __IO uint32_t SECWM2R1;         /*!< FLASH secure watermark2 register 1,             Address offset: 0x60 */
658   __IO uint32_t SECWM2R2;         /*!< FLASH secure watermark2 register 2,             Address offset: 0x64 */
659   __IO uint32_t WRP2AR;           /*!< FLASH WRP2 area A address register,             Address offset: 0x68 */
660   __IO uint32_t WRP2BR;           /*!< FLASH WRP2 area B address register,             Address offset: 0x6C */
661   __IO uint32_t OEM1KEYR1;        /*!< FLASH OEM1 key register 1,                      Address offset: 0x70 */
662   __IO uint32_t OEM1KEYR2;        /*!< FLASH OEM1 key register 2,                      Address offset: 0x74 */
663   __IO uint32_t OEM2KEYR1;        /*!< FLASH OEM2 key register 1,                      Address offset: 0x78 */
664   __IO uint32_t OEM2KEYR2;        /*!< FLASH OEM2 key register 2,                      Address offset: 0x7C */
665   __IO uint32_t SECBB1R1;         /*!< FLASH secure block-based bank 1 register 1,     Address offset: 0x80 */
666   __IO uint32_t SECBB1R2;         /*!< FLASH secure block-based bank 1 register 2,     Address offset: 0x84 */
667   __IO uint32_t SECBB1R3;         /*!< FLASH secure block-based bank 1 register 3,     Address offset: 0x88 */
668   __IO uint32_t SECBB1R4;         /*!< FLASH secure block-based bank 1 register 4,     Address offset: 0x8C */
669   __IO uint32_t SECBB1R5;         /*!< FLASH secure block-based bank 1 register 5,     Address offset: 0x90 */
670   __IO uint32_t SECBB1R6;         /*!< FLASH secure block-based bank 1 register 6,     Address offset: 0x94 */
671   __IO uint32_t SECBB1R7;         /*!< FLASH secure block-based bank 1 register 7,     Address offset: 0x98 */
672   __IO uint32_t SECBB1R8;         /*!< FLASH secure block-based bank 1 register 8,     Address offset: 0x9C */
673   __IO uint32_t SECBB2R1;         /*!< FLASH secure block-based bank 2 register 1,     Address offset: 0xA0 */
674   __IO uint32_t SECBB2R2;         /*!< FLASH secure block-based bank 2 register 2,     Address offset: 0xA4 */
675   __IO uint32_t SECBB2R3;         /*!< FLASH secure block-based bank 2 register 3,     Address offset: 0xA8 */
676   __IO uint32_t SECBB2R4;         /*!< FLASH secure block-based bank 2 register 4,     Address offset: 0xAC */
677   __IO uint32_t SECBB2R5;         /*!< FLASH secure block-based bank 2 register 5,     Address offset: 0xB0 */
678   __IO uint32_t SECBB2R6;         /*!< FLASH secure block-based bank 2 register 6,     Address offset: 0xB4 */
679   __IO uint32_t SECBB2R7;         /*!< FLASH secure block-based bank 2 register 7,     Address offset: 0xB8 */
680   __IO uint32_t SECBB2R8;         /*!< FLASH secure block-based bank 2 register 8,     Address offset: 0xBC */
681   __IO uint32_t SECHDPCR;         /*!< FLASH secure HDP control register,              Address offset: 0xC0 */
682   __IO uint32_t PRIVCFGR;         /*!< FLASH privilege configuration register,         Address offset: 0xC4 */
683        uint32_t RESERVED6[2];     /*!< Reserved6,                                      Address offset: 0xC8-0xCC */
684   __IO uint32_t PRIVBB1R1;        /*!< FLASH privilege block-based bank 1 register 1,  Address offset: 0xD0 */
685   __IO uint32_t PRIVBB1R2;        /*!< FLASH privilege block-based bank 1 register 2,  Address offset: 0xD4 */
686   __IO uint32_t PRIVBB1R3;        /*!< FLASH privilege block-based bank 1 register 3,  Address offset: 0xD8 */
687   __IO uint32_t PRIVBB1R4;        /*!< FLASH privilege block-based bank 1 register 4,  Address offset: 0xDC */
688   __IO uint32_t PRIVBB1R5;        /*!< FLASH privilege block-based bank 1 register 5,  Address offset: 0xE0 */
689   __IO uint32_t PRIVBB1R6;        /*!< FLASH privilege block-based bank 1 register 6,  Address offset: 0xE4 */
690   __IO uint32_t PRIVBB1R7;        /*!< FLASH privilege block-based bank 1 register 7,  Address offset: 0xE8 */
691   __IO uint32_t PRIVBB1R8;        /*!< FLASH privilege block-based bank 1 register 8,  Address offset: 0xEC */
692   __IO uint32_t PRIVBB2R1;        /*!< FLASH privilege block-based bank 2 register 1,  Address offset: 0xF0 */
693   __IO uint32_t PRIVBB2R2;        /*!< FLASH privilege block-based bank 2 register 2,  Address offset: 0xF4 */
694   __IO uint32_t PRIVBB2R3;        /*!< FLASH privilege block-based bank 2 register 3,  Address offset: 0xF8 */
695   __IO uint32_t PRIVBB2R4;        /*!< FLASH privilege block-based bank 2 register 4,  Address offset: 0xFC */
696   __IO uint32_t PRIVBB2R5;        /*!< FLASH privilege block-based bank 2 register 5,  Address offset: 0x100 */
697   __IO uint32_t PRIVBB2R6;        /*!< FLASH privilege block-based bank 2 register 6,  Address offset: 0x104 */
698   __IO uint32_t PRIVBB2R7;        /*!< FLASH privilege block-based bank 2 register 7,  Address offset: 0x108 */
699   __IO uint32_t PRIVBB2R8;        /*!< FLASH privilege block-based bank 2 register 8,  Address offset: 0x10C */
700 } FLASH_TypeDef;
701 
702 /**
703   * @brief FMAC
704   */
705 typedef struct
706 {
707   __IO uint32_t X1BUFCFG;        /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00          */
708   __IO uint32_t X2BUFCFG;        /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04          */
709   __IO uint32_t YBUFCFG;         /*!< FMAC Y Buffer Configuration register,  Address offset: 0x08          */
710   __IO uint32_t PARAM;           /*!< FMAC Parameter register,               Address offset: 0x0C          */
711   __IO uint32_t CR;              /*!< FMAC Control register,                 Address offset: 0x10          */
712   __IO uint32_t SR;              /*!< FMAC Status register,                  Address offset: 0x14          */
713   __IO uint32_t WDATA;           /*!< FMAC Write Data register,              Address offset: 0x18          */
714   __IO uint32_t RDATA;           /*!< FMAC Read Data register,               Address offset: 0x1C          */
715 } FMAC_TypeDef;
716 
717 /**
718   * @brief GFXMMU registers
719   */
720 typedef struct
721 {
722   __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */
723   __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */
724   __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */
725   __IO uint32_t CCR;             /*!< GFXMMU Cache Control Register,                     Address offset: 0x0C */
726   __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */
727        uint32_t RESERVED1[3];    /*!< Reserved1,                                         Address offset: 0x14 to 0x1C */
728   __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */
729   __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */
730   __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */
731   __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */
732        uint32_t RESERVED2[1008]; /*!< Reserved2,                                         Address offset: 0x30 to 0xFEC */
733   __IO uint32_t HWCFGR;          /*!< GFXMMU hardware configuration register,            Address offset: 0xFF0 */
734   __IO uint32_t VERR;            /*!< GFXMMU version register,                           Address offset: 0xFF4 */
735   __IO uint32_t IPIDR;           /*!< GFXMMU identification register,                    Address offset: 0xFF8 */
736   __IO uint32_t SIDR;            /*!< GFXMMU size identification register,               Address offset: 0xFFC */
737   __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                              Address offset: 0x1000 to 0x2FFC
738                                       For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
739 } GFXMMU_TypeDef;
740 
741 /**
742   * @brief General Purpose I/O
743   */
744 typedef struct
745 {
746   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
747   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
748   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
749   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
750   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
751   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
752   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
753   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
754   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
755   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
756   __IO uint32_t HSLVR;       /*!< GPIO high-speed low voltage register,  Address offset: 0x2C      */
757   __IO uint32_t SECCFGR;     /*!< GPIO secure configuration register,    Address offset: 0x30      */
758 } GPIO_TypeDef;
759 
760 /**
761   * @brief Global TrustZone Controller
762   */
763 typedef struct
764 {
765   __IO uint32_t CR;             /*!< TZSC control register,                                                Address offset: 0x00      */
766        uint32_t RESERVED1[3];   /*!< Reserved1,                                                            Address offset: 0x04-0x0C */
767   __IO uint32_t SECCFGR1;       /*!< TZSC secure configuration register 1,                                 Address offset: 0x10      */
768   __IO uint32_t SECCFGR2;       /*!< TZSC secure configuration register 2,                                 Address offset: 0x14      */
769   __IO uint32_t SECCFGR3;       /*!< TZSC secure configuration register 3,                                 Address offset: 0x18      */
770        uint32_t RESERVED2;      /*!< Reserved2,                                                            Address offset: 0x1C      */
771   __IO uint32_t PRIVCFGR1;      /*!< TZSC privilege configuration register 1,                              Address offset: 0x20      */
772   __IO uint32_t PRIVCFGR2;      /*!< TZSC privilege configuration register 2,                              Address offset: 0x24      */
773   __IO uint32_t PRIVCFGR3;      /*!< TZSC privilege configuration register 3,                              Address offset: 0x28      */
774        uint32_t RESERVED3[5];   /*!< Reserved3,                                                            Address offset: 0x2C-0x3C */
775   __IO uint32_t MPCWM1ACFGR;    /*!< TZSC memory 1 sub-region A watermark configuration register,          Address offset: 0x40      */
776   __IO uint32_t MPCWM1AR;       /*!< TZSC memory 1 sub-region A watermark register,                        Address offset: 0x44      */
777   __IO uint32_t MPCWM1BCFGR;    /*!< TZSC memory 1 sub-region B watermark configuration register,          Address offset: 0x48      */
778   __IO uint32_t MPCWM1BR;       /*!< TZSC memory 1 sub-region B watermark register,                        Address offset: 0x4C      */
779   __IO uint32_t MPCWM2ACFGR;    /*!< TZSC memory 2 sub-region A watermark configuration register,          Address offset: 0x50      */
780   __IO uint32_t MPCWM2AR;       /*!< TZSC memory 2 sub-region A watermark register,                        Address offset: 0x54      */
781   __IO uint32_t MPCWM2BCFGR;    /*!< TZSC memory 2 sub-region B watermark configuration register,          Address offset: 0x58      */
782   __IO uint32_t MPCWM2BR;       /*!< TZSC memory 2 sub-region B watermark register,                        Address offset: 0x5C      */
783   __IO uint32_t MPCWM3ACFGR;    /*!< TZSC memory 3 sub-region A watermark configuration register,          Address offset: 0x60      */
784   __IO uint32_t MPCWM3AR;       /*!< TZSC memory 3 sub-region A watermark register,                        Address offset: 0x64      */
785        uint32_t RESERVED4[2];   /*!< Reserved4,                                                            Address offset: 0x68-0x6C */
786   __IO uint32_t MPCWM4ACFGR;    /*!< TZSC memory 4 sub-region A watermark configuration register,          Address offset: 0x70      */
787   __IO uint32_t MPCWM4AR;       /*!< TZSC memory 4 sub-region A watermark register,                        Address offset: 0x74      */
788        uint32_t RESERVED5[2];   /*!< Reserved5,                                                            Address offset: 0x78-0x7C */
789   __IO uint32_t MPCWM5ACFGR;    /*!< TZSC memory 5 sub-region A watermark configuration register,          Address offset: 0x80      */
790   __IO uint32_t MPCWM5AR;       /*!< TZSC memory 5 sub-region A watermark register,                        Address offset: 0x84      */
791   __IO uint32_t MPCWM5BCFGR;    /*!< TZSC memory 5 sub-region B watermark configuration register,          Address offset: 0x88      */
792   __IO uint32_t MPCWM5BR;       /*!< TZSC memory 5 sub-region B watermark register,                        Address offset: 0x8C      */
793   __IO uint32_t MPCWM6ACFGR;    /*!< TZSC memory 6 sub-region A watermark configuration register,          Address offset: 0x90      */
794   __IO uint32_t MPCWM6AR;       /*!< TZSC memory 6 sub-region A watermark register,                        Address offset: 0x94      */
795   __IO uint32_t MPCWM6BCFGR;    /*!< TZSC memory 6 sub-region B watermark configuration register,          Address offset: 0x98      */
796   __IO uint32_t MPCWM6BR;       /*!< TZSC memory 6 sub-region B watermark register,                        Address offset: 0x9C      */
797 } GTZC_TZSC_TypeDef;
798 
799 typedef struct
800 {
801   __IO uint32_t CR;             /*!< MPCBBx control register,                  Address offset: 0x00        */
802   uint32_t RESERVED1[3];        /*!< Reserved1,                                Address offset: 0x04-0x0C   */
803   __IO uint32_t CFGLOCKR1;      /*!< MPCBBx Configuration lock register 1,     Address offset: 0x10        */
804   __IO uint32_t CFGLOCKR2;      /*!< MPCBBx Configuration lock register 2,     Address offset: 0x14        */
805   uint32_t RESERVED2[58];       /*!< Reserved2,                                Address offset: 0x18-0xFC   */
806   __IO uint32_t SECCFGR[52];    /*!< MPCBBx security configuration registers,  Address offset: 0x100-0x1CC */
807   uint32_t RESERVED3[12];       /*!< Reserved3,                                Address offset: 0x1D0-0x1FC */
808   __IO uint32_t PRIVCFGR[52];   /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */
809 } GTZC_MPCBB_TypeDef;
810 
811 typedef struct
812 {
813   __IO uint32_t IER1;           /*!< TZIC interrupt enable register 1, Address offset: 0x00 */
814   __IO uint32_t IER2;           /*!< TZIC interrupt enable register 2, Address offset: 0x04 */
815   __IO uint32_t IER3;           /*!< TZIC interrupt enable register 3, Address offset: 0x08 */
816   __IO uint32_t IER4;           /*!< TZIC interrupt enable register 4, Address offset: 0x0C */
817   __IO uint32_t SR1;            /*!< TZIC status register 1,           Address offset: 0x10 */
818   __IO uint32_t SR2;            /*!< TZIC status register 2,           Address offset: 0x14 */
819   __IO uint32_t SR3;            /*!< TZIC status register 3,           Address offset: 0x18 */
820   __IO uint32_t SR4;            /*!< TZIC status register 4,           Address offset: 0x1C */
821   __IO uint32_t FCR1;           /*!< TZIC flag clear register 1,       Address offset: 0x20 */
822   __IO uint32_t FCR2;           /*!< TZIC flag clear register 2,       Address offset: 0x24 */
823   __IO uint32_t FCR3;           /*!< TZIC flag clear register 3,       Address offset: 0x28 */
824   __IO uint32_t FCR4;           /*!< TZIC flag clear register 3,       Address offset: 0x2C */
825 } GTZC_TZIC_TypeDef;
826 
827 /**
828   * @brief GFXTIM
829   */
830 typedef struct
831 {
832   __IO uint32_t CR;            /*!< GFXTIM configuration register,                    Address offset: 0x00 */
833   __IO uint32_t CGCR;          /*!< GFXTIM clock generator configuration register,    Address offset: 0x04 */
834   __IO uint32_t TCR;           /*!< GFXTIM timers configuration register,             Address offset: 0x08 */
835   __IO uint32_t TDR;           /*!< GFXTIM timers disable register,                   Address offset: 0x0C */
836   __IO uint32_t EVCR;          /*!< GFXTIM events control register,                   Address offset: 0x10 */
837   __IO uint32_t EVSR;          /*!< GFXTIM events selection register,                 Address offset: 0x14 */
838   uint32_t RESERVED1[2];       /*!< Reserved,                                         Address offset: 0x18-0x1C */
839   __IO uint32_t WDGTCR;        /*!< GFXTIM watchdog timer configuration register,     Address offset: 0x20 */
840   uint32_t RESERVED2[3];       /*!< Reserved,                                         Address offset: 0x24-0x2C */
841   __IO uint32_t ISR;           /*!< GFXTIM interrupt status register,                 Address offset: 0x30 */
842   __IO uint32_t ICR;           /*!< GFXTIM interrupt clear register,                  Address offset: 0x34 */
843   __IO uint32_t IER;           /*!< GFXTIM interrupt enable register,                 Address offset: 0x38 */
844   __IO uint32_t TSR;           /*!< GFXTIM timers status register,                    Address offset: 0x3C */
845   __IO uint32_t LCCRR;         /*!< GFXTIM line clock counter reload register,        Address offset: 0x40 */
846   __IO uint32_t FCCRR;         /*!< GFXTIM frame clock counter reload register,       Address offset: 0x44 */
847   uint32_t RESERVED3[2];       /*!< Reserved,                                         Address offset: 0x48-0x4C */
848   __IO uint32_t ATR;           /*!< GFXTIM absolute time register,                    Address offset: 0x50 */
849   __IO uint32_t AFCR;          /*!< GFXTIM absolute frame counter register,           Address offset: 0x54 */
850   __IO uint32_t ALCR;          /*!< GFXTIM absolute line counter register,            Address offset: 0x58 */
851   uint32_t RESERVED4[1];       /*!< Reserved,                                         Address offset: 0x5C */
852   __IO uint32_t AFCC1R;        /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */
853   uint32_t RESERVED5[3];       /*!< Reserved,                                         Address offset: 0x64-0X6C */
854   __IO uint32_t ALCC1R;        /*!< GFXTIM absolute line counter compare 1 register,  Address offset: 0x70 */
855   __IO uint32_t ALCC2R;        /*!< GFXTIM absolute line counter compare 2 register,  Address offset: 0x74 */
856   uint32_t RESERVED6[2];       /*!< Reserved,                                         Address offset: 0x78-0X7C */
857   __IO uint32_t RFC1R;         /*!< GFXTIM relative frame counter 1 register,         Address offset: 0x80 */
858   __IO uint32_t RFC1RR;        /*!< GFXTIM relative frame counter 1 reload register,  Address offset: 0x84 */
859   __IO uint32_t RFC2R;         /*!< GFXTIM relative frame counter 2 register,         Address offset: 0x88 */
860   __IO uint32_t RFC2RR;        /*!< GFXTIM relative frame counter 2 reload register,  Address offset: 0x8C */
861   uint32_t RESERVED7[4];       /*!< Reserved,                                         Address offset: 0x90-0X9C */
862   __IO uint32_t WDGCR;         /*!< GFXTIM watchdog counter register,                 Address offset: 0xA0 */
863   __IO uint32_t WDGRR;         /*!< GFXTIM watchdog reload register,                  Address offset: 0xA4 */
864   __IO uint32_t WDGPAR;        /*!< GFXTIM watchdog pre-alarm register,               Address offset: 0xA8 */
865   uint32_t RESERVED8[209];     /*!< Reserved,                                         Address offset: 0xAC-0X3EC */
866   __IO uint32_t HWCFGR;        /*!< GFXTIM HW configuration register,                 Address offset: 0x3F0 */
867   __IO uint32_t VERR;          /*!< GFXTIM version register,                          Address offset: 0x3F4 */
868   __IO uint32_t IPIDR;         /*!< GFXTIM identification register,                   Address offset: 0x3F8 */
869   __IO uint32_t SIDR;          /*!< GFXTIM size identification register,              Address offset: 0x3FC */
870 } GFXTIM_TypeDef;
871 
872 /**
873   * @brief JPEG Codec
874   */
875 typedef struct
876 {
877   __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
878   __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
879   __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
880   __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
881   __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
882   __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
883   __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
884   __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
885   uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
886   __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
887   __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
888   __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
889   uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
890   __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
891   __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
892   uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
893   __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
894   __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
895   __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
896   __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
897   __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
898   __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
899   __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
900   __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
901   uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
902   __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
903   __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
904   __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
905   __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
906 
907 } JPEG_TypeDef;
908 
909 /**
910   * @brief LCD-TFT Display Controller
911   */
912 typedef struct
913 {
914   uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
915   __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
916   __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
917   __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
918   __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
919   __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
920   uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
921   __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
922   uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
923   __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
924   uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
925   __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
926   __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
927   __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
928   __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
929   __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
930   __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
931 } LTDC_TypeDef;
932 
933 /**
934   * @brief LCD-TFT Display layer x Controller
935   */
936 
937 typedef struct
938 {
939   __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
940   __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
941   __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
942   __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
943   __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
944   __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
945   __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
946   __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
947   uint32_t      RESERVED0[2];  /*!< Reserved */
948   __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
949   __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
950   __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
951   uint32_t      RESERVED1[3];  /*!< Reserved */
952   __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
953 
954 } LTDC_Layer_TypeDef;
955 
956 /**
957   * @brief Instruction Cache
958   */
959 typedef struct
960 {
961   __IO uint32_t CR;             /*!< ICACHE control register,                Address offset: 0x00 */
962   __IO uint32_t SR;             /*!< ICACHE status register,                 Address offset: 0x04 */
963   __IO uint32_t IER;            /*!< ICACHE interrupt enable register,       Address offset: 0x08 */
964   __IO uint32_t FCR;            /*!< ICACHE Flag clear register,             Address offset: 0x0C */
965   __IO uint32_t HMONR;          /*!< ICACHE hit monitor register,            Address offset: 0x10 */
966   __IO uint32_t MMONR;          /*!< ICACHE miss monitor register,           Address offset: 0x14 */
967        uint32_t RESERVED1[2];   /*!< Reserved,                               Address offset: 0x018-0x01C */
968   __IO uint32_t CRR0;           /*!< ICACHE region 0 configuration register, Address offset: 0x20 */
969   __IO uint32_t CRR1;           /*!< ICACHE region 1 configuration register, Address offset: 0x24 */
970   __IO uint32_t CRR2;           /*!< ICACHE region 2 configuration register, Address offset: 0x28 */
971   __IO uint32_t CRR3;           /*!< ICACHE region 3 configuration register, Address offset: 0x2C */
972 } ICACHE_TypeDef;
973 
974 /**
975   * @brief Data Cache
976   */
977 typedef struct
978 {
979   __IO uint32_t CR;             /*!< DCACHE control register,               Address offset: 0x00 */
980   __IO uint32_t SR;             /*!< DCACHE status register,                Address offset: 0x04 */
981   __IO uint32_t IER;            /*!< DCACHE interrupt enable register,      Address offset: 0x08 */
982   __IO uint32_t FCR;            /*!< DCACHE Flag clear register,            Address offset: 0x0C */
983   __IO uint32_t RHMONR;         /*!< DCACHE Read hit monitor register,      Address offset: 0x10 */
984   __IO uint32_t RMMONR;         /*!< DCACHE Read miss monitor register,     Address offset: 0x14 */
985        uint32_t RESERVED1[2];   /*!< Reserved,                              Address offset: 0x18-0x1C */
986   __IO uint32_t WHMONR;         /*!< DCACHE Write hit monitor register,     Address offset: 0x20 */
987   __IO uint32_t WMMONR;         /*!< DCACHE Write miss monitor register,    Address offset: 0x24 */
988   __IO uint32_t CMDRSADDRR;     /*!< DCACHE Command Start Address register, Address offset: 0x28 */
989   __IO uint32_t CMDREADDRR;     /*!< DCACHE Command End Address register,   Address offset: 0x2C */
990 } DCACHE_TypeDef;
991 
992 /**
993   * @brief PSSI
994   */
995 typedef struct
996 {
997   __IO uint32_t CR;             /*!< PSSI control register,                 Address offset: 0x000 */
998   __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */
999   __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */
1000   __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */
1001   __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */
1002   __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */
1003   __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */
1004   __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */
1005 } PSSI_TypeDef;
1006 
1007 /**
1008   * @brief TIM
1009   */
1010 typedef struct
1011 {
1012   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
1013   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
1014   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
1015   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
1016   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
1017   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
1018   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
1019   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
1020   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
1021   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
1022   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
1023   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
1024   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
1025   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
1026   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
1027   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
1028   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
1029   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
1030   __IO uint32_t CCR5;        /*!< TIM capture/compare register 5,           Address offset: 0x48 */
1031   __IO uint32_t CCR6;        /*!< TIM capture/compare register 6,           Address offset: 0x4C */
1032   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x50 */
1033   __IO uint32_t DTR2;        /*!< TIM deadtime register 2,                  Address offset: 0x54 */
1034   __IO uint32_t ECR;         /*!< TIM encoder control register,             Address offset: 0x58 */
1035   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x5C */
1036   __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
1037   __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
1038   __IO uint32_t OR1 ;        /*!< TIM option register,                      Address offset: 0x68 */
1039        uint32_t RESERVED0[220];/*!< Reserved,                               Address offset: 0x6C */
1040   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x3DC */
1041   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
1042 } TIM_TypeDef;
1043 
1044 /**
1045   * @brief LPTIMER
1046   */
1047 typedef struct
1048 {
1049   __IO uint32_t ISR;            /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
1050   __IO uint32_t ICR;            /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
1051   __IO uint32_t DIER;           /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
1052   __IO uint32_t CFGR;           /*!< LPTIM Configuration register,           Address offset: 0x0C */
1053   __IO uint32_t CR;             /*!< LPTIM Control register,                 Address offset: 0x10 */
1054   __IO uint32_t CCR1;           /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
1055   __IO uint32_t ARR;            /*!< LPTIM Autoreload register,              Address offset: 0x18 */
1056   __IO uint32_t CNT;            /*!< LPTIM Counter register,                 Address offset: 0x1C */
1057   __IO uint32_t RESERVED0;      /*!< Reserved,                               Address offset: 0x20 */
1058   __IO uint32_t CFGR2;          /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
1059   __IO uint32_t RCR;            /*!< LPTIM Repetition register,              Address offset: 0x28 */
1060   __IO uint32_t CCMR1;          /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
1061   __IO uint32_t RESERVED1;      /*!< Reserved,                               Address offset: 0x30 */
1062   __IO uint32_t CCR2;           /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
1063 } LPTIM_TypeDef;
1064 
1065 /**
1066   * @brief Comparator
1067   */
1068 typedef struct
1069 {
1070   __IO uint32_t CSR;            /*!< Comparator control and status register, Address offset: 0x00 */
1071 } COMP_TypeDef;
1072 
1073 typedef struct
1074 {
1075   __IO uint32_t CSR_ODD;        /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */
1076   __IO uint32_t CSR_EVEN;       /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */
1077 } COMP_Common_TypeDef;
1078 
1079 /**
1080   * @brief Operational Amplifier (OPAMP)
1081   */
1082 typedef struct
1083 {
1084   __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
1085   __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
1086   __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
1087 } OPAMP_TypeDef;
1088 
1089 typedef struct
1090 {
1091   __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to
1092                                   several OPAMP instances, Address offset: 0x00         */
1093 } OPAMP_Common_TypeDef;
1094 
1095 
1096 /**
1097   * @brief MDF/ADF
1098   */
1099 typedef struct
1100 {
1101  __IO uint32_t GCR;            /*!< MDF Global Control register,             Address offset: 0x00  */
1102  __IO uint32_t CKGCR;          /*!< MDF Clock Generator Control Register,    Address offset: 0x04  */
1103  uint32_t     RESERVED1[6];    /*!< Reserved, 0x08-0x1C                                            */
1104  __IO uint32_t OR;             /*!< MDF  Option Register,                    Address offset: 0x20  */
1105 }MDF_TypeDef;
1106 
1107 /**
1108   * @brief MDF/ADF filter
1109   */
1110 typedef struct
1111 {
1112  __IO uint32_t SITFCR;         /*!< MDF Serial Interface Control Register,          Address offset: 0x80 */
1113  __IO uint32_t BSMXCR;         /*!< MDF Bitstream Matrix Control Register,          Address offset: 0x84 */
1114  __IO uint32_t DFLTCR;         /*!< MDF Digital Filter Control Register,            Address offset: 0x88 */
1115  __IO uint32_t DFLTCICR;       /*!< MDF MCIC Configuration Register,                Address offset: 0x8C */
1116  __IO uint32_t DFLTRSFR;       /*!< MDF Reshape Filter Configuration Register,      Address offset: 0x90 */
1117  __IO uint32_t DFLTINTR;       /*!< MDF Integrator Configuration Register,          Address offset: 0x94 */
1118  __IO uint32_t OLDCR;          /*!< MDF Out-Of Limit Detector Control Register,     Address offset: 0x98 */
1119  __IO uint32_t OLDTHLR;        /*!< MDF OLD Threshold Low Register,                 Address offset: 0x9C */
1120  __IO uint32_t OLDTHHR;        /*!< MDF OLD Threshold High Register,                Address offset: 0xA0 */
1121  __IO uint32_t DLYCR;          /*!< MDF Delay control Register,                     Address offset: 0xA4 */
1122  __IO uint32_t SCDCR;          /*!< MDF short circuit detector control Register,    Address offset: 0xA8 */
1123  __IO uint32_t DFLTIER;        /*!< MDF DFLT Interrupt enable Register,             Address offset: 0xAC */
1124  __IO uint32_t DFLTISR;        /*!< MDF DFLT Interrupt status Register,             Address offset: 0xB0 */
1125  __IO uint32_t OECCR;          /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */
1126  __IO uint32_t SADCR;          /*!< MDF SAD Control Register,                       Address offset: 0xB8 */
1127  __IO uint32_t SADCFGR;        /*!< MDF SAD configuration register,                 Address offset: 0xBC */
1128  __IO uint32_t SADSDLVR;       /*!< MDF SAD Sound level Register,                   Address offset: 0xC0 */
1129  __IO uint32_t SADANLVR;       /*!< MDF SAD Ambient Noise level Register,           Address offset: 0xC4 */
1130  uint32_t     RESERVED1[9];    /*!< Reserved, 0xC8-0xE8                                                  */
1131  __IO uint32_t SNPSDR;         /*!< MDF Snapshot Data Register,                     Address offset: 0xEC */
1132  __IO uint32_t DFLTDR;         /*!< MDF Digital Filter Data Register,               Address offset: 0xF0 */
1133 } MDF_Filter_TypeDef;
1134 
1135 /**
1136   * @brief HEXA and OCTO Serial Peripheral Interface
1137   */
1138 
1139 typedef struct
1140 {
1141   __IO uint32_t CR;          /*!< XSPI Control register,                            Address offset: 0x000 */
1142   uint32_t RESERVED;         /*!< Reserved,                                         Address offset: 0x004 */
1143   __IO uint32_t DCR1;        /*!< XSPI Device Configuration register 1,             Address offset: 0x008 */
1144   __IO uint32_t DCR2;        /*!< XSPI Device Configuration register 2,             Address offset: 0x00C */
1145   __IO uint32_t DCR3;        /*!< XSPI Device Configuration register 3,             Address offset: 0x010 */
1146   __IO uint32_t DCR4;        /*!< XSPI Device Configuration register 4,             Address offset: 0x014 */
1147   uint32_t RESERVED1[2];     /*!< Reserved,                                         Address offset: 0x018-0x01C */
1148   __IO uint32_t SR;          /*!< XSPI Status register,                             Address offset: 0x020 */
1149   __IO uint32_t FCR;         /*!< XSPI Flag Clear register,                         Address offset: 0x024 */
1150   uint32_t RESERVED2[6];     /*!< Reserved,                                         Address offset: 0x028-0x03C */
1151   __IO uint32_t DLR;         /*!< XSPI Data Length register,                        Address offset: 0x040 */
1152   uint32_t RESERVED3;        /*!< Reserved,                                         Address offset: 0x044 */
1153   __IO uint32_t AR;          /*!< XSPI Address register,                            Address offset: 0x048 */
1154   uint32_t RESERVED4;        /*!< Reserved,                                         Address offset: 0x04C */
1155   __IO uint32_t DR;          /*!< XSPI Data register,                               Address offset: 0x050 */
1156   uint32_t RESERVED5[11];    /*!< Reserved,                                         Address offset: 0x054-0x07C */
1157   __IO uint32_t PSMKR;       /*!< XSPI Polling Status Mask register,                Address offset: 0x080 */
1158   uint32_t RESERVED6;        /*!< Reserved,                                         Address offset: 0x084 */
1159   __IO uint32_t PSMAR;       /*!< XSPI Polling Status Match register,               Address offset: 0x088 */
1160   uint32_t RESERVED7;        /*!< Reserved,                                         Address offset: 0x08C */
1161   __IO uint32_t PIR;         /*!< XSPI Polling Interval register,                   Address offset: 0x090 */
1162   uint32_t RESERVED8[27];    /*!< Reserved,                                         Address offset: 0x094-0x0FC */
1163   __IO uint32_t CCR;         /*!< XSPI Communication Configuration register,        Address offset: 0x100 */
1164   uint32_t RESERVED9;        /*!< Reserved,                                         Address offset: 0x104 */
1165   __IO uint32_t TCR;         /*!< XSPI Timing Configuration register,               Address offset: 0x108 */
1166   uint32_t RESERVED10;       /*!< Reserved,                                         Address offset: 0x10C */
1167   __IO uint32_t IR;          /*!< XSPI Instruction register,                        Address offset: 0x110 */
1168   uint32_t RESERVED11[3];    /*!< Reserved,                                         Address offset: 0x114-0x11C */
1169   __IO uint32_t ABR;         /*!< XSPI Alternate Bytes register,                    Address offset: 0x120 */
1170   uint32_t RESERVED12[3];    /*!< Reserved,                                         Address offset: 0x124-0x12C */
1171   __IO uint32_t LPTR;        /*!< XSPI Low Power Timeout register,                  Address offset: 0x130 */
1172   uint32_t RESERVED13[3];    /*!< Reserved,                                         Address offset: 0x134-0x13C */
1173   __IO uint32_t WPCCR;       /*!< XSPI Wrap Communication Configuration register,   Address offset: 0x140 */
1174   uint32_t RESERVED14;       /*!< Reserved,                                         Address offset: 0x144 */
1175   __IO uint32_t WPTCR;       /*!< XSPI Wrap Timing Configuration register,          Address offset: 0x148 */
1176   uint32_t RESERVED15;       /*!< Reserved,                                         Address offset: 0x14C */
1177   __IO uint32_t WPIR;        /*!< XSPI Wrap Instruction register,                   Address offset: 0x150 */
1178   uint32_t RESERVED16[3];    /*!< Reserved,                                         Address offset: 0x154-0x15C */
1179   __IO uint32_t WPABR;       /*!< XSPI Wrap Alternate Bytes register,               Address offset: 0x160 */
1180   uint32_t RESERVED17[7];    /*!< Reserved,                                         Address offset: 0x164-0x17C */
1181   __IO uint32_t WCCR;        /*!< XSPI Write Communication Configuration register,  Address offset: 0x180 */
1182   uint32_t RESERVED18;       /*!< Reserved,                                         Address offset: 0x184 */
1183   __IO uint32_t WTCR;        /*!< XSPI Write Timing Configuration register,         Address offset: 0x188 */
1184   uint32_t RESERVED19;       /*!< Reserved,                                         Address offset: 0x18C */
1185   __IO uint32_t WIR;         /*!< XSPI Write Instruction register,                  Address offset: 0x190 */
1186   uint32_t RESERVED20[3];    /*!< Reserved,                                         Address offset: 0x194-0x19C */
1187   __IO uint32_t WABR;        /*!< XSPI Write Alternate Bytes register,              Address offset: 0x1A0 */
1188   uint32_t RESERVED21[23];   /*!< Reserved,                                         Address offset: 0x1A4-0x1FC */
1189   __IO uint32_t HLCR;        /*!< XSPI Hyperbus Latency Configuration register,     Address offset: 0x200 */
1190   uint32_t RESERVED22[3];    /*!< Reserved,                                         Address offset: 0x204-0x20C */
1191   __IO uint32_t CALFCR;      /*!< XSPI Full-cycle calibration configuration
1192                                   HSPI only, invalid for OCTOSPI,                   Address offset: 0x210 */
1193   uint32_t RESERVED23;       /*!< Reserved,                                         Address offset: 0x214 */
1194   __IO uint32_t CALMR;       /*!< XSPI DLL master calibration configuration
1195                                   HSPI only, invalid for OCTOSPI,                   Address offset: 0x218 */
1196   uint32_t RESERVED24;       /*!< Reserved,                                         Address offset: 0x21C */
1197   __IO uint32_t CALSOR;      /*!< XSPI slave output calibration configuration
1198                                   HSPI only, invalid for OCTOSPI,                   Address offset: 0x220 */
1199   uint32_t RESERVED25;       /*!< Reserved,                                         Address offset: 0x224 */
1200   __IO uint32_t CALSIR;      /*!< XSPI slave input calibration configuration
1201                                   HSPI only, invalid for OCTOSPI,                   Address offset: 0x228 */
1202 } XSPI_TypeDef;
1203 
1204 typedef  XSPI_TypeDef OCTOSPI_TypeDef;
1205 
1206 typedef  XSPI_TypeDef HSPI_TypeDef;
1207 
1208 /**
1209   * @brief OTFDEC register
1210   */
1211 typedef struct
1212 {
1213   __IO uint32_t REG_CONFIGR;      /*!< OTFDEC Region Configuration register,          Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */
1214   __IO uint32_t REG_START_ADDR;   /*!< OTFDEC Region Start Address register,          Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */
1215   __IO uint32_t REG_END_ADDR;     /*!< OTFDEC Region End Address register,            Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */
1216   __IO uint32_t REG_NONCER0;      /*!< OTFDEC Region Nonce register 0,                Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */
1217   __IO uint32_t REG_NONCER1;      /*!< OTFDEC Region Nonce register 1,                Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */
1218   __IO uint32_t REG_KEYR0;        /*!< OTFDEC Region Key register 0,                  Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */
1219   __IO uint32_t REG_KEYR1;        /*!< OTFDEC Region Key register 1,                  Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */
1220   __IO uint32_t REG_KEYR2;        /*!< OTFDEC Region Key register 2,                  Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */
1221   __IO uint32_t REG_KEYR3;        /*!< OTFDEC Region Key register 3,                  Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */
1222 } OTFDEC_Region_TypeDef;
1223 
1224 typedef struct
1225 {
1226   __IO uint32_t CR;               /*!< OTFDEC Control register,                                 Address offset: 0x000 */
1227   uint32_t RESERVED1[3];          /*!< Reserved,                                                Address offset: 0x004-0x00C */
1228   __IO uint32_t PRIVCFGR;         /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */
1229   uint32_t RESERVED2[187];        /*!< Reserved,                                                Address offset: 0x014-0x2FC */
1230   __IO uint32_t ISR;              /*!< OTFDEC Interrupt Status register,                        Address offset: 0x300 */
1231   __IO uint32_t ICR;              /*!< OTFDEC Interrupt Clear register,                         Address offset: 0x304 */
1232   __IO uint32_t IER;              /*!< OTFDEC Interrupt Enable register,                        Address offset: 0x308 */
1233 } OTFDEC_TypeDef;
1234 
1235 
1236 /**
1237   * @brief Serial Peripheral Interface IO Manager
1238   */
1239 typedef struct
1240 {
1241   __IO uint32_t CR;          /*!< OCTOSPIM IO Manager Control register,                 Address offset: 0x00 */
1242   __IO uint32_t PCR[8];      /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
1243 } XSPIM_TypeDef;
1244 
1245 typedef  XSPIM_TypeDef OCTOSPIM_TypeDef;
1246 
1247 /**
1248   * @brief Power Control
1249   */
1250 typedef struct
1251 {
1252   __IO uint32_t CR1;      /*!< Power control register 1,                          Address offset: 0x00 */
1253   __IO uint32_t CR2;      /*!< Power control register 2,                          Address offset: 0x04 */
1254   __IO uint32_t CR3;      /*!< Power control register 3,                          Address offset: 0x08 */
1255   __IO uint32_t VOSR;     /*!< Power voltage scaling register,                    Address offset: 0x0C */
1256   __IO uint32_t SVMCR;    /*!< Power supply voltage monitoring control register,  Address offset: 0x10 */
1257   __IO uint32_t WUCR1;    /*!< Power wakeup control register 1,                   Address offset: 0x14 */
1258   __IO uint32_t WUCR2;    /*!< Power wakeup control register 2,                   Address offset: 0x18 */
1259   __IO uint32_t WUCR3;    /*!< Power wakeup control register 3,                   Address offset: 0x1C */
1260   __IO uint32_t BDCR1;    /*!< Power backup domain control register 1,            Address offset: 0x20 */
1261   __IO uint32_t BDCR2;    /*!< Power backup domain control register 2,            Address offset: 0x24 */
1262   __IO uint32_t DBPR;     /*!< Power disable backup domain register,              Address offset: 0x28 */
1263   __IO uint32_t UCPDR;    /*!< Power USB Type-C and Power Delivery register,      Address offset: 0x2C */
1264   __IO uint32_t SECCFGR;  /*!< Power Security configuration register,             Address offset: 0x30 */
1265   __IO uint32_t PRIVCFGR; /*!< Power privilege control register,                  Address offset: 0x34 */
1266   __IO uint32_t SR;       /*!< Power status register,                             Address offset: 0x38 */
1267   __IO uint32_t SVMSR;    /*!< Power supply voltage monitoring status register,   Address offset: 0x3C */
1268   __IO uint32_t BDSR;     /*!< Power backup domain status register,               Address offset: 0x40 */
1269   __IO uint32_t WUSR;     /*!< Power wakeup status register,                      Address offset: 0x44 */
1270   __IO uint32_t WUSCR;    /*!< Power wakeup status clear register,                Address offset: 0x48 */
1271   __IO uint32_t APCR;     /*!< Power apply pull configuration register,           Address offset: 0x4C */
1272   __IO uint32_t PUCRA;    /*!< Power Port A pull-up control register,             Address offset: 0x50 */
1273   __IO uint32_t PDCRA;    /*!< Power Port A pull-down control register,           Address offset: 0x54 */
1274   __IO uint32_t PUCRB;    /*!< Power Port B pull-up control register,             Address offset: 0x58 */
1275   __IO uint32_t PDCRB;    /*!< Power Port B pull-down control register,           Address offset: 0x5C */
1276   __IO uint32_t PUCRC;    /*!< Power Port C pull-up control register,             Address offset: 0x60 */
1277   __IO uint32_t PDCRC;    /*!< Power Port C pull-down control register,           Address offset: 0x64 */
1278   __IO uint32_t PUCRD;    /*!< Power Port D pull-up control register,             Address offset: 0x68 */
1279   __IO uint32_t PDCRD;    /*!< Power Port D pull-down control register,           Address offset: 0x6C */
1280   __IO uint32_t PUCRE;    /*!< Power Port E pull-up control register,             Address offset: 0x70 */
1281   __IO uint32_t PDCRE;    /*!< Power Port E pull-down control register,           Address offset: 0x74 */
1282   __IO uint32_t PUCRF;    /*!< Power Port F pull-up control register,             Address offset: 0x78 */
1283   __IO uint32_t PDCRF;    /*!< Power Port F pull-down control register,           Address offset: 0x7C */
1284   __IO uint32_t PUCRG;    /*!< Power Port G pull-up control register,             Address offset: 0x80 */
1285   __IO uint32_t PDCRG;    /*!< Power Port G pull-down control register,           Address offset: 0x84 */
1286   __IO uint32_t PUCRH;    /*!< Power Port H pull-up control register,             Address offset: 0x88 */
1287   __IO uint32_t PDCRH;    /*!< Power Port H pull-down control register,           Address offset: 0x8C */
1288   __IO uint32_t PUCRI;    /*!< Power Port I pull-up control register,             Address offset: 0x90 */
1289   __IO uint32_t PDCRI;    /*!< Power Port I pull-down control register,           Address offset: 0x94 */
1290   __IO uint32_t PUCRJ;    /*!< Power Port J pull-up control register,             Address offset: 0x98        */
1291   __IO uint32_t PDCRJ;    /*!< Power Port J pull-down control register,           Address offset: 0x9C        */
1292        uint32_t RESERVED3[2];  /*!< Reserved3,                                    Address offset: 0x0A0-0x0A4 */
1293   __IO uint32_t CR4;      /*!< Power power control register 4,                    Address offset: 0xA8        */
1294   __IO uint32_t CR5;      /*!< Power power control register 5,                    Address offset: 0xAC        */
1295 } PWR_TypeDef;
1296 
1297 /**
1298   * @brief SRAMs configuration controller
1299   */
1300 typedef struct
1301 {
1302   __IO uint32_t CR;       /*!< Control Register,                  Address offset: 0x00 */
1303   __IO uint32_t IER;      /*!< Interrupt Enable Register,         Address offset: 0x04 */
1304   __IO uint32_t ISR;      /*!< Interrupt Status Register,         Address offset: 0x08 */
1305   __IO uint32_t SEAR;     /*!< ECC Single Error Address Register, Address offset: 0x0C */
1306   __IO uint32_t DEAR;     /*!< ECC Double Error Address Register, Address offset: 0x10 */
1307   __IO uint32_t ICR;      /*!< Interrupt Clear Register,          Address offset: 0x14 */
1308   __IO uint32_t WPR1;     /*!< SRAM Write Protection Register 1,  Address offset: 0x18 */
1309   __IO uint32_t WPR2;     /*!< SRAM Write Protection Register 2,  Address offset: 0x1C */
1310   uint32_t      RESERVED; /*!< Reserved,                          Address offset: 0x20 */
1311   __IO uint32_t ECCKEY;   /*!< SRAM ECC Key Register,             Address offset: 0x24 */
1312   __IO uint32_t ERKEYR;   /*!< SRAM Erase Key Register,           Address offset: 0x28 */
1313 }RAMCFG_TypeDef;
1314 
1315 /**
1316   * @brief Reset and Clock Control
1317   */
1318 typedef struct
1319 {
1320   __IO uint32_t CR;            /*!< RCC clock control register                                               Address offset: 0x00 */
1321   uint32_t      RESERVED0;     /*!< Reserved                                                                 Address offset: 0x04 */
1322   __IO uint32_t ICSCR1;        /*!< RCC internal clock sources calibration register 1                        Address offset: 0x08 */
1323   __IO uint32_t ICSCR2;        /*!< RCC internal clock sources calibration register 2                        Address offset: 0x0C */
1324   __IO uint32_t ICSCR3;        /*!< RCC internal clock sources calibration register 3                        Address offset: 0x10 */
1325   __IO uint32_t CRRCR;         /*!< RCC Clock Recovery RC Register                                           Address offset: 0x14 */
1326   uint32_t      RESERVED1;     /*!< Reserved                                                                 Address offset: 0x18 */
1327   __IO uint32_t CFGR1;         /*!< RCC clock configuration register 1                                       Address offset: 0x1C */
1328   __IO uint32_t CFGR2;         /*!< RCC clock configuration register 2                                       Address offset: 0x20 */
1329   __IO uint32_t CFGR3;         /*!< RCC clock configuration register 3                                       Address offset: 0x24 */
1330   __IO uint32_t PLL1CFGR;      /*!< PLL1 Configuration Register                                              Address offset: 0x28 */
1331   __IO uint32_t PLL2CFGR;      /*!< PLL2 Configuration Register                                              Address offset: 0x2C */
1332   __IO uint32_t PLL3CFGR;      /*!< PLL3 Configuration Register                                              Address offset: 0x30 */
1333   __IO uint32_t PLL1DIVR;      /*!< PLL1 Dividers Configuration Register                                     Address offset: 0x34 */
1334   __IO uint32_t PLL1FRACR;     /*!< PLL1 Fractional Divider Configuration Register                           Address offset: 0x38 */
1335   __IO uint32_t PLL2DIVR;      /*!< PLL2 Dividers Configuration Register                                     Address offset: 0x3C */
1336   __IO uint32_t PLL2FRACR;     /*!< PLL2 Fractional Divider Configuration Register                           Address offset: 0x40 */
1337   __IO uint32_t PLL3DIVR;      /*!< PLL3 Dividers Configuration Register                                     Address offset: 0x44 */
1338   __IO uint32_t PLL3FRACR;     /*!< PLL3 Fractional Divider Configuration Register                           Address offset: 0x48 */
1339   uint32_t      RESERVED2;     /*!< Reserved                                                                 Address offset: 0x4C */
1340   __IO uint32_t CIER;          /*!< Clock Interrupt Enable Register                                          Address offset: 0x50 */
1341   __IO uint32_t CIFR;          /*!< Clock Interrupt Flag Register                                            Address offset: 0x54 */
1342   __IO uint32_t CICR;          /*!< Clock Interrupt Clear Register                                           Address offset: 0x58 */
1343   uint32_t      RESERVED3;     /*!< Reserved                                                                 Address offset: 0x5C */
1344   __IO uint32_t AHB1RSTR;      /*!< AHB1 Peripherals Reset Register                                          Address offset: 0x60 */
1345   __IO uint32_t AHB2RSTR1;     /*!< AHB2 Peripherals Reset Register 1                                        Address offset: 0x64 */
1346   __IO uint32_t AHB2RSTR2;     /*!< AHB2 Peripherals Reset Register 2                                        Address offset: 0x68 */
1347   __IO uint32_t AHB3RSTR;      /*!< AHB3 Peripherals Reset Register                                          Address offset: 0x6C */
1348   uint32_t      RESERVED4;     /*!< Reserved                                                                 Address offset: 0x70 */
1349   __IO uint32_t APB1RSTR1;     /*!< APB1 Peripherals Reset Register 1                                        Address offset: 0x74 */
1350   __IO uint32_t APB1RSTR2;     /*!< APB1 Peripherals Reset Register 2                                        Address offset: 0x78 */
1351   __IO uint32_t APB2RSTR;      /*!< APB2 Peripherals Reset Register                                          Address offset: 0x7C */
1352   __IO uint32_t APB3RSTR;      /*!< APB3 Peripherals Reset Register                                          Address offset: 0x80 */
1353   uint32_t      RESERVED5;     /*!< Reserved                                                                 Address offset: 0x84 */
1354   __IO uint32_t AHB1ENR;       /*!< AHB1 Peripherals Clock Enable Register                                   Address offset: 0x88 */
1355   __IO uint32_t AHB2ENR1;      /*!< AHB2 Peripherals Clock Enable Register 1                                 Address offset: 0x8C */
1356   __IO uint32_t AHB2ENR2;      /*!< AHB2 Peripherals Clock Enable Register 2                                 Address offset: 0x90 */
1357   __IO uint32_t AHB3ENR;       /*!< AHB3 Peripherals Clock Enable Register                                   Address offset: 0x94 */
1358   uint32_t      RESERVED6;     /*!< Reserved                                                                 Address offset: 0x98 */
1359   __IO uint32_t APB1ENR1;      /*!< APB1 Peripherals Clock Enable Register 1                                 Address offset: 0x9C */
1360   __IO uint32_t APB1ENR2;      /*!< APB1 Peripherals Clock Enable Register 2                                 Address offset: 0xA0 */
1361   __IO uint32_t APB2ENR;       /*!< APB2 Peripherals Clock Enable Register                                   Address offset: 0xA4 */
1362   __IO uint32_t APB3ENR;       /*!< APB3 Peripherals Clock Enable Register                                   Address offset: 0xA8 */
1363   uint32_t      RESERVED7;     /*!< Reserved                                                                 Address offset: 0xAC */
1364   __IO uint32_t AHB1SMENR;     /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register           Address offset: 0xB0 */
1365   __IO uint32_t AHB2SMENR1;    /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1         Address offset: 0xB4 */
1366   __IO uint32_t AHB2SMENR2;    /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2         Address offset: 0xB8 */
1367   __IO uint32_t AHB3SMENR;     /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register           Address offset: 0xBC */
1368   uint32_t      RESERVED8;     /*!< Reserved                                                                 Address offset: 0xC0 */
1369   __IO uint32_t APB1SMENR1;    /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1         Address offset: 0xC4 */
1370   __IO uint32_t APB1SMENR2;    /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2         Address offset: 0xC8 */
1371   __IO uint32_t APB2SMENR;     /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1         Address offset: 0xCC */
1372   __IO uint32_t APB3SMENR;     /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2         Address offset: 0xD0 */
1373   uint32_t      RESERVED9;     /*!< Reserved                                                                 Address offset: 0xD4 */
1374   __IO uint32_t SRDAMR;        /*!< SRD Autonomous Mode Register                                             Address offset: 0xD8 */
1375   uint32_t      RESERVED10;    /*!< Reserved,                                                                Address offset: 0xDC */
1376   __IO uint32_t CCIPR1;        /*!< IPs Clocks Configuration Register 1                                      Address offset: 0xE0 */
1377   __IO uint32_t CCIPR2;        /*!< IPs Clocks Configuration Register 2                                      Address offset: 0xE4 */
1378   __IO uint32_t CCIPR3;        /*!< IPs Clocks Configuration Register 3                                      Address offset: 0xE8 */
1379   uint32_t      RESERVED11;    /*!< Reserved,                                                                Address offset: 0xEC */
1380   __IO uint32_t BDCR;          /*!< Backup Domain Control Register                                           Address offset: 0xF0 */
1381   __IO uint32_t CSR;           /*!< V33 Clock Control & Status Register                                      Address offset: 0xF4 */
1382   uint32_t      RESERVED[6];   /*!< Reserved                                                                 Address offset: 0xF8 */
1383   __IO uint32_t SECCFGR;       /*!< RCC secure configuration register                                        Address offset: 0x110 */
1384   __IO uint32_t PRIVCFGR;      /*!< RCC privilege configuration register                                     Address offset: 0x114 */
1385 } RCC_TypeDef;
1386 
1387 /**
1388   * @brief PKA
1389   */
1390 typedef struct
1391 {
1392   __IO uint32_t CR;            /*!< PKA control register,             Address offset: 0x00 */
1393   __IO uint32_t SR;            /*!< PKA status register,              Address offset: 0x04 */
1394   __IO uint32_t CLRFR;         /*!< PKA clear flag register,          Address offset: 0x08 */
1395   uint32_t Reserved[253];      /*!< Reserved memory area              Address offset: 0x0C  -> 0x03FC */
1396   __IO uint32_t RAM[1334];     /*!< PKA RAM                           Address offset: 0x400 -> 0x18D4 */
1397 } PKA_TypeDef;
1398 
1399 /*
1400 * @brief RTC Specific device feature definitions
1401 */
1402 #define RTC_BKP_NB         32U
1403 #define RTC_TAMP_NB        8U
1404 
1405 /**
1406   * @brief Real-Time Clock
1407   */
1408 typedef struct
1409 {
1410   __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
1411   __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
1412   __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
1413   __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
1414   __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
1415   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
1416   __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
1417   __IO uint32_t PRIVCFGR;    /*!< RTC privilege mode control register,            Address offset: 0x1C */
1418   __IO uint32_t SECCFGR;     /*!< RTC secure mode control register,               Address offset: 0x20 */
1419   __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
1420   __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
1421   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
1422   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
1423   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
1424   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
1425        uint32_t RESERVED0;   /*!< Reserved,                                       Address offset: 0x3C */
1426   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
1427   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
1428   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
1429   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
1430   __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
1431   __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
1432   __IO uint32_t SMISR;       /*!< RTC secure masked interrupt status register,    Address offset: 0x58 */
1433   __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
1434        uint32_t RESERVED4[4];/*!< Reserved,                                       Address offset: 0x58 */
1435   __IO uint32_t ALRABINR;    /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
1436   __IO uint32_t ALRBBINR;    /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
1437 } RTC_TypeDef;
1438 
1439 /**
1440   * @brief Tamper and backup registers
1441   */
1442 typedef struct
1443 {
1444   __IO uint32_t CR1;           /*!< TAMP configuration register 1,               Address offset: 0x00 */
1445   __IO uint32_t CR2;           /*!< TAMP configuration register 2,               Address offset: 0x04 */
1446   __IO uint32_t CR3;           /*!< TAMP configuration register 3,               Address offset: 0x08 */
1447   __IO uint32_t FLTCR;         /*!< TAMP filter control register,                Address offset: 0x0C */
1448   __IO uint32_t ATCR1;         /*!< TAMP filter control register 1               Address offset: 0x10 */
1449   __IO uint32_t ATSEEDR;       /*!< TAMP active tamper seed register,            Address offset: 0x14 */
1450   __IO uint32_t ATOR;          /*!< TAMP active tamper output register,          Address offset: 0x18 */
1451   __IO uint32_t ATCR2;         /*!< TAMP filter control register 2,              Address offset: 0x1C */
1452   __IO uint32_t SECCFGR;       /*!< TAMP secure mode control register,           Address offset: 0x20 */
1453   __IO uint32_t PRIVCFGR;      /*!< TAMP privilege mode control register,        Address offset: 0x24 */
1454        uint32_t RESERVED0;     /*!< Reserved,                                    Address offset: 0x28 */
1455   __IO uint32_t IER;           /*!< TAMP interrupt enable register,              Address offset: 0x2C */
1456   __IO uint32_t SR;            /*!< TAMP status register,                        Address offset: 0x30 */
1457   __IO uint32_t MISR;          /*!< TAMP masked interrupt status register,       Address offset: 0x34 */
1458   __IO uint32_t SMISR;         /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */
1459   __IO uint32_t SCR;           /*!< TAMP status clear register,                  Address offset: 0x3C */
1460   __IO uint32_t COUNTR;        /*!< TAMP monotonic counter register,             Address offset: 0x40 */
1461        uint32_t RESERVED1[4];  /*!< Reserved,                                    Address offset: 0x43 -- 0x50 */
1462   __IO uint32_t ERCFGR;        /*!< TAMP erase configuration register,           Address offset: 0x54 */
1463        uint32_t RESERVED2[42]; /*!< Reserved,                                    Address offset: 0x58 -- 0xFC */
1464   __IO uint32_t BKP0R;         /*!< TAMP backup register 0,                      Address offset: 0x100 */
1465   __IO uint32_t BKP1R;         /*!< TAMP backup register 1,                      Address offset: 0x104 */
1466   __IO uint32_t BKP2R;         /*!< TAMP backup register 2,                      Address offset: 0x108 */
1467   __IO uint32_t BKP3R;         /*!< TAMP backup register 3,                      Address offset: 0x10C */
1468   __IO uint32_t BKP4R;         /*!< TAMP backup register 4,                      Address offset: 0x110 */
1469   __IO uint32_t BKP5R;         /*!< TAMP backup register 5,                      Address offset: 0x114 */
1470   __IO uint32_t BKP6R;         /*!< TAMP backup register 6,                      Address offset: 0x118 */
1471   __IO uint32_t BKP7R;         /*!< TAMP backup register 7,                      Address offset: 0x11C */
1472   __IO uint32_t BKP8R;         /*!< TAMP backup register 8,                      Address offset: 0x120 */
1473   __IO uint32_t BKP9R;         /*!< TAMP backup register 9,                      Address offset: 0x124 */
1474   __IO uint32_t BKP10R;        /*!< TAMP backup register 10,                     Address offset: 0x128 */
1475   __IO uint32_t BKP11R;        /*!< TAMP backup register 11,                     Address offset: 0x12C */
1476   __IO uint32_t BKP12R;        /*!< TAMP backup register 12,                     Address offset: 0x130 */
1477   __IO uint32_t BKP13R;        /*!< TAMP backup register 13,                     Address offset: 0x134 */
1478   __IO uint32_t BKP14R;        /*!< TAMP backup register 14,                     Address offset: 0x138 */
1479   __IO uint32_t BKP15R;        /*!< TAMP backup register 15,                     Address offset: 0x13C */
1480   __IO uint32_t BKP16R;        /*!< TAMP backup register 16,                     Address offset: 0x140 */
1481   __IO uint32_t BKP17R;        /*!< TAMP backup register 17,                     Address offset: 0x144 */
1482   __IO uint32_t BKP18R;        /*!< TAMP backup register 18,                     Address offset: 0x148 */
1483   __IO uint32_t BKP19R;        /*!< TAMP backup register 19,                     Address offset: 0x14C */
1484   __IO uint32_t BKP20R;        /*!< TAMP backup register 20,                     Address offset: 0x150 */
1485   __IO uint32_t BKP21R;        /*!< TAMP backup register 21,                     Address offset: 0x154 */
1486   __IO uint32_t BKP22R;        /*!< TAMP backup register 22,                     Address offset: 0x158 */
1487   __IO uint32_t BKP23R;        /*!< TAMP backup register 23,                     Address offset: 0x15C */
1488   __IO uint32_t BKP24R;        /*!< TAMP backup register 24,                     Address offset: 0x160 */
1489   __IO uint32_t BKP25R;        /*!< TAMP backup register 25,                     Address offset: 0x164 */
1490   __IO uint32_t BKP26R;        /*!< TAMP backup register 26,                     Address offset: 0x168 */
1491   __IO uint32_t BKP27R;        /*!< TAMP backup register 27,                     Address offset: 0x16C */
1492   __IO uint32_t BKP28R;        /*!< TAMP backup register 28,                     Address offset: 0x170 */
1493   __IO uint32_t BKP29R;        /*!< TAMP backup register 29,                     Address offset: 0x174 */
1494   __IO uint32_t BKP30R;        /*!< TAMP backup register 30,                     Address offset: 0x178 */
1495   __IO uint32_t BKP31R;        /*!< TAMP backup register 31,                     Address offset: 0x17C */
1496 } TAMP_TypeDef;
1497 
1498 /**
1499   * @brief Universal Synchronous Asynchronous Receiver Transmitter
1500   */
1501 typedef struct
1502 {
1503   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
1504   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
1505   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
1506   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
1507   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
1508   __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14  */
1509   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
1510   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
1511   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
1512   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
1513   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
1514   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
1515   __IO uint32_t AUTOCR;      /*!< USART Autonomous mode control register    Address offset: 0x30  */
1516 } USART_TypeDef;
1517 
1518 /**
1519   * @brief Serial Audio Interface
1520   */
1521 typedef struct
1522 {
1523   __IO uint32_t GCR;          /*!< SAI global configuration register,        Address offset: 0x00 */
1524   uint32_t      RESERVED[16]; /*!< Reserved,                         Address offset: 0x04 to 0x40 */
1525   __IO uint32_t PDMCR;        /*!< SAI PDM control register,                 Address offset: 0x44 */
1526   __IO uint32_t PDMDLY;       /*!< SAI PDM delay register,                   Address offset: 0x48 */
1527 } SAI_TypeDef;
1528 
1529 typedef struct
1530 {
1531   __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
1532   __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
1533   __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
1534   __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
1535   __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
1536   __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
1537   __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
1538   __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
1539 } SAI_Block_TypeDef;
1540 
1541 /**
1542   * @brief System configuration controller
1543   */
1544 typedef struct
1545 {
1546   __IO uint32_t SECCFGR;        /*!< SYSCFG secure configuration register,            Address offset: 0x00 */
1547   __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                 Address offset: 0x04 */
1548   __IO uint32_t FPUIMR;         /*!< SYSCFG FPU interrupt mask register,              Address offset: 0x08 */
1549   __IO uint32_t CNSLCKR;        /*!< SYSCFG CPU non-secure lock register,             Address offset: 0x0C */
1550   __IO uint32_t CSLCKR;         /*!< SYSCFG CPU secure lock register,                 Address offset: 0x10 */
1551   __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                 Address offset: 0x14 */
1552   __IO uint32_t MESR;           /*!< SYSCFG Memory Erase Status register,             Address offset: 0x18 */
1553   __IO uint32_t CCCSR;          /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
1554   __IO uint32_t CCVR;           /*!< SYSCFG Conpensaion Cell value register,          Address offset: 0x20 */
1555   __IO uint32_t CCCR;           /*!< SYSCFG Conpensaion Cell Code register,           Address offset: 0x24 */
1556        uint32_t RESERVED1;      /*!< RESERVED1,                                       Address offset: 0x28 */
1557   __IO uint32_t RSSCMDR;        /*!< SYSCFG RSS command mode register,                Address offset: 0x2C */
1558        uint32_t RESERVED2[17];  /*!< RESERVED2,                                       Address offset: 0x30 - 0x70 */
1559   __IO uint32_t OTGHSPHYCR;     /*!< SYSCFG USB OTG_HS PHY register                   Address offset: 0x74 */
1560        uint32_t RESERVED3;      /*!< RESERVED3,                                       Address offset: 0x78 */
1561   __IO uint32_t OTGHSPHYTUNER2; /*!< SYSCFG USB OTG_HS PHY tune register 2            Address offset: 0x7C */
1562 } SYSCFG_TypeDef;
1563 
1564 /**
1565   * @brief Secure digital input/output Interface
1566   */
1567 typedef struct
1568 {
1569   __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */
1570   __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */
1571   __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */
1572   __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */
1573   __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */
1574   __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */
1575   __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */
1576   __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */
1577   __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */
1578   __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */
1579   __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */
1580   __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */
1581   __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */
1582   __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */
1583   __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */
1584   __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */
1585   __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */
1586   uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */
1587   __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */
1588   __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */
1589   __IO uint32_t IDMABASER;      /*!< SDMMC DMA buffer base address register,   Address offset: 0x58  */
1590   uint32_t      RESERVED1[2];   /*!< Reserved, 0x60                                             */
1591   __IO uint32_t IDMALAR;        /*!< SDMMC DMA linked list address register,   Address offset: 0x64  */
1592   __IO uint32_t IDMABAR;        /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */
1593   uint32_t      RESERVED2[5];   /*!< Reserved, 0x6C-0x7C                                             */
1594   __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */
1595 } SDMMC_TypeDef;
1596 
1597 
1598 
1599 /**
1600   * @brief Delay Block DLYB
1601   */
1602 typedef struct
1603 {
1604   __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */
1605   __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */
1606 } DLYB_TypeDef;
1607 
1608 /**
1609   * @brief UCPD
1610   */
1611 typedef struct
1612 {
1613   __IO uint32_t CFG1;         /*!< UCPD configuration register 1,             Address offset: 0x00 */
1614   __IO uint32_t CFG2;         /*!< UCPD configuration register 2,             Address offset: 0x04 */
1615   __IO uint32_t CFG3;         /*!< UCPD configuration register 3,             Address offset: 0x08 */
1616   __IO uint32_t CR;           /*!< UCPD control register,                     Address offset: 0x0C */
1617   __IO uint32_t IMR;          /*!< UCPD interrupt mask register,              Address offset: 0x10 */
1618   __IO uint32_t SR;           /*!< UCPD status register,                      Address offset: 0x14 */
1619   __IO uint32_t ICR;          /*!< UCPD interrupt flag clear register         Address offset: 0x18 */
1620   __IO uint32_t TX_ORDSET;    /*!< UCPD Tx ordered set type register,         Address offset: 0x1C */
1621   __IO uint32_t TX_PAYSZ;     /*!< UCPD Tx payload size register,             Address offset: 0x20 */
1622   __IO uint32_t TXDR;         /*!< UCPD Tx data register,                     Address offset: 0x24 */
1623   __IO uint32_t RX_ORDSET;    /*!< UCPD Rx ordered set type register,         Address offset: 0x28 */
1624   __IO uint32_t RX_PAYSZ;     /*!< UCPD Rx payload size register,             Address offset: 0x2C */
1625   __IO uint32_t RXDR;         /*!< UCPD Rx data register,                     Address offset: 0x30 */
1626   __IO uint32_t RX_ORDEXT1;   /*!< UCPD Rx ordered set extension 1 register,  Address offset: 0x34 */
1627   __IO uint32_t RX_ORDEXT2;   /*!< UCPD Rx ordered set extension 2 register,  Address offset: 0x38 */
1628 } UCPD_TypeDef;
1629 
1630 /**
1631   * @brief USB_OTG_Core_register
1632   */
1633 typedef struct
1634 {
1635   __IO uint32_t GOTGCTL;             /*!< USB_OTG Control and Status Register,       Address offset: 000h */
1636   __IO uint32_t GOTGINT;             /*!< USB_OTG Interrupt Register,                Address offset: 004h */
1637   __IO uint32_t GAHBCFG;             /*!< Core AHB Configuration Register,           Address offset: 008h */
1638   __IO uint32_t GUSBCFG;             /*!< Core USB Configuration Register,           Address offset: 00Ch */
1639   __IO uint32_t GRSTCTL;             /*!< Core Reset Register,                       Address offset: 010h */
1640   __IO uint32_t GINTSTS;             /*!< Core Interrupt Register,                   Address offset: 014h */
1641   __IO uint32_t GINTMSK;             /*!< Core Interrupt Mask Register,              Address offset: 018h */
1642   __IO uint32_t GRXSTSR;             /*!< Receive Sts Q Read Register,               Address offset: 01Ch */
1643   __IO uint32_t GRXSTSP;             /*!< Receive Sts Q Read & POP Register,         Address offset: 020h */
1644   __IO uint32_t GRXFSIZ;             /*!< Receive FIFO Size Register,                Address offset: 024h */
1645   __IO uint32_t DIEPTXF0_HNPTXFSIZ;  /*!< EP0 / Non Periodic Tx FIFO Size Register,  Address offset: 028h */
1646   __IO uint32_t HNPTXSTS;            /*!< Non Periodic Tx FIFO/Queue Sts reg,        Address offset: 02Ch */
1647   __IO uint32_t Reserved30[2];       /*!< Reserved,                                  Address offset: 030h */
1648   __IO uint32_t GCCFG;               /*!< General Purpose IO Register,               Address offset: 038h */
1649   __IO uint32_t CID;                 /*!< User ID Register,                          Address offset: 03Ch */
1650   __IO uint32_t GSNPSID;             /*!< USB_OTG core ID,                           Address offset: 040h */
1651   __IO uint32_t GHWCFG1;             /*!< User HW config1,                           Address offset: 044h */
1652   __IO uint32_t GHWCFG2;             /*!< User HW config2,                           Address offset: 048h */
1653   __IO uint32_t GHWCFG3;             /*!< User HW config3,                           Address offset: 04Ch */
1654   __IO uint32_t  Reserved6;          /*!< Reserved,                                  Address offset: 050h */
1655   __IO uint32_t GLPMCFG;             /*!< LPM Register,                              Address offset: 054h */
1656   __IO uint32_t GPWRDN;              /*!< Power Down Register,                       Address offset: 058h */
1657   __IO uint32_t GDFIFOCFG;           /*!< DFIFO Software Config Register,            Address offset: 05Ch */
1658   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register,    Address offset: 60Ch */
1659   __IO uint32_t  Reserved43[39];     /*!< Reserved,                                  Address offset: 058h */
1660   __IO uint32_t HPTXFSIZ;            /*!< Host Periodic Tx FIFO Size Reg,            Address offset: 100h */
1661   __IO uint32_t DIEPTXF[0x0F];       /*!< dev Periodic Transmit FIFO                 Address offset: 104h */
1662 } USB_OTG_GlobalTypeDef;
1663 
1664 /**
1665   * @brief USB_OTG_device_Registers
1666   */
1667 typedef struct
1668 {
1669   __IO uint32_t DCFG;                /*!< dev Configuration Register,   Address offset: 800h */
1670   __IO uint32_t DCTL;                /*!< dev Control Register,         Address offset: 804h */
1671   __IO uint32_t DSTS;                /*!< dev Status Register (RO),     Address offset: 808h */
1672   uint32_t Reserved0C;               /*!< Reserved,                     Address offset: 80Ch */
1673   __IO uint32_t DIEPMSK;             /*!< dev IN Endpoint Mask,         Address offset: 810h */
1674   __IO uint32_t DOEPMSK;             /*!< dev OUT Endpoint Mask,        Address offset: 814h */
1675   __IO uint32_t DAINT;               /*!< dev All Endpoints Itr Reg,    Address offset: 818h */
1676   __IO uint32_t DAINTMSK;            /*!< dev All Endpoints Itr Mask,   Address offset: 81Ch */
1677   uint32_t  Reserved20;              /*!< Reserved,                     Address offset: 820h */
1678   uint32_t Reserved9;                /*!< Reserved,                     Address offset: 824h */
1679   __IO uint32_t DVBUSDIS;            /*!< dev VBUS discharge Register,  Address offset: 828h */
1680   __IO uint32_t DVBUSPULSE;          /*!< dev VBUS Pulse Register,      Address offset: 82Ch */
1681   __IO uint32_t DTHRCTL;             /*!< dev threshold,                Address offset: 830h */
1682   __IO uint32_t DIEPEMPMSK;          /*!< dev empty msk,                Address offset: 834h */
1683   __IO uint32_t DEACHINT;            /*!< dedicated EP interrupt,       Address offset: 838h */
1684   __IO uint32_t DEACHMSK;            /*!< dedicated EP msk,             Address offset: 83Ch */
1685   uint32_t Reserved40;               /*!< dedicated EP mask,            Address offset: 840h */
1686   __IO uint32_t DINEP1MSK;           /*!< dedicated EP mask,            Address offset: 844h */
1687   uint32_t  Reserved44[15];          /*!< Reserved,                     Address offset: 844-87Ch */
1688   __IO uint32_t DOUTEP1MSK;          /*!< dedicated EP msk,             Address offset: 884h */
1689 } USB_OTG_DeviceTypeDef;
1690 
1691 
1692 /**
1693   * @brief USB_OTG_IN_Endpoint-Specific_Register
1694   */
1695 typedef struct
1696 {
1697   __IO uint32_t DIEPCTL;             /*!< dev IN Endpoint Control Register,          Address offset: 900h + (ep_num * 20h) + 00h */
1698   __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 04h */
1699   __IO uint32_t DIEPINT;             /*!< dev IN Endpoint Itr Register,              Address offset: 900h + (ep_num * 20h) + 08h */
1700   __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 0Ch */
1701   __IO uint32_t DIEPTSIZ;            /*!< IN Endpoint Txfer Size Register,           Address offset: 900h + (ep_num * 20h) + 10h */
1702   __IO uint32_t DIEPDMA;             /*!< IN Endpoint DMA Address Register,          Address offset: 900h + (ep_num * 20h) + 14h */
1703   __IO uint32_t DTXFSTS;             /*!< IN Endpoint Tx FIFO Status Register,       Address offset: 900h + (ep_num * 20h) + 18h */
1704   __IO uint32_t Reserved18;          /*!< Reserved,                                  Address offset: 900h + (ep_num * 20h) + 1Ch */
1705 } USB_OTG_INEndpointTypeDef;
1706 
1707 /**
1708   * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1709   */
1710 typedef struct
1711 {
1712   __IO uint32_t DOEPCTL;             /*!< dev OUT Endpoint Control Register,         Address offset: B00h + (ep_num * 20h) + 00h */
1713   __IO uint32_t Reserved04;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 04h */
1714   __IO uint32_t DOEPINT;             /*!< dev OUT Endpoint Itr Register,             Address offset: B00h + (ep_num * 20h) + 08h */
1715   __IO uint32_t Reserved0C;          /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 0Ch */
1716   __IO uint32_t DOEPTSIZ;            /*!< dev OUT Endpoint Txfer Size Register,      Address offset: B00h + (ep_num * 20h) + 10h */
1717   __IO uint32_t DOEPDMA;             /*!< dev OUT Endpoint DMA Address Register,     Address offset: B00h + (ep_num * 20h) + 14h */
1718   __IO uint32_t Reserved18[2];       /*!< Reserved,                                  Address offset: B00h + (ep_num * 20h) + 18h */
1719 } USB_OTG_OUTEndpointTypeDef;
1720 
1721 /**
1722   * @brief USB_OTG_Host_Mode_Register_Structures
1723   */
1724 typedef struct
1725 {
1726   __IO uint32_t HCFG;                 /*!< Host Configuration Register,              Address offset: 400h */
1727   __IO uint32_t HFIR;                 /*!< Host Frame Interval Register,             Address offset: 404h */
1728   __IO uint32_t HFNUM;                /*!< Host Frame Nbr/Frame Remaining,           Address offset: 408h */
1729   uint32_t Reserved40C;               /*!< Reserved,                                 Address offset: 40Ch */
1730   __IO uint32_t HPTXSTS;              /*!< Host Periodic Tx FIFO/ Queue Status,      Address offset: 410h */
1731   __IO uint32_t HAINT;                /*!< Host All Channels Interrupt Register,     Address offset: 414h */
1732   __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask,         Address offset: 418h */
1733 } USB_OTG_HostTypeDef;
1734 
1735 /**
1736   * @brief USB_OTG_Host_Channel_Specific_Registers
1737   */
1738 typedef struct
1739 {
1740   __IO uint32_t HCCHAR;               /*!< Host Channel Characteristics Register,    Address offset: 500h */
1741   __IO uint32_t HCSPLT;               /*!< Host Channel Split Control Register,      Address offset: 504h */
1742   __IO uint32_t HCINT;                /*!< Host Channel Interrupt Register,          Address offset: 508h */
1743   __IO uint32_t HCINTMSK;             /*!< Host Channel Interrupt Mask Register,     Address offset: 50Ch */
1744   __IO uint32_t HCTSIZ;               /*!< Host Channel Transfer Size Register,      Address offset: 510h */
1745   __IO uint32_t HCDMA;                /*!< Host Channel DMA Address Register,        Address offset: 514h */
1746   uint32_t Reserved[2];               /*!< Reserved,                                 Address offset: 518h */
1747 } USB_OTG_HostChannelTypeDef;
1748 
1749 /**
1750   * @brief FD Controller Area Network
1751   */
1752 typedef struct
1753 {
1754   __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
1755   __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
1756        uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
1757   __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
1758   __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
1759   __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
1760   __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
1761   __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
1762   __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
1763   __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
1764   __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
1765   __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
1766        uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
1767   __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
1768   __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
1769   __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
1770        uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
1771   __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
1772   __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
1773   __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
1774   __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
1775        uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
1776   __IO uint32_t RXGFC;        /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
1777   __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x084 */
1778   __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x088 */
1779        uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
1780   __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x090 */
1781   __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x094 */
1782   __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x098 */
1783   __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x09C */
1784        uint32_t RESERVED6[8]; /*!< Reserved,                                                                0x0A0 - 0x0BC */
1785   __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
1786   __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
1787   __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0C8 */
1788   __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0CC */
1789   __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D0 */
1790   __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D4 */
1791   __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0D8 */
1792   __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
1793   __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
1794   __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0E4 */
1795   __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0E8 */
1796 } FDCAN_GlobalTypeDef;
1797 
1798 /**
1799   * @brief FD Controller Area Network Configuration
1800   */
1801 typedef struct
1802 {
1803   __IO uint32_t CKDIV;        /*!< FDCAN clock divider register,                            Address offset: 0x100 + 0x000 */
1804        uint32_t RESERVED1[128];/*!< Reserved,                                               0x100 + 0x004 - 0x100 + 0x200 */
1805   __IO uint32_t OPTR;         /*!< FDCAN option register,                                   Address offset: 0x100 + 0x204 */
1806        uint32_t RESERVED2[58];/*!< Reserved,                                                0x100 + 0x208 - 0x100 + 0x2EC */
1807   __IO uint32_t HWCFG;        /*!< FDCAN hardware configuration register,                   Address offset: 0x100 + 0x2F0 */
1808   __IO uint32_t VERR;         /*!< FDCAN IP version register,                               Address offset: 0x100 + 0x2F4 */
1809   __IO uint32_t IPIDR;        /*!< FDCAN IP ID register,                                    Address offset: 0x100 + 0x2F8 */
1810   __IO uint32_t SIDR;         /*!< FDCAN size ID register,                                  Address offset: 0x100 + 0x2FC */
1811 } FDCAN_Config_TypeDef;
1812 
1813 /**
1814   * @brief Flexible Memory Controller
1815   */
1816 typedef struct
1817 {
1818   __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
1819   __IO uint32_t PCSCNTR;     /*!< PSRAM chip-select counter register,                                               Address offset:    0x20 */
1820 } FMC_Bank1_TypeDef;
1821 
1822 /**
1823   * @brief Flexible Memory Controller Bank1E
1824   */
1825 typedef struct
1826 {
1827   __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1828 } FMC_Bank1E_TypeDef;
1829 
1830 /**
1831   * @brief Flexible Memory Controller Bank3
1832   */
1833 typedef struct
1834 {
1835   __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
1836   __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
1837   __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
1838   __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
1839   uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
1840   __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
1841 } FMC_Bank3_TypeDef;
1842 
1843 /**
1844   * @brief VREFBUF
1845   */
1846 typedef struct
1847 {
1848   __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
1849   __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
1850 } VREFBUF_TypeDef;
1851 
1852 /**
1853   * @brief ADC
1854   */
1855 typedef struct
1856 {
1857   __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                 Address offset: 0x00 */
1858   __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                     Address offset: 0x04 */
1859   __IO uint32_t CR;               /*!< ADC control register,                              Address offset: 0x08 */
1860   __IO uint32_t CFGR1;            /*!< ADC Configuration register,                        Address offset: 0x0C */
1861   __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                      Address offset: 0x10 */
1862   __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                        Address offset: 0x14 */
1863   __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                        Address offset: 0x18 */ /* Specific to ADC 14Bits*/
1864   __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                         Address offset: 0x1C */
1865   __IO uint32_t AWD1TR;           /*!< ADC watchdog threshold register,                   Address offset: 0x20 */ /* Specific to ADC 12Bits*/
1866   __IO uint32_t AWD2TR;           /*!< ADC watchdog threshold register,                   Address offset: 0x24 */ /* Specific to ADC 12Bits*/
1867   __IO uint32_t CHSELR;           /*!< ADC channel select register,                       Address offset: 0x28 */ /* Specific to ADC 12Bits*/
1868   __IO uint32_t AWD3TR;           /*!< ADC watchdog threshold register,                   Address offset: 0x2C */ /* Specific to ADC 12Bits*/
1869   __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                   Address offset: 0x30 */ /* Specific to ADC 14Bits*/
1870   __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                   Address offset: 0x34 */ /* Specific to ADC 14Bits*/
1871   __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                   Address offset: 0x38 */ /* Specific to ADC 14Bits*/
1872   __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                   Address offset: 0x3C */ /* Specific to ADC 14Bits*/
1873   __IO uint32_t DR;               /*!< ADC regular data register,                         Address offset: 0x40 */
1874   __IO uint32_t PWRR;             /*!< ADC power register,                                Address offset: 0x44 */
1875   uint32_t      RESERVED1;        /*!< Reserved, 0x048                                                         */
1876   __IO uint32_t JSQR;             /*!< ADC injected sequence register,                    Address offset: 0x4C */ /* Specific to ADC 14Bits*/
1877   uint32_t      RESERVED2[4];     /*!< Reserved, 0x050 - 0x05C                                                 */
1878   __IO uint32_t OFR1;             /*!< ADC offset register 1,                             Address offset: 0x60 */ /* Specific to ADC 14Bits*/
1879   __IO uint32_t OFR2;             /*!< ADC offset register 2,                             Address offset: 0x64 */ /* Specific to ADC 14Bits*/
1880   __IO uint32_t OFR3;             /*!< ADC offset register 3,                             Address offset: 0x68 */ /* Specific to ADC 14Bits*/
1881   __IO uint32_t OFR4;             /*!< ADC offset register 4,                             Address offset: 0x6C */ /* Specific to ADC 14Bits*/
1882   __IO uint32_t GCOMP;            /*!< ADC gain compensation register,                    Address offset: 0x70 */ /* Specific to ADC 14Bits*/
1883   uint32_t      RESERVED3[3];     /*!< Reserved, 0x074 - 0x07C                                                 */
1884   __IO uint32_t JDR1;             /*!< ADC injected data register 1,                      Address offset: 0x80 */ /* Specific to ADC 14Bits*/
1885   __IO uint32_t JDR2;             /*!< ADC injected data register 2,                      Address offset: 0x84 */ /* Specific to ADC 14Bits*/
1886   __IO uint32_t JDR3;             /*!< ADC injected data register 3,                      Address offset: 0x88 */ /* Specific to ADC 14Bits*/
1887   __IO uint32_t JDR4;             /*!< ADC injected data register 4,                      Address offset: 0x8C */ /* Specific to ADC 14Bits*/
1888   uint32_t      RESERVED4[4];     /*!< Reserved, 0x090 - 0x09C                                                 */
1889   __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,     Address offset: 0xA0 */
1890   __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,     Address offset: 0xA4 */
1891   __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,           Address offset: 0xA8 */ /* Specific to ADC 14Bits*/
1892   __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,          Address offset: 0xAC */ /* Specific to ADC 14Bits*/
1893   __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,           Address offset: 0xB0 */ /* Specific to ADC 14Bits*/
1894   __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,          Address offset: 0xB4 */ /* Specific to ADC 14Bits*/
1895   __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,           Address offset: 0xB8 */ /* Specific to ADC 14Bits*/
1896   __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,          Address offset: 0xBC */ /* Specific to ADC 14Bits*/
1897   __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,         Address offset: 0xC0 */ /* Specific to ADC 14Bits*/
1898   __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                          Address offset: 0xC4 */
1899   __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                Address offset: 0xC8 */ /* Specific to ADC 14Bits*/
1900   uint32_t      RESERVED5;        /*!< Reserved, 0x0CC                                                         */
1901   __IO uint32_t OR;               /*!< ADC  Option Register,                              Address offset: 0xD0 */  /* Specific to ADC 12Bits*/
1902 } ADC_TypeDef;
1903 
1904 typedef struct
1905 {
1906   __IO uint32_t CSR;            /*!< ADC common status register,                         Address offset: 0x300 */
1907   uint32_t RESERVED;            /*!< Reserved,                                           Address offset: 0x304 */
1908   __IO uint32_t CCR;            /*!< ADC common control register,                        Address offset: 0x308 */
1909   __IO uint32_t CDR;            /*!< ADC common regular data register for dual mode,         Address offset: 0x30C */
1910   __IO uint32_t CDR2;           /*!< ADC common regular data register for 32-bit dual mode,  Address offset: 0x310 */
1911 } ADC_Common_TypeDef;
1912 
1913 
1914 /* Legacy registers naming */
1915 #define PW      PWRR
1916 
1917 /**
1918   * @brief CORDIC
1919   */
1920 typedef struct
1921 {
1922   __IO uint32_t CSR;           /*!< CORDIC control and status register,        Address offset: 0x00 */
1923   __IO uint32_t WDATA;         /*!< CORDIC argument register,                  Address offset: 0x04 */
1924   __IO uint32_t RDATA;         /*!< CORDIC result register,                    Address offset: 0x08 */
1925 } CORDIC_TypeDef;
1926 
1927 /**
1928   * @brief IWDG
1929   */
1930 typedef struct
1931 {
1932   __IO uint32_t KR;            /*!< IWDG Key register,          Address offset: 0x00 */
1933   __IO uint32_t PR;            /*!< IWDG Prescaler register,    Address offset: 0x04 */
1934   __IO uint32_t RLR;           /*!< IWDG Reload register,       Address offset: 0x08 */
1935   __IO uint32_t SR;            /*!< IWDG Status register,       Address offset: 0x0C */
1936   __IO uint32_t WINR;          /*!< IWDG Window register,       Address offset: 0x10 */
1937   __IO uint32_t EWCR;          /*!< IWDG Early Wakeup register, Address offset: 0x14 */
1938 } IWDG_TypeDef;
1939 
1940 /**
1941   * @brief SPI
1942   */
1943 typedef struct
1944 {
1945   __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
1946   __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
1947   __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
1948   __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
1949   __IO uint32_t IER;           /*!< SPI Interrupt Enable register,                   Address offset: 0x10 */
1950   __IO uint32_t SR;            /*!< SPI Status register,                             Address offset: 0x14 */
1951   __IO uint32_t IFCR;          /*!< SPI Interrupt/Status Flags Clear register,       Address offset: 0x18 */
1952   __IO uint32_t AUTOCR;        /*!< SPI Autonomous Mode Control register,            Address offset: 0x1C */
1953   __IO uint32_t TXDR;          /*!< SPI Transmit data register,                      Address offset: 0x20 */
1954   uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
1955   __IO uint32_t RXDR;          /*!< SPI/I2S data register,                           Address offset: 0x30 */
1956   uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
1957   __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
1958   __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
1959   __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
1960   __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
1961 } SPI_TypeDef;
1962 
1963 /**
1964   * @brief Touch Sensing Controller (TSC)
1965   */
1966 
1967 typedef struct
1968 {
1969   __IO uint32_t CR;          /*!< TSC control register,                                     Address offset: 0x00 */
1970   __IO uint32_t IER;         /*!< TSC interrupt enable register,                            Address offset: 0x04 */
1971   __IO uint32_t ICR;         /*!< TSC interrupt clear register,                             Address offset: 0x08 */
1972   __IO uint32_t ISR;         /*!< TSC interrupt status register,                            Address offset: 0x0C */
1973   __IO uint32_t IOHCR;       /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
1974   uint32_t      RESERVED1;   /*!< Reserved,                                                 Address offset: 0x14 */
1975   __IO uint32_t IOASCR;      /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
1976   uint32_t      RESERVED2;   /*!< Reserved,                                                 Address offset: 0x1C */
1977   __IO uint32_t IOSCR;       /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
1978   uint32_t      RESERVED3;   /*!< Reserved,                                                 Address offset: 0x24 */
1979   __IO uint32_t IOCCR;       /*!< TSC I/O channel control register,                         Address offset: 0x28 */
1980   uint32_t      RESERVED4;   /*!< Reserved,                                                 Address offset: 0x2C */
1981   __IO uint32_t IOGCSR;      /*!< TSC I/O group control status register,                    Address offset: 0x30 */
1982   __IO uint32_t IOGXCR[8];   /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
1983 } TSC_TypeDef;
1984 
1985 /**
1986   * @brief WWDG
1987   */
1988 typedef struct
1989 {
1990   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
1991   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
1992   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
1993 } WWDG_TypeDef;
1994 
1995 /*@}*/ /* end of group STM32U5xx_peripherals */
1996 
1997 
1998 /* --------  End of section using anonymous unions and disabling warnings  -------- */
1999 #if   defined (__CC_ARM)
2000   #pragma pop
2001 #elif defined (__ICCARM__)
2002   /* leave anonymous unions enabled */
2003 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
2004   #pragma clang diagnostic pop
2005 #elif defined (__GNUC__)
2006   /* anonymous unions are enabled by default */
2007 #elif defined (__TMS470__)
2008   /* anonymous unions are enabled by default */
2009 #elif defined (__TASKING__)
2010   #pragma warning restore
2011 #elif defined (__CSMC__)
2012   /* anonymous unions are enabled by default */
2013 #else
2014   #warning Not supported compiler type
2015 #endif
2016 
2017 
2018 /* =========================================================================================================================== */
2019 /* ================                          Device Specific Peripheral Address Map                           ================ */
2020 /* =========================================================================================================================== */
2021 
2022 
2023 /** @addtogroup STM32U5xx_Peripheral_peripheralAddr
2024   * @{
2025   */
2026 
2027 /* Internal SRAMs size */
2028 #define SRAM1_SIZE               (0xC0000UL)    /*!< SRAM1=768k */
2029 #define SRAM2_SIZE               (0x10000UL)    /*!< SRAM2=64k  */
2030 #define SRAM3_SIZE               (0xD0000UL)    /*!< SRAM3=832k */
2031 #define SRAM4_SIZE               (0x04000UL)    /*!< SRAM4=16k  */
2032 #define SRAM5_SIZE               (0xD0000UL)    /*!< SRAM5=832k */
2033 #define SRAM6_SIZE               (0x80000UL)    /*!< SRAM6=512k */
2034 
2035 /* External memories base addresses - Not aliased */
2036 #define FMC_BASE                 (0x60000000UL) /*!< FMC base address                                   */
2037 #define OCTOSPI2_BASE            (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */
2038 #define OCTOSPI1_BASE            (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */
2039 #define HSPI1_BASE               (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address    */
2040 
2041 #define FMC_BANK1                FMC_BASE
2042 #define FMC_BANK1_1              FMC_BANK1
2043 #define FMC_BANK1_2              (FMC_BANK1 + 0x04000000UL)
2044 #define FMC_BANK1_3              (FMC_BANK1 + 0x08000000UL)
2045 #define FMC_BANK1_4              (FMC_BANK1 + 0x0C000000UL)
2046 #define FMC_BANK3                (FMC_BASE  + 0x20000000UL)
2047 
2048 /* Flash, Peripheral and internal SRAMs base addresses - Non secure */
2049 #define FLASH_BASE_NS            (0x08000000UL) /*!< FLASH (4 MB) non-secure base address               */
2050 #define SRAM1_BASE_NS            (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address             */
2051 #define SRAM2_BASE_NS            (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address              */
2052 #define SRAM3_BASE_NS            (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address             */
2053 #define SRAM4_BASE_NS            (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address              */
2054 #define SRAM5_BASE_NS            (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address             */
2055 #define SRAM6_BASE_NS            (0x20270000UL) /*!< SRAM6 (512 KB) non-secure base address             */
2056 #define PERIPH_BASE_NS           (0x40000000UL) /*!< Peripheral non-secure base address                 */
2057 
2058 /* Peripheral memory map - Non secure */
2059 #define APB1PERIPH_BASE_NS       PERIPH_BASE_NS
2060 #define APB2PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x00010000UL)
2061 #define AHB1PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x00020000UL)
2062 #define AHB2PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x02020000UL)
2063 #define APB3PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x06000000UL)
2064 #define AHB3PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x06020000UL)
2065 
2066 /*!< APB1 Non secure peripherals */
2067 #define TIM2_BASE_NS             (APB1PERIPH_BASE_NS + 0x0000UL)
2068 #define TIM3_BASE_NS             (APB1PERIPH_BASE_NS + 0x0400UL)
2069 #define TIM4_BASE_NS             (APB1PERIPH_BASE_NS + 0x0800UL)
2070 #define TIM5_BASE_NS             (APB1PERIPH_BASE_NS + 0x0C00UL)
2071 #define TIM6_BASE_NS             (APB1PERIPH_BASE_NS + 0x1000UL)
2072 #define TIM7_BASE_NS             (APB1PERIPH_BASE_NS + 0x1400UL)
2073 #define WWDG_BASE_NS             (APB1PERIPH_BASE_NS + 0x2C00UL)
2074 #define IWDG_BASE_NS             (APB1PERIPH_BASE_NS + 0x3000UL)
2075 #define SPI2_BASE_NS             (APB1PERIPH_BASE_NS + 0x3800UL)
2076 #define USART2_BASE_NS           (APB1PERIPH_BASE_NS + 0x4400UL)
2077 #define USART3_BASE_NS           (APB1PERIPH_BASE_NS + 0x4800UL)
2078 #define UART4_BASE_NS            (APB1PERIPH_BASE_NS + 0x4C00UL)
2079 #define UART5_BASE_NS            (APB1PERIPH_BASE_NS + 0x5000UL)
2080 #define I2C1_BASE_NS             (APB1PERIPH_BASE_NS + 0x5400UL)
2081 #define I2C2_BASE_NS             (APB1PERIPH_BASE_NS + 0x5800UL)
2082 #define CRS_BASE_NS              (APB1PERIPH_BASE_NS + 0x6000UL)
2083 #define USART6_BASE_NS           (APB1PERIPH_BASE_NS + 0x6400UL)
2084 #define I2C4_BASE_NS             (APB1PERIPH_BASE_NS + 0x8400UL)
2085 #define LPTIM2_BASE_NS           (APB1PERIPH_BASE_NS + 0x9400UL)
2086 #define I2C5_BASE_NS             (APB1PERIPH_BASE_NS + 0x9800UL)
2087 #define I2C6_BASE_NS             (APB1PERIPH_BASE_NS + 0x9C00UL)
2088 #define FDCAN1_BASE_NS           (APB1PERIPH_BASE_NS + 0xA400UL)
2089 #define FDCAN_CONFIG_BASE_NS     (APB1PERIPH_BASE_NS + 0xA500UL)
2090 #define SRAMCAN_BASE_NS          (APB1PERIPH_BASE_NS + 0xAC00UL)
2091 #define UCPD1_BASE_NS            (APB1PERIPH_BASE_NS + 0xDC00UL)
2092 
2093 /*!< APB2 Non secure peripherals */
2094 #define TIM1_BASE_NS             (APB2PERIPH_BASE_NS + 0x2C00UL)
2095 #define SPI1_BASE_NS             (APB2PERIPH_BASE_NS + 0x3000UL)
2096 #define TIM8_BASE_NS             (APB2PERIPH_BASE_NS + 0x3400UL)
2097 #define USART1_BASE_NS           (APB2PERIPH_BASE_NS + 0x3800UL)
2098 #define TIM15_BASE_NS            (APB2PERIPH_BASE_NS + 0x4000UL)
2099 #define TIM16_BASE_NS            (APB2PERIPH_BASE_NS + 0x4400UL)
2100 #define TIM17_BASE_NS            (APB2PERIPH_BASE_NS + 0x4800UL)
2101 #define SAI1_BASE_NS             (APB2PERIPH_BASE_NS + 0x5400UL)
2102 #define SAI1_Block_A_BASE_NS     (SAI1_BASE_NS + 0x004UL)
2103 #define SAI1_Block_B_BASE_NS     (SAI1_BASE_NS + 0x024UL)
2104 #define SAI2_BASE_NS             (APB2PERIPH_BASE_NS + 0x5800UL)
2105 #define SAI2_Block_A_BASE_NS     (SAI2_BASE_NS + 0x004UL)
2106 #define SAI2_Block_B_BASE_NS     (SAI2_BASE_NS + 0x024UL)
2107 #define LTDC_BASE_NS             (APB2PERIPH_BASE_NS + 0x6800UL)
2108 #define LTDC_Layer1_BASE_NS      (LTDC_BASE_NS + 0x0084UL)
2109 #define LTDC_Layer2_BASE_NS      (LTDC_BASE_NS + 0x0104UL)
2110 #define GFXTIM_BASE_NS           (APB2PERIPH_BASE_NS + 0x6400UL)
2111 #define DSI_BASE_NS              (APB2PERIPH_BASE_NS + 0x6C00UL)
2112 #define REFBIAS_BASE_NS          (DSI_BASE_NS + 0x800UL)
2113 #define DPHY_BASE_NS             (DSI_BASE_NS + 0xC00UL)
2114 
2115 /*!< APB3 Non secure peripherals */
2116 #define SYSCFG_BASE_NS           (APB3PERIPH_BASE_NS + 0x0400UL)
2117 #define SPI3_BASE_NS             (APB3PERIPH_BASE_NS + 0x2000UL)
2118 #define LPUART1_BASE_NS          (APB3PERIPH_BASE_NS + 0x2400UL)
2119 #define I2C3_BASE_NS             (APB3PERIPH_BASE_NS + 0x2800UL)
2120 #define LPTIM1_BASE_NS           (APB3PERIPH_BASE_NS + 0x4400UL)
2121 #define LPTIM3_BASE_NS           (APB3PERIPH_BASE_NS + 0x4800UL)
2122 #define LPTIM4_BASE_NS           (APB3PERIPH_BASE_NS + 0x4C00UL)
2123 #define OPAMP_BASE_NS            (APB3PERIPH_BASE_NS + 0x5000UL)
2124 #define OPAMP1_BASE_NS           (APB3PERIPH_BASE_NS + 0x5000UL)
2125 #define OPAMP2_BASE_NS           (APB3PERIPH_BASE_NS + 0x5010UL)
2126 #define COMP12_BASE_NS           (APB3PERIPH_BASE_NS + 0x5400UL)
2127 #define COMP1_BASE_NS            (COMP12_BASE_NS)
2128 #define COMP2_BASE_NS            (COMP12_BASE_NS + 0x04UL)
2129 #define VREFBUF_BASE_NS          (APB3PERIPH_BASE_NS + 0x7400UL)
2130 #define RTC_BASE_NS              (APB3PERIPH_BASE_NS + 0x7800UL)
2131 #define TAMP_BASE_NS             (APB3PERIPH_BASE_NS + 0x7C00UL)
2132 
2133 /*!< AHB1 Non secure peripherals */
2134 #define GPDMA1_BASE_NS           (AHB1PERIPH_BASE_NS)
2135 #define GPDMA1_Channel0_BASE_NS  (GPDMA1_BASE_NS + 0x0050UL)
2136 #define GPDMA1_Channel1_BASE_NS  (GPDMA1_BASE_NS + 0x00D0UL)
2137 #define GPDMA1_Channel2_BASE_NS  (GPDMA1_BASE_NS + 0x0150UL)
2138 #define GPDMA1_Channel3_BASE_NS  (GPDMA1_BASE_NS + 0x01D0UL)
2139 #define GPDMA1_Channel4_BASE_NS  (GPDMA1_BASE_NS + 0x0250UL)
2140 #define GPDMA1_Channel5_BASE_NS  (GPDMA1_BASE_NS + 0x02D0UL)
2141 #define GPDMA1_Channel6_BASE_NS  (GPDMA1_BASE_NS + 0x0350UL)
2142 #define GPDMA1_Channel7_BASE_NS  (GPDMA1_BASE_NS + 0x03D0UL)
2143 #define GPDMA1_Channel8_BASE_NS  (GPDMA1_BASE_NS + 0x0450UL)
2144 #define GPDMA1_Channel9_BASE_NS  (GPDMA1_BASE_NS + 0x04D0UL)
2145 #define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL)
2146 #define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL)
2147 #define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL)
2148 #define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL)
2149 #define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL)
2150 #define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL)
2151 #define CORDIC_BASE_NS           (AHB1PERIPH_BASE_NS + 0x01000UL)
2152 #define FMAC_BASE_NS             (AHB1PERIPH_BASE_NS + 0x01400UL)
2153 #define FLASH_R_BASE_NS          (AHB1PERIPH_BASE_NS + 0x02000UL)
2154 #define CRC_BASE_NS              (AHB1PERIPH_BASE_NS + 0x03000UL)
2155 #define TSC_BASE_NS              (AHB1PERIPH_BASE_NS + 0x04000UL)
2156 #define MDF1_BASE_NS             (AHB1PERIPH_BASE_NS + 0x05000UL)
2157 #define MDF1_Filter0_BASE_NS     (MDF1_BASE_NS + 0x80UL)
2158 #define MDF1_Filter1_BASE_NS     (MDF1_BASE_NS + 0x100UL)
2159 #define MDF1_Filter2_BASE_NS     (MDF1_BASE_NS + 0x180UL)
2160 #define MDF1_Filter3_BASE_NS     (MDF1_BASE_NS + 0x200UL)
2161 #define MDF1_Filter4_BASE_NS     (MDF1_BASE_NS + 0x280UL)
2162 #define MDF1_Filter5_BASE_NS     (MDF1_BASE_NS + 0x300UL)
2163 #define RAMCFG_BASE_NS           (AHB1PERIPH_BASE_NS + 0x06000UL)
2164 #define RAMCFG_SRAM1_BASE_NS     (RAMCFG_BASE_NS)
2165 #define RAMCFG_SRAM2_BASE_NS     (RAMCFG_BASE_NS + 0x0040UL)
2166 #define RAMCFG_SRAM3_BASE_NS     (RAMCFG_BASE_NS + 0x0080UL)
2167 #define RAMCFG_SRAM4_BASE_NS     (RAMCFG_BASE_NS + 0x00C0UL)
2168 #define RAMCFG_BKPRAM_BASE_NS    (RAMCFG_BASE_NS + 0x0100UL)
2169 #define RAMCFG_SRAM5_BASE_NS     (RAMCFG_BASE_NS + 0x0140UL)
2170 #define RAMCFG_SRAM6_BASE_NS     (RAMCFG_BASE_NS + 0x0180UL)
2171 #define JPEG_BASE_NS             (AHB1PERIPH_BASE_NS + 0x0A000UL)
2172 #define DMA2D_BASE_NS            (AHB1PERIPH_BASE_NS + 0x0B000UL)
2173 #define GFXMMU_BASE_NS           (AHB1PERIPH_BASE_NS + 0x0C000UL)
2174 #define GPU2D_BASE_NS            (AHB1PERIPH_BASE_NS + 0x0F000UL)
2175 #define ICACHE_BASE_NS           (AHB1PERIPH_BASE_NS + 0x10400UL)
2176 #define DCACHE1_BASE_NS          (AHB1PERIPH_BASE_NS + 0x11400UL)
2177 #define DCACHE2_BASE_NS          (AHB1PERIPH_BASE_NS + 0x11800UL)
2178 #define GTZC_TZSC1_BASE_NS       (AHB1PERIPH_BASE_NS + 0x12400UL)
2179 #define GTZC_TZIC1_BASE_NS       (AHB1PERIPH_BASE_NS + 0x12800UL)
2180 #define GTZC_MPCBB1_BASE_NS      (AHB1PERIPH_BASE_NS + 0x12C00UL)
2181 #define GTZC_MPCBB2_BASE_NS      (AHB1PERIPH_BASE_NS + 0x13000UL)
2182 #define GTZC_MPCBB3_BASE_NS      (AHB1PERIPH_BASE_NS + 0x13400UL)
2183 #define GTZC_MPCBB5_BASE_NS      (AHB1PERIPH_BASE_NS + 0x13800UL)
2184 #define GTZC_MPCBB6_BASE_NS      (AHB1PERIPH_BASE_NS + 0x13C00UL)
2185 #define BKPSRAM_BASE_NS          (AHB1PERIPH_BASE_NS + 0x16400UL)
2186 
2187 /*!< AHB2 Non secure peripherals */
2188 #define GPIOA_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00000UL)
2189 #define GPIOB_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00400UL)
2190 #define GPIOC_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00800UL)
2191 #define GPIOD_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00C00UL)
2192 #define GPIOE_BASE_NS            (AHB2PERIPH_BASE_NS + 0x01000UL)
2193 #define GPIOF_BASE_NS            (AHB2PERIPH_BASE_NS + 0x01400UL)
2194 #define GPIOG_BASE_NS            (AHB2PERIPH_BASE_NS + 0x01800UL)
2195 #define GPIOH_BASE_NS            (AHB2PERIPH_BASE_NS + 0x01C00UL)
2196 #define GPIOI_BASE_NS            (AHB2PERIPH_BASE_NS + 0x02000UL)
2197 #define GPIOJ_BASE_NS            (AHB2PERIPH_BASE_NS + 0x02400UL)
2198 #define ADC1_BASE_NS             (AHB2PERIPH_BASE_NS + 0x08000UL)
2199 #define ADC2_BASE_NS             (AHB2PERIPH_BASE_NS + 0x08100UL)
2200 #define ADC12_COMMON_BASE_NS     (AHB2PERIPH_BASE_NS + 0x08300UL)
2201 #define DCMI_BASE_NS             (AHB2PERIPH_BASE_NS + 0x0C000UL)
2202 #define PSSI_BASE_NS             (AHB2PERIPH_BASE_NS + 0x0C400UL)
2203 #define USB_OTG_HS_BASE_NS       (AHB2PERIPH_BASE_NS + 0x20000UL)
2204 #define AES_BASE_NS              (AHB2PERIPH_BASE_NS + 0xA0000UL)
2205 #define HASH_BASE_NS             (AHB2PERIPH_BASE_NS + 0xA0400UL)
2206 #define HASH_DIGEST_BASE_NS      (AHB2PERIPH_BASE_NS + 0xA0710UL)
2207 #define RNG_BASE_NS              (AHB2PERIPH_BASE_NS + 0xA0800UL)
2208 #define SAES_BASE_NS             (AHB2PERIPH_BASE_NS + 0xA0C00UL)
2209 #define PKA_BASE_NS              (AHB2PERIPH_BASE_NS + 0xA2000UL)
2210 #define PKA_RAM_BASE_NS          (AHB2PERIPH_BASE_NS + 0xA2400UL)
2211 #define OCTOSPIM_R_BASE_NS       (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */
2212 #define OTFDEC1_BASE_NS          (AHB2PERIPH_BASE_NS + 0xA5000UL)
2213 #define OTFDEC1_REGION1_BASE_NS  (OTFDEC1_BASE_NS + 0x20UL)
2214 #define OTFDEC1_REGION2_BASE_NS  (OTFDEC1_BASE_NS + 0x50UL)
2215 #define OTFDEC1_REGION3_BASE_NS  (OTFDEC1_BASE_NS + 0x80UL)
2216 #define OTFDEC1_REGION4_BASE_NS  (OTFDEC1_BASE_NS + 0xB0UL)
2217 #define OTFDEC2_BASE_NS          (AHB2PERIPH_BASE_NS + 0xA5400UL)
2218 #define OTFDEC2_REGION1_BASE_NS  (OTFDEC2_BASE_NS + 0x20UL)
2219 #define OTFDEC2_REGION2_BASE_NS  (OTFDEC2_BASE_NS + 0x50UL)
2220 #define OTFDEC2_REGION3_BASE_NS  (OTFDEC2_BASE_NS + 0x80UL)
2221 #define OTFDEC2_REGION4_BASE_NS  (OTFDEC2_BASE_NS + 0xB0UL)
2222 #define SDMMC1_BASE_NS           (AHB2PERIPH_BASE_NS + 0xA8000UL)
2223 #define SDMMC2_BASE_NS           (AHB2PERIPH_BASE_NS + 0xA8C00UL)
2224 #define DLYB_SDMMC1_BASE_NS      (AHB2PERIPH_BASE_NS + 0xA8400UL)
2225 #define DLYB_SDMMC2_BASE_NS      (AHB2PERIPH_BASE_NS + 0xA8800UL)
2226 #define DLYB_OCTOSPI1_BASE_NS    (AHB2PERIPH_BASE_NS + 0xAF000UL)
2227 #define DLYB_OCTOSPI2_BASE_NS    (AHB2PERIPH_BASE_NS + 0xAF400UL)
2228 #define FMC_R_BASE_NS            (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address              */
2229 /*!< FMC Banks Non secure registers base address */
2230 #define FMC_Bank1_R_BASE_NS      (FMC_R_BASE_NS + 0x0000UL)
2231 #define FMC_Bank1E_R_BASE_NS     (FMC_R_BASE_NS + 0x0104UL)
2232 #define FMC_Bank3_R_BASE_NS      (FMC_R_BASE_NS + 0x0080UL)
2233 #define OCTOSPI1_R_BASE_NS       (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address         */
2234 #define OCTOSPI2_R_BASE_NS       (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address         */
2235 #define HSPI1_R_BASE_NS          (AHB2PERIPH_BASE_NS + 0xB3400UL)
2236 
2237 /*!< AHB3 Non secure peripherals */
2238 #define LPGPIO1_BASE_NS          (AHB3PERIPH_BASE_NS)
2239 #define PWR_BASE_NS              (AHB3PERIPH_BASE_NS + 0x0800UL)
2240 #define RCC_BASE_NS              (AHB3PERIPH_BASE_NS + 0x0C00UL)
2241 #define ADC4_BASE_NS             (AHB3PERIPH_BASE_NS + 0x1000UL)
2242 #define ADC4_COMMON_BASE_NS      (AHB3PERIPH_BASE_NS + 0x1300UL)
2243 #define DAC1_BASE_NS             (AHB3PERIPH_BASE_NS + 0x1800UL)
2244 #define EXTI_BASE_NS             (AHB3PERIPH_BASE_NS + 0x2000UL)
2245 #define GTZC_TZSC2_BASE_NS       (AHB3PERIPH_BASE_NS + 0x3000UL)
2246 #define GTZC_TZIC2_BASE_NS       (AHB3PERIPH_BASE_NS + 0x3400UL)
2247 #define GTZC_MPCBB4_BASE_NS      (AHB3PERIPH_BASE_NS + 0x3800UL)
2248 #define ADF1_BASE_NS             (AHB3PERIPH_BASE_NS + 0x4000UL)
2249 #define ADF1_Filter0_BASE_NS     (ADF1_BASE_NS + 0x80UL)
2250 #define LPDMA1_BASE_NS           (AHB3PERIPH_BASE_NS + 0x5000UL)
2251 #define LPDMA1_Channel0_BASE_NS  (LPDMA1_BASE_NS + 0x0050UL)
2252 #define LPDMA1_Channel1_BASE_NS  (LPDMA1_BASE_NS + 0x00D0UL)
2253 #define LPDMA1_Channel2_BASE_NS  (LPDMA1_BASE_NS + 0x0150UL)
2254 #define LPDMA1_Channel3_BASE_NS  (LPDMA1_BASE_NS + 0x01D0UL)
2255 /* GFXMMU non secure virtual buffers base address */
2256 #define GFXMMU_VIRTUAL_BUFFERS_BASE_NS  (0x24000000UL)
2257 #define GFXMMU_VIRTUAL_BUFFER0_BASE_NS  (GFXMMU_VIRTUAL_BUFFERS_BASE_NS)
2258 #define GFXMMU_VIRTUAL_BUFFER1_BASE_NS  (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x400000UL)
2259 #define GFXMMU_VIRTUAL_BUFFER2_BASE_NS  (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x800000UL)
2260 #define GFXMMU_VIRTUAL_BUFFER3_BASE_NS  (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0xC00000UL)
2261 
2262 /* Flash, Peripheral and internal SRAMs base addresses - Secure */
2263 #define FLASH_BASE_S            (0x0C000000UL) /*!< FLASH (4 MB) secure base address       */
2264 #define SRAM1_BASE_S            (0x30000000UL) /*!< SRAM1 (768 KB) secure base address     */
2265 #define SRAM2_BASE_S            (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address      */
2266 #define SRAM3_BASE_S            (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address     */
2267 #define SRAM4_BASE_S            (0x38000000UL) /*!< SRAM4 (16 KB) secure base address      */
2268 #define SRAM5_BASE_S            (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address     */
2269 #define PERIPH_BASE_S           (0x50000000UL) /*!< Peripheral secure base address         */
2270 #define SRAM6_BASE_S            (0x30270000UL) /*!< SRAM6 (512 KB) secure base address     */
2271 
2272 /* Peripheral memory map - Secure */
2273 #define APB1PERIPH_BASE_S       PERIPH_BASE_S
2274 #define APB2PERIPH_BASE_S       (PERIPH_BASE_S + 0x00010000UL)
2275 #define AHB1PERIPH_BASE_S       (PERIPH_BASE_S + 0x00020000UL)
2276 #define AHB2PERIPH_BASE_S       (PERIPH_BASE_S + 0x02020000UL)
2277 #define APB3PERIPH_BASE_S       (PERIPH_BASE_S + 0x06000000UL)
2278 #define AHB3PERIPH_BASE_S       (PERIPH_BASE_S + 0x06020000UL)
2279 
2280 /*!< APB1 Secure peripherals */
2281 #define TIM2_BASE_S             (APB1PERIPH_BASE_S + 0x0000UL)
2282 #define TIM3_BASE_S             (APB1PERIPH_BASE_S + 0x0400UL)
2283 #define TIM4_BASE_S             (APB1PERIPH_BASE_S + 0x0800UL)
2284 #define TIM5_BASE_S             (APB1PERIPH_BASE_S + 0x0C00UL)
2285 #define TIM6_BASE_S             (APB1PERIPH_BASE_S + 0x1000UL)
2286 #define TIM7_BASE_S             (APB1PERIPH_BASE_S + 0x1400UL)
2287 #define WWDG_BASE_S             (APB1PERIPH_BASE_S + 0x2C00UL)
2288 #define IWDG_BASE_S             (APB1PERIPH_BASE_S + 0x3000UL)
2289 #define SPI2_BASE_S             (APB1PERIPH_BASE_S + 0x3800UL)
2290 #define USART2_BASE_S           (APB1PERIPH_BASE_S + 0x4400UL)
2291 #define USART3_BASE_S           (APB1PERIPH_BASE_S + 0x4800UL)
2292 #define UART4_BASE_S            (APB1PERIPH_BASE_S + 0x4C00UL)
2293 #define UART5_BASE_S            (APB1PERIPH_BASE_S + 0x5000UL)
2294 #define I2C1_BASE_S             (APB1PERIPH_BASE_S + 0x5400UL)
2295 #define I2C2_BASE_S             (APB1PERIPH_BASE_S + 0x5800UL)
2296 #define USART6_BASE_S           (APB1PERIPH_BASE_S + 0x6400UL)
2297 #define I2C4_BASE_S             (APB1PERIPH_BASE_S + 0x8400UL)
2298 #define CRS_BASE_S              (APB1PERIPH_BASE_S + 0x6000UL)
2299 #define LPTIM2_BASE_S           (APB1PERIPH_BASE_S + 0x9400UL)
2300 #define I2C5_BASE_S             (APB1PERIPH_BASE_S + 0x9800UL)
2301 #define I2C6_BASE_S             (APB1PERIPH_BASE_S + 0x9C00UL)
2302 #define FDCAN1_BASE_S           (APB1PERIPH_BASE_S + 0xA400UL)
2303 #define FDCAN_CONFIG_BASE_S     (APB1PERIPH_BASE_S + 0xA500UL)
2304 #define SRAMCAN_BASE_S          (APB1PERIPH_BASE_S + 0xAC00UL)
2305 #define UCPD1_BASE_S            (APB1PERIPH_BASE_S + 0xDC00UL)
2306 
2307 /*!< APB2 Secure peripherals */
2308 #define TIM1_BASE_S             (APB2PERIPH_BASE_S + 0x2C00UL)
2309 #define SPI1_BASE_S             (APB2PERIPH_BASE_S + 0x3000UL)
2310 #define TIM8_BASE_S             (APB2PERIPH_BASE_S + 0x3400UL)
2311 #define USART1_BASE_S           (APB2PERIPH_BASE_S + 0x3800UL)
2312 #define TIM15_BASE_S            (APB2PERIPH_BASE_S + 0x4000UL)
2313 #define TIM16_BASE_S            (APB2PERIPH_BASE_S + 0x4400UL)
2314 #define TIM17_BASE_S            (APB2PERIPH_BASE_S + 0x4800UL)
2315 #define SAI1_BASE_S             (APB2PERIPH_BASE_S + 0x5400UL)
2316 #define SAI1_Block_A_BASE_S     (SAI1_BASE_S + 0x004UL)
2317 #define SAI1_Block_B_BASE_S     (SAI1_BASE_S + 0x024UL)
2318 #define SAI2_BASE_S             (APB2PERIPH_BASE_S + 0x5800UL)
2319 #define SAI2_Block_A_BASE_S     (SAI2_BASE_S + 0x004UL)
2320 #define SAI2_Block_B_BASE_S     (SAI2_BASE_S + 0x024UL)
2321 #define GFXTIM_BASE_S             (APB2PERIPH_BASE_S + 0x6400UL)
2322 #define LTDC_BASE_S             (APB2PERIPH_BASE_S + 0x6800UL)
2323 #define LTDC_Layer1_BASE_S      (LTDC_BASE_S + 0x0084UL)
2324 #define LTDC_Layer2_BASE_S      (LTDC_BASE_S + 0x0104UL)
2325 #define DSI_BASE_S              (APB2PERIPH_BASE_S + 0x6C00UL)
2326 #define REFBIAS_BASE_S          (DSI_BASE_S + 0x800UL)
2327 #define DPHY_BASE_S             (DSI_BASE_S + 0xC00UL)
2328 
2329 /*!< APB3 Secure peripherals */
2330 #define SYSCFG_BASE_S           (APB3PERIPH_BASE_S + 0x0400UL)
2331 #define SPI3_BASE_S             (APB3PERIPH_BASE_S + 0x2000UL)
2332 #define LPUART1_BASE_S          (APB3PERIPH_BASE_S + 0x2400UL)
2333 #define I2C3_BASE_S             (APB3PERIPH_BASE_S + 0x2800UL)
2334 #define LPTIM1_BASE_S           (APB3PERIPH_BASE_S + 0x4400UL)
2335 #define LPTIM3_BASE_S           (APB3PERIPH_BASE_S + 0x4800UL)
2336 #define LPTIM4_BASE_S           (APB3PERIPH_BASE_S + 0x4C00UL)
2337 #define OPAMP_BASE_S            (APB3PERIPH_BASE_S + 0x5000UL)
2338 #define OPAMP1_BASE_S           (APB3PERIPH_BASE_S + 0x5000UL)
2339 #define OPAMP2_BASE_S           (APB3PERIPH_BASE_S + 0x5010UL)
2340 #define COMP12_BASE_S           (APB3PERIPH_BASE_S + 0x5400UL)
2341 #define COMP1_BASE_S            (COMP12_BASE_S)
2342 #define COMP2_BASE_S            (COMP12_BASE_S + 0x04UL)
2343 #define VREFBUF_BASE_S          (APB3PERIPH_BASE_S + 0x7400UL)
2344 #define RTC_BASE_S              (APB3PERIPH_BASE_S + 0x7800UL)
2345 #define TAMP_BASE_S             (APB3PERIPH_BASE_S + 0x7C00UL)
2346 
2347 /*!< AHB1 Secure peripherals */
2348 #define GPDMA1_BASE_S           (AHB1PERIPH_BASE_S)
2349 #define GPDMA1_Channel0_BASE_S  (GPDMA1_BASE_S + 0x0050UL)
2350 #define GPDMA1_Channel1_BASE_S  (GPDMA1_BASE_S + 0x00D0UL)
2351 #define GPDMA1_Channel2_BASE_S  (GPDMA1_BASE_S + 0x0150UL)
2352 #define GPDMA1_Channel3_BASE_S  (GPDMA1_BASE_S + 0x01D0UL)
2353 #define GPDMA1_Channel4_BASE_S  (GPDMA1_BASE_S + 0x0250UL)
2354 #define GPDMA1_Channel5_BASE_S  (GPDMA1_BASE_S + 0x02D0UL)
2355 #define GPDMA1_Channel6_BASE_S  (GPDMA1_BASE_S + 0x0350UL)
2356 #define GPDMA1_Channel7_BASE_S  (GPDMA1_BASE_S + 0x03D0UL)
2357 #define GPDMA1_Channel8_BASE_S  (GPDMA1_BASE_S + 0x0450UL)
2358 #define GPDMA1_Channel9_BASE_S  (GPDMA1_BASE_S + 0x04D0UL)
2359 #define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL)
2360 #define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL)
2361 #define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL)
2362 #define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL)
2363 #define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL)
2364 #define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL)
2365 #define CORDIC_BASE_S           (AHB1PERIPH_BASE_S + 0x01000UL)
2366 #define FMAC_BASE_S             (AHB1PERIPH_BASE_S + 0x01400UL)
2367 #define FLASH_R_BASE_S          (AHB1PERIPH_BASE_S + 0x02000UL)
2368 #define CRC_BASE_S              (AHB1PERIPH_BASE_S + 0x03000UL)
2369 #define TSC_BASE_S              (AHB1PERIPH_BASE_S + 0x04000UL)
2370 #define MDF1_BASE_S             (AHB1PERIPH_BASE_S + 0x05000UL)
2371 #define MDF1_Filter0_BASE_S     (MDF1_BASE_S + 0x80UL)
2372 #define MDF1_Filter1_BASE_S     (MDF1_BASE_S + 0x100UL)
2373 #define MDF1_Filter2_BASE_S     (MDF1_BASE_S + 0x180UL)
2374 #define MDF1_Filter3_BASE_S     (MDF1_BASE_S + 0x200UL)
2375 #define MDF1_Filter4_BASE_S     (MDF1_BASE_S + 0x280UL)
2376 #define MDF1_Filter5_BASE_S     (MDF1_BASE_S + 0x300UL)
2377 #define RAMCFG_BASE_S           (AHB1PERIPH_BASE_S + 0x06000UL)
2378 #define RAMCFG_SRAM1_BASE_S     (RAMCFG_BASE_S)
2379 #define RAMCFG_SRAM2_BASE_S     (RAMCFG_BASE_S + 0x0040UL)
2380 #define RAMCFG_SRAM3_BASE_S     (RAMCFG_BASE_S + 0x0080UL)
2381 #define RAMCFG_SRAM4_BASE_S     (RAMCFG_BASE_S + 0x00C0UL)
2382 #define RAMCFG_BKPRAM_BASE_S    (RAMCFG_BASE_S + 0x0100UL)
2383 #define RAMCFG_SRAM5_BASE_S     (RAMCFG_BASE_S + 0x0140UL)
2384 #define RAMCFG_SRAM6_BASE_S     (RAMCFG_BASE_S + 0x0180UL)
2385 #define JPEG_BASE_S             (AHB1PERIPH_BASE_S + 0x0A00UL)
2386 #define DMA2D_BASE_S            (AHB1PERIPH_BASE_S + 0x0B000UL)
2387 #define GFXMMU_BASE_S           (AHB1PERIPH_BASE_S + 0x0C000UL)
2388 #define GPU2D_BASE_S            (AHB1PERIPH_BASE_S + 0x0F000UL)
2389 #define ICACHE_BASE_S           (AHB1PERIPH_BASE_S + 0x10400UL)
2390 #define DCACHE1_BASE_S          (AHB1PERIPH_BASE_S + 0x11400UL)
2391 #define DCACHE2_BASE_S           (AHB1PERIPH_BASE_S + 0x11800UL)
2392 #define GTZC_TZSC1_BASE_S       (AHB1PERIPH_BASE_S + 0x12400UL)
2393 #define GTZC_TZIC1_BASE_S       (AHB1PERIPH_BASE_S + 0x12800UL)
2394 #define GTZC_MPCBB1_BASE_S      (AHB1PERIPH_BASE_S + 0x12C00UL)
2395 #define GTZC_MPCBB2_BASE_S      (AHB1PERIPH_BASE_S + 0x13000UL)
2396 #define GTZC_MPCBB3_BASE_S      (AHB1PERIPH_BASE_S + 0x13400UL)
2397 #define GTZC_MPCBB5_BASE_S      (AHB1PERIPH_BASE_S + 0x13800UL)
2398 #define GTZC_MPCBB6_BASE_S      (AHB1PERIPH_BASE_S + 0x13C00UL)
2399 #define BKPSRAM_BASE_S          (AHB1PERIPH_BASE_S + 0x16400UL)
2400 
2401 /*!< AHB2 Secure peripherals */
2402 #define GPIOA_BASE_S            (AHB2PERIPH_BASE_S + 0x00000UL)
2403 #define GPIOB_BASE_S            (AHB2PERIPH_BASE_S + 0x00400UL)
2404 #define GPIOC_BASE_S            (AHB2PERIPH_BASE_S + 0x00800UL)
2405 #define GPIOD_BASE_S            (AHB2PERIPH_BASE_S + 0x00C00UL)
2406 #define GPIOE_BASE_S            (AHB2PERIPH_BASE_S + 0x01000UL)
2407 #define GPIOF_BASE_S            (AHB2PERIPH_BASE_S + 0x01400UL)
2408 #define GPIOG_BASE_S            (AHB2PERIPH_BASE_S + 0x01800UL)
2409 #define GPIOH_BASE_S            (AHB2PERIPH_BASE_S + 0x01C00UL)
2410 #define GPIOI_BASE_S            (AHB2PERIPH_BASE_S + 0x02000UL)
2411 #define GPIOJ_BASE_S            (AHB2PERIPH_BASE_S + 0x02400UL)
2412 #define ADC1_BASE_S             (AHB2PERIPH_BASE_S + 0x08000UL)
2413 #define ADC2_BASE_S             (AHB2PERIPH_BASE_S + 0x08100UL)
2414 #define ADC12_COMMON_BASE_S     (AHB2PERIPH_BASE_S + 0x08300UL)
2415 #define DCMI_BASE_S             (AHB2PERIPH_BASE_S + 0x0C000UL)
2416 #define PSSI_BASE_S             (AHB2PERIPH_BASE_S + 0x0C400UL)
2417 #define USB_OTG_HS_BASE_S       (AHB2PERIPH_BASE_S + 0x20000UL)
2418 #define AES_BASE_S              (AHB2PERIPH_BASE_S + 0xA0000UL)
2419 #define HASH_BASE_S             (AHB2PERIPH_BASE_S + 0xA0400UL)
2420 #define HASH_DIGEST_BASE_S      (AHB2PERIPH_BASE_S + 0xA0710UL)
2421 #define RNG_BASE_S              (AHB2PERIPH_BASE_S + 0xA0800UL)
2422 #define SAES_BASE_S             (AHB2PERIPH_BASE_S + 0xA0C00UL)
2423 #define PKA_BASE_S              (AHB2PERIPH_BASE_S + 0xA2000UL)
2424 #define PKA_RAM_BASE_S          (AHB2PERIPH_BASE_S + 0xA2400UL)
2425 #define OTFDEC1_BASE_S          (AHB2PERIPH_BASE_S + 0xA5000UL)
2426 #define OTFDEC1_REGION1_BASE_S  (OTFDEC1_BASE_S + 0x20UL)
2427 #define OTFDEC1_REGION2_BASE_S  (OTFDEC1_BASE_S + 0x50UL)
2428 #define OTFDEC1_REGION3_BASE_S  (OTFDEC1_BASE_S + 0x80UL)
2429 #define OTFDEC1_REGION4_BASE_S  (OTFDEC1_BASE_S + 0xB0UL)
2430 #define OTFDEC2_BASE_S          (AHB2PERIPH_BASE_S + 0xA5400UL)
2431 #define OTFDEC2_REGION1_BASE_S  (OTFDEC2_BASE_S + 0x20UL)
2432 #define OTFDEC2_REGION2_BASE_S  (OTFDEC2_BASE_S + 0x50UL)
2433 #define OTFDEC2_REGION3_BASE_S  (OTFDEC2_BASE_S + 0x80UL)
2434 #define OTFDEC2_REGION4_BASE_S  (OTFDEC2_BASE_S + 0xB0UL)
2435 #define OCTOSPIM_R_BASE_S       (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */
2436 #define SDMMC1_BASE_S           (AHB2PERIPH_BASE_S + 0xA8000UL)
2437 #define SDMMC2_BASE_S           (AHB2PERIPH_BASE_S + 0xA8C00UL)
2438 #define DLYB_SDMMC1_BASE_S      (AHB2PERIPH_BASE_S + 0xA8400UL)
2439 #define DLYB_SDMMC2_BASE_S      (AHB2PERIPH_BASE_S + 0xA8800UL)
2440 #define DLYB_OCTOSPI1_BASE_S    (AHB2PERIPH_BASE_S + 0xAF000UL)
2441 #define DLYB_OCTOSPI2_BASE_S    (AHB2PERIPH_BASE_S + 0xAF400UL)
2442 #define FMC_R_BASE_S            (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC  control registers base address     */
2443 #define HSPI1_R_BASE_S          (AHB2PERIPH_BASE_S + 0xB3400UL)
2444 #define FMC_Bank1_R_BASE_S      (FMC_R_BASE_S + 0x0000UL)
2445 #define FMC_Bank1E_R_BASE_S     (FMC_R_BASE_S + 0x0104UL)
2446 #define FMC_Bank3_R_BASE_S      (FMC_R_BASE_S + 0x0080UL)
2447 #define OCTOSPI1_R_BASE_S       (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */
2448 #define OCTOSPI2_R_BASE_S       (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */
2449 
2450 /*!< AHB3 Secure peripherals */
2451 #define LPGPIO1_BASE_S          (AHB3PERIPH_BASE_S)
2452 #define PWR_BASE_S              (AHB3PERIPH_BASE_S + 0x0800UL)
2453 #define RCC_BASE_S              (AHB3PERIPH_BASE_S + 0x0C00UL)
2454 #define ADC4_BASE_S             (AHB3PERIPH_BASE_S + 0x1000UL)
2455 #define ADC4_COMMON_BASE_S      (AHB3PERIPH_BASE_S + 0x1300UL)
2456 #define DAC1_BASE_S             (AHB3PERIPH_BASE_S + 0x1800UL)
2457 #define EXTI_BASE_S             (AHB3PERIPH_BASE_S + 0x2000UL)
2458 #define GTZC_TZSC2_BASE_S       (AHB3PERIPH_BASE_S + 0x3000UL)
2459 #define GTZC_TZIC2_BASE_S       (AHB3PERIPH_BASE_S + 0x3400UL)
2460 #define GTZC_MPCBB4_BASE_S      (AHB3PERIPH_BASE_S + 0x3800UL)
2461 #define ADF1_BASE_S             (AHB3PERIPH_BASE_S + 0x4000UL)
2462 #define ADF1_Filter0_BASE_S     (ADF1_BASE_S + 0x80UL)
2463 #define LPDMA1_BASE_S           (AHB3PERIPH_BASE_S + 0x5000UL)
2464 #define LPDMA1_Channel0_BASE_S  (LPDMA1_BASE_S + 0x0050UL)
2465 #define LPDMA1_Channel1_BASE_S  (LPDMA1_BASE_S + 0x00D0UL)
2466 #define LPDMA1_Channel2_BASE_S  (LPDMA1_BASE_S + 0x0150UL)
2467 #define LPDMA1_Channel3_BASE_S  (LPDMA1_BASE_S + 0x01D0UL)
2468 
2469 /* GFXMMU secure virtual buffers base address */
2470 #define GFXMMU_VIRTUAL_BUFFERS_BASE_S  (0x34000000UL)
2471 #define GFXMMU_VIRTUAL_BUFFER0_BASE_S  (GFXMMU_VIRTUAL_BUFFERS_BASE_S)
2472 #define GFXMMU_VIRTUAL_BUFFER1_BASE_S  (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x400000UL)
2473 #define GFXMMU_VIRTUAL_BUFFER2_BASE_S  (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x800000UL)
2474 #define GFXMMU_VIRTUAL_BUFFER3_BASE_S  (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0xC00000UL)
2475 
2476 /* Debug MCU registers base address */
2477 #define DBGMCU_BASE             (0xE0044000UL)
2478 #define PACKAGE_BASE            (0x0BFA0500UL) /*!< Package data register base address     */
2479 #define UID_BASE                (0x0BFA0700UL) /*!< Unique device ID register base address */
2480 #define FLASHSIZE_BASE          (0x0BFA07A0UL) /*!< Flash size data register base address  */
2481 
2482 /* Internal Flash OTP Area */
2483 #define FLASH_OTP_BASE          (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */
2484 #define FLASH_OTP_SIZE          (0x200U)       /*!< 512 bytes OTP (one-time programmable)          */
2485 
2486 /* USB OTG registers Base address */
2487 #define USB_OTG_GLOBAL_BASE                  (0x0000UL)
2488 #define USB_OTG_DEVICE_BASE                  (0x0800UL)
2489 #define USB_OTG_IN_ENDPOINT_BASE             (0x0900UL)
2490 #define USB_OTG_OUT_ENDPOINT_BASE            (0x0B00UL)
2491 #define USB_OTG_EP_REG_SIZE                  (0x0020UL)
2492 #define USB_OTG_HOST_BASE                    (0x0400UL)
2493 #define USB_OTG_HOST_PORT_BASE               (0x0440UL)
2494 #define USB_OTG_HOST_CHANNEL_BASE            (0x0500UL)
2495 #define USB_OTG_HOST_CHANNEL_SIZE            (0x0020UL)
2496 #define USB_OTG_PCGCCTL_BASE                 (0x0E00UL)
2497 #define USB_OTG_FIFO_BASE                    (0x1000UL)
2498 #define USB_OTG_FIFO_SIZE                    (0x1000UL)
2499 
2500 /*!< Root Secure Service Library */
2501 /************ RSSLIB SAU system Flash region definition constants *************/
2502 #define RSSLIB_SYS_FLASH_NS_PFUNC_START   (0x0BF99E40UL)
2503 #define RSSLIB_SYS_FLASH_NS_PFUNC_END     (0x0BF99EFFUL)
2504 
2505 /************ RSSLIB function return constants ********************************/
2506 #define RSSLIB_ERROR   (0xF5F5F5F5UL)
2507 #define RSSLIB_SUCCESS (0xEAEAEAEAUL)
2508 
2509 /*!< RSSLIB  pointer function structure address definition */
2510 #define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START
2511 #define RSSLIB_PFUNC      ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE)
2512 
2513 /*!< HDP Area constant definition */
2514 #define RSSLIB_HDP_AREA_Pos  (0U)
2515 #define RSSLIB_HDP_AREA_Msk  (0x3UL << RSSLIB_HDP_AREA_Pos )
2516 #define RSSLIB_HDP_AREA1_Pos (0U)
2517 #define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos )
2518 #define RSSLIB_HDP_AREA2_Pos (1U)
2519 #define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos )
2520 
2521 /**
2522   * @brief  Prototype of RSSLIB Close and exit HDP Function
2523   * @detail This function close the requested hdp area passed in input
2524   *         parameter and jump to the reset handler present within the
2525   *         Vector table. The function does not return on successful execution.
2526   * @param  HdpArea notifies which hdp area to close, can be a combination of
2527   *         hdpa area 1 and hdp area 2
2528   * @param  pointer on the vector table containing the reset handler the function
2529   *         jumps to.
2530   * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
2531   */
2532 typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr );
2533 
2534 
2535 /**
2536   * @brief RSSLib non-secure callable function pointer structure
2537   */
2538 typedef struct
2539 {
2540   __IM uint32_t Reserved[8];
2541 }NSC_pFuncTypeDef;
2542 
2543 /**
2544   * @brief RSSLib secure callable function pointer structure
2545   */
2546 typedef struct
2547 {
2548   __IM uint32_t Reserved2[2];
2549   __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP;        /*!< RSSLIB Bootloader Close and exit HDP  Address offset: 0x28 */
2550 }S_pFuncTypeDef;
2551 
2552 /**
2553   * @brief RSSLib function pointer structure
2554   */
2555 typedef struct
2556 {
2557   NSC_pFuncTypeDef NSC;
2558   S_pFuncTypeDef S;
2559 }RSSLIB_pFunc_TypeDef;
2560 
2561 /** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */
2562 
2563 
2564 /* =========================================================================================================================== */
2565 /* ================                                  Peripheral declaration                                   ================ */
2566 /* =========================================================================================================================== */
2567 
2568 
2569 /** @addtogroup STM32U5xx_Peripheral_declaration
2570   * @{
2571   */
2572 
2573 /*!< APB1 Non secure peripherals */
2574 #define TIM2_NS                ((TIM_TypeDef *) TIM2_BASE_NS)
2575 #define TIM3_NS                ((TIM_TypeDef *) TIM3_BASE_NS)
2576 #define TIM4_NS                ((TIM_TypeDef *) TIM4_BASE_NS)
2577 #define TIM5_NS                ((TIM_TypeDef *) TIM5_BASE_NS)
2578 #define TIM6_NS                ((TIM_TypeDef *) TIM6_BASE_NS)
2579 #define TIM7_NS                ((TIM_TypeDef *) TIM7_BASE_NS)
2580 #define WWDG_NS                ((WWDG_TypeDef *) WWDG_BASE_NS)
2581 #define IWDG_NS                ((IWDG_TypeDef *) IWDG_BASE_NS)
2582 #define SPI2_NS                ((SPI_TypeDef *) SPI2_BASE_NS)
2583 #define USART2_NS              ((USART_TypeDef *) USART2_BASE_NS)
2584 #define USART3_NS              ((USART_TypeDef *) USART3_BASE_NS)
2585 #define UART4_NS               ((USART_TypeDef *) UART4_BASE_NS)
2586 #define UART5_NS               ((USART_TypeDef *) UART5_BASE_NS)
2587 #define I2C1_NS                ((I2C_TypeDef *) I2C1_BASE_NS)
2588 #define I2C2_NS                ((I2C_TypeDef *) I2C2_BASE_NS)
2589 #define CRS_NS                 ((CRS_TypeDef *) CRS_BASE_NS)
2590 #define USART6_NS              ((USART_TypeDef *) USART6_BASE_NS)
2591 #define I2C5_NS                ((I2C_TypeDef *) I2C5_BASE_NS)
2592 #define I2C6_NS                ((I2C_TypeDef *) I2C6_BASE_NS)
2593 #define I2C4_NS                ((I2C_TypeDef *) I2C4_BASE_NS)
2594 #define LPTIM2_NS              ((LPTIM_TypeDef *) LPTIM2_BASE_NS)
2595 #define FDCAN1_NS              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS)
2596 #define FDCAN_CONFIG_NS        ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
2597 #define UCPD1_NS               ((UCPD_TypeDef *) UCPD1_BASE_NS)
2598 
2599 /*!< APB2 Non secure peripherals */
2600 #define TIM1_NS                ((TIM_TypeDef *) TIM1_BASE_NS)
2601 #define SPI1_NS                ((SPI_TypeDef *) SPI1_BASE_NS)
2602 #define TIM8_NS                ((TIM_TypeDef *) TIM8_BASE_NS)
2603 #define USART1_NS              ((USART_TypeDef *) USART1_BASE_NS)
2604 #define TIM15_NS               ((TIM_TypeDef *) TIM15_BASE_NS)
2605 #define TIM16_NS               ((TIM_TypeDef *) TIM16_BASE_NS)
2606 #define TIM17_NS               ((TIM_TypeDef *) TIM17_BASE_NS)
2607 #define SAI1_NS                ((SAI_TypeDef *) SAI1_BASE_NS)
2608 #define SAI1_Block_A_NS        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS)
2609 #define SAI1_Block_B_NS        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS)
2610 #define SAI2_NS                ((SAI_TypeDef *) SAI2_BASE_NS)
2611 #define SAI2_Block_A_NS        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS)
2612 #define SAI2_Block_B_NS        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS)
2613 #define LTDC_NS                ((LTDC_TypeDef *) LTDC_BASE_NS)
2614 #define LTDC_Layer1_NS         ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_NS)
2615 #define LTDC_Layer2_NS         ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_NS)
2616 #define DSI_NS                 ((DSI_TypeDef *) DSI_BASE_NS)
2617 #define REFBIAS_NS             ((REFBIAS_TypeDef *) REFBIAS_BASE_NS)
2618 #define DPHY_NS                ((DPHY_TypeDef *) DPHY_BASE_NS)
2619 #define GFXTIM_NS                 ((GFXTIM_TypeDef *) GFXTIM_BASE_NS)
2620 
2621 /*!< APB3 Non secure peripherals */
2622 #define SYSCFG_NS              ((SYSCFG_TypeDef *) SYSCFG_BASE_NS)
2623 #define SPI3_NS                ((SPI_TypeDef *) SPI3_BASE_NS)
2624 #define LPUART1_NS             ((USART_TypeDef *) LPUART1_BASE_NS)
2625 #define I2C3_NS                ((I2C_TypeDef *) I2C3_BASE_NS)
2626 #define LPTIM1_NS              ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
2627 #define LPTIM3_NS              ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
2628 #define LPTIM4_NS              ((LPTIM_TypeDef *) LPTIM4_BASE_NS)
2629 #define OPAMP_NS               ((OPAMP_TypeDef *) OPAMP_BASE_NS)
2630 #define OPAMP1_NS              ((OPAMP_TypeDef *) OPAMP1_BASE_NS)
2631 #define OPAMP2_NS              ((OPAMP_TypeDef *) OPAMP2_BASE_NS)
2632 #define OPAMP12_COMMON_NS      ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS)
2633 #define COMP12_NS              ((COMP_TypeDef *) COMP12_BASE_NS)
2634 #define COMP1_NS               ((COMP_TypeDef *) COMP1_BASE_NS)
2635 #define COMP2_NS               ((COMP_TypeDef *) COMP2_BASE_NS)
2636 #define COMP12_COMMON_NS       ((COMP_Common_TypeDef *) COMP1_BASE_NS)
2637 #define VREFBUF_NS             ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
2638 #define RTC_NS                 ((RTC_TypeDef *) RTC_BASE_NS)
2639 #define TAMP_NS                ((TAMP_TypeDef *) TAMP_BASE_NS)
2640 
2641 /*!< AHB1 Non secure peripherals */
2642 #define GPDMA1_NS              ((DMA_TypeDef *) GPDMA1_BASE_NS)
2643 #define GPDMA1_Channel0_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
2644 #define GPDMA1_Channel1_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
2645 #define GPDMA1_Channel2_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
2646 #define GPDMA1_Channel3_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
2647 #define GPDMA1_Channel4_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
2648 #define GPDMA1_Channel5_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
2649 #define GPDMA1_Channel6_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
2650 #define GPDMA1_Channel7_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
2651 #define GPDMA1_Channel8_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS)
2652 #define GPDMA1_Channel9_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS)
2653 #define GPDMA1_Channel10_NS    ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS)
2654 #define GPDMA1_Channel11_NS    ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS)
2655 #define GPDMA1_Channel12_NS    ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS)
2656 #define GPDMA1_Channel13_NS    ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS)
2657 #define GPDMA1_Channel14_NS    ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS)
2658 #define GPDMA1_Channel15_NS    ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS)
2659 #define CORDIC_NS              ((CORDIC_TypeDef *) CORDIC_BASE_NS)
2660 #define FMAC_NS                ((FMAC_TypeDef *) FMAC_BASE_NS)
2661 #define FLASH_NS               ((FLASH_TypeDef *) FLASH_R_BASE_NS)
2662 #define CRC_NS                 ((CRC_TypeDef *) CRC_BASE_NS)
2663 #define TSC_NS                 ((TSC_TypeDef *) TSC_BASE_NS)
2664 #define MDF1_NS                ((MDF_TypeDef *) MDF1_BASE_NS)
2665 #define MDF1_Filter0_NS        ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS)
2666 #define MDF1_Filter1_NS        ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS)
2667 #define MDF1_Filter2_NS        ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS)
2668 #define MDF1_Filter3_NS        ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS)
2669 #define MDF1_Filter4_NS        ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS)
2670 #define MDF1_Filter5_NS        ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS)
2671 #define RAMCFG_SRAM1_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS)
2672 #define RAMCFG_SRAM2_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS)
2673 #define RAMCFG_SRAM3_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS)
2674 #define RAMCFG_SRAM4_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS)
2675 #define RAMCFG_SRAM5_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS)
2676 #define RAMCFG_SRAM6_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_NS)
2677 #define JPEG_NS                 ((JPEG_TypeDef *) JPEG_BASE_NS)
2678 #define RAMCFG_BKPRAM_NS       ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS)
2679 #define DMA2D_NS               ((DMA2D_TypeDef *) DMA2D_BASE_NS)
2680 #define ICACHE_NS              ((ICACHE_TypeDef *) ICACHE_BASE_NS)
2681 #define DCACHE1_NS             ((DCACHE_TypeDef *) DCACHE1_BASE_NS)
2682 #define DCACHE2_NS              ((DCACHE_TypeDef *) DCACHE2_BASE_NS)
2683 #define GTZC_TZSC1_NS          ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS)
2684 #define GTZC_TZIC1_NS          ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS)
2685 #define GTZC_MPCBB1_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS)
2686 #define GTZC_MPCBB2_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS)
2687 #define GTZC_MPCBB3_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS)
2688 #define GTZC_MPCBB5_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS)
2689 #define GTZC_MPCBB6_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_NS)
2690 #define GFXMMU_NS              ((GFXMMU_TypeDef *) GFXMMU_BASE_NS)
2691 
2692 /*!< AHB2 Non secure peripherals */
2693 #define GPIOA_NS               ((GPIO_TypeDef *) GPIOA_BASE_NS)
2694 #define GPIOB_NS               ((GPIO_TypeDef *) GPIOB_BASE_NS)
2695 #define GPIOC_NS               ((GPIO_TypeDef *) GPIOC_BASE_NS)
2696 #define GPIOD_NS               ((GPIO_TypeDef *) GPIOD_BASE_NS)
2697 #define GPIOE_NS               ((GPIO_TypeDef *) GPIOE_BASE_NS)
2698 #define GPIOF_NS               ((GPIO_TypeDef *) GPIOF_BASE_NS)
2699 #define GPIOG_NS               ((GPIO_TypeDef *) GPIOG_BASE_NS)
2700 #define GPIOH_NS               ((GPIO_TypeDef *) GPIOH_BASE_NS)
2701 #define GPIOI_NS               ((GPIO_TypeDef *) GPIOI_BASE_NS)
2702 #define GPIOJ_NS               ((GPIO_TypeDef *) GPIOJ_BASE_NS)
2703 #define ADC1_NS                ((ADC_TypeDef *) ADC1_BASE_NS)
2704 #define ADC2_NS                ((ADC_TypeDef *) ADC2_BASE_NS)
2705 #define ADC12_COMMON_NS        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
2706 #define DCMI_NS                ((DCMI_TypeDef *) DCMI_BASE_NS)
2707 #define PSSI_NS                ((PSSI_TypeDef *) PSSI_BASE_NS)
2708 #define USB_OTG_HS_NS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS)
2709 #define AES_NS                 ((AES_TypeDef *) AES_BASE_NS)
2710 #define HASH_NS                ((HASH_TypeDef *) HASH_BASE_NS)
2711 #define HASH_DIGEST_NS         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
2712 #define RNG_NS                 ((RNG_TypeDef *) RNG_BASE_NS)
2713 #define SAES_NS                ((AES_TypeDef *) SAES_BASE_NS)
2714 #define PKA_NS                 ((PKA_TypeDef *) PKA_BASE_NS)
2715 #define OTFDEC1_NS             ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS)
2716 #define OTFDEC1_REGION1_NS     ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS)
2717 #define OTFDEC1_REGION2_NS     ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS)
2718 #define OTFDEC1_REGION3_NS     ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS)
2719 #define OTFDEC1_REGION4_NS     ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS)
2720 #define OTFDEC2_NS             ((OTFDEC_TypeDef *) OTFDEC2_BASE_NS)
2721 #define OTFDEC2_REGION1_NS     ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_NS)
2722 #define OTFDEC2_REGION2_NS     ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS)
2723 #define OTFDEC2_REGION3_NS     ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS)
2724 #define OTFDEC2_REGION4_NS     ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS)
2725 #define SDMMC1_NS              ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
2726 #define SDMMC2_NS              ((SDMMC_TypeDef *) SDMMC2_BASE_NS)
2727 #define DLYB_SDMMC1_NS         ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS)
2728 #define DLYB_SDMMC2_NS         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS)
2729 #define DLYB_OCTOSPI1_NS       ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS)
2730 #define DLYB_OCTOSPI2_NS       ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS)
2731 #define FMC_Bank1_R_NS         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
2732 #define FMC_Bank1E_R_NS        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
2733 #define FMC_Bank3_R_NS         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
2734 #define OCTOSPIM_NS            ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS)
2735 #define OCTOSPI1_NS            ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS)
2736 #define OCTOSPI2_NS            ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS)
2737 #define HSPI1_NS               ((HSPI_TypeDef *) HSPI1_R_BASE_NS)
2738 
2739 /*!< AHB3 Non secure peripherals */
2740 #define LPGPIO1_NS             ((GPIO_TypeDef *) LPGPIO1_BASE_NS)
2741 #define PWR_NS                 ((PWR_TypeDef *) PWR_BASE_NS)
2742 #define RCC_NS                 ((RCC_TypeDef *) RCC_BASE_NS)
2743 #define ADC4_NS                ((ADC_TypeDef *) ADC4_BASE_NS)
2744 #define ADC4_COMMON_NS         ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS)
2745 #define DAC1_NS                ((DAC_TypeDef *) DAC1_BASE_NS)
2746 #define EXTI_NS                ((EXTI_TypeDef *) EXTI_BASE_NS)
2747 #define GTZC_TZSC2_NS          ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS)
2748 #define GTZC_TZIC2_NS          ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS)
2749 #define GTZC_MPCBB4_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS)
2750 #define ADF1_NS                ((MDF_TypeDef *) ADF1_BASE_NS)
2751 #define ADF1_Filter0_NS        ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS)
2752 #define LPDMA1_NS              ((DMA_TypeDef *) LPDMA1_BASE_NS)
2753 #define LPDMA1_Channel0_NS     ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS)
2754 #define LPDMA1_Channel1_NS     ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS)
2755 #define LPDMA1_Channel2_NS     ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS)
2756 #define LPDMA1_Channel3_NS     ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS)
2757 
2758 /*!< APB1 Secure peripherals */
2759 #define TIM2_S                 ((TIM_TypeDef *) TIM2_BASE_S)
2760 #define TIM3_S                 ((TIM_TypeDef *) TIM3_BASE_S)
2761 #define TIM4_S                 ((TIM_TypeDef *) TIM4_BASE_S)
2762 #define TIM5_S                 ((TIM_TypeDef *) TIM5_BASE_S)
2763 #define TIM6_S                 ((TIM_TypeDef *) TIM6_BASE_S)
2764 #define TIM7_S                 ((TIM_TypeDef *) TIM7_BASE_S)
2765 #define WWDG_S                 ((WWDG_TypeDef *) WWDG_BASE_S)
2766 #define IWDG_S                 ((IWDG_TypeDef *) IWDG_BASE_S)
2767 #define SPI2_S                 ((SPI_TypeDef *) SPI2_BASE_S)
2768 #define USART2_S               ((USART_TypeDef *) USART2_BASE_S)
2769 #define USART3_S               ((USART_TypeDef *) USART3_BASE_S)
2770 #define UART4_S                ((USART_TypeDef *) UART4_BASE_S)
2771 #define UART5_S                ((USART_TypeDef *) UART5_BASE_S)
2772 #define I2C1_S                 ((I2C_TypeDef *) I2C1_BASE_S)
2773 #define I2C2_S                 ((I2C_TypeDef *) I2C2_BASE_S)
2774 #define CRS_S                  ((CRS_TypeDef *) CRS_BASE_S)
2775 #define USART6_S               ((USART_TypeDef *) USART6_BASE_S)
2776 #define I2C5_S                 ((I2C_TypeDef *) I2C5_BASE_S)
2777 #define I2C6_S                 ((I2C_TypeDef *) I2C6_BASE_S)
2778 #define I2C4_S                 ((I2C_TypeDef *) I2C4_BASE_S)
2779 #define LPTIM2_S               ((LPTIM_TypeDef *) LPTIM2_BASE_S)
2780 #define FDCAN1_S               ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S)
2781 #define FDCAN_CONFIG_S         ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
2782 #define UCPD1_S                ((UCPD_TypeDef *) UCPD1_BASE_S)
2783 
2784 /*!< APB2 Secure peripherals */
2785 #define TIM1_S                 ((TIM_TypeDef *) TIM1_BASE_S)
2786 #define SPI1_S                 ((SPI_TypeDef *) SPI1_BASE_S)
2787 #define TIM8_S                 ((TIM_TypeDef *) TIM8_BASE_S)
2788 #define USART1_S               ((USART_TypeDef *) USART1_BASE_S)
2789 #define TIM15_S                ((TIM_TypeDef *) TIM15_BASE_S)
2790 #define TIM16_S                ((TIM_TypeDef *) TIM16_BASE_S)
2791 #define TIM17_S                ((TIM_TypeDef *) TIM17_BASE_S)
2792 #define SAI1_S                 ((SAI_TypeDef *) SAI1_BASE_S)
2793 #define SAI1_Block_A_S         ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S)
2794 #define SAI1_Block_B_S         ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S)
2795 #define SAI2_S                 ((SAI_TypeDef *) SAI2_BASE_S)
2796 #define SAI2_Block_A_S         ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S)
2797 #define SAI2_Block_B_S         ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S)
2798 #define LTDC_S                 ((LTDC_TypeDef *) LTDC_BASE_S)
2799 #define LTDC_Layer1_S          ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_S)
2800 #define LTDC_Layer2_S          ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_S)
2801 #define DSI_S                  ((DSI_TypeDef *) DSI_BASE_S)
2802 #define REFBIAS_S              ((REFBIAS_TypeDef *) REFBIAS_BASE_S)
2803 #define DPHY_S                 ((DPHY_TypeDef *) DPHY_BASE_S)
2804 #define GFXTIM_S               ((GFXTIM_TypeDef *) GFXTIM_BASE_S)
2805 
2806 /*!< APB3 secure peripherals */
2807 #define SYSCFG_S               ((SYSCFG_TypeDef *) SYSCFG_BASE_S)
2808 #define SPI3_S                 ((SPI_TypeDef *) SPI3_BASE_S)
2809 #define LPUART1_S              ((USART_TypeDef *) LPUART1_BASE_S)
2810 #define I2C3_S                 ((I2C_TypeDef *) I2C3_BASE_S)
2811 #define LPTIM1_S               ((LPTIM_TypeDef *) LPTIM1_BASE_S)
2812 #define LPTIM3_S               ((LPTIM_TypeDef *) LPTIM3_BASE_S)
2813 #define LPTIM4_S               ((LPTIM_TypeDef *) LPTIM4_BASE_S)
2814 #define OPAMP_S                ((OPAMP_TypeDef *) OPAMP_BASE_S)
2815 #define OPAMP1_S               ((OPAMP_TypeDef *) OPAMP1_BASE_S)
2816 #define OPAMP2_S               ((OPAMP_TypeDef *) OPAMP2_BASE_S)
2817 #define OPAMP12_COMMON_S       ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S)
2818 #define COMP12_S               ((COMP_TypeDef *) COMP12_BASE_S)
2819 #define COMP1_S                ((COMP_TypeDef *) COMP1_BASE_S)
2820 #define COMP2_S                ((COMP_TypeDef *) COMP2_BASE_S)
2821 #define COMP12_COMMON_S        ((COMP_Common_TypeDef *) COMP1_BASE_S)
2822 #define VREFBUF_S              ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
2823 #define RTC_S                  ((RTC_TypeDef *) RTC_BASE_S)
2824 #define TAMP_S                 ((TAMP_TypeDef *) TAMP_BASE_S)
2825 
2826 /*!< AHB1 Secure peripherals */
2827 #define GPDMA1_S               ((DMA_TypeDef *) GPDMA1_BASE_S)
2828 #define GPDMA1_Channel0_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S)
2829 #define GPDMA1_Channel1_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S)
2830 #define GPDMA1_Channel2_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S)
2831 #define GPDMA1_Channel3_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S)
2832 #define GPDMA1_Channel4_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S)
2833 #define GPDMA1_Channel5_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S)
2834 #define GPDMA1_Channel6_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S)
2835 #define GPDMA1_Channel7_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S)
2836 #define GPDMA1_Channel8_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S)
2837 #define GPDMA1_Channel9_S      ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S)
2838 #define GPDMA1_Channel10_S     ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S)
2839 #define GPDMA1_Channel11_S     ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S)
2840 #define GPDMA1_Channel12_S     ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S)
2841 #define GPDMA1_Channel13_S     ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S)
2842 #define GPDMA1_Channel14_S     ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S)
2843 #define GPDMA1_Channel15_S     ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S)
2844 #define CORDIC_S               ((CORDIC_TypeDef *) CORDIC_BASE_S)
2845 #define FMAC_S                 ((FMAC_TypeDef *) FMAC_BASE_S)
2846 #define FLASH_S                ((FLASH_TypeDef *) FLASH_R_BASE_S)
2847 #define CRC_S                  ((CRC_TypeDef *) CRC_BASE_S)
2848 #define TSC_S                  ((TSC_TypeDef *) TSC_BASE_S)
2849 #define MDF1_S                 ((MDF_TypeDef *) MDF1_BASE_S)
2850 #define MDF1_Filter0_S         ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S)
2851 #define MDF1_Filter1_S         ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S)
2852 #define MDF1_Filter2_S         ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S)
2853 #define MDF1_Filter3_S         ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S)
2854 #define MDF1_Filter4_S         ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S)
2855 #define MDF1_Filter5_S         ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S)
2856 #define RAMCFG_SRAM1_S         ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S)
2857 #define RAMCFG_SRAM2_S         ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S)
2858 #define RAMCFG_SRAM3_S         ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S)
2859 #define RAMCFG_SRAM4_S         ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S)
2860 #define RAMCFG_SRAM5_S         ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S)
2861 #define RAMCFG_SRAM6_S         ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_S)
2862 #define JPEG_S                 ((JPEG_TypeDef *) JPEG_BASE_S)
2863 #define RAMCFG_BKPRAM_S        ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S)
2864 #define DMA2D_S                ((DMA2D_TypeDef *) DMA2D_BASE_S)
2865 #define ICACHE_S               ((ICACHE_TypeDef *) ICACHE_BASE_S)
2866 #define DCACHE1_S              ((DCACHE_TypeDef *) DCACHE1_BASE_S)
2867 #define DCACHE2_S               ((DCACHE_TypeDef *) DCACHE2_BASE_S)
2868 #define GTZC_TZSC1_S           ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S)
2869 #define GTZC_TZIC1_S           ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S)
2870 #define GTZC_MPCBB1_S          ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S)
2871 #define GTZC_MPCBB2_S          ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S)
2872 #define GTZC_MPCBB3_S          ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S)
2873 #define GTZC_MPCBB5_S          ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S)
2874 #define GTZC_MPCBB6_S          ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_S)
2875 #define GFXMMU_S               ((GFXMMU_TypeDef *) GFXMMU_BASE_S)
2876 
2877 /*!< AHB2 Secure peripherals */
2878 #define GPIOA_S                ((GPIO_TypeDef *) GPIOA_BASE_S)
2879 #define GPIOB_S                ((GPIO_TypeDef *) GPIOB_BASE_S)
2880 #define GPIOC_S                ((GPIO_TypeDef *) GPIOC_BASE_S)
2881 #define GPIOD_S                ((GPIO_TypeDef *) GPIOD_BASE_S)
2882 #define GPIOE_S                ((GPIO_TypeDef *) GPIOE_BASE_S)
2883 #define GPIOF_S                ((GPIO_TypeDef *) GPIOF_BASE_S)
2884 #define GPIOG_S                ((GPIO_TypeDef *) GPIOG_BASE_S)
2885 #define GPIOH_S                ((GPIO_TypeDef *) GPIOH_BASE_S)
2886 #define GPIOI_S                ((GPIO_TypeDef *) GPIOI_BASE_S)
2887 #define GPIOJ_S                ((GPIO_TypeDef *) GPIOJ_BASE_S)
2888 #define ADC1_S                 ((ADC_TypeDef *) ADC1_BASE_S)
2889 #define ADC2_S                 ((ADC_TypeDef *) ADC2_BASE_S)
2890 #define ADC12_COMMON_S         ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
2891 #define DCMI_S                 ((DCMI_TypeDef *) DCMI_BASE_S)
2892 #define PSSI_S                 ((PSSI_TypeDef *) PSSI_BASE_S)
2893 #define USB_OTG_HS_S           ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S)
2894 #define AES_S                  ((AES_TypeDef *) AES_BASE_S)
2895 #define HASH_S                 ((HASH_TypeDef *) HASH_BASE_S)
2896 #define HASH_DIGEST_S          ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
2897 #define RNG_S                  ((RNG_TypeDef *) RNG_BASE_S)
2898 #define SAES_S                 ((AES_TypeDef *) SAES_BASE_S)
2899 #define PKA_S                  ((PKA_TypeDef *) PKA_BASE_S)
2900 #define OTFDEC1_S              ((OTFDEC_TypeDef *) OTFDEC1_BASE_S)
2901 #define OTFDEC1_REGION1_S      ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S)
2902 #define OTFDEC1_REGION2_S      ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S)
2903 #define OTFDEC1_REGION3_S      ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S)
2904 #define OTFDEC1_REGION4_S      ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S)
2905 #define OTFDEC2_S              ((OTFDEC_TypeDef *) OTFDEC2_BASE_S)
2906 #define OTFDEC2_REGION1_S      ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_S)
2907 #define OTFDEC2_REGION2_S      ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S)
2908 #define OTFDEC2_REGION3_S      ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S)
2909 #define OTFDEC2_REGION4_S      ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S)
2910 #define SDMMC1_S               ((SDMMC_TypeDef *) SDMMC1_BASE_S)
2911 #define SDMMC2_S               ((SDMMC_TypeDef *) SDMMC2_BASE_S)
2912 #define DLYB_SDMMC1_S          ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S)
2913 #define DLYB_SDMMC2_S          ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S)
2914 #define DLYB_OCTOSPI1_S        ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S)
2915 #define DLYB_OCTOSPI2_S        ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S)
2916 #define FMC_Bank1_R_S          ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
2917 #define FMC_Bank1E_R_S         ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
2918 #define FMC_Bank3_R_S          ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
2919 #define OCTOSPIM_S             ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S)
2920 #define OCTOSPI1_S             ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S)
2921 #define OCTOSPI2_S             ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S)
2922 #define HSPI1_S                ((HSPI_TypeDef *) HSPI1_R_BASE_S)
2923 
2924 /*!< AHB3 Secure peripherals */
2925 #define LPGPIO1_S              ((GPIO_TypeDef *) LPGPIO1_BASE_S)
2926 #define PWR_S                  ((PWR_TypeDef *) PWR_BASE_S)
2927 #define RCC_S                  ((RCC_TypeDef *) RCC_BASE_S)
2928 #define ADC4_S                 ((ADC_TypeDef *) ADC4_BASE_S)
2929 #define ADC4_COMMON_S          ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S)
2930 #define DAC1_S                 ((DAC_TypeDef *) DAC1_BASE_S)
2931 #define EXTI_S                 ((EXTI_TypeDef *) EXTI_BASE_S)
2932 #define GTZC_TZSC2_S           ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S)
2933 #define GTZC_TZIC2_S           ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S)
2934 #define GTZC_MPCBB4_S          ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S)
2935 #define ADF1_S                 ((MDF_TypeDef *) ADF1_BASE_S)
2936 #define ADF1_Filter0_S         ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S)
2937 #define LPDMA1_S               ((DMA_TypeDef *) LPDMA1_BASE_S)
2938 #define LPDMA1_Channel0_S      ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S)
2939 #define LPDMA1_Channel1_S      ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S)
2940 #define LPDMA1_Channel2_S      ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S)
2941 #define LPDMA1_Channel3_S      ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S)
2942 
2943 /*!< DBGMCU peripheral */
2944 #define DBGMCU                 ((DBGMCU_TypeDef *) DBGMCU_BASE)
2945 
2946 /*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
2947 
2948 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2949 
2950 /*!< Memory base addresses for Secure peripherals */
2951 #define FLASH_BASE                     FLASH_BASE_S
2952 #define SRAM1_BASE                     SRAM1_BASE_S
2953 #define SRAM2_BASE                     SRAM2_BASE_S
2954 #define SRAM3_BASE                     SRAM3_BASE_S
2955 #define SRAM4_BASE                     SRAM4_BASE_S
2956 #define SRAM5_BASE                     SRAM5_BASE_S
2957 #define BKPSRAM_BASE                   BKPSRAM_BASE_S
2958 #define SRAM6_BASE                     SRAM6_BASE_S
2959 #define PERIPH_BASE                    PERIPH_BASE_S
2960 #define APB1PERIPH_BASE                APB1PERIPH_BASE_S
2961 #define APB2PERIPH_BASE                APB2PERIPH_BASE_S
2962 #define AHB1PERIPH_BASE                AHB1PERIPH_BASE_S
2963 #define AHB2PERIPH_BASE                AHB2PERIPH_BASE_S
2964 
2965 /*!< Instance aliases and base addresses for Secure peripherals */
2966 #define CORDIC                         CORDIC_S
2967 #define CORDIC_BASE                    CORDIC_BASE_S
2968 
2969 #define RCC                            RCC_S
2970 #define RCC_BASE                       RCC_BASE_S
2971 
2972 #define DCMI                           DCMI_S
2973 #define DCMI_BASE                      DCMI_BASE_S
2974 
2975 #define PSSI                           PSSI_S
2976 #define PSSI_BASE                      PSSI_BASE_S
2977 
2978 #define FLASH                          FLASH_S
2979 #define FLASH_R_BASE                   FLASH_R_BASE_S
2980 
2981 #define FMAC                           FMAC_S
2982 #define FMAC_BASE                      FMAC_BASE_S
2983 
2984 #define GPDMA1                         GPDMA1_S
2985 #define GPDMA1_BASE                    GPDMA1_BASE_S
2986 
2987 #define GPDMA1_Channel0                GPDMA1_Channel0_S
2988 #define GPDMA1_Channel0_BASE           GPDMA1_Channel0_BASE_S
2989 
2990 #define GPDMA1_Channel1                GPDMA1_Channel1_S
2991 #define GPDMA1_Channel1_BASE           GPDMA1_Channel1_BASE_S
2992 
2993 #define GPDMA1_Channel2                GPDMA1_Channel2_S
2994 #define GPDMA1_Channel2_BASE           GPDMA1_Channel2_BASE_S
2995 
2996 #define GPDMA1_Channel3                GPDMA1_Channel3_S
2997 #define GPDMA1_Channel3_BASE           GPDMA1_Channel3_BASE_S
2998 
2999 #define GPDMA1_Channel4                GPDMA1_Channel4_S
3000 #define GPDMA1_Channel4_BASE           GPDMA1_Channel4_BASE_S
3001 
3002 #define GPDMA1_Channel5                GPDMA1_Channel5_S
3003 #define GPDMA1_Channel5_BASE           GPDMA1_Channel5_BASE_S
3004 
3005 #define GPDMA1_Channel6                GPDMA1_Channel6_S
3006 #define GPDMA1_Channel6_BASE           GPDMA1_Channel6_BASE_S
3007 
3008 #define GPDMA1_Channel7                GPDMA1_Channel7_S
3009 #define GPDMA1_Channel7_BASE           GPDMA1_Channel7_BASE_S
3010 
3011 #define GPDMA1_Channel8                GPDMA1_Channel8_S
3012 #define GPDMA1_Channel8_BASE           GPDMA1_Channel8_BASE_S
3013 
3014 #define GPDMA1_Channel9                GPDMA1_Channel9_S
3015 #define GPDMA1_Channel9_BASE           GPDMA1_Channel9_BASE_S
3016 
3017 #define GPDMA1_Channel10               GPDMA1_Channel10_S
3018 #define GPDMA1_Channel10_BASE          GPDMA1_Channel10_BASE_S
3019 
3020 #define GPDMA1_Channel11               GPDMA1_Channel11_S
3021 #define GPDMA1_Channel11_BASE          GPDMA1_Channel11_BASE_S
3022 
3023 #define GPDMA1_Channel12               GPDMA1_Channel12_S
3024 #define GPDMA1_Channel12_BASE          GPDMA1_Channel12_BASE_S
3025 
3026 #define GPDMA1_Channel13               GPDMA1_Channel13_S
3027 #define GPDMA1_Channel13_BASE          GPDMA1_Channel13_BASE_S
3028 
3029 #define GPDMA1_Channel14               GPDMA1_Channel14_S
3030 #define GPDMA1_Channel14_BASE          GPDMA1_Channel14_BASE_S
3031 
3032 #define GPDMA1_Channel15               GPDMA1_Channel15_S
3033 #define GPDMA1_Channel15_BASE          GPDMA1_Channel15_BASE_S
3034 
3035 #define LPDMA1                         LPDMA1_S
3036 #define LPDMA1_BASE                    LPDMA1_BASE_S
3037 
3038 #define LPDMA1_Channel0                LPDMA1_Channel0_S
3039 #define LPDMA1_Channel0_BASE           LPDMA1_Channel0_BASE_S
3040 
3041 #define LPDMA1_Channel1                LPDMA1_Channel1_S
3042 #define LPDMA1_Channel1_BASE           LPDMA1_Channel1_BASE_S
3043 
3044 #define LPDMA1_Channel2                LPDMA1_Channel2_S
3045 #define LPDMA1_Channel2_BASE           LPDMA1_Channel2_BASE_S
3046 
3047 #define LPDMA1_Channel3                LPDMA1_Channel3_S
3048 #define LPDMA1_Channel3_BASE           LPDMA1_Channel3_BASE_S
3049 
3050 #define GPIOA                          GPIOA_S
3051 #define GPIOA_BASE                     GPIOA_BASE_S
3052 
3053 #define GPIOB                          GPIOB_S
3054 #define GPIOB_BASE                     GPIOB_BASE_S
3055 
3056 #define GPIOC                          GPIOC_S
3057 #define GPIOC_BASE                     GPIOC_BASE_S
3058 
3059 #define GPIOD                          GPIOD_S
3060 #define GPIOD_BASE                     GPIOD_BASE_S
3061 
3062 #define GPIOE                          GPIOE_S
3063 #define GPIOE_BASE                     GPIOE_BASE_S
3064 
3065 #define GPIOF                          GPIOF_S
3066 #define GPIOF_BASE                     GPIOF_BASE_S
3067 
3068 #define GPIOG                          GPIOG_S
3069 #define GPIOG_BASE                     GPIOG_BASE_S
3070 
3071 #define GPIOH                          GPIOH_S
3072 #define GPIOH_BASE                     GPIOH_BASE_S
3073 
3074 #define GPIOI                          GPIOI_S
3075 #define GPIOI_BASE                     GPIOI_BASE_S
3076 
3077 #define GPIOJ                          GPIOJ_S
3078 #define GPIOJ_BASE                     GPIOJ_BASE_S
3079 
3080 #define LPGPIO1                        LPGPIO1_S
3081 #define LPGPIO1_BASE                   LPGPIO1_BASE_S
3082 
3083 #define PWR                            PWR_S
3084 #define PWR_BASE                       PWR_BASE_S
3085 
3086 #define RAMCFG_SRAM1                   RAMCFG_SRAM1_S
3087 #define RAMCFG_SRAM1_BASE              RAMCFG_SRAM1_BASE_S
3088 
3089 #define RAMCFG_SRAM2                   RAMCFG_SRAM2_S
3090 #define RAMCFG_SRAM2_BASE              RAMCFG_SRAM2_BASE_S
3091 
3092 #define RAMCFG_SRAM3                   RAMCFG_SRAM3_S
3093 #define RAMCFG_SRAM3_BASE              RAMCFG_SRAM3_BASE_S
3094 
3095 #define RAMCFG_SRAM4                   RAMCFG_SRAM4_S
3096 #define RAMCFG_SRAM4_BASE              RAMCFG_SRAM4_BASE_S
3097 
3098 #define RAMCFG_SRAM5                   RAMCFG_SRAM5_S
3099 #define RAMCFG_SRAM5_BASE              RAMCFG_SRAM5_BASE_S
3100 
3101 #define RAMCFG_BKPRAM                  RAMCFG_BKPRAM_S
3102 #define RAMCFG_BKPRAM_BASE             RAMCFG_BKPRAM_BASE_S
3103 
3104 #define RAMCFG_SRAM6                   RAMCFG_SRAM6_S
3105 #define RAMCFG_SRAM6_BASE              RAMCFG_SRAM6_BASE_S
3106 
3107 #define EXTI                           EXTI_S
3108 #define EXTI_BASE                      EXTI_BASE_S
3109 
3110 #define ICACHE                         ICACHE_S
3111 #define ICACHE_BASE                    ICACHE_BASE_S
3112 
3113 #define DCACHE1                        DCACHE1_S
3114 #define DCACHE1_BASE                   DCACHE1_BASE_S
3115 
3116 #define DCACHE2                         DCACHE2_S
3117 #define DCACHE2_BASE                    DCACHE2_BASE_S
3118 
3119 #define GTZC_TZSC1                     GTZC_TZSC1_S
3120 #define GTZC_TZSC1_BASE                GTZC_TZSC1_BASE_S
3121 
3122 #define GTZC_TZSC2                     GTZC_TZSC2_S
3123 #define GTZC_TZSC2_BASE                GTZC_TZSC2_BASE_S
3124 
3125 #define GTZC_TZIC1                     GTZC_TZIC1_S
3126 #define GTZC_TZIC1_BASE                GTZC_TZIC1_BASE_S
3127 
3128 #define GTZC_TZIC2                     GTZC_TZIC2_S
3129 #define GTZC_TZIC2_BASE                GTZC_TZIC2_BASE_S
3130 
3131 #define GTZC_MPCBB1                    GTZC_MPCBB1_S
3132 #define GTZC_MPCBB1_BASE               GTZC_MPCBB1_BASE_S
3133 
3134 #define GTZC_MPCBB2                    GTZC_MPCBB2_S
3135 #define GTZC_MPCBB2_BASE               GTZC_MPCBB2_BASE_S
3136 
3137 #define GTZC_MPCBB3                    GTZC_MPCBB3_S
3138 #define GTZC_MPCBB3_BASE               GTZC_MPCBB3_BASE_S
3139 
3140 #define GTZC_MPCBB4                    GTZC_MPCBB4_S
3141 #define GTZC_MPCBB4_BASE               GTZC_MPCBB4_BASE_S
3142 
3143 #define GTZC_MPCBB5                    GTZC_MPCBB5_S
3144 #define GTZC_MPCBB5_BASE               GTZC_MPCBB5_BASE_S
3145 
3146 #define GTZC_MPCBB6                    GTZC_MPCBB6_S
3147 #define GTZC_MPCBB6_BASE               GTZC_MPCBB6_BASE_S
3148 
3149 #define RTC                            RTC_S
3150 #define RTC_BASE                       RTC_BASE_S
3151 
3152 #define TAMP                           TAMP_S
3153 #define TAMP_BASE                      TAMP_BASE_S
3154 
3155 #define TIM1                           TIM1_S
3156 #define TIM1_BASE                      TIM1_BASE_S
3157 
3158 #define TIM2                           TIM2_S
3159 #define TIM2_BASE                      TIM2_BASE_S
3160 
3161 #define TIM3                           TIM3_S
3162 #define TIM3_BASE                      TIM3_BASE_S
3163 
3164 #define TIM4                           TIM4_S
3165 #define TIM4_BASE                      TIM4_BASE_S
3166 
3167 #define TIM5                           TIM5_S
3168 #define TIM5_BASE                      TIM5_BASE_S
3169 
3170 #define TIM6                           TIM6_S
3171 #define TIM6_BASE                      TIM6_BASE_S
3172 
3173 #define TIM7                           TIM7_S
3174 #define TIM7_BASE                      TIM7_BASE_S
3175 
3176 #define TIM8                           TIM8_S
3177 #define TIM8_BASE                      TIM8_BASE_S
3178 
3179 #define TIM15                          TIM15_S
3180 #define TIM15_BASE                     TIM15_BASE_S
3181 
3182 #define TIM16                          TIM16_S
3183 #define TIM16_BASE                     TIM16_BASE_S
3184 
3185 #define TIM17                          TIM17_S
3186 #define TIM17_BASE                     TIM17_BASE_S
3187 
3188 #define WWDG                           WWDG_S
3189 #define WWDG_BASE                      WWDG_BASE_S
3190 
3191 #define IWDG                           IWDG_S
3192 #define IWDG_BASE                      IWDG_BASE_S
3193 
3194 #define SPI1                           SPI1_S
3195 #define SPI1_BASE                      SPI1_BASE_S
3196 
3197 #define SPI2                           SPI2_S
3198 #define SPI2_BASE                      SPI2_BASE_S
3199 
3200 #define SPI3                           SPI3_S
3201 #define SPI3_BASE                      SPI3_BASE_S
3202 
3203 #define USART1                         USART1_S
3204 #define USART1_BASE                    USART1_BASE_S
3205 
3206 #define USART2                         USART2_S
3207 #define USART2_BASE                    USART2_BASE_S
3208 
3209 #define USART3                         USART3_S
3210 #define USART3_BASE                    USART3_BASE_S
3211 
3212 #define UART4                          UART4_S
3213 #define UART4_BASE                     UART4_BASE_S
3214 
3215 #define UART5                          UART5_S
3216 #define UART5_BASE                     UART5_BASE_S
3217 
3218 #define USART6                         USART6_S
3219 #define USART6_BASE                    USART6_BASE_S
3220 
3221 #define I2C1                           I2C1_S
3222 #define I2C1_BASE                      I2C1_BASE_S
3223 
3224 #define I2C2                           I2C2_S
3225 #define I2C2_BASE                      I2C2_BASE_S
3226 
3227 #define I2C3                           I2C3_S
3228 #define I2C3_BASE                      I2C3_BASE_S
3229 
3230 #define I2C4                           I2C4_S
3231 #define I2C4_BASE                      I2C4_BASE_S
3232 
3233 #define I2C5                           I2C5_S
3234 #define I2C5_BASE                      I2C5_BASE_S
3235 
3236 #define I2C6                           I2C6_S
3237 #define I2C6_BASE                      I2C6_BASE_S
3238 
3239 #define CRS                            CRS_S
3240 #define CRS_BASE                       CRS_BASE_S
3241 
3242 #define FDCAN1                         FDCAN1_S
3243 #define FDCAN1_BASE                    FDCAN1_BASE_S
3244 
3245 #define FDCAN_CONFIG                   FDCAN_CONFIG_S
3246 #define FDCAN_CONFIG_BASE              FDCAN_CONFIG_BASE_S
3247 #define SRAMCAN_BASE                   SRAMCAN_BASE_S
3248 
3249 #define DAC                            DAC_S
3250 #define DAC_BASE                       DAC_BASE_S
3251 
3252 #define DAC1                           DAC1_S
3253 #define DAC1_BASE                      DAC1_BASE_S
3254 
3255 #define OPAMP                          OPAMP_S
3256 #define OPAMP_BASE                     OPAMP_BASE_S
3257 
3258 #define OPAMP1                         OPAMP1_S
3259 #define OPAMP1_BASE                    OPAMP1_BASE_S
3260 
3261 #define OPAMP2                         OPAMP2_S
3262 #define OPAMP2_BASE                    OPAMP2_BASE_S
3263 
3264 #define OPAMP12_COMMON                 OPAMP12_COMMON_S
3265 #define OPAMP12_COMMON_BASE            OPAMP12_COMMON_BASE_S
3266 
3267 #define LPTIM1                         LPTIM1_S
3268 #define LPTIM1_BASE                    LPTIM1_BASE_S
3269 
3270 #define LPTIM2                         LPTIM2_S
3271 #define LPTIM2_BASE                    LPTIM2_BASE_S
3272 
3273 #define LPTIM3                         LPTIM3_S
3274 #define LPTIM3_BASE                    LPTIM3_BASE_S
3275 
3276 #define LPTIM4                         LPTIM4_S
3277 #define LPTIM4_BASE                    LPTIM4_BASE_S
3278 
3279 #define LPUART1                        LPUART1_S
3280 #define LPUART1_BASE                   LPUART1_BASE_S
3281 
3282 #define UCPD1                          UCPD1_S
3283 #define UCPD1_BASE                     UCPD1_BASE_S
3284 
3285 #define SYSCFG                         SYSCFG_S
3286 #define SYSCFG_BASE                    SYSCFG_BASE_S
3287 
3288 #define VREFBUF                        VREFBUF_S
3289 #define VREFBUF_BASE                   VREFBUF_BASE_S
3290 
3291 #define COMP12                         COMP12_S
3292 #define COMP12_BASE                    COMP12_BASE_S
3293 
3294 #define COMP1                          COMP1_S
3295 #define COMP1_BASE                     COMP1_BASE_S
3296 
3297 #define COMP2                          COMP2_S
3298 #define COMP2_BASE                     COMP2_BASE_S
3299 
3300 #define COMP12_COMMON                  COMP12_COMMON_S
3301 #define COMP12_COMMON_BASE             COMP1_BASE_S
3302 
3303 #define SAI1                           SAI1_S
3304 #define SAI1_BASE                      SAI1_BASE_S
3305 
3306 #define SAI1_Block_A                   SAI1_Block_A_S
3307 #define SAI1_Block_A_BASE              SAI1_Block_A_BASE_S
3308 
3309 #define SAI1_Block_B                   SAI1_Block_B_S
3310 #define SAI1_Block_B_BASE              SAI1_Block_B_BASE_S
3311 
3312 #define SAI2                           SAI2_S
3313 #define SAI2_BASE                      SAI2_BASE_S
3314 
3315 #define SAI2_Block_A                   SAI2_Block_A_S
3316 #define SAI2_Block_A_BASE              SAI2_Block_A_BASE_S
3317 
3318 #define SAI2_Block_B                   SAI2_Block_B_S
3319 #define SAI2_Block_B_BASE              SAI2_Block_B_BASE_S
3320 
3321 #define CRC                            CRC_S
3322 #define CRC_BASE                       CRC_BASE_S
3323 
3324 #define TSC                            TSC_S
3325 #define TSC_BASE                       TSC_BASE_S
3326 
3327 #define ADC1                           ADC1_S
3328 #define ADC1_BASE                      ADC1_BASE_S
3329 
3330 #define ADC2                           ADC2_S
3331 #define ADC2_BASE                      ADC2_BASE_S
3332 #define ADC12_COMMON                   ADC12_COMMON_S
3333 #define ADC12_COMMON_BASE              ADC12_COMMON_BASE_S
3334 
3335 
3336 #define ADC4                           ADC4_S
3337 #define ADC4_BASE                      ADC4_BASE_S
3338 
3339 #define ADC4_COMMON                    ADC4_COMMON_S
3340 #define ADC4_COMMON_BASE               ADC4_COMMON_BASE_S
3341 
3342 #define HASH                           HASH_S
3343 #define HASH_BASE                      HASH_BASE_S
3344 
3345 #define HASH_DIGEST                    HASH_DIGEST_S
3346 #define HASH_DIGEST_BASE               HASH_DIGEST_BASE_S
3347 
3348 #define AES                            AES_S
3349 #define AES_BASE                       AES_BASE_S
3350 
3351 #define RNG                            RNG_S
3352 #define RNG_BASE                       RNG_BASE_S
3353 
3354 #define SAES                           SAES_S
3355 #define SAES_BASE                      SAES_BASE_S
3356 
3357 #define PKA                            PKA_S
3358 #define PKA_BASE                       PKA_BASE_S
3359 #define PKA_RAM_BASE                   PKA_RAM_BASE_S
3360 
3361 #define OTFDEC1                        OTFDEC1_S
3362 #define OTFDEC1_BASE                   OTFDEC1_BASE_S
3363 
3364 #define OTFDEC1_REGION1                OTFDEC1_REGION1_S
3365 #define OTFDEC1_REGION1_BASE           OTFDEC1_REGION1_BASE_S
3366 
3367 #define OTFDEC1_REGION2                OTFDEC1_REGION2_S
3368 #define OTFDEC1_REGION2_BASE           OTFDEC1_REGION2_BASE_S
3369 
3370 #define OTFDEC1_REGION3                OTFDEC1_REGION3_S
3371 #define OTFDEC1_REGION3_BASE           OTFDEC1_REGION3_BASE_S
3372 
3373 #define OTFDEC1_REGION4                OTFDEC1_REGION4_S
3374 #define OTFDEC1_REGION4_BASE           OTFDEC1_REGION4_BASE_S
3375 
3376 #define OTFDEC2                        OTFDEC2_S
3377 #define OTFDEC2_BASE                   OTFDEC2_BASE_S
3378 
3379 #define OTFDEC2_REGION1                OTFDEC2_REGION1_S
3380 #define OTFDEC2_REGION1_BASE           OTFDEC2_REGION1_BASE_S
3381 
3382 #define OTFDEC2_REGION2                OTFDEC2_REGION2_S
3383 #define OTFDEC2_REGION2_BASE           OTFDEC2_REGION2_BASE_S
3384 
3385 #define OTFDEC2_REGION3                OTFDEC2_REGION3_S
3386 #define OTFDEC2_REGION3_BASE           OTFDEC2_REGION3_BASE_S
3387 
3388 #define OTFDEC2_REGION4                OTFDEC2_REGION4_S
3389 #define OTFDEC2_REGION4_BASE           OTFDEC2_REGION4_BASE_S
3390 
3391 #define SDMMC1                         SDMMC1_S
3392 #define SDMMC1_BASE                    SDMMC1_BASE_S
3393 
3394 #define SDMMC2                         SDMMC2_S
3395 #define SDMMC2_BASE                    SDMMC2_BASE_S
3396 
3397 #define FMC_Bank1_R                    FMC_Bank1_R_S
3398 #define FMC_Bank1_R_BASE               FMC_Bank1_R_BASE_S
3399 
3400 #define FMC_Bank1E_R                   FMC_Bank1E_R_S
3401 #define FMC_Bank1E_R_BASE              FMC_Bank1E_R_BASE_S
3402 
3403 #define FMC_Bank3_R                    FMC_Bank3_R_S
3404 #define FMC_Bank3_R_BASE               FMC_Bank3_R_BASE_S
3405 
3406 #define OCTOSPI1                       OCTOSPI1_S
3407 #define OCTOSPI1_R_BASE                OCTOSPI1_R_BASE_S
3408 
3409 #define OCTOSPI2                       OCTOSPI2_S
3410 #define OCTOSPI2_R_BASE                OCTOSPI2_R_BASE_S
3411 
3412 #define OCTOSPIM                       OCTOSPIM_S
3413 #define OCTOSPIM_R_BASE                OCTOSPIM_R_BASE_S
3414 
3415 #define DLYB_SDMMC1                    DLYB_SDMMC1_S
3416 #define DLYB_SDMMC1_BASE               DLYB_SDMMC1_BASE_S
3417 
3418 #define DLYB_SDMMC2                    DLYB_SDMMC2_S
3419 #define DLYB_SDMMC2_BASE               DLYB_SDMMC2_BASE_S
3420 
3421 #define DLYB_OCTOSPI1                  DLYB_OCTOSPI1_S
3422 #define DLYB_OCTOSPI1_BASE             DLYB_OCTOSPI1_BASE_S
3423 
3424 #define DLYB_OCTOSPI2                  DLYB_OCTOSPI2_S
3425 #define DLYB_OCTOSPI2_BASE             DLYB_OCTOSPI2_BASE_S
3426 
3427 #define HSPI1                          HSPI1_S
3428 #define HSPI1_R_BASE                   HSPI1_R_BASE_S
3429 
3430 #define DMA2D                          DMA2D_S
3431 #define DMA2D_BASE                     DMA2D_BASE_S
3432 
3433 #define USB_OTG_HS                     USB_OTG_HS_S
3434 #define USB_OTG_HS_BASE                USB_OTG_HS_BASE_S
3435 
3436 #define MDF1                           MDF1_S
3437 #define MDF1_BASE                      MDF1_BASE_S
3438 
3439 #define MDF1_Filter0                   MDF1_Filter0_S
3440 #define MDF1_Filter0_BASE              MDF1_Filter0_BASE_S
3441 
3442 #define MDF1_Filter1                   MDF1_Filter1_S
3443 #define MDF1_Filter1_BASE              MDF1_Filter1_BASE_S
3444 
3445 #define MDF1_Filter2                   MDF1_Filter2_S
3446 #define MDF1_Filter2_BASE              MDF1_Filter2_BASE_S
3447 
3448 #define MDF1_Filter3                   MDF1_Filter3_S
3449 #define MDF1_Filter3_BASE              MDF1_Filter3_BASE_S
3450 
3451 #define MDF1_Filter4                   MDF1_Filter4_S
3452 #define MDF1_Filter4_BASE              MDF1_Filter4_BASE_S
3453 
3454 #define MDF1_Filter5                   MDF1_Filter5_S
3455 #define MDF1_Filter5_BASE              MDF1_Filter5_BASE_S
3456 
3457 #define ADF1                           ADF1_S
3458 #define ADF1_BASE                      ADF1_BASE_S
3459 
3460 #define ADF1_Filter0                   ADF1_Filter0_S
3461 #define ADF1_Filter0_BASE              ADF1_Filter0_BASE_S
3462 
3463 #define GFXMMU                         GFXMMU_S
3464 #define GFXMMU_BASE                    GFXMMU_BASE_S
3465 /* GFXMMU virtual buffers base address */
3466 #define GFXMMU_VIRTUAL_BUFFERS_BASE    GFXMMU_VIRTUAL_BUFFERS_BASE_S
3467 #define GFXMMU_VIRTUAL_BUFFER0_BASE    GFXMMU_VIRTUAL_BUFFER0_BASE_S
3468 #define GFXMMU_VIRTUAL_BUFFER1_BASE    GFXMMU_VIRTUAL_BUFFER1_BASE_S
3469 #define GFXMMU_VIRTUAL_BUFFER2_BASE    GFXMMU_VIRTUAL_BUFFER2_BASE_S
3470 #define GFXMMU_VIRTUAL_BUFFER3_BASE    GFXMMU_VIRTUAL_BUFFER3_BASE_S
3471 
3472 #define GPU2D                          GPU2D_BASE_S
3473 
3474 #define LTDC                           LTDC_S
3475 #define LTDC_BASE                      LTDC_BASE_S
3476 
3477 #define LTDC_Layer1_BASE               LTDC_Layer1_BASE_S
3478 #define LTDC_Layer2_BASE               LTDC_Layer2_BASE_S
3479 
3480 #define DSI                            DSI_S
3481 #define DSI_BASE                       DSI_BASE_S
3482 
3483 #define REFBIAS                        REFBIAS_S
3484 #define REFBIAS_BASE                   REFBIAS_BASE_S
3485 
3486 #define DPHY                           DPHY_S
3487 #define DPHY_BASE                      DPHY_BASE_S
3488 
3489 #define JPEG                           JPEG_S
3490 #define JPEG_BASE                      JPEG_BASE_S
3491 
3492 #define GFXTIM                         GFXTIM_S
3493 #define GFXTIM_BASE                    GFXTIM_BASE_S
3494 #else
3495 /*!< Memory base addresses for Non secure peripherals */
3496 #define FLASH_BASE                     FLASH_BASE_NS
3497 #define SRAM1_BASE                     SRAM1_BASE_NS
3498 #define SRAM2_BASE                     SRAM2_BASE_NS
3499 #define SRAM3_BASE                     SRAM3_BASE_NS
3500 #define SRAM4_BASE                     SRAM4_BASE_NS
3501 #define SRAM5_BASE                     SRAM5_BASE_NS
3502 #define BKPSRAM_BASE                   BKPSRAM_BASE_NS
3503 #define SRAM6_BASE                     SRAM6_BASE_NS
3504 #define PERIPH_BASE                    PERIPH_BASE_NS
3505 #define APB1PERIPH_BASE                APB1PERIPH_BASE_NS
3506 #define APB2PERIPH_BASE                APB2PERIPH_BASE_NS
3507 #define AHB1PERIPH_BASE                AHB1PERIPH_BASE_NS
3508 #define AHB2PERIPH_BASE                AHB2PERIPH_BASE_NS
3509 
3510 /*!< Instance aliases and base addresses for Non secure peripherals */
3511 #define CORDIC                         CORDIC_NS
3512 #define CORDIC_BASE                    CORDIC_BASE_NS
3513 
3514 #define RCC                            RCC_NS
3515 #define RCC_BASE                       RCC_BASE_NS
3516 
3517 #define DMA2D                          DMA2D_NS
3518 #define DMA2D_BASE                     DMA2D_BASE_NS
3519 
3520 #define DCMI                           DCMI_NS
3521 #define DCMI_BASE                      DCMI_BASE_NS
3522 
3523 #define PSSI                           PSSI_NS
3524 #define PSSI_BASE                      PSSI_BASE_NS
3525 
3526 #define FLASH                          FLASH_NS
3527 #define FLASH_R_BASE                   FLASH_R_BASE_NS
3528 
3529 #define FMAC                           FMAC_NS
3530 #define FMAC_BASE                      FMAC_BASE_NS
3531 
3532 #define GPDMA1                         GPDMA1_NS
3533 #define GPDMA1_BASE                    GPDMA1_BASE_NS
3534 
3535 #define GPDMA1_Channel0                GPDMA1_Channel0_NS
3536 #define GPDMA1_Channel0_BASE           GPDMA1_Channel0_BASE_NS
3537 
3538 #define GPDMA1_Channel1                GPDMA1_Channel1_NS
3539 #define GPDMA1_Channel1_BASE           GPDMA1_Channel1_BASE_NS
3540 
3541 #define GPDMA1_Channel2                GPDMA1_Channel2_NS
3542 #define GPDMA1_Channel2_BASE           GPDMA1_Channel2_BASE_NS
3543 
3544 #define GPDMA1_Channel3                GPDMA1_Channel3_NS
3545 #define GPDMA1_Channel3_BASE           GPDMA1_Channel3_BASE_NS
3546 
3547 #define GPDMA1_Channel4                GPDMA1_Channel4_NS
3548 #define GPDMA1_Channel4_BASE           GPDMA1_Channel4_BASE_NS
3549 
3550 #define GPDMA1_Channel5                GPDMA1_Channel5_NS
3551 #define GPDMA1_Channel5_BASE           GPDMA1_Channel5_BASE_NS
3552 
3553 #define GPDMA1_Channel6                GPDMA1_Channel6_NS
3554 #define GPDMA1_Channel6_BASE           GPDMA1_Channel6_BASE_NS
3555 
3556 #define GPDMA1_Channel7                GPDMA1_Channel7_NS
3557 #define GPDMA1_Channel7_BASE           GPDMA1_Channel7_BASE_NS
3558 
3559 #define GPDMA1_Channel8                GPDMA1_Channel8_NS
3560 #define GPDMA1_Channel8_BASE           GPDMA1_Channel8_BASE_NS
3561 
3562 #define GPDMA1_Channel9                GPDMA1_Channel9_NS
3563 #define GPDMA1_Channel9_BASE           GPDMA1_Channel9_BASE_NS
3564 
3565 #define GPDMA1_Channel10               GPDMA1_Channel10_NS
3566 #define GPDMA1_Channel10_BASE          GPDMA1_Channel10_BASE_NS
3567 
3568 #define GPDMA1_Channel11               GPDMA1_Channel11_NS
3569 #define GPDMA1_Channel11_BASE          GPDMA1_Channel11_BASE_NS
3570 
3571 #define GPDMA1_Channel12               GPDMA1_Channel12_NS
3572 #define GPDMA1_Channel12_BASE          GPDMA1_Channel12_BASE_NS
3573 
3574 #define GPDMA1_Channel13               GPDMA1_Channel13_NS
3575 #define GPDMA1_Channel13_BASE          GPDMA1_Channel13_BASE_NS
3576 
3577 #define GPDMA1_Channel14               GPDMA1_Channel14_NS
3578 #define GPDMA1_Channel14_BASE          GPDMA1_Channel14_BASE_NS
3579 
3580 #define GPDMA1_Channel15               GPDMA1_Channel15_NS
3581 #define GPDMA1_Channel15_BASE          GPDMA1_Channel15_BASE_NS
3582 
3583 #define LPDMA1                         LPDMA1_NS
3584 #define LPDMA1_BASE                    LPDMA1_BASE_NS
3585 
3586 #define LPDMA1_Channel0                LPDMA1_Channel0_NS
3587 #define LPDMA1_Channel0_BASE           LPDMA1_Channel0_BASE_NS
3588 
3589 #define LPDMA1_Channel1                LPDMA1_Channel1_NS
3590 #define LPDMA1_Channel1_BASE           LPDMA1_Channel1_BASE_NS
3591 
3592 #define LPDMA1_Channel2                LPDMA1_Channel2_NS
3593 #define LPDMA1_Channel2_BASE           LPDMA1_Channel2_BASE_NS
3594 
3595 #define LPDMA1_Channel3                LPDMA1_Channel3_NS
3596 #define LPDMA1_Channel3_BASE           LPDMA1_Channel3_BASE_NS
3597 
3598 #define GPIOA                          GPIOA_NS
3599 #define GPIOA_BASE                     GPIOA_BASE_NS
3600 
3601 #define GPIOB                          GPIOB_NS
3602 #define GPIOB_BASE                     GPIOB_BASE_NS
3603 
3604 #define GPIOC                          GPIOC_NS
3605 #define GPIOC_BASE                     GPIOC_BASE_NS
3606 
3607 #define GPIOD                          GPIOD_NS
3608 #define GPIOD_BASE                     GPIOD_BASE_NS
3609 
3610 #define GPIOE                          GPIOE_NS
3611 #define GPIOE_BASE                     GPIOE_BASE_NS
3612 
3613 #define GPIOF                          GPIOF_NS
3614 #define GPIOF_BASE                     GPIOF_BASE_NS
3615 
3616 #define GPIOG                          GPIOG_NS
3617 #define GPIOG_BASE                     GPIOG_BASE_NS
3618 
3619 #define GPIOH                          GPIOH_NS
3620 #define GPIOH_BASE                     GPIOH_BASE_NS
3621 
3622 #define GPIOI                          GPIOI_NS
3623 #define GPIOI_BASE                     GPIOI_BASE_NS
3624 #define GPIOJ                          GPIOJ_NS
3625 #define GPIOJ_BASE                     GPIOJ_BASE_NS
3626 
3627 #define LPGPIO1                        LPGPIO1_NS
3628 #define LPGPIO1_BASE                   LPGPIO1_BASE_NS
3629 
3630 #define PWR                            PWR_NS
3631 #define PWR_BASE                       PWR_BASE_NS
3632 
3633 #define RAMCFG_SRAM1                   RAMCFG_SRAM1_NS
3634 #define RAMCFG_SRAM1_BASE              RAMCFG_SRAM1_BASE_NS
3635 
3636 #define RAMCFG_SRAM2                   RAMCFG_SRAM2_NS
3637 #define RAMCFG_SRAM2_BASE              RAMCFG_SRAM2_BASE_NS
3638 
3639 #define RAMCFG_SRAM3                   RAMCFG_SRAM3_NS
3640 #define RAMCFG_SRAM3_BASE              RAMCFG_SRAM3_BASE_NS
3641 
3642 #define RAMCFG_SRAM4                   RAMCFG_SRAM4_NS
3643 #define RAMCFG_SRAM4_BASE              RAMCFG_SRAM4_BASE_NS
3644 
3645 #define RAMCFG_SRAM5                   RAMCFG_SRAM5_NS
3646 #define RAMCFG_SRAM5_BASE              RAMCFG_SRAM5_BASE_NS
3647 
3648 #define RAMCFG_BKPRAM                  RAMCFG_BKPRAM_NS
3649 #define RAMCFG_BKPRAM_BASE             RAMCFG_BKPRAM_BASE_NS
3650 
3651 #define RAMCFG_SRAM6                   RAMCFG_SRAM6_NS
3652 #define RAMCFG_SRAM6_BASE              RAMCFG_SRAM6_BASE_NS
3653 
3654 #define EXTI                           EXTI_NS
3655 #define EXTI_BASE                      EXTI_BASE_NS
3656 
3657 #define ICACHE                         ICACHE_NS
3658 #define ICACHE_BASE                    ICACHE_BASE_NS
3659 
3660 #define DCACHE1                        DCACHE1_NS
3661 #define DCACHE1_BASE                   DCACHE1_BASE_NS
3662 
3663 #define DCACHE2                         DCACHE2_NS
3664 #define DCACHE2_BASE                    DCACHE2_BASE_NS
3665 
3666 #define GTZC_TZSC1                     GTZC_TZSC1_NS
3667 #define GTZC_TZSC1_BASE                GTZC_TZSC1_BASE_NS
3668 
3669 #define GTZC_TZSC2                     GTZC_TZSC2_NS
3670 #define GTZC_TZSC2_BASE                GTZC_TZSC2_BASE_NS
3671 
3672 #define GTZC_TZIC1                     GTZC_TZIC1_NS
3673 #define GTZC_TZIC1_BASE                GTZC_TZIC1_BASE_NS
3674 
3675 #define GTZC_TZIC2                     GTZC_TZIC2_NS
3676 #define GTZC_TZIC2_BASE                GTZC_TZIC2_BASE_NS
3677 
3678 #define GTZC_MPCBB1                    GTZC_MPCBB1_NS
3679 #define GTZC_MPCBB1_BASE               GTZC_MPCBB1_BASE_NS
3680 
3681 #define GTZC_MPCBB2                    GTZC_MPCBB2_NS
3682 #define GTZC_MPCBB2_BASE               GTZC_MPCBB2_BASE_NS
3683 
3684 #define GTZC_MPCBB3                    GTZC_MPCBB3_NS
3685 #define GTZC_MPCBB3_BASE               GTZC_MPCBB3_BASE_NS
3686 
3687 #define GTZC_MPCBB4                    GTZC_MPCBB4_NS
3688 #define GTZC_MPCBB4_BASE               GTZC_MPCBB4_BASE_NS
3689 
3690 #define GTZC_MPCBB5                    GTZC_MPCBB5_NS
3691 #define GTZC_MPCBB5_BASE               GTZC_MPCBB5_BASE_NS
3692 
3693 #define GTZC_MPCBB6                    GTZC_MPCBB6_NS
3694 #define GTZC_MPCBB6_BASE               GTZC_MPCBB6_BASE_NS
3695 
3696 #define RTC                            RTC_NS
3697 #define RTC_BASE                       RTC_BASE_NS
3698 
3699 #define TAMP                           TAMP_NS
3700 #define TAMP_BASE                      TAMP_BASE_NS
3701 
3702 #define TIM1                           TIM1_NS
3703 #define TIM1_BASE                      TIM1_BASE_NS
3704 
3705 #define TIM2                           TIM2_NS
3706 #define TIM2_BASE                      TIM2_BASE_NS
3707 
3708 #define TIM3                           TIM3_NS
3709 #define TIM3_BASE                      TIM3_BASE_NS
3710 
3711 #define TIM4                           TIM4_NS
3712 #define TIM4_BASE                      TIM4_BASE_NS
3713 
3714 #define TIM5                           TIM5_NS
3715 #define TIM5_BASE                      TIM5_BASE_NS
3716 
3717 #define TIM6                           TIM6_NS
3718 #define TIM6_BASE                      TIM6_BASE_NS
3719 
3720 #define TIM7                           TIM7_NS
3721 #define TIM7_BASE                      TIM7_BASE_NS
3722 
3723 #define TIM8                           TIM8_NS
3724 #define TIM8_BASE                      TIM8_BASE_NS
3725 
3726 #define TIM15                          TIM15_NS
3727 #define TIM15_BASE                     TIM15_BASE_NS
3728 
3729 #define TIM16                          TIM16_NS
3730 #define TIM16_BASE                     TIM16_BASE_NS
3731 
3732 #define TIM17                          TIM17_NS
3733 #define TIM17_BASE                     TIM17_BASE_NS
3734 
3735 #define WWDG                           WWDG_NS
3736 #define WWDG_BASE                      WWDG_BASE_NS
3737 
3738 #define IWDG                           IWDG_NS
3739 #define IWDG_BASE                      IWDG_BASE_NS
3740 
3741 #define SPI1                           SPI1_NS
3742 #define SPI1_BASE                      SPI1_BASE_NS
3743 
3744 #define SPI2                           SPI2_NS
3745 #define SPI2_BASE                      SPI2_BASE_NS
3746 
3747 #define SPI3                           SPI3_NS
3748 #define SPI3_BASE                      SPI3_BASE_NS
3749 
3750 #define USART1                         USART1_NS
3751 #define USART1_BASE                    USART1_BASE_NS
3752 
3753 #define USART2                         USART2_NS
3754 #define USART2_BASE                    USART2_BASE_NS
3755 
3756 #define USART3                         USART3_NS
3757 #define USART3_BASE                    USART3_BASE_NS
3758 
3759 #define UART4                          UART4_NS
3760 #define UART4_BASE                     UART4_BASE_NS
3761 
3762 #define UART5                          UART5_NS
3763 #define UART5_BASE                     UART5_BASE_NS
3764 
3765 #define USART6                         USART6_NS
3766 #define USART6_BASE                    USART6_BASE_NS
3767 
3768 #define I2C1                           I2C1_NS
3769 #define I2C1_BASE                      I2C1_BASE_NS
3770 
3771 #define I2C2                           I2C2_NS
3772 #define I2C2_BASE                      I2C2_BASE_NS
3773 
3774 #define I2C3                           I2C3_NS
3775 #define I2C3_BASE                      I2C3_BASE_NS
3776 
3777 #define I2C4                           I2C4_NS
3778 #define I2C4_BASE                      I2C4_BASE_NS
3779 
3780 #define I2C5                           I2C5_NS
3781 #define I2C5_BASE                      I2C5_BASE_NS
3782 
3783 #define I2C6                           I2C6_NS
3784 #define I2C6_BASE                      I2C6_BASE_NS
3785 
3786 #define CRS                            CRS_NS
3787 #define CRS_BASE                       CRS_BASE_NS
3788 
3789 #define FDCAN1                         FDCAN1_NS
3790 #define FDCAN1_BASE                    FDCAN1_BASE_NS
3791 
3792 #define FDCAN_CONFIG                   FDCAN_CONFIG_NS
3793 #define FDCAN_CONFIG_BASE              FDCAN_CONFIG_BASE_NS
3794 #define SRAMCAN_BASE                   SRAMCAN_BASE_NS
3795 
3796 #define DAC1                           DAC1_NS
3797 #define DAC1_BASE                      DAC1_BASE_NS
3798 
3799 #define OPAMP                          OPAMP_NS
3800 #define OPAMP_BASE                     OPAMP_BASE_NS
3801 
3802 #define OPAMP1                         OPAMP1_NS
3803 #define OPAMP1_BASE                    OPAMP1_BASE_NS
3804 
3805 #define OPAMP2                         OPAMP2_NS
3806 #define OPAMP2_BASE                    OPAMP2_BASE_NS
3807 
3808 #define OPAMP12_COMMON                 OPAMP12_COMMON_NS
3809 #define OPAMP12_COMMON_BASE            OPAMP12_COMMON_BASE_NS
3810 
3811 #define LPTIM1                         LPTIM1_NS
3812 #define LPTIM1_BASE                    LPTIM1_BASE_NS
3813 
3814 #define LPTIM2                         LPTIM2_NS
3815 #define LPTIM2_BASE                    LPTIM2_BASE_NS
3816 
3817 #define LPTIM3                         LPTIM3_NS
3818 #define LPTIM3_BASE                    LPTIM3_BASE_NS
3819 
3820 #define LPTIM4                         LPTIM4_NS
3821 #define LPTIM4_BASE                    LPTIM4_BASE_NS
3822 
3823 #define LPUART1                        LPUART1_NS
3824 #define LPUART1_BASE                   LPUART1_BASE_NS
3825 
3826 #define UCPD1                          UCPD1_NS
3827 #define UCPD1_BASE                     UCPD1_BASE_NS
3828 
3829 #define SYSCFG                         SYSCFG_NS
3830 #define SYSCFG_BASE                    SYSCFG_BASE_NS
3831 
3832 #define VREFBUF                        VREFBUF_NS
3833 #define VREFBUF_BASE                   VREFBUF_BASE_NS
3834 
3835 #define COMP12                         COMP12_NS
3836 #define COMP12_BASE                    COMP12_BASE_NS
3837 
3838 #define COMP1                          COMP1_NS
3839 #define COMP1_BASE                     COMP1_BASE_NS
3840 
3841 #define COMP2                          COMP2_NS
3842 #define COMP2_BASE                     COMP2_BASE_NS
3843 
3844 #define COMP12_COMMON                  COMP12_COMMON_NS
3845 #define COMP12_COMMON_BASE             COMP1_BASE_NS
3846 
3847 #define SAI1                           SAI1_NS
3848 #define SAI1_BASE                      SAI1_BASE_NS
3849 
3850 #define SAI1_Block_A                   SAI1_Block_A_NS
3851 #define SAI1_Block_A_BASE              SAI1_Block_A_BASE_NS
3852 
3853 #define SAI1_Block_B                   SAI1_Block_B_NS
3854 #define SAI1_Block_B_BASE              SAI1_Block_B_BASE_NS
3855 
3856 #define SAI2                           SAI2_NS
3857 #define SAI2_BASE                      SAI2_BASE_NS
3858 
3859 #define SAI2_Block_A                   SAI2_Block_A_NS
3860 #define SAI2_Block_A_BASE              SAI2_Block_A_BASE_NS
3861 
3862 #define SAI2_Block_B                   SAI2_Block_B_NS
3863 #define SAI2_Block_B_BASE              SAI2_Block_B_BASE_NS
3864 
3865 #define CRC                            CRC_NS
3866 #define CRC_BASE                       CRC_BASE_NS
3867 
3868 #define TSC                            TSC_NS
3869 #define TSC_BASE                       TSC_BASE_NS
3870 
3871 #define ADC1                           ADC1_NS
3872 #define ADC1_BASE                      ADC1_BASE_NS
3873 
3874 #define ADC2                           ADC2_NS
3875 #define ADC2_BASE                      ADC2_BASE_NS
3876 
3877 #define ADC12_COMMON                   ADC12_COMMON_NS
3878 #define ADC12_COMMON_BASE              ADC12_COMMON_BASE_NS
3879 
3880 #define ADC4                           ADC4_NS
3881 #define ADC4_BASE                      ADC4_BASE_NS
3882 
3883 #define ADC4_COMMON                    ADC4_COMMON_NS
3884 #define ADC4_COMMON_BASE               ADC4_COMMON_BASE_NS
3885 
3886 #define HASH                           HASH_NS
3887 #define HASH_BASE                      HASH_BASE_NS
3888 
3889 #define HASH_DIGEST                    HASH_DIGEST_NS
3890 #define HASH_DIGEST_BASE               HASH_DIGEST_BASE_NS
3891 
3892 #define AES                            AES_NS
3893 #define AES_BASE                       AES_BASE_NS
3894 
3895 #define RNG                            RNG_NS
3896 #define RNG_BASE                       RNG_BASE_NS
3897 
3898 #define SAES                            SAES_NS
3899 #define SAES_BASE                       SAES_BASE_NS
3900 
3901 #define PKA                            PKA_NS
3902 #define PKA_BASE                       PKA_BASE_NS
3903 #define PKA_RAM_BASE                   PKA_RAM_BASE_NS
3904 
3905 #define OTFDEC1                        OTFDEC1_NS
3906 #define OTFDEC1_BASE                   OTFDEC1_BASE_NS
3907 
3908 #define OTFDEC1_REGION1                OTFDEC1_REGION1_NS
3909 #define OTFDEC1_REGION1_BASE           OTFDEC1_REGION1_BASE_NS
3910 
3911 #define OTFDEC1_REGION2                OTFDEC1_REGION2_NS
3912 #define OTFDEC1_REGION2_BASE           OTFDEC1_REGION2_BASE_NS
3913 
3914 #define OTFDEC1_REGION3                OTFDEC1_REGION3_NS
3915 #define OTFDEC1_REGION3_BASE           OTFDEC1_REGION3_BASE_NS
3916 
3917 #define OTFDEC1_REGION4                OTFDEC1_REGION4_NS
3918 #define OTFDEC1_REGION4_BASE           OTFDEC1_REGION4_BASE_NS
3919 
3920 #define OTFDEC2                        OTFDEC2_NS
3921 #define OTFDEC2_BASE                   OTFDEC2_BASE_NS
3922 
3923 #define OTFDEC2_REGION1                OTFDEC2_REGION1_NS
3924 #define OTFDEC2_REGION1_BASE           OTFDEC2_REGION1_BASE_NS
3925 
3926 #define OTFDEC2_REGION2                OTFDEC2_REGION2_NS
3927 #define OTFDEC2_REGION2_BASE           OTFDEC2_REGION2_BASE_NS
3928 
3929 #define OTFDEC2_REGION3                OTFDEC2_REGION3_NS
3930 #define OTFDEC2_REGION3_BASE           OTFDEC2_REGION3_BASE_NS
3931 
3932 #define OTFDEC2_REGION4                OTFDEC2_REGION4_NS
3933 #define OTFDEC2_REGION4_BASE           OTFDEC2_REGION4_BASE_NS
3934 
3935 #define SDMMC1                         SDMMC1_NS
3936 #define SDMMC1_BASE                    SDMMC1_BASE_NS
3937 
3938 #define SDMMC2                         SDMMC2_NS
3939 #define SDMMC2_BASE                    SDMMC2_BASE_NS
3940 
3941 #define FMC_Bank1_R                    FMC_Bank1_R_NS
3942 #define FMC_Bank1_R_BASE               FMC_Bank1_R_BASE_NS
3943 
3944 #define FMC_Bank1E_R                   FMC_Bank1E_R_NS
3945 #define FMC_Bank1E_R_BASE              FMC_Bank1E_R_BASE_NS
3946 
3947 #define FMC_Bank3_R                    FMC_Bank3_R_NS
3948 #define FMC_Bank3_R_BASE               FMC_Bank3_R_BASE_NS
3949 
3950 #define OCTOSPI1                       OCTOSPI1_NS
3951 #define OCTOSPI1_R_BASE                OCTOSPI1_R_BASE_NS
3952 
3953 #define OCTOSPI2                       OCTOSPI2_NS
3954 #define OCTOSPI2_R_BASE                OCTOSPI2_R_BASE_NS
3955 
3956 #define OCTOSPIM                       OCTOSPIM_NS
3957 #define OCTOSPIM_R_BASE                OCTOSPIM_R_BASE_NS
3958 
3959 #define DLYB_SDMMC1                    DLYB_SDMMC1_NS
3960 #define DLYB_SDMMC1_BASE               DLYB_SDMMC1_BASE_NS
3961 
3962 #define DLYB_SDMMC2                    DLYB_SDMMC2_NS
3963 #define DLYB_SDMMC2_BASE               DLYB_SDMMC2_BASE_NS
3964 
3965 #define DLYB_OCTOSPI1                  DLYB_OCTOSPI1_NS
3966 #define DLYB_OCTOSPI1_BASE             DLYB_OCTOSPI1_BASE_NS
3967 
3968 #define DLYB_OCTOSPI2                  DLYB_OCTOSPI2_NS
3969 #define DLYB_OCTOSPI2_BASE             DLYB_OCTOSPI2_BASE_NS
3970 
3971 #define HSPI1                          HSPI1_NS
3972 #define HSPI1_R_BASE                   HSPI1_R_BASE_NS
3973 
3974 #define USB_OTG_HS                     USB_OTG_HS_NS
3975 #define USB_OTG_HS_BASE                USB_OTG_HS_BASE_NS
3976 
3977 #define MDF1                           MDF1_NS
3978 #define MDF1_BASE                      MDF1_BASE_NS
3979 
3980 #define MDF1_Filter0                   MDF1_Filter0_NS
3981 #define MDF1_Filter0_BASE              MDF1_Filter0_BASE_NS
3982 
3983 #define MDF1_Filter1                   MDF1_Filter1_NS
3984 #define MDF1_Filter1_BASE              MDF1_Filter1_BASE_NS
3985 
3986 #define MDF1_Filter2                   MDF1_Filter2_NS
3987 #define MDF1_Filter2_BASE              MDF1_Filter2_BASE_NS
3988 
3989 #define MDF1_Filter3                   MDF1_Filter3_NS
3990 #define MDF1_Filter3_BASE              MDF1_Filter3_BASE_NS
3991 
3992 #define MDF1_Filter4                   MDF1_Filter4_NS
3993 #define MDF1_Filter4_BASE              MDF1_Filter4_BASE_NS
3994 
3995 #define MDF1_Filter5                   MDF1_Filter5_NS
3996 #define MDF1_Filter5_BASE              MDF1_Filter5_BASE_NS
3997 
3998 #define ADF1                           ADF1_NS
3999 #define ADF1_BASE                      ADF1_BASE_NS
4000 
4001 #define ADF1_Filter0                   ADF1_Filter0_NS
4002 #define ADF1_Filter0_BASE              ADF1_Filter0_BASE_NS
4003 #define GFXMMU                         GFXMMU_NS
4004 #define GFXMMU_BASE                    GFXMMU_BASE_NS
4005 /* GFXMMU virtual buffers base address */
4006 #define GFXMMU_VIRTUAL_BUFFERS_BASE    GFXMMU_VIRTUAL_BUFFERS_BASE_NS
4007 #define GFXMMU_VIRTUAL_BUFFER0_BASE    GFXMMU_VIRTUAL_BUFFER0_BASE_NS
4008 #define GFXMMU_VIRTUAL_BUFFER1_BASE    GFXMMU_VIRTUAL_BUFFER1_BASE_NS
4009 #define GFXMMU_VIRTUAL_BUFFER2_BASE    GFXMMU_VIRTUAL_BUFFER2_BASE_NS
4010 #define GFXMMU_VIRTUAL_BUFFER3_BASE    GFXMMU_VIRTUAL_BUFFER3_BASE_NS
4011 
4012 #define GPU2D                          GPU2D_BASE_NS
4013 
4014 #define LTDC                           LTDC_NS
4015 #define LTDC_BASE                      LTDC_BASE_NS
4016 
4017 #define LTDC_Layer1                    LTDC_Layer1_NS
4018 #define LTDC_Layer1_BASE               LTDC_Layer1_BASE_NS
4019 
4020 #define LTDC_Layer2                    LTDC_Layer2_NS
4021 #define LTDC_Layer2_BASE               LTDC_Layer2_BASE_NS
4022 
4023 #define DSI                            DSI_NS
4024 #define DSI_BASE                       DSI_BASE_NS
4025 
4026 #define REFBIAS                        REFBIAS_NS
4027 #define REFBIAS_BASE                   REFBIAS_BASE_NS
4028 
4029 #define DPHY                           DPHY_NS
4030 #define DPHY_BASE                      DPHY_BASE_NS
4031 
4032 #define JPEG                           JPEG_NS
4033 #define JPEG_BASE                      JPEG_BASE_NS
4034 
4035 #define GFXTIM                         GFXTIM_NS
4036 #define GFXTIM_BASE                    GFXTIM_BASE_NS
4037 #endif
4038 
4039 /** @addtogroup Hardware_Constant_Definition
4040   * @{
4041   */
4042 #define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */
4043 
4044 /**
4045   * @}
4046   */
4047 
4048 /******************************************************************************/
4049 /*                                                                            */
4050 /*                        Analog to Digital Converter                         */
4051 /*                                                                            */
4052 /******************************************************************************/
4053 /*******************************  ADC VERSION  ********************************/
4054 #define ADC_VER_V5_X
4055 #define ADC_MULTIMODE_SUPPORT
4056 /********************  Bit definition for ADC_ISR register  ********************/
4057 #define ADC_ISR_ADRDY_Pos                 (0U)
4058 #define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)          /*!< 0x00000001 */
4059 #define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                     /*!< ADC Ready (ADRDY) flag  */
4060 #define ADC_ISR_EOSMP_Pos                 (1U)
4061 #define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)          /*!< 0x00000002 */
4062 #define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                     /*!< ADC End of Sampling flag */
4063 #define ADC_ISR_EOC_Pos                   (2U)
4064 #define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)            /*!< 0x00000004 */
4065 #define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                       /*!< ADC End of Regular Conversion flag */
4066 #define ADC_ISR_EOS_Pos                   (3U)
4067 #define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)            /*!< 0x00000008 */
4068 #define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                       /*!< ADC End of Regular sequence of Conversions flag */
4069 #define ADC_ISR_OVR_Pos                   (4U)
4070 #define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)            /*!< 0x00000010 */
4071 #define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                       /*!< ADC overrun flag */
4072 #define ADC_ISR_JEOC_Pos                  (5U)
4073 #define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)           /*!< 0x00000020 */
4074 #define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                      /*!< ADC End of Injected Conversion flag */
4075 #define ADC_ISR_JEOS_Pos                  (6U)
4076 #define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)           /*!< 0x00000040 */
4077 #define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                      /*!< ADC End of Injected sequence of Conversions flag */
4078 #define ADC_ISR_AWD1_Pos                  (7U)
4079 #define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)           /*!< 0x00000080 */
4080 #define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                      /*!< ADC Analog watchdog 1 flag */
4081 #define ADC_ISR_AWD2_Pos                  (8U)
4082 #define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)           /*!< 0x00000100 */
4083 #define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                      /*!< ADC Analog watchdog 2 flag */
4084 #define ADC_ISR_AWD3_Pos                  (9U)
4085 #define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)           /*!< 0x00000200 */
4086 #define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                      /*!< ADC Analog watchdog 3 flag */
4087 #define ADC_ISR_JQOVF_Pos                 (10U)
4088 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)          /*!< 0x00000400 */
4089 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                     /*!< ADC Injected Context Queue Overflow flag */
4090 #define ADC_ISR_EOCAL_Pos                 (11U)
4091 #define ADC_ISR_EOCAL_Msk                 (0x1UL << ADC_ISR_EOCAL_Pos)          /*!< 0x00000800 */
4092 #define ADC_ISR_EOCAL                     ADC_ISR_EOCAL_Msk                     /*!< ADC End of Calibration flag */
4093 #define ADC_ISR_LDORDY_Pos                (12U)
4094 #define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)         /*!< 0x00001000 */
4095 #define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                    /*!< ADC  Voltage Regulator Ready flag */
4096 
4097 /********************  Bit definition for ADC_IER register  ********************/
4098 #define ADC_IER_ADRDYIE_Pos               (0U)
4099 #define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)        /*!< 0x00000001 */
4100 #define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                   /*!< ADC Ready (ADRDY) interrupt source */
4101 #define ADC_IER_EOSMPIE_Pos               (1U)
4102 #define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)        /*!< 0x00000002 */
4103 #define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                   /*!< ADC End of Sampling interrupt source */
4104 #define ADC_IER_EOCIE_Pos                 (2U)
4105 #define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)          /*!< 0x00000004 */
4106 #define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                     /*!< ADC End of Regular Conversion interrupt source */
4107 #define ADC_IER_EOSIE_Pos                 (3U)
4108 #define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)          /*!< 0x00000008 */
4109 #define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                     /*!< ADC End of Regular sequence of Conversions interrupt source */
4110 #define ADC_IER_OVRIE_Pos                 (4U)
4111 #define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)          /*!< 0x00000010 */
4112 #define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                     /*!< ADC overrun interrupt source */
4113 #define ADC_IER_JEOCIE_Pos                (5U)
4114 #define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)         /*!< 0x00000020 */
4115 #define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                    /*!< ADC End of Injected Conversion interrupt source */
4116 #define ADC_IER_JEOSIE_Pos                (6U)
4117 #define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)         /*!< 0x00000040 */
4118 #define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                    /*!< ADC End of Injected sequence of Conversions interrupt source */
4119 #define ADC_IER_AWD1IE_Pos                (7U)
4120 #define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)         /*!< 0x00000080 */
4121 #define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                    /*!< ADC Analog watchdog 1 interrupt source */
4122 #define ADC_IER_AWD2IE_Pos                (8U)
4123 #define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)         /*!< 0x00000100 */
4124 #define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                    /*!< ADC Analog watchdog 2 interrupt source */
4125 #define ADC_IER_AWD3IE_Pos                (9U)
4126 #define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)         /*!< 0x00000200 */
4127 #define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                    /*!< ADC Analog watchdog 3 interrupt source */
4128 #define ADC_IER_JQOVFIE_Pos               (10U)
4129 #define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)        /*!< 0x00000400 */
4130 #define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                   /*!< ADC Injected Context Queue Overflow interrupt source */
4131 #define ADC_IER_EOCALIE_Pos               (11U)
4132 #define ADC_IER_EOCALIE_Msk               (0x1UL << ADC_IER_EOCALIE_Pos)        /*!< 0x00000800 */
4133 #define ADC_IER_EOCALIE                   ADC_IER_EOCALIE_Msk                   /*!< ADC End of Calibration Enable */
4134 #define ADC_IER_LDORDYIE_Pos              (12U)
4135 #define ADC_IER_LDORDYIE_Msk              (0x1UL << ADC_IER_LDORDYIE_Pos)       /*!< 0x00001000 */
4136 #define ADC_IER_LDORDYIE                  ADC_IER_LDORDYIE_Msk                  /*!< ADC  Voltage Regulator Ready flag */
4137 
4138 /********************  Bit definition for ADC_CR register  ********************/
4139 #define ADC_CR_ADEN_Pos                   (0U)
4140 #define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)            /*!< 0x00000001 */
4141 #define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                       /*!< ADC Enable control */
4142 #define ADC_CR_ADDIS_Pos                  (1U)
4143 #define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)           /*!< 0x00000002 */
4144 #define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                      /*!< ADC Disable command */
4145 #define ADC_CR_ADSTART_Pos                (2U)
4146 #define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)         /*!< 0x00000004 */
4147 #define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                    /*!< ADC Start of Regular conversion */
4148 #define ADC_CR_JADSTART_Pos               (3U)
4149 #define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)        /*!< 0x00000008 */
4150 #define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                   /*!< ADC Start of injected conversion */
4151 #define ADC_CR_ADSTP_Pos                  (4U)
4152 #define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)           /*!< 0x00000010 */
4153 #define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                      /*!< ADC Stop of Regular conversion */
4154 #define ADC_CR_JADSTP_Pos                 (5U)
4155 #define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)          /*!< 0x00000020 */
4156 #define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                     /*!< ADC Stop of injected conversion */
4157 #define ADC_CR_ADCALLIN_Pos               (16U)
4158 #define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)        /*!< 0x00010000 */
4159 #define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                   /*!< ADC Linearity calibration */
4160 
4161 #define ADC_CR_CALINDEX_Pos               (24U)
4162 #define ADC_CR_CALINDEX_Msk               (0xFUL << ADC_CR_CALINDEX_Pos)        /*!< 0x0F000000 */
4163 #define ADC_CR_CALINDEX                   ADC_CR_CALINDEX_Msk                   /*!< ADC calibration factor selection */
4164 #define ADC_CR_CALINDEX0_Pos              (24U)
4165 #define ADC_CR_CALINDEX0_Msk              (0x1UL << ADC_CR_CALINDEX0_Pos)       /*!< 0x01000000 */
4166 #define ADC_CR_CALINDEX0                  ADC_CR_CALINDEX0_Msk                  /*!< ADC calibration factor selection (bit 0) */
4167 #define ADC_CR_CALINDEX1_Pos              (25U)
4168 #define ADC_CR_CALINDEX1_Msk              (0x1UL << ADC_CR_CALINDEX1_Pos)       /*!< 0x02000000 */
4169 #define ADC_CR_CALINDEX1                  ADC_CR_CALINDEX1_Msk                  /*!< ADC calibration factor selection (bit 1) */
4170 #define ADC_CR_CALINDEX2_Pos              (26U)
4171 #define ADC_CR_CALINDEX2_Msk              (0x1UL << ADC_CR_CALINDEX2_Pos)       /*!< 0x04000000 */
4172 #define ADC_CR_CALINDEX2                  ADC_CR_CALINDEX2_Msk                  /*!< ADC calibration factor selection (bit 2) */
4173 #define ADC_CR_CALINDEX3_Pos              (27U)
4174 #define ADC_CR_CALINDEX3_Msk              (0x1UL << ADC_CR_CALINDEX3_Pos)       /*!< 0x08000000 */
4175 #define ADC_CR_CALINDEX3                  ADC_CR_CALINDEX3_Msk                  /*!< ADC calibration factor selection (bit 3) */
4176 #define ADC_CR_ADVREGEN_Pos               (28U)
4177 #define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)        /*!< 0x10000000 */
4178 #define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                   /*!< ADC Voltage regulator Enable */
4179 #define ADC_CR_DEEPPWD_Pos                (29U)
4180 #define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)         /*!< 0x20000000 */
4181 #define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                    /*!< ADC Deep power down Enable */
4182 #define ADC_CR_ADCAL_Pos                  (31U)
4183 #define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)           /*!< 0x80000000 */
4184 #define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                      /*!< ADC Calibration */
4185 
4186 /********************  Bit definition for ADC_CFGR register  ********************/
4187 #define ADC_CFGR1_DMNGT_Pos                (0U)
4188 #define ADC_CFGR1_DMNGT_Msk                (0x3UL << ADC_CFGR1_DMNGT_Pos)       /*!< 0x00000003 */
4189 #define ADC_CFGR1_DMNGT                    ADC_CFGR1_DMNGT_Msk                  /*!< ADC Data Management configuration */
4190 #define ADC_CFGR1_DMNGT_0                  (0x1UL << ADC_CFGR1_DMNGT_Pos)       /*!< 0x00000001 */
4191 #define ADC_CFGR1_DMNGT_1                  (0x2UL << ADC_CFGR1_DMNGT_Pos)       /*!< 0x00000002 */
4192 
4193 #define ADC_CFGR1_RES_Pos                  (2U)
4194 #define ADC_CFGR1_RES_Msk                  (0x3UL << ADC_CFGR1_RES_Pos)         /*!< 0x0000000C */
4195 #define ADC_CFGR1_RES                      ADC_CFGR1_RES_Msk                    /*!< ADC Data resolution */
4196 #define ADC_CFGR1_RES_0                    (0x1UL << ADC_CFGR1_RES_Pos)         /*!< 0x00000004 */
4197 #define ADC_CFGR1_RES_1                    (0x2UL << ADC_CFGR1_RES_Pos)         /*!< 0x00000008 */
4198 
4199 #define ADC4_CFGR1_DMAEN_Pos                (0U)
4200 #define ADC4_CFGR1_DMAEN_Msk                (0x1UL << ADC4_CFGR1_DMAEN_Pos)     /*!< 0x00000001 */
4201 #define ADC4_CFGR1_DMAEN                    ADC4_CFGR1_DMAEN_Msk                /*!< ADC DMA transfer enable */
4202 #define ADC4_CFGR1_DMACFG_Pos               (1U)
4203 #define ADC4_CFGR1_DMACFG_Msk               (0x1UL << ADC4_CFGR1_DMACFG_Pos)    /*!< 0x00000002 */
4204 #define ADC4_CFGR1_DMACFG                   ADC4_CFGR1_DMACFG_Msk               /*!< ADC DMA transfer configuration */
4205 
4206 #define ADC4_CFGR1_SCANDIR_Pos              (4U)
4207 #define ADC4_CFGR1_SCANDIR_Msk              (0x1UL << ADC4_CFGR1_SCANDIR_Pos)   /*!< 0x00000004 */
4208 #define ADC4_CFGR1_SCANDIR                  ADC4_CFGR1_SCANDIR_Msk              /*!< ADC group regular sequencer scan direction */
4209 
4210 #define ADC4_CFGR1_ALIGN_Pos                (5U)
4211 #define ADC4_CFGR1_ALIGN_Msk                (0x1UL << ADC4_CFGR1_ALIGN_Pos)     /*!< 0x00000020 */
4212 #define ADC4_CFGR1_ALIGN                    ADC4_CFGR1_ALIGN_Msk                /*!< ADC data alignment */
4213 
4214 #define ADC_CFGR1_EXTSEL_Pos               (5U)
4215 #define ADC_CFGR1_EXTSEL_Msk               (0x1FUL << ADC_CFGR1_EXTSEL_Pos)     /*!< 0x000003E0 */
4216 #define ADC_CFGR1_EXTSEL                   ADC_CFGR1_EXTSEL_Msk                 /*!< ADC External trigger selection for regular group */
4217 #define ADC_CFGR1_EXTSEL_0                 (0x01UL << ADC_CFGR1_EXTSEL_Pos)     /*!< 0x00000020 */
4218 #define ADC_CFGR1_EXTSEL_1                 (0x02UL << ADC_CFGR1_EXTSEL_Pos)     /*!< 0x00000040 */
4219 #define ADC_CFGR1_EXTSEL_2                 (0x04UL << ADC_CFGR1_EXTSEL_Pos)     /*!< 0x00000080 */
4220 #define ADC_CFGR1_EXTSEL_3                 (0x08UL << ADC_CFGR1_EXTSEL_Pos)     /*!< 0x00000100 */
4221 #define ADC_CFGR1_EXTSEL_4                 (0x10UL << ADC_CFGR1_EXTSEL_Pos)     /*!< 0x00000200 */
4222 
4223 #define ADC_CFGR1_EXTEN_Pos                (10U)
4224 #define ADC_CFGR1_EXTEN_Msk                (0x3UL << ADC_CFGR1_EXTEN_Pos)       /*!< 0x00000C00 */
4225 #define ADC_CFGR1_EXTEN                    ADC_CFGR1_EXTEN_Msk                  /*!< ADC External trigger enable and polarity selection for regular channels */
4226 #define ADC_CFGR1_EXTEN_0                  (0x1UL << ADC_CFGR1_EXTEN_Pos)       /*!< 0x00000400 */
4227 #define ADC_CFGR1_EXTEN_1                  (0x2UL << ADC_CFGR1_EXTEN_Pos)       /*!< 0x00000800 */
4228 
4229 #define ADC_CFGR1_OVRMOD_Pos               (12U)
4230 #define ADC_CFGR1_OVRMOD_Msk               (0x1UL << ADC_CFGR1_OVRMOD_Pos)      /*!< 0x00001000 */
4231 #define ADC_CFGR1_OVRMOD                   ADC_CFGR1_OVRMOD_Msk                 /*!< ADC overrun mode */
4232 #define ADC_CFGR1_CONT_Pos                 (13U)
4233 #define ADC_CFGR1_CONT_Msk                 (0x1UL << ADC_CFGR1_CONT_Pos)        /*!< 0x00002000 */
4234 #define ADC_CFGR1_CONT                     ADC_CFGR1_CONT_Msk                   /*!< ADC Single/continuous conversion mode for regular conversion */
4235 
4236 #define ADC_CFGR1_AUTDLY_Pos               (14U)
4237 #define ADC_CFGR1_AUTDLY_Msk               (0x1UL << ADC_CFGR1_AUTDLY_Pos)      /*!< 0x00004000 */
4238 #define ADC_CFGR1_AUTDLY                   ADC_CFGR1_AUTDLY_Msk                 /*!< ADC Delayed conversion mode */
4239 
4240 #define ADC4_CFGR1_WAIT_Pos                (14U)
4241 #define ADC4_CFGR1_WAIT_Msk                (0x1UL << ADC4_CFGR1_WAIT_Pos)       /*!< 0x00004000 */
4242 #define ADC4_CFGR1_WAIT                    ADC4_CFGR1_WAIT_Msk                  /*!< ADC Delayed conversion mode */
4243 
4244 #define ADC_CFGR1_DISCEN_Pos               (16U)
4245 #define ADC_CFGR1_DISCEN_Msk               (0x1UL << ADC_CFGR1_DISCEN_Pos)      /*!< 0x00010000 */
4246 #define ADC_CFGR1_DISCEN                   ADC_CFGR1_DISCEN_Msk                 /*!< ADC Discontinuous mode for regular channels */
4247 
4248 #define ADC_CFGR1_DISCNUM_Pos              (17U)
4249 #define ADC_CFGR1_DISCNUM_Msk              (0x7UL << ADC_CFGR1_DISCNUM_Pos)     /*!< 0x000E0000 */
4250 #define ADC_CFGR1_DISCNUM                  ADC_CFGR1_DISCNUM_Msk                /*!< ADC Discontinuous mode channel count */
4251 #define ADC_CFGR1_DISCNUM_0                (0x1UL << ADC_CFGR1_DISCNUM_Pos)     /*!< 0x00020000 */
4252 #define ADC_CFGR1_DISCNUM_1                (0x2UL << ADC_CFGR1_DISCNUM_Pos)     /*!< 0x00040000 */
4253 #define ADC_CFGR1_DISCNUM_2                (0x4UL << ADC_CFGR1_DISCNUM_Pos)     /*!< 0x00080000 */
4254 
4255 #define ADC_CFGR1_JDISCEN_Pos              (20U)
4256 #define ADC_CFGR1_JDISCEN_Msk              (0x1UL << ADC_CFGR1_JDISCEN_Pos)     /*!< 0x00100000 */
4257 #define ADC_CFGR1_JDISCEN                  ADC_CFGR1_JDISCEN_Msk                /*!< ADC Discontinuous mode on injected channels */
4258 
4259 #define ADC_CFGR1_AWD1SGL_Pos              (22U)
4260 #define ADC_CFGR1_AWD1SGL_Msk              (0x1UL << ADC_CFGR1_AWD1SGL_Pos)     /*!< 0x00400000 */
4261 #define ADC_CFGR1_AWD1SGL                  ADC_CFGR1_AWD1SGL_Msk                /*!< Enable the watchdog 1 on a single channel or on all channels */
4262 #define ADC_CFGR1_AWD1EN_Pos               (23U)
4263 #define ADC_CFGR1_AWD1EN_Msk               (0x1UL << ADC_CFGR1_AWD1EN_Pos)      /*!< 0x00800000 */
4264 #define ADC_CFGR1_AWD1EN                   ADC_CFGR1_AWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on regular Channels */
4265 #define ADC_CFGR1_JAWD1EN_Pos              (24U)
4266 #define ADC_CFGR1_JAWD1EN_Msk              (0x1UL << ADC_CFGR1_JAWD1EN_Pos)     /*!< 0x01000000 */
4267 #define ADC_CFGR1_JAWD1EN                  ADC_CFGR1_JAWD1EN_Msk                /*!< ADC Analog watchdog 1 enable on injected Channels */
4268 #define ADC_CFGR1_JAUTO_Pos                (25U)
4269 #define ADC_CFGR1_JAUTO_Msk                (0x1UL << ADC_CFGR1_JAUTO_Pos)       /*!< 0x02000000 */
4270 #define ADC_CFGR1_JAUTO                    ADC_CFGR1_JAUTO_Msk                  /*!< ADC Automatic injected group conversion */
4271 
4272 /* Specific ADC4 */
4273 #define ADC4_CFGR1_EXTSEL_Pos               (6U)
4274 #define ADC4_CFGR1_EXTSEL_Msk               (0x7UL << ADC4_CFGR1_EXTSEL_Pos)    /*!< 0x000003E0 */
4275 #define ADC4_CFGR1_EXTSEL                   ADC4_CFGR1_EXTSEL_Msk               /*!< ADC External trigger selection for regular group */
4276 #define ADC4_CFGR1_EXTSEL_0                 (0x01UL << ADC4_CFGR1_EXTSEL_Pos)   /*!< 0x00000020 */
4277 #define ADC4_CFGR1_EXTSEL_1                 (0x02UL << ADC4_CFGR1_EXTSEL_Pos)   /*!< 0x00000040 */
4278 #define ADC4_CFGR1_EXTSEL_2                 (0x04UL << ADC4_CFGR1_EXTSEL_Pos)   /*!< 0x00000080 */
4279 
4280 #define ADC4_CFGR1_CHSELRMOD_Pos           (21U)
4281 #define ADC4_CFGR1_CHSELRMOD_Msk           (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos)  /*!< 0x00200000 */
4282 #define ADC4_CFGR1_CHSELRMOD               ADC4_CFGR1_CHSELRMOD_Msk             /*!< ADC JSQR Queue mode */
4283 
4284 #define ADC_CFGR1_AWD1CH_Pos               (26U)
4285 #define ADC_CFGR1_AWD1CH_Msk               (0x1FUL << ADC_CFGR1_AWD1CH_Pos)     /*!< 0x7C000000 */
4286 #define ADC_CFGR1_AWD1CH                   ADC_CFGR1_AWD1CH_Msk                 /*!< ADC Analog watchdog 1 Channel selection */
4287 #define ADC_CFGR1_AWD1CH_0                 (0x01UL << ADC_CFGR1_AWD1CH_Pos)     /*!< 0x04000000 */
4288 #define ADC_CFGR1_AWD1CH_1                 (0x02UL << ADC_CFGR1_AWD1CH_Pos)     /*!< 0x08000000 */
4289 #define ADC_CFGR1_AWD1CH_2                 (0x04UL << ADC_CFGR1_AWD1CH_Pos)     /*!< 0x10000000 */
4290 #define ADC_CFGR1_AWD1CH_3                 (0x08UL << ADC_CFGR1_AWD1CH_Pos)     /*!< 0x20000000 */
4291 #define ADC_CFGR1_AWD1CH_4                 (0x10UL << ADC_CFGR1_AWD1CH_Pos)     /*!< 0x40000000 */
4292 
4293 /********************  Bit definition for ADC_CFGR2 register  ********************/
4294 #define ADC_CFGR2_ROVSE_Pos               (0U)
4295 #define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)        /*!< 0x00000001 */
4296 #define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                   /*!< ADC Regular group oversampler enable */
4297 #define ADC_CFGR2_JOVSE_Pos               (1U)
4298 #define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)        /*!< 0x00000002 */
4299 #define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                   /*!< ADC Injected group oversampler enable */
4300 
4301 #define ADC_CFGR2_OVSS_Pos                (5U)
4302 #define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)         /*!< 0x000001E0 */
4303 #define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                    /*!< ADC Regular Oversampling shift */
4304 #define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */
4305 #define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */
4306 #define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */
4307 #define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */
4308 
4309 #define ADC_CFGR2_TROVS_Pos               (9U)
4310 #define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)        /*!< 0x00000200 */
4311 #define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                   /*!< ADC Triggered regular Oversampling */
4312 #define ADC_CFGR2_ROVSM_Pos               (10U)
4313 #define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)        /*!< 0x00000400 */
4314 #define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                   /*!< ADC Regular oversampling mode */
4315 
4316 #define ADC_CFGR2_OVSR_Pos                (16U)
4317 #define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)       /*!< 0x03FF0000 */
4318 #define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                    /*!< ADC oversampling Ratio */
4319 #define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */
4320 #define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */
4321 #define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */
4322 #define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */
4323 #define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */
4324 #define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */
4325 #define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */
4326 #define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */
4327 #define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */
4328 #define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */
4329 
4330 #define ADC_CFGR2_BULB_Pos                (13U)
4331 #define ADC_CFGR2_BULB_Msk                (0x1UL << ADC_CFGR2_BULB_Pos)         /*!< 0x00002000 */
4332 #define ADC_CFGR2_BULB                    ADC_CFGR2_BULB_Msk                    /*!< ADC Bulb sampling mode */
4333 
4334 #define ADC_CFGR2_SWTRIG_Pos              (14U)
4335 #define ADC_CFGR2_SWTRIG_Msk              (0x1UL << ADC_CFGR2_SWTRIG_Pos)       /*!< 0x00004000 */
4336 #define ADC_CFGR2_SWTRIG                  ADC_CFGR2_SWTRIG_Msk                  /*!< ADC Software trigger bit for sampling time control trigger mode */
4337 
4338 #define ADC_CFGR2_SMPTRIG_Pos             (15U)
4339 #define ADC_CFGR2_SMPTRIG_Msk             (0x1UL << ADC_CFGR2_SMPTRIG_Pos)      /*!< 0x00008000 */
4340 #define ADC_CFGR2_SMPTRIG                 ADC_CFGR2_SMPTRIG_Msk                 /*!< ADC Sampling time control trigger mode */
4341 
4342 #define ADC_CFGR2_LFTRIG_Pos              (27U)
4343 #define ADC_CFGR2_LFTRIG_Msk              (0x1UL << ADC_CFGR2_LFTRIG_Pos)       /*!< 0x08000000 */
4344 #define ADC_CFGR2_LFTRIG                  ADC_CFGR2_LFTRIG_Msk                  /*!< ADC low frequency trigger mode */
4345 
4346 #define ADC_CFGR2_LSHIFT_Pos              (28U)
4347 #define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0xF0000000 */
4348 #define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                  /*!< ADC Left shift factor */
4349 #define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */
4350 #define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */
4351 #define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */
4352 #define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */
4353 
4354 /* Specific ADC4 */
4355 #define ADC4_CFGR2_OVSR_Pos               (2U)
4356 #define ADC4_CFGR2_OVSR_Msk               (0x7UL << ADC4_CFGR2_OVSR_Pos)        /*!< 0x0000001C */
4357 #define ADC4_CFGR2_OVSR                   ADC4_CFGR2_OVSR_Msk                   /*!< ADC oversampling ratio */
4358 #define ADC4_CFGR2_OVSR_0                 (0x1UL << ADC4_CFGR2_OVSR_Pos)        /*!< 0x00000004 */
4359 #define ADC4_CFGR2_OVSR_1                 (0x2UL << ADC4_CFGR2_OVSR_Pos)        /*!< 0x00000008 */
4360 #define ADC4_CFGR2_OVSR_2                 (0x4UL << ADC4_CFGR2_OVSR_Pos)        /*!< 0x00000010 */
4361 
4362 #define ADC4_CFGR2_LFTRIG_Pos             (29U)
4363 #define ADC4_CFGR2_LFTRIG_Msk             (0x1UL << ADC4_CFGR2_LFTRIG_Pos)      /*!< 0x20000000 */
4364 #define ADC4_CFGR2_LFTRIG                 ADC4_CFGR2_LFTRIG_Msk                 /*!< ADC4 low frequency trigger mode */
4365 
4366 /********************  Bit definition for ADC_SMPR1 register  ********************/
4367 #define ADC_SMPR1_SMP0_Pos                (0U)
4368 #define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000007 */
4369 #define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                    /*!< ADC Channel 0 Sampling time selection  */
4370 #define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */
4371 #define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */
4372 #define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */
4373 
4374 #define ADC_SMPR1_SMP1_Pos                (3U)
4375 #define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000038 */
4376 #define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                    /*!< ADC Channel 1 Sampling time selection  */
4377 #define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */
4378 #define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */
4379 #define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */
4380 
4381 #define ADC_SMPR1_SMP2_Pos                (6U)
4382 #define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x000001C0 */
4383 #define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                    /*!< ADC Channel 2 Sampling time selection  */
4384 #define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */
4385 #define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */
4386 #define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */
4387 
4388 #define ADC_SMPR1_SMP3_Pos                (9U)
4389 #define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000E00 */
4390 #define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                    /*!< ADC Channel 3 Sampling time selection  */
4391 #define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */
4392 #define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */
4393 #define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */
4394 
4395 #define ADC_SMPR1_SMP4_Pos                (12U)
4396 #define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00007000 */
4397 #define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                    /*!< ADC Channel 4 Sampling time selection  */
4398 #define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */
4399 #define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */
4400 #define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */
4401 
4402 #define ADC_SMPR1_SMP5_Pos                (15U)
4403 #define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00038000 */
4404 #define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                    /*!< ADC Channel 5 Sampling time selection  */
4405 #define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */
4406 #define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */
4407 #define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */
4408 
4409 #define ADC_SMPR1_SMP6_Pos                (18U)
4410 #define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x001C0000 */
4411 #define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                    /*!< ADC Channel 6 Sampling time selection  */
4412 #define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */
4413 #define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */
4414 #define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */
4415 
4416 #define ADC_SMPR1_SMP7_Pos                (21U)
4417 #define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00E00000 */
4418 #define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                    /*!< ADC Channel 7 Sampling time selection  */
4419 #define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */
4420 #define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */
4421 #define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */
4422 
4423 #define ADC_SMPR1_SMP8_Pos                (24U)
4424 #define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x07000000 */
4425 #define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                    /*!< ADC Channel 8 Sampling time selection  */
4426 #define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */
4427 #define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */
4428 #define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */
4429 
4430 #define ADC_SMPR1_SMP9_Pos                (27U)
4431 #define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x38000000 */
4432 #define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                    /*!< ADC Channel 9 Sampling time selection  */
4433 #define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */
4434 #define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */
4435 #define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */
4436 
4437 #define ADC4_SMPR_SMP1_Pos                (0U)
4438 #define ADC4_SMPR_SMP1_Msk                (0x7UL << ADC4_SMPR_SMP1_Pos)         /*!< 0x00000007 */
4439 #define ADC4_SMPR_SMP1                    ADC4_SMPR_SMP1_Msk                    /*!< ADC Channel 0 Sampling time selection  */
4440 #define ADC4_SMPR_SMP1_0                  (0x1UL << ADC4_SMPR_SMP1_Pos)         /*!< 0x00000001 */
4441 #define ADC4_SMPR_SMP1_1                  (0x2UL << ADC4_SMPR_SMP1_Pos)         /*!< 0x00000002 */
4442 #define ADC4_SMPR_SMP1_2                  (0x4UL << ADC4_SMPR_SMP1_Pos)         /*!< 0x00000004 */
4443 
4444 #define ADC4_SMPR_SMP2_Pos                (4U)
4445 #define ADC4_SMPR_SMP2_Msk                (0x7UL << ADC4_SMPR_SMP2_Pos)         /*!< 0x00000070 */
4446 #define ADC4_SMPR_SMP2                    ADC4_SMPR_SMP2_Msk                    /*!< ADC group of channels sampling time 2 */
4447 #define ADC4_SMPR_SMP2_0                  (0x1UL << ADC4_SMPR_SMP2_Pos)         /*!< 0x00000010 */
4448 #define ADC4_SMPR_SMP2_1                  (0x2UL << ADC4_SMPR_SMP2_Pos)         /*!< 0x00000020 */
4449 #define ADC4_SMPR_SMP2_2                  (0x4UL << ADC4_SMPR_SMP2_Pos)         /*!< 0x00000040 */
4450 
4451 #define ADC4_SMPR_SMPSEL_Pos              (8U)
4452 #define ADC4_SMPR_SMPSEL_Msk              (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos)  /*!< 0xFFFFFF00 */
4453 #define ADC4_SMPR_SMPSEL                  ADC4_SMPR_SMPSEL_Msk                  /*!< ADC4 all channels sampling time selection */
4454 #define ADC4_SMPR_SMPSEL0_Pos             (8U)
4455 #define ADC4_SMPR_SMPSEL0_Msk             (0x1UL << ADC4_SMPR_SMPSEL0_Pos)      /*!< 0x00000100 */
4456 #define ADC4_SMPR_SMPSEL0                 ADC4_SMPR_SMPSEL0_Msk                 /*!< ADC4 channel 0 sampling time selection */
4457 #define ADC4_SMPR_SMPSEL1_Pos             (9U)
4458 #define ADC4_SMPR_SMPSEL1_Msk             (0x1UL << ADC4_SMPR_SMPSEL1_Pos)      /*!< 0x00000200 */
4459 #define ADC4_SMPR_SMPSEL1                 ADC4_SMPR_SMPSEL1_Msk                 /*!< ADC4 channel 1 sampling time selection */
4460 #define ADC4_SMPR_SMPSEL2_Pos             (10U)
4461 #define ADC4_SMPR_SMPSEL2_Msk             (0x1UL << ADC4_SMPR_SMPSEL2_Pos)      /*!< 0x00000400 */
4462 #define ADC4_SMPR_SMPSEL2                 ADC4_SMPR_SMPSEL2_Msk                 /*!< ADC4 channel 2 sampling time selection */
4463 #define ADC4_SMPR_SMPSEL3_Pos             (11U)
4464 #define ADC4_SMPR_SMPSEL3_Msk             (0x1UL << ADC4_SMPR_SMPSEL3_Pos)      /*!< 0x00000800 */
4465 #define ADC4_SMPR_SMPSEL3                 ADC4_SMPR_SMPSEL3_Msk                 /*!< ADC4 channel 3 sampling time selection */
4466 #define ADC4_SMPR_SMPSEL4_Pos             (12U)
4467 #define ADC4_SMPR_SMPSEL4_Msk             (0x1UL << ADC4_SMPR_SMPSEL4_Pos)      /*!< 0x00001000 */
4468 #define ADC4_SMPR_SMPSEL4                 ADC4_SMPR_SMPSEL4_Msk                 /*!< ADC4 channel 4 sampling time selection */
4469 #define ADC4_SMPR_SMPSEL5_Pos             (13U)
4470 #define ADC4_SMPR_SMPSEL5_Msk             (0x1UL << ADC4_SMPR_SMPSEL5_Pos)      /*!< 0x00002000 */
4471 #define ADC4_SMPR_SMPSEL5                 ADC4_SMPR_SMPSEL5_Msk                 /*!< ADC4 channel 5 sampling time selection */
4472 #define ADC4_SMPR_SMPSEL6_Pos             (14U)
4473 #define ADC4_SMPR_SMPSEL6_Msk             (0x1UL << ADC4_SMPR_SMPSEL6_Pos)      /*!< 0x00004000 */
4474 #define ADC4_SMPR_SMPSEL6                 ADC4_SMPR_SMPSEL6_Msk                 /*!< ADC4 channel 6 sampling time selection */
4475 #define ADC4_SMPR_SMPSEL7_Pos             (15U)
4476 #define ADC4_SMPR_SMPSEL7_Msk             (0x1UL << ADC4_SMPR_SMPSEL7_Pos)      /*!< 0x00008000 */
4477 #define ADC4_SMPR_SMPSEL7                 ADC4_SMPR_SMPSEL7_Msk                 /*!< ADC4 channel 7 sampling time selection */
4478 #define ADC4_SMPR_SMPSEL8_Pos             (16U)
4479 #define ADC4_SMPR_SMPSEL8_Msk             (0x1UL << ADC4_SMPR_SMPSEL8_Pos)      /*!< 0x00010000 */
4480 #define ADC4_SMPR_SMPSEL8                 ADC4_SMPR_SMPSEL8_Msk                 /*!< ADC4 channel 8 sampling time selection */
4481 #define ADC4_SMPR_SMPSEL9_Pos             (17U)
4482 #define ADC4_SMPR_SMPSEL9_Msk             (0x1UL << ADC4_SMPR_SMPSEL9_Pos)      /*!< 0x00020000 */
4483 #define ADC4_SMPR_SMPSEL9                 ADC4_SMPR_SMPSEL9_Msk                 /*!< ADC4 channel 9 sampling time selection */
4484 #define ADC4_SMPR_SMPSEL10_Pos            (18U)
4485 #define ADC4_SMPR_SMPSEL10_Msk            (0x1UL << ADC4_SMPR_SMPSEL10_Pos)     /*!< 0x00040000 */
4486 #define ADC4_SMPR_SMPSEL10                ADC4_SMPR_SMPSEL10_Msk                /*!< ADC4 channel 10 sampling time selection */
4487 #define ADC4_SMPR_SMPSEL11_Pos            (19U)
4488 #define ADC4_SMPR_SMPSEL11_Msk            (0x1UL << ADC4_SMPR_SMPSEL11_Pos)     /*!< 0x00080000 */
4489 #define ADC4_SMPR_SMPSEL11                ADC4_SMPR_SMPSEL11_Msk                /*!< ADC4 channel 11 sampling time selection */
4490 #define ADC4_SMPR_SMPSEL12_Pos            (20U)
4491 #define ADC4_SMPR_SMPSEL12_Msk            (0x1UL << ADC4_SMPR_SMPSEL12_Pos)     /*!< 0x00100000 */
4492 #define ADC4_SMPR_SMPSEL12                ADC4_SMPR_SMPSEL12_Msk                /*!< ADC4 channel 12 sampling time selection */
4493 #define ADC4_SMPR_SMPSEL13_Pos            (21U)
4494 #define ADC4_SMPR_SMPSEL13_Msk            (0x1UL << ADC4_SMPR_SMPSEL13_Pos)     /*!< 0x00200000 */
4495 #define ADC4_SMPR_SMPSEL13                ADC4_SMPR_SMPSEL13_Msk                /*!< ADC4 channel 13 sampling time selection */
4496 #define ADC4_SMPR_SMPSEL14_Pos            (22U)
4497 #define ADC4_SMPR_SMPSEL14_Msk            (0x1UL << ADC4_SMPR_SMPSEL14_Pos)     /*!< 0x00400000 */
4498 #define ADC4_SMPR_SMPSEL14                ADC4_SMPR_SMPSEL14_Msk                /*!< ADC4 channel 14 sampling time selection */
4499 #define ADC4_SMPR_SMPSEL15_Pos            (23U)
4500 #define ADC4_SMPR_SMPSEL15_Msk            (0x1UL << ADC4_SMPR_SMPSEL15_Pos)     /*!< 0x00800000 */
4501 #define ADC4_SMPR_SMPSEL15                ADC4_SMPR_SMPSEL15_Msk                /*!< ADC4 channel 15 sampling time selection */
4502 #define ADC4_SMPR_SMPSEL16_Pos            (24U)
4503 #define ADC4_SMPR_SMPSEL16_Msk            (0x1UL << ADC4_SMPR_SMPSEL16_Pos)     /*!< 0x01000000 */
4504 #define ADC4_SMPR_SMPSEL16                ADC4_SMPR_SMPSEL16_Msk                /*!< ADC4 channel 16 sampling time selection */
4505 #define ADC4_SMPR_SMPSEL17_Pos            (25U)
4506 #define ADC4_SMPR_SMPSEL17_Msk            (0x1UL << ADC4_SMPR_SMPSEL17_Pos)     /*!< 0x02000000 */
4507 #define ADC4_SMPR_SMPSEL17                ADC4_SMPR_SMPSEL17_Msk                /*!< ADC4 channel 17 sampling time selection */
4508 #define ADC4_SMPR_SMPSEL18_Pos            (26U)
4509 #define ADC4_SMPR_SMPSEL18_Msk            (0x1UL << ADC4_SMPR_SMPSEL18_Pos)     /*!< 0x04000000 */
4510 #define ADC4_SMPR_SMPSEL18                ADC4_SMPR_SMPSEL18_Msk                /*!< ADC4 channel 18 sampling time selection */
4511 #define ADC4_SMPR_SMPSEL19_Pos            (27U)
4512 #define ADC4_SMPR_SMPSEL19_Msk            (0x1UL << ADC4_SMPR_SMPSEL19_Pos)     /*!< 0x08000000 */
4513 #define ADC4_SMPR_SMPSEL19                ADC4_SMPR_SMPSEL19_Msk                /*!< ADC4 channel 19 sampling time selection */
4514 #define ADC4_SMPR_SMPSEL20_Pos            (26U)
4515 #define ADC4_SMPR_SMPSEL20_Msk            (0x1UL << ADC4_SMPR_SMPSEL20_Pos)     /*!< 0x10000000 */
4516 #define ADC4_SMPR_SMPSEL20                ADC4_SMPR_SMPSEL20_Msk                /*!< ADC4 channel 20 sampling time selection */
4517 #define ADC4_SMPR_SMPSEL21_Pos            (26U)
4518 #define ADC4_SMPR_SMPSEL21_Msk            (0x1UL << ADC4_SMPR_SMPSEL21_Pos)     /*!< 0x20000000 */
4519 #define ADC4_SMPR_SMPSEL21                ADC4_SMPR_SMPSEL21_Msk                /*!< ADC4 channel 20 sampling time selection */
4520 #define ADC4_SMPR_SMPSEL22_Pos            (30U)
4521 #define ADC4_SMPR_SMPSEL22_Msk            (0x1UL << ADC4_SMPR_SMPSEL22_Pos)     /*!< 0x40000000 */
4522 #define ADC4_SMPR_SMPSEL22                ADC4_SMPR_SMPSEL22_Msk                /*!< ADC4 channel 21 sampling time selection */
4523 #define ADC4_SMPR_SMPSEL23_Pos            (31U)
4524 #define ADC4_SMPR_SMPSEL23_Msk            (0x1UL << ADC4_SMPR_SMPSEL23_Pos)     /*!< 0x80000000 */
4525 #define ADC4_SMPR_SMPSEL23                ADC4_SMPR_SMPSEL23_Msk                /*!< ADC4 channel 23 sampling time selection */
4526 
4527 /********************  Bit definition for ADC_SMPR2 register  ********************/
4528 #define ADC_SMPR2_SMP10_Pos               (0U)
4529 #define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000007 */
4530 #define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                   /*!< ADC Channel 10 Sampling time selection  */
4531 #define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */
4532 #define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */
4533 #define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */
4534 
4535 #define ADC_SMPR2_SMP11_Pos               (3U)
4536 #define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000038 */
4537 #define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                   /*!< ADC Channel 11 Sampling time selection  */
4538 #define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */
4539 #define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */
4540 #define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */
4541 
4542 #define ADC_SMPR2_SMP12_Pos               (6U)
4543 #define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x000001C0 */
4544 #define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                   /*!< ADC Channel 12 Sampling time selection  */
4545 #define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */
4546 #define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */
4547 #define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */
4548 
4549 #define ADC_SMPR2_SMP13_Pos               (9U)
4550 #define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000E00 */
4551 #define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                   /*!< ADC Channel 13 Sampling time selection  */
4552 #define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */
4553 #define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */
4554 #define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */
4555 
4556 #define ADC_SMPR2_SMP14_Pos               (12U)
4557 #define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00007000 */
4558 #define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                   /*!< ADC Channel 14 Sampling time selection  */
4559 #define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */
4560 #define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */
4561 #define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */
4562 
4563 #define ADC_SMPR2_SMP15_Pos               (15U)
4564 #define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00038000 */
4565 #define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                   /*!< ADC Channel 15 Sampling time selection  */
4566 #define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */
4567 #define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */
4568 #define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */
4569 
4570 #define ADC_SMPR2_SMP16_Pos               (18U)
4571 #define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x001C0000 */
4572 #define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                   /*!< ADC Channel 16 Sampling time selection  */
4573 #define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */
4574 #define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */
4575 #define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */
4576 
4577 #define ADC_SMPR2_SMP17_Pos               (21U)
4578 #define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00E00000 */
4579 #define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                   /*!< ADC Channel 17 Sampling time selection  */
4580 #define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */
4581 #define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */
4582 #define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */
4583 
4584 #define ADC_SMPR2_SMP18_Pos               (24U)
4585 #define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x07000000 */
4586 #define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                   /*!< ADC Channel 18 Sampling time selection  */
4587 #define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */
4588 #define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */
4589 #define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */
4590 
4591 #define ADC_SMPR2_SMP19_Pos               (27U)
4592 #define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x38000000 */
4593 #define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                   /*!< ADC Channel 19 Sampling time selection  */
4594 #define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */
4595 #define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */
4596 #define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */
4597 
4598 /********************  Bit definition for ADC_PCSEL register  ********************/
4599 #define ADC_PCSEL_PCSEL_Pos               (0U)
4600 #define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x000FFFFF */
4601 #define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                   /*!< ADC pre channel selection */
4602 #define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
4603 #define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
4604 #define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
4605 #define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
4606 #define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
4607 #define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
4608 #define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
4609 #define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
4610 #define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
4611 #define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
4612 #define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
4613 #define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
4614 #define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
4615 #define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
4616 #define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
4617 #define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
4618 #define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
4619 #define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
4620 #define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
4621 #define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
4622 
4623 /*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/
4624 #define ADC_LTR_LT_Pos                    (0U)
4625 #define ADC_LTR_LT_Msk                    (0x01FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x01FFFFFF */
4626 #define ADC_LTR_LT                        ADC_LTR_LT_Msk                        /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
4627 
4628 /*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/
4629 #define ADC_HTR_HT_Pos                    (0U)
4630 #define ADC_HTR_HT_Msk                    (0x01FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x01FFFFFF */
4631 #define ADC_HTR_HT                        ADC_HTR_HT_Msk                        /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
4632 
4633 #define ADC_HTR_AWDFILT_Pos               (29U)
4634 #define ADC_HTR_AWDFILT_Msk               (0x7UL << ADC_HTR_AWDFILT_Pos)        /*!< 0xE0000000 */
4635 #define ADC_HTR_AWDFILT                   ADC_HTR_AWDFILT_Msk                   /*!< Analog watchdog filtering parameter, HTR1 only */
4636 #define ADC_HTR_AWDFILT_0                 (0x1UL << ADC_HTR_AWDFILT_Pos)        /*!< 0x20000000 */
4637 #define ADC_HTR_AWDFILT_1                 (0x2UL << ADC_HTR_AWDFILT_Pos)        /*!< 0x40000000 */
4638 #define ADC_HTR_AWDFILT_2                 (0x4UL << ADC_HTR_AWDFILT_Pos)        /*!< 0x80000000 */
4639 
4640 /********************  Bit definition for ADC_SQR1 register  ********************/
4641 #define ADC_SQR1_L_Pos                    (0U)
4642 #define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)             /*!< 0x0000000F */
4643 #define ADC_SQR1_L                        ADC_SQR1_L_Msk                        /*!< ADC regular channel sequence length */
4644 #define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */
4645 #define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */
4646 #define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */
4647 #define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */
4648 
4649 #define ADC_SQR1_SQ1_Pos                  (6U)
4650 #define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)          /*!< 0x000007C0 */
4651 #define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                      /*!< ADC 1st conversion in regular sequence */
4652 #define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */
4653 #define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */
4654 #define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */
4655 #define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */
4656 #define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */
4657 
4658 #define ADC_SQR1_SQ2_Pos                  (12U)
4659 #define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)          /*!< 0x0001F000 */
4660 #define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                      /*!< ADC 2nd conversion in regular sequence */
4661 #define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */
4662 #define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */
4663 #define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */
4664 #define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */
4665 #define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */
4666 
4667 #define ADC_SQR1_SQ3_Pos                  (18U)
4668 #define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)          /*!< 0x007C0000 */
4669 #define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                      /*!< ADC 3rd conversion in regular sequence */
4670 #define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */
4671 #define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */
4672 #define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */
4673 #define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */
4674 #define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */
4675 
4676 #define ADC_SQR1_SQ4_Pos                  (24U)
4677 #define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)          /*!< 0x1F000000 */
4678 #define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                      /*!< ADC 4th conversion in regular sequence */
4679 #define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */
4680 #define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */
4681 #define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */
4682 #define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */
4683 #define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */
4684 
4685 /********************  Bit definition for ADC_SQR2 register  ********************/
4686 #define ADC_SQR2_SQ5_Pos                  (0U)
4687 #define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)          /*!< 0x0000001F */
4688 #define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                      /*!< ADC 5th conversion in regular sequence */
4689 #define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */
4690 #define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */
4691 #define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */
4692 #define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */
4693 #define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */
4694 
4695 #define ADC_SQR2_SQ6_Pos                  (6U)
4696 #define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)          /*!< 0x000007C0 */
4697 #define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                      /*!< ADC 6th conversion in regular sequence */
4698 #define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */
4699 #define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */
4700 #define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */
4701 #define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */
4702 #define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */
4703 
4704 #define ADC_SQR2_SQ7_Pos                  (12U)
4705 #define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)          /*!< 0x0001F000 */
4706 #define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                      /*!< ADC 7th conversion in regular sequence */
4707 #define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */
4708 #define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */
4709 #define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */
4710 #define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */
4711 #define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */
4712 
4713 #define ADC_SQR2_SQ8_Pos                  (18U)
4714 #define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)          /*!< 0x007C0000 */
4715 #define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                      /*!< ADC 8th conversion in regular sequence */
4716 #define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */
4717 #define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */
4718 #define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */
4719 #define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */
4720 #define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */
4721 
4722 #define ADC_SQR2_SQ9_Pos                  (24U)
4723 #define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)          /*!< 0x1F000000 */
4724 #define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                      /*!< ADC 9th conversion in regular sequence */
4725 #define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */
4726 #define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */
4727 #define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */
4728 #define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */
4729 #define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */
4730 
4731 /********************  Bit definition for ADC_SQR3 register  ********************/
4732 #define ADC_SQR3_SQ10_Pos                 (0U)
4733 #define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)         /*!< 0x0000001F */
4734 #define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                     /*!< ADC 10th conversion in regular sequence */
4735 #define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */
4736 #define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */
4737 #define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */
4738 #define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */
4739 #define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */
4740 
4741 #define ADC_SQR3_SQ11_Pos                 (6U)
4742 #define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)         /*!< 0x000007C0 */
4743 #define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                     /*!< ADC 11th conversion in regular sequence */
4744 #define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */
4745 #define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */
4746 #define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */
4747 #define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */
4748 #define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */
4749 
4750 #define ADC_SQR3_SQ12_Pos                 (12U)
4751 #define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)         /*!< 0x0001F000 */
4752 #define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                     /*!< ADC 12th conversion in regular sequence */
4753 #define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */
4754 #define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */
4755 #define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */
4756 #define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */
4757 #define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */
4758 
4759 #define ADC_SQR3_SQ13_Pos                 (18U)
4760 #define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)         /*!< 0x007C0000 */
4761 #define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                     /*!< ADC 13th conversion in regular sequence */
4762 #define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */
4763 #define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */
4764 #define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */
4765 #define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */
4766 #define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */
4767 
4768 #define ADC_SQR3_SQ14_Pos                 (24U)
4769 #define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)         /*!< 0x1F000000 */
4770 #define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                     /*!< ADC 14th conversion in regular sequence */
4771 #define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */
4772 #define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */
4773 #define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */
4774 #define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */
4775 #define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */
4776 
4777 /********************  Bit definition for ADC_SQR4 register  ********************/
4778 #define ADC_SQR4_SQ15_Pos                 (0U)
4779 #define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)         /*!< 0x0000001F */
4780 #define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                     /*!< ADC 15th conversion in regular sequence */
4781 #define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */
4782 #define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */
4783 #define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */
4784 #define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */
4785 #define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */
4786 
4787 #define ADC_SQR4_SQ16_Pos                 (6U)
4788 #define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)         /*!< 0x000007C0 */
4789 #define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                     /*!< ADC 16th conversion in regular sequence */
4790 #define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */
4791 #define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */
4792 #define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */
4793 #define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */
4794 #define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */
4795 /********************  Bit definition for ADC_DR register  ********************/
4796 #define ADC_DR_RDATA_Pos                  (0U)
4797 #define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)    /*!< 0xFFFFFFFF */
4798 #define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                      /*!< ADC regular Data converted */
4799 
4800 /********************  Bit definition for ADC_PW register  ********************/
4801 #define ADC4_PWRR_AUTOFF_Pos              (0U)
4802 #define ADC4_PWRR_AUTOFF_Msk              (0x1UL << ADC4_PWRR_AUTOFF_Pos)       /*!< 0x00000001 */
4803 #define ADC4_PWRR_AUTOFF                  ADC4_PWRR_AUTOFF_Msk                  /*!< ADC Auto-Off mode */
4804 #define ADC4_PWRR_DPD_Pos                 (1U)
4805 #define ADC4_PWRR_DPD_Msk                 (0x1UL << ADC4_PWRR_DPD_Pos)          /*!< 0x00000002 */
4806 #define ADC4_PWRR_DPD                     ADC4_PWRR_DPD_Msk                     /*!< ADC Deep Power mode */
4807 #define ADC4_PWRR_VREFPROT_Pos            (2U)
4808 #define ADC4_PWRR_VREFPROT_Msk            (0x1UL << ADC4_PWRR_VREFPROT_Pos)     /*!< 0x00000004 */
4809 #define ADC4_PWRR_VREFPROT                ADC4_PWRR_VREFPROT_Msk                /*!< ADC Vref protection */
4810 #define ADC4_PWRR_VREFSECSMP_Pos          (3U)
4811 #define ADC4_PWRR_VREFSECSMP_Msk          (0x1UL << ADC4_PWRR_VREFSECSMP_Pos)   /*!< 0x00000008 */
4812 #define ADC4_PWRR_VREFSECSMP              ADC4_PWRR_VREFSECSMP_Msk              /*!< ADC Vref Second Sample */
4813 
4814 /* Legacy definitions */
4815 #define ADC4_PW_AUTOFF_Pos                ADC4_PWRR_AUTOFF_Pos
4816 #define ADC4_PW_AUTOFF_Msk                ADC4_PWRR_AUTOFF_Msk
4817 #define ADC4_PW_AUTOFF                    ADC4_PWRR_AUTOFF
4818 #define ADC4_PW_DPD_Pos                   ADC4_PWRR_DPD_Pos
4819 #define ADC4_PW_DPD_Msk                   ADC4_PWRR_DPD_Msk
4820 #define ADC4_PW_DPD                       ADC4_PWRR_DPD
4821 #define ADC4_PW_VREFPROT_Pos              ADC4_PWRR_VREFPROT_Pos
4822 #define ADC4_PW_VREFPROT_Msk              ADC4_PWRR_VREFPROT_Msk
4823 #define ADC4_PW_VREFPROT                  ADC4_PWRR_VREFPROT
4824 #define ADC4_PW_VREFSECSMP_Pos            ADC4_PWRR_VREFSECSMP_Pos
4825 #define ADC4_PW_VREFSECSMP_Msk            ADC4_PWRR_VREFSECSMP_Msk
4826 #define ADC4_PW_VREFSECSMP                ADC4_PWRR_VREFSECSMP
4827 
4828 /********************  Bit definition for ADC_JSQR register  ********************/
4829 #define ADC_JSQR_JL_Pos                   (0U)
4830 #define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)            /*!< 0x00000003 */
4831 #define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                       /*!< ADC injected channel sequence length */
4832 #define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)            /*!< 0x00000001 */
4833 #define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)            /*!< 0x00000002 */
4834 
4835 #define ADC_JSQR_JEXTSEL_Pos              (2U)
4836 #define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x0000007C */
4837 #define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                  /*!< ADC external trigger selection for injected group */
4838 #define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x00000004 */
4839 #define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x00000008 */
4840 #define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x00000010 */
4841 #define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x00000020 */
4842 #define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)      /*!< 0x00000040 */
4843 
4844 #define ADC_JSQR_JEXTEN_Pos               (7U)
4845 #define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)        /*!< 0x00000180 */
4846 #define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                   /*!< ADC external trigger enable and polarity selection for injected channels */
4847 #define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)        /*!< 0x00000080 */
4848 #define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)        /*!< 0x00000100 */
4849 
4850 #define ADC_JSQR_JSQ1_Pos                 (9U)
4851 #define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)         /*!< 0x00003E00 */
4852 #define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                     /*!< ADC 1st conversion in injected sequence */
4853 #define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)         /*!< 0x00000200 */
4854 #define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)         /*!< 0x00000400 */
4855 #define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)         /*!< 0x00000800 */
4856 #define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)         /*!< 0x00001000 */
4857 #define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)         /*!< 0x00002000 */
4858 
4859 #define ADC_JSQR_JSQ2_Pos                 (15U)
4860 #define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)         /*!< 0x000F8000 */
4861 #define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                     /*!< ADC 2nd conversion in injected sequence */
4862 #define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)         /*!< 0x00008000 */
4863 #define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)         /*!< 0x00010000 */
4864 #define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)         /*!< 0x00020000 */
4865 #define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)         /*!< 0x00040000 */
4866 #define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)         /*!< 0x00080000 */
4867 
4868 #define ADC_JSQR_JSQ3_Pos                 (21U)
4869 #define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)         /*!< 0x03E00000 */
4870 #define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                     /*!< ADC 3rd conversion in injected sequence */
4871 #define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)         /*!< 0x00200000 */
4872 #define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)         /*!< 0x00400000 */
4873 #define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)         /*!< 0x00800000 */
4874 #define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)         /*!< 0x01000000 */
4875 #define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)         /*!< 0x02000000 */
4876 
4877 #define ADC_JSQR_JSQ4_Pos                 (27U)
4878 #define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)         /*!< 0xF8000000 */
4879 #define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                     /*!< ADC 4th conversion in injected sequence */
4880 #define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)         /*!< 0x08000000 */
4881 #define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)         /*!< 0x10000000 */
4882 #define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)         /*!< 0x20000000 */
4883 #define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)         /*!< 0x40000000 */
4884 #define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)         /*!< 0x80000000 */
4885 
4886 /********************  Bit definition for ADC_OFR1 register  ********************/
4887 #define ADC_OFR1_OFFSET1_Pos              (0U)
4888 #define ADC_OFR1_OFFSET1_Msk              (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */
4889 #define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
4890 #define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
4891 #define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
4892 #define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
4893 #define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
4894 #define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
4895 #define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
4896 #define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
4897 #define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
4898 #define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
4899 #define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
4900 #define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
4901 #define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
4902 #define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
4903 #define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
4904 #define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
4905 #define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
4906 #define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
4907 #define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
4908 #define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
4909 #define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
4910 #define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
4911 #define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
4912 #define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
4913 #define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
4914 
4915 #define ADC_OFR1_OFFSETPOS_Pos            (24U)
4916 #define ADC_OFR1_OFFSETPOS_Msk            (0x1UL << ADC_OFR1_OFFSETPOS_Pos)     /*!< 0x01000000 */
4917 #define ADC_OFR1_OFFSETPOS                ADC_OFR1_OFFSETPOS_Msk                /*!< ADC offset number 1 positive */
4918 #define ADC_OFR1_USAT_Pos                 (25U)
4919 #define ADC_OFR1_USAT_Msk                 (0x1UL << ADC_OFR1_USAT_Pos)          /*!< 0x02000000 */
4920 #define ADC_OFR1_USAT                     ADC_OFR1_USAT_Msk                     /*!< ADC offset number 1 saturation enable */
4921 
4922 #define ADC_OFR1_SSAT_Pos                 (26U)
4923 #define ADC_OFR1_SSAT_Msk                 (0x1UL << ADC_OFR1_SSAT_Pos)          /*!< 0x80000000 */
4924 #define ADC_OFR1_SSAT                     ADC_OFR1_SSAT_Msk                     /*!< ADC Signed saturation Enable */
4925 
4926 #define ADC_OFR1_OFFSET1_CH_Pos           (27U)
4927 #define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */
4928 #define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */
4929 #define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */
4930 #define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */
4931 #define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */
4932 #define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */
4933 #define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */
4934 
4935 /********************  Bit definition for ADC_OFR2 register  ********************/
4936 #define ADC_OFR2_OFFSET2_Pos              (0U)
4937 #define ADC_OFR2_OFFSET2_Msk              (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */
4938 #define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
4939 #define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
4940 #define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
4941 #define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
4942 #define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
4943 #define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
4944 #define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
4945 #define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
4946 #define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
4947 #define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
4948 #define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
4949 #define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
4950 #define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
4951 #define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
4952 #define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
4953 #define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
4954 #define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
4955 #define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
4956 #define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
4957 #define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
4958 #define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
4959 #define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
4960 #define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
4961 #define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
4962 #define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
4963 
4964 #define ADC_OFR2_OFFSETPOS_Pos            (24U)
4965 #define ADC_OFR2_OFFSETPOS_Msk            (0x1UL << ADC_OFR2_OFFSETPOS_Pos)     /*!< 0x01000000 */
4966 #define ADC_OFR2_OFFSETPOS                ADC_OFR2_OFFSETPOS_Msk                /*!< ADC offset number 1 positive */
4967 #define ADC_OFR2_USAT_Pos                 (25U)
4968 #define ADC_OFR2_USAT_Msk                 (0x1UL << ADC_OFR2_USAT_Pos)          /*!< 0x02000000 */
4969 #define ADC_OFR2_USAT                     ADC_OFR2_USAT_Msk                     /*!< ADC offset number 1 saturation enable */
4970 
4971 #define ADC_OFR2_SSAT_Pos                 (26U)
4972 #define ADC_OFR2_SSAT_Msk                 (0x1UL << ADC_OFR2_SSAT_Pos)          /*!< 0x80000000 */
4973 #define ADC_OFR2_SSAT                     ADC_OFR2_SSAT_Msk                     /*!< ADC Signed saturation Enable */
4974 
4975 #define ADC_OFR2_OFFSET2_CH_Pos           (27U)
4976 #define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */
4977 #define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */
4978 #define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */
4979 #define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */
4980 #define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */
4981 #define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */
4982 #define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */
4983 
4984 /********************  Bit definition for ADC_OFR3 register  ********************/
4985 #define ADC_OFR3_OFFSET3_Pos              (0U)
4986 #define ADC_OFR3_OFFSET3_Msk              (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */
4987 #define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
4988 #define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
4989 #define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
4990 #define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
4991 #define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
4992 #define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
4993 #define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
4994 #define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
4995 #define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
4996 #define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
4997 #define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
4998 #define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
4999 #define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
5000 #define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
5001 #define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
5002 #define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
5003 #define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
5004 #define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
5005 #define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
5006 #define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
5007 #define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
5008 #define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
5009 #define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
5010 #define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
5011 #define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
5012 
5013 #define ADC_OFR3_OFFSETPOS_Pos            (24U)
5014 #define ADC_OFR3_OFFSETPOS_Msk            (0x1UL << ADC_OFR3_OFFSETPOS_Pos)     /*!< 0x01000000 */
5015 #define ADC_OFR3_OFFSETPOS                ADC_OFR3_OFFSETPOS_Msk                /*!< ADC offset number 1 positive */
5016 #define ADC_OFR3_USAT_Pos                 (25U)
5017 #define ADC_OFR3_USAT_Msk                 (0x1UL << ADC_OFR3_USAT_Pos)          /*!< 0x02000000 */
5018 #define ADC_OFR3_USAT                     ADC_OFR3_USAT_Msk                     /*!< ADC offset number 1 saturation enable */
5019 
5020 #define ADC_OFR3_SSAT_Pos                 (26U)
5021 #define ADC_OFR3_SSAT_Msk                 (0x1UL << ADC_OFR3_SSAT_Pos)          /*!< 0x80000000 */
5022 #define ADC_OFR3_SSAT                     ADC_OFR3_SSAT_Msk                     /*!< ADC Signed saturation Enable */
5023 
5024 #define ADC_OFR3_OFFSET3_CH_Pos           (27U)
5025 #define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */
5026 #define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */
5027 #define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */
5028 #define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */
5029 #define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */
5030 #define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */
5031 #define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */
5032 
5033 /********************  Bit definition for ADC_OFR4 register  ********************/
5034 #define ADC_OFR4_OFFSET4_Pos              (0U)
5035 #define ADC_OFR4_OFFSET4_Msk              (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */
5036 #define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
5037 #define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
5038 #define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
5039 #define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
5040 #define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
5041 #define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
5042 #define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
5043 #define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
5044 #define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
5045 #define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
5046 #define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
5047 #define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
5048 #define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
5049 #define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
5050 #define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
5051 #define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
5052 #define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
5053 #define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
5054 #define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
5055 #define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
5056 #define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
5057 #define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
5058 #define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
5059 #define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
5060 #define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
5061 
5062 #define ADC_OFR4_OFFSETPOS_Pos            (24U)
5063 #define ADC_OFR4_OFFSETPOS_Msk            (0x1UL << ADC_OFR4_OFFSETPOS_Pos)     /*!< 0x01000000 */
5064 #define ADC_OFR4_OFFSETPOS                ADC_OFR4_OFFSETPOS_Msk                /*!< ADC offset number 1 positive */
5065 #define ADC_OFR4_USAT_Pos                 (25U)
5066 #define ADC_OFR4_USAT_Msk                 (0x1UL << ADC_OFR4_USAT_Pos)          /*!< 0x02000000 */
5067 #define ADC_OFR4_USAT                     ADC_OFR4_USAT_Msk                     /*!< ADC offset number 1 saturation enable */
5068 
5069 #define ADC_OFR4_SSAT_Pos                 (26U)
5070 #define ADC_OFR4_SSAT_Msk                 (0x1UL << ADC_OFR4_SSAT_Pos)          /*!< 0x80000000 */
5071 #define ADC_OFR4_SSAT                     ADC_OFR4_SSAT_Msk                     /*!< ADC Signed saturation Enable */
5072 
5073 #define ADC_OFR4_OFFSET4_CH_Pos           (27U)
5074 #define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */
5075 #define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */
5076 #define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */
5077 #define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */
5078 #define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */
5079 #define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */
5080 #define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */
5081 
5082 /********************  Bit definition for ADC_GCOMP register  ********************/
5083 #define ADC_GCOMP_GCOMPCOEFF_Pos          (0U)
5084 #define ADC_GCOMP_GCOMPCOEFF_Msk          (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */
5085 #define ADC_GCOMP_GCOMPCOEFF               ADC_GCOMP_GCOMPCOEFF_Msk             /*!< ADC Injected DATA */
5086 #define ADC_GCOMP_GCOMP_Pos               (31U)
5087 #define ADC_GCOMP_GCOMP_Msk               (0x1UL << ADC_GCOMP_GCOMP_Pos)        /*!< 0x00003FFF */
5088 #define ADC_GCOMP_GCOMP                   ADC_GCOMP_GCOMP_Msk                   /*!< ADC Injected DATA */
5089 
5090 /********************  Bit definition for ADC_JDR1 register  ********************/
5091 #define ADC_JDR1_JDATA_Pos                (0U)
5092 #define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */
5093 #define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */
5094 #define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */
5095 #define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */
5096 #define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */
5097 #define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */
5098 #define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */
5099 #define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */
5100 #define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */
5101 #define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */
5102 #define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */
5103 #define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */
5104 #define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */
5105 #define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */
5106 #define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */
5107 #define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */
5108 #define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */
5109 #define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */
5110 #define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */
5111 #define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */
5112 #define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */
5113 #define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */
5114 #define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */
5115 #define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */
5116 #define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */
5117 #define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */
5118 #define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */
5119 #define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */
5120 #define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */
5121 #define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */
5122 #define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */
5123 #define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */
5124 #define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */
5125 #define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */
5126 
5127 /********************  Bit definition for ADC_JDR2 register  ********************/
5128 #define ADC_JDR2_JDATA_Pos                (0U)
5129 #define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */
5130 #define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */
5131 #define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */
5132 #define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */
5133 #define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */
5134 #define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */
5135 #define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */
5136 #define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */
5137 #define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */
5138 #define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */
5139 #define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */
5140 #define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */
5141 #define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */
5142 #define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */
5143 #define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */
5144 #define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */
5145 #define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */
5146 #define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */
5147 #define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */
5148 #define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */
5149 #define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */
5150 #define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */
5151 #define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */
5152 #define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */
5153 #define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */
5154 #define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */
5155 #define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */
5156 #define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */
5157 #define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */
5158 #define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */
5159 #define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */
5160 #define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */
5161 #define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */
5162 #define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */
5163 
5164 /********************  Bit definition for ADC_JDR3 register  ********************/
5165 #define ADC_JDR3_JDATA_Pos                (0U)
5166 #define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */
5167 #define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */
5168 #define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */
5169 #define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */
5170 #define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */
5171 #define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */
5172 #define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */
5173 #define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */
5174 #define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */
5175 #define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */
5176 #define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */
5177 #define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */
5178 #define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */
5179 #define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */
5180 #define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */
5181 #define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */
5182 #define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */
5183 #define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */
5184 #define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */
5185 #define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */
5186 #define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */
5187 #define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */
5188 #define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */
5189 #define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */
5190 #define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */
5191 #define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */
5192 #define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */
5193 #define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */
5194 #define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */
5195 #define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */
5196 #define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */
5197 #define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */
5198 #define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */
5199 #define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */
5200 
5201 /********************  Bit definition for ADC_JDR4 register  ********************/
5202 #define ADC_JDR4_JDATA_Pos                (0U)
5203 #define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */
5204 #define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */
5205 #define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */
5206 #define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */
5207 #define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */
5208 #define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */
5209 #define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */
5210 #define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */
5211 #define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */
5212 #define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */
5213 #define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */
5214 #define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */
5215 #define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */
5216 #define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */
5217 #define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */
5218 #define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */
5219 #define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */
5220 #define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */
5221 #define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */
5222 #define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */
5223 #define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */
5224 #define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */
5225 #define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */
5226 #define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */
5227 #define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */
5228 #define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */
5229 #define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */
5230 #define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */
5231 #define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */
5232 #define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */
5233 #define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */
5234 #define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */
5235 #define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */
5236 #define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */
5237 
5238 /********************  Bit definition for ADC_AWD2CR register  ********************/
5239 #define ADC_AWD2CR_AWD2CH_Pos             (0U)
5240 #define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */
5241 #define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
5242 #define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */
5243 #define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */
5244 #define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */
5245 #define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */
5246 #define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */
5247 #define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */
5248 #define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */
5249 #define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */
5250 #define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */
5251 #define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */
5252 #define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */
5253 #define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */
5254 #define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */
5255 #define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */
5256 #define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */
5257 #define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */
5258 #define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */
5259 #define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */
5260 #define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
5261 #define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
5262 #define ADC_AWD2CR_AWD2CH_20              (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */
5263 #define ADC_AWD2CR_AWD2CH_21              (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */
5264 #define ADC_AWD2CR_AWD2CH_22              (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */
5265 #define ADC_AWD2CR_AWD2CH_23              (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */
5266 
5267 /********************  Bit definition for ADC_AWD1TR register  *******************/
5268 #define ADC_AWD1TR_LT1_Pos                (0U)
5269 #define ADC_AWD1TR_LT1_Msk                (0xFFFUL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000FFF */
5270 #define ADC_AWD1TR_LT1                    ADC_AWD1TR_LT1_Msk                   /*!< ADC analog watchdog 1 threshold low */
5271 #define ADC_AWD1TR_LT1_0                  (0x001UL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000001 */
5272 #define ADC_AWD1TR_LT1_1                  (0x002UL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000002 */
5273 #define ADC_AWD1TR_LT1_2                  (0x004UL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000004 */
5274 #define ADC_AWD1TR_LT1_3                  (0x008UL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000008 */
5275 #define ADC_AWD1TR_LT1_4                  (0x010UL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000010 */
5276 #define ADC_AWD1TR_LT1_5                  (0x020UL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000020 */
5277 #define ADC_AWD1TR_LT1_6                  (0x040UL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000040 */
5278 #define ADC_AWD1TR_LT1_7                  (0x080UL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000080 */
5279 #define ADC_AWD1TR_LT1_8                  (0x100UL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000100 */
5280 #define ADC_AWD1TR_LT1_9                  (0x200UL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000200 */
5281 #define ADC_AWD1TR_LT1_10                 (0x400UL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000400 */
5282 #define ADC_AWD1TR_LT1_11                 (0x800UL << ADC_AWD1TR_LT1_Pos)      /*!< 0x00000800 */
5283 
5284 #define ADC_AWD1TR_HT1_Pos                (16U)
5285 #define ADC_AWD1TR_HT1_Msk                (0xFFFUL << ADC_AWD1TR_HT1_Pos)      /*!< 0x0FFF0000 */
5286 #define ADC_AWD1TR_HT1                    ADC_AWD1TR_HT1_Msk                   /*!< ADC Analog watchdog 1 threshold high */
5287 #define ADC_AWD1TR_HT1_0                  (0x001UL << ADC_AWD1TR_HT1_Pos)      /*!< 0x00010000 */
5288 #define ADC_AWD1TR_HT1_1                  (0x002UL << ADC_AWD1TR_HT1_Pos)      /*!< 0x00020000 */
5289 #define ADC_AWD1TR_HT1_2                  (0x004UL << ADC_AWD1TR_HT1_Pos)      /*!< 0x00040000 */
5290 #define ADC_AWD1TR_HT1_3                  (0x008UL << ADC_AWD1TR_HT1_Pos)      /*!< 0x00080000 */
5291 #define ADC_AWD1TR_HT1_4                  (0x010UL << ADC_AWD1TR_HT1_Pos)      /*!< 0x00100000 */
5292 #define ADC_AWD1TR_HT1_5                  (0x020UL << ADC_AWD1TR_HT1_Pos)      /*!< 0x00200000 */
5293 #define ADC_AWD1TR_HT1_6                  (0x040UL << ADC_AWD1TR_HT1_Pos)      /*!< 0x00400000 */
5294 #define ADC_AWD1TR_HT1_7                  (0x080UL << ADC_AWD1TR_HT1_Pos)      /*!< 0x00800000 */
5295 #define ADC_AWD1TR_HT1_8                  (0x100UL << ADC_AWD1TR_HT1_Pos)      /*!< 0x01000000 */
5296 #define ADC_AWD1TR_HT1_9                  (0x200UL << ADC_AWD1TR_HT1_Pos)      /*!< 0x02000000 */
5297 #define ADC_AWD1TR_HT1_10                 (0x400UL << ADC_AWD1TR_HT1_Pos)      /*!< 0x04000000 */
5298 #define ADC_AWD1TR_HT1_11                 (0x800UL << ADC_AWD1TR_HT1_Pos)      /*!< 0x08000000 */
5299 
5300 /********************  Bit definition for ADC_AWDTR2 register  *******************/
5301 #define ADC_AWD2TR_LT2_Pos                (0U)
5302 #define ADC_AWD2TR_LT2_Msk                (0xFFFUL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000FFF */
5303 #define ADC_AWD2TR_LT2                    ADC_AWD2TR_LT2_Msk                   /*!< ADC analog watchdog 2 threshold low */
5304 #define ADC_AWD2TR_LT2_0                  (0x001UL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000001 */
5305 #define ADC_AWD2TR_LT2_1                  (0x002UL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000002 */
5306 #define ADC_AWD2TR_LT2_2                  (0x004UL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000004 */
5307 #define ADC_AWD2TR_LT2_3                  (0x008UL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000008 */
5308 #define ADC_AWD2TR_LT2_4                  (0x010UL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000010 */
5309 #define ADC_AWD2TR_LT2_5                  (0x020UL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000020 */
5310 #define ADC_AWD2TR_LT2_6                  (0x040UL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000040 */
5311 #define ADC_AWD2TR_LT2_7                  (0x080UL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000080 */
5312 #define ADC_AWD2TR_LT2_8                  (0x100UL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000100 */
5313 #define ADC_AWD2TR_LT2_9                  (0x200UL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000200 */
5314 #define ADC_AWD2TR_LT2_10                 (0x400UL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000400 */
5315 #define ADC_AWD2TR_LT2_11                 (0x800UL << ADC_AWD2TR_LT2_Pos)      /*!< 0x00000800 */
5316 
5317 #define ADC_AWD2TR_HT2_Pos                (16U)
5318 #define ADC_AWD2TR_HT2_Msk                (0xFFFUL << ADC_AWD2TR_HT2_Pos)      /*!< 0x0FFF0000 */
5319 #define ADC_AWD2TR_HT2                    ADC_AWD2TR_HT2_Msk                   /*!< ADC analog watchdog 2 threshold high */
5320 #define ADC_AWD2TR_HT2_0                  (0x001UL << ADC_AWD2TR_HT2_Pos)      /*!< 0x00010000 */
5321 #define ADC_AWD2TR_HT2_1                  (0x002UL << ADC_AWD2TR_HT2_Pos)      /*!< 0x00020000 */
5322 #define ADC_AWD2TR_HT2_2                  (0x004UL << ADC_AWD2TR_HT2_Pos)      /*!< 0x00040000 */
5323 #define ADC_AWD2TR_HT2_3                  (0x008UL << ADC_AWD2TR_HT2_Pos)      /*!< 0x00080000 */
5324 #define ADC_AWD2TR_HT2_4                  (0x010UL << ADC_AWD2TR_HT2_Pos)      /*!< 0x00100000 */
5325 #define ADC_AWD2TR_HT2_5                  (0x020UL << ADC_AWD2TR_HT2_Pos)      /*!< 0x00200000 */
5326 #define ADC_AWD2TR_HT2_6                  (0x040UL << ADC_AWD2TR_HT2_Pos)      /*!< 0x00400000 */
5327 #define ADC_AWD2TR_HT2_7                  (0x080UL << ADC_AWD2TR_HT2_Pos)      /*!< 0x00800000 */
5328 #define ADC_AWD2TR_HT2_8                  (0x100UL << ADC_AWD2TR_HT2_Pos)      /*!< 0x01000000 */
5329 #define ADC_AWD2TR_HT2_9                  (0x200UL << ADC_AWD2TR_HT2_Pos)      /*!< 0x02000000 */
5330 #define ADC_AWD2TR_HT2_10                 (0x400UL << ADC_AWD2TR_HT2_Pos)      /*!< 0x04000000 */
5331 #define ADC_AWD2TR_HT2_11                 (0x800UL << ADC_AWD2TR_HT2_Pos)      /*!< 0x08000000 */
5332 
5333 /********************  Bit definition for ADC_CHSELR register  ****************/
5334 #define ADC_CHSELR_CHSEL_Pos           (0U)
5335 #define ADC_CHSELR_CHSEL_Msk           (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos)    /*!< 0x0007FFFF */
5336 #define ADC_CHSELR_CHSEL               ADC_CHSELR_CHSEL_Msk                    /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
5337 
5338 #define ADC_CHSELR_CHSEL0_Pos          (0U)
5339 #define ADC_CHSELR_CHSEL0_Msk          (0x1UL << ADC_CHSELR_CHSEL0_Pos)        /*!< 0x00000001 */
5340 #define ADC_CHSELR_CHSEL0              ADC_CHSELR_CHSEL0_Msk                   /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
5341 #define ADC_CHSELR_CHSEL1_Pos          (1U)
5342 #define ADC_CHSELR_CHSEL1_Msk          (0x1UL << ADC_CHSELR_CHSEL1_Pos)        /*!< 0x00000002 */
5343 #define ADC_CHSELR_CHSEL1              ADC_CHSELR_CHSEL1_Msk                   /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
5344 #define ADC_CHSELR_CHSEL2_Pos          (2U)
5345 #define ADC_CHSELR_CHSEL2_Msk          (0x1UL << ADC_CHSELR_CHSEL2_Pos)        /*!< 0x00000004 */
5346 #define ADC_CHSELR_CHSEL2              ADC_CHSELR_CHSEL2_Msk                   /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
5347 #define ADC_CHSELR_CHSEL3_Pos          (3U)
5348 #define ADC_CHSELR_CHSEL3_Msk          (0x1UL << ADC_CHSELR_CHSEL3_Pos)        /*!< 0x00000008 */
5349 #define ADC_CHSELR_CHSEL3              ADC_CHSELR_CHSEL3_Msk                   /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
5350 #define ADC_CHSELR_CHSEL4_Pos          (4U)
5351 #define ADC_CHSELR_CHSEL4_Msk          (0x1UL << ADC_CHSELR_CHSEL4_Pos)        /*!< 0x00000010 */
5352 #define ADC_CHSELR_CHSEL4              ADC_CHSELR_CHSEL4_Msk                   /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
5353 #define ADC_CHSELR_CHSEL5_Pos          (5U)
5354 #define ADC_CHSELR_CHSEL5_Msk          (0x1UL << ADC_CHSELR_CHSEL5_Pos)        /*!< 0x00000020 */
5355 #define ADC_CHSELR_CHSEL5              ADC_CHSELR_CHSEL5_Msk                   /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
5356 #define ADC_CHSELR_CHSEL6_Pos          (6U)
5357 #define ADC_CHSELR_CHSEL6_Msk          (0x1UL << ADC_CHSELR_CHSEL6_Pos)        /*!< 0x00000040 */
5358 #define ADC_CHSELR_CHSEL6              ADC_CHSELR_CHSEL6_Msk                   /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
5359 #define ADC_CHSELR_CHSEL7_Pos          (7U)
5360 #define ADC_CHSELR_CHSEL7_Msk          (0x1UL << ADC_CHSELR_CHSEL7_Pos)        /*!< 0x00000080 */
5361 #define ADC_CHSELR_CHSEL7              ADC_CHSELR_CHSEL7_Msk                   /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
5362 #define ADC_CHSELR_CHSEL8_Pos          (8U)
5363 #define ADC_CHSELR_CHSEL8_Msk          (0x1UL << ADC_CHSELR_CHSEL8_Pos)        /*!< 0x00000100 */
5364 #define ADC_CHSELR_CHSEL8              ADC_CHSELR_CHSEL8_Msk                   /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
5365 #define ADC_CHSELR_CHSEL9_Pos          (9U)
5366 #define ADC_CHSELR_CHSEL9_Msk          (0x1UL << ADC_CHSELR_CHSEL9_Pos)        /*!< 0x00000200 */
5367 #define ADC_CHSELR_CHSEL9              ADC_CHSELR_CHSEL9_Msk                   /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
5368 #define ADC_CHSELR_CHSEL10_Pos         (10U)
5369 #define ADC_CHSELR_CHSEL10_Msk         (0x1UL << ADC_CHSELR_CHSEL10_Pos)       /*!< 0x00000400 */
5370 #define ADC_CHSELR_CHSEL10             ADC_CHSELR_CHSEL10_Msk                  /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
5371 #define ADC_CHSELR_CHSEL11_Pos         (11U)
5372 #define ADC_CHSELR_CHSEL11_Msk         (0x1UL << ADC_CHSELR_CHSEL11_Pos)       /*!< 0x00000800 */
5373 #define ADC_CHSELR_CHSEL11             ADC_CHSELR_CHSEL11_Msk                  /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
5374 #define ADC_CHSELR_CHSEL12_Pos         (12U)
5375 #define ADC_CHSELR_CHSEL12_Msk         (0x1UL << ADC_CHSELR_CHSEL12_Pos)       /*!< 0x00001000 */
5376 #define ADC_CHSELR_CHSEL12             ADC_CHSELR_CHSEL12_Msk                  /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
5377 #define ADC_CHSELR_CHSEL13_Pos         (13U)
5378 #define ADC_CHSELR_CHSEL13_Msk         (0x1UL << ADC_CHSELR_CHSEL13_Pos)       /*!< 0x00002000 */
5379 #define ADC_CHSELR_CHSEL13             ADC_CHSELR_CHSEL13_Msk                  /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
5380 #define ADC_CHSELR_CHSEL14_Pos         (14U)
5381 #define ADC_CHSELR_CHSEL14_Msk         (0x1UL << ADC_CHSELR_CHSEL14_Pos)       /*!< 0x00004000 */
5382 #define ADC_CHSELR_CHSEL14             ADC_CHSELR_CHSEL14_Msk                  /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
5383 #define ADC_CHSELR_CHSEL15_Pos         (15U)
5384 #define ADC_CHSELR_CHSEL15_Msk         (0x1UL << ADC_CHSELR_CHSEL15_Pos)       /*!< 0x00008000 */
5385 #define ADC_CHSELR_CHSEL15             ADC_CHSELR_CHSEL15_Msk                  /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
5386 #define ADC_CHSELR_CHSEL16_Pos         (16U)
5387 #define ADC_CHSELR_CHSEL16_Msk         (0x1UL << ADC_CHSELR_CHSEL16_Pos)       /*!< 0x00010000 */
5388 #define ADC_CHSELR_CHSEL16             ADC_CHSELR_CHSEL16_Msk                  /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
5389 #define ADC_CHSELR_CHSEL17_Pos         (17U)
5390 #define ADC_CHSELR_CHSEL17_Msk         (0x1UL << ADC_CHSELR_CHSEL17_Pos)       /*!< 0x00020000 */
5391 #define ADC_CHSELR_CHSEL17             ADC_CHSELR_CHSEL17_Msk                  /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
5392 #define ADC_CHSELR_CHSEL18_Pos         (18U)
5393 #define ADC_CHSELR_CHSEL18_Msk         (0x1UL << ADC_CHSELR_CHSEL18_Pos)       /*!< 0x00040000 */
5394 #define ADC_CHSELR_CHSEL18             ADC_CHSELR_CHSEL18_Msk                  /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
5395 #define ADC_CHSELR_CHSEL19_Pos         (19U)
5396 #define ADC_CHSELR_CHSEL19_Msk         (0x1UL << ADC_CHSELR_CHSEL19_Pos)       /*!< 0x00040000 */
5397 #define ADC_CHSELR_CHSEL19             ADC_CHSELR_CHSEL19_Msk                  /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
5398 #define ADC_CHSELR_CHSEL20_Pos         (20U)
5399 #define ADC_CHSELR_CHSEL20_Msk         (0x1UL << ADC_CHSELR_CHSEL20_Pos)       /*!< 0x00040000 */
5400 #define ADC_CHSELR_CHSEL20             ADC_CHSELR_CHSEL20_Msk                  /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
5401 #define ADC_CHSELR_CHSEL21_Pos         (21U)
5402 #define ADC_CHSELR_CHSEL21_Msk         (0x1UL << ADC_CHSELR_CHSEL21_Pos)       /*!< 0x00040000 */
5403 #define ADC_CHSELR_CHSEL21             ADC_CHSELR_CHSEL21_Msk                  /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
5404 #define ADC_CHSELR_CHSEL22_Pos         (22U)
5405 #define ADC_CHSELR_CHSEL22_Msk         (0x1UL << ADC_CHSELR_CHSEL22_Pos)       /*!< 0x00040000 */
5406 #define ADC_CHSELR_CHSEL22             ADC_CHSELR_CHSEL22_Msk                  /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
5407 #define ADC_CHSELR_CHSEL23_Pos         (23U)
5408 #define ADC_CHSELR_CHSEL23_Msk         (0x1UL << ADC_CHSELR_CHSEL23_Pos)       /*!< 0x00040000 */
5409 #define ADC_CHSELR_CHSEL23             ADC_CHSELR_CHSEL23_Msk                  /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
5410 
5411 #define ADC_CHSELR_SQ_ALL_Pos          (0U)
5412 #define ADC_CHSELR_SQ_ALL_Msk          (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
5413 #define ADC_CHSELR_SQ_ALL              ADC_CHSELR_SQ_ALL_Msk                   /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
5414 
5415 #define ADC_CHSELR_SQ1_Pos             (0U)
5416 #define ADC_CHSELR_SQ1_Msk             (0xFUL << ADC_CHSELR_SQ1_Pos)           /*!< 0x0000000F */
5417 #define ADC_CHSELR_SQ1                 ADC_CHSELR_SQ1_Msk                      /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
5418 #define ADC_CHSELR_SQ1_0               (0x1UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000001 */
5419 #define ADC_CHSELR_SQ1_1               (0x2UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000002 */
5420 #define ADC_CHSELR_SQ1_2               (0x4UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000004 */
5421 #define ADC_CHSELR_SQ1_3               (0x8UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000008 */
5422 
5423 #define ADC_CHSELR_SQ2_Pos             (4U)
5424 #define ADC_CHSELR_SQ2_Msk             (0xFUL << ADC_CHSELR_SQ2_Pos)           /*!< 0x000000F0 */
5425 #define ADC_CHSELR_SQ2                 ADC_CHSELR_SQ2_Msk                      /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
5426 #define ADC_CHSELR_SQ2_0               (0x1UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000010 */
5427 #define ADC_CHSELR_SQ2_1               (0x2UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000020 */
5428 #define ADC_CHSELR_SQ2_2               (0x4UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000040 */
5429 #define ADC_CHSELR_SQ2_3               (0x8UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000080 */
5430 
5431 #define ADC_CHSELR_SQ3_Pos             (8U)
5432 #define ADC_CHSELR_SQ3_Msk             (0xFUL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000F00 */
5433 #define ADC_CHSELR_SQ3                 ADC_CHSELR_SQ3_Msk                      /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
5434 #define ADC_CHSELR_SQ3_0               (0x1UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000100 */
5435 #define ADC_CHSELR_SQ3_1               (0x2UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000200 */
5436 #define ADC_CHSELR_SQ3_2               (0x4UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000400 */
5437 #define ADC_CHSELR_SQ3_3               (0x8UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000800 */
5438 
5439 #define ADC_CHSELR_SQ4_Pos             (12U)
5440 #define ADC_CHSELR_SQ4_Msk             (0xFUL << ADC_CHSELR_SQ4_Pos)           /*!< 0x0000F000 */
5441 #define ADC_CHSELR_SQ4                 ADC_CHSELR_SQ4_Msk                      /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
5442 #define ADC_CHSELR_SQ4_0               (0x1UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00001000 */
5443 #define ADC_CHSELR_SQ4_1               (0x2UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00002000 */
5444 #define ADC_CHSELR_SQ4_2               (0x4UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00004000 */
5445 #define ADC_CHSELR_SQ4_3               (0x8UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00008000 */
5446 
5447 #define ADC_CHSELR_SQ5_Pos             (16U)
5448 #define ADC_CHSELR_SQ5_Msk             (0xFUL << ADC_CHSELR_SQ5_Pos)           /*!< 0x000F0000 */
5449 #define ADC_CHSELR_SQ5                 ADC_CHSELR_SQ5_Msk                      /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
5450 #define ADC_CHSELR_SQ5_0               (0x1UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00010000 */
5451 #define ADC_CHSELR_SQ5_1               (0x2UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00020000 */
5452 #define ADC_CHSELR_SQ5_2               (0x4UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00040000 */
5453 #define ADC_CHSELR_SQ5_3               (0x8UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00080000 */
5454 
5455 #define ADC_CHSELR_SQ6_Pos             (20U)
5456 #define ADC_CHSELR_SQ6_Msk             (0xFUL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00F00000 */
5457 #define ADC_CHSELR_SQ6                 ADC_CHSELR_SQ6_Msk                      /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
5458 #define ADC_CHSELR_SQ6_0               (0x1UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00100000 */
5459 #define ADC_CHSELR_SQ6_1               (0x2UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00200000 */
5460 #define ADC_CHSELR_SQ6_2               (0x4UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00400000 */
5461 #define ADC_CHSELR_SQ6_3               (0x8UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00800000 */
5462 
5463 #define ADC_CHSELR_SQ7_Pos             (24U)
5464 #define ADC_CHSELR_SQ7_Msk             (0xFUL << ADC_CHSELR_SQ7_Pos)           /*!< 0x0F000000 */
5465 #define ADC_CHSELR_SQ7                 ADC_CHSELR_SQ7_Msk                      /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
5466 #define ADC_CHSELR_SQ7_0               (0x1UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x01000000 */
5467 #define ADC_CHSELR_SQ7_1               (0x2UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x02000000 */
5468 #define ADC_CHSELR_SQ7_2               (0x4UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x04000000 */
5469 #define ADC_CHSELR_SQ7_3               (0x8UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x08000000 */
5470 
5471 #define ADC_CHSELR_SQ8_Pos             (28U)
5472 #define ADC_CHSELR_SQ8_Msk             (0xFUL << ADC_CHSELR_SQ8_Pos)           /*!< 0xF0000000 */
5473 #define ADC_CHSELR_SQ8                 ADC_CHSELR_SQ8_Msk                      /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
5474 #define ADC_CHSELR_SQ8_0               (0x1UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x10000000 */
5475 #define ADC_CHSELR_SQ8_1               (0x2UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x20000000 */
5476 #define ADC_CHSELR_SQ8_2               (0x4UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x40000000 */
5477 #define ADC_CHSELR_SQ8_3               (0x8UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x80000000 */
5478 
5479 /********************  Bit definition for ADC_AWD3TR register  *******************/
5480 #define ADC_AWD3TR_LT3_Pos                (0U)
5481 #define ADC_AWD3TR_LT3_Msk                (0xFFFUL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000FFF */
5482 #define ADC_AWD3TR_LT3                    ADC_AWD3TR_LT3_Msk                   /*!< ADC analog watchdog 3 threshold low */
5483 #define ADC_AWD3TR_LT3_0                  (0x001UL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000001 */
5484 #define ADC_AWD3TR_LT3_1                  (0x002UL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000002 */
5485 #define ADC_AWD3TR_LT3_2                  (0x004UL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000004 */
5486 #define ADC_AWD3TR_LT3_3                  (0x008UL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000008 */
5487 #define ADC_AWD3TR_LT3_4                  (0x010UL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000010 */
5488 #define ADC_AWD3TR_LT3_5                  (0x020UL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000020 */
5489 #define ADC_AWD3TR_LT3_6                  (0x040UL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000040 */
5490 #define ADC_AWD3TR_LT3_7                  (0x080UL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000080 */
5491 #define ADC_AWD3TR_LT3_8                  (0x100UL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000100 */
5492 #define ADC_AWD3TR_LT3_9                  (0x200UL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000200 */
5493 #define ADC_AWD3TR_LT3_10                 (0x400UL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000400 */
5494 #define ADC_AWD3TR_LT3_11                 (0x800UL << ADC_AWD3TR_LT3_Pos)      /*!< 0x00000800 */
5495 
5496 #define ADC_AWD3TR_HT3_Pos                (16U)
5497 #define ADC_AWD3TR_HT3_Msk                (0xFFFUL << ADC_AWD3TR_HT3_Pos)      /*!< 0x0FFF0000 */
5498 #define ADC_AWD3TR_HT3                    ADC_AWD3TR_HT3_Msk                   /*!< ADC analog watchdog 3 threshold high */
5499 #define ADC_AWD3TR_HT3_0                  (0x001UL << ADC_AWD3TR_HT3_Pos)      /*!< 0x00010000 */
5500 #define ADC_AWD3TR_HT3_1                  (0x002UL << ADC_AWD3TR_HT3_Pos)      /*!< 0x00020000 */
5501 #define ADC_AWD3TR_HT3_2                  (0x004UL << ADC_AWD3TR_HT3_Pos)      /*!< 0x00040000 */
5502 #define ADC_AWD3TR_HT3_3                  (0x008UL << ADC_AWD3TR_HT3_Pos)      /*!< 0x00080000 */
5503 #define ADC_AWD3TR_HT3_4                  (0x010UL << ADC_AWD3TR_HT3_Pos)      /*!< 0x00100000 */
5504 #define ADC_AWD3TR_HT3_5                  (0x020UL << ADC_AWD3TR_HT3_Pos)      /*!< 0x00200000 */
5505 #define ADC_AWD3TR_HT3_6                  (0x040UL << ADC_AWD3TR_HT3_Pos)      /*!< 0x00400000 */
5506 #define ADC_AWD3TR_HT3_7                  (0x080UL << ADC_AWD3TR_HT3_Pos)      /*!< 0x00800000 */
5507 #define ADC_AWD3TR_HT3_8                  (0x100UL << ADC_AWD3TR_HT3_Pos)      /*!< 0x01000000 */
5508 #define ADC_AWD3TR_HT3_9                  (0x200UL << ADC_AWD3TR_HT3_Pos)      /*!< 0x02000000 */
5509 #define ADC_AWD3TR_HT3_10                 (0x400UL << ADC_AWD3TR_HT3_Pos)      /*!< 0x04000000 */
5510 #define ADC_AWD3TR_HT3_11                 (0x800UL << ADC_AWD3TR_HT3_Pos)      /*!< 0x08000000 */
5511 
5512 /********************  Bit definition for ADC_AWD3CR register  ********************/
5513 #define ADC_AWD3CR_AWD3CH_Pos             (0U)
5514 #define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */
5515 #define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
5516 #define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */
5517 #define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */
5518 #define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */
5519 #define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */
5520 #define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */
5521 #define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */
5522 #define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */
5523 #define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */
5524 #define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */
5525 #define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */
5526 #define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */
5527 #define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */
5528 #define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */
5529 #define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */
5530 #define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */
5531 #define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */
5532 #define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */
5533 #define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */
5534 #define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
5535 #define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
5536 #define ADC_AWD3CR_AWD2CH_20              (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */
5537 #define ADC_AWD3CR_AWD2CH_21              (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */
5538 #define ADC_AWD3CR_AWD2CH_22              (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */
5539 #define ADC_AWD3CR_AWD2CH_23              (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */
5540 
5541 /********************  Bit definition for ADC_DIFSEL register  ********************/
5542 #define ADC_DIFSEL_DIFSEL_Pos             (0U)
5543 #define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
5544 #define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */
5545 #define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */
5546 #define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */
5547 #define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */
5548 #define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */
5549 #define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */
5550 #define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */
5551 #define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */
5552 #define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */
5553 #define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */
5554 #define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */
5555 #define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */
5556 #define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */
5557 #define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */
5558 #define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */
5559 #define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */
5560 #define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */
5561 #define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */
5562 #define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */
5563 #define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */
5564 #define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */
5565 
5566 /********************  Bit definition for ADC_CALFACT register  ********************/
5567 #define ADC_CALFACT_I_APB_ADDR_Pos         (0U)
5568 #define ADC_CALFACT_I_APB_ADDR_Msk         (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */
5569 #define ADC_CALFACT_I_APB_ADDR             ADC_CALFACT_I_APB_ADDR_Msk             /*!< ADC calibration factors in single-ended mode */
5570 #define ADC_CALFACT_I_APB_ADDR_0           (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */
5571 #define ADC_CALFACT_I_APB_ADDR_1           (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */
5572 #define ADC_CALFACT_I_APB_ADDR_2           (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */
5573 #define ADC_CALFACT_I_APB_ADDR_3           (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */
5574 #define ADC_CALFACT_I_APB_ADDR_4           (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */
5575 #define ADC_CALFACT_I_APB_ADDR_5           (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */
5576 #define ADC_CALFACT_I_APB_ADDR_6           (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */
5577 #define ADC_CALFACT_I_APB_ADDR_7           (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */
5578 
5579 #define ADC_CALFACT_I_APB_DATA_Pos         (08U)
5580 #define ADC_CALFACT_I_APB_DATA_Msk         (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */
5581 #define ADC_CALFACT_I_APB_DATA             ADC_CALFACT_I_APB_DATA_Msk             /*!< ADC calibration factors in differential mode */
5582 #define ADC_CALFACT_APB_DATA_0             (0x001U << ADC_CALFACT_APB_DATA_Pos)   /*!< 0x00000100 */
5583 #define ADC_CALFACT_APB_DATA_1             (0x002U << ADC_CALFACT_APB_DATA_Pos)   /*!< 0x00000200 */
5584 #define ADC_CALFACT_APB_DATA_2             (0x004U << ADC_CALFACT_APB_DATA_Pos)   /*!< 0x00000400 */
5585 #define ADC_CALFACT_APB_DATA_3             (0x008U << ADC_CALFACT_APB_DATA_Pos)   /*!< 0x00000800 */
5586 #define ADC_CALFACT_APB_DATA_4             (0x010U << ADC_CALFACT_APB_DATA_Pos)   /*!< 0x00001000 */
5587 #define ADC_CALFACT_APB_DATA_5             (0x020U << ADC_CALFACT_APB_DATA_Pos)   /*!< 0x00002000 */
5588 #define ADC_CALFACT_APB_DATA_6             (0x040U << ADC_CALFACT_APB_DATA_Pos)   /*!< 0x00004000 */
5589 #define ADC_CALFACT_APB_DATA_7             (0x080U << ADC_CALFACT_APB_DATA_Pos)   /*!< 0x00008000 */
5590 
5591 #define ADC_CALFACT_VALIDITY_Pos           (16U)
5592 #define ADC_CALFACT_VALIDITY_Msk           (0x1UL << ADC_CALFACT_VALIDITY_Pos)     /*!< 0x00010000 */
5593 #define ADC_CALFACT_VALIDITY               ADC_CALFACT_VALIDITY_Msk                /*!< ADC calibration factors in differential mode */
5594 #define ADC_CALFACT_LATCH_COEF_Pos         (24U)
5595 #define ADC_CALFACT_LATCH_COEF_Msk         (0x1UL << ADC_CALFACT_LATCH_COEF_Pos)   /*!< 0x01000000 */
5596 #define ADC_CALFACT_LATCH_COEF             ADC_CALFACT_LATCH_COEF_Msk              /*!< ADC calibration factors in differential mode */
5597 #define ADC_CALFACT_CAPTURE_COEF_Pos       (25U)
5598 #define ADC_CALFACT_CAPTURE_COEF_Msk       (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */
5599 #define ADC_CALFACT_CAPTURE_COEF           ADC_CALFACT_CAPTURE_COEF_Msk            /*!< ADC calibration factors in differential mode */
5600 
5601 #define ADC4_CALFACT_CALFACT_Pos        (0U)
5602 #define ADC4_CALFACT_CALFACT_Msk        (0x7FUL << ADC4_CALFACT_CALFACT_Pos)     /*!< 0x0000007F */
5603 #define ADC4_CALFACT_CALFACT            ADC4_CALFACT_CALFACT_Msk                 /*!< ADC calibration factor in single-ended mode */
5604 #define ADC4_CALFACT_CALFACT_0          (0x01UL << ADC4_CALFACT_CALFACT_Pos)     /*!< 0x00000001 */
5605 #define ADC4_CALFACT_CALFACT_1          (0x02UL << ADC4_CALFACT_CALFACT_Pos)     /*!< 0x00000002 */
5606 #define ADC4_CALFACT_CALFACT_2          (0x04UL << ADC4_CALFACT_CALFACT_Pos)     /*!< 0x00000004 */
5607 #define ADC4_CALFACT_CALFACT_3          (0x08UL << ADC4_CALFACT_CALFACT_Pos)     /*!< 0x00000008 */
5608 #define ADC4_CALFACT_CALFACT_4          (0x10UL << ADC4_CALFACT_CALFACT_Pos)     /*!< 0x00000010 */
5609 #define ADC4_CALFACT_CALFACT_5          (0x20UL << ADC4_CALFACT_CALFACT_Pos)     /*!< 0x00000020 */
5610 #define ADC4_CALFACT_CALFACT_6          (0x40UL << ADC4_CALFACT_CALFACT_Pos)     /*!< 0x00000040 */
5611 
5612 /********************  Bit definition for ADC_CALFACT2 register  ********************/
5613 #define ADC_CALFACT2_CALFACT_Pos       (0U)
5614 #define ADC_CALFACT2_CALFACT_Msk       (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */
5615 #define ADC_CALFACT2_CALFACT           ADC_CALFACT2_CALFACT_Msk                   /*!< ADC Linearity calibration factors */
5616 #define ADC_CALFACT2_CALFACT_0         (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */
5617 #define ADC_CALFACT2_CALFACT_1         (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */
5618 #define ADC_CALFACT2_CALFACT_2         (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */
5619 #define ADC_CALFACT2_CALFACT_3         (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */
5620 #define ADC_CALFACT2_CALFACT_4         (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */
5621 #define ADC_CALFACT2_CALFACT_5         (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */
5622 #define ADC_CALFACT2_CALFACT_6         (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */
5623 #define ADC_CALFACT2_CALFACT_7         (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */
5624 #define ADC_CALFACT2_CALFACT_8         (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */
5625 #define ADC_CALFACT2_CALFACT_9         (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */
5626 #define ADC_CALFACT2_CALFACT_10        (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */
5627 #define ADC_CALFACT2_CALFACT_11        (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */
5628 #define ADC_CALFACT2_CALFACT_12        (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */
5629 #define ADC_CALFACT2_CALFACT_13        (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */
5630 #define ADC_CALFACT2_CALFACT_14        (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */
5631 #define ADC_CALFACT2_CALFACT_15        (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */
5632 #define ADC_CALFACT2_CALFACT_16        (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */
5633 #define ADC_CALFACT2_CALFACT_17        (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */
5634 #define ADC_CALFACT2_CALFACT_18        (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */
5635 #define ADC_CALFACT2_CALFACT_19        (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */
5636 #define ADC_CALFACT2_CALFACT_20        (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */
5637 #define ADC_CALFACT2_CALFACT_21        (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */
5638 #define ADC_CALFACT2_CALFACT_22        (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */
5639 #define ADC_CALFACT2_CALFACT_23        (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */
5640 #define ADC_CALFACT2_CALFACT_24        (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */
5641 #define ADC_CALFACT2_CALFACT_25        (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */
5642 #define ADC_CALFACT2_CALFACT_26        (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */
5643 #define ADC_CALFACT2_CALFACT_27        (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */
5644 #define ADC_CALFACT2_CALFACT_28        (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */
5645 #define ADC_CALFACT2_CALFACT_29        (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */
5646 #define ADC_CALFACT2_CALFACT_30        (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */
5647 #define ADC_CALFACT2_CALFACT_31        (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */
5648 
5649 /********************  Bit definition for ADC_OR register  ********************/
5650 #define ADC_OR_CHN0SEL_Pos             (0U)
5651 #define ADC_OR_CHN0SEL_Msk             (0x1UL << ADC_OR_CHN0SEL_Pos)              /*!< 0x00000001 */
5652 #define ADC_OR_CHN0SEL                 ADC_OR_CHN0SEL_Msk                         /*!< ADC Channel 0 selection */
5653 
5654 /*************************  ADC Common registers  *****************************/
5655 /********************  Bit definition for ADC_CSR register  ********************/
5656 #define ADC_CSR_ADRDY_MST_Pos             (0U)
5657 #define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
5658 #define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */
5659 #define ADC_CSR_EOSMP_MST_Pos             (1U)
5660 #define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */
5661 #define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */
5662 #define ADC_CSR_EOC_MST_Pos               (2U)
5663 #define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */
5664 #define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */
5665 #define ADC_CSR_EOS_MST_Pos               (3U)
5666 #define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */
5667 #define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */
5668 #define ADC_CSR_OVR_MST_Pos               (4U)
5669 #define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */
5670 #define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */
5671 #define ADC_CSR_JEOC_MST_Pos              (5U)
5672 #define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */
5673 #define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */
5674 #define ADC_CSR_JEOS_MST_Pos              (6U)
5675 #define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */
5676 #define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */
5677 #define ADC_CSR_AWD1_MST_Pos              (7U)
5678 #define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
5679 #define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */
5680 #define ADC_CSR_AWD2_MST_Pos              (8U)
5681 #define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
5682 #define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */
5683 #define ADC_CSR_AWD3_MST_Pos              (9U)
5684 #define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
5685 #define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */
5686 #define ADC_CSR_JQOVF_MST_Pos             (10U)
5687 #define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
5688 #define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */
5689 #define ADC_CSR_LDORDY_MST_Pos            (12U)
5690 #define ADC_CSR_LDORDY_MST_Msk            (0x1UL << ADC_CSR_LDORDY_MST_Pos)     /*!< 0x00001000 */
5691 #define ADC_CSR_LDORDY_MST                ADC_CSR_LDORDY_MST_Msk                /*!< Voltage regulator ready flag of the master ADC */
5692 #define ADC_CSR_ADRDY_SLV_Pos             (16U)
5693 #define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
5694 #define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */
5695 #define ADC_CSR_EOSMP_SLV_Pos             (17U)
5696 #define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */
5697 #define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */
5698 #define ADC_CSR_EOC_SLV_Pos               (18U)
5699 #define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */
5700 #define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */
5701 #define ADC_CSR_EOS_SLV_Pos               (19U)
5702 #define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */
5703 #define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */
5704 #define ADC_CSR_OVR_SLV_Pos               (20U)
5705 #define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */
5706 #define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */
5707 #define ADC_CSR_JEOC_SLV_Pos              (21U)
5708 #define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */
5709 #define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */
5710 #define ADC_CSR_JEOS_SLV_Pos              (22U)
5711 #define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */
5712 #define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */
5713 #define ADC_CSR_AWD1_SLV_Pos              (23U)
5714 #define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
5715 #define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */
5716 #define ADC_CSR_AWD2_SLV_Pos              (24U)
5717 #define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
5718 #define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */
5719 #define ADC_CSR_AWD3_SLV_Pos              (25U)
5720 #define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
5721 #define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */
5722 #define ADC_CSR_JQOVF_SLV_Pos             (26U)
5723 #define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
5724 #define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */
5725 #define ADC_CSR_LDORDY_SLV_Pos            (28U)
5726 #define ADC_CSR_LDORDY_SLV_Msk            (0x1UL << ADC_CSR_LDORDY_SLV_Pos)     /*!< 0x10000000 */
5727 #define ADC_CSR_LDORDY_SLV                ADC_CSR_LDORDY_SLV_Msk                /*!< Voltage regulator ready flag of the slave ADC */
5728 
5729 /********************  Bit definition for ADC_CCR register  ********************/
5730 #define ADC_CCR_DUAL_Pos                  (0U)
5731 #define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */
5732 #define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */
5733 #define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */
5734 #define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */
5735 #define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */
5736 #define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */
5737 #define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */
5738 
5739 #define ADC_CCR_DELAY_Pos                 (8U)
5740 #define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */
5741 #define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */
5742 #define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */
5743 #define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */
5744 #define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */
5745 #define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */
5746 
5747 #define ADC_CCR_DAMDF_Pos                 (14U)
5748 #define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */
5749 #define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode data format */
5750 #define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */
5751 #define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */
5752 
5753 #define ADC_CCR_PRESC_Pos                 (18U)
5754 #define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */
5755 #define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */
5756 #define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */
5757 #define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */
5758 #define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */
5759 #define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */
5760 
5761 #define ADC_CCR_VREFEN_Pos                (22U)
5762 #define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */
5763 #define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */
5764 #define ADC_CCR_VSENSEEN_Pos              (23U)
5765 #define ADC_CCR_VSENSEEN_Msk              (0x1UL << ADC_CCR_VSENSEEN_Pos)       /*!< 0x00800000 */
5766 #define ADC_CCR_VSENSEEN                  ADC_CCR_VSENSEEN_Msk                  /*!< Temperature sensor enable */
5767 #define ADC_CCR_VBATEN_Pos                (24U)
5768 #define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */
5769 #define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */
5770 #define ADC_CCR_LFMEN_Pos                 (25U)
5771 #define ADC_CCR_LFMEN_Msk                 (0x1UL << ADC_CCR_LFMEN_Pos)          /*!< 0x02000000 */
5772 #define ADC_CCR_LFMEN                     ADC_CCR_LFMEN_Msk                     /*!< Low Frequency Mode Enable, specific ADC4*/
5773 #define ADC_CCR_VDDCOREN_Pos              (26U)
5774 #define ADC_CCR_VDDCOREN_Msk              (0x1UL << ADC_CCR_VDDCOREN_Pos)       /*!< 0x04000000 */
5775 #define ADC_CCR_VDDCOREN                  ADC_CCR_VDDCOREN_Msk                  /*!< VDDCode enable */
5776 
5777 /********************  Bit definition for ADC_CDR register  *******************/
5778 #define ADC_CDR_RDATA_MST_Pos             (0U)
5779 #define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */
5780 #define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */
5781 
5782 #define ADC_CDR_RDATA_SLV_Pos             (16U)
5783 #define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */
5784 #define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */
5785 
5786 /********************  Bit definition for ADC_CDR2 register  ******************/
5787 #define ADC_CDR2_RDATA_ALT_Pos            (0U)
5788 #define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
5789 #define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */
5790 
5791 /******************************************************************************/
5792 /*                                                                            */
5793 /*                          CORDIC calculation unit                           */
5794 /*                                                                            */
5795 /******************************************************************************/
5796 /*******************  Bit definition for CORDIC_CSR register  *****************/
5797 #define CORDIC_CSR_FUNC_Pos                 (0U)
5798 #define CORDIC_CSR_FUNC_Msk                 (0xFUL << CORDIC_CSR_FUNC_Pos)          /*!< 0x0000000F */
5799 #define CORDIC_CSR_FUNC                     CORDIC_CSR_FUNC_Msk                     /*!< Function */
5800 #define CORDIC_CSR_FUNC_0                   (0x1UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000001 */
5801 #define CORDIC_CSR_FUNC_1                   (0x2UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000002 */
5802 #define CORDIC_CSR_FUNC_2                   (0x4UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000004 */
5803 #define CORDIC_CSR_FUNC_3                   (0x8UL << CORDIC_CSR_FUNC_Pos)          /*!< 0x00000008 */
5804 #define CORDIC_CSR_PRECISION_Pos            (4U)
5805 #define CORDIC_CSR_PRECISION_Msk            (0xFUL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x000000F0 */
5806 #define CORDIC_CSR_PRECISION                CORDIC_CSR_PRECISION_Msk                /*!< Precision */
5807 #define CORDIC_CSR_PRECISION_0              (0x1UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000010 */
5808 #define CORDIC_CSR_PRECISION_1              (0x2UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000020 */
5809 #define CORDIC_CSR_PRECISION_2              (0x4UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000040 */
5810 #define CORDIC_CSR_PRECISION_3              (0x8UL << CORDIC_CSR_PRECISION_Pos)     /*!< 0x00000080 */
5811 #define CORDIC_CSR_SCALE_Pos                (8U)
5812 #define CORDIC_CSR_SCALE_Msk                (0x7UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000700 */
5813 #define CORDIC_CSR_SCALE                    CORDIC_CSR_SCALE_Msk                    /*!< Scaling factor */
5814 #define CORDIC_CSR_SCALE_0                  (0x1UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000100 */
5815 #define CORDIC_CSR_SCALE_1                  (0x2UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000200 */
5816 #define CORDIC_CSR_SCALE_2                  (0x4UL << CORDIC_CSR_SCALE_Pos)         /*!< 0x00000400 */
5817 #define CORDIC_CSR_IEN_Pos                  (16U)
5818 #define CORDIC_CSR_IEN_Msk                  (0x1UL << CORDIC_CSR_IEN_Pos)           /*!< 0x00010000 */
5819 #define CORDIC_CSR_IEN                      CORDIC_CSR_IEN_Msk                      /*!< Interrupt Enable */
5820 #define CORDIC_CSR_DMAREN_Pos               (17U)
5821 #define CORDIC_CSR_DMAREN_Msk               (0x1UL << CORDIC_CSR_DMAREN_Pos)        /*!< 0x00020000 */
5822 #define CORDIC_CSR_DMAREN                   CORDIC_CSR_DMAREN_Msk                   /*!< DMA Read channel Enable */
5823 #define CORDIC_CSR_DMAWEN_Pos               (18U)
5824 #define CORDIC_CSR_DMAWEN_Msk               (0x1UL << CORDIC_CSR_DMAWEN_Pos)        /*!< 0x00040000 */
5825 #define CORDIC_CSR_DMAWEN                   CORDIC_CSR_DMAWEN_Msk                   /*!< DMA Write channel Enable */
5826 #define CORDIC_CSR_NRES_Pos                 (19U)
5827 #define CORDIC_CSR_NRES_Msk                 (0x1UL << CORDIC_CSR_NRES_Pos)          /*!< 0x00080000 */
5828 #define CORDIC_CSR_NRES                     CORDIC_CSR_NRES_Msk                     /*!< Number of results in WDATA register */
5829 #define CORDIC_CSR_NARGS_Pos                (20U)
5830 #define CORDIC_CSR_NARGS_Msk                (0x1UL << CORDIC_CSR_NARGS_Pos)         /*!< 0x00100000 */
5831 #define CORDIC_CSR_NARGS                    CORDIC_CSR_NARGS_Msk                    /*!< Number of arguments in RDATA register */
5832 #define CORDIC_CSR_RESSIZE_Pos              (21U)
5833 #define CORDIC_CSR_RESSIZE_Msk              (0x1UL << CORDIC_CSR_RESSIZE_Pos)       /*!< 0x00200000 */
5834 #define CORDIC_CSR_RESSIZE                  CORDIC_CSR_RESSIZE_Msk                  /*!< Width of output data */
5835 #define CORDIC_CSR_ARGSIZE_Pos              (22U)
5836 #define CORDIC_CSR_ARGSIZE_Msk              (0x1UL << CORDIC_CSR_ARGSIZE_Pos)       /*!< 0x00400000 */
5837 #define CORDIC_CSR_ARGSIZE                  CORDIC_CSR_ARGSIZE_Msk                  /*!< Width of input data */
5838 #define CORDIC_CSR_RRDY_Pos                 (31U)
5839 #define CORDIC_CSR_RRDY_Msk                 (0x1UL << CORDIC_CSR_RRDY_Pos)          /*!< 0x80000000 */
5840 #define CORDIC_CSR_RRDY                     CORDIC_CSR_RRDY_Msk                     /*!< Result Ready Flag */
5841 
5842 /*******************  Bit definition for CORDIC_WDATA register  ***************/
5843 #define CORDIC_WDATA_ARG_Pos                (0U)
5844 #define CORDIC_WDATA_ARG_Msk                (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)  /*!< 0xFFFFFFFF */
5845 #define CORDIC_WDATA_ARG                    CORDIC_WDATA_ARG_Msk                    /*!< Input Argument */
5846 
5847 /*******************  Bit definition for CORDIC_RDATA register  ***************/
5848 #define CORDIC_RDATA_RES_Pos                (0U)
5849 #define CORDIC_RDATA_RES_Msk                (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)  /*!< 0xFFFFFFFF */
5850 #define CORDIC_RDATA_RES                    CORDIC_RDATA_RES_Msk                    /*!< Output Result */
5851 
5852 /******************************************************************************/
5853 /*                                                                            */
5854 /*                          CRC calculation unit                              */
5855 /*                                                                            */
5856 /******************************************************************************/
5857 /*******************  Bit definition for CRC_DR register  *********************/
5858 #define CRC_DR_DR_Pos                       (0U)
5859 #define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)         /*!< 0xFFFFFFFF */
5860 #define CRC_DR_DR                           CRC_DR_DR_Msk                           /*!< Data register bits */
5861 
5862 /*******************  Bit definition for CRC_IDR register  ********************/
5863 #define CRC_IDR_IDR_Pos                     (0U)
5864 #define CRC_IDR_IDR_Msk                     (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)       /*!< 0xFFFFFFFF */
5865 #define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                         /*!< General-purpose 32-bits data register bits */
5866 
5867 /********************  Bit definition for CRC_CR register  ********************/
5868 #define CRC_CR_RESET_Pos                    (0U)
5869 #define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)             /*!< 0x00000001 */
5870 #define CRC_CR_RESET                        CRC_CR_RESET_Msk                        /*!< RESET the CRC computation unit bit */
5871 #define CRC_CR_POLYSIZE_Pos                 (3U)
5872 #define CRC_CR_POLYSIZE_Msk                 (0x3UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000018 */
5873 #define CRC_CR_POLYSIZE                     CRC_CR_POLYSIZE_Msk                     /*!< Polynomial size bits */
5874 #define CRC_CR_POLYSIZE_0                   (0x1UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000008 */
5875 #define CRC_CR_POLYSIZE_1                   (0x2UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000010 */
5876 #define CRC_CR_REV_IN_Pos                   (5U)
5877 #define CRC_CR_REV_IN_Msk                   (0x3UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000060 */
5878 #define CRC_CR_REV_IN                       CRC_CR_REV_IN_Msk                       /*!< REV_IN Reverse Input Data bits */
5879 #define CRC_CR_REV_IN_0                     (0x1UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000020 */
5880 #define CRC_CR_REV_IN_1                     (0x2UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000040 */
5881 #define CRC_CR_REV_OUT_Pos                  (7U)
5882 #define CRC_CR_REV_OUT_Msk                  (0x1UL << CRC_CR_REV_OUT_Pos)           /*!< 0x00000080 */
5883 #define CRC_CR_REV_OUT                      CRC_CR_REV_OUT_Msk                      /*!< REV_OUT Reverse Output Data bits */
5884 
5885 /*******************  Bit definition for CRC_INIT register  *******************/
5886 #define CRC_INIT_INIT_Pos                   (0U)
5887 #define CRC_INIT_INIT_Msk                   (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)     /*!< 0xFFFFFFFF */
5888 #define CRC_INIT_INIT                       CRC_INIT_INIT_Msk                       /*!< Initial CRC value bits */
5889 
5890 /*******************  Bit definition for CRC_POL register  ********************/
5891 #define CRC_POL_POL_Pos                     (0U)
5892 #define CRC_POL_POL_Msk                     (0xFFFFFFFFUL << CRC_POL_POL_Pos)       /*!< 0xFFFFFFFF */
5893 #define CRC_POL_POL                         CRC_POL_POL_Msk                         /*!< Coefficients of the polynomial */
5894 
5895 /******************************************************************************/
5896 /*                                                                            */
5897 /*                          CRS Clock Recovery System                         */
5898 /******************************************************************************/
5899 /*******************  Bit definition for CRS_CR register  *********************/
5900 #define CRS_CR_SYNCOKIE_Pos                 (0U)
5901 #define CRS_CR_SYNCOKIE_Msk                 (0x1UL << CRS_CR_SYNCOKIE_Pos)          /*!< 0x00000001 */
5902 #define CRS_CR_SYNCOKIE                     CRS_CR_SYNCOKIE_Msk                     /*!< SYNC event OK interrupt enable */
5903 #define CRS_CR_SYNCWARNIE_Pos               (1U)
5904 #define CRS_CR_SYNCWARNIE_Msk               (0x1UL << CRS_CR_SYNCWARNIE_Pos)        /*!< 0x00000002 */
5905 #define CRS_CR_SYNCWARNIE                   CRS_CR_SYNCWARNIE_Msk                   /*!< SYNC warning interrupt enable */
5906 #define CRS_CR_ERRIE_Pos                    (2U)
5907 #define CRS_CR_ERRIE_Msk                    (0x1UL << CRS_CR_ERRIE_Pos)             /*!< 0x00000004 */
5908 #define CRS_CR_ERRIE                        CRS_CR_ERRIE_Msk                        /*!< SYNC error or trimming error interrupt enable */
5909 #define CRS_CR_ESYNCIE_Pos                  (3U)
5910 #define CRS_CR_ESYNCIE_Msk                  (0x1UL << CRS_CR_ESYNCIE_Pos)           /*!< 0x00000008 */
5911 #define CRS_CR_ESYNCIE                      CRS_CR_ESYNCIE_Msk                      /*!< Expected SYNC interrupt enable */
5912 #define CRS_CR_CEN_Pos                      (5U)
5913 #define CRS_CR_CEN_Msk                      (0x1UL << CRS_CR_CEN_Pos)               /*!< 0x00000020 */
5914 #define CRS_CR_CEN                          CRS_CR_CEN_Msk                          /*!< Frequency error counter enable */
5915 #define CRS_CR_AUTOTRIMEN_Pos               (6U)
5916 #define CRS_CR_AUTOTRIMEN_Msk               (0x1UL << CRS_CR_AUTOTRIMEN_Pos)        /*!< 0x00000040 */
5917 #define CRS_CR_AUTOTRIMEN                   CRS_CR_AUTOTRIMEN_Msk                   /*!< Automatic trimming enable */
5918 #define CRS_CR_SWSYNC_Pos                   (7U)
5919 #define CRS_CR_SWSYNC_Msk                   (0x1UL << CRS_CR_SWSYNC_Pos)            /*!< 0x00000080 */
5920 #define CRS_CR_SWSYNC                       CRS_CR_SWSYNC_Msk                       /*!< Generate software SYNC event */
5921 #define CRS_CR_TRIM_Pos                     (8U)
5922 #define CRS_CR_TRIM_Msk                     (0x7FUL << CRS_CR_TRIM_Pos)             /*!< 0x00007F00 */
5923 #define CRS_CR_TRIM                         CRS_CR_TRIM_Msk                         /*!< HSI48 oscillator smooth trimming */
5924 
5925 /*******************  Bit definition for CRS_CFGR register  *********************/
5926 #define CRS_CFGR_RELOAD_Pos                 (0U)
5927 #define CRS_CFGR_RELOAD_Msk                 (0xFFFFUL << CRS_CFGR_RELOAD_Pos)       /*!< 0x0000FFFF */
5928 #define CRS_CFGR_RELOAD                     CRS_CFGR_RELOAD_Msk                     /*!< Counter reload value */
5929 #define CRS_CFGR_FELIM_Pos                  (16U)
5930 #define CRS_CFGR_FELIM_Msk                  (0xFFUL << CRS_CFGR_FELIM_Pos)          /*!< 0x00FF0000 */
5931 #define CRS_CFGR_FELIM                      CRS_CFGR_FELIM_Msk                      /*!< Frequency error limit */
5932 #define CRS_CFGR_SYNCDIV_Pos                (24U)
5933 #define CRS_CFGR_SYNCDIV_Msk                (0x7UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x07000000 */
5934 #define CRS_CFGR_SYNCDIV                    CRS_CFGR_SYNCDIV_Msk                    /*!< SYNC divider */
5935 #define CRS_CFGR_SYNCDIV_0                  (0x1UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x01000000 */
5936 #define CRS_CFGR_SYNCDIV_1                  (0x2UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x02000000 */
5937 #define CRS_CFGR_SYNCDIV_2                  (0x4UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x04000000 */
5938 #define CRS_CFGR_SYNCSRC_Pos                (28U)
5939 #define CRS_CFGR_SYNCSRC_Msk                (0x3UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x30000000 */
5940 #define CRS_CFGR_SYNCSRC                    CRS_CFGR_SYNCSRC_Msk                    /*!< SYNC signal source selection */
5941 #define CRS_CFGR_SYNCSRC_0                  (0x1UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x10000000 */
5942 #define CRS_CFGR_SYNCSRC_1                  (0x2UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x20000000 */
5943 #define CRS_CFGR_SYNCPOL_Pos                (31U)
5944 #define CRS_CFGR_SYNCPOL_Msk                (0x1UL << CRS_CFGR_SYNCPOL_Pos)         /*!< 0x80000000 */
5945 #define CRS_CFGR_SYNCPOL                    CRS_CFGR_SYNCPOL_Msk                    /*!< SYNC polarity selection */
5946 
5947 /*******************  Bit definition for CRS_ISR register  *********************/
5948 #define CRS_ISR_SYNCOKF_Pos                 (0U)
5949 #define CRS_ISR_SYNCOKF_Msk                 (0x1UL << CRS_ISR_SYNCOKF_Pos)          /*!< 0x00000001 */
5950 #define CRS_ISR_SYNCOKF                     CRS_ISR_SYNCOKF_Msk                     /*!< SYNC event OK flag */
5951 #define CRS_ISR_SYNCWARNF_Pos               (1U)
5952 #define CRS_ISR_SYNCWARNF_Msk               (0x1UL << CRS_ISR_SYNCWARNF_Pos)        /*!< 0x00000002 */
5953 #define CRS_ISR_SYNCWARNF                   CRS_ISR_SYNCWARNF_Msk                   /*!< SYNC warning flag */
5954 #define CRS_ISR_ERRF_Pos                    (2U)
5955 #define CRS_ISR_ERRF_Msk                    (0x1UL << CRS_ISR_ERRF_Pos)             /*!< 0x00000004 */
5956 #define CRS_ISR_ERRF                        CRS_ISR_ERRF_Msk                        /*!< Error flag */
5957 #define CRS_ISR_ESYNCF_Pos                  (3U)
5958 #define CRS_ISR_ESYNCF_Msk                  (0x1UL << CRS_ISR_ESYNCF_Pos)           /*!< 0x00000008 */
5959 #define CRS_ISR_ESYNCF                      CRS_ISR_ESYNCF_Msk                      /*!< Expected SYNC flag */
5960 #define CRS_ISR_SYNCERR_Pos                 (8U)
5961 #define CRS_ISR_SYNCERR_Msk                 (0x1UL << CRS_ISR_SYNCERR_Pos)          /*!< 0x00000100 */
5962 #define CRS_ISR_SYNCERR                     CRS_ISR_SYNCERR_Msk                     /*!< SYNC error */
5963 #define CRS_ISR_SYNCMISS_Pos                (9U)
5964 #define CRS_ISR_SYNCMISS_Msk                (0x1UL << CRS_ISR_SYNCMISS_Pos)         /*!< 0x00000200 */
5965 #define CRS_ISR_SYNCMISS                    CRS_ISR_SYNCMISS_Msk                    /*!< SYNC missed */
5966 #define CRS_ISR_TRIMOVF_Pos                 (10U)
5967 #define CRS_ISR_TRIMOVF_Msk                 (0x1UL << CRS_ISR_TRIMOVF_Pos)          /*!< 0x00000400 */
5968 #define CRS_ISR_TRIMOVF                     CRS_ISR_TRIMOVF_Msk                     /*!< Trimming overflow or underflow */
5969 #define CRS_ISR_FEDIR_Pos                   (15U)
5970 #define CRS_ISR_FEDIR_Msk                   (0x1UL << CRS_ISR_FEDIR_Pos)            /*!< 0x00008000 */
5971 #define CRS_ISR_FEDIR                       CRS_ISR_FEDIR_Msk                       /*!< Frequency error direction */
5972 #define CRS_ISR_FECAP_Pos                   (16U)
5973 #define CRS_ISR_FECAP_Msk                   (0xFFFFUL << CRS_ISR_FECAP_Pos)         /*!< 0xFFFF0000 */
5974 #define CRS_ISR_FECAP                       CRS_ISR_FECAP_Msk                       /*!< Frequency error capture */
5975 
5976 /*******************  Bit definition for CRS_ICR register  *********************/
5977 #define CRS_ICR_SYNCOKC_Pos                 (0U)
5978 #define CRS_ICR_SYNCOKC_Msk                 (0x1UL << CRS_ICR_SYNCOKC_Pos)          /*!< 0x00000001 */
5979 #define CRS_ICR_SYNCOKC                     CRS_ICR_SYNCOKC_Msk                     /*!< SYNC event OK clear flag */
5980 #define CRS_ICR_SYNCWARNC_Pos               (1U)
5981 #define CRS_ICR_SYNCWARNC_Msk               (0x1UL << CRS_ICR_SYNCWARNC_Pos)        /*!< 0x00000002 */
5982 #define CRS_ICR_SYNCWARNC                   CRS_ICR_SYNCWARNC_Msk                   /*!< SYNC warning clear flag */
5983 #define CRS_ICR_ERRC_Pos                    (2U)
5984 #define CRS_ICR_ERRC_Msk                    (0x1UL << CRS_ICR_ERRC_Pos)             /*!< 0x00000004 */
5985 #define CRS_ICR_ERRC                        CRS_ICR_ERRC_Msk                        /*!< Error clear flag */
5986 #define CRS_ICR_ESYNCC_Pos                  (3U)
5987 #define CRS_ICR_ESYNCC_Msk                  (0x1UL << CRS_ICR_ESYNCC_Pos)           /*!< 0x00000008 */
5988 #define CRS_ICR_ESYNCC                      CRS_ICR_ESYNCC_Msk                      /*!< Expected SYNC clear flag */
5989 
5990 /******************************************************************************/
5991 /*                                                                            */
5992 /*                                    RNG                                     */
5993 /*                                                                            */
5994 /******************************************************************************/
5995 /********************  Bits definition for RNG_CR register  *******************/
5996 #define RNG_CR_RNGEN_Pos                    (2U)
5997 #define RNG_CR_RNGEN_Msk                    (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
5998 #define RNG_CR_RNGEN                        RNG_CR_RNGEN_Msk
5999 #define RNG_CR_IE_Pos                       (3U)
6000 #define RNG_CR_IE_Msk                       (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
6001 #define RNG_CR_IE                           RNG_CR_IE_Msk
6002 #define RNG_CR_CED_Pos                      (5U)
6003 #define RNG_CR_CED_Msk                      (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
6004 #define RNG_CR_CED                          RNG_CR_CED_Msk
6005 #define RNG_CR_ARDIS_Pos                    (7U)
6006 #define RNG_CR_ARDIS_Msk                    (0x1UL << RNG_CR_ARDIS_Pos)
6007 #define RNG_CR_ARDIS                        RNG_CR_ARDIS_Msk
6008 #define RNG_CR_RNG_CONFIG3_Pos              (8U)
6009 #define RNG_CR_RNG_CONFIG3_Msk              (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
6010 #define RNG_CR_RNG_CONFIG3                  RNG_CR_RNG_CONFIG3_Msk
6011 #define RNG_CR_NISTC_Pos                    (12U)
6012 #define RNG_CR_NISTC_Msk                    (0x1UL << RNG_CR_NISTC_Pos)
6013 #define RNG_CR_NISTC                        RNG_CR_NISTC_Msk
6014 #define RNG_CR_RNG_CONFIG2_Pos              (13U)
6015 #define RNG_CR_RNG_CONFIG2_Msk              (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
6016 #define RNG_CR_RNG_CONFIG2                  RNG_CR_RNG_CONFIG2_Msk
6017 #define RNG_CR_CLKDIV_Pos                   (16U)
6018 #define RNG_CR_CLKDIV_Msk                   (0xFUL << RNG_CR_CLKDIV_Pos)
6019 #define RNG_CR_CLKDIV                       RNG_CR_CLKDIV_Msk
6020 #define RNG_CR_CLKDIV_0                     (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
6021 #define RNG_CR_CLKDIV_1                     (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
6022 #define RNG_CR_CLKDIV_2                     (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
6023 #define RNG_CR_CLKDIV_3                     (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
6024 #define RNG_CR_RNG_CONFIG1_Pos              (20U)
6025 #define RNG_CR_RNG_CONFIG1_Msk              (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
6026 #define RNG_CR_RNG_CONFIG1                  RNG_CR_RNG_CONFIG1_Msk
6027 #define RNG_CR_CONDRST_Pos                  (30U)
6028 #define RNG_CR_CONDRST_Msk                  (0x1UL << RNG_CR_CONDRST_Pos)
6029 #define RNG_CR_CONDRST                      RNG_CR_CONDRST_Msk
6030 #define RNG_CR_CONFIGLOCK_Pos               (31U)
6031 #define RNG_CR_CONFIGLOCK_Msk               (0x1UL << RNG_CR_CONFIGLOCK_Pos)
6032 #define RNG_CR_CONFIGLOCK                   RNG_CR_CONFIGLOCK_Msk
6033 
6034 /********************  Bits definition for RNG_SR register  *******************/
6035 #define RNG_SR_DRDY_Pos                     (0U)
6036 #define RNG_SR_DRDY_Msk                     (0x1UL << RNG_SR_DRDY_Pos)              /*!< 0x00000001 */
6037 #define RNG_SR_DRDY                         RNG_SR_DRDY_Msk
6038 #define RNG_SR_CECS_Pos                     (1U)
6039 #define RNG_SR_CECS_Msk                     (0x1UL << RNG_SR_CECS_Pos)              /*!< 0x00000002 */
6040 #define RNG_SR_CECS                         RNG_SR_CECS_Msk
6041 #define RNG_SR_SECS_Pos                     (2U)
6042 #define RNG_SR_SECS_Msk                     (0x1UL << RNG_SR_SECS_Pos)              /*!< 0x00000004 */
6043 #define RNG_SR_SECS                         RNG_SR_SECS_Msk
6044 #define RNG_SR_CEIS_Pos                     (5U)
6045 #define RNG_SR_CEIS_Msk                     (0x1UL << RNG_SR_CEIS_Pos)              /*!< 0x00000020 */
6046 #define RNG_SR_CEIS                         RNG_SR_CEIS_Msk
6047 #define RNG_SR_SEIS_Pos                     (6U)
6048 #define RNG_SR_SEIS_Msk                     (0x1UL << RNG_SR_SEIS_Pos)              /*!< 0x00000040 */
6049 #define RNG_SR_SEIS                         RNG_SR_SEIS_Msk
6050 
6051 /********************  Bits definition for RNG_NSCR register  *******************/
6052 #define RNG_NSCR_EN_OSC1_Pos                (0U)
6053 #define RNG_NSCR_EN_OSC1_Msk                (0x7UL << RNG_NSCR_EN_OSC1_Pos)         /*!< 0x00000007 */
6054 #define RNG_NSCR_EN_OSC1                    RNG_NSCR_EN_OSC1_Msk
6055 #define RNG_NSCR_EN_OSC2_Pos                (3U)
6056 #define RNG_NSCR_EN_OSC2_Msk                (0x7UL << RNG_NSCR_EN_OSC2_Pos)         /*!< 0x00000038 */
6057 #define RNG_NSCR_EN_OSC2                    RNG_NSCR_EN_OSC2_Msk
6058 #define RNG_NSCR_EN_OSC3_Pos                (6U)
6059 #define RNG_NSCR_EN_OSC3_Msk                (0x7UL << RNG_NSCR_EN_OSC3_Pos)         /*!< 0x000001C0 */
6060 #define RNG_NSCR_EN_OSC3                    RNG_NSCR_EN_OSC3_Msk
6061 #define RNG_NSCR_EN_OSC4_Pos                (9U)
6062 #define RNG_NSCR_EN_OSC4_Msk                (0x7UL << RNG_NSCR_EN_OSC4_Pos)         /*!< 0x00000E00 */
6063 #define RNG_NSCR_EN_OSC4                    RNG_NSCR_EN_OSC4_Msk
6064 #define RNG_NSCR_EN_OSC5_Pos                (12U)
6065 #define RNG_NSCR_EN_OSC5_Msk                (0x7UL << RNG_NSCR_EN_OSC5_Pos)         /*!< 0x00007000 */
6066 #define RNG_NSCR_EN_OSC5                    RNG_NSCR_EN_OSC5_Msk
6067 #define RNG_NSCR_EN_OSC6_Pos                (15U)
6068 #define RNG_NSCR_EN_OSC6_Msk                (0x7UL << RNG_NSCR_EN_OSC6_Pos)         /*!< 0x00038000 */
6069 #define RNG_NSCR_EN_OSC6                    RNG_NSCR_EN_OSC6_Msk
6070 
6071 /********************  Bits definition for RNG_HTCR register  *******************/
6072 #define RNG_HTCR_HTCFG_Pos                  (0U)
6073 #define RNG_HTCR_HTCFG_Msk                  (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
6074 #define RNG_HTCR_HTCFG                      RNG_HTCR_HTCFG_Msk
6075 /********************  RNG Nist Compliance Values  *******************/
6076 #define RNG_CR_NIST_VALUE                   (0x00F10F00U)
6077 #define RNG_HTCR_NIST_VALUE                 (0xA715U)
6078 #define RNG_NSCR_NIST_VALUE                 (0x9049U)
6079 
6080 /******************************************************************************/
6081 /*                                                                            */
6082 /*                      Digital to Analog Converter                           */
6083 /*                                                                            */
6084 /******************************************************************************/
6085 #define DAC_CHANNEL2_SUPPORT                                                        /*!< DAC feature available only on specific devices: DAC channel 2 available */
6086 
6087 /********************  Bit definition for DAC_CR register  ********************/
6088 #define DAC_CR_EN1_Pos                      (0U)
6089 #define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)               /*!< 0x00000001 */
6090 #define DAC_CR_EN1                          DAC_CR_EN1_Msk                          /*!<DAC channel1 enable */
6091 #define DAC_CR_TEN1_Pos                     (1U)
6092 #define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)              /*!< 0x00000002 */
6093 #define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                         /*!<DAC channel1 Trigger enable */
6094 #define DAC_CR_TSEL1_Pos                    (2U)
6095 #define DAC_CR_TSEL1_Msk                    (0xFUL << DAC_CR_TSEL1_Pos)             /*!< 0x0000003C */
6096 #define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                        /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
6097 #define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000004 */
6098 #define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000008 */
6099 #define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000010 */
6100 #define DAC_CR_TSEL1_3                      (0x8UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000020 */
6101 #define DAC_CR_WAVE1_Pos                    (6U)
6102 #define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)             /*!< 0x000000C0 */
6103 #define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
6104 #define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)             /*!< 0x00000040 */
6105 #define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)             /*!< 0x00000080 */
6106 #define DAC_CR_MAMP1_Pos                    (8U)
6107 #define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)             /*!< 0x00000F00 */
6108 #define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
6109 #define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000100 */
6110 #define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000200 */
6111 #define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000400 */
6112 #define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000800 */
6113 #define DAC_CR_DMAEN1_Pos                   (12U)
6114 #define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)            /*!< 0x00001000 */
6115 #define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                       /*!<DAC channel1 DMA enable */
6116 #define DAC_CR_DMAUDRIE1_Pos                (13U)
6117 #define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)         /*!< 0x00002000 */
6118 #define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk                    /*!<DAC channel 1 DMA underrun interrupt enable  >*/
6119 #define DAC_CR_CEN1_Pos                     (14U)
6120 #define DAC_CR_CEN1_Msk                     (0x1UL << DAC_CR_CEN1_Pos)              /*!< 0x00004000 */
6121 #define DAC_CR_CEN1                         DAC_CR_CEN1_Msk                         /*!<DAC channel 1 calibration enable >*/
6122 #define DAC_CR_EN2_Pos                      (16U)
6123 #define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)               /*!< 0x00010000 */
6124 #define DAC_CR_EN2                          DAC_CR_EN2_Msk                          /*!<DAC channel2 enable */
6125 #define DAC_CR_TEN2_Pos                     (17U)
6126 #define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)              /*!< 0x00020000 */
6127 #define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                         /*!<DAC channel2 Trigger enable */
6128 #define DAC_CR_TSEL2_Pos                    (18U)
6129 #define DAC_CR_TSEL2_Msk                    (0xFUL << DAC_CR_TSEL2_Pos)             /*!< 0x003C0000 */
6130 #define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                        /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
6131 #define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)             /*!< 0x00040000 */
6132 #define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)             /*!< 0x00080000 */
6133 #define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)             /*!< 0x00100000 */
6134 #define DAC_CR_TSEL2_3                      (0x8UL << DAC_CR_TSEL2_Pos)             /*!< 0x00200000 */
6135 #define DAC_CR_WAVE2_Pos                    (22U)
6136 #define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)             /*!< 0x00C00000 */
6137 #define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
6138 #define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)             /*!< 0x00400000 */
6139 #define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)             /*!< 0x00800000 */
6140 #define DAC_CR_MAMP2_Pos                    (24U)
6141 #define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)             /*!< 0x0F000000 */
6142 #define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
6143 #define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)             /*!< 0x01000000 */
6144 #define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)             /*!< 0x02000000 */
6145 #define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)             /*!< 0x04000000 */
6146 #define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)             /*!< 0x08000000 */
6147 #define DAC_CR_DMAEN2_Pos                   (28U)
6148 #define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)            /*!< 0x10000000 */
6149 #define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                       /*!<DAC channel2 DMA enabled */
6150 #define DAC_CR_DMAUDRIE2_Pos                (29U)
6151 #define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)         /*!< 0x20000000 */
6152 #define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk                    /*!<DAC channel2 DMA underrun interrupt enable  >*/
6153 #define DAC_CR_CEN2_Pos                     (30U)
6154 #define DAC_CR_CEN2_Msk                     (0x1UL << DAC_CR_CEN2_Pos)              /*!< 0x40000000 */
6155 #define DAC_CR_CEN2                         DAC_CR_CEN2_Msk                         /*!<DAC channel2 calibration enable >*/
6156 
6157 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
6158 #define DAC_SWTRIGR_SWTRIG1_Pos             (0U)
6159 #define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)      /*!< 0x00000001 */
6160 #define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk                 /*!<DAC channel1 software trigger */
6161 #define DAC_SWTRIGR_SWTRIG2_Pos             (1U)
6162 #define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)      /*!< 0x00000002 */
6163 #define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk                 /*!<DAC channel2 software trigger */
6164 #define DAC_SWTRIGR_SWTRIGB1_Pos            (16U)
6165 #define DAC_SWTRIGR_SWTRIGB1_Msk            (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)     /*!< 0x00010000 */
6166 #define DAC_SWTRIGR_SWTRIGB1                DAC_SWTRIGR_SWTRIGB1_Msk                /*!<DAC channel1 software trigger B */
6167 #define DAC_SWTRIGR_SWTRIGB2_Pos            (17U)
6168 #define DAC_SWTRIGR_SWTRIGB2_Msk            (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)     /*!< 0x00020000 */
6169 #define DAC_SWTRIGR_SWTRIGB2                DAC_SWTRIGR_SWTRIGB2_Msk                /*!<DAC channel2 software trigger B */
6170 
6171 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
6172 #define DAC_DHR12R1_DACC1DHR_Pos            (0U)
6173 #define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)   /*!< 0x00000FFF */
6174 #define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk                /*!<DAC channel1 12-bit Right aligned data */
6175 #define DAC_DHR12R1_DACC1DHRB_Pos           (16U)
6176 #define DAC_DHR12R1_DACC1DHRB_Msk           (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)  /*!< 0x0FFF0000 */
6177 #define DAC_DHR12R1_DACC1DHRB               DAC_DHR12R1_DACC1DHRB_Msk               /*!<DAC channel1 12-bit Right-aligned data B */
6178 
6179 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
6180 #define DAC_DHR12L1_DACC1DHR_Pos            (4U)
6181 #define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)   /*!< 0x0000FFF0 */
6182 #define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk                /*!<DAC channel1 12-bit Left aligned data */
6183 #define DAC_DHR12L1_DACC1DHRB_Pos           (20U)
6184 #define DAC_DHR12L1_DACC1DHRB_Msk           (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)  /*!< 0xFFF00000 */
6185 #define DAC_DHR12L1_DACC1DHRB               DAC_DHR12L1_DACC1DHRB_Msk               /*!<DAC channel1 12-bit Left aligned data B */
6186 
6187 /******************  Bit definition for DAC_DHR8R1 register  ******************/
6188 #define DAC_DHR8R1_DACC1DHR_Pos             (0U)
6189 #define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)     /*!< 0x000000FF */
6190 #define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk                 /*!<DAC channel1 8-bit Right aligned data */
6191 #define DAC_DHR8R1_DACC1DHRB_Pos            (8U)
6192 #define DAC_DHR8R1_DACC1DHRB_Msk            (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)    /*!< 0x0000FF00 */
6193 #define DAC_DHR8R1_DACC1DHRB                DAC_DHR8R1_DACC1DHRB_Msk                /*!<DAC channel1 8-bit Right aligned data B */
6194 
6195 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
6196 #define DAC_DHR12R2_DACC2DHR_Pos            (0U)
6197 #define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)   /*!< 0x00000FFF */
6198 #define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk                /*!<DAC channel2 12-bit Right aligned data */
6199 #define DAC_DHR12R2_DACC2DHRB_Pos           (16U)
6200 #define DAC_DHR12R2_DACC2DHRB_Msk           (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)  /*!< 0x0FFF0000 */
6201 #define DAC_DHR12R2_DACC2DHRB               DAC_DHR12R2_DACC2DHRB_Msk               /*!<DAC channel2 12-bit Right-aligned data B */
6202 
6203 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
6204 #define DAC_DHR12L2_DACC2DHR_Pos            (4U)
6205 #define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)   /*!< 0x0000FFF0 */
6206 #define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk                /*!<DAC channel2 12-bit Left aligned data */
6207 #define DAC_DHR12L2_DACC2DHRB_Pos           (20U)
6208 #define DAC_DHR12L2_DACC2DHRB_Msk           (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)  /*!< 0xFFF00000 */
6209 #define DAC_DHR12L2_DACC2DHRB               DAC_DHR12L2_DACC2DHRB_Msk               /*!<DAC channel2 12-bit Left aligned data B */
6210 
6211 /******************  Bit definition for DAC_DHR8R2 register  ******************/
6212 #define DAC_DHR8R2_DACC2DHR_Pos             (0U)
6213 #define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)     /*!< 0x000000FF */
6214 #define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk                 /*!<DAC channel2 8-bit Right aligned data */
6215 #define DAC_DHR8R2_DACC2DHRB_Pos            (8U)
6216 #define DAC_DHR8R2_DACC2DHRB_Msk            (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)    /*!< 0x0000FF00 */
6217 #define DAC_DHR8R2_DACC2DHRB                DAC_DHR8R2_DACC2DHRB_Msk                /*!<DAC channel2 8-bit Right aligned data B */
6218 
6219 /*****************  Bit definition for DAC_DHR12RD register  ******************/
6220 #define DAC_DHR12RD_DACC1DHR_Pos            (0U)
6221 #define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)   /*!< 0x00000FFF */
6222 #define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk                /*!<DAC channel1 12-bit Right aligned data */
6223 #define DAC_DHR12RD_DACC2DHR_Pos            (16U)
6224 #define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)   /*!< 0x0FFF0000 */
6225 #define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk                /*!<DAC channel2 12-bit Right aligned data */
6226 
6227 /*****************  Bit definition for DAC_DHR12LD register  ******************/
6228 #define DAC_DHR12LD_DACC1DHR_Pos            (4U)
6229 #define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)   /*!< 0x0000FFF0 */
6230 #define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk                /*!<DAC channel1 12-bit Left aligned data */
6231 #define DAC_DHR12LD_DACC2DHR_Pos            (20U)
6232 #define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)   /*!< 0xFFF00000 */
6233 #define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk                /*!<DAC channel2 12-bit Left aligned data */
6234 
6235 /******************  Bit definition for DAC_DHR8RD register  ******************/
6236 #define DAC_DHR8RD_DACC1DHR_Pos             (0U)
6237 #define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)     /*!< 0x000000FF */
6238 #define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk                 /*!<DAC channel1 8-bit Right aligned data */
6239 #define DAC_DHR8RD_DACC2DHR_Pos             (8U)
6240 #define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)     /*!< 0x0000FF00 */
6241 #define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk                 /*!<DAC channel2 8-bit Right aligned data */
6242 
6243 /*******************  Bit definition for DAC_DOR1 register  *******************/
6244 #define DAC_DOR1_DACC1DOR_Pos               (0U)
6245 #define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)      /*!< 0x00000FFF */
6246 #define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk                   /*!<DAC channel1 data output */
6247 #define DAC_DOR1_DACC1DORB_Pos              (16U)
6248 #define DAC_DOR1_DACC1DORB_Msk              (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)     /*!< 0x0FFF0000 */
6249 #define DAC_DOR1_DACC1DORB                  DAC_DOR1_DACC1DORB_Msk                  /*!<DAC channel1 data output B */
6250 
6251 /*******************  Bit definition for DAC_DOR2 register  *******************/
6252 #define DAC_DOR2_DACC2DOR_Pos               (0U)
6253 #define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)      /*!< 0x00000FFF */
6254 #define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk                   /*!<DAC channel2 data output */
6255 #define DAC_DOR2_DACC2DORB_Pos              (16U)
6256 #define DAC_DOR2_DACC2DORB_Msk              (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)     /*!< 0x0FFF0000 */
6257 #define DAC_DOR2_DACC2DORB                  DAC_DOR2_DACC2DORB_Msk                  /*!<DAC channel2 data output B */
6258 
6259 /********************  Bit definition for DAC_SR register  ********************/
6260 #define DAC_SR_DAC1RDY_Pos                  (11U)
6261 #define DAC_SR_DAC1RDY_Msk                  (0x1UL << DAC_SR_DAC1RDY_Pos)           /*!< 0x00000800 */
6262 #define DAC_SR_DAC1RDY                      DAC_SR_DAC1RDY_Msk                      /*!<DAC channel 1 ready status bit */
6263 #define DAC_SR_DORSTAT1_Pos                 (12U)
6264 #define DAC_SR_DORSTAT1_Msk                 (0x1UL << DAC_SR_DORSTAT1_Pos)          /*!< 0x00001000 */
6265 #define DAC_SR_DORSTAT1                     DAC_SR_DORSTAT1_Msk                     /*!<DAC channel 1 output register status bit */
6266 #define DAC_SR_DMAUDR1_Pos                  (13U)
6267 #define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)           /*!< 0x00002000 */
6268 #define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                      /*!<DAC channel1 DMA underrun flag */
6269 #define DAC_SR_CAL_FLAG1_Pos                (14U)
6270 #define DAC_SR_CAL_FLAG1_Msk                (0x1UL << DAC_SR_CAL_FLAG1_Pos)         /*!< 0x00004000 */
6271 #define DAC_SR_CAL_FLAG1                    DAC_SR_CAL_FLAG1_Msk                    /*!<DAC channel1 calibration offset status */
6272 #define DAC_SR_BWST1_Pos                    (15U)
6273 #define DAC_SR_BWST1_Msk                    (0x1UL << DAC_SR_BWST1_Pos)             /*!< 0x00008000 */
6274 #define DAC_SR_BWST1                        DAC_SR_BWST1_Msk                        /*!<DAC channel1 busy writing sample time flag */
6275 
6276 #define DAC_SR_DAC2RDY_Pos                  (27U)
6277 #define DAC_SR_DAC2RDY_Msk                  (0x1UL << DAC_SR_DAC2RDY_Pos)           /*!< 0x08000000 */
6278 #define DAC_SR_DAC2RDY                      DAC_SR_DAC2RDY_Msk                      /*!<DAC channel 2 ready status bit */
6279 #define DAC_SR_DORSTAT2_Pos                 (28U)
6280 #define DAC_SR_DORSTAT2_Msk                 (0x1UL << DAC_SR_DORSTAT2_Pos)          /*!< 0x10000000 */
6281 #define DAC_SR_DORSTAT2                     DAC_SR_DORSTAT2_Msk                     /*!<DAC channel 2 output register status bit */
6282 #define DAC_SR_DMAUDR2_Pos                  (29U)
6283 #define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)           /*!< 0x20000000 */
6284 #define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                      /*!<DAC channel2 DMA underrun flag */
6285 #define DAC_SR_CAL_FLAG2_Pos                (30U)
6286 #define DAC_SR_CAL_FLAG2_Msk                (0x1UL << DAC_SR_CAL_FLAG2_Pos)         /*!< 0x40000000 */
6287 #define DAC_SR_CAL_FLAG2                    DAC_SR_CAL_FLAG2_Msk                    /*!<DAC channel2 calibration offset status */
6288 #define DAC_SR_BWST2_Pos                    (31U)
6289 #define DAC_SR_BWST2_Msk                    (0x1UL << DAC_SR_BWST2_Pos)             /*!< 0x80000000 */
6290 #define DAC_SR_BWST2                        DAC_SR_BWST2_Msk                        /*!<DAC channel2 busy writing sample time flag */
6291 
6292 /*******************  Bit definition for DAC_CCR register  ********************/
6293 #define DAC_CCR_OTRIM1_Pos                  (0U)
6294 #define DAC_CCR_OTRIM1_Msk                  (0x1FUL << DAC_CCR_OTRIM1_Pos)          /*!< 0x0000001F */
6295 #define DAC_CCR_OTRIM1                      DAC_CCR_OTRIM1_Msk                      /*!<DAC channel1 offset trimming value */
6296 #define DAC_CCR_OTRIM2_Pos                  (16U)
6297 #define DAC_CCR_OTRIM2_Msk                  (0x1FUL << DAC_CCR_OTRIM2_Pos)          /*!< 0x001F0000 */
6298 #define DAC_CCR_OTRIM2                      DAC_CCR_OTRIM2_Msk                      /*!<DAC channel2 offset trimming value */
6299 
6300 /*******************  Bit definition for DAC_MCR register  *******************/
6301 #define DAC_MCR_MODE1_Pos                   (0U)
6302 #define DAC_MCR_MODE1_Msk                   (0x7UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000007 */
6303 #define DAC_MCR_MODE1                       DAC_MCR_MODE1_Msk                       /*!<MODE1[2:0] (DAC channel1 mode) */
6304 #define DAC_MCR_MODE1_0                     (0x1UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000001 */
6305 #define DAC_MCR_MODE1_1                     (0x2UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000002 */
6306 #define DAC_MCR_MODE1_2                     (0x4UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000004 */
6307 #define DAC_MCR_DMADOUBLE1_Pos              (8U)
6308 #define DAC_MCR_DMADOUBLE1_Msk              (0x1UL << DAC_MCR_DMADOUBLE1_Pos)       /*!< 0x00000100 */
6309 #define DAC_MCR_DMADOUBLE1                  DAC_MCR_DMADOUBLE1_Msk                  /*!<DAC Channel 1 DMA double data mode */
6310 #define DAC_MCR_SINFORMAT1_Pos              (9U)
6311 #define DAC_MCR_SINFORMAT1_Msk              (0x1UL << DAC_MCR_SINFORMAT1_Pos)       /*!< 0x00000200 */
6312 #define DAC_MCR_SINFORMAT1                  DAC_MCR_SINFORMAT1_Msk                  /*!<DAC Channel 1 enable signed format */
6313 #define DAC_MCR_HFSEL_Pos                   (14U)
6314 #define DAC_MCR_HFSEL_Msk                   (0x3UL << DAC_MCR_HFSEL_Pos)            /*!< 0x0000C000 */
6315 #define DAC_MCR_HFSEL                       DAC_MCR_HFSEL_Msk                       /*!<HFSEL[1:0] (High Frequency interface mode selection) */
6316 #define DAC_MCR_HFSEL_0                     (0x1UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00004000 */
6317 #define DAC_MCR_HFSEL_1                     (0x2UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00008000 */
6318 #define DAC_MCR_MODE2_Pos                   (16U)
6319 #define DAC_MCR_MODE2_Msk                   (0x7UL << DAC_MCR_MODE2_Pos)            /*!< 0x00070000 */
6320 #define DAC_MCR_MODE2                       DAC_MCR_MODE2_Msk                       /*!<MODE2[2:0] (DAC channel2 mode) */
6321 #define DAC_MCR_MODE2_0                     (0x1UL << DAC_MCR_MODE2_Pos)            /*!< 0x00010000 */
6322 #define DAC_MCR_MODE2_1                     (0x2UL << DAC_MCR_MODE2_Pos)            /*!< 0x00020000 */
6323 #define DAC_MCR_MODE2_2                     (0x4UL << DAC_MCR_MODE2_Pos)            /*!< 0x00040000 */
6324 #define DAC_MCR_DMADOUBLE2_Pos              (24U)
6325 #define DAC_MCR_DMADOUBLE2_Msk              (0x1UL << DAC_MCR_DMADOUBLE2_Pos)       /*!< 0x01000000 */
6326 #define DAC_MCR_DMADOUBLE2                  DAC_MCR_DMADOUBLE2_Msk                  /*!<DAC Channel 2 DMA double data mode */
6327 #define DAC_MCR_SINFORMAT2_Pos              (25U)
6328 #define DAC_MCR_SINFORMAT2_Msk              (0x1UL << DAC_MCR_SINFORMAT2_Pos)       /*!< 0x02000000 */
6329 #define DAC_MCR_SINFORMAT2                  DAC_MCR_SINFORMAT2_Msk                  /*!<DAC Channel 2 enable signed format */
6330 
6331 /******************  Bit definition for DAC_SHSR1 register  ******************/
6332 #define DAC_SHSR1_TSAMPLE1_Pos              (0U)
6333 #define DAC_SHSR1_TSAMPLE1_Msk              (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)     /*!< 0x000003FF */
6334 #define DAC_SHSR1_TSAMPLE1                  DAC_SHSR1_TSAMPLE1_Msk                  /*!<DAC channel1 sample time */
6335 
6336 /******************  Bit definition for DAC_SHSR2 register  ******************/
6337 #define DAC_SHSR2_TSAMPLE2_Pos              (0U)
6338 #define DAC_SHSR2_TSAMPLE2_Msk              (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)     /*!< 0x000003FF */
6339 #define DAC_SHSR2_TSAMPLE2                  DAC_SHSR2_TSAMPLE2_Msk                  /*!<DAC channel2 sample time */
6340 
6341 /******************  Bit definition for DAC_SHHR register  ******************/
6342 #define DAC_SHHR_THOLD1_Pos                 (0U)
6343 #define DAC_SHHR_THOLD1_Msk                 (0x3FFUL << DAC_SHHR_THOLD1_Pos)        /*!< 0x000003FF */
6344 #define DAC_SHHR_THOLD1                     DAC_SHHR_THOLD1_Msk                     /*!<DAC channel1 hold time */
6345 #define DAC_SHHR_THOLD2_Pos                 (16U)
6346 #define DAC_SHHR_THOLD2_Msk                 (0x3FFUL << DAC_SHHR_THOLD2_Pos)        /*!< 0x03FF0000 */
6347 #define DAC_SHHR_THOLD2                     DAC_SHHR_THOLD2_Msk                     /*!<DAC channel2 hold time */
6348 
6349 /******************  Bit definition for DAC_SHRR register  ******************/
6350 #define DAC_SHRR_TREFRESH1_Pos              (0U)
6351 #define DAC_SHRR_TREFRESH1_Msk              (0xFFUL << DAC_SHRR_TREFRESH1_Pos)      /*!< 0x000000FF */
6352 #define DAC_SHRR_TREFRESH1                  DAC_SHRR_TREFRESH1_Msk                  /*!<DAC channel1 refresh time */
6353 #define DAC_SHRR_TREFRESH2_Pos              (16U)
6354 #define DAC_SHRR_TREFRESH2_Msk              (0xFFUL << DAC_SHRR_TREFRESH2_Pos)      /*!< 0x00FF0000 */
6355 #define DAC_SHRR_TREFRESH2                  DAC_SHRR_TREFRESH2_Msk                  /*!<DAC channel2 refresh time */
6356 
6357 /******************  Bit definition for DAC_AUTOCR register  ******************/
6358 #define DAC_AUTOCR_AUTOMODE_Pos             (22U)
6359 #define DAC_AUTOCR_AUTOMODE_Msk             (0x1UL << DAC_AUTOCR_AUTOMODE_Pos)      /*!< 0x00400000 */
6360 #define DAC_AUTOCR_AUTOMODE                 DAC_AUTOCR_AUTOMODE_Msk                 /*!< AUTOCR Enable */
6361 
6362 /******************************************************************************/
6363 /*                                                                            */
6364 /*                       Advanced Encryption Standard (AES)                   */
6365 /*                                                                            */
6366 /******************************************************************************/
6367 /*******************  Bit definition for AES_CR register  *********************/
6368 #define AES_CR_EN_Pos                       (0U)
6369 #define AES_CR_EN_Msk                       (0x1UL << AES_CR_EN_Pos)                /*!< 0x00000001 */
6370 #define AES_CR_EN                           AES_CR_EN_Msk                           /*!< AES Enable */
6371 #define AES_CR_DATATYPE_Pos                 (1U)
6372 #define AES_CR_DATATYPE_Msk                 (0x3UL << AES_CR_DATATYPE_Pos)          /*!< 0x00000006 */
6373 #define AES_CR_DATATYPE                     AES_CR_DATATYPE_Msk                     /*!< Data type selection */
6374 #define AES_CR_DATATYPE_0                   (0x1UL << AES_CR_DATATYPE_Pos)          /*!< 0x00000002 */
6375 #define AES_CR_DATATYPE_1                   (0x2UL << AES_CR_DATATYPE_Pos)          /*!< 0x00000004 */
6376 #define AES_CR_MODE_Pos                     (3U)
6377 #define AES_CR_MODE_Msk                     (0x3UL << AES_CR_MODE_Pos)              /*!< 0x00000018 */
6378 #define AES_CR_MODE                         AES_CR_MODE_Msk                         /*!< AES Mode Of Operation */
6379 #define AES_CR_MODE_0                       (0x1UL << AES_CR_MODE_Pos)              /*!< 0x00000008 */
6380 #define AES_CR_MODE_1                       (0x2UL << AES_CR_MODE_Pos)              /*!< 0x00000010 */
6381 #define AES_CR_CHMOD_Pos                    (5U)
6382 #define AES_CR_CHMOD_Msk                    (0x803UL << AES_CR_CHMOD_Pos)           /*!< 0x00010060 */
6383 #define AES_CR_CHMOD                        AES_CR_CHMOD_Msk                        /*!< AES Chaining Mode */
6384 #define AES_CR_CHMOD_0                      (0x001UL << AES_CR_CHMOD_Pos)           /*!< 0x00000020 */
6385 #define AES_CR_CHMOD_1                      (0x002UL << AES_CR_CHMOD_Pos)           /*!< 0x00000040 */
6386 #define AES_CR_CHMOD_2                      (0x800UL << AES_CR_CHMOD_Pos)           /*!< 0x00010000 */
6387 #define AES_CR_DMAINEN_Pos                  (11U)
6388 #define AES_CR_DMAINEN_Msk                  (0x1UL << AES_CR_DMAINEN_Pos)           /*!< 0x00000800 */
6389 #define AES_CR_DMAINEN                      AES_CR_DMAINEN_Msk                      /*!< Enable data input phase DMA management  */
6390 #define AES_CR_DMAOUTEN_Pos                 (12U)
6391 #define AES_CR_DMAOUTEN_Msk                 (0x1UL << AES_CR_DMAOUTEN_Pos)          /*!< 0x00001000 */
6392 #define AES_CR_DMAOUTEN                     AES_CR_DMAOUTEN_Msk                     /*!< Enable data output phase DMA management */
6393 #define AES_CR_GCMPH_Pos                    (13U)
6394 #define AES_CR_GCMPH_Msk                    (0x3UL << AES_CR_GCMPH_Pos)             /*!< 0x00006000 */
6395 #define AES_CR_GCMPH                        AES_CR_GCMPH_Msk                        /*!< GCM Phase */
6396 #define AES_CR_GCMPH_0                      (0x1UL << AES_CR_GCMPH_Pos)             /*!< 0x00002000 */
6397 #define AES_CR_GCMPH_1                      (0x2UL << AES_CR_GCMPH_Pos)             /*!< 0x00004000 */
6398 #define AES_CR_KEYSIZE_Pos                  (18U)
6399 #define AES_CR_KEYSIZE_Msk                  (0x1UL << AES_CR_KEYSIZE_Pos)           /*!< 0x00040000 */
6400 #define AES_CR_KEYSIZE                      AES_CR_KEYSIZE_Msk                      /*!< Key size selection */
6401 #define AES_CR_KEYPROT_Pos                 (19U)
6402 #define AES_CR_KEYPROT_Msk                 (0x1UL << AES_CR_KEYPROT_Pos)          /*!< 0x00040000 */
6403 #define AES_CR_KEYPROT                     AES_CR_KEYPROT_Msk                     /*!<  Key protection */
6404 #define AES_CR_NPBLB_Pos                    (20U)
6405 #define AES_CR_NPBLB_Msk                    (0xFUL << AES_CR_NPBLB_Pos)             /*!< 0x00F00000 */
6406 #define AES_CR_NPBLB                        AES_CR_NPBLB_Msk                        /*!< Number of padding bytes in payload last block */
6407 #define AES_CR_NPBLB_0                      (0x1UL << AES_CR_NPBLB_Pos)             /*!< 0x00100000 */
6408 #define AES_CR_NPBLB_1                      (0x2UL << AES_CR_NPBLB_Pos)             /*!< 0x00200000 */
6409 #define AES_CR_NPBLB_2                      (0x4UL << AES_CR_NPBLB_Pos)             /*!< 0x00400000 */
6410 #define AES_CR_NPBLB_3                      (0x8UL << AES_CR_NPBLB_Pos)             /*!< 0x00800000 */
6411 #define AES_CR_KMOD_Pos                     (24U)
6412 #define AES_CR_KMOD_Msk                     (0x3UL << AES_CR_KMOD_Pos)              /*!< 0x00000006 */
6413 #define AES_CR_KMOD                         AES_CR_KMOD_Msk                         /*!< Key mode selection */
6414 #define AES_CR_KMOD_0                       (0x1UL << AES_CR_KMOD_Pos)             /*!< 0x01000000 */
6415 #define AES_CR_KMOD_1                       (0x2UL << AES_CR_KMOD_Pos)              /*!< 0x02000000 */
6416 #define AES_CR_KSHAREID_Pos                (26U)
6417 #define AES_CR_KSHAREID_Msk                (0x3UL << AES_CR_KSHAREID_Pos)         /*!< 0x00000006 */
6418 #define AES_CR_KSHAREID                    AES_CR_KSHAREID_Msk                    /*!< Key Shared ID */
6419 #define AES_CR_KEYSEL_Pos                  (28U)
6420 #define AES_CR_KEYSEL_Msk                  (0x7UL << AES_CR_KEYSEL_Pos)           /*!< 0x00000006 */
6421 #define AES_CR_KEYSEL                      AES_CR_KEYSEL_Msk                      /*!< Key Selection */
6422 #define AES_CR_KEYSEL_0                    (0x1UL << AES_CR_KEYSEL_Pos)           /*!< 0x02000000 */
6423 #define AES_CR_KEYSEL_1                    (0x2UL << AES_CR_KEYSEL_Pos)           /*!< 0x02000000 */
6424 #define AES_CR_KEYSEL_2                    (0x4UL << AES_CR_KEYSEL_Pos)           /*!< 0x02000000 */
6425 #define AES_CR_IPRST_Pos                    (31U)
6426 #define AES_CR_IPRST_Msk                    (0x1UL << AES_CR_IPRST_Pos)             /*!< 0x80000001 */
6427 #define AES_CR_IPRST                        AES_CR_IPRST_Msk                        /*!< AES IP software reset */
6428 
6429 /*******************  Bit definition for AES_SR register  *********************/
6430 #define AES_SR_CCF_Pos                      (0U)
6431 #define AES_SR_CCF_Msk                      (0x1UL << AES_SR_CCF_Pos)               /*!< 0x00000001 */
6432 #define AES_SR_CCF                          AES_SR_CCF_Msk                          /*!< Computation Complete Flag */
6433 #define AES_SR_RDERR_Pos                    (1U)
6434 #define AES_SR_RDERR_Msk                    (0x1UL << AES_SR_RDERR_Pos)             /*!< 0x00000002 */
6435 #define AES_SR_RDERR                        AES_SR_RDERR_Msk                        /*!< Read Error Flag */
6436 #define AES_SR_WRERR_Pos                    (2U)
6437 #define AES_SR_WRERR_Msk                    (0x1UL << AES_SR_WRERR_Pos)             /*!< 0x00000004 */
6438 #define AES_SR_WRERR                        AES_SR_WRERR_Msk                        /*!< Write Error Flag */
6439 #define AES_SR_BUSY_Pos                     (3U)
6440 #define AES_SR_BUSY_Msk                     (0x1UL << AES_SR_BUSY_Pos)              /*!< 0x00000008 */
6441 #define AES_SR_BUSY                         AES_SR_BUSY_Msk                         /*!< Busy Flag */
6442 #define AES_SR_KEYVALID_Pos                 (7U)
6443 #define AES_SR_KEYVALID_Msk                 (0x1UL << AES_SR_KEYVALID_Pos)          /*!< 0x00000008 */
6444 #define AES_SR_KEYVALID                     AES_SR_KEYVALID_Msk                     /*!< KEYVALID Flag */
6445 
6446 /*******************  Bit definition for AES_DINR register  *******************/
6447 #define AES_DINR_Pos                        (0U)
6448 #define AES_DINR_Msk                        (0xFFFFFFFFUL << AES_DINR_Pos)          /*!< 0xFFFFFFFF */
6449 #define AES_DINR                            AES_DINR_Msk                            /*!< AES Data Input Register */
6450 
6451 /*******************  Bit definition for AES_DOUTR register  ******************/
6452 #define AES_DOUTR_Pos                       (0U)
6453 #define AES_DOUTR_Msk                       (0xFFFFFFFFUL << AES_DOUTR_Pos)         /*!< 0xFFFFFFFF */
6454 #define AES_DOUTR                           AES_DOUTR_Msk                           /*!< AES Data Output Register */
6455 
6456 /*******************  Bit definition for AES_KEYR0 register  ******************/
6457 #define AES_KEYR0_Pos                       (0U)
6458 #define AES_KEYR0_Msk                       (0xFFFFFFFFUL << AES_KEYR0_Pos)         /*!< 0xFFFFFFFF */
6459 #define AES_KEYR0                           AES_KEYR0_Msk                           /*!< AES Key Register 0 */
6460 
6461 /*******************  Bit definition for AES_KEYR1 register  ******************/
6462 #define AES_KEYR1_Pos                       (0U)
6463 #define AES_KEYR1_Msk                       (0xFFFFFFFFUL << AES_KEYR1_Pos)         /*!< 0xFFFFFFFF */
6464 #define AES_KEYR1                           AES_KEYR1_Msk                           /*!< AES Key Register 1 */
6465 
6466 /*******************  Bit definition for AES_KEYR2 register  ******************/
6467 #define AES_KEYR2_Pos                       (0U)
6468 #define AES_KEYR2_Msk                       (0xFFFFFFFFUL << AES_KEYR2_Pos)         /*!< 0xFFFFFFFF */
6469 #define AES_KEYR2                           AES_KEYR2_Msk                           /*!< AES Key Register 2 */
6470 
6471 /*******************  Bit definition for AES_KEYR3 register  ******************/
6472 #define AES_KEYR3_Pos                       (0U)
6473 #define AES_KEYR3_Msk                       (0xFFFFFFFFUL << AES_KEYR3_Pos)         /*!< 0xFFFFFFFF */
6474 #define AES_KEYR3                           AES_KEYR3_Msk                           /*!< AES Key Register 3 */
6475 
6476 /*******************  Bit definition for AES_KEYR4 register  ******************/
6477 #define AES_KEYR4_Pos                       (0U)
6478 #define AES_KEYR4_Msk                       (0xFFFFFFFFUL << AES_KEYR4_Pos)         /*!< 0xFFFFFFFF */
6479 #define AES_KEYR4                           AES_KEYR4_Msk                           /*!< AES Key Register 4 */
6480 
6481 /*******************  Bit definition for AES_KEYR5 register  ******************/
6482 #define AES_KEYR5_Pos                       (0U)
6483 #define AES_KEYR5_Msk                       (0xFFFFFFFFUL << AES_KEYR5_Pos)         /*!< 0xFFFFFFFF */
6484 #define AES_KEYR5                           AES_KEYR5_Msk                           /*!< AES Key Register 5 */
6485 
6486 /*******************  Bit definition for AES_KEYR6 register  ******************/
6487 #define AES_KEYR6_Pos                       (0U)
6488 #define AES_KEYR6_Msk                       (0xFFFFFFFFUL << AES_KEYR6_Pos)         /*!< 0xFFFFFFFF */
6489 #define AES_KEYR6                           AES_KEYR6_Msk                           /*!< AES Key Register 6 */
6490 
6491 /*******************  Bit definition for AES_KEYR7 register  ******************/
6492 #define AES_KEYR7_Pos                       (0U)
6493 #define AES_KEYR7_Msk                       (0xFFFFFFFFUL << AES_KEYR7_Pos)         /*!< 0xFFFFFFFF */
6494 #define AES_KEYR7                           AES_KEYR7_Msk                           /*!< AES Key Register 7 */
6495 
6496 /*******************  Bit definition for AES_IVR0 register   ******************/
6497 #define AES_IVR0_Pos                        (0U)
6498 #define AES_IVR0_Msk                        (0xFFFFFFFFUL << AES_IVR0_Pos)          /*!< 0xFFFFFFFF */
6499 #define AES_IVR0                            AES_IVR0_Msk                            /*!< AES Initialization Vector Register 0 */
6500 
6501 /*******************  Bit definition for AES_IVR1 register   ******************/
6502 #define AES_IVR1_Pos                        (0U)
6503 #define AES_IVR1_Msk                        (0xFFFFFFFFUL << AES_IVR1_Pos)          /*!< 0xFFFFFFFF */
6504 #define AES_IVR1                            AES_IVR1_Msk                            /*!< AES Initialization Vector Register 1 */
6505 
6506 /*******************  Bit definition for AES_IVR2 register   ******************/
6507 #define AES_IVR2_Pos                        (0U)
6508 #define AES_IVR2_Msk                        (0xFFFFFFFFUL << AES_IVR2_Pos)          /*!< 0xFFFFFFFF */
6509 #define AES_IVR2                            AES_IVR2_Msk                            /*!< AES Initialization Vector Register 2 */
6510 
6511 /*******************  Bit definition for AES_IVR3 register   ******************/
6512 #define AES_IVR3_Pos                        (0U)
6513 #define AES_IVR3_Msk                        (0xFFFFFFFFUL << AES_IVR3_Pos)          /*!< 0xFFFFFFFF */
6514 #define AES_IVR3                            AES_IVR3_Msk                            /*!< AES Initialization Vector Register 3 */
6515 
6516 /*******************  Bit definition for AES_SUSP0R register  ******************/
6517 #define AES_SUSP0R_Pos                      (0U)
6518 #define AES_SUSP0R_Msk                      (0xFFFFFFFFUL << AES_SUSP0R_Pos)        /*!< 0xFFFFFFFF */
6519 #define AES_SUSP0R                          AES_SUSP0R_Msk                          /*!< AES Suspend registers 0 */
6520 
6521 /*******************  Bit definition for AES_SUSP1R register  ******************/
6522 #define AES_SUSP1R_Pos                      (0U)
6523 #define AES_SUSP1R_Msk                      (0xFFFFFFFFUL << AES_SUSP1R_Pos)        /*!< 0xFFFFFFFF */
6524 #define AES_SUSP1R                          AES_SUSP1R_Msk                          /*!< AES Suspend registers 1 */
6525 
6526 /*******************  Bit definition for AES_SUSP2R register  ******************/
6527 #define AES_SUSP2R_Pos                      (0U)
6528 #define AES_SUSP2R_Msk                      (0xFFFFFFFFUL << AES_SUSP2R_Pos)        /*!< 0xFFFFFFFF */
6529 #define AES_SUSP2R                          AES_SUSP2R_Msk                          /*!< AES Suspend registers 2 */
6530 
6531 /*******************  Bit definition for AES_SUSP3R register  ******************/
6532 #define AES_SUSP3R_Pos                      (0U)
6533 #define AES_SUSP3R_Msk                      (0xFFFFFFFFUL << AES_SUSP3R_Pos)        /*!< 0xFFFFFFFF */
6534 #define AES_SUSP3R                          AES_SUSP3R_Msk                          /*!< AES Suspend registers 3 */
6535 
6536 /*******************  Bit definition for AES_SUSP4R register  ******************/
6537 #define AES_SUSP4R_Pos                      (0U)
6538 #define AES_SUSP4R_Msk                      (0xFFFFFFFFUL << AES_SUSP4R_Pos)        /*!< 0xFFFFFFFF */
6539 #define AES_SUSP4R                          AES_SUSP4R_Msk                          /*!< AES Suspend registers 4 */
6540 
6541 /*******************  Bit definition for AES_SUSP5R register  ******************/
6542 #define AES_SUSP5R_Pos                      (0U)
6543 #define AES_SUSP5R_Msk                      (0xFFFFFFFFUL << AES_SUSP5R_Pos)        /*!< 0xFFFFFFFF */
6544 #define AES_SUSP5R                          AES_SUSP5R_Msk                          /*!< AES Suspend registers 5 */
6545 
6546 /*******************  Bit definition for AES_SUSP6R register  ******************/
6547 #define AES_SUSP6R_Pos                      (0U)
6548 #define AES_SUSP6R_Msk                      (0xFFFFFFFFUL << AES_SUSP6R_Pos)        /*!< 0xFFFFFFFF */
6549 #define AES_SUSP6R                          AES_SUSP6R_Msk                          /*!< AES Suspend registers 6 */
6550 
6551 /*******************  Bit definition for AES_SUSP7R register  ******************/
6552 #define AES_SUSP7R_Pos                      (0U)
6553 #define AES_SUSP7R_Msk                      (0xFFFFFFFFUL << AES_SUSP7R_Pos)        /*!< 0xFFFFFFFF */
6554 #define AES_SUSP7R                          AES_SUSP7R_Msk                          /*!< AES Suspend registers 7 */
6555 
6556 /*******************  Bit definition for AES_IER register     ******************/
6557 #define AES_IER_CCFIE_Pos                   (0U)
6558 #define AES_IER_CCFIE_Msk                   (0x1UL << AES_IER_CCFIE_Pos)            /*!< 0x00000001 */
6559 #define AES_IER_CCFIE                       AES_IER_CCFIE_Msk                       /*!< Computation complete flag interrupt enable */
6560 #define AES_IER_RWEIE_Pos                   (1U)
6561 #define AES_IER_RWEIE_Msk                   (0x1UL << AES_IER_RWEIE_Pos)            /*!< 0x00000002 */
6562 #define AES_IER_RWEIE                       AES_IER_RWEIE_Msk                       /*!< Read or write error Interrupt Enable */
6563 #define AES_IER_KEIE_Pos                    (2U)
6564 #define AES_IER_KEIE_Msk                    (0x1UL << AES_IER_KEIE_Pos)             /*!< 0x00000004 */
6565 #define AES_IER_KEIE                        AES_IER_KEIE_Msk                        /*!< Key error interrupt enable */
6566 #define AES_IER_RNGEIE_Pos                  (3U)
6567 #define AES_IER_RNGEIE_Msk                  (0x1UL << AES_IER_RNGEIE_Pos)           /*!< 0x00000008 */
6568 #define AES_IER_RNGEIE                      AES_IER_RNGEIE_Msk                      /*!< Rng error interrupt enable */
6569 
6570 /*******************  Bit definition for AES_ISR register     ******************/
6571 #define AES_ISR_CCF_Pos                     (0U)
6572 #define AES_ISR_CCF_Msk                     (0x1UL << AES_ISR_CCF_Pos)              /*!< 0x00000001 */
6573 #define AES_ISR_CCF                         AES_ISR_CCF_Msk                         /*!< Computation complete flag */
6574 #define AES_ISR_RWEIF_Pos                   (1U)
6575 #define AES_ISR_RWEIF_Msk                   (0x1UL << AES_ISR_RWEIF_Pos)            /*!< 0x00000002 */
6576 #define AES_ISR_RWEIF                       AES_ISR_RWEIF_Msk                       /*!< Read or write error Interrupt flag */
6577 #define AES_ISR_KEIF_Pos                    (2U)
6578 #define AES_ISR_KEIF_Msk                    (0x1UL << AES_ISR_KEIF_Pos)             /*!< 0x00000004 */
6579 #define AES_ISR_KEIF                        AES_ISR_KEIF_Msk                        /*!< Key error interrupt flag */
6580 #define AES_ISR_RNGEIF_Pos                  (3U)
6581 #define AES_ISR_RNGEIF_Msk                  (0x1UL << AES_ISR_RNGEIF_Pos)           /*!< 0x00000008 */
6582 #define AES_ISR_RNGEIF                      AES_ISR_RNGEIF_Msk                      /*!< Rng error interrupt flag */
6583 
6584 /*******************  Bit definition for AES_ICR register     ******************/
6585 #define AES_ICR_CCF_Pos                     (0U)
6586 #define AES_ICR_CCF_Msk                     (0x1UL << AES_ICR_CCF_Pos)              /*!< 0x00000001 */
6587 #define AES_ICR_CCF                         AES_ICR_CCF_Msk                         /*!< Computation complete flag clear */
6588 #define AES_ICR_RWEIF_Pos                   (1U)
6589 #define AES_ICR_RWEIF_Msk                   (0x1UL << AES_ICR_RWEIF_Pos)            /*!< 0x00000002 */
6590 #define AES_ICR_RWEIF                       AES_ICR_RWEIF_Msk                       /*!< Read or write error Interrupt flag clear */
6591 #define AES_ICR_KEIF_Pos                    (2U)
6592 #define AES_ICR_KEIF_Msk                    (0x1UL << AES_ICR_KEIF_Pos)             /*!< 0x00000004 */
6593 #define AES_ICR_KEIF                        AES_ICR_KEIF_Msk                        /*!< Key error interrupt flag clear */
6594 #define AES_ICR_RNGEIF_Pos                  (3U)
6595 #define AES_ICR_RNGEIF_Msk                  (0x1UL << AES_ICR_RNGEIF_Pos)           /*!< 0x00000008 */
6596 #define AES_ICR_RNGEIF                       AES_ICR_RNGEIF_Msk                     /*!< Rng error interrupt flag clear */
6597 
6598 /******************************************************************************/
6599 /*                                                                            */
6600 /*                                    HASH                                    */
6601 /*                                                                            */
6602 /******************************************************************************/
6603 /******************  Bits definition for HASH_CR register  ********************/
6604 #define HASH_CR_INIT_Pos                    (2U)
6605 #define HASH_CR_INIT_Msk                    (0x1UL << HASH_CR_INIT_Pos)             /*!< 0x00000004 */
6606 #define HASH_CR_INIT                        HASH_CR_INIT_Msk
6607 #define HASH_CR_DMAE_Pos                    (3U)
6608 #define HASH_CR_DMAE_Msk                    (0x1UL << HASH_CR_DMAE_Pos)             /*!< 0x00000008 */
6609 #define HASH_CR_DMAE                        HASH_CR_DMAE_Msk
6610 #define HASH_CR_DATATYPE_Pos                (4U)
6611 #define HASH_CR_DATATYPE_Msk                (0x3UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000030 */
6612 #define HASH_CR_DATATYPE                    HASH_CR_DATATYPE_Msk
6613 #define HASH_CR_DATATYPE_0                  (0x1UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000010 */
6614 #define HASH_CR_DATATYPE_1                  (0x2UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000020 */
6615 #define HASH_CR_MODE_Pos                    (6U)
6616 #define HASH_CR_MODE_Msk                    (0x1UL << HASH_CR_MODE_Pos)             /*!< 0x00000040 */
6617 #define HASH_CR_MODE                        HASH_CR_MODE_Msk
6618 #define HASH_CR_NBW_Pos                     (8U)
6619 #define HASH_CR_NBW_Msk                     (0xFUL << HASH_CR_NBW_Pos)              /*!< 0x00000F00 */
6620 #define HASH_CR_NBW                         HASH_CR_NBW_Msk
6621 #define HASH_CR_NBW_0                       (0x1UL << HASH_CR_NBW_Pos)              /*!< 0x00000100 */
6622 #define HASH_CR_NBW_1                       (0x2UL << HASH_CR_NBW_Pos)              /*!< 0x00000200 */
6623 #define HASH_CR_NBW_2                       (0x4UL << HASH_CR_NBW_Pos)              /*!< 0x00000400 */
6624 #define HASH_CR_NBW_3                       (0x8UL << HASH_CR_NBW_Pos)              /*!< 0x00000800 */
6625 #define HASH_CR_DINNE_Pos                   (12U)
6626 #define HASH_CR_DINNE_Msk                   (0x1UL << HASH_CR_DINNE_Pos)            /*!< 0x00001000 */
6627 #define HASH_CR_DINNE                       HASH_CR_DINNE_Msk
6628 #define HASH_CR_MDMAT_Pos                   (13U)
6629 #define HASH_CR_MDMAT_Msk                   (0x1UL << HASH_CR_MDMAT_Pos)            /*!< 0x00002000 */
6630 #define HASH_CR_MDMAT                       HASH_CR_MDMAT_Msk
6631 #define HASH_CR_LKEY_Pos                    (16U)
6632 #define HASH_CR_LKEY_Msk                    (0x1UL << HASH_CR_LKEY_Pos)             /*!< 0x00010000 */
6633 #define HASH_CR_LKEY                        HASH_CR_LKEY_Msk
6634 #define HASH_CR_ALGO_Pos                    (17U)
6635 #define HASH_CR_ALGO_Msk                    (0x3UL << HASH_CR_ALGO_Pos)             /*!< 0x00040080 */
6636 #define HASH_CR_ALGO                        HASH_CR_ALGO_Msk
6637 #define HASH_CR_ALGO_0                      (0x1UL << HASH_CR_ALGO_Pos)             /*!< 0x00000080 */
6638 #define HASH_CR_ALGO_1                      (0x2UL << HASH_CR_ALGO_Pos)             /*!< 0x00040000 */
6639 
6640 /******************  Bits definition for HASH_STR register  *******************/
6641 #define HASH_STR_NBLW_Pos                   (0U)
6642 #define HASH_STR_NBLW_Msk                   (0x1FUL << HASH_STR_NBLW_Pos)           /*!< 0x0000001F */
6643 #define HASH_STR_NBLW                       HASH_STR_NBLW_Msk
6644 #define HASH_STR_NBLW_0                     (0x01UL << HASH_STR_NBLW_Pos)           /*!< 0x00000001 */
6645 #define HASH_STR_NBLW_1                     (0x02UL << HASH_STR_NBLW_Pos)           /*!< 0x00000002 */
6646 #define HASH_STR_NBLW_2                     (0x04UL << HASH_STR_NBLW_Pos)           /*!< 0x00000004 */
6647 #define HASH_STR_NBLW_3                     (0x08UL << HASH_STR_NBLW_Pos)           /*!< 0x00000008 */
6648 #define HASH_STR_NBLW_4                     (0x10UL << HASH_STR_NBLW_Pos)           /*!< 0x00000010 */
6649 #define HASH_STR_DCAL_Pos                   (8U)
6650 #define HASH_STR_DCAL_Msk                   (0x1UL << HASH_STR_DCAL_Pos)            /*!< 0x00000100 */
6651 #define HASH_STR_DCAL                       HASH_STR_DCAL_Msk
6652 
6653 /******************  Bits definition for HASH_IMR register  *******************/
6654 #define HASH_IMR_DINIE_Pos                  (0U)
6655 #define HASH_IMR_DINIE_Msk                  (0x1UL << HASH_IMR_DINIE_Pos)           /*!< 0x00000001 */
6656 #define HASH_IMR_DINIE                      HASH_IMR_DINIE_Msk
6657 #define HASH_IMR_DCIE_Pos                   (1U)
6658 #define HASH_IMR_DCIE_Msk                   (0x1UL << HASH_IMR_DCIE_Pos)            /*!< 0x00000002 */
6659 #define HASH_IMR_DCIE                       HASH_IMR_DCIE_Msk
6660 
6661 /******************  Bits definition for HASH_SR register  ********************/
6662 #define HASH_SR_DINIS_Pos                   (0U)
6663 #define HASH_SR_DINIS_Msk                   (0x1UL << HASH_SR_DINIS_Pos)            /*!< 0x00000001 */
6664 #define HASH_SR_DINIS                       HASH_SR_DINIS_Msk
6665 #define HASH_SR_DCIS_Pos                    (1U)
6666 #define HASH_SR_DCIS_Msk                    (0x1UL << HASH_SR_DCIS_Pos)             /*!< 0x00000002 */
6667 #define HASH_SR_DCIS                        HASH_SR_DCIS_Msk
6668 #define HASH_SR_DMAS_Pos                    (2U)
6669 #define HASH_SR_DMAS_Msk                    (0x1UL << HASH_SR_DMAS_Pos)             /*!< 0x00000004 */
6670 #define HASH_SR_DMAS                        HASH_SR_DMAS_Msk
6671 #define HASH_SR_BUSY_Pos                    (3U)
6672 #define HASH_SR_BUSY_Msk                    (0x1UL << HASH_SR_BUSY_Pos)             /*!< 0x00000008 */
6673 #define HASH_SR_BUSY                        HASH_SR_BUSY_Msk
6674 #define HASH_SR_NBWE_Pos                    (16U)
6675 #define HASH_SR_NBWE_Msk                    (0xFUL << HASH_SR_NBWE_Pos)             /*!< 0x000F0000 */
6676 #define HASH_SR_NBWE                        HASH_SR_NBWE_Msk
6677 #define HASH_SR_NBWE_0                      (0x01UL << HASH_SR_NBWE_Pos)            /*!< 0x00010000 */
6678 #define HASH_SR_NBWE_1                      (0x02UL << HASH_SR_NBWE_Pos)            /*!< 0x00020000 */
6679 #define HASH_SR_NBWE_2                      (0x04UL << HASH_SR_NBWE_Pos)            /*!< 0x00040000 */
6680 #define HASH_SR_NBWE_3                      (0x08UL << HASH_SR_NBWE_Pos)            /*!< 0x00080000 */
6681 #define HASH_SR_DINNE_Pos                   (15U)
6682 #define HASH_SR_DINNE_Msk                   (0x1UL << HASH_SR_DINNE_Pos)            /*!< 0x00008000 */
6683 #define HASH_SR_DINNE                       HASH_SR_DINNE_Msk
6684 #define HASH_SR_NBWP_Pos                    (9U)
6685 #define HASH_SR_NBWP_Msk                    (0xFUL << HASH_SR_NBWP_Pos)             /*!< 0x000F0000 */
6686 #define HASH_SR_NBWP                        HASH_SR_NBWP_Msk
6687 #define HASH_SR_NBWP_0                      (0x01UL << HASH_SR_NBWP_Pos)            /*!< 0x000O0200 */
6688 #define HASH_SR_NBWP_1                      (0x02UL << HASH_SR_NBWP_Pos)            /*!< 0x00000400 */
6689 #define HASH_SR_NBWP_2                      (0x04UL << HASH_SR_NBWP_Pos)            /*!< 0x00000800 */
6690 #define HASH_SR_NBWP_3                      (0x08UL << HASH_SR_NBWP_Pos)            /*!< 0x00001000 */
6691 
6692 /******************************************************************************/
6693 /*                                                                            */
6694 /*                                 Debug MCU                                  */
6695 /*                                                                            */
6696 /******************************************************************************/
6697 /********************  Bit definition for DBGMCU_IDCODE register  *************/
6698 #define DBGMCU_IDCODE_DEV_ID_Pos            (0U)
6699 #define DBGMCU_IDCODE_DEV_ID_Msk            (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)   /*!< 0x00000FFF */
6700 #define DBGMCU_IDCODE_DEV_ID                DBGMCU_IDCODE_DEV_ID_Msk
6701 #define DBGMCU_IDCODE_REV_ID_Pos            (16U)
6702 #define DBGMCU_IDCODE_REV_ID_Msk            (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)  /*!< 0xFFFF0000 */
6703 #define DBGMCU_IDCODE_REV_ID                DBGMCU_IDCODE_REV_ID_Msk
6704 
6705 /********************  Bit definition for DBGMCU_CR register  *****************/
6706 #define DBGMCU_CR_DBG_STOP_Pos              (1U)
6707 #define DBGMCU_CR_DBG_STOP_Msk              (0x1UL << DBGMCU_CR_DBG_STOP_Pos)       /*!< 0x00000002 */
6708 #define DBGMCU_CR_DBG_STOP                  DBGMCU_CR_DBG_STOP_Msk
6709 #define DBGMCU_CR_DBG_STANDBY_Pos           (2U)
6710 #define DBGMCU_CR_DBG_STANDBY_Msk           (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)    /*!< 0x00000004 */
6711 #define DBGMCU_CR_DBG_STANDBY               DBGMCU_CR_DBG_STANDBY_Msk
6712 #define DBGMCU_CR_TRACE_IOEN_Pos            (4U)
6713 #define DBGMCU_CR_TRACE_IOEN_Msk            (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)     /*!< 0x00000010 */
6714 #define DBGMCU_CR_TRACE_IOEN                DBGMCU_CR_TRACE_IOEN_Msk
6715 #define DBGMCU_CR_TRACE_CLKEN_Pos           (5U)
6716 #define DBGMCU_CR_TRACE_CLKEN_Msk           (0x1UL << DBGMCU_CR_TRACE_CLKEN_Pos)    /*!< 0x00000020 */
6717 #define DBGMCU_CR_TRACE_CLKEN               DBGMCU_CR_TRACE_CLKEN_Msk
6718 #define DBGMCU_CR_TRACE_MODE_Pos            (6U)
6719 #define DBGMCU_CR_TRACE_MODE_Msk            (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x000000C0 */
6720 #define DBGMCU_CR_TRACE_MODE                DBGMCU_CR_TRACE_MODE_Msk
6721 #define DBGMCU_CR_TRACE_MODE_0              (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x00000040 */
6722 #define DBGMCU_CR_TRACE_MODE_1              (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x00000080 */
6723 
6724 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
6725 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos   (0U)
6726 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)
6727 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP       DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
6728 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos   (1U)
6729 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)
6730 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP       DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
6731 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos   (2U)
6732 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)
6733 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP       DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
6734 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos   (3U)
6735 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)
6736 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP       DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
6737 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos   (4U)
6738 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)
6739 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP       DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
6740 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos   (5U)
6741 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)
6742 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP       DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
6743 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos   (11U)
6744 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)
6745 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP       DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
6746 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos   (12U)
6747 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)
6748 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP       DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
6749 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos   (21U)
6750 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)
6751 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP       DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
6752 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos   (22U)
6753 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)
6754 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP       DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
6755 
6756 /********************  Bit definition for DBGMCU_APB1FZR2 register  ***********/
6757 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos   (1U)
6758 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk   (0x1UL << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos)
6759 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP       DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
6760 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
6761 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)
6762 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP     DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
6763 #define DBGMCU_APB1FZR2_DBG_I2C5_STOP_Pos   (6U)
6764 #define DBGMCU_APB1FZR2_DBG_I2C5_STOP_Msk   (0x1UL << DBGMCU_APB1FZR2_DBG_I2C5_STOP_Pos)
6765 #define DBGMCU_APB1FZR2_DBG_I2C5_STOP       DBGMCU_APB1FZR2_DBG_I2C5_STOP_Msk
6766 #define DBGMCU_APB1FZR2_DBG_I2C6_STOP_Pos   (7U)
6767 #define DBGMCU_APB1FZR2_DBG_I2C6_STOP_Msk   (0x1UL << DBGMCU_APB1FZR2_DBG_I2C6_STOP_Pos)
6768 #define DBGMCU_APB1FZR2_DBG_I2C6_STOP       DBGMCU_APB1FZR2_DBG_I2C6_STOP_Msk
6769 
6770 /********************  Bit definition for DBGMCU_APB2FZR register  ***********/
6771 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos    (11U)
6772 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk    (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)
6773 #define DBGMCU_APB2FZR_DBG_TIM1_STOP        DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk
6774 #define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos    (13U)
6775 #define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk    (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos)
6776 #define DBGMCU_APB2FZR_DBG_TIM8_STOP        DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk
6777 #define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos   (16U)
6778 #define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk   (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos)
6779 #define DBGMCU_APB2FZR_DBG_TIM15_STOP       DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk
6780 #define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos   (17U)
6781 #define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk   (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)
6782 #define DBGMCU_APB2FZR_DBG_TIM16_STOP       DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk
6783 #define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos   (18U)
6784 #define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk   (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)
6785 #define DBGMCU_APB2FZR_DBG_TIM17_STOP       DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk
6786 
6787 /********************  Bit definition for DBGMCU_APB3FZR register  ***********/
6788 #define DBGMCU_APB3FZR_DBG_I2C3_STOP_Pos    (10U)
6789 #define DBGMCU_APB3FZR_DBG_I2C3_STOP_Msk    (0x1UL << DBGMCU_APB3FZR_DBG_I2C3_STOP_Pos)
6790 #define DBGMCU_APB3FZR_DBG_I2C3_STOP        DBGMCU_APB3FZR_DBG_I2C3_STOP_Msk
6791 #define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos  (17U)
6792 #define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos)
6793 #define DBGMCU_APB3FZR_DBG_LPTIM1_STOP      DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk
6794 #define DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Pos  (18U)
6795 #define DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Pos)
6796 #define DBGMCU_APB3FZR_DBG_LPTIM3_STOP      DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Msk
6797 #define DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Pos  (19U)
6798 #define DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Pos)
6799 #define DBGMCU_APB3FZR_DBG_LPTIM4_STOP      DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Msk
6800 #define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos     (30U)
6801 #define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk     (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos)
6802 #define DBGMCU_APB3FZR_DBG_RTC_STOP         DBGMCU_APB3FZR_DBG_RTC_STOP_Msk
6803 
6804 /********************  Bit definition for DBGMCU_AHB1FZR register  ***********/
6805 #define DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Pos  (0U)
6806 #define DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Pos)
6807 #define DBGMCU_AHB1FZR_DBG_GPDMA0_STOP      DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Msk
6808 #define DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Pos  (1U)
6809 #define DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Pos)
6810 #define DBGMCU_AHB1FZR_DBG_GPDMA1_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Msk
6811 #define DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Pos  (2U)
6812 #define DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Pos)
6813 #define DBGMCU_AHB1FZR_DBG_GPDMA2_STOP      DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Msk
6814 #define DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Pos  (3U)
6815 #define DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Pos)
6816 #define DBGMCU_AHB1FZR_DBG_GPDMA3_STOP      DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Msk
6817 #define DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Pos  (4U)
6818 #define DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Pos)
6819 #define DBGMCU_AHB1FZR_DBG_GPDMA4_STOP      DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Msk
6820 #define DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Pos  (5U)
6821 #define DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Pos)
6822 #define DBGMCU_AHB1FZR_DBG_GPDMA5_STOP      DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Msk
6823 #define DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Pos  (6U)
6824 #define DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Pos)
6825 #define DBGMCU_AHB1FZR_DBG_GPDMA6_STOP      DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Msk
6826 #define DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Pos  (7U)
6827 #define DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Pos)
6828 #define DBGMCU_AHB1FZR_DBG_GPDMA7_STOP      DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Msk
6829 #define DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Pos  (8U)
6830 #define DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Pos)
6831 #define DBGMCU_AHB1FZR_DBG_GPDMA8_STOP      DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Msk
6832 #define DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Pos  (9U)
6833 #define DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Pos)
6834 #define DBGMCU_AHB1FZR_DBG_GPDMA9_STOP      DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Msk
6835 #define DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Pos (10U)
6836 #define DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Pos)
6837 #define DBGMCU_AHB1FZR_DBG_GPDMA10_STOP     DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Msk
6838 #define DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Pos (11U)
6839 #define DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Pos)
6840 #define DBGMCU_AHB1FZR_DBG_GPDMA11_STOP     DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Msk
6841 #define DBGMCU_AHB1FZR_DBG_GPDMA12_STOP_Pos (12U)
6842 #define DBGMCU_AHB1FZR_DBG_GPDMA12_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA12_STOP_Pos)
6843 #define DBGMCU_AHB1FZR_DBG_GPDMA12_STOP     DBGMCU_AHB1FZR_DBG_GPDMA12_STOP_Msk
6844 #define DBGMCU_AHB1FZR_DBG_GPDMA13_STOP_Pos (13U)
6845 #define DBGMCU_AHB1FZR_DBG_GPDMA13_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA13_STOP_Pos)
6846 #define DBGMCU_AHB1FZR_DBG_GPDMA13_STOP     DBGMCU_AHB1FZR_DBG_GPDMA13_STOP_Msk
6847 #define DBGMCU_AHB1FZR_DBG_GPDMA14_STOP_Pos (14U)
6848 #define DBGMCU_AHB1FZR_DBG_GPDMA14_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA14_STOP_Pos)
6849 #define DBGMCU_AHB1FZR_DBG_GPDMA14_STOP     DBGMCU_AHB1FZR_DBG_GPDMA14_STOP_Msk
6850 #define DBGMCU_AHB1FZR_DBG_GPDMA15_STOP_Pos (15U)
6851 #define DBGMCU_AHB1FZR_DBG_GPDMA15_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA15_STOP_Pos)
6852 #define DBGMCU_AHB1FZR_DBG_GPDMA15_STOP     DBGMCU_AHB1FZR_DBG_GPDMA15_STOP_Msk
6853 
6854 /********************  Bit definition for DBGMCU_AHB3FZR register  ***********/
6855 #define DBGMCU_AHB3FZR_DBG_LPDMA0_STOP_Pos  (0U)
6856 #define DBGMCU_AHB3FZR_DBG_LPDMA0_STOP_Msk  (0x1UL << DBGMCU_AHB3FZR_DBG_LPDMA0_STOP_Pos)
6857 #define DBGMCU_AHB3FZR_DBG_LPDMA0_STOP      DBGMCU_AHB3FZR_DBG_LPDMA0_STOP_Msk
6858 #define DBGMCU_AHB3FZR_DBG_LPDMA1_STOP_Pos  (1U)
6859 #define DBGMCU_AHB3FZR_DBG_LPDMA1_STOP_Msk  (0x1UL << DBGMCU_AHB3FZR_DBG_LPDMA1_STOP_Pos)
6860 #define DBGMCU_AHB3FZR_DBG_LPDMA1_STOP      DBGMCU_AHB3FZR_DBG_LPDMA1_STOP_Msk
6861 #define DBGMCU_AHB3FZR_DBG_LPDMA2_STOP_Pos  (2U)
6862 #define DBGMCU_AHB3FZR_DBG_LPDMA2_STOP_Msk  (0x1UL << DBGMCU_AHB3FZR_DBG_LPDMA2_STOP_Pos)
6863 #define DBGMCU_AHB3FZR_DBG_LPDMA2_STOP      DBGMCU_AHB3FZR_DBG_LPDMA2_STOP_Msk
6864 #define DBGMCU_AHB3FZR_DBG_LPDMA3_STOP_Pos  (3U)
6865 #define DBGMCU_AHB3FZR_DBG_LPDMA3_STOP_Msk  (0x1UL << DBGMCU_AHB3FZR_DBG_LPDMA3_STOP_Pos)
6866 #define DBGMCU_AHB3FZR_DBG_LPDMA3_STOP      DBGMCU_AHB3FZR_DBG_LPDMA3_STOP_Msk
6867 
6868 /******************************************************************************/
6869 /*                                                                            */
6870 /*                                    DCMI                                    */
6871 /*                                                                            */
6872 /******************************************************************************/
6873 /********************  Bits definition for DCMI_CR register  ******************/
6874 #define DCMI_CR_CAPTURE_Pos                 (0U)
6875 #define DCMI_CR_CAPTURE_Msk                 (0x1UL << DCMI_CR_CAPTURE_Pos)          /*!< 0x00000001 */
6876 #define DCMI_CR_CAPTURE                     DCMI_CR_CAPTURE_Msk
6877 #define DCMI_CR_CM_Pos                      (1U)
6878 #define DCMI_CR_CM_Msk                      (0x1UL << DCMI_CR_CM_Pos)               /*!< 0x00000002 */
6879 #define DCMI_CR_CM                          DCMI_CR_CM_Msk
6880 #define DCMI_CR_CROP_Pos                    (2U)
6881 #define DCMI_CR_CROP_Msk                    (0x1UL << DCMI_CR_CROP_Pos)             /*!< 0x00000004 */
6882 #define DCMI_CR_CROP                        DCMI_CR_CROP_Msk
6883 #define DCMI_CR_JPEG_Pos                    (3U)
6884 #define DCMI_CR_JPEG_Msk                    (0x1UL << DCMI_CR_JPEG_Pos)             /*!< 0x00000008 */
6885 #define DCMI_CR_JPEG                        DCMI_CR_JPEG_Msk
6886 #define DCMI_CR_ESS_Pos                     (4U)
6887 #define DCMI_CR_ESS_Msk                     (0x1UL << DCMI_CR_ESS_Pos)              /*!< 0x00000010 */
6888 #define DCMI_CR_ESS                         DCMI_CR_ESS_Msk
6889 #define DCMI_CR_PCKPOL_Pos                  (5U)
6890 #define DCMI_CR_PCKPOL_Msk                  (0x1UL << DCMI_CR_PCKPOL_Pos)           /*!< 0x00000020 */
6891 #define DCMI_CR_PCKPOL                      DCMI_CR_PCKPOL_Msk
6892 #define DCMI_CR_HSPOL_Pos                   (6U)
6893 #define DCMI_CR_HSPOL_Msk                   (0x1UL << DCMI_CR_HSPOL_Pos)            /*!< 0x00000040 */
6894 #define DCMI_CR_HSPOL                       DCMI_CR_HSPOL_Msk
6895 #define DCMI_CR_VSPOL_Pos                   (7U)
6896 #define DCMI_CR_VSPOL_Msk                   (0x1UL << DCMI_CR_VSPOL_Pos)            /*!< 0x00000080 */
6897 #define DCMI_CR_VSPOL                       DCMI_CR_VSPOL_Msk
6898 #define DCMI_CR_FCRC_Pos                    (8U)
6899 #define DCMI_CR_FCRC_Msk                    (0x3UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000300 */
6900 #define DCMI_CR_FCRC                        DCMI_CR_FCRC_Msk                        /*!< DCMI Frame capture rate control FCRC[1:0] */
6901 #define DCMI_CR_FCRC_0                      (0x1UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000100 */
6902 #define DCMI_CR_FCRC_1                      (0x2UL << DCMI_CR_FCRC_Pos)             /*!< 0x00000200 */
6903 #define DCMI_CR_EDM_Pos                     (10U)
6904 #define DCMI_CR_EDM_Msk                     (0x3UL << DCMI_CR_EDM_Pos)              /*!< 0x00000C00 */
6905 #define DCMI_CR_EDM                         DCMI_CR_EDM_Msk                         /*!< DCMI Extended data mode EDM[1:0] */
6906 #define DCMI_CR_EDM_0                       (0x1UL << DCMI_CR_EDM_Pos)              /*!< 0x00000400 */
6907 #define DCMI_CR_EDM_1                       (0x2UL << DCMI_CR_EDM_Pos)              /*!< 0x00000800 */
6908 #define DCMI_CR_ENABLE_Pos                  (14U)
6909 #define DCMI_CR_ENABLE_Msk                  (0x1UL << DCMI_CR_ENABLE_Pos)           /*!< 0x00004000 */
6910 #define DCMI_CR_ENABLE                      DCMI_CR_ENABLE_Msk
6911 #define DCMI_CR_BSM_Pos                     (16U)
6912 #define DCMI_CR_BSM_Msk                     (0x3UL << DCMI_CR_BSM_Pos)              /*!< 0x00030000 */
6913 #define DCMI_CR_BSM                         DCMI_CR_BSM_Msk
6914 #define DCMI_CR_BSM_0                       (0x1UL << DCMI_CR_BSM_Pos)              /*!< 0x00010000 */
6915 #define DCMI_CR_BSM_1                       (0x2UL << DCMI_CR_BSM_Pos)              /*!< 0x00020000 */
6916 #define DCMI_CR_OEBS_Pos                    (18U)
6917 #define DCMI_CR_OEBS_Msk                    (0x1UL << DCMI_CR_OEBS_Pos)             /*!< 0x00040000 */
6918 #define DCMI_CR_OEBS                        DCMI_CR_OEBS_Msk
6919 #define DCMI_CR_LSM_Pos                     (19U)
6920 #define DCMI_CR_LSM_Msk                     (0x1UL << DCMI_CR_LSM_Pos)              /*!< 0x00080000 */
6921 #define DCMI_CR_LSM                         DCMI_CR_LSM_Msk
6922 #define DCMI_CR_OELS_Pos                    (20U)
6923 #define DCMI_CR_OELS_Msk                    (0x1UL << DCMI_CR_OELS_Pos)             /*!< 0x00100000 */
6924 #define DCMI_CR_OELS                        DCMI_CR_OELS_Msk
6925 #define DCMI_CR_PSDM_Pos                    (31U)
6926 #define DCMI_CR_PSDM_Msk                    (0x0UL << DCMI_CR_PSDM_Pos)             /*!< 0x00000000 */
6927 #define DCMI_CR_PSDM                        DCMI_CR_PSDM_Msk                        /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/
6928 
6929 /********************  Bits definition for DCMI_SR register  ******************/
6930 #define DCMI_SR_HSYNC_Pos                   (0U)
6931 #define DCMI_SR_HSYNC_Msk                   (0x1UL << DCMI_SR_HSYNC_Pos)            /*!< 0x00000001 */
6932 #define DCMI_SR_HSYNC                       DCMI_SR_HSYNC_Msk
6933 #define DCMI_SR_VSYNC_Pos                   (1U)
6934 #define DCMI_SR_VSYNC_Msk                   (0x1UL << DCMI_SR_VSYNC_Pos)            /*!< 0x00000002 */
6935 #define DCMI_SR_VSYNC                       DCMI_SR_VSYNC_Msk
6936 #define DCMI_SR_FNE_Pos                     (2U)
6937 #define DCMI_SR_FNE_Msk                     (0x1UL << DCMI_SR_FNE_Pos)              /*!< 0x00000004 */
6938 #define DCMI_SR_FNE                         DCMI_SR_FNE_Msk
6939 
6940 /********************  Bits definition for DCMI_RIS register   ****************/
6941 #define DCMI_RIS_FRAME_RIS_Pos              (0U)
6942 #define DCMI_RIS_FRAME_RIS_Msk              (0x1UL << DCMI_RIS_FRAME_RIS_Pos)       /*!< 0x00000001 */
6943 #define DCMI_RIS_FRAME_RIS                  DCMI_RIS_FRAME_RIS_Msk
6944 #define DCMI_RIS_OVR_RIS_Pos                (1U)
6945 #define DCMI_RIS_OVR_RIS_Msk                (0x1UL << DCMI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
6946 #define DCMI_RIS_OVR_RIS                    DCMI_RIS_OVR_RIS_Msk
6947 #define DCMI_RIS_ERR_RIS_Pos                (2U)
6948 #define DCMI_RIS_ERR_RIS_Msk                (0x1UL << DCMI_RIS_ERR_RIS_Pos)         /*!< 0x00000004 */
6949 #define DCMI_RIS_ERR_RIS                    DCMI_RIS_ERR_RIS_Msk
6950 #define DCMI_RIS_VSYNC_RIS_Pos              (3U)
6951 #define DCMI_RIS_VSYNC_RIS_Msk              (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)       /*!< 0x00000008 */
6952 #define DCMI_RIS_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS_Msk
6953 #define DCMI_RIS_LINE_RIS_Pos               (4U)
6954 #define DCMI_RIS_LINE_RIS_Msk               (0x1UL << DCMI_RIS_LINE_RIS_Pos)        /*!< 0x00000010 */
6955 #define DCMI_RIS_LINE_RIS                   DCMI_RIS_LINE_RIS_Msk
6956 
6957 /********************  Bits definition for DCMI_IER register  *****************/
6958 #define DCMI_IER_FRAME_IE_Pos               (0U)
6959 #define DCMI_IER_FRAME_IE_Msk               (0x1UL << DCMI_IER_FRAME_IE_Pos)        /*!< 0x00000001 */
6960 #define DCMI_IER_FRAME_IE                   DCMI_IER_FRAME_IE_Msk
6961 #define DCMI_IER_OVR_IE_Pos                 (1U)
6962 #define DCMI_IER_OVR_IE_Msk                 (0x1UL << DCMI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
6963 #define DCMI_IER_OVR_IE                     DCMI_IER_OVR_IE_Msk
6964 #define DCMI_IER_ERR_IE_Pos                 (2U)
6965 #define DCMI_IER_ERR_IE_Msk                 (0x1UL << DCMI_IER_ERR_IE_Pos)          /*!< 0x00000004 */
6966 #define DCMI_IER_ERR_IE                     DCMI_IER_ERR_IE_Msk
6967 #define DCMI_IER_VSYNC_IE_Pos               (3U)
6968 #define DCMI_IER_VSYNC_IE_Msk               (0x1UL << DCMI_IER_VSYNC_IE_Pos)        /*!< 0x00000008 */
6969 #define DCMI_IER_VSYNC_IE                   DCMI_IER_VSYNC_IE_Msk
6970 #define DCMI_IER_LINE_IE_Pos                (4U)
6971 #define DCMI_IER_LINE_IE_Msk                (0x1UL << DCMI_IER_LINE_IE_Pos)         /*!< 0x00000010 */
6972 #define DCMI_IER_LINE_IE                    DCMI_IER_LINE_IE_Msk
6973 
6974 /********************  Bits definition for DCMI_MIS register  *****************/
6975 #define DCMI_MIS_FRAME_MIS_Pos              (0U)
6976 #define DCMI_MIS_FRAME_MIS_Msk              (0x1UL << DCMI_MIS_FRAME_MIS_Pos)       /*!< 0x00000001 */
6977 #define DCMI_MIS_FRAME_MIS                  DCMI_MIS_FRAME_MIS_Msk
6978 #define DCMI_MIS_OVR_MIS_Pos                (1U)
6979 #define DCMI_MIS_OVR_MIS_Msk                (0x1UL << DCMI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
6980 #define DCMI_MIS_OVR_MIS                    DCMI_MIS_OVR_MIS_Msk
6981 #define DCMI_MIS_ERR_MIS_Pos                (2U)
6982 #define DCMI_MIS_ERR_MIS_Msk                (0x1UL << DCMI_MIS_ERR_MIS_Pos)         /*!< 0x00000004 */
6983 #define DCMI_MIS_ERR_MIS                    DCMI_MIS_ERR_MIS_Msk
6984 #define DCMI_MIS_VSYNC_MIS_Pos              (3U)
6985 #define DCMI_MIS_VSYNC_MIS_Msk              (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)       /*!< 0x00000008 */
6986 #define DCMI_MIS_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS_Msk
6987 #define DCMI_MIS_LINE_MIS_Pos               (4U)
6988 #define DCMI_MIS_LINE_MIS_Msk               (0x1UL << DCMI_MIS_LINE_MIS_Pos)        /*!< 0x00000010 */
6989 #define DCMI_MIS_LINE_MIS                   DCMI_MIS_LINE_MIS_Msk
6990 
6991 /********************  Bits definition for DCMI_ICR register  *****************/
6992 #define DCMI_ICR_FRAME_ISC_Pos              (0U)
6993 #define DCMI_ICR_FRAME_ISC_Msk              (0x1UL << DCMI_ICR_FRAME_ISC_Pos)       /*!< 0x00000001 */
6994 #define DCMI_ICR_FRAME_ISC                  DCMI_ICR_FRAME_ISC_Msk
6995 #define DCMI_ICR_OVR_ISC_Pos                (1U)
6996 #define DCMI_ICR_OVR_ISC_Msk                (0x1UL << DCMI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
6997 #define DCMI_ICR_OVR_ISC                    DCMI_ICR_OVR_ISC_Msk
6998 #define DCMI_ICR_ERR_ISC_Pos                (2U)
6999 #define DCMI_ICR_ERR_ISC_Msk                (0x1UL << DCMI_ICR_ERR_ISC_Pos)         /*!< 0x00000004 */
7000 #define DCMI_ICR_ERR_ISC                    DCMI_ICR_ERR_ISC_Msk
7001 #define DCMI_ICR_VSYNC_ISC_Pos              (3U)
7002 #define DCMI_ICR_VSYNC_ISC_Msk              (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)       /*!< 0x00000008 */
7003 #define DCMI_ICR_VSYNC_ISC                  DCMI_ICR_VSYNC_ISC_Msk
7004 #define DCMI_ICR_LINE_ISC_Pos               (4U)
7005 #define DCMI_ICR_LINE_ISC_Msk               (0x1UL << DCMI_ICR_LINE_ISC_Pos)        /*!< 0x00000010 */
7006 #define DCMI_ICR_LINE_ISC                   DCMI_ICR_LINE_ISC_Msk
7007 
7008 /********************  Bits definition for DCMI_ESCR register  ******************/
7009 #define DCMI_ESCR_FSC_Pos                   (0U)
7010 #define DCMI_ESCR_FSC_Msk                   (0xFFUL << DCMI_ESCR_FSC_Pos)           /*!< 0x000000FF */
7011 #define DCMI_ESCR_FSC                       DCMI_ESCR_FSC_Msk
7012 #define DCMI_ESCR_LSC_Pos                   (8U)
7013 #define DCMI_ESCR_LSC_Msk                   (0xFFUL << DCMI_ESCR_LSC_Pos)           /*!< 0x0000FF00 */
7014 #define DCMI_ESCR_LSC                       DCMI_ESCR_LSC_Msk
7015 #define DCMI_ESCR_LEC_Pos                   (16U)
7016 #define DCMI_ESCR_LEC_Msk                   (0xFFUL << DCMI_ESCR_LEC_Pos)           /*!< 0x00FF0000 */
7017 #define DCMI_ESCR_LEC                       DCMI_ESCR_LEC_Msk
7018 #define DCMI_ESCR_FEC_Pos                   (24U)
7019 #define DCMI_ESCR_FEC_Msk                   (0xFFUL << DCMI_ESCR_FEC_Pos)           /*!< 0xFF000000 */
7020 #define DCMI_ESCR_FEC                       DCMI_ESCR_FEC_Msk
7021 
7022 /********************  Bits definition for DCMI_ESUR register  ******************/
7023 #define DCMI_ESUR_FSU_Pos                   (0U)
7024 #define DCMI_ESUR_FSU_Msk                   (0xFFUL << DCMI_ESUR_FSU_Pos)           /*!< 0x000000FF */
7025 #define DCMI_ESUR_FSU                       DCMI_ESUR_FSU_Msk
7026 #define DCMI_ESUR_LSU_Pos                   (8U)
7027 #define DCMI_ESUR_LSU_Msk                   (0xFFUL << DCMI_ESUR_LSU_Pos)           /*!< 0x0000FF00 */
7028 #define DCMI_ESUR_LSU                       DCMI_ESUR_LSU_Msk
7029 #define DCMI_ESUR_LEU_Pos                   (16U)
7030 #define DCMI_ESUR_LEU_Msk                   (0xFFUL << DCMI_ESUR_LEU_Pos)           /*!< 0x00FF0000 */
7031 #define DCMI_ESUR_LEU                       DCMI_ESUR_LEU_Msk
7032 #define DCMI_ESUR_FEU_Pos                   (24U)
7033 #define DCMI_ESUR_FEU_Msk                   (0xFFUL << DCMI_ESUR_FEU_Pos)           /*!< 0xFF000000 */
7034 #define DCMI_ESUR_FEU                       DCMI_ESUR_FEU_Msk
7035 
7036 /********************  Bits definition for DCMI_CWSTRT register  ******************/
7037 #define DCMI_CWSTRT_HOFFCNT_Pos             (0U)
7038 #define DCMI_CWSTRT_HOFFCNT_Msk             (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)   /*!< 0x00003FFF */
7039 #define DCMI_CWSTRT_HOFFCNT                 DCMI_CWSTRT_HOFFCNT_Msk
7040 #define DCMI_CWSTRT_VST_Pos                 (16U)
7041 #define DCMI_CWSTRT_VST_Msk                 (0x1FFFUL << DCMI_CWSTRT_VST_Pos)       /*!< 0x1FFF0000 */
7042 #define DCMI_CWSTRT_VST                     DCMI_CWSTRT_VST_Msk
7043 
7044 /********************  Bits definition for DCMI_CWSIZE register  ******************/
7045 #define DCMI_CWSIZE_CAPCNT_Pos              (0U)
7046 #define DCMI_CWSIZE_CAPCNT_Msk              (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)    /*!< 0x00003FFF */
7047 #define DCMI_CWSIZE_CAPCNT                  DCMI_CWSIZE_CAPCNT_Msk
7048 #define DCMI_CWSIZE_VLINE_Pos               (16U)
7049 #define DCMI_CWSIZE_VLINE_Msk               (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)     /*!< 0x3FFF0000 */
7050 #define DCMI_CWSIZE_VLINE                   DCMI_CWSIZE_VLINE_Msk
7051 
7052 /********************  Bits definition for DCMI_DR register  ******************/
7053 #define DCMI_DR_BYTE0_Pos                   (0U)
7054 #define DCMI_DR_BYTE0_Msk                   (0xFFUL << DCMI_DR_BYTE0_Pos)           /*!< 0x000000FF */
7055 #define DCMI_DR_BYTE0                       DCMI_DR_BYTE0_Msk
7056 #define DCMI_DR_BYTE1_Pos                   (8U)
7057 #define DCMI_DR_BYTE1_Msk                   (0xFFUL << DCMI_DR_BYTE1_Pos)           /*!< 0x0000FF00 */
7058 #define DCMI_DR_BYTE1                       DCMI_DR_BYTE1_Msk
7059 #define DCMI_DR_BYTE2_Pos                   (16U)
7060 #define DCMI_DR_BYTE2_Msk                   (0xFFUL << DCMI_DR_BYTE2_Pos)           /*!< 0x00FF0000 */
7061 #define DCMI_DR_BYTE2                       DCMI_DR_BYTE2_Msk
7062 #define DCMI_DR_BYTE3_Pos                   (24U)
7063 #define DCMI_DR_BYTE3_Msk                   (0xFFUL << DCMI_DR_BYTE3_Pos)           /*!< 0xFF000000 */
7064 #define DCMI_DR_BYTE3                       DCMI_DR_BYTE3_Msk
7065 
7066 /******************************************************************************/
7067 /*                                                                            */
7068 /*                           DMA Controller (DMA)                             */
7069 /*                                                                            */
7070 /******************************************************************************/
7071 /************************  DMA Trigger Signals Support  ***********************/
7072 #define TIM3_TRGO_TRIGGER_SUPPORT /* TIM3 TRGO HW signal support  */
7073 #define TIM4_TRGO_TRIGGER_SUPPORT /* TIM4 TRGO HW signal support  */
7074 #define TIM5_TRGO_TRIGGER_SUPPORT /* TIM5 TRGO HW signal support  */
7075 #define DMA2D_TRIGGER_SUPPORT     /* DMA2D TRGO HW signal support */
7076 /*******************  Bit definition for DMA_SECCFGR register  ****************/
7077 #define DMA_SECCFGR_SEC0_Pos                (0U)
7078 #define DMA_SECCFGR_SEC0_Msk                (0x1UL << DMA_SECCFGR_SEC0_Pos)         /*!< 0x00000001 */
7079 #define DMA_SECCFGR_SEC0                    DMA_SECCFGR_SEC0_Msk                    /*!< Secure State of Channel 0  */
7080 #define DMA_SECCFGR_SEC1_Pos                (1U)
7081 #define DMA_SECCFGR_SEC1_Msk                (0x1UL << DMA_SECCFGR_SEC1_Pos)         /*!< 0x00000002 */
7082 #define DMA_SECCFGR_SEC1                    DMA_SECCFGR_SEC1_Msk                    /*!< Secure State of Channel 1  */
7083 #define DMA_SECCFGR_SEC2_Pos                (2U)
7084 #define DMA_SECCFGR_SEC2_Msk                (0x1UL << DMA_SECCFGR_SEC2_Pos)         /*!< 0x00000004 */
7085 #define DMA_SECCFGR_SEC2                    DMA_SECCFGR_SEC2_Msk                    /*!< Secure State of Channel 2  */
7086 #define DMA_SECCFGR_SEC3_Pos                (3U)
7087 #define DMA_SECCFGR_SEC3_Msk                (0x1UL << DMA_SECCFGR_SEC3_Pos)         /*!< 0x00000008 */
7088 #define DMA_SECCFGR_SEC3                    DMA_SECCFGR_SEC3_Msk                    /*!< Secure State of Channel 3  */
7089 #define DMA_SECCFGR_SEC4_Pos                (4U)
7090 #define DMA_SECCFGR_SEC4_Msk                (0x1UL << DMA_SECCFGR_SEC4_Pos)         /*!< 0x00000010 */
7091 #define DMA_SECCFGR_SEC4                    DMA_SECCFGR_SEC4_Msk                    /*!< Secure State of Channel 4  */
7092 #define DMA_SECCFGR_SEC5_Pos                (5U)
7093 #define DMA_SECCFGR_SEC5_Msk                (0x1UL << DMA_SECCFGR_SEC5_Pos)         /*!< 0x00000020 */
7094 #define DMA_SECCFGR_SEC5                    DMA_SECCFGR_SEC5_Msk                    /*!< Secure State of Channel 5  */
7095 #define DMA_SECCFGR_SEC6_Pos                (6U)
7096 #define DMA_SECCFGR_SEC6_Msk                (0x1UL << DMA_SECCFGR_SEC6_Pos)         /*!< 0x00000040 */
7097 #define DMA_SECCFGR_SEC6                    DMA_SECCFGR_SEC6_Msk                    /*!< Secure State of Channel 6  */
7098 #define DMA_SECCFGR_SEC7_Pos                (7U)
7099 #define DMA_SECCFGR_SEC7_Msk                (0x1UL << DMA_SECCFGR_SEC7_Pos)         /*!< 0x00000080 */
7100 #define DMA_SECCFGR_SEC7                    DMA_SECCFGR_SEC7_Msk                    /*!< Secure State of Channel 7  */
7101 #define DMA_SECCFGR_SEC8_Pos                (8U)
7102 #define DMA_SECCFGR_SEC8_Msk                (0x1UL << DMA_SECCFGR_SEC8_Pos)         /*!< 0x00000100 */
7103 #define DMA_SECCFGR_SEC8                    DMA_SECCFGR_SEC8_Msk                    /*!< Secure State of Channel 8  */
7104 #define DMA_SECCFGR_SEC9_Pos                (9U)
7105 #define DMA_SECCFGR_SEC9_Msk                (0x1UL << DMA_SECCFGR_SEC9_Pos)         /*!< 0x00000200 */
7106 #define DMA_SECCFGR_SEC9                    DMA_SECCFGR_SEC9_Msk                    /*!< Secure State of Channel 9  */
7107 #define DMA_SECCFGR_SEC10_Pos               (10U)
7108 #define DMA_SECCFGR_SEC10_Msk               (0x1UL << DMA_SECCFGR_SEC10_Pos)        /*!< 0x00000400 */
7109 #define DMA_SECCFGR_SEC10                   DMA_SECCFGR_SEC10_Msk                   /*!< Secure State of Channel 10 */
7110 #define DMA_SECCFGR_SEC11_Pos               (11U)
7111 #define DMA_SECCFGR_SEC11_Msk               (0x1UL << DMA_SECCFGR_SEC11_Pos)        /*!< 0x00000800 */
7112 #define DMA_SECCFGR_SEC11                   DMA_SECCFGR_SEC11_Msk                   /*!< Secure State of Channel 11 */
7113 #define DMA_SECCFGR_SEC12_Pos               (12U)
7114 #define DMA_SECCFGR_SEC12_Msk               (0x1UL << DMA_SECCFGR_SEC12_Pos)        /*!< 0x00001000 */
7115 #define DMA_SECCFGR_SEC12                   DMA_SECCFGR_SEC12_Msk                   /*!< Secure State of Channel 12 */
7116 #define DMA_SECCFGR_SEC13_Pos               (13U)
7117 #define DMA_SECCFGR_SEC13_Msk               (0x1UL << DMA_SECCFGR_SEC13_Pos)        /*!< 0x00002000 */
7118 #define DMA_SECCFGR_SEC13                   DMA_SECCFGR_SEC13_Msk                   /*!< Secure State of Channel 13 */
7119 #define DMA_SECCFGR_SEC14_Pos               (14U)
7120 #define DMA_SECCFGR_SEC14_Msk               (0x1UL << DMA_SECCFGR_SEC14_Pos)        /*!< 0x00004000 */
7121 #define DMA_SECCFGR_SEC14                   DMA_SECCFGR_SEC14_Msk                   /*!< Secure State of Channel 14 */
7122 #define DMA_SECCFGR_SEC15_Pos               (15U)
7123 #define DMA_SECCFGR_SEC15_Msk               (0x1UL << DMA_SECCFGR_SEC15_Pos)        /*!< 0x00008000 */
7124 #define DMA_SECCFGR_SEC15                   DMA_SECCFGR_SEC15_Msk                   /*!< Secure State of Channel 15 */
7125 
7126 /*******************  Bit definition for DMA_PRIVCFGR register  ****************/
7127 #define DMA_PRIVCFGR_PRIV0_Pos              (0U)
7128 #define DMA_PRIVCFGR_PRIV0_Msk              (0x1UL << DMA_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
7129 #define DMA_PRIVCFGR_PRIV0                  DMA_PRIVCFGR_PRIV0_Msk                  /*!< Privileged State of Channel 0  */
7130 #define DMA_PRIVCFGR_PRIV1_Pos              (1U)
7131 #define DMA_PRIVCFGR_PRIV1_Msk              (0x1UL << DMA_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
7132 #define DMA_PRIVCFGR_PRIV1                  DMA_PRIVCFGR_PRIV1_Msk                  /*!< Privileged State of Channel 1  */
7133 #define DMA_PRIVCFGR_PRIV2_Pos              (2U)
7134 #define DMA_PRIVCFGR_PRIV2_Msk              (0x1UL << DMA_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
7135 #define DMA_PRIVCFGR_PRIV2                  DMA_PRIVCFGR_PRIV2_Msk                  /*!< Privileged State of Channel 2  */
7136 #define DMA_PRIVCFGR_PRIV3_Pos              (3U)
7137 #define DMA_PRIVCFGR_PRIV3_Msk              (0x1UL << DMA_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
7138 #define DMA_PRIVCFGR_PRIV3                  DMA_PRIVCFGR_PRIV3_Msk                  /*!< Privileged State of Channel 3  */
7139 #define DMA_PRIVCFGR_PRIV4_Pos              (4U)
7140 #define DMA_PRIVCFGR_PRIV4_Msk              (0x1UL << DMA_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
7141 #define DMA_PRIVCFGR_PRIV4                  DMA_PRIVCFGR_PRIV4_Msk                  /*!< Privileged State of Channel 4  */
7142 #define DMA_PRIVCFGR_PRIV5_Pos              (5U)
7143 #define DMA_PRIVCFGR_PRIV5_Msk              (0x1UL << DMA_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
7144 #define DMA_PRIVCFGR_PRIV5                  DMA_PRIVCFGR_PRIV5_Msk                  /*!< Privileged State of Channel 5  */
7145 #define DMA_PRIVCFGR_PRIV6_Pos              (6U)
7146 #define DMA_PRIVCFGR_PRIV6_Msk              (0x1UL << DMA_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
7147 #define DMA_PRIVCFGR_PRIV6                  DMA_PRIVCFGR_PRIV6_Msk                  /*!< Privileged State of Channel 6  */
7148 #define DMA_PRIVCFGR_PRIV7_Pos              (7U)
7149 #define DMA_PRIVCFGR_PRIV7_Msk              (0x1UL << DMA_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
7150 #define DMA_PRIVCFGR_PRIV7                  DMA_PRIVCFGR_PRIV7_Msk                  /*!< Privileged State of Channel 7  */
7151 #define DMA_PRIVCFGR_PRIV8_Pos              (8U)
7152 #define DMA_PRIVCFGR_PRIV8_Msk              (0x1UL << DMA_PRIVCFGR_PRIV8_Pos)       /*!< 0x00000100 */
7153 #define DMA_PRIVCFGR_PRIV8                  DMA_PRIVCFGR_PRIV8_Msk                  /*!< Privileged State of Channel 8  */
7154 #define DMA_PRIVCFGR_PRIV9_Pos              (9U)
7155 #define DMA_PRIVCFGR_PRIV9_Msk              (0x1UL << DMA_PRIVCFGR_PRIV9_Pos)       /*!< 0x00000200 */
7156 #define DMA_PRIVCFGR_PRIV9                  DMA_PRIVCFGR_PRIV9_Msk                  /*!< Privileged State of Channel 9  */
7157 #define DMA_PRIVCFGR_PRIV10_Pos             (10U)
7158 #define DMA_PRIVCFGR_PRIV10_Msk             (0x1UL << DMA_PRIVCFGR_PRIV10_Pos)      /*!< 0x00000400 */
7159 #define DMA_PRIVCFGR_PRIV10                 DMA_PRIVCFGR_PRIV10_Msk                 /*!< Privileged State of Channel 10 */
7160 #define DMA_PRIVCFGR_PRIV11_Pos             (11U)
7161 #define DMA_PRIVCFGR_PRIV11_Msk             (0x1UL << DMA_PRIVCFGR_PRIV11_Pos)      /*!< 0x00000800 */
7162 #define DMA_PRIVCFGR_PRIV11                 DMA_PRIVCFGR_PRIV11_Msk                 /*!< Privileged State of Channel 11 */
7163 #define DMA_PRIVCFGR_PRIV12_Pos             (12U)
7164 #define DMA_PRIVCFGR_PRIV12_Msk             (0x1UL << DMA_PRIVCFGR_PRIV12_Pos)      /*!< 0x00001000 */
7165 #define DMA_PRIVCFGR_PRIV12                 DMA_PRIVCFGR_PRIV12_Msk                 /*!< Privileged State of Channel 12 */
7166 #define DMA_PRIVCFGR_PRIV13_Pos             (13U)
7167 #define DMA_PRIVCFGR_PRIV13_Msk             (0x1UL << DMA_PRIVCFGR_PRIV13_Pos)      /*!< 0x00002000 */
7168 #define DMA_PRIVCFGR_PRIV13                 DMA_PRIVCFGR_PRIV13_Msk                 /*!< Privileged State of Channel 13 */
7169 #define DMA_PRIVCFGR_PRIV14_Pos             (14U)
7170 #define DMA_PRIVCFGR_PRIV14_Msk             (0x1UL << DMA_PRIVCFGR_PRIV14_Pos)      /*!< 0x00004000 */
7171 #define DMA_PRIVCFGR_PRIV14                 DMA_PRIVCFGR_PRIV14_Msk                 /*!< Privileged State of Channel 14 */
7172 #define DMA_PRIVCFGR_PRIV15_Pos             (15U)
7173 #define DMA_PRIVCFGR_PRIV15_Msk             (0x1UL << DMA_PRIVCFGR_PRIV15_Pos)      /*!< 0x00008000 */
7174 #define DMA_PRIVCFGR_PRIV15                 DMA_PRIVCFGR_PRIV15_Msk                 /*!< Privileged State of Channel 15 */
7175 
7176 /*******************  Bit definition for DMA_RCFGLOCKR register  ****************/
7177 #define DMA_RCFGLOCKR_LOCK0_Pos              (0U)
7178 #define DMA_RCFGLOCKR_LOCK0_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos)       /*!< 0x00000001 */
7179 #define DMA_RCFGLOCKR_LOCK0                  DMA_RCFGLOCKR_LOCK0_Msk                  /*!< Lock the configuration of Channel 0  */
7180 #define DMA_RCFGLOCKR_LOCK1_Pos              (1U)
7181 #define DMA_RCFGLOCKR_LOCK1_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos)       /*!< 0x00000002 */
7182 #define DMA_RCFGLOCKR_LOCK1                  DMA_RCFGLOCKR_LOCK1_Msk                  /*!< Lock the configuration of Channel 1  */
7183 #define DMA_RCFGLOCKR_LOCK2_Pos              (2U)
7184 #define DMA_RCFGLOCKR_LOCK2_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos)       /*!< 0x00000004 */
7185 #define DMA_RCFGLOCKR_LOCK2                  DMA_RCFGLOCKR_LOCK2_Msk                  /*!< Lock the configuration of Channel 2  */
7186 #define DMA_RCFGLOCKR_LOCK3_Pos              (3U)
7187 #define DMA_RCFGLOCKR_LOCK3_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos)       /*!< 0x00000008 */
7188 #define DMA_RCFGLOCKR_LOCK3                  DMA_RCFGLOCKR_LOCK3_Msk                  /*!< Lock the configuration of Channel 3  */
7189 #define DMA_RCFGLOCKR_LOCK4_Pos              (4U)
7190 #define DMA_RCFGLOCKR_LOCK4_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos)       /*!< 0x00000010 */
7191 #define DMA_RCFGLOCKR_LOCK4                  DMA_RCFGLOCKR_LOCK4_Msk                  /*!< Lock the configuration of Channel 4  */
7192 #define DMA_RCFGLOCKR_LOCK5_Pos              (5U)
7193 #define DMA_RCFGLOCKR_LOCK5_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos)       /*!< 0x00000020 */
7194 #define DMA_RCFGLOCKR_LOCK5                  DMA_RCFGLOCKR_LOCK5_Msk                  /*!< Lock the configuration of Channel 5  */
7195 #define DMA_RCFGLOCKR_LOCK6_Pos              (6U)
7196 #define DMA_RCFGLOCKR_LOCK6_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos)       /*!< 0x00000040 */
7197 #define DMA_RCFGLOCKR_LOCK6                  DMA_RCFGLOCKR_LOCK6_Msk                  /*!< Lock the configuration of Channel 6  */
7198 #define DMA_RCFGLOCKR_LOCK7_Pos              (7U)
7199 #define DMA_RCFGLOCKR_LOCK7_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos)       /*!< 0x00000080 */
7200 #define DMA_RCFGLOCKR_LOCK7                  DMA_RCFGLOCKR_LOCK7_Msk                  /*!< Lock the configuration of Channel 7  */
7201 #define DMA_RCFGLOCKR_LOCK8_Pos              (8U)
7202 #define DMA_RCFGLOCKR_LOCK8_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK8_Pos)       /*!< 0x00000100 */
7203 #define DMA_RCFGLOCKR_LOCK8                  DMA_RCFGLOCKR_LOCK8_Msk                  /*!< Lock the configuration of Channel 8  */
7204 #define DMA_RCFGLOCKR_LOCK9_Pos              (9U)
7205 #define DMA_RCFGLOCKR_LOCK9_Msk              (0x1UL << DMA_RCFGLOCKR_LOCK9_Pos)       /*!< 0x00000200 */
7206 #define DMA_RCFGLOCKR_LOCK9                  DMA_RCFGLOCKR_LOCK9_Msk                  /*!< Lock the configuration of Channel 9  */
7207 #define DMA_RCFGLOCKR_LOCK10_Pos             (10U)
7208 #define DMA_RCFGLOCKR_LOCK10_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK10_Pos)      /*!< 0x00000400 */
7209 #define DMA_RCFGLOCKR_LOCK10                 DMA_RCFGLOCKR_LOCK10_Msk                 /*!< Lock the configuration of Channel 10 */
7210 #define DMA_RCFGLOCKR_LOCK11_Pos             (11U)
7211 #define DMA_RCFGLOCKR_LOCK11_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK11_Pos)      /*!< 0x00000800 */
7212 #define DMA_RCFGLOCKR_LOCK11                 DMA_RCFGLOCKR_LOCK11_Msk                 /*!< Lock the configuration of Channel 11 */
7213 #define DMA_RCFGLOCKR_LOCK12_Pos             (12U)
7214 #define DMA_RCFGLOCKR_LOCK12_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK12_Pos)      /*!< 0x00001000 */
7215 #define DMA_RCFGLOCKR_LOCK12                 DMA_RCFGLOCKR_LOCK12_Msk                 /*!< Lock the configuration of Channel 12 */
7216 #define DMA_RCFGLOCKR_LOCK13_Pos             (13U)
7217 #define DMA_RCFGLOCKR_LOCK13_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK13_Pos)      /*!< 0x00002000 */
7218 #define DMA_RCFGLOCKR_LOCK13                 DMA_RCFGLOCKR_LOCK13_Msk                 /*!< Lock the configuration of Channel 13 */
7219 #define DMA_RCFGLOCKR_LOCK14_Pos             (14U)
7220 #define DMA_RCFGLOCKR_LOCK14_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK14_Pos)      /*!< 0x00004000 */
7221 #define DMA_RCFGLOCKR_LOCK14                 DMA_RCFGLOCKR_LOCK14_Msk                 /*!< Lock the configuration of Channel 14 */
7222 #define DMA_RCFGLOCKR_LOCK15_Pos             (15U)
7223 #define DMA_RCFGLOCKR_LOCK15_Msk             (0x1UL << DMA_RCFGLOCKR_LOCK15_Pos)      /*!< 0x00008000 */
7224 #define DMA_RCFGLOCKR_LOCK15                 DMA_RCFGLOCKR_LOCK15_Msk                 /*!< Lock the configuration of Channel 15 */
7225 
7226 /*******************  Bit definition for DMA_MISR register  ****************/
7227 #define DMA_MISR_MIS0_Pos                   (0U)
7228 #define DMA_MISR_MIS0_Msk                   (0x1UL << DMA_MISR_MIS0_Pos)            /*!< 0x00000001 */
7229 #define DMA_MISR_MIS0                       DMA_MISR_MIS0_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 0  */
7230 #define DMA_MISR_MIS1_Pos                   (1U)
7231 #define DMA_MISR_MIS1_Msk                   (0x1UL << DMA_MISR_MIS1_Pos)            /*!< 0x00000002 */
7232 #define DMA_MISR_MIS1                       DMA_MISR_MIS1_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 1  */
7233 #define DMA_MISR_MIS2_Pos                   (2U)
7234 #define DMA_MISR_MIS2_Msk                   (0x1UL << DMA_MISR_MIS2_Pos)            /*!< 0x00000004 */
7235 #define DMA_MISR_MIS2                       DMA_MISR_MIS2_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 2  */
7236 #define DMA_MISR_MIS3_Pos                   (3U)
7237 #define DMA_MISR_MIS3_Msk                   (0x1UL << DMA_MISR_MIS3_Pos)            /*!< 0x00000008 */
7238 #define DMA_MISR_MIS3                       DMA_MISR_MIS3_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 3  */
7239 #define DMA_MISR_MIS4_Pos                   (4U)
7240 #define DMA_MISR_MIS4_Msk                   (0x1UL << DMA_MISR_MIS4_Pos)            /*!< 0x00000010 */
7241 #define DMA_MISR_MIS4                       DMA_MISR_MIS4_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 4  */
7242 #define DMA_MISR_MIS5_Pos                   (5U)
7243 #define DMA_MISR_MIS5_Msk                   (0x1UL << DMA_MISR_MIS5_Pos)            /*!< 0x00000020 */
7244 #define DMA_MISR_MIS5                       DMA_MISR_MIS5_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 5  */
7245 #define DMA_MISR_MIS6_Pos                   (6U)
7246 #define DMA_MISR_MIS6_Msk                   (0x1UL << DMA_MISR_MIS6_Pos)            /*!< 0x00000040 */
7247 #define DMA_MISR_MIS6                       DMA_MISR_MIS6_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 6  */
7248 #define DMA_MISR_MIS7_Pos                   (7U)
7249 #define DMA_MISR_MIS7_Msk                   (0x1UL << DMA_MISR_MIS7_Pos)            /*!< 0x00000080 */
7250 #define DMA_MISR_MIS7                       DMA_MISR_MIS7_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 7  */
7251 #define DMA_MISR_MIS8_Pos                   (8U)
7252 #define DMA_MISR_MIS8_Msk                   (0x1UL << DMA_MISR_MIS8_Pos)            /*!< 0x00000100 */
7253 #define DMA_MISR_MIS8                       DMA_MISR_MIS8_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 8  */
7254 #define DMA_MISR_MIS9_Pos                   (9U)
7255 #define DMA_MISR_MIS9_Msk                   (0x1UL << DMA_MISR_MIS9_Pos)            /*!< 0x00000200 */
7256 #define DMA_MISR_MIS9                       DMA_MISR_MIS9_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 9  */
7257 #define DMA_MISR_MIS10_Pos                  (10U)
7258 #define DMA_MISR_MIS10_Msk                  (0x1UL << DMA_MISR_MIS10_Pos)           /*!< 0x00000400 */
7259 #define DMA_MISR_MIS10                      DMA_MISR_MIS10_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 10 */
7260 #define DMA_MISR_MIS11_Pos                  (11U)
7261 #define DMA_MISR_MIS11_Msk                  (0x1UL << DMA_MISR_MIS11_Pos)           /*!< 0x00000800 */
7262 #define DMA_MISR_MIS11                      DMA_MISR_MIS11_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 11 */
7263 #define DMA_MISR_MIS12_Pos                  (12U)
7264 #define DMA_MISR_MIS12_Msk                  (0x1UL << DMA_MISR_MIS12_Pos)           /*!< 0x00001000 */
7265 #define DMA_MISR_MIS12                      DMA_MISR_MIS12_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 12 */
7266 #define DMA_MISR_MIS13_Pos                  (13U)
7267 #define DMA_MISR_MIS13_Msk                  (0x1UL << DMA_MISR_MIS13_Pos)           /*!< 0x00002000 */
7268 #define DMA_MISR_MIS13                      DMA_MISR_MIS13_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 13 */
7269 #define DMA_MISR_MIS14_Pos                  (14U)
7270 #define DMA_MISR_MIS14_Msk                  (0x1UL << DMA_MISR_MIS14_Pos)           /*!< 0x00004000 */
7271 #define DMA_MISR_MIS14                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 14 */
7272 #define DMA_MISR_MIS15_Pos                  (15U)
7273 #define DMA_MISR_MIS15_Msk                  (0x1UL << DMA_MISR_MIS15_Pos)           /*!< 0x00008000 */
7274 #define DMA_MISR_MIS15                      DMA_MISR_MIS14_Msk                      /*!< Masked Interrupt State of Non-Secure Channel 15 */
7275 
7276 /*******************  Bit definition for DMA_SMISR register  ****************/
7277 #define DMA_SMISR_MIS0_Pos                  (0U)
7278 #define DMA_SMISR_MIS0_Msk                  (0x1UL << DMA_SMISR_MIS0_Pos)           /*!< 0x00000001 */
7279 #define DMA_SMISR_MIS0                      DMA_SMISR_MIS0_Msk                      /*!< Masked Interrupt State of Secure Channel 0  */
7280 #define DMA_SMISR_MIS1_Pos                  (1U)
7281 #define DMA_SMISR_MIS1_Msk                  (0x1UL << DMA_SMISR_MIS1_Pos)           /*!< 0x00000002 */
7282 #define DMA_SMISR_MIS1                      DMA_SMISR_MIS1_Msk                      /*!< Masked Interrupt State of Secure Channel 1  */
7283 #define DMA_SMISR_MIS2_Pos                  (2U)
7284 #define DMA_SMISR_MIS2_Msk                  (0x1UL << DMA_SMISR_MIS2_Pos)           /*!< 0x00000004 */
7285 #define DMA_SMISR_MIS2                      DMA_SMISR_MIS2_Msk                      /*!< Masked Interrupt State of Secure Channel 2  */
7286 #define DMA_SMISR_MIS3_Pos                  (3U)
7287 #define DMA_SMISR_MIS3_Msk                  (0x1UL << DMA_SMISR_MIS3_Pos)           /*!< 0x00000008 */
7288 #define DMA_SMISR_MIS3                      DMA_SMISR_MIS3_Msk                      /*!< Masked Interrupt State of Secure Channel 3  */
7289 #define DMA_SMISR_MIS4_Pos                  (4U)
7290 #define DMA_SMISR_MIS4_Msk                  (0x1UL << DMA_SMISR_MIS4_Pos)           /*!< 0x00000010 */
7291 #define DMA_SMISR_MIS4                      DMA_SMISR_MIS4_Msk                      /*!< Masked Interrupt State of Secure Channel 4  */
7292 #define DMA_SMISR_MIS5_Pos                  (5U)
7293 #define DMA_SMISR_MIS5_Msk                  (0x1UL << DMA_SMISR_MIS5_Pos)           /*!< 0x00000020 */
7294 #define DMA_SMISR_MIS5                      DMA_SMISR_MIS5_Msk                      /*!< Masked Interrupt State of Secure Channel 5  */
7295 #define DMA_SMISR_MIS6_Pos                  (6U)
7296 #define DMA_SMISR_MIS6_Msk                  (0x1UL << DMA_SMISR_MIS6_Pos)           /*!< 0x00000040 */
7297 #define DMA_SMISR_MIS6                      DMA_SMISR_MIS6_Msk                      /*!< Masked Interrupt State of Secure Channel 6  */
7298 #define DMA_SMISR_MIS7_Pos                  (7U)
7299 #define DMA_SMISR_MIS7_Msk                  (0x1UL << DMA_SMISR_MIS7_Pos)           /*!< 0x00000080 */
7300 #define DMA_SMISR_MIS7                      DMA_SMISR_MIS7_Msk                      /*!< Masked Interrupt State of Secure Channel 7  */
7301 #define DMA_SMISR_MIS8_Pos                  (8U)
7302 #define DMA_SMISR_MIS8_Msk                  (0x1UL << DMA_SMISR_MIS8_Pos)           /*!< 0x00000100 */
7303 #define DMA_SMISR_MIS8                      DMA_SMISR_MIS8_Msk                      /*!< Masked Interrupt State of Secure Channel 8  */
7304 #define DMA_SMISR_MIS9_Pos                  (9U)
7305 #define DMA_SMISR_MIS9_Msk                  (0x1UL << DMA_SMISR_MIS9_Pos)           /*!< 0x00000200 */
7306 #define DMA_SMISR_MIS9                      DMA_SMISR_MIS9_Msk                      /*!< Masked Interrupt State of Secure Channel 9  */
7307 #define DMA_SMISR_MIS10_Pos                 (10U)
7308 #define DMA_SMISR_MIS10_Msk                 (0x1UL << DMA_SMISR_MIS10_Pos)          /*!< 0x00000400 */
7309 #define DMA_SMISR_MIS10                     DMA_SMISR_MIS10_Msk                     /*!< Masked Interrupt State of Secure Channel 10 */
7310 #define DMA_SMISR_MIS11_Pos                 (11U)
7311 #define DMA_SMISR_MIS11_Msk                 (0x1UL << DMA_SMISR_MIS11_Pos)          /*!< 0x00000800 */
7312 #define DMA_SMISR_MIS11                     DMA_SMISR_MIS11_Msk                     /*!< Masked Interrupt State of Secure Channel 11 */
7313 #define DMA_SMISR_MIS12_Pos                 (12U)
7314 #define DMA_SMISR_MIS12_Msk                 (0x1UL << DMA_SMISR_MIS12_Pos)          /*!< 0x00001000 */
7315 #define DMA_SMISR_MIS12                     DMA_SMISR_MIS12_Msk                     /*!< Masked Interrupt State of Secure Channel 12 */
7316 #define DMA_SMISR_MIS13_Pos                 (13U)
7317 #define DMA_SMISR_MIS13_Msk                 (0x1UL << DMA_SMISR_MIS13_Pos)          /*!< 0x00002000 */
7318 #define DMA_SMISR_MIS13                     DMA_SMISR_MIS13_Msk                     /*!< Masked Interrupt State of Secure Channel 13 */
7319 #define DMA_SMISR_MIS14_Pos                 (14U)
7320 #define DMA_SMISR_MIS14_Msk                 (0x1UL << DMA_SMISR_MIS14_Pos)          /*!< 0x00004000 */
7321 #define DMA_SMISR_MIS14                     DMA_SMISR_MIS14_Msk                     /*!< Masked Interrupt State of Secure Channel 14 */
7322 #define DMA_SMISR_MIS15_Pos                 (15U)
7323 #define DMA_SMISR_MIS15_Msk                 (0x1UL << DMA_SMISR_MIS15_Pos)          /*!< 0x00008000 */
7324 #define DMA_SMISR_MIS15                     DMA_SMISR_MIS14_Msk                     /*!< Masked Interrupt State of Secure Channel 15 */
7325 
7326 /*******************  Bit definition for DMA_CLBAR register  ****************/
7327 #define DMA_CLBAR_LBA_Pos                   (16U)
7328 #define DMA_CLBAR_LBA_Msk                   (0xFFFFUL << DMA_CLBAR_LBA_Pos)         /*!< 0xFFFF0000 */
7329 #define DMA_CLBAR_LBA                       DMA_CLBAR_LBA_Msk                       /*!< Linked-list Base Address of DMA channel x */
7330 
7331 /*******************  Bit definition for DMA_CFCR register  *******************/
7332 #define DMA_CFCR_TCF_Pos                    (8U)
7333 #define DMA_CFCR_TCF_Msk                    (0x1UL << DMA_CFCR_TCF_Pos)             /*!< 0x00000100 */
7334 #define DMA_CFCR_TCF                        DMA_CFCR_TCF_Msk                        /*!< Transfer complete flag clear             */
7335 #define DMA_CFCR_HTF_Pos                    (9U)
7336 #define DMA_CFCR_HTF_Msk                    (0x1UL << DMA_CFCR_HTF_Pos)             /*!< 0x00000200 */
7337 #define DMA_CFCR_HTF                        DMA_CFCR_HTF_Msk                        /*!< Half transfer complete flag clear        */
7338 #define DMA_CFCR_DTEF_Pos                   (10U)
7339 #define DMA_CFCR_DTEF_Msk                   (0x1UL << DMA_CFCR_DTEF_Pos)            /*!< 0x00000400 */
7340 #define DMA_CFCR_DTEF                       DMA_CFCR_DTEF_Msk                       /*!< Data transfer error flag clear           */
7341 #define DMA_CFCR_ULEF_Pos                   (11U)
7342 #define DMA_CFCR_ULEF_Msk                   (0x1UL << DMA_CFCR_ULEF_Pos)            /*!< 0x00000800 */
7343 #define DMA_CFCR_ULEF                       DMA_CFCR_ULEF_Msk                       /*!< Update linked-list item error flag clear */
7344 #define DMA_CFCR_USEF_Pos                   (12U)
7345 #define DMA_CFCR_USEF_Msk                   (0x1UL << DMA_CFCR_USEF_Pos)            /*!< 0x00001000 */
7346 #define DMA_CFCR_USEF                       DMA_CFCR_USEF_Msk                       /*!< User setting error flag clear            */
7347 #define DMA_CFCR_SUSPF_Pos                  (13U)
7348 #define DMA_CFCR_SUSPF_Msk                  (0x1UL << DMA_CFCR_SUSPF_Pos)           /*!< 0x00002000 */
7349 #define DMA_CFCR_SUSPF                      DMA_CFCR_SUSPF_Msk                      /*!< Completed suspension flag clear          */
7350 #define DMA_CFCR_TOF_Pos                    (14U)
7351 #define DMA_CFCR_TOF_Msk                    (0x1UL << DMA_CFCR_TOF_Pos)             /*!< 0x00004000 */
7352 #define DMA_CFCR_TOF                        DMA_CFCR_TOF_Msk                        /*!< Trigger overrun flag clear               */
7353 
7354 /*******************  Bit definition for DMA_CSR register  *******************/
7355 #define DMA_CSR_IDLEF_Pos                   (0U)
7356 #define DMA_CSR_IDLEF_Msk                   (0x1UL << DMA_CSR_IDLEF_Pos)            /*!< 0x00000001 */
7357 #define DMA_CSR_IDLEF                       DMA_CSR_IDLEF_Msk                       /*!< Idle flag                          */
7358 #define DMA_CSR_TCF_Pos                     (8U)
7359 #define DMA_CSR_TCF_Msk                     (0x1UL << DMA_CSR_TCF_Pos)              /*!< 0x00000100 */
7360 #define DMA_CSR_TCF                         DMA_CSR_TCF_Msk                         /*!< Transfer complete flag             */
7361 #define DMA_CSR_HTF_Pos                     (9U)
7362 #define DMA_CSR_HTF_Msk                     (0x1UL << DMA_CSR_HTF_Pos)              /*!< 0x00000200 */
7363 #define DMA_CSR_HTF                         DMA_CSR_HTF_Msk                         /*!< Half transfer complete flag        */
7364 #define DMA_CSR_DTEF_Pos                    (10U)
7365 #define DMA_CSR_DTEF_Msk                    (0x1UL << DMA_CSR_DTEF_Pos)             /*!< 0x00000400 */
7366 #define DMA_CSR_DTEF                        DMA_CSR_DTEF_Msk                        /*!< Data transfer error flag           */
7367 #define DMA_CSR_ULEF_Pos                    (11U)
7368 #define DMA_CSR_ULEF_Msk                    (0x1UL << DMA_CSR_ULEF_Pos)             /*!< 0x00000800 */
7369 #define DMA_CSR_ULEF                        DMA_CSR_ULEF_Msk                        /*!< Update linked-list item error flag */
7370 #define DMA_CSR_USEF_Pos                    (12U)
7371 #define DMA_CSR_USEF_Msk                    (0x1UL << DMA_CSR_USEF_Pos)             /*!< 0x00001000 */
7372 #define DMA_CSR_USEF                        DMA_CSR_USEF_Msk                        /*!< User setting error flag            */
7373 #define DMA_CSR_SUSPF_Pos                   (13U)
7374 #define DMA_CSR_SUSPF_Msk                   (0x1UL << DMA_CSR_SUSPF_Pos)            /*!< 0x00002000 */
7375 #define DMA_CSR_SUSPF                       DMA_CSR_SUSPF_Msk                       /*!< Completed suspension flag          */
7376 #define DMA_CSR_TOF_Pos                     (14U)
7377 #define DMA_CSR_TOF_Msk                     (0x1UL << DMA_CSR_TOF_Pos)              /*!< 0x00004000 */
7378 #define DMA_CSR_TOF                         DMA_CSR_TOF_Msk                         /*!< Trigger overrun flag               */
7379 #define DMA_CSR_FIFOL_Pos                   (16U)
7380 #define DMA_CSR_FIFOL_Msk                   (0xFFUL << DMA_CSR_FIFOL_Pos)           /*!< 0x00FF0000 */
7381 #define DMA_CSR_FIFOL                       DMA_CSR_FIFOL_Msk                       /*!< Monitored FIFO level in bytes      */
7382 
7383 /*******************  Bit definition for DMA_CCR register  ********************/
7384 #define DMA_CCR_EN_Pos                      (0U)
7385 #define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)               /*!< 0x00000001 */
7386 #define DMA_CCR_EN                          DMA_CCR_EN_Msk                          /*!< Channel enable                                 */
7387 #define DMA_CCR_RESET_Pos                   (1U)
7388 #define DMA_CCR_RESET_Msk                   (0x1UL << DMA_CCR_RESET_Pos)            /*!< 0x00000002 */
7389 #define DMA_CCR_RESET                       DMA_CCR_RESET_Msk                       /*!< Channel reset                                  */
7390 #define DMA_CCR_SUSP_Pos                    (2U)
7391 #define DMA_CCR_SUSP_Msk                    (0x1UL << DMA_CCR_SUSP_Pos)             /*!< 0x00000004 */
7392 #define DMA_CCR_SUSP                        DMA_CCR_SUSP_Msk                        /*!< Channel suspend                                */
7393 #define DMA_CCR_TCIE_Pos                    (8U)
7394 #define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)             /*!< 0x00000100 */
7395 #define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                        /*!< Transfer complete interrupt enable             */
7396 #define DMA_CCR_HTIE_Pos                    (9U)
7397 #define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)             /*!< 0x00000200 */
7398 #define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                        /*!< Half transfer complete interrupt enable        */
7399 #define DMA_CCR_DTEIE_Pos                   (10U)
7400 #define DMA_CCR_DTEIE_Msk                   (0x1UL << DMA_CCR_DTEIE_Pos)            /*!< 0x00000400 */
7401 #define DMA_CCR_DTEIE                       DMA_CCR_DTEIE_Msk                       /*!< Data transfer error interrupt enable           */
7402 #define DMA_CCR_ULEIE_Pos                   (11U)
7403 #define DMA_CCR_ULEIE_Msk                   (0x1UL << DMA_CCR_ULEIE_Pos)            /*!< 0x00000800 */
7404 #define DMA_CCR_ULEIE                       DMA_CCR_ULEIE_Msk                       /*!< Update linked-list item error interrupt enable */
7405 #define DMA_CCR_USEIE_Pos                   (12U)
7406 #define DMA_CCR_USEIE_Msk                   (0x1UL << DMA_CCR_USEIE_Pos)            /*!< 0x00001000 */
7407 #define DMA_CCR_USEIE                       DMA_CCR_USEIE_Msk                       /*!< User setting error interrupt enable            */
7408 #define DMA_CCR_SUSPIE_Pos                  (13U)
7409 #define DMA_CCR_SUSPIE_Msk                  (0x1UL << DMA_CCR_SUSPIE_Pos)           /*!< 0x00002000 */
7410 #define DMA_CCR_SUSPIE                      DMA_CCR_SUSPIE_Msk                      /*!< Completed suspension interrupt enable          */
7411 #define DMA_CCR_TOIE_Pos                    (14U)
7412 #define DMA_CCR_TOIE_Msk                    (0x1UL << DMA_CCR_TOIE_Pos)             /*!< 0x00004000 */
7413 #define DMA_CCR_TOIE                        DMA_CCR_TOIE_Msk                        /*!< Trigger overrun interrupt enable               */
7414 #define DMA_CCR_LSM_Pos                     (16U)
7415 #define DMA_CCR_LSM_Msk                     (0x1UL << DMA_CCR_LSM_Pos)              /*!< 0x00010000 */
7416 #define DMA_CCR_LSM                         DMA_CCR_LSM_Msk                         /*!< Link step mode                                 */
7417 #define DMA_CCR_LAP_Pos                     (17U)
7418 #define DMA_CCR_LAP_Msk                     (0x1UL << DMA_CCR_LAP_Pos)              /*!< 0x00020000 */
7419 #define DMA_CCR_LAP                         DMA_CCR_LAP_Msk                         /*!< Linked-list allocated port                     */
7420 #define DMA_CCR_PRIO_Pos                    (22U)
7421 #define DMA_CCR_PRIO_Msk                    (0x3UL << DMA_CCR_PRIO_Pos)             /*!< 0x00C00000 */
7422 #define DMA_CCR_PRIO                        DMA_CCR_PRIO_Msk                        /*!< Priority level                                 */
7423 #define DMA_CCR_PRIO_0                      (0x1UL << DMA_CCR_PRIO_Pos)             /*!< 0x00400000 */
7424 #define DMA_CCR_PRIO_1                      (0x2UL << DMA_CCR_PRIO_Pos)             /*!< 0x00800000 */
7425 
7426 /*******************  Bit definition for DMA_CTR1 register  *******************/
7427 #define DMA_CTR1_SDW_LOG2_Pos               (0U)
7428 #define DMA_CTR1_SDW_LOG2_Msk               (0x3UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< 0x00000003 */
7429 #define DMA_CTR1_SDW_LOG2                   DMA_CTR1_SDW_LOG2_Msk                   /*!< Binary logarithm of the source data width of a burst                    */
7430 #define DMA_CTR1_SDW_LOG2_0                 (0x1UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 0 */
7431 #define DMA_CTR1_SDW_LOG2_1                 (0x2UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 1 */
7432 #define DMA_CTR1_SINC_Pos                   (3U)
7433 #define DMA_CTR1_SINC_Msk                   (0x1UL << DMA_CTR1_SINC_Pos)            /*!< 0x00000008 */
7434 #define DMA_CTR1_SINC                       DMA_CTR1_SINC_Msk                       /*!< Source incrementing burst                                               */
7435 #define DMA_CTR1_SBL_1_Pos                  (4U)
7436 #define DMA_CTR1_SBL_1_Msk                  (0x3FUL << DMA_CTR1_SBL_1_Pos)          /*!< 0x000003F0 */
7437 #define DMA_CTR1_SBL_1                      DMA_CTR1_SBL_1_Msk                      /*!< Source burst length minus 1                                             */
7438 #define DMA_CTR1_PAM_Pos                    (11U)
7439 #define DMA_CTR1_PAM_Msk                    (0x3UL << DMA_CTR1_PAM_Pos)             /*!< 0x0001800 */
7440 #define DMA_CTR1_PAM                        DMA_CTR1_PAM_Msk                        /*!< Padding / alignment mode                                                */
7441 #define DMA_CTR1_PAM_0                      (0x1UL << DMA_CTR1_PAM_Pos)             /*!< Bit 0 */
7442 #define DMA_CTR1_PAM_1                      (0x2UL << DMA_CTR1_PAM_Pos)             /*!< Bit 1 */
7443 #define DMA_CTR1_SBX_Pos                    (13U)
7444 #define DMA_CTR1_SBX_Msk                    (0x1UL << DMA_CTR1_SBX_Pos)             /*!< 0x00002000 */
7445 #define DMA_CTR1_SBX                        DMA_CTR1_SBX_Msk                        /*!< Source byte exchange within the unaligned half-word of each source word */
7446 #define DMA_CTR1_SAP_Pos                    (14U)
7447 #define DMA_CTR1_SAP_Msk                    (0x1UL << DMA_CTR1_SAP_Pos)             /*!< 0x00004000 */
7448 #define DMA_CTR1_SAP                        DMA_CTR1_SAP_Msk                        /*!< Source allocated port                                                   */
7449 #define DMA_CTR1_SSEC_Pos                   (15U)
7450 #define DMA_CTR1_SSEC_Msk                   (0x1UL << DMA_CTR1_SSEC_Pos)            /*!< 0x00008000 */
7451 #define DMA_CTR1_SSEC                       DMA_CTR1_SSEC_Msk                       /*!< Security attribute of the DMA transfer from the source                  */
7452 #define DMA_CTR1_DDW_LOG2_Pos               (16U)
7453 #define DMA_CTR1_DDW_LOG2_Msk               (0x3UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< 0x00030000 */
7454 #define DMA_CTR1_DDW_LOG2                   DMA_CTR1_DDW_LOG2_Msk                   /*!< Binary logarithm of the destination data width of a burst               */
7455 #define DMA_CTR1_DDW_LOG2_0                 (0x1UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 0 */
7456 #define DMA_CTR1_DDW_LOG2_1                 (0x2UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 1 */
7457 #define DMA_CTR1_DINC_Pos                   (19U)
7458 #define DMA_CTR1_DINC_Msk                   (0x1UL << DMA_CTR1_DINC_Pos)            /*!< 0x00080000 */
7459 #define DMA_CTR1_DINC                       DMA_CTR1_DINC_Msk                       /*!< Destination incrementing burst                                          */
7460 #define DMA_CTR1_DBL_1_Pos                  (20U)
7461 #define DMA_CTR1_DBL_1_Msk                  (0x3FUL << DMA_CTR1_DBL_1_Pos)          /*!< 0x03F00000 */
7462 #define DMA_CTR1_DBL_1                      DMA_CTR1_DBL_1_Msk                      /*!< Destination burst length minus 1                                        */
7463 #define DMA_CTR1_DBX_Pos                    (26U)
7464 #define DMA_CTR1_DBX_Msk                    (0x1UL << DMA_CTR1_DBX_Pos)             /*!< 0x04000000 */
7465 #define DMA_CTR1_DBX                        DMA_CTR1_DBX_Msk                        /*!< Destination byte exchange                                               */
7466 #define DMA_CTR1_DHX_Pos                    (27U)
7467 #define DMA_CTR1_DHX_Msk                    (0x1UL << DMA_CTR1_DHX_Pos)             /*!< 0x08000000 */
7468 #define DMA_CTR1_DHX                        DMA_CTR1_DHX_Msk                        /*!< Destination half-word exchange                                          */
7469 #define DMA_CTR1_DAP_Pos                    (30U)
7470 #define DMA_CTR1_DAP_Msk                    (0x1UL << DMA_CTR1_DAP_Pos)             /*!< 0x40000000 */
7471 #define DMA_CTR1_DAP                        DMA_CTR1_DAP_Msk                        /*!< Destination allocated port                                              */
7472 #define DMA_CTR1_DSEC_Pos                   (31U)
7473 #define DMA_CTR1_DSEC_Msk                   (0x1UL << DMA_CTR1_DSEC_Pos)            /*!< 0x80000000 */
7474 #define DMA_CTR1_DSEC                       DMA_CTR1_DSEC_Msk                       /*!< Security attribute of the DMA transfer from the destination             */
7475 
7476 /******************  Bit definition for DMA_CTR2 register  *******************/
7477 #define DMA_CTR2_REQSEL_Pos                 (0U)
7478 #define DMA_CTR2_REQSEL_Msk                 (0x7FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000007F */
7479 #define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
7480 #define DMA_CTR2_SWREQ_Pos                  (9U)
7481 #define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000200 */
7482 #define DMA_CTR2_SWREQ                      DMA_CTR2_SWREQ_Msk                      /*!< Software request               */
7483 #define DMA_CTR2_DREQ_Pos                   (10U)
7484 #define DMA_CTR2_DREQ_Msk                   (0x1UL << DMA_CTR2_DREQ_Pos)            /*!< 0x00000400 */
7485 #define DMA_CTR2_DREQ                       DMA_CTR2_DREQ_Msk                       /*!< Destination hardware request   */
7486 #define DMA_CTR2_BREQ_Pos                   (11U)
7487 #define DMA_CTR2_BREQ_Msk                   (0x1UL << DMA_CTR2_BREQ_Pos)            /*!< 0x00000800 */
7488 #define DMA_CTR2_BREQ                       DMA_CTR2_BREQ_Msk                       /*!< Block hardware request         */
7489 #define DMA_CTR2_TRIGM_Pos                  (14U)
7490 #define DMA_CTR2_TRIGM_Msk                  (0x3UL << DMA_CTR2_TRIGM_Pos)           /*!< 0x0000C000 */
7491 #define DMA_CTR2_TRIGM                      DMA_CTR2_TRIGM_Msk                      /*!< Trigger mode                   */
7492 #define DMA_CTR2_TRIGM_0                    (0x1UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 0 */
7493 #define DMA_CTR2_TRIGM_1                    (0x2UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 1 */
7494 #define DMA_CTR2_TRIGSEL_Pos                (16U)
7495 #define DMA_CTR2_TRIGSEL_Msk                (0x7FUL << DMA_CTR2_TRIGSEL_Pos)        /*!< 0x007F0000 */
7496 #define DMA_CTR2_TRIGSEL                    DMA_CTR2_TRIGSEL_Msk                    /*!< Trigger event input selection  */
7497 #define DMA_CTR2_TRIGPOL_Pos                (24U)
7498 #define DMA_CTR2_TRIGPOL_Msk                (0x3UL << DMA_CTR2_TRIGPOL_Pos)         /*!< 0x03000000 */
7499 #define DMA_CTR2_TRIGPOL                    DMA_CTR2_TRIGPOL_Msk                    /*!< Trigger event polarity         */
7500 #define DMA_CTR2_TRIGPOL_0                  (0x1UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 0 */
7501 #define DMA_CTR2_TRIGPOL_1                  (0x2UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 1 */
7502 #define DMA_CTR2_TCEM_Pos                   (30U)
7503 #define DMA_CTR2_TCEM_Msk                   (0x3UL << DMA_CTR2_TCEM_Pos)            /*!< 0xC0000000 */
7504 #define DMA_CTR2_TCEM                       DMA_CTR2_TCEM_Msk                       /*!< Transfer complete event mode   */
7505 #define DMA_CTR2_TCEM_0                     (0x1UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 0 */
7506 #define DMA_CTR2_TCEM_1                     (0x2UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 1 */
7507 
7508 /******************  Bit definition for DMA_CBR1 register  *******************/
7509 #define DMA_CBR1_BNDT_Pos                   (0U)
7510 #define DMA_CBR1_BNDT_Msk                   (0xFFFFUL << DMA_CBR1_BNDT_Pos)         /*!< 0x0000FFFF */
7511 #define DMA_CBR1_BNDT                       DMA_CBR1_BNDT_Msk                       /*!< Block number of data bytes to transfer from the source */
7512 #define DMA_CBR1_BRC_Pos                    (16U)
7513 #define DMA_CBR1_BRC_Msk                    (0x7FFUL << DMA_CBR1_BRC_Pos)           /*!< 0x07FF0000 */
7514 #define DMA_CBR1_BRC                        DMA_CBR1_BRC_Msk                        /*!< Block repeat counter                                   */
7515 #define DMA_CBR1_SDEC_Pos                   (28U)
7516 #define DMA_CBR1_SDEC_Msk                   (0x1UL << DMA_CBR1_SDEC_Pos)            /*!< 0x10000000 */
7517 #define DMA_CBR1_SDEC                       DMA_CBR1_SDEC_Msk                       /*!< Source address decrement                               */
7518 #define DMA_CBR1_DDEC_Pos                   (29U)
7519 #define DMA_CBR1_DDEC_Msk                   (0x1UL << DMA_CBR1_DDEC_Pos)            /*!< 0x20000000 */
7520 #define DMA_CBR1_DDEC                       DMA_CBR1_DDEC_Msk                       /*!< Destination address decrement                          */
7521 #define DMA_CBR1_BRSDEC_Pos                 (30U)
7522 #define DMA_CBR1_BRSDEC_Msk                 (0x1UL << DMA_CBR1_BRSDEC_Pos)          /*!< 0x40000000 */
7523 #define DMA_CBR1_BRSDEC                     DMA_CBR1_BRSDEC_Msk                     /*!< Block repeat source address decrement                  */
7524 #define DMA_CBR1_BRDDEC_Pos                 (31U)
7525 #define DMA_CBR1_BRDDEC_Msk                 (0x1UL << DMA_CBR1_BRDDEC_Pos)          /*!< 0x80000000 */
7526 #define DMA_CBR1_BRDDEC                     DMA_CBR1_BRDDEC_Msk                     /*!< Block repeat destination address decrement             */
7527 
7528 /******************  Bit definition for DMA_CSAR register  ********************/
7529 #define DMA_CSAR_SA_Pos                     (0U)
7530 #define DMA_CSAR_SA_Msk                     (0xFFFFFFFFUL << DMA_CSAR_SA_Pos)       /*!< 0xFFFFFFFF */
7531 #define DMA_CSAR_SA                         DMA_CSAR_SA_Msk                         /*!< Source Address */
7532 
7533 /******************  Bit definition for DMA_CDAR register  *******************/
7534 #define DMA_CDAR_DA_Pos                     (0U)
7535 #define DMA_CDAR_DA_Msk                     (0xFFFFFFFFUL << DMA_CDAR_DA_Pos)       /*!< 0xFFFFFFFF */
7536 #define DMA_CDAR_DA                         DMA_CDAR_DA_Msk                         /*!< Destination address */
7537 
7538 /******************  Bit definition for DMA_CTR3 register  *******************/
7539 #define DMA_CTR3_SAO_Pos                    (0U)
7540 #define DMA_CTR3_SAO_Msk                    (0x1FFFUL << DMA_CTR3_SAO_Pos)          /*!< 0x00001FFF */
7541 #define DMA_CTR3_SAO                        DMA_CTR3_SAO_Msk                        /*!< Source address offset increment      */
7542 #define DMA_CTR3_DAO_Pos                    (16U)
7543 #define DMA_CTR3_DAO_Msk                    (0x1FFFUL << DMA_CTR3_DAO_Pos)          /*!< 0x1FFF0000 */
7544 #define DMA_CTR3_DAO                        DMA_CTR3_DAO_Msk                        /*!< Destination address offset increment */
7545 
7546 /******************  Bit definition for DMA_CBR2 register  *******************/
7547 #define DMA_CBR2_BRSAO_Pos                  (0U)
7548 #define DMA_CBR2_BRSAO_Msk                  (0xFFFFUL << DMA_CBR2_BRSAO_Pos)        /*!< 0x0000FFFF */
7549 #define DMA_CBR2_BRSAO                      DMA_CBR2_BRSAO_Msk                      /*!< Block repeated source address offset      */
7550 #define DMA_CBR2_BRDAO_Pos                  (16U)
7551 #define DMA_CBR2_BRDAO_Msk                  (0xFFFFUL << DMA_CBR2_BRDAO_Pos)        /*!< 0xFFFF0000 */
7552 #define DMA_CBR2_BRDAO                      DMA_CBR2_BRDAO_Msk                      /*!< Block repeated destination address offset */
7553 
7554 /******************  Bit definition for DMA_CLLR register  *******************/
7555 #define DMA_CLLR_LA_Pos                     (2U)
7556 #define DMA_CLLR_LA_Msk                     (0x3FFFUL << DMA_CLLR_LA_Pos)           /*!< 0x0000FFFC */
7557 #define DMA_CLLR_LA                         DMA_CLLR_LA_Msk                         /*!< Pointer to the next linked-list data structure */
7558 #define DMA_CLLR_ULL_Pos                    (16U)
7559 #define DMA_CLLR_ULL_Msk                    (0x1UL << DMA_CLLR_ULL_Pos)             /*!< 0x00010000 */
7560 #define DMA_CLLR_ULL                        DMA_CLLR_ULL_Msk                        /*!< Update link address register from memory       */
7561 #define DMA_CLLR_UB2_Pos                    (25U)
7562 #define DMA_CLLR_UB2_Msk                    (0x1UL << DMA_CLLR_UB2_Pos)             /*!< 0x02000000 */
7563 #define DMA_CLLR_UB2                        DMA_CLLR_UB2_Msk                        /*!< Update block register 2 from memory            */
7564 #define DMA_CLLR_UT3_Pos                    (26U)
7565 #define DMA_CLLR_UT3_Msk                    (0x1UL << DMA_CLLR_UT3_Pos)             /*!< 0x04000000 */
7566 #define DMA_CLLR_UT3                        DMA_CLLR_UT3_Msk                        /*!< Update transfer register 3 from SRAM           */
7567 #define DMA_CLLR_UDA_Pos                    (27U)
7568 #define DMA_CLLR_UDA_Msk                    (0x1UL << DMA_CLLR_UDA_Pos)             /*!< 0x08000000 */
7569 #define DMA_CLLR_UDA                        DMA_CLLR_UDA_Msk                        /*!< Update destination address register from SRAM  */
7570 #define DMA_CLLR_USA_Pos                    (28U)
7571 #define DMA_CLLR_USA_Msk                    (0x1UL << DMA_CLLR_USA_Pos)             /*!< 0x10000000 */
7572 #define DMA_CLLR_USA                        DMA_CLLR_USA_Msk                        /*!< Update source address register from SRAM       */
7573 #define DMA_CLLR_UB1_Pos                    (29U)
7574 #define DMA_CLLR_UB1_Msk                    (0x1UL << DMA_CLLR_UB1_Pos)             /*!< 0x20000000 */
7575 #define DMA_CLLR_UB1                        DMA_CLLR_UB1_Msk                        /*!< Update block register 1 from SRAM              */
7576 #define DMA_CLLR_UT2_Pos                    (30U)
7577 #define DMA_CLLR_UT2_Msk                    (0x1UL << DMA_CLLR_UT2_Pos)             /*!< 0x40000000 */
7578 #define DMA_CLLR_UT2                        DMA_CLLR_UT2_Msk                        /*!< Update transfer register 2 from SRAM           */
7579 #define DMA_CLLR_UT1_Pos                    (31U)
7580 #define DMA_CLLR_UT1_Msk                    (0x1UL << DMA_CLLR_UT1_Pos)             /*!< 0x80000000 */
7581 #define DMA_CLLR_UT1                        DMA_CLLR_UT1_Msk                        /*!< Update transfer register 1 from SRAM           */
7582 
7583 /******************************************************************************/
7584 /*                                                                            */
7585 /*                         AHB Master DMA2D Controller (DMA2D)                */
7586 /*                                                                            */
7587 /******************************************************************************/
7588 
7589 /********************  Bit definition for DMA2D_CR register  ******************/
7590 #define DMA2D_CR_START_Pos                  (0U)
7591 #define DMA2D_CR_START_Msk                  (0x1UL << DMA2D_CR_START_Pos)           /*!< 0x00000001 */
7592 #define DMA2D_CR_START                      DMA2D_CR_START_Msk                      /*!< Start transfer                          */
7593 #define DMA2D_CR_SUSP_Pos                   (1U)
7594 #define DMA2D_CR_SUSP_Msk                   (0x1UL << DMA2D_CR_SUSP_Pos)            /*!< 0x00000002 */
7595 #define DMA2D_CR_SUSP                       DMA2D_CR_SUSP_Msk                       /*!< Suspend transfer                        */
7596 #define DMA2D_CR_ABORT_Pos                  (2U)
7597 #define DMA2D_CR_ABORT_Msk                  (0x1UL << DMA2D_CR_ABORT_Pos)           /*!< 0x00000004 */
7598 #define DMA2D_CR_ABORT                      DMA2D_CR_ABORT_Msk                      /*!< Abort transfer                          */
7599 #define DMA2D_CR_LOM_Pos                    (6U)
7600 #define DMA2D_CR_LOM_Msk                    (0x1UL << DMA2D_CR_LOM_Pos)             /*!< 0x00000040 */
7601 #define DMA2D_CR_LOM                        DMA2D_CR_LOM_Msk
7602 #define DMA2D_CR_TEIE_Pos                   (8U)
7603 #define DMA2D_CR_TEIE_Msk                   (0x1UL << DMA2D_CR_TEIE_Pos)            /*!< 0x00000100 */
7604 #define DMA2D_CR_TEIE                       DMA2D_CR_TEIE_Msk                       /*!< Transfer Error Interrupt Enable         */
7605 #define DMA2D_CR_TCIE_Pos                   (9U)
7606 #define DMA2D_CR_TCIE_Msk                   (0x1UL << DMA2D_CR_TCIE_Pos)            /*!< 0x00000200 */
7607 #define DMA2D_CR_TCIE                       DMA2D_CR_TCIE_Msk                       /*!< Transfer Complete Interrupt Enable      */
7608 #define DMA2D_CR_TWIE_Pos                   (10U)
7609 #define DMA2D_CR_TWIE_Msk                   (0x1UL << DMA2D_CR_TWIE_Pos)            /*!< 0x00000400 */
7610 #define DMA2D_CR_TWIE                       DMA2D_CR_TWIE_Msk                       /*!< Transfer Watermark Interrupt Enable     */
7611 #define DMA2D_CR_CAEIE_Pos                  (11U)
7612 #define DMA2D_CR_CAEIE_Msk                  (0x1UL << DMA2D_CR_CAEIE_Pos)           /*!< 0x00000800 */
7613 #define DMA2D_CR_CAEIE                      DMA2D_CR_CAEIE_Msk                      /*!< CLUT Access Error Interrupt Enable      */
7614 #define DMA2D_CR_CTCIE_Pos                  (12U)
7615 #define DMA2D_CR_CTCIE_Msk                  (0x1UL << DMA2D_CR_CTCIE_Pos)           /*!< 0x00001000 */
7616 #define DMA2D_CR_CTCIE                      DMA2D_CR_CTCIE_Msk                      /*!< CLUT Transfer Complete Interrupt Enable */
7617 #define DMA2D_CR_CEIE_Pos                   (13U)
7618 #define DMA2D_CR_CEIE_Msk                   (0x1UL << DMA2D_CR_CEIE_Pos)            /*!< 0x00002000 */
7619 #define DMA2D_CR_CEIE                       DMA2D_CR_CEIE_Msk                       /*!< Configuration Error Interrupt Enable    */
7620 #define DMA2D_CR_MODE_Pos                   (16U)
7621 #define DMA2D_CR_MODE_Msk                   (0x7UL << DMA2D_CR_MODE_Pos)            /*!< 0x00070000 */
7622 #define DMA2D_CR_MODE                       DMA2D_CR_MODE_Msk                       /*!< DMA2D Mode[2:0]                         */
7623 #define DMA2D_CR_MODE_0                     (0x1UL << DMA2D_CR_MODE_Pos)            /*!< 0x00010000 */
7624 #define DMA2D_CR_MODE_1                     (0x2UL << DMA2D_CR_MODE_Pos)            /*!< 0x00020000 */
7625 #define DMA2D_CR_MODE_2                     (0x4UL << DMA2D_CR_MODE_Pos)            /*!< 0x00040000 */
7626 
7627 /********************  Bit definition for DMA2D_ISR register  *****************/
7628 #define DMA2D_ISR_TEIF_Pos                  (0U)
7629 #define DMA2D_ISR_TEIF_Msk                  (0x1UL << DMA2D_ISR_TEIF_Pos)           /*!< 0x00000001 */
7630 #define DMA2D_ISR_TEIF                      DMA2D_ISR_TEIF_Msk                      /*!< Transfer Error Interrupt Flag         */
7631 #define DMA2D_ISR_TCIF_Pos                  (1U)
7632 #define DMA2D_ISR_TCIF_Msk                  (0x1UL << DMA2D_ISR_TCIF_Pos)           /*!< 0x00000002 */
7633 #define DMA2D_ISR_TCIF                      DMA2D_ISR_TCIF_Msk                      /*!< Transfer Complete Interrupt Flag      */
7634 #define DMA2D_ISR_TWIF_Pos                  (2U)
7635 #define DMA2D_ISR_TWIF_Msk                  (0x1UL << DMA2D_ISR_TWIF_Pos)           /*!< 0x00000004 */
7636 #define DMA2D_ISR_TWIF                      DMA2D_ISR_TWIF_Msk                      /*!< Transfer Watermark Interrupt Flag     */
7637 #define DMA2D_ISR_CAEIF_Pos                 (3U)
7638 #define DMA2D_ISR_CAEIF_Msk                 (0x1UL << DMA2D_ISR_CAEIF_Pos)          /*!< 0x00000008 */
7639 #define DMA2D_ISR_CAEIF                     DMA2D_ISR_CAEIF_Msk                     /*!< CLUT Access Error Interrupt Flag      */
7640 #define DMA2D_ISR_CTCIF_Pos                 (4U)
7641 #define DMA2D_ISR_CTCIF_Msk                 (0x1UL << DMA2D_ISR_CTCIF_Pos)          /*!< 0x00000010 */
7642 #define DMA2D_ISR_CTCIF                     DMA2D_ISR_CTCIF_Msk                     /*!< CLUT Transfer Complete Interrupt Flag */
7643 #define DMA2D_ISR_CEIF_Pos                  (5U)
7644 #define DMA2D_ISR_CEIF_Msk                  (0x1UL << DMA2D_ISR_CEIF_Pos)           /*!< 0x00000020 */
7645 #define DMA2D_ISR_CEIF                      DMA2D_ISR_CEIF_Msk                      /*!< Configuration Error Interrupt Flag    */
7646 
7647 /********************  Bit definition for DMA2D_IFCR register  ****************/
7648 #define DMA2D_IFCR_CTEIF_Pos                (0U)
7649 #define DMA2D_IFCR_CTEIF_Msk                (0x1UL << DMA2D_IFCR_CTEIF_Pos)         /*!< 0x00000001 */
7650 #define DMA2D_IFCR_CTEIF                    DMA2D_IFCR_CTEIF_Msk                    /*!< Clears Transfer Error Interrupt Flag         */
7651 #define DMA2D_IFCR_CTCIF_Pos                (1U)
7652 #define DMA2D_IFCR_CTCIF_Msk                (0x1UL << DMA2D_IFCR_CTCIF_Pos)         /*!< 0x00000002 */
7653 #define DMA2D_IFCR_CTCIF                    DMA2D_IFCR_CTCIF_Msk                    /*!< Clears Transfer Complete Interrupt Flag      */
7654 #define DMA2D_IFCR_CTWIF_Pos                (2U)
7655 #define DMA2D_IFCR_CTWIF_Msk                (0x1UL << DMA2D_IFCR_CTWIF_Pos)         /*!< 0x00000004 */
7656 #define DMA2D_IFCR_CTWIF                    DMA2D_IFCR_CTWIF_Msk                    /*!< Clears Transfer Watermark Interrupt Flag     */
7657 #define DMA2D_IFCR_CAECIF_Pos               (3U)
7658 #define DMA2D_IFCR_CAECIF_Msk               (0x1UL << DMA2D_IFCR_CAECIF_Pos)        /*!< 0x00000008 */
7659 #define DMA2D_IFCR_CAECIF                   DMA2D_IFCR_CAECIF_Msk                   /*!< Clears CLUT Access Error Interrupt Flag      */
7660 #define DMA2D_IFCR_CCTCIF_Pos               (4U)
7661 #define DMA2D_IFCR_CCTCIF_Msk               (0x1UL << DMA2D_IFCR_CCTCIF_Pos)        /*!< 0x00000010 */
7662 #define DMA2D_IFCR_CCTCIF                   DMA2D_IFCR_CCTCIF_Msk                   /*!< Clears CLUT Transfer Complete Interrupt Flag */
7663 #define DMA2D_IFCR_CCEIF_Pos                (5U)
7664 #define DMA2D_IFCR_CCEIF_Msk                (0x1UL << DMA2D_IFCR_CCEIF_Pos)         /*!< 0x00000020 */
7665 #define DMA2D_IFCR_CCEIF                    DMA2D_IFCR_CCEIF_Msk                    /*!< Clears Configuration Error Interrupt Flag    */
7666 
7667 /********************  Bit definition for DMA2D_FGMAR register  ***************/
7668 #define DMA2D_FGMAR_MA_Pos                  (0U)
7669 #define DMA2D_FGMAR_MA_Msk                  (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)    /*!< 0xFFFFFFFF */
7670 #define DMA2D_FGMAR_MA                      DMA2D_FGMAR_MA_Msk                      /*!< Foreground Memory Address */
7671 
7672 /********************  Bit definition for DMA2D_FGOR register  ****************/
7673 #define DMA2D_FGOR_LO_Pos                   (0U)
7674 #define DMA2D_FGOR_LO_Msk                   (0xFFFFUL << DMA2D_FGOR_LO_Pos)         /*!< 0x0000FFFF */
7675 #define DMA2D_FGOR_LO                       DMA2D_FGOR_LO_Msk                       /*!< Line Offset */
7676 
7677 /********************  Bit definition for DMA2D_BGMAR register  ***************/
7678 #define DMA2D_BGMAR_MA_Pos                  (0U)
7679 #define DMA2D_BGMAR_MA_Msk                  (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)    /*!< 0xFFFFFFFF */
7680 #define DMA2D_BGMAR_MA                      DMA2D_BGMAR_MA_Msk                      /*!< Background Memory Address */
7681 
7682 /********************  Bit definition for DMA2D_BGOR register  ****************/
7683 #define DMA2D_BGOR_LO_Pos                   (0U)
7684 #define DMA2D_BGOR_LO_Msk                   (0xFFFFUL << DMA2D_BGOR_LO_Pos)         /*!< 0x0000FFFF */
7685 #define DMA2D_BGOR_LO                       DMA2D_BGOR_LO_Msk                       /*!< Line Offset */
7686 
7687 /********************  Bit definition for DMA2D_FGPFCCR register  *************/
7688 #define DMA2D_FGPFCCR_CM_Pos                (0U)
7689 #define DMA2D_FGPFCCR_CM_Msk                (0xFUL << DMA2D_FGPFCCR_CM_Pos)         /*!< 0x0000000F */
7690 #define DMA2D_FGPFCCR_CM                    DMA2D_FGPFCCR_CM_Msk                    /*!< Input color mode CM[3:0] */
7691 #define DMA2D_FGPFCCR_CM_0                  (0x1UL << DMA2D_FGPFCCR_CM_Pos)         /*!< 0x00000001 */
7692 #define DMA2D_FGPFCCR_CM_1                  (0x2UL << DMA2D_FGPFCCR_CM_Pos)         /*!< 0x00000002 */
7693 #define DMA2D_FGPFCCR_CM_2                  (0x4UL << DMA2D_FGPFCCR_CM_Pos)         /*!< 0x00000004 */
7694 #define DMA2D_FGPFCCR_CM_3                  (0x8UL << DMA2D_FGPFCCR_CM_Pos)         /*!< 0x00000008 */
7695 #define DMA2D_FGPFCCR_CCM_Pos               (4U)
7696 #define DMA2D_FGPFCCR_CCM_Msk               (0x1UL << DMA2D_FGPFCCR_CCM_Pos)        /*!< 0x00000010 */
7697 #define DMA2D_FGPFCCR_CCM                   DMA2D_FGPFCCR_CCM_Msk                   /*!< CLUT Color mode */
7698 #define DMA2D_FGPFCCR_START_Pos             (5U)
7699 #define DMA2D_FGPFCCR_START_Msk             (0x1UL << DMA2D_FGPFCCR_START_Pos)      /*!< 0x00000020 */
7700 #define DMA2D_FGPFCCR_START                 DMA2D_FGPFCCR_START_Msk                 /*!< Start */
7701 #define DMA2D_FGPFCCR_CS_Pos                (8U)
7702 #define DMA2D_FGPFCCR_CS_Msk                (0xFFUL << DMA2D_FGPFCCR_CS_Pos)        /*!< 0x0000FF00 */
7703 #define DMA2D_FGPFCCR_CS                    DMA2D_FGPFCCR_CS_Msk                    /*!< CLUT size */
7704 #define DMA2D_FGPFCCR_AM_Pos                (16U)
7705 #define DMA2D_FGPFCCR_AM_Msk                (0x3UL << DMA2D_FGPFCCR_AM_Pos)         /*!< 0x00030000 */
7706 #define DMA2D_FGPFCCR_AM                    DMA2D_FGPFCCR_AM_Msk                    /*!< Alpha mode AM[1:0] */
7707 #define DMA2D_FGPFCCR_AM_0                  (0x1UL << DMA2D_FGPFCCR_AM_Pos)         /*!< 0x00010000 */
7708 #define DMA2D_FGPFCCR_AM_1                  (0x2UL << DMA2D_FGPFCCR_AM_Pos)         /*!< 0x00020000 */
7709 #define DMA2D_FGPFCCR_CSS_Pos               (18U)
7710 #define DMA2D_FGPFCCR_CSS_Msk               (0x3UL << DMA2D_FGPFCCR_CSS_Pos)        /*!< 0x000C0000 */
7711 #define DMA2D_FGPFCCR_CSS                   DMA2D_FGPFCCR_CSS_Msk                   /* !< Chroma Sub-Sampling */
7712 #define DMA2D_FGPFCCR_CSS_0                 (0x1UL << DMA2D_FGPFCCR_CSS_Pos)        /*!< 0x00040000 */
7713 #define DMA2D_FGPFCCR_CSS_1                 (0x2UL << DMA2D_FGPFCCR_CSS_Pos)        /*!< 0x00080000 */
7714 #define DMA2D_FGPFCCR_AI_Pos                (20U)
7715 #define DMA2D_FGPFCCR_AI_Msk                (0x1UL << DMA2D_FGPFCCR_AI_Pos)         /*!< 0x00100000 */
7716 #define DMA2D_FGPFCCR_AI                    DMA2D_FGPFCCR_AI_Msk                    /*!< Foreground Input Alpha Inverted */
7717 #define DMA2D_FGPFCCR_RBS_Pos               (21U)
7718 #define DMA2D_FGPFCCR_RBS_Msk               (0x1UL << DMA2D_FGPFCCR_RBS_Pos)        /*!< 0x00200000 */
7719 #define DMA2D_FGPFCCR_RBS                   DMA2D_FGPFCCR_RBS_Msk                   /*!< Foreground Input Red Blue Swap */
7720 #define DMA2D_FGPFCCR_ALPHA_Pos             (24U)
7721 #define DMA2D_FGPFCCR_ALPHA_Msk             (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)     /*!< 0xFF000000 */
7722 #define DMA2D_FGPFCCR_ALPHA                 DMA2D_FGPFCCR_ALPHA_Msk                 /*!< Alpha value */
7723 
7724 /********************  Bit definition for DMA2D_FGCOLR register  **************/
7725 #define DMA2D_FGCOLR_BLUE_Pos               (0U)
7726 #define DMA2D_FGCOLR_BLUE_Msk               (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)       /*!< 0x000000FF */
7727 #define DMA2D_FGCOLR_BLUE                   DMA2D_FGCOLR_BLUE_Msk                   /*!< Foreground Blue Value */
7728 #define DMA2D_FGCOLR_GREEN_Pos              (8U)
7729 #define DMA2D_FGCOLR_GREEN_Msk              (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)      /*!< 0x0000FF00 */
7730 #define DMA2D_FGCOLR_GREEN                  DMA2D_FGCOLR_GREEN_Msk                  /*!< Foreground Green Value */
7731 #define DMA2D_FGCOLR_RED_Pos                (16U)
7732 #define DMA2D_FGCOLR_RED_Msk                (0xFFUL << DMA2D_FGCOLR_RED_Pos)        /*!< 0x00FF0000 */
7733 #define DMA2D_FGCOLR_RED                    DMA2D_FGCOLR_RED_Msk                    /*!< Foreground Red Value */
7734 
7735 /********************  Bit definition for DMA2D_BGPFCCR register  *************/
7736 #define DMA2D_BGPFCCR_CM_Pos                (0U)
7737 #define DMA2D_BGPFCCR_CM_Msk                (0xFUL << DMA2D_BGPFCCR_CM_Pos)         /*!< 0x0000000F */
7738 #define DMA2D_BGPFCCR_CM                    DMA2D_BGPFCCR_CM_Msk                    /*!< Input color mode CM[3:0] */
7739 #define DMA2D_BGPFCCR_CM_0                  (0x1UL << DMA2D_BGPFCCR_CM_Pos)         /*!< 0x00000001 */
7740 #define DMA2D_BGPFCCR_CM_1                  (0x2UL << DMA2D_BGPFCCR_CM_Pos)         /*!< 0x00000002 */
7741 #define DMA2D_BGPFCCR_CM_2                  (0x4UL << DMA2D_BGPFCCR_CM_Pos)         /*!< 0x00000004 */
7742 #define DMA2D_BGPFCCR_CM_3                  (0x8UL << DMA2D_BGPFCCR_CM_Pos)         /*!< 0x00000008 */
7743 #define DMA2D_BGPFCCR_CCM_Pos               (4U)
7744 #define DMA2D_BGPFCCR_CCM_Msk               (0x1UL << DMA2D_BGPFCCR_CCM_Pos)        /*!< 0x00000010 */
7745 #define DMA2D_BGPFCCR_CCM                   DMA2D_BGPFCCR_CCM_Msk                   /*!< CLUT Color mode */
7746 #define DMA2D_BGPFCCR_START_Pos             (5U)
7747 #define DMA2D_BGPFCCR_START_Msk             (0x1UL << DMA2D_BGPFCCR_START_Pos)      /*!< 0x00000020 */
7748 #define DMA2D_BGPFCCR_START                 DMA2D_BGPFCCR_START_Msk                 /*!< Start */
7749 #define DMA2D_BGPFCCR_CS_Pos                (8U)
7750 #define DMA2D_BGPFCCR_CS_Msk                (0xFFUL << DMA2D_BGPFCCR_CS_Pos)        /*!< 0x0000FF00 */
7751 #define DMA2D_BGPFCCR_CS                    DMA2D_BGPFCCR_CS_Msk                    /*!< CLUT size */
7752 #define DMA2D_BGPFCCR_AM_Pos                (16U)
7753 #define DMA2D_BGPFCCR_AM_Msk                (0x3UL << DMA2D_BGPFCCR_AM_Pos)         /*!< 0x00030000 */
7754 #define DMA2D_BGPFCCR_AM                    DMA2D_BGPFCCR_AM_Msk                    /*!< Alpha mode AM[1:0] */
7755 #define DMA2D_BGPFCCR_AM_0                  (0x1UL << DMA2D_BGPFCCR_AM_Pos)         /*!< 0x00010000 */
7756 #define DMA2D_BGPFCCR_AM_1                  (0x2UL << DMA2D_BGPFCCR_AM_Pos)         /*!< 0x00020000 */
7757 #define DMA2D_BGPFCCR_AI_Pos                (20U)
7758 #define DMA2D_BGPFCCR_AI_Msk                (0x1UL << DMA2D_BGPFCCR_AI_Pos)         /*!< 0x00100000 */
7759 #define DMA2D_BGPFCCR_AI                    DMA2D_BGPFCCR_AI_Msk                    /*!< background Input Alpha Inverted */
7760 #define DMA2D_BGPFCCR_RBS_Pos               (21U)
7761 #define DMA2D_BGPFCCR_RBS_Msk               (0x1UL << DMA2D_BGPFCCR_RBS_Pos)        /*!< 0x00200000 */
7762 #define DMA2D_BGPFCCR_RBS                   DMA2D_BGPFCCR_RBS_Msk                   /*!< Background Input Red Blue Swap */
7763 #define DMA2D_BGPFCCR_ALPHA_Pos             (24U)
7764 #define DMA2D_BGPFCCR_ALPHA_Msk             (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)     /*!< 0xFF000000 */
7765 #define DMA2D_BGPFCCR_ALPHA                 DMA2D_BGPFCCR_ALPHA_Msk                 /*!< background Input Alpha value */
7766 
7767 /********************  Bit definition for DMA2D_BGCOLR register  **************/
7768 #define DMA2D_BGCOLR_BLUE_Pos               (0U)
7769 #define DMA2D_BGCOLR_BLUE_Msk               (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)       /*!< 0x000000FF */
7770 #define DMA2D_BGCOLR_BLUE                   DMA2D_BGCOLR_BLUE_Msk                   /*!< Background Blue Value */
7771 #define DMA2D_BGCOLR_GREEN_Pos              (8U)
7772 #define DMA2D_BGCOLR_GREEN_Msk              (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)      /*!< 0x0000FF00 */
7773 #define DMA2D_BGCOLR_GREEN                  DMA2D_BGCOLR_GREEN_Msk                  /*!< Background Green Value */
7774 #define DMA2D_BGCOLR_RED_Pos                (16U)
7775 #define DMA2D_BGCOLR_RED_Msk                (0xFFUL << DMA2D_BGCOLR_RED_Pos)        /*!< 0x00FF0000 */
7776 #define DMA2D_BGCOLR_RED                    DMA2D_BGCOLR_RED_Msk                    /*!< Background Red Value */
7777 
7778 /********************  Bit definition for DMA2D_FGCMAR register  **************/
7779 #define DMA2D_FGCMAR_MA_Pos                 (0U)
7780 #define DMA2D_FGCMAR_MA_Msk                 (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)   /*!< 0xFFFFFFFF */
7781 #define DMA2D_FGCMAR_MA                     DMA2D_FGCMAR_MA_Msk                     /*!< Foreground CLUT Memory Address */
7782 
7783 /********************  Bit definition for DMA2D_BGCMAR register  **************/
7784 #define DMA2D_BGCMAR_MA_Pos                 (0U)
7785 #define DMA2D_BGCMAR_MA_Msk                 (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)   /*!< 0xFFFFFFFF */
7786 #define DMA2D_BGCMAR_MA                     DMA2D_BGCMAR_MA_Msk                     /*!< Background CLUT Memory Address */
7787 
7788 /********************  Bit definition for DMA2D_OPFCCR register  **************/
7789 #define DMA2D_OPFCCR_CM_Pos                 (0U)
7790 #define DMA2D_OPFCCR_CM_Msk                 (0x7UL << DMA2D_OPFCCR_CM_Pos)          /*!< 0x00000007 */
7791 #define DMA2D_OPFCCR_CM                     DMA2D_OPFCCR_CM_Msk                     /*!< Output Color mode CM[2:0] */
7792 #define DMA2D_OPFCCR_CM_0                   (0x1UL << DMA2D_OPFCCR_CM_Pos)          /*!< 0x00000001 */
7793 #define DMA2D_OPFCCR_CM_1                   (0x2UL << DMA2D_OPFCCR_CM_Pos)          /*!< 0x00000002 */
7794 #define DMA2D_OPFCCR_CM_2                   (0x4UL << DMA2D_OPFCCR_CM_Pos)          /*!< 0x00000004 */
7795 #define DMA2D_OPFCCR_SB_Pos                 (8U)
7796 #define DMA2D_OPFCCR_SB_Msk                 (0x1UL << DMA2D_OPFCCR_SB_Pos)          /*!< 0x00000100 */
7797 #define DMA2D_OPFCCR_SB                     DMA2D_OPFCCR_SB_Msk                     /*!< Swap Bytes */
7798 #define DMA2D_OPFCCR_AI_Pos                 (20U)
7799 #define DMA2D_OPFCCR_AI_Msk                 (0x1UL << DMA2D_OPFCCR_AI_Pos)          /*!< 0x00100000 */
7800 #define DMA2D_OPFCCR_AI                     DMA2D_OPFCCR_AI_Msk                     /*!< Output Alpha Inverted */
7801 #define DMA2D_OPFCCR_RBS_Pos                (21U)
7802 #define DMA2D_OPFCCR_RBS_Msk                (0x1UL << DMA2D_OPFCCR_RBS_Pos)         /*!< 0x00200000 */
7803 #define DMA2D_OPFCCR_RBS                    DMA2D_OPFCCR_RBS_Msk                    /*!< Output Red Blue Swap */
7804 
7805 /********************  Bit definition for DMA2D_OCOLR register  ***************/
7806 /*!<Mode_ARGB8888/RGB888 */
7807 #define DMA2D_OCOLR_BLUE_1_Pos              (0U)
7808 #define DMA2D_OCOLR_BLUE_1_Msk              (0xFFUL << DMA2D_OCOLR_BLUE_1_Pos)      /*0x000000FFU*/
7809 #define DMA2D_OCOLR_BLUE_1                  DMA2D_OCOLR_BLUE_1_Msk                  /*!< Output BLUE Value */
7810 #define DMA2D_OCOLR_GREEN_1_Pos             (8U)
7811 #define DMA2D_OCOLR_GREEN_1_Msk             (0xFFUL << DMA2D_OCOLR_GREEN_1_Pos)     /*0x0000FF00U)*/
7812 #define DMA2D_OCOLR_GREEN_1                 DMA2D_OCOLR_GREEN_1_Msk                 /*!< Output GREEN Value  */
7813 #define DMA2D_OCOLR_RED_1_Pos               (16U)
7814 #define DMA2D_OCOLR_RED_1_Msk               (0xFFUL << DMA2D_OCOLR_RED_1_Pos)       /*0x00FF0000U */
7815 #define DMA2D_OCOLR_RED_1                   DMA2D_OCOLR_RED_1_Msk                   /*!< Output Red Value */
7816 #define DMA2D_OCOLR_ALPHA_1_Pos             (24U)
7817 #define DMA2D_OCOLR_ALPHA_1_Msk             (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)     /*0xFF000000U*/
7818 #define DMA2D_OCOLR_ALPHA_1                 DMA2D_OCOLR_ALPHA_1_Msk                 /*!< Output Alpha Channel Value */
7819 /*!<Mode_RGB565 */
7820 #define DMA2D_OCOLR_BLUE_2_Pos              (0U)
7821 #define DMA2D_OCOLR_BLUE_2_Msk              (0x1FUL << DMA2D_OCOLR_BLUE_2_Pos)      /*0x0000001FU*/
7822 #define DMA2D_OCOLR_BLUE_2                  DMA2D_OCOLR_BLUE_2_Msk                  /*!< Output BLUE Value */
7823 #define DMA2D_OCOLR_GREEN_2_Pos             (5U)
7824 #define DMA2D_OCOLR_GREEN_2_Msk             (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)     /* 0x000007E0U */
7825 #define DMA2D_OCOLR_GREEN_2                 DMA2D_OCOLR_GREEN_2_Msk                 /*!< Output GREEN Value  */
7826 #define DMA2D_OCOLR_RED_2_Pos               (11U)
7827 #define DMA2D_OCOLR_RED_2_Msk               (0xF8UL << DMA2D_OCOLR_RED_2_Pos)       /*0x0000F800U*/
7828 #define DMA2D_OCOLR_RED_2                   DMA2D_OCOLR_RED_2_Msk                   /*!< Output Red Value */
7829 /*!<Mode_ARGB1555 */
7830 #define DMA2D_OCOLR_BLUE_3_Pos              (0U)
7831 #define DMA2D_OCOLR_BLUE_3_Msk              (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)      /*0x0000001FU*/
7832 #define DMA2D_OCOLR_BLUE_3                  DMA2D_OCOLR_BLUE_3_Msk                  /*!< Output BLUE Value */
7833 #define DMA2D_OCOLR_GREEN_3_Pos             (5U)
7834 #define DMA2D_OCOLR_GREEN_3_Msk             (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)     /*0x000003E0U*/
7835 #define DMA2D_OCOLR_GREEN_3                 DMA2D_OCOLR_GREEN_3_Msk                 /*!< Output GREEN Value  */
7836 #define DMA2D_OCOLR_RED_3_Pos               (10U)
7837 #define DMA2D_OCOLR_RED_3_Msk               (0x7CUL << DMA2D_OCOLR_RED_3_Pos)       /* 0x00007C00U*/
7838 #define DMA2D_OCOLR_RED_3                   DMA2D_OCOLR_RED_3_Msk                   /*!< Output Red Value */
7839 #define DMA2D_OCOLR_ALPHA_3_Pos             (15U)
7840 #define DMA2D_OCOLR_ALPHA_3_Msk             (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)      /*0x00008000U*/
7841 #define DMA2D_OCOLR_ALPHA_3                 DMA2D_OCOLR_ALPHA_3_Msk                 /*!< Output Alpha Channel Value */
7842 /*!<Mode_ARGB4444 */
7843 #define DMA2D_OCOLR_BLUE_4_Pos              (0U)
7844 #define DMA2D_OCOLR_BLUE_4_Msk              (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)       /*0x0000000FU*/
7845 #define DMA2D_OCOLR_BLUE_4                  DMA2D_OCOLR_BLUE_4_Msk                  /*!< Output BLUE Value */
7846 #define DMA2D_OCOLR_GREEN_4_Pos             (4U)
7847 #define DMA2D_OCOLR_GREEN_4_Msk             (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)      /*0x000000F0U*/
7848 #define DMA2D_OCOLR_GREEN_4                 DMA2D_OCOLR_GREEN_4_Msk                 /*!< Output GREEN Value  */
7849 #define DMA2D_OCOLR_RED_4_Pos               (8U)
7850 #define DMA2D_OCOLR_RED_4_Msk               (0xFUL << DMA2D_OCOLR_RED_4_Pos)        /*0x00000F00U*/
7851 #define DMA2D_OCOLR_RED_4                   DMA2D_OCOLR_RED_4_Msk                   /*!< Output Red Value */
7852 #define DMA2D_OCOLR_ALPHA_4_Pos             (12U)
7853 #define DMA2D_OCOLR_ALPHA_4_Msk             (0xF << DMA2D_OCOLR_ALPHA_4_Pos)        /*0x0000F000U*/
7854 #define DMA2D_OCOLR_ALPHA_4                 DMA2D_OCOLR_ALPHA_4_Msk                 /*!< Output Alpha Channel Value */
7855 
7856 /********************  Bit definition for DMA2D_OMAR register  ****************/
7857 #define DMA2D_OMAR_MA_Pos                   (0U)
7858 #define DMA2D_OMAR_MA_Msk                   (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)     /*!< 0xFFFFFFFF */
7859 #define DMA2D_OMAR_MA                       DMA2D_OMAR_MA_Msk                       /*!< Output Memory Address */
7860 
7861 /********************  Bit definition for DMA2D_OOR register  *****************/
7862 #define DMA2D_OOR_LO_Pos                    (0U)
7863 #define DMA2D_OOR_LO_Msk                    (0xFFFFUL << DMA2D_OOR_LO_Pos)          /*!< 0x0000FFFF */
7864 #define DMA2D_OOR_LO                        DMA2D_OOR_LO_Msk                        /*!< Output Line Offset */
7865 
7866 /********************  Bit definition for DMA2D_NLR register  *****************/
7867 #define DMA2D_NLR_NL_Pos                    (0U)
7868 #define DMA2D_NLR_NL_Msk                    (0xFFFFUL << DMA2D_NLR_NL_Pos)          /*!< 0x0000FFFF */
7869 #define DMA2D_NLR_NL                        DMA2D_NLR_NL_Msk                        /*!< Number of Lines */
7870 #define DMA2D_NLR_PL_Pos                    (16U)
7871 #define DMA2D_NLR_PL_Msk                    (0x3FFFUL << DMA2D_NLR_PL_Pos)          /*!< 0x3FFF0000 */
7872 #define DMA2D_NLR_PL                        DMA2D_NLR_PL_Msk                        /*!< Pixel per Lines */
7873 
7874 /********************  Bit definition for DMA2D_LWR register  *****************/
7875 #define DMA2D_LWR_LW_Pos                    (0U)
7876 #define DMA2D_LWR_LW_Msk                    (0xFFFFUL << DMA2D_LWR_LW_Pos)          /*!< 0x0000FFFF */
7877 #define DMA2D_LWR_LW                        DMA2D_LWR_LW_Msk                        /*!< Line Watermark */
7878 
7879 /********************  Bit definition for DMA2D_AMTCR register  ***************/
7880 #define DMA2D_AMTCR_EN_Pos                  (0U)
7881 #define DMA2D_AMTCR_EN_Msk                  (0x1UL << DMA2D_AMTCR_EN_Pos)           /*!< 0x00000001 */
7882 #define DMA2D_AMTCR_EN                      DMA2D_AMTCR_EN_Msk                      /*!< Enable */
7883 #define DMA2D_AMTCR_DT_Pos                  (8U)
7884 #define DMA2D_AMTCR_DT_Msk                  (0xFFUL << DMA2D_AMTCR_DT_Pos)          /*!< 0x0000FF00 */
7885 #define DMA2D_AMTCR_DT                      DMA2D_AMTCR_DT_Msk                      /*!< Dead Time */
7886 
7887 /******************************************************************************/
7888 /*                                                                            */
7889 /*                     Display Serial Interface (DSI)                         */
7890 /*                                                                            */
7891 /******************************************************************************/
7892 /*******************  Bit definition for DSI_VR register  *****************/
7893 #define DSI_VR_Pos                    (0U)
7894 #define DSI_VR_Msk                    (0xFFFFFFFFUL << DSI_VR_Pos)             /*!< 0xFFFFFFFF */
7895 #define DSI_VR                        DSI_VR_Msk                               /*!< DSI Host Version 0x3134312A */
7896 
7897 /*******************  Bit definition for DSI_CR register  *****************/
7898 #define DSI_CR_EN_Pos                 (0U)
7899 #define DSI_CR_EN_Msk                 (0x1UL << DSI_CR_EN_Pos)                 /*!< 0x00000001 */
7900 #define DSI_CR_EN                     DSI_CR_EN_Msk                            /*!< DSI Host power up and reset */
7901 
7902 /*******************  Bit definition for DSI_CCR register  ****************/
7903 #define DSI_CCR_TXECKDIV_Pos          (0U)
7904 #define DSI_CCR_TXECKDIV_Msk          (0xFFUL << DSI_CCR_TXECKDIV_Pos)         /*!< 0x000000FF */
7905 #define DSI_CCR_TXECKDIV              DSI_CCR_TXECKDIV_Msk                     /*!< TX Escape Clock Division */
7906 #define DSI_CCR_TXECKDIV0_Pos         (0U)
7907 #define DSI_CCR_TXECKDIV0_Msk         (0x1UL << DSI_CCR_TXECKDIV0_Pos)         /*!< 0x00000001 */
7908 #define DSI_CCR_TXECKDIV0             DSI_CCR_TXECKDIV0_Msk
7909 #define DSI_CCR_TXECKDIV1_Pos         (1U)
7910 #define DSI_CCR_TXECKDIV1_Msk         (0x1UL << DSI_CCR_TXECKDIV1_Pos)         /*!< 0x00000002 */
7911 #define DSI_CCR_TXECKDIV1             DSI_CCR_TXECKDIV1_Msk
7912 #define DSI_CCR_TXECKDIV2_Pos         (2U)
7913 #define DSI_CCR_TXECKDIV2_Msk         (0x1UL << DSI_CCR_TXECKDIV2_Pos)         /*!< 0x00000004 */
7914 #define DSI_CCR_TXECKDIV2             DSI_CCR_TXECKDIV2_Msk
7915 #define DSI_CCR_TXECKDIV3_Pos         (3U)
7916 #define DSI_CCR_TXECKDIV3_Msk         (0x1UL << DSI_CCR_TXECKDIV3_Pos)         /*!< 0x00000008 */
7917 #define DSI_CCR_TXECKDIV3             DSI_CCR_TXECKDIV3_Msk
7918 #define DSI_CCR_TXECKDIV4_Pos         (4U)
7919 #define DSI_CCR_TXECKDIV4_Msk         (0x1UL << DSI_CCR_TXECKDIV4_Pos)         /*!< 0x00000010 */
7920 #define DSI_CCR_TXECKDIV4             DSI_CCR_TXECKDIV4_Msk
7921 #define DSI_CCR_TXECKDIV5_Pos         (5U)
7922 #define DSI_CCR_TXECKDIV5_Msk         (0x1UL << DSI_CCR_TXECKDIV5_Pos)         /*!< 0x00000020 */
7923 #define DSI_CCR_TXECKDIV5             DSI_CCR_TXECKDIV5_Msk
7924 #define DSI_CCR_TXECKDIV6_Pos         (6U)
7925 #define DSI_CCR_TXECKDIV6_Msk         (0x1UL << DSI_CCR_TXECKDIV6_Pos)         /*!< 0x00000040 */
7926 #define DSI_CCR_TXECKDIV6             DSI_CCR_TXECKDIV6_Msk
7927 #define DSI_CCR_TXECKDIV7_Pos         (7U)
7928 #define DSI_CCR_TXECKDIV7_Msk         (0x1UL << DSI_CCR_TXECKDIV7_Pos)         /*!< 0x00000080 */
7929 #define DSI_CCR_TXECKDIV7             DSI_CCR_TXECKDIV7_Msk
7930 
7931 #define DSI_CCR_TOCKDIV_Pos           (8U)
7932 #define DSI_CCR_TOCKDIV_Msk           (0xFFUL << DSI_CCR_TOCKDIV_Pos)          /*!< 0x0000FF00 */
7933 #define DSI_CCR_TOCKDIV               DSI_CCR_TOCKDIV_Msk                      /*!< Timeout Clock Division */
7934 #define DSI_CCR_TOCKDIV0_Pos          (8U)
7935 #define DSI_CCR_TOCKDIV0_Msk          (0x1UL << DSI_CCR_TOCKDIV0_Pos)          /*!< 0x00000100 */
7936 #define DSI_CCR_TOCKDIV0              DSI_CCR_TOCKDIV0_Msk
7937 #define DSI_CCR_TOCKDIV1_Pos          (9U)
7938 #define DSI_CCR_TOCKDIV1_Msk          (0x1UL << DSI_CCR_TOCKDIV1_Pos)          /*!< 0x00000200 */
7939 #define DSI_CCR_TOCKDIV1              DSI_CCR_TOCKDIV1_Msk
7940 #define DSI_CCR_TOCKDIV2_Pos          (10U)
7941 #define DSI_CCR_TOCKDIV2_Msk          (0x1UL << DSI_CCR_TOCKDIV2_Pos)          /*!< 0x00000400 */
7942 #define DSI_CCR_TOCKDIV2              DSI_CCR_TOCKDIV2_Msk
7943 #define DSI_CCR_TOCKDIV3_Pos          (11U)
7944 #define DSI_CCR_TOCKDIV3_Msk          (0x1UL << DSI_CCR_TOCKDIV3_Pos)          /*!< 0x00000800 */
7945 #define DSI_CCR_TOCKDIV3              DSI_CCR_TOCKDIV3_Msk
7946 #define DSI_CCR_TOCKDIV4_Pos          (12U)
7947 #define DSI_CCR_TOCKDIV4_Msk          (0x1UL << DSI_CCR_TOCKDIV4_Pos)          /*!< 0x00001000 */
7948 #define DSI_CCR_TOCKDIV4              DSI_CCR_TOCKDIV4_Msk
7949 #define DSI_CCR_TOCKDIV5_Pos          (13U)
7950 #define DSI_CCR_TOCKDIV5_Msk          (0x1UL << DSI_CCR_TOCKDIV5_Pos)          /*!< 0x00002000 */
7951 #define DSI_CCR_TOCKDIV5              DSI_CCR_TOCKDIV5_Msk
7952 #define DSI_CCR_TOCKDIV6_Pos          (14U)
7953 #define DSI_CCR_TOCKDIV6_Msk          (0x1UL << DSI_CCR_TOCKDIV6_Pos)          /*!< 0x00004000 */
7954 #define DSI_CCR_TOCKDIV6              DSI_CCR_TOCKDIV6_Msk
7955 #define DSI_CCR_TOCKDIV7_Pos          (15U)
7956 #define DSI_CCR_TOCKDIV7_Msk          (0x1UL << DSI_CCR_TOCKDIV7_Pos)          /*!< 0x00008000 */
7957 #define DSI_CCR_TOCKDIV7              DSI_CCR_TOCKDIV7_Msk
7958 
7959 /*******************  Bit definition for DSI_LVCIDR register  *************/
7960 #define DSI_LVCIDR_VCID_Pos           (0U)
7961 #define DSI_LVCIDR_VCID_Msk           (0x3UL << DSI_LVCIDR_VCID_Pos)           /*!< 0x00000003 */
7962 #define DSI_LVCIDR_VCID               DSI_LVCIDR_VCID_Msk                      /*!< Virtual Channel ID */
7963 #define DSI_LVCIDR_VCID0_Pos          (0U)
7964 #define DSI_LVCIDR_VCID0_Msk          (0x1UL << DSI_LVCIDR_VCID0_Pos)          /*!< 0x00000001 */
7965 #define DSI_LVCIDR_VCID0              DSI_LVCIDR_VCID0_Msk
7966 #define DSI_LVCIDR_VCID1_Pos          (1U)
7967 #define DSI_LVCIDR_VCID1_Msk          (0x1UL << DSI_LVCIDR_VCID1_Pos)          /*!< 0x00000002 */
7968 #define DSI_LVCIDR_VCID1              DSI_LVCIDR_VCID1_Msk
7969 
7970 /*******************  Bit definition for DSI_LCOLCR register  *************/
7971 #define DSI_LCOLCR_COLC_Pos           (0U)
7972 #define DSI_LCOLCR_COLC_Msk           (0xFUL << DSI_LCOLCR_COLC_Pos)           /*!< 0x0000000F */
7973 #define DSI_LCOLCR_COLC               DSI_LCOLCR_COLC_Msk                      /*!< Color Coding */
7974 #define DSI_LCOLCR_COLC0_Pos          (0U)
7975 #define DSI_LCOLCR_COLC0_Msk          (0x1UL << DSI_LCOLCR_COLC0_Pos)          /*!< 0x00000001 */
7976 #define DSI_LCOLCR_COLC0              DSI_LCOLCR_COLC0_Msk
7977 #define DSI_LCOLCR_COLC1_Pos          (1U)
7978 #define DSI_LCOLCR_COLC1_Msk          (0x1UL << DSI_LCOLCR_COLC1_Pos)          /*!< 0x00000020 */
7979 #define DSI_LCOLCR_COLC1              DSI_LCOLCR_COLC1_Msk
7980 #define DSI_LCOLCR_COLC2_Pos          (2U)
7981 #define DSI_LCOLCR_COLC2_Msk          (0x1UL << DSI_LCOLCR_COLC2_Pos)          /*!< 0x00000040 */
7982 #define DSI_LCOLCR_COLC2              DSI_LCOLCR_COLC2_Msk
7983 #define DSI_LCOLCR_COLC3_Pos          (3U)
7984 #define DSI_LCOLCR_COLC3_Msk          (0x1UL << DSI_LCOLCR_COLC3_Pos)          /*!< 0x00000080 */
7985 #define DSI_LCOLCR_COLC3              DSI_LCOLCR_COLC3_Msk
7986 
7987 #define DSI_LCOLCR_LPE_Pos            (8U)
7988 #define DSI_LCOLCR_LPE_Msk            (0x1UL << DSI_LCOLCR_LPE_Pos)            /*!< 0x00000100 */
7989 #define DSI_LCOLCR_LPE                DSI_LCOLCR_LPE_Msk                       /*!< Loosely Packet Enable */
7990 
7991 /*******************  Bit definition for DSI_LPCR register  ***************/
7992 #define DSI_LPCR_DEP_Pos              (0U)
7993 #define DSI_LPCR_DEP_Msk              (0x1UL << DSI_LPCR_DEP_Pos)              /*!< 0x00000001 */
7994 #define DSI_LPCR_DEP                  DSI_LPCR_DEP_Msk                         /*!< Data Enable Polarity */
7995 #define DSI_LPCR_VSP_Pos              (1U)
7996 #define DSI_LPCR_VSP_Msk              (0x1UL << DSI_LPCR_VSP_Pos)              /*!< 0x00000002 */
7997 #define DSI_LPCR_VSP                  DSI_LPCR_VSP_Msk                         /*!< VSYNC Polarity */
7998 #define DSI_LPCR_HSP_Pos              (2U)
7999 #define DSI_LPCR_HSP_Msk              (0x1UL << DSI_LPCR_HSP_Pos)              /*!< 0x00000004 */
8000 #define DSI_LPCR_HSP                  DSI_LPCR_HSP_Msk                         /*!< HSYNC Polarity */
8001 
8002 /*******************  Bit definition for DSI_LPMCR register  **************/
8003 #define DSI_LPMCR_VLPSIZE_Pos         (0U)
8004 #define DSI_LPMCR_VLPSIZE_Msk         (0xFFUL << DSI_LPMCR_VLPSIZE_Pos)        /*!< 0x000000FF */
8005 #define DSI_LPMCR_VLPSIZE             DSI_LPMCR_VLPSIZE_Msk                    /*!< VACT Largest Packet Size */
8006 #define DSI_LPMCR_VLPSIZE0_Pos        (0U)
8007 #define DSI_LPMCR_VLPSIZE0_Msk        (0x1UL << DSI_LPMCR_VLPSIZE0_Pos)        /*!< 0x00000001 */
8008 #define DSI_LPMCR_VLPSIZE0            DSI_LPMCR_VLPSIZE0_Msk
8009 #define DSI_LPMCR_VLPSIZE1_Pos        (1U)
8010 #define DSI_LPMCR_VLPSIZE1_Msk        (0x1UL << DSI_LPMCR_VLPSIZE1_Pos)        /*!< 0x00000002 */
8011 #define DSI_LPMCR_VLPSIZE1            DSI_LPMCR_VLPSIZE1_Msk
8012 #define DSI_LPMCR_VLPSIZE2_Pos        (2U)
8013 #define DSI_LPMCR_VLPSIZE2_Msk        (0x1UL << DSI_LPMCR_VLPSIZE2_Pos)        /*!< 0x00000004 */
8014 #define DSI_LPMCR_VLPSIZE2            DSI_LPMCR_VLPSIZE2_Msk
8015 #define DSI_LPMCR_VLPSIZE3_Pos        (3U)
8016 #define DSI_LPMCR_VLPSIZE3_Msk        (0x1UL << DSI_LPMCR_VLPSIZE3_Pos)        /*!< 0x00000008 */
8017 #define DSI_LPMCR_VLPSIZE3            DSI_LPMCR_VLPSIZE3_Msk
8018 #define DSI_LPMCR_VLPSIZE4_Pos        (4U)
8019 #define DSI_LPMCR_VLPSIZE4_Msk        (0x1UL << DSI_LPMCR_VLPSIZE4_Pos)        /*!< 0x00000010 */
8020 #define DSI_LPMCR_VLPSIZE4            DSI_LPMCR_VLPSIZE4_Msk
8021 #define DSI_LPMCR_VLPSIZE5_Pos        (5U)
8022 #define DSI_LPMCR_VLPSIZE5_Msk        (0x1UL << DSI_LPMCR_VLPSIZE5_Pos)        /*!< 0x00000020 */
8023 #define DSI_LPMCR_VLPSIZE5            DSI_LPMCR_VLPSIZE5_Msk
8024 #define DSI_LPMCR_VLPSIZE6_Pos        (6U)
8025 #define DSI_LPMCR_VLPSIZE6_Msk        (0x1UL << DSI_LPMCR_VLPSIZE6_Pos)        /*!< 0x00000040 */
8026 #define DSI_LPMCR_VLPSIZE6            DSI_LPMCR_VLPSIZE6_Msk
8027 #define DSI_LPMCR_VLPSIZE7_Pos        (7U)
8028 #define DSI_LPMCR_VLPSIZE7_Msk        (0x1UL << DSI_LPMCR_VLPSIZE7_Pos)        /*!< 0x00000080 */
8029 #define DSI_LPMCR_VLPSIZE7            DSI_LPMCR_VLPSIZE7_Msk
8030 
8031 #define DSI_LPMCR_LPSIZE_Pos          (16U)
8032 #define DSI_LPMCR_LPSIZE_Msk          (0xFFUL << DSI_LPMCR_LPSIZE_Pos)         /*!< 0x00FF0000 */
8033 #define DSI_LPMCR_LPSIZE              DSI_LPMCR_LPSIZE_Msk                     /*!< Largest Packet Size */
8034 #define DSI_LPMCR_LPSIZE0_Pos         (16U)
8035 #define DSI_LPMCR_LPSIZE0_Msk         (0x1UL << DSI_LPMCR_LPSIZE0_Pos)         /*!< 0x00010000 */
8036 #define DSI_LPMCR_LPSIZE0             DSI_LPMCR_LPSIZE0_Msk
8037 #define DSI_LPMCR_LPSIZE1_Pos         (17U)
8038 #define DSI_LPMCR_LPSIZE1_Msk         (0x1UL << DSI_LPMCR_LPSIZE1_Pos)         /*!< 0x00020000 */
8039 #define DSI_LPMCR_LPSIZE1             DSI_LPMCR_LPSIZE1_Msk
8040 #define DSI_LPMCR_LPSIZE2_Pos         (18U)
8041 #define DSI_LPMCR_LPSIZE2_Msk         (0x1UL << DSI_LPMCR_LPSIZE2_Pos)         /*!< 0x00040000 */
8042 #define DSI_LPMCR_LPSIZE2             DSI_LPMCR_LPSIZE2_Msk
8043 #define DSI_LPMCR_LPSIZE3_Pos         (19U)
8044 #define DSI_LPMCR_LPSIZE3_Msk         (0x1UL << DSI_LPMCR_LPSIZE3_Pos)         /*!< 0x00080000 */
8045 #define DSI_LPMCR_LPSIZE3             DSI_LPMCR_LPSIZE3_Msk
8046 #define DSI_LPMCR_LPSIZE4_Pos         (20U)
8047 #define DSI_LPMCR_LPSIZE4_Msk         (0x1UL << DSI_LPMCR_LPSIZE4_Pos)         /*!< 0x00100000 */
8048 #define DSI_LPMCR_LPSIZE4             DSI_LPMCR_LPSIZE4_Msk
8049 #define DSI_LPMCR_LPSIZE5_Pos         (21U)
8050 #define DSI_LPMCR_LPSIZE5_Msk         (0x1UL << DSI_LPMCR_LPSIZE5_Pos)         /*!< 0x00200000 */
8051 #define DSI_LPMCR_LPSIZE5             DSI_LPMCR_LPSIZE5_Msk
8052 #define DSI_LPMCR_LPSIZE6_Pos         (22U)
8053 #define DSI_LPMCR_LPSIZE6_Msk         (0x1UL << DSI_LPMCR_LPSIZE6_Pos)         /*!< 0x00400000 */
8054 #define DSI_LPMCR_LPSIZE6             DSI_LPMCR_LPSIZE6_Msk
8055 #define DSI_LPMCR_LPSIZE7_Pos         (23U)
8056 #define DSI_LPMCR_LPSIZE7_Msk         (0x1UL << DSI_LPMCR_LPSIZE7_Pos)         /*!< 0x00800000 */
8057 #define DSI_LPMCR_LPSIZE7             DSI_LPMCR_LPSIZE7_Msk
8058 
8059 /*******************  Bit definition for DSI_PCR register  ****************/
8060 #define DSI_PCR_ETTXE_Pos             (0U)
8061 #define DSI_PCR_ETTXE_Msk             (0x1UL << DSI_PCR_ETTXE_Pos)             /*!< 0x00000001 */
8062 #define DSI_PCR_ETTXE                 DSI_PCR_ETTXE_Msk                        /*!< EoTp Transmission Enable */
8063 #define DSI_PCR_ETRXE_Pos             (1U)
8064 #define DSI_PCR_ETRXE_Msk             (0x1UL << DSI_PCR_ETRXE_Pos)             /*!< 0x00000002 */
8065 #define DSI_PCR_ETRXE                 DSI_PCR_ETRXE_Msk                        /*!< EoTp Reception Enable */
8066 #define DSI_PCR_BTAE_Pos              (2U)
8067 #define DSI_PCR_BTAE_Msk              (0x1UL << DSI_PCR_BTAE_Pos)              /*!< 0x00000004 */
8068 #define DSI_PCR_BTAE                  DSI_PCR_BTAE_Msk                         /*!< Bus Turn Around Enable */
8069 #define DSI_PCR_ECCRXE_Pos            (3U)
8070 #define DSI_PCR_ECCRXE_Msk            (0x1UL << DSI_PCR_ECCRXE_Pos)            /*!< 0x00000008 */
8071 #define DSI_PCR_ECCRXE                DSI_PCR_ECCRXE_Msk                       /*!< ECC Reception Enable */
8072 #define DSI_PCR_CRCRXE_Pos            (4U)
8073 #define DSI_PCR_CRCRXE_Msk            (0x1UL << DSI_PCR_CRCRXE_Pos)            /*!< 0x00000010 */
8074 #define DSI_PCR_CRCRXE                DSI_PCR_CRCRXE_Msk                       /*!< CRC Reception Enable */
8075 #define DSI_PCR_ETTXLPE_Pos           (5U)
8076 #define DSI_PCR_ETTXLPE_Msk           (0x1UL << DSI_PCR_ETTXLPE_Pos)           /*!< 0x00000020 */
8077 #define DSI_PCR_ETTXLPE               DSI_PCR_ETTXLPE_Msk                      /*!< EoTp Transmission in Low-Power Enable */
8078 
8079 /*******************  Bit definition for DSI_GVCIDR register  *************/
8080 #define DSI_GVCIDR_VCIDRX_Pos         (0U)
8081 #define DSI_GVCIDR_VCIDRX_Msk         (0x3UL << DSI_GVCIDR_VCIDRX_Pos)         /*!< 0x00000003 */
8082 #define DSI_GVCIDR_VCIDRX             DSI_GVCIDR_VCIDRX_Msk                    /*!< Virtual Channel ID for Reception */
8083 #define DSI_GVCIDR_VCIDRX0_Pos        (0U)
8084 #define DSI_GVCIDR_VCIDRX0_Msk        (0x1UL << DSI_GVCIDR_VCIDRX0_Pos)        /*!< 0x00000001 */
8085 #define DSI_GVCIDR_VCIDRX0            DSI_GVCIDR_VCIDRX0_Msk
8086 #define DSI_GVCIDR_VCIDRX1_Pos        (1U)
8087 #define DSI_GVCIDR_VCIDRX1_Msk        (0x1UL << DSI_GVCIDR_VCIDRX1_Pos)        /*!< 0x00000002 */
8088 #define DSI_GVCIDR_VCIDRX1            DSI_GVCIDR_VCIDRX1_Msk
8089 #define DSI_GVCIDR_VCIDTX_Pos         (16U)
8090 #define DSI_GVCIDR_VCIDTX_Msk         (0x3UL << DSI_GVCIDR_VCIDTX_Pos)         /*!< 0x00030000 */
8091 #define DSI_GVCIDR_VCIDTX             DSI_GVCIDR_VCIDTX_Msk                    /*!< Virtual Channel ID for Transmission */
8092 #define DSI_GVCIDR_VCIDTX0_Pos        (16U)
8093 #define DSI_GVCIDR_VCIDTX0_Msk        (0x1UL << DSI_GVCIDR_VCIDTX0_Pos)        /*!< 0x00010000 */
8094 #define DSI_GVCIDR_VCIDTX0            DSI_GVCIDR_VCIDTX0_Msk
8095 #define DSI_GVCIDR_VCIDTX1_Pos        (17U)
8096 #define DSI_GVCIDR_VCIDTX1_Msk        (0x1UL << DSI_GVCIDR_VCIDRT1_Pos)        /*!< 0x00020000 */
8097 #define DSI_GVCIDR_VCIDTX1            DSI_GVCIDR_VCIDRT1_Msk
8098 
8099 /*******************  Bit definition for DSI_MCR register  ****************/
8100 #define DSI_MCR_CMDM_Pos              (0U)
8101 #define DSI_MCR_CMDM_Msk              (0x1UL << DSI_MCR_CMDM_Pos)              /*!< 0x00000001 */
8102 #define DSI_MCR_CMDM                  DSI_MCR_CMDM_Msk                         /*!< Command Mode */
8103 
8104 /*******************  Bit definition for DSI_VMCR register  ***************/
8105 #define DSI_VMCR_VMT_Pos              (0U)
8106 #define DSI_VMCR_VMT_Msk              (0x3UL << DSI_VMCR_VMT_Pos)              /*!< 0x00000003 */
8107 #define DSI_VMCR_VMT                  DSI_VMCR_VMT_Msk                         /*!< Video Mode Type */
8108 #define DSI_VMCR_VMT0_Pos             (0U)
8109 #define DSI_VMCR_VMT0_Msk             (0x1UL << DSI_VMCR_VMT0_Pos)             /*!< 0x00000001 */
8110 #define DSI_VMCR_VMT0                 DSI_VMCR_VMT0_Msk
8111 #define DSI_VMCR_VMT1_Pos             (1U)
8112 #define DSI_VMCR_VMT1_Msk             (0x1UL << DSI_VMCR_VMT1_Pos)             /*!< 0x00000002 */
8113 #define DSI_VMCR_VMT1                 DSI_VMCR_VMT1_Msk
8114 
8115 #define DSI_VMCR_LPVSAE_Pos           (8U)
8116 #define DSI_VMCR_LPVSAE_Msk           (0x1UL << DSI_VMCR_LPVSAE_Pos)           /*!< 0x00000100 */
8117 #define DSI_VMCR_LPVSAE               DSI_VMCR_LPVSAE_Msk                      /*!< Low-Power Vertical Sync Active Enable */
8118 #define DSI_VMCR_LPVBPE_Pos           (9U)
8119 #define DSI_VMCR_LPVBPE_Msk           (0x1UL << DSI_VMCR_LPVBPE_Pos)           /*!< 0x00000200 */
8120 #define DSI_VMCR_LPVBPE               DSI_VMCR_LPVBPE_Msk                      /*!< Low-power Vertical Back-Porch Enable */
8121 #define DSI_VMCR_LPVFPE_Pos           (10U)
8122 #define DSI_VMCR_LPVFPE_Msk           (0x1UL << DSI_VMCR_LPVFPE_Pos)           /*!< 0x00000400 */
8123 #define DSI_VMCR_LPVFPE               DSI_VMCR_LPVFPE_Msk                      /*!< Low-power Vertical Front-porch Enable */
8124 #define DSI_VMCR_LPVAE_Pos            (11U)
8125 #define DSI_VMCR_LPVAE_Msk            (0x1UL << DSI_VMCR_LPVAE_Pos)            /*!< 0x00000800 */
8126 #define DSI_VMCR_LPVAE                DSI_VMCR_LPVAE_Msk                       /*!< Low-Power Vertical Active Enable */
8127 #define DSI_VMCR_LPHBPE_Pos           (12U)
8128 #define DSI_VMCR_LPHBPE_Msk           (0x1UL << DSI_VMCR_LPHBPE_Pos)           /*!< 0x00001000 */
8129 #define DSI_VMCR_LPHBPE               DSI_VMCR_LPHBPE_Msk                      /*!< Low-Power Horizontal Back-Porch Enable */
8130 #define DSI_VMCR_LPHFPE_Pos           (13U)
8131 #define DSI_VMCR_LPHFPE_Msk           (0x1UL << DSI_VMCR_LPHFPE_Pos)           /*!< 0x00002000 */
8132 #define DSI_VMCR_LPHFPE               DSI_VMCR_LPHFPE_Msk                      /*!< Low-Power Horizontal Front-Porch Enable */
8133 #define DSI_VMCR_FBTAAE_Pos           (14U)
8134 #define DSI_VMCR_FBTAAE_Msk           (0x1UL << DSI_VMCR_FBTAAE_Pos)           /*!< 0x00004000 */
8135 #define DSI_VMCR_FBTAAE               DSI_VMCR_FBTAAE_Msk                      /*!< Frame Bus-Turn-Around Acknowledge Enable */
8136 #define DSI_VMCR_LPCE_Pos             (15U)
8137 #define DSI_VMCR_LPCE_Msk             (0x1UL << DSI_VMCR_LPCE_Pos)             /*!< 0x00008000 */
8138 #define DSI_VMCR_LPCE                 DSI_VMCR_LPCE_Msk                        /*!< Low-Power Command Enable */
8139 #define DSI_VMCR_PGE_Pos              (16U)
8140 #define DSI_VMCR_PGE_Msk              (0x1UL << DSI_VMCR_PGE_Pos)              /*!< 0x00010000 */
8141 #define DSI_VMCR_PGE                  DSI_VMCR_PGE_Msk                         /*!< Pattern Generator Enable */
8142 #define DSI_VMCR_PGM_Pos              (20U)
8143 #define DSI_VMCR_PGM_Msk              (0x1UL << DSI_VMCR_PGM_Pos)              /*!< 0x00100000 */
8144 #define DSI_VMCR_PGM                  DSI_VMCR_PGM_Msk                         /*!< Pattern Generator Mode */
8145 #define DSI_VMCR_PGO_Pos              (24U)
8146 #define DSI_VMCR_PGO_Msk              (0x1UL << DSI_VMCR_PGO_Pos)              /*!< 0x01000000 */
8147 #define DSI_VMCR_PGO                  DSI_VMCR_PGO_Msk                         /*!< Pattern Generator Orientation */
8148 
8149 /*******************  Bit definition for DSI_VPCR register  ***************/
8150 #define DSI_VPCR_VPSIZE_Pos           (0U)
8151 #define DSI_VPCR_VPSIZE_Msk           (0x3FFFUL << DSI_VPCR_VPSIZE_Pos)        /*!< 0x00003FFF */
8152 #define DSI_VPCR_VPSIZE               DSI_VPCR_VPSIZE_Msk                      /*!< Video Packet Size */
8153 #define DSI_VPCR_VPSIZE0_Pos          (0U)
8154 #define DSI_VPCR_VPSIZE0_Msk          (0x1UL << DSI_VPCR_VPSIZE0_Pos)          /*!< 0x00000001 */
8155 #define DSI_VPCR_VPSIZE0              DSI_VPCR_VPSIZE0_Msk
8156 #define DSI_VPCR_VPSIZE1_Pos          (1U)
8157 #define DSI_VPCR_VPSIZE1_Msk          (0x1UL << DSI_VPCR_VPSIZE1_Pos)          /*!< 0x00000002 */
8158 #define DSI_VPCR_VPSIZE1              DSI_VPCR_VPSIZE1_Msk
8159 #define DSI_VPCR_VPSIZE2_Pos          (2U)
8160 #define DSI_VPCR_VPSIZE2_Msk          (0x1UL << DSI_VPCR_VPSIZE2_Pos)          /*!< 0x00000004 */
8161 #define DSI_VPCR_VPSIZE2              DSI_VPCR_VPSIZE2_Msk
8162 #define DSI_VPCR_VPSIZE3_Pos          (3U)
8163 #define DSI_VPCR_VPSIZE3_Msk          (0x1UL << DSI_VPCR_VPSIZE3_Pos)          /*!< 0x00000008 */
8164 #define DSI_VPCR_VPSIZE3              DSI_VPCR_VPSIZE3_Msk
8165 #define DSI_VPCR_VPSIZE4_Pos          (4U)
8166 #define DSI_VPCR_VPSIZE4_Msk          (0x1UL << DSI_VPCR_VPSIZE4_Pos)          /*!< 0x00000010 */
8167 #define DSI_VPCR_VPSIZE4              DSI_VPCR_VPSIZE4_Msk
8168 #define DSI_VPCR_VPSIZE5_Pos          (5U)
8169 #define DSI_VPCR_VPSIZE5_Msk          (0x1UL << DSI_VPCR_VPSIZE5_Pos)          /*!< 0x00000020 */
8170 #define DSI_VPCR_VPSIZE5              DSI_VPCR_VPSIZE5_Msk
8171 #define DSI_VPCR_VPSIZE6_Pos          (6U)
8172 #define DSI_VPCR_VPSIZE6_Msk          (0x1UL << DSI_VPCR_VPSIZE6_Pos)          /*!< 0x00000040 */
8173 #define DSI_VPCR_VPSIZE6              DSI_VPCR_VPSIZE6_Msk
8174 #define DSI_VPCR_VPSIZE7_Pos          (7U)
8175 #define DSI_VPCR_VPSIZE7_Msk          (0x1UL << DSI_VPCR_VPSIZE7_Pos)          /*!< 0x00000080 */
8176 #define DSI_VPCR_VPSIZE7              DSI_VPCR_VPSIZE7_Msk
8177 #define DSI_VPCR_VPSIZE8_Pos          (8U)
8178 #define DSI_VPCR_VPSIZE8_Msk          (0x1UL << DSI_VPCR_VPSIZE8_Pos)          /*!< 0x00000100 */
8179 #define DSI_VPCR_VPSIZE8              DSI_VPCR_VPSIZE8_Msk
8180 #define DSI_VPCR_VPSIZE9_Pos          (9U)
8181 #define DSI_VPCR_VPSIZE9_Msk          (0x1UL << DSI_VPCR_VPSIZE9_Pos)          /*!< 0x00000200 */
8182 #define DSI_VPCR_VPSIZE9              DSI_VPCR_VPSIZE9_Msk
8183 #define DSI_VPCR_VPSIZE10_Pos         (10U)
8184 #define DSI_VPCR_VPSIZE10_Msk         (0x1UL << DSI_VPCR_VPSIZE10_Pos)         /*!< 0x00000400 */
8185 #define DSI_VPCR_VPSIZE10             DSI_VPCR_VPSIZE10_Msk
8186 #define DSI_VPCR_VPSIZE11_Pos         (11U)
8187 #define DSI_VPCR_VPSIZE11_Msk         (0x1UL << DSI_VPCR_VPSIZE11_Pos)         /*!< 0x00000800 */
8188 #define DSI_VPCR_VPSIZE11             DSI_VPCR_VPSIZE11_Msk
8189 #define DSI_VPCR_VPSIZE12_Pos         (12U)
8190 #define DSI_VPCR_VPSIZE12_Msk         (0x1UL << DSI_VPCR_VPSIZE12_Pos)         /*!< 0x00001000 */
8191 #define DSI_VPCR_VPSIZE12             DSI_VPCR_VPSIZE12_Msk
8192 #define DSI_VPCR_VPSIZE13_Pos         (13U)
8193 #define DSI_VPCR_VPSIZE13_Msk         (0x1UL << DSI_VPCR_VPSIZE13_Pos)         /*!< 0x00002000 */
8194 #define DSI_VPCR_VPSIZE13             DSI_VPCR_VPSIZE13_Msk
8195 
8196 /*******************  Bit definition for DSI_VCCR register  ***************/
8197 #define DSI_VCCR_NUMC_Pos             (0U)
8198 #define DSI_VCCR_NUMC_Msk             (0x1FFFUL << DSI_VCCR_NUMC_Pos)          /*!< 0x00001FFF */
8199 #define DSI_VCCR_NUMC                 DSI_VCCR_NUMC_Msk                        /*!< Number of Chunks */
8200 #define DSI_VCCR_NUMC0_Pos            (0U)
8201 #define DSI_VCCR_NUMC0_Msk            (0x1UL << DSI_VCCR_NUMC0_Pos)            /*!< 0x00000001 */
8202 #define DSI_VCCR_NUMC0                DSI_VCCR_NUMC0_Msk
8203 #define DSI_VCCR_NUMC1_Pos            (1U)
8204 #define DSI_VCCR_NUMC1_Msk            (0x1UL << DSI_VCCR_NUMC1_Pos)            /*!< 0x00000002 */
8205 #define DSI_VCCR_NUMC1                DSI_VCCR_NUMC1_Msk
8206 #define DSI_VCCR_NUMC2_Pos            (2U)
8207 #define DSI_VCCR_NUMC2_Msk            (0x1UL << DSI_VCCR_NUMC2_Pos)            /*!< 0x00000004 */
8208 #define DSI_VCCR_NUMC2                DSI_VCCR_NUMC2_Msk
8209 #define DSI_VCCR_NUMC3_Pos            (3U)
8210 #define DSI_VCCR_NUMC3_Msk            (0x1UL << DSI_VCCR_NUMC3_Pos)            /*!< 0x00000008 */
8211 #define DSI_VCCR_NUMC3                DSI_VCCR_NUMC3_Msk
8212 #define DSI_VCCR_NUMC4_Pos            (4U)
8213 #define DSI_VCCR_NUMC4_Msk            (0x1UL << DSI_VCCR_NUMC4_Pos)            /*!< 0x00000010 */
8214 #define DSI_VCCR_NUMC4                DSI_VCCR_NUMC4_Msk
8215 #define DSI_VCCR_NUMC5_Pos            (5U)
8216 #define DSI_VCCR_NUMC5_Msk            (0x1UL << DSI_VCCR_NUMC5_Pos)            /*!< 0x00000020 */
8217 #define DSI_VCCR_NUMC5                DSI_VCCR_NUMC5_Msk
8218 #define DSI_VCCR_NUMC6_Pos            (6U)
8219 #define DSI_VCCR_NUMC6_Msk            (0x1UL << DSI_VCCR_NUMC6_Pos)            /*!< 0x00000040 */
8220 #define DSI_VCCR_NUMC6                DSI_VCCR_NUMC6_Msk
8221 #define DSI_VCCR_NUMC7_Pos            (7U)
8222 #define DSI_VCCR_NUMC7_Msk            (0x1UL << DSI_VCCR_NUMC7_Pos)            /*!< 0x00000080 */
8223 #define DSI_VCCR_NUMC7                DSI_VCCR_NUMC7_Msk
8224 #define DSI_VCCR_NUMC8_Pos            (8U)
8225 #define DSI_VCCR_NUMC8_Msk            (0x1UL << DSI_VCCR_NUMC8_Pos)            /*!< 0x00000100 */
8226 #define DSI_VCCR_NUMC8                DSI_VCCR_NUMC8_Msk
8227 #define DSI_VCCR_NUMC9_Pos            (9U)
8228 #define DSI_VCCR_NUMC9_Msk            (0x1UL << DSI_VCCR_NUMC9_Pos)            /*!< 0x00000200 */
8229 #define DSI_VCCR_NUMC9                DSI_VCCR_NUMC9_Msk
8230 #define DSI_VCCR_NUMC10_Pos           (10U)
8231 #define DSI_VCCR_NUMC10_Msk           (0x1UL << DSI_VCCR_NUMC10_Pos)           /*!< 0x00000400 */
8232 #define DSI_VCCR_NUMC10               DSI_VCCR_NUMC10_Msk
8233 #define DSI_VCCR_NUMC11_Pos           (11U)
8234 #define DSI_VCCR_NUMC11_Msk           (0x1UL << DSI_VCCR_NUMC11_Pos)           /*!< 0x00000800 */
8235 #define DSI_VCCR_NUMC11               DSI_VCCR_NUMC11_Msk
8236 #define DSI_VCCR_NUMC12_Pos           (12U)
8237 #define DSI_VCCR_NUMC12_Msk           (0x1UL << DSI_VCCR_NUMC12_Pos)           /*!< 0x00001000 */
8238 #define DSI_VCCR_NUMC12               DSI_VCCR_NUMC12_Msk
8239 
8240 /*******************  Bit definition for DSI_VNPCR register  **************/
8241 #define DSI_VNPCR_NPSIZE_Pos          (0U)
8242 #define DSI_VNPCR_NPSIZE_Msk          (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos)       /*!< 0x00001FFF */
8243 #define DSI_VNPCR_NPSIZE              DSI_VNPCR_NPSIZE_Msk                     /*!< Null Packet Size */
8244 #define DSI_VNPCR_NPSIZE0_Pos         (0U)
8245 #define DSI_VNPCR_NPSIZE0_Msk         (0x1UL << DSI_VNPCR_NPSIZE0_Pos)         /*!< 0x00000001 */
8246 #define DSI_VNPCR_NPSIZE0             DSI_VNPCR_NPSIZE0_Msk
8247 #define DSI_VNPCR_NPSIZE1_Pos         (1U)
8248 #define DSI_VNPCR_NPSIZE1_Msk         (0x1UL << DSI_VNPCR_NPSIZE1_Pos)         /*!< 0x00000002 */
8249 #define DSI_VNPCR_NPSIZE1             DSI_VNPCR_NPSIZE1_Msk
8250 #define DSI_VNPCR_NPSIZE2_Pos         (2U)
8251 #define DSI_VNPCR_NPSIZE2_Msk         (0x1UL << DSI_VNPCR_NPSIZE2_Pos)         /*!< 0x00000004 */
8252 #define DSI_VNPCR_NPSIZE2             DSI_VNPCR_NPSIZE2_Msk
8253 #define DSI_VNPCR_NPSIZE3_Pos         (3U)
8254 #define DSI_VNPCR_NPSIZE3_Msk         (0x1UL << DSI_VNPCR_NPSIZE3_Pos)         /*!< 0x00000008 */
8255 #define DSI_VNPCR_NPSIZE3             DSI_VNPCR_NPSIZE3_Msk
8256 #define DSI_VNPCR_NPSIZE4_Pos         (4U)
8257 #define DSI_VNPCR_NPSIZE4_Msk         (0x1UL << DSI_VNPCR_NPSIZE4_Pos)         /*!< 0x00000010 */
8258 #define DSI_VNPCR_NPSIZE4             DSI_VNPCR_NPSIZE4_Msk
8259 #define DSI_VNPCR_NPSIZE5_Pos         (5U)
8260 #define DSI_VNPCR_NPSIZE5_Msk         (0x1UL << DSI_VNPCR_NPSIZE5_Pos)         /*!< 0x00000020 */
8261 #define DSI_VNPCR_NPSIZE5             DSI_VNPCR_NPSIZE5_Msk
8262 #define DSI_VNPCR_NPSIZE6_Pos         (6U)
8263 #define DSI_VNPCR_NPSIZE6_Msk         (0x1UL << DSI_VNPCR_NPSIZE6_Pos)         /*!< 0x00000040 */
8264 #define DSI_VNPCR_NPSIZE6             DSI_VNPCR_NPSIZE6_Msk
8265 #define DSI_VNPCR_NPSIZE7_Pos         (7U)
8266 #define DSI_VNPCR_NPSIZE7_Msk         (0x1UL << DSI_VNPCR_NPSIZE7_Pos)         /*!< 0x00000080 */
8267 #define DSI_VNPCR_NPSIZE7             DSI_VNPCR_NPSIZE7_Msk
8268 #define DSI_VNPCR_NPSIZE8_Pos         (8U)
8269 #define DSI_VNPCR_NPSIZE8_Msk         (0x1UL << DSI_VNPCR_NPSIZE8_Pos)         /*!< 0x00000100 */
8270 #define DSI_VNPCR_NPSIZE8             DSI_VNPCR_NPSIZE8_Msk
8271 #define DSI_VNPCR_NPSIZE9_Pos         (9U)
8272 #define DSI_VNPCR_NPSIZE9_Msk         (0x1UL << DSI_VNPCR_NPSIZE9_Pos)         /*!< 0x00000200 */
8273 #define DSI_VNPCR_NPSIZE9             DSI_VNPCR_NPSIZE9_Msk
8274 #define DSI_VNPCR_NPSIZE10_Pos        (10U)
8275 #define DSI_VNPCR_NPSIZE10_Msk        (0x1UL << DSI_VNPCR_NPSIZE10_Pos)        /*!< 0x00000400 */
8276 #define DSI_VNPCR_NPSIZE10            DSI_VNPCR_NPSIZE10_Msk
8277 #define DSI_VNPCR_NPSIZE11_Pos        (11U)
8278 #define DSI_VNPCR_NPSIZE11_Msk        (0x1UL << DSI_VNPCR_NPSIZE11_Pos)        /*!< 0x00000800 */
8279 #define DSI_VNPCR_NPSIZE11            DSI_VNPCR_NPSIZE11_Msk
8280 #define DSI_VNPCR_NPSIZE12_Pos        (12U)
8281 #define DSI_VNPCR_NPSIZE12_Msk        (0x1UL << DSI_VNPCR_NPSIZE12_Pos)        /*!< 0x00001000 */
8282 #define DSI_VNPCR_NPSIZE12            DSI_VNPCR_NPSIZE12_Msk
8283 
8284 /*******************  Bit definition for DSI_VHSACR register  *************/
8285 #define DSI_VHSACR_HSA_Pos            (0U)
8286 #define DSI_VHSACR_HSA_Msk            (0xFFFUL << DSI_VHSACR_HSA_Pos)          /*!< 0x00000FFF */
8287 #define DSI_VHSACR_HSA                DSI_VHSACR_HSA_Msk                       /*!< Horizontal Synchronism Active duration */
8288 #define DSI_VHSACR_HSA0_Pos           (0U)
8289 #define DSI_VHSACR_HSA0_Msk           (0x1UL << DSI_VHSACR_HSA0_Pos)           /*!< 0x00000001 */
8290 #define DSI_VHSACR_HSA0               DSI_VHSACR_HSA0_Msk
8291 #define DSI_VHSACR_HSA1_Pos           (1U)
8292 #define DSI_VHSACR_HSA1_Msk           (0x1UL << DSI_VHSACR_HSA1_Pos)           /*!< 0x00000002 */
8293 #define DSI_VHSACR_HSA1               DSI_VHSACR_HSA1_Msk
8294 #define DSI_VHSACR_HSA2_Pos           (2U)
8295 #define DSI_VHSACR_HSA2_Msk           (0x1UL << DSI_VHSACR_HSA2_Pos)           /*!< 0x00000004 */
8296 #define DSI_VHSACR_HSA2               DSI_VHSACR_HSA2_Msk
8297 #define DSI_VHSACR_HSA3_Pos           (3U)
8298 #define DSI_VHSACR_HSA3_Msk           (0x1UL << DSI_VHSACR_HSA3_Pos)           /*!< 0x00000008 */
8299 #define DSI_VHSACR_HSA3               DSI_VHSACR_HSA3_Msk
8300 #define DSI_VHSACR_HSA4_Pos           (4U)
8301 #define DSI_VHSACR_HSA4_Msk           (0x1UL << DSI_VHSACR_HSA4_Pos)           /*!< 0x00000010 */
8302 #define DSI_VHSACR_HSA4               DSI_VHSACR_HSA4_Msk
8303 #define DSI_VHSACR_HSA5_Pos           (5U)
8304 #define DSI_VHSACR_HSA5_Msk           (0x1UL << DSI_VHSACR_HSA5_Pos)           /*!< 0x00000020 */
8305 #define DSI_VHSACR_HSA5               DSI_VHSACR_HSA5_Msk
8306 #define DSI_VHSACR_HSA6_Pos           (6U)
8307 #define DSI_VHSACR_HSA6_Msk           (0x1UL << DSI_VHSACR_HSA6_Pos)           /*!< 0x00000040 */
8308 #define DSI_VHSACR_HSA6               DSI_VHSACR_HSA6_Msk
8309 #define DSI_VHSACR_HSA7_Pos           (7U)
8310 #define DSI_VHSACR_HSA7_Msk           (0x1UL << DSI_VHSACR_HSA7_Pos)           /*!< 0x00000080 */
8311 #define DSI_VHSACR_HSA7               DSI_VHSACR_HSA7_Msk
8312 #define DSI_VHSACR_HSA8_Pos           (8U)
8313 #define DSI_VHSACR_HSA8_Msk           (0x1UL << DSI_VHSACR_HSA8_Pos)           /*!< 0x00000100 */
8314 #define DSI_VHSACR_HSA8               DSI_VHSACR_HSA8_Msk
8315 #define DSI_VHSACR_HSA9_Pos           (9U)
8316 #define DSI_VHSACR_HSA9_Msk           (0x1UL << DSI_VHSACR_HSA9_Pos)           /*!< 0x00000200 */
8317 #define DSI_VHSACR_HSA9               DSI_VHSACR_HSA9_Msk
8318 #define DSI_VHSACR_HSA10_Pos          (10U)
8319 #define DSI_VHSACR_HSA10_Msk          (0x1UL << DSI_VHSACR_HSA10_Pos)          /*!< 0x00000400 */
8320 #define DSI_VHSACR_HSA10              DSI_VHSACR_HSA10_Msk
8321 #define DSI_VHSACR_HSA11_Pos          (11U)
8322 #define DSI_VHSACR_HSA11_Msk          (0x1UL << DSI_VHSACR_HSA11_Pos)          /*!< 0x00000800 */
8323 #define DSI_VHSACR_HSA11              DSI_VHSACR_HSA11_Msk
8324 
8325 /*******************  Bit definition for DSI_VHBPCR register  *************/
8326 #define DSI_VHBPCR_HBP_Pos            (0U)
8327 #define DSI_VHBPCR_HBP_Msk            (0xFFFUL << DSI_VHBPCR_HBP_Pos)          /*!< 0x00000FFF */
8328 #define DSI_VHBPCR_HBP                DSI_VHBPCR_HBP_Msk                       /*!< Horizontal Back-Porch duration */
8329 #define DSI_VHBPCR_HBP0_Pos           (0U)
8330 #define DSI_VHBPCR_HBP0_Msk           (0x1UL << DSI_VHBPCR_HBP0_Pos)           /*!< 0x00000001 */
8331 #define DSI_VHBPCR_HBP0               DSI_VHBPCR_HBP0_Msk
8332 #define DSI_VHBPCR_HBP1_Pos           (1U)
8333 #define DSI_VHBPCR_HBP1_Msk           (0x1UL << DSI_VHBPCR_HBP1_Pos)           /*!< 0x00000002 */
8334 #define DSI_VHBPCR_HBP1               DSI_VHBPCR_HBP1_Msk
8335 #define DSI_VHBPCR_HBP2_Pos           (2U)
8336 #define DSI_VHBPCR_HBP2_Msk           (0x1UL << DSI_VHBPCR_HBP2_Pos)           /*!< 0x00000004 */
8337 #define DSI_VHBPCR_HBP2               DSI_VHBPCR_HBP2_Msk
8338 #define DSI_VHBPCR_HBP3_Pos           (3U)
8339 #define DSI_VHBPCR_HBP3_Msk           (0x1UL << DSI_VHBPCR_HBP3_Pos)           /*!< 0x00000008 */
8340 #define DSI_VHBPCR_HBP3               DSI_VHBPCR_HBP3_Msk
8341 #define DSI_VHBPCR_HBP4_Pos           (4U)
8342 #define DSI_VHBPCR_HBP4_Msk           (0x1UL << DSI_VHBPCR_HBP4_Pos)           /*!< 0x00000010 */
8343 #define DSI_VHBPCR_HBP4               DSI_VHBPCR_HBP4_Msk
8344 #define DSI_VHBPCR_HBP5_Pos           (5U)
8345 #define DSI_VHBPCR_HBP5_Msk           (0x1UL << DSI_VHBPCR_HBP5_Pos)           /*!< 0x00000020 */
8346 #define DSI_VHBPCR_HBP5               DSI_VHBPCR_HBP5_Msk
8347 #define DSI_VHBPCR_HBP6_Pos           (6U)
8348 #define DSI_VHBPCR_HBP6_Msk           (0x1UL << DSI_VHBPCR_HBP6_Pos)           /*!< 0x00000040 */
8349 #define DSI_VHBPCR_HBP6               DSI_VHBPCR_HBP6_Msk
8350 #define DSI_VHBPCR_HBP7_Pos           (7U)
8351 #define DSI_VHBPCR_HBP7_Msk           (0x1UL << DSI_VHBPCR_HBP7_Pos)           /*!< 0x00000080 */
8352 #define DSI_VHBPCR_HBP7               DSI_VHBPCR_HBP7_Msk
8353 #define DSI_VHBPCR_HBP8_Pos           (8U)
8354 #define DSI_VHBPCR_HBP8_Msk           (0x1UL << DSI_VHBPCR_HBP8_Pos)           /*!< 0x00000100 */
8355 #define DSI_VHBPCR_HBP8               DSI_VHBPCR_HBP8_Msk
8356 #define DSI_VHBPCR_HBP9_Pos           (9U)
8357 #define DSI_VHBPCR_HBP9_Msk           (0x1UL << DSI_VHBPCR_HBP9_Pos)           /*!< 0x00000200 */
8358 #define DSI_VHBPCR_HBP9               DSI_VHBPCR_HBP9_Msk
8359 #define DSI_VHBPCR_HBP10_Pos          (10U)
8360 #define DSI_VHBPCR_HBP10_Msk          (0x1UL << DSI_VHBPCR_HBP10_Pos)          /*!< 0x00000400 */
8361 #define DSI_VHBPCR_HBP10              DSI_VHBPCR_HBP10_Msk
8362 #define DSI_VHBPCR_HBP11_Pos          (11U)
8363 #define DSI_VHBPCR_HBP11_Msk          (0x1UL << DSI_VHBPCR_HBP11_Pos)          /*!< 0x00000800 */
8364 #define DSI_VHBPCR_HBP11              DSI_VHBPCR_HBP11_Msk
8365 
8366 /*******************  Bit definition for DSI_VLCR register  ***************/
8367 #define DSI_VLCR_HLINE_Pos            (0U)
8368 #define DSI_VLCR_HLINE_Msk            (0x7FFFUL << DSI_VLCR_HLINE_Pos)         /*!< 0x00007FFF */
8369 #define DSI_VLCR_HLINE                DSI_VLCR_HLINE_Msk                       /*!< Horizontal Line duration */
8370 #define DSI_VLCR_HLINE0_Pos           (0U)
8371 #define DSI_VLCR_HLINE0_Msk           (0x1UL << DSI_VLCR_HLINE0_Pos)           /*!< 0x00000001 */
8372 #define DSI_VLCR_HLINE0               DSI_VLCR_HLINE0_Msk
8373 #define DSI_VLCR_HLINE1_Pos           (1U)
8374 #define DSI_VLCR_HLINE1_Msk           (0x1UL << DSI_VLCR_HLINE1_Pos)           /*!< 0x00000002 */
8375 #define DSI_VLCR_HLINE1               DSI_VLCR_HLINE1_Msk
8376 #define DSI_VLCR_HLINE2_Pos           (2U)
8377 #define DSI_VLCR_HLINE2_Msk           (0x1UL << DSI_VLCR_HLINE2_Pos)           /*!< 0x00000004 */
8378 #define DSI_VLCR_HLINE2               DSI_VLCR_HLINE2_Msk
8379 #define DSI_VLCR_HLINE3_Pos           (3U)
8380 #define DSI_VLCR_HLINE3_Msk           (0x1UL << DSI_VLCR_HLINE3_Pos)           /*!< 0x00000008 */
8381 #define DSI_VLCR_HLINE3               DSI_VLCR_HLINE3_Msk
8382 #define DSI_VLCR_HLINE4_Pos           (4U)
8383 #define DSI_VLCR_HLINE4_Msk           (0x1UL << DSI_VLCR_HLINE4_Pos)           /*!< 0x00000010 */
8384 #define DSI_VLCR_HLINE4               DSI_VLCR_HLINE4_Msk
8385 #define DSI_VLCR_HLINE5_Pos           (5U)
8386 #define DSI_VLCR_HLINE5_Msk           (0x1UL << DSI_VLCR_HLINE5_Pos)           /*!< 0x00000020 */
8387 #define DSI_VLCR_HLINE5               DSI_VLCR_HLINE5_Msk
8388 #define DSI_VLCR_HLINE6_Pos           (6U)
8389 #define DSI_VLCR_HLINE6_Msk           (0x1UL << DSI_VLCR_HLINE6_Pos)           /*!< 0x00000040 */
8390 #define DSI_VLCR_HLINE6               DSI_VLCR_HLINE6_Msk
8391 #define DSI_VLCR_HLINE7_Pos           (7U)
8392 #define DSI_VLCR_HLINE7_Msk           (0x1UL << DSI_VLCR_HLINE7_Pos)           /*!< 0x00000080 */
8393 #define DSI_VLCR_HLINE7               DSI_VLCR_HLINE7_Msk
8394 #define DSI_VLCR_HLINE8_Pos           (8U)
8395 #define DSI_VLCR_HLINE8_Msk           (0x1UL << DSI_VLCR_HLINE8_Pos)           /*!< 0x00000100 */
8396 #define DSI_VLCR_HLINE8               DSI_VLCR_HLINE8_Msk
8397 #define DSI_VLCR_HLINE9_Pos           (9U)
8398 #define DSI_VLCR_HLINE9_Msk           (0x1UL << DSI_VLCR_HLINE9_Pos)           /*!< 0x00000200 */
8399 #define DSI_VLCR_HLINE9               DSI_VLCR_HLINE9_Msk
8400 #define DSI_VLCR_HLINE10_Pos          (10U)
8401 #define DSI_VLCR_HLINE10_Msk          (0x1UL << DSI_VLCR_HLINE10_Pos)          /*!< 0x00000400 */
8402 #define DSI_VLCR_HLINE10              DSI_VLCR_HLINE10_Msk
8403 #define DSI_VLCR_HLINE11_Pos          (11U)
8404 #define DSI_VLCR_HLINE11_Msk          (0x1UL << DSI_VLCR_HLINE11_Pos)          /*!< 0x00000800 */
8405 #define DSI_VLCR_HLINE11              DSI_VLCR_HLINE11_Msk
8406 #define DSI_VLCR_HLINE12_Pos          (12U)
8407 #define DSI_VLCR_HLINE12_Msk          (0x1UL << DSI_VLCR_HLINE12_Pos)          /*!< 0x00001000 */
8408 #define DSI_VLCR_HLINE12              DSI_VLCR_HLINE12_Msk
8409 #define DSI_VLCR_HLINE13_Pos          (13U)
8410 #define DSI_VLCR_HLINE13_Msk          (0x1UL << DSI_VLCR_HLINE13_Pos)          /*!< 0x00002000 */
8411 #define DSI_VLCR_HLINE13              DSI_VLCR_HLINE13_Msk
8412 #define DSI_VLCR_HLINE14_Pos          (14U)
8413 #define DSI_VLCR_HLINE14_Msk          (0x1UL << DSI_VLCR_HLINE14_Pos)          /*!< 0x00004000 */
8414 #define DSI_VLCR_HLINE14              DSI_VLCR_HLINE14_Msk
8415 
8416 /*******************  Bit definition for DSI_VVSACR register  *************/
8417 #define DSI_VVSACR_VSA_Pos            (0U)
8418 #define DSI_VVSACR_VSA_Msk            (0x3FFUL << DSI_VVSACR_VSA_Pos)          /*!< 0x000003FF */
8419 #define DSI_VVSACR_VSA                DSI_VVSACR_VSA_Msk                       /*!< Vertical Synchronism Active duration */
8420 #define DSI_VVSACR_VSA0_Pos           (0U)
8421 #define DSI_VVSACR_VSA0_Msk           (0x1UL << DSI_VVSACR_VSA0_Pos)           /*!< 0x00000001 */
8422 #define DSI_VVSACR_VSA0               DSI_VVSACR_VSA0_Msk
8423 #define DSI_VVSACR_VSA1_Pos           (1U)
8424 #define DSI_VVSACR_VSA1_Msk           (0x1UL << DSI_VVSACR_VSA1_Pos)           /*!< 0x00000002 */
8425 #define DSI_VVSACR_VSA1               DSI_VVSACR_VSA1_Msk
8426 #define DSI_VVSACR_VSA2_Pos           (2U)
8427 #define DSI_VVSACR_VSA2_Msk           (0x1UL << DSI_VVSACR_VSA2_Pos)           /*!< 0x00000004 */
8428 #define DSI_VVSACR_VSA2               DSI_VVSACR_VSA2_Msk
8429 #define DSI_VVSACR_VSA3_Pos           (3U)
8430 #define DSI_VVSACR_VSA3_Msk           (0x1UL << DSI_VVSACR_VSA3_Pos)           /*!< 0x00000008 */
8431 #define DSI_VVSACR_VSA3               DSI_VVSACR_VSA3_Msk
8432 #define DSI_VVSACR_VSA4_Pos           (4U)
8433 #define DSI_VVSACR_VSA4_Msk           (0x1UL << DSI_VVSACR_VSA4_Pos)           /*!< 0x00000010 */
8434 #define DSI_VVSACR_VSA4               DSI_VVSACR_VSA4_Msk
8435 #define DSI_VVSACR_VSA5_Pos           (5U)
8436 #define DSI_VVSACR_VSA5_Msk           (0x1UL << DSI_VVSACR_VSA5_Pos)           /*!< 0x00000020 */
8437 #define DSI_VVSACR_VSA5               DSI_VVSACR_VSA5_Msk
8438 #define DSI_VVSACR_VSA6_Pos           (6U)
8439 #define DSI_VVSACR_VSA6_Msk           (0x1UL << DSI_VVSACR_VSA6_Pos)           /*!< 0x00000040 */
8440 #define DSI_VVSACR_VSA6               DSI_VVSACR_VSA6_Msk
8441 #define DSI_VVSACR_VSA7_Pos           (7U)
8442 #define DSI_VVSACR_VSA7_Msk           (0x1UL << DSI_VVSACR_VSA7_Pos)           /*!< 0x00000080 */
8443 #define DSI_VVSACR_VSA7               DSI_VVSACR_VSA7_Msk
8444 #define DSI_VVSACR_VSA8_Pos           (8U)
8445 #define DSI_VVSACR_VSA8_Msk           (0x1UL << DSI_VVSACR_VSA8_Pos)           /*!< 0x00000100 */
8446 #define DSI_VVSACR_VSA8               DSI_VVSACR_VSA8_Msk
8447 #define DSI_VVSACR_VSA9_Pos           (9U)
8448 #define DSI_VVSACR_VSA9_Msk           (0x1UL << DSI_VVSACR_VSA9_Pos)           /*!< 0x00000200 */
8449 #define DSI_VVSACR_VSA9               DSI_VVSACR_VSA9_Msk
8450 
8451 /*******************  Bit definition for DSI_VVBPCR register  *************/
8452 #define DSI_VVBPCR_VBP_Pos            (0U)
8453 #define DSI_VVBPCR_VBP_Msk            (0x3FFUL << DSI_VVBPCR_VBP_Pos)          /*!< 0x000003FF */
8454 #define DSI_VVBPCR_VBP                DSI_VVBPCR_VBP_Msk                       /*!< Vertical Back-Porch duration */
8455 #define DSI_VVBPCR_VBP0_Pos           (0U)
8456 #define DSI_VVBPCR_VBP0_Msk           (0x1UL << DSI_VVBPCR_VBP0_Pos)           /*!< 0x00000001 */
8457 #define DSI_VVBPCR_VBP0               DSI_VVBPCR_VBP0_Msk
8458 #define DSI_VVBPCR_VBP1_Pos           (1U)
8459 #define DSI_VVBPCR_VBP1_Msk           (0x1UL << DSI_VVBPCR_VBP1_Pos)           /*!< 0x00000002 */
8460 #define DSI_VVBPCR_VBP1               DSI_VVBPCR_VBP1_Msk
8461 #define DSI_VVBPCR_VBP2_Pos           (2U)
8462 #define DSI_VVBPCR_VBP2_Msk           (0x1UL << DSI_VVBPCR_VBP2_Pos)           /*!< 0x00000004 */
8463 #define DSI_VVBPCR_VBP2               DSI_VVBPCR_VBP2_Msk
8464 #define DSI_VVBPCR_VBP3_Pos           (3U)
8465 #define DSI_VVBPCR_VBP3_Msk           (0x1UL << DSI_VVBPCR_VBP3_Pos)           /*!< 0x00000008 */
8466 #define DSI_VVBPCR_VBP3               DSI_VVBPCR_VBP3_Msk
8467 #define DSI_VVBPCR_VBP4_Pos           (4U)
8468 #define DSI_VVBPCR_VBP4_Msk           (0x1UL << DSI_VVBPCR_VBP4_Pos)           /*!< 0x00000010 */
8469 #define DSI_VVBPCR_VBP4               DSI_VVBPCR_VBP4_Msk
8470 #define DSI_VVBPCR_VBP5_Pos           (5U)
8471 #define DSI_VVBPCR_VBP5_Msk           (0x1UL << DSI_VVBPCR_VBP5_Pos)           /*!< 0x00000020 */
8472 #define DSI_VVBPCR_VBP5               DSI_VVBPCR_VBP5_Msk
8473 #define DSI_VVBPCR_VBP6_Pos           (6U)
8474 #define DSI_VVBPCR_VBP6_Msk           (0x1UL << DSI_VVBPCR_VBP6_Pos)           /*!< 0x00000040 */
8475 #define DSI_VVBPCR_VBP6               DSI_VVBPCR_VBP6_Msk
8476 #define DSI_VVBPCR_VBP7_Pos           (7U)
8477 #define DSI_VVBPCR_VBP7_Msk           (0x1UL << DSI_VVBPCR_VBP7_Pos)           /*!< 0x00000080 */
8478 #define DSI_VVBPCR_VBP7               DSI_VVBPCR_VBP7_Msk
8479 #define DSI_VVBPCR_VBP8_Pos           (8U)
8480 #define DSI_VVBPCR_VBP8_Msk           (0x1UL << DSI_VVBPCR_VBP8_Pos)           /*!< 0x00000100 */
8481 #define DSI_VVBPCR_VBP8               DSI_VVBPCR_VBP8_Msk
8482 #define DSI_VVBPCR_VBP9_Pos           (9U)
8483 #define DSI_VVBPCR_VBP9_Msk           (0x1UL << DSI_VVBPCR_VBP9_Pos)           /*!< 0x00000200 */
8484 #define DSI_VVBPCR_VBP9               DSI_VVBPCR_VBP9_Msk
8485 
8486 /*******************  Bit definition for DSI_VVFPCR register  *************/
8487 #define DSI_VVFPCR_VFP_Pos            (0U)
8488 #define DSI_VVFPCR_VFP_Msk            (0x3FFUL << DSI_VVFPCR_VFP_Pos)          /*!< 0x000003FF */
8489 #define DSI_VVFPCR_VFP                DSI_VVFPCR_VFP_Msk                       /*!< Vertical Front-Porch duration */
8490 #define DSI_VVFPCR_VFP0_Pos           (0U)
8491 #define DSI_VVFPCR_VFP0_Msk           (0x1UL << DSI_VVFPCR_VFP0_Pos)           /*!< 0x00000001 */
8492 #define DSI_VVFPCR_VFP0               DSI_VVFPCR_VFP0_Msk
8493 #define DSI_VVFPCR_VFP1_Pos           (1U)
8494 #define DSI_VVFPCR_VFP1_Msk           (0x1UL << DSI_VVFPCR_VFP1_Pos)           /*!< 0x00000002 */
8495 #define DSI_VVFPCR_VFP1               DSI_VVFPCR_VFP1_Msk
8496 #define DSI_VVFPCR_VFP2_Pos           (2U)
8497 #define DSI_VVFPCR_VFP2_Msk           (0x1UL << DSI_VVFPCR_VFP2_Pos)           /*!< 0x00000004 */
8498 #define DSI_VVFPCR_VFP2               DSI_VVFPCR_VFP2_Msk
8499 #define DSI_VVFPCR_VFP3_Pos           (3U)
8500 #define DSI_VVFPCR_VFP3_Msk           (0x1UL << DSI_VVFPCR_VFP3_Pos)           /*!< 0x00000008 */
8501 #define DSI_VVFPCR_VFP3               DSI_VVFPCR_VFP3_Msk
8502 #define DSI_VVFPCR_VFP4_Pos           (4U)
8503 #define DSI_VVFPCR_VFP4_Msk           (0x1UL << DSI_VVFPCR_VFP4_Pos)           /*!< 0x00000010 */
8504 #define DSI_VVFPCR_VFP4               DSI_VVFPCR_VFP4_Msk
8505 #define DSI_VVFPCR_VFP5_Pos           (5U)
8506 #define DSI_VVFPCR_VFP5_Msk           (0x1UL << DSI_VVFPCR_VFP5_Pos)           /*!< 0x00000020 */
8507 #define DSI_VVFPCR_VFP5               DSI_VVFPCR_VFP5_Msk
8508 #define DSI_VVFPCR_VFP6_Pos           (6U)
8509 #define DSI_VVFPCR_VFP6_Msk           (0x1UL << DSI_VVFPCR_VFP6_Pos)           /*!< 0x00000040 */
8510 #define DSI_VVFPCR_VFP6               DSI_VVFPCR_VFP6_Msk
8511 #define DSI_VVFPCR_VFP7_Pos           (7U)
8512 #define DSI_VVFPCR_VFP7_Msk           (0x1UL << DSI_VVFPCR_VFP7_Pos)           /*!< 0x00000080 */
8513 #define DSI_VVFPCR_VFP7               DSI_VVFPCR_VFP7_Msk
8514 #define DSI_VVFPCR_VFP8_Pos           (8U)
8515 #define DSI_VVFPCR_VFP8_Msk           (0x1UL << DSI_VVFPCR_VFP8_Pos)           /*!< 0x00000100 */
8516 #define DSI_VVFPCR_VFP8               DSI_VVFPCR_VFP8_Msk
8517 #define DSI_VVFPCR_VFP9_Pos           (9U)
8518 #define DSI_VVFPCR_VFP9_Msk           (0x1UL << DSI_VVFPCR_VFP9_Pos)           /*!< 0x00000200 */
8519 #define DSI_VVFPCR_VFP9               DSI_VVFPCR_VFP9_Msk
8520 
8521 /*******************  Bit definition for DSI_VVACR register  **************/
8522 #define DSI_VVACR_VA_Pos              (0U)
8523 #define DSI_VVACR_VA_Msk              (0x3FFFUL << DSI_VVACR_VA_Pos)           /*!< 0x00003FFF */
8524 #define DSI_VVACR_VA                  DSI_VVACR_VA_Msk                         /*!< Vertical Active duration */
8525 #define DSI_VVACR_VA0_Pos             (0U)
8526 #define DSI_VVACR_VA0_Msk             (0x1UL << DSI_VVACR_VA0_Pos)             /*!< 0x00000001 */
8527 #define DSI_VVACR_VA0                 DSI_VVACR_VA0_Msk
8528 #define DSI_VVACR_VA1_Pos             (1U)
8529 #define DSI_VVACR_VA1_Msk             (0x1UL << DSI_VVACR_VA1_Pos)             /*!< 0x00000002 */
8530 #define DSI_VVACR_VA1                 DSI_VVACR_VA1_Msk
8531 #define DSI_VVACR_VA2_Pos             (2U)
8532 #define DSI_VVACR_VA2_Msk             (0x1UL << DSI_VVACR_VA2_Pos)             /*!< 0x00000004 */
8533 #define DSI_VVACR_VA2                 DSI_VVACR_VA2_Msk
8534 #define DSI_VVACR_VA3_Pos             (3U)
8535 #define DSI_VVACR_VA3_Msk             (0x1UL << DSI_VVACR_VA3_Pos)             /*!< 0x00000008 */
8536 #define DSI_VVACR_VA3                 DSI_VVACR_VA3_Msk
8537 #define DSI_VVACR_VA4_Pos             (4U)
8538 #define DSI_VVACR_VA4_Msk             (0x1UL << DSI_VVACR_VA4_Pos)             /*!< 0x00000010 */
8539 #define DSI_VVACR_VA4                 DSI_VVACR_VA4_Msk
8540 #define DSI_VVACR_VA5_Pos             (5U)
8541 #define DSI_VVACR_VA5_Msk             (0x1UL << DSI_VVACR_VA5_Pos)             /*!< 0x00000020 */
8542 #define DSI_VVACR_VA5                 DSI_VVACR_VA5_Msk
8543 #define DSI_VVACR_VA6_Pos             (6U)
8544 #define DSI_VVACR_VA6_Msk             (0x1UL << DSI_VVACR_VA6_Pos)             /*!< 0x00000040 */
8545 #define DSI_VVACR_VA6                 DSI_VVACR_VA6_Msk
8546 #define DSI_VVACR_VA7_Pos             (7U)
8547 #define DSI_VVACR_VA7_Msk             (0x1UL << DSI_VVACR_VA7_Pos)             /*!< 0x00000080 */
8548 #define DSI_VVACR_VA7                 DSI_VVACR_VA7_Msk
8549 #define DSI_VVACR_VA8_Pos             (8U)
8550 #define DSI_VVACR_VA8_Msk             (0x1UL << DSI_VVACR_VA8_Pos)             /*!< 0x00000100 */
8551 #define DSI_VVACR_VA8                 DSI_VVACR_VA8_Msk
8552 #define DSI_VVACR_VA9_Pos             (9U)
8553 #define DSI_VVACR_VA9_Msk             (0x1UL << DSI_VVACR_VA9_Pos)             /*!< 0x00000200 */
8554 #define DSI_VVACR_VA9                 DSI_VVACR_VA9_Msk
8555 #define DSI_VVACR_VA10_Pos            (10U)
8556 #define DSI_VVACR_VA10_Msk            (0x1UL << DSI_VVACR_VA10_Pos)            /*!< 0x00000400 */
8557 #define DSI_VVACR_VA10                DSI_VVACR_VA10_Msk
8558 #define DSI_VVACR_VA11_Pos            (11U)
8559 #define DSI_VVACR_VA11_Msk            (0x1UL << DSI_VVACR_VA11_Pos)            /*!< 0x00000800 */
8560 #define DSI_VVACR_VA11                DSI_VVACR_VA11_Msk
8561 #define DSI_VVACR_VA12_Pos            (12U)
8562 #define DSI_VVACR_VA12_Msk            (0x1UL << DSI_VVACR_VA12_Pos)            /*!< 0x00001000 */
8563 #define DSI_VVACR_VA12                DSI_VVACR_VA12_Msk
8564 #define DSI_VVACR_VA13_Pos            (13U)
8565 #define DSI_VVACR_VA13_Msk            (0x1UL << DSI_VVACR_VA13_Pos)            /*!< 0x00002000 */
8566 #define DSI_VVACR_VA13                DSI_VVACR_VA13_Msk
8567 
8568 /*******************  Bit definition for DSI_LCCR register  ***************/
8569 #define DSI_LCCR_CMDSIZE_Pos          (0U)
8570 #define DSI_LCCR_CMDSIZE_Msk          (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos)       /*!< 0x0000FFFF */
8571 #define DSI_LCCR_CMDSIZE              DSI_LCCR_CMDSIZE_Msk                     /*!< Command Size */
8572 #define DSI_LCCR_CMDSIZE0_Pos         (0U)
8573 #define DSI_LCCR_CMDSIZE0_Msk         (0x1UL << DSI_LCCR_CMDSIZE0_Pos)         /*!< 0x00000001 */
8574 #define DSI_LCCR_CMDSIZE0             DSI_LCCR_CMDSIZE0_Msk
8575 #define DSI_LCCR_CMDSIZE1_Pos         (1U)
8576 #define DSI_LCCR_CMDSIZE1_Msk         (0x1UL << DSI_LCCR_CMDSIZE1_Pos)         /*!< 0x00000002 */
8577 #define DSI_LCCR_CMDSIZE1             DSI_LCCR_CMDSIZE1_Msk
8578 #define DSI_LCCR_CMDSIZE2_Pos         (2U)
8579 #define DSI_LCCR_CMDSIZE2_Msk         (0x1UL << DSI_LCCR_CMDSIZE2_Pos)         /*!< 0x00000004 */
8580 #define DSI_LCCR_CMDSIZE2             DSI_LCCR_CMDSIZE2_Msk
8581 #define DSI_LCCR_CMDSIZE3_Pos         (3U)
8582 #define DSI_LCCR_CMDSIZE3_Msk         (0x1UL << DSI_LCCR_CMDSIZE3_Pos)         /*!< 0x00000008 */
8583 #define DSI_LCCR_CMDSIZE3             DSI_LCCR_CMDSIZE3_Msk
8584 #define DSI_LCCR_CMDSIZE4_Pos         (4U)
8585 #define DSI_LCCR_CMDSIZE4_Msk         (0x1UL << DSI_LCCR_CMDSIZE4_Pos)         /*!< 0x00000010 */
8586 #define DSI_LCCR_CMDSIZE4             DSI_LCCR_CMDSIZE4_Msk
8587 #define DSI_LCCR_CMDSIZE5_Pos         (5U)
8588 #define DSI_LCCR_CMDSIZE5_Msk         (0x1UL << DSI_LCCR_CMDSIZE5_Pos)         /*!< 0x00000020 */
8589 #define DSI_LCCR_CMDSIZE5             DSI_LCCR_CMDSIZE5_Msk
8590 #define DSI_LCCR_CMDSIZE6_Pos         (6U)
8591 #define DSI_LCCR_CMDSIZE6_Msk         (0x1UL << DSI_LCCR_CMDSIZE6_Pos)         /*!< 0x00000040 */
8592 #define DSI_LCCR_CMDSIZE6             DSI_LCCR_CMDSIZE6_Msk
8593 #define DSI_LCCR_CMDSIZE7_Pos         (7U)
8594 #define DSI_LCCR_CMDSIZE7_Msk         (0x1UL << DSI_LCCR_CMDSIZE7_Pos)         /*!< 0x00000080 */
8595 #define DSI_LCCR_CMDSIZE7             DSI_LCCR_CMDSIZE7_Msk
8596 #define DSI_LCCR_CMDSIZE8_Pos         (8U)
8597 #define DSI_LCCR_CMDSIZE8_Msk         (0x1UL << DSI_LCCR_CMDSIZE8_Pos)         /*!< 0x00000100 */
8598 #define DSI_LCCR_CMDSIZE8             DSI_LCCR_CMDSIZE8_Msk
8599 #define DSI_LCCR_CMDSIZE9_Pos         (9U)
8600 #define DSI_LCCR_CMDSIZE9_Msk         (0x1UL << DSI_LCCR_CMDSIZE9_Pos)         /*!< 0x00000200 */
8601 #define DSI_LCCR_CMDSIZE9             DSI_LCCR_CMDSIZE9_Msk
8602 #define DSI_LCCR_CMDSIZE10_Pos        (10U)
8603 #define DSI_LCCR_CMDSIZE10_Msk        (0x1UL << DSI_LCCR_CMDSIZE10_Pos)        /*!< 0x00000400 */
8604 #define DSI_LCCR_CMDSIZE10            DSI_LCCR_CMDSIZE10_Msk
8605 #define DSI_LCCR_CMDSIZE11_Pos        (11U)
8606 #define DSI_LCCR_CMDSIZE11_Msk        (0x1UL << DSI_LCCR_CMDSIZE11_Pos)        /*!< 0x00000800 */
8607 #define DSI_LCCR_CMDSIZE11            DSI_LCCR_CMDSIZE11_Msk
8608 #define DSI_LCCR_CMDSIZE12_Pos        (12U)
8609 #define DSI_LCCR_CMDSIZE12_Msk        (0x1UL << DSI_LCCR_CMDSIZE12_Pos)        /*!< 0x00001000 */
8610 #define DSI_LCCR_CMDSIZE12            DSI_LCCR_CMDSIZE12_Msk
8611 #define DSI_LCCR_CMDSIZE13_Pos        (13U)
8612 #define DSI_LCCR_CMDSIZE13_Msk        (0x1UL << DSI_LCCR_CMDSIZE13_Pos)        /*!< 0x00002000 */
8613 #define DSI_LCCR_CMDSIZE13            DSI_LCCR_CMDSIZE13_Msk
8614 #define DSI_LCCR_CMDSIZE14_Pos        (14U)
8615 #define DSI_LCCR_CMDSIZE14_Msk        (0x1UL << DSI_LCCR_CMDSIZE14_Pos)        /*!< 0x00004000 */
8616 #define DSI_LCCR_CMDSIZE14            DSI_LCCR_CMDSIZE14_Msk
8617 #define DSI_LCCR_CMDSIZE15_Pos        (15U)
8618 #define DSI_LCCR_CMDSIZE15_Msk        (0x1UL << DSI_LCCR_CMDSIZE15_Pos)        /*!< 0x00008000 */
8619 #define DSI_LCCR_CMDSIZE15            DSI_LCCR_CMDSIZE15_Msk
8620 
8621 /*******************  Bit definition for DSI_CMCR register  ***************/
8622 #define DSI_CMCR_TEARE_Pos            (0U)
8623 #define DSI_CMCR_TEARE_Msk            (0x1UL << DSI_CMCR_TEARE_Pos)            /*!< 0x00000001 */
8624 #define DSI_CMCR_TEARE                DSI_CMCR_TEARE_Msk                       /*!< Tearing Effect Acknowledge Request Enable */
8625 #define DSI_CMCR_ARE_Pos              (1U)
8626 #define DSI_CMCR_ARE_Msk              (0x1UL << DSI_CMCR_ARE_Pos)              /*!< 0x00000002 */
8627 #define DSI_CMCR_ARE                  DSI_CMCR_ARE_Msk                         /*!< Acknowledge Request Enable */
8628 #define DSI_CMCR_GSW0TX_Pos           (8U)
8629 #define DSI_CMCR_GSW0TX_Msk           (0x1UL << DSI_CMCR_GSW0TX_Pos)           /*!< 0x00000100 */
8630 #define DSI_CMCR_GSW0TX               DSI_CMCR_GSW0TX_Msk                      /*!< Generic Short Write Zero parameters Transmission */
8631 #define DSI_CMCR_GSW1TX_Pos           (9U)
8632 #define DSI_CMCR_GSW1TX_Msk           (0x1UL << DSI_CMCR_GSW1TX_Pos)           /*!< 0x00000200 */
8633 #define DSI_CMCR_GSW1TX               DSI_CMCR_GSW1TX_Msk                      /*!< Generic Short Write One parameters Transmission */
8634 #define DSI_CMCR_GSW2TX_Pos           (10U)
8635 #define DSI_CMCR_GSW2TX_Msk           (0x1UL << DSI_CMCR_GSW2TX_Pos)           /*!< 0x00000400 */
8636 #define DSI_CMCR_GSW2TX               DSI_CMCR_GSW2TX_Msk                      /*!< Generic Short Write Two parameters Transmission */
8637 #define DSI_CMCR_GSR0TX_Pos           (11U)
8638 #define DSI_CMCR_GSR0TX_Msk           (0x1UL << DSI_CMCR_GSR0TX_Pos)           /*!< 0x00000800 */
8639 #define DSI_CMCR_GSR0TX               DSI_CMCR_GSR0TX_Msk                      /*!< Generic Short Read Zero parameters Transmission */
8640 #define DSI_CMCR_GSR1TX_Pos           (12U)
8641 #define DSI_CMCR_GSR1TX_Msk           (0x1UL << DSI_CMCR_GSR1TX_Pos)           /*!< 0x00001000 */
8642 #define DSI_CMCR_GSR1TX               DSI_CMCR_GSR1TX_Msk                      /*!< Generic Short Read One parameters Transmission */
8643 #define DSI_CMCR_GSR2TX_Pos           (13U)
8644 #define DSI_CMCR_GSR2TX_Msk           (0x1UL << DSI_CMCR_GSR2TX_Pos)           /*!< 0x00002000 */
8645 #define DSI_CMCR_GSR2TX               DSI_CMCR_GSR2TX_Msk                      /*!< Generic Short Read Two parameters Transmission */
8646 #define DSI_CMCR_GLWTX_Pos            (14U)
8647 #define DSI_CMCR_GLWTX_Msk            (0x1UL << DSI_CMCR_GLWTX_Pos)            /*!< 0x00004000 */
8648 #define DSI_CMCR_GLWTX                DSI_CMCR_GLWTX_Msk                       /*!< Generic Long Write Transmission */
8649 #define DSI_CMCR_DSW0TX_Pos           (16U)
8650 #define DSI_CMCR_DSW0TX_Msk           (0x1UL << DSI_CMCR_DSW0TX_Pos)           /*!< 0x00010000 */
8651 #define DSI_CMCR_DSW0TX               DSI_CMCR_DSW0TX_Msk                      /*!< DCS Short Write Zero parameter Transmission */
8652 #define DSI_CMCR_DSW1TX_Pos           (17U)
8653 #define DSI_CMCR_DSW1TX_Msk           (0x1UL << DSI_CMCR_DSW1TX_Pos)           /*!< 0x00020000 */
8654 #define DSI_CMCR_DSW1TX               DSI_CMCR_DSW1TX_Msk                      /*!< DCS Short Read One parameter Transmission */
8655 #define DSI_CMCR_DSR0TX_Pos           (18U)
8656 #define DSI_CMCR_DSR0TX_Msk           (0x1UL << DSI_CMCR_DSR0TX_Pos)           /*!< 0x00040000 */
8657 #define DSI_CMCR_DSR0TX               DSI_CMCR_DSR0TX_Msk                      /*!< DCS Short Read Zero parameter Transmission */
8658 #define DSI_CMCR_DLWTX_Pos            (19U)
8659 #define DSI_CMCR_DLWTX_Msk            (0x1UL << DSI_CMCR_DLWTX_Pos)            /*!< 0x00080000 */
8660 #define DSI_CMCR_DLWTX                DSI_CMCR_DLWTX_Msk                       /*!< DCS Long Write Transmission */
8661 #define DSI_CMCR_MRDPS_Pos            (24U)
8662 #define DSI_CMCR_MRDPS_Msk            (0x1UL << DSI_CMCR_MRDPS_Pos)            /*!< 0x01000000 */
8663 #define DSI_CMCR_MRDPS                DSI_CMCR_MRDPS_Msk                       /*!< Maximum Read Packet Size */
8664 
8665 /*******************  Bit definition for DSI_GHCR register  ***************/
8666 #define DSI_GHCR_DT_Pos               (0U)
8667 #define DSI_GHCR_DT_Msk               (0x3FUL << DSI_GHCR_DT_Pos)              /*!< 0x0000003F */
8668 #define DSI_GHCR_DT                   DSI_GHCR_DT_Msk                          /*!< Type */
8669 #define DSI_GHCR_DT0_Pos              (0U)
8670 #define DSI_GHCR_DT0_Msk              (0x1UL << DSI_GHCR_DT0_Pos)              /*!< 0x00000001 */
8671 #define DSI_GHCR_DT0                  DSI_GHCR_DT0_Msk
8672 #define DSI_GHCR_DT1_Pos              (1U)
8673 #define DSI_GHCR_DT1_Msk              (0x1UL << DSI_GHCR_DT1_Pos)              /*!< 0x00000002 */
8674 #define DSI_GHCR_DT1                  DSI_GHCR_DT1_Msk
8675 #define DSI_GHCR_DT2_Pos              (2U)
8676 #define DSI_GHCR_DT2_Msk              (0x1UL << DSI_GHCR_DT2_Pos)              /*!< 0x00000004 */
8677 #define DSI_GHCR_DT2                  DSI_GHCR_DT2_Msk
8678 #define DSI_GHCR_DT3_Pos              (3U)
8679 #define DSI_GHCR_DT3_Msk              (0x1UL << DSI_GHCR_DT3_Pos)              /*!< 0x00000008 */
8680 #define DSI_GHCR_DT3                  DSI_GHCR_DT3_Msk
8681 #define DSI_GHCR_DT4_Pos              (4U)
8682 #define DSI_GHCR_DT4_Msk              (0x1UL << DSI_GHCR_DT4_Pos)              /*!< 0x00000010 */
8683 #define DSI_GHCR_DT4                  DSI_GHCR_DT4_Msk
8684 #define DSI_GHCR_DT5_Pos              (5U)
8685 #define DSI_GHCR_DT5_Msk              (0x1UL << DSI_GHCR_DT5_Pos)              /*!< 0x00000020 */
8686 #define DSI_GHCR_DT5                  DSI_GHCR_DT5_Msk
8687 
8688 #define DSI_GHCR_VCID_Pos             (6U)
8689 #define DSI_GHCR_VCID_Msk             (0x3UL << DSI_GHCR_VCID_Pos)             /*!< 0x000000C0 */
8690 #define DSI_GHCR_VCID                 DSI_GHCR_VCID_Msk                        /*!< Channel */
8691 #define DSI_GHCR_VCID0_Pos            (6U)
8692 #define DSI_GHCR_VCID0_Msk            (0x1UL << DSI_GHCR_VCID0_Pos)            /*!< 0x00000040 */
8693 #define DSI_GHCR_VCID0                DSI_GHCR_VCID0_Msk
8694 #define DSI_GHCR_VCID1_Pos            (7U)
8695 #define DSI_GHCR_VCID1_Msk            (0x1UL << DSI_GHCR_VCID1_Pos)            /*!< 0x00000080 */
8696 #define DSI_GHCR_VCID1                DSI_GHCR_VCID1_Msk
8697 
8698 #define DSI_GHCR_WCLSB_Pos            (8U)
8699 #define DSI_GHCR_WCLSB_Msk            (0xFFUL << DSI_GHCR_WCLSB_Pos)           /*!< 0x0000FF00 */
8700 #define DSI_GHCR_WCLSB                DSI_GHCR_WCLSB_Msk                       /*!< WordCount LSB */
8701 #define DSI_GHCR_WCLSB0_Pos           (8U)
8702 #define DSI_GHCR_WCLSB0_Msk           (0x1UL << DSI_GHCR_WCLSB0_Pos)           /*!< 0x00000100 */
8703 #define DSI_GHCR_WCLSB0               DSI_GHCR_WCLSB0_Msk
8704 #define DSI_GHCR_WCLSB1_Pos           (9U)
8705 #define DSI_GHCR_WCLSB1_Msk           (0x1UL << DSI_GHCR_WCLSB1_Pos)           /*!< 0x00000200 */
8706 #define DSI_GHCR_WCLSB1               DSI_GHCR_WCLSB1_Msk
8707 #define DSI_GHCR_WCLSB2_Pos           (10U)
8708 #define DSI_GHCR_WCLSB2_Msk           (0x1UL << DSI_GHCR_WCLSB2_Pos)           /*!< 0x00000400 */
8709 #define DSI_GHCR_WCLSB2               DSI_GHCR_WCLSB2_Msk
8710 #define DSI_GHCR_WCLSB3_Pos           (11U)
8711 #define DSI_GHCR_WCLSB3_Msk           (0x1UL << DSI_GHCR_WCLSB3_Pos)           /*!< 0x00000800 */
8712 #define DSI_GHCR_WCLSB3               DSI_GHCR_WCLSB3_Msk
8713 #define DSI_GHCR_WCLSB4_Pos           (12U)
8714 #define DSI_GHCR_WCLSB4_Msk           (0x1UL << DSI_GHCR_WCLSB4_Pos)           /*!< 0x00001000 */
8715 #define DSI_GHCR_WCLSB4               DSI_GHCR_WCLSB4_Msk
8716 #define DSI_GHCR_WCLSB5_Pos           (13U)
8717 #define DSI_GHCR_WCLSB5_Msk           (0x1UL << DSI_GHCR_WCLSB5_Pos)           /*!< 0x00002000 */
8718 #define DSI_GHCR_WCLSB5               DSI_GHCR_WCLSB5_Msk
8719 #define DSI_GHCR_WCLSB6_Pos           (14U)
8720 #define DSI_GHCR_WCLSB6_Msk           (0x1UL << DSI_GHCR_WCLSB6_Pos)           /*!< 0x00004000 */
8721 #define DSI_GHCR_WCLSB6               DSI_GHCR_WCLSB6_Msk
8722 #define DSI_GHCR_WCLSB7_Pos           (15U)
8723 #define DSI_GHCR_WCLSB7_Msk           (0x1UL << DSI_GHCR_WCLSB7_Pos)           /*!< 0x00008000 */
8724 #define DSI_GHCR_WCLSB7               DSI_GHCR_WCLSB7_Msk
8725 
8726 #define DSI_GHCR_WCMSB_Pos            (16U)
8727 #define DSI_GHCR_WCMSB_Msk            (0xFFUL << DSI_GHCR_WCMSB_Pos)           /*!< 0x00FF0000 */
8728 #define DSI_GHCR_WCMSB                DSI_GHCR_WCMSB_Msk                       /*!< WordCount MSB */
8729 #define DSI_GHCR_WCMSB0_Pos           (16U)
8730 #define DSI_GHCR_WCMSB0_Msk           (0x1UL << DSI_GHCR_WCMSB0_Pos)           /*!< 0x00010000 */
8731 #define DSI_GHCR_WCMSB0               DSI_GHCR_WCMSB0_Msk
8732 #define DSI_GHCR_WCMSB1_Pos           (17U)
8733 #define DSI_GHCR_WCMSB1_Msk           (0x1UL << DSI_GHCR_WCMSB1_Pos)           /*!< 0x00020000 */
8734 #define DSI_GHCR_WCMSB1               DSI_GHCR_WCMSB1_Msk
8735 #define DSI_GHCR_WCMSB2_Pos           (18U)
8736 #define DSI_GHCR_WCMSB2_Msk           (0x1UL << DSI_GHCR_WCMSB2_Pos)           /*!< 0x00040000 */
8737 #define DSI_GHCR_WCMSB2               DSI_GHCR_WCMSB2_Msk
8738 #define DSI_GHCR_WCMSB3_Pos           (19U)
8739 #define DSI_GHCR_WCMSB3_Msk           (0x1UL << DSI_GHCR_WCMSB3_Pos)           /*!< 0x00080000 */
8740 #define DSI_GHCR_WCMSB3               DSI_GHCR_WCMSB3_Msk
8741 #define DSI_GHCR_WCMSB4_Pos           (20U)
8742 #define DSI_GHCR_WCMSB4_Msk           (0x1UL << DSI_GHCR_WCMSB4_Pos)           /*!< 0x00100000 */
8743 #define DSI_GHCR_WCMSB4               DSI_GHCR_WCMSB4_Msk
8744 #define DSI_GHCR_WCMSB5_Pos           (21U)
8745 #define DSI_GHCR_WCMSB5_Msk           (0x1UL << DSI_GHCR_WCMSB5_Pos)           /*!< 0x00200000 */
8746 #define DSI_GHCR_WCMSB5               DSI_GHCR_WCMSB5_Msk
8747 #define DSI_GHCR_WCMSB6_Pos           (22U)
8748 #define DSI_GHCR_WCMSB6_Msk           (0x1UL << DSI_GHCR_WCMSB6_Pos)           /*!< 0x00400000 */
8749 #define DSI_GHCR_WCMSB6               DSI_GHCR_WCMSB6_Msk
8750 #define DSI_GHCR_WCMSB7_Pos           (23U)
8751 #define DSI_GHCR_WCMSB7_Msk           (0x1UL << DSI_GHCR_WCMSB7_Pos)           /*!< 0x00800000 */
8752 #define DSI_GHCR_WCMSB7               DSI_GHCR_WCMSB7_Msk
8753 
8754 /*******************  Bit definition for DSI_GPDR register  ***************/
8755 #define DSI_GPDR_DATA1_Pos            (0U)
8756 #define DSI_GPDR_DATA1_Msk            (0xFFUL << DSI_GPDR_DATA1_Pos)           /*!< 0x000000FF */
8757 #define DSI_GPDR_DATA1                DSI_GPDR_DATA1_Msk                       /*!< Payload Byte 1 */
8758 #define DSI_GPDR_DATA1_0              (0x01UL << DSI_GPDR_DATA1_Pos)           /*!< 0x00000001 */
8759 #define DSI_GPDR_DATA1_1              (0x02UL << DSI_GPDR_DATA1_Pos)           /*!< 0x00000002 */
8760 #define DSI_GPDR_DATA1_2              (0x04UL << DSI_GPDR_DATA1_Pos)           /*!< 0x00000004 */
8761 #define DSI_GPDR_DATA1_3              (0x08UL << DSI_GPDR_DATA1_Pos)           /*!< 0x00000008 */
8762 #define DSI_GPDR_DATA1_4              (0x10UL << DSI_GPDR_DATA1_Pos)           /*!< 0x00000010 */
8763 #define DSI_GPDR_DATA1_5              (0x20UL << DSI_GPDR_DATA1_Pos)           /*!< 0x00000020 */
8764 #define DSI_GPDR_DATA1_6              (0x40UL << DSI_GPDR_DATA1_Pos)           /*!< 0x00000040 */
8765 #define DSI_GPDR_DATA1_7              (0x80UL << DSI_GPDR_DATA1_Pos)           /*!< 0x00000080 */
8766 
8767 #define DSI_GPDR_DATA2_Pos            (8U)
8768 #define DSI_GPDR_DATA2_Msk            (0xFFUL << DSI_GPDR_DATA2_Pos)           /*!< 0x0000FF00 */
8769 #define DSI_GPDR_DATA2                DSI_GPDR_DATA2_Msk                       /*!< Payload Byte 2 */
8770 #define DSI_GPDR_DATA2_0              (0x01UL << DSI_GPDR_DATA2_Pos)           /*!< 0x00000100 */
8771 #define DSI_GPDR_DATA2_1              (0x02UL << DSI_GPDR_DATA2_Pos)           /*!< 0x00000200 */
8772 #define DSI_GPDR_DATA2_2              (0x04UL << DSI_GPDR_DATA2_Pos)           /*!< 0x00000400 */
8773 #define DSI_GPDR_DATA2_3              (0x08UL << DSI_GPDR_DATA2_Pos)           /*!< 0x00000800 */
8774 #define DSI_GPDR_DATA2_4              (0x10UL << DSI_GPDR_DATA2_Pos)           /*!< 0x00001000 */
8775 #define DSI_GPDR_DATA2_5              (0x20UL << DSI_GPDR_DATA2_Pos)           /*!< 0x00002000 */
8776 #define DSI_GPDR_DATA2_6              (0x40UL << DSI_GPDR_DATA2_Pos)           /*!< 0x00004000 */
8777 #define DSI_GPDR_DATA2_7              (0x80UL << DSI_GPDR_DATA2_Pos)           /*!< 0x00008000 */
8778 
8779 #define DSI_GPDR_DATA3_Pos            (16U)
8780 #define DSI_GPDR_DATA3_Msk            (0xFFUL << DSI_GPDR_DATA3_Pos)           /*!< 0x00FF0000 */
8781 #define DSI_GPDR_DATA3                DSI_GPDR_DATA3_Msk                       /*!< Payload Byte 3 */
8782 #define DSI_GPDR_DATA3_0              (0x01UL << DSI_GPDR_DATA3_Pos)           /*!< 0x00010000 */
8783 #define DSI_GPDR_DATA3_1              (0x02UL << DSI_GPDR_DATA3_Pos)           /*!< 0x00020000 */
8784 #define DSI_GPDR_DATA3_2              (0x04UL << DSI_GPDR_DATA3_Pos)           /*!< 0x00040000 */
8785 #define DSI_GPDR_DATA3_3              (0x08UL << DSI_GPDR_DATA3_Pos)           /*!< 0x00080000 */
8786 #define DSI_GPDR_DATA3_4              (0x10UL << DSI_GPDR_DATA3_Pos)           /*!< 0x00100000 */
8787 #define DSI_GPDR_DATA3_5              (0x20UL << DSI_GPDR_DATA3_Pos)           /*!< 0x00200000 */
8788 #define DSI_GPDR_DATA3_6              (0x40UL << DSI_GPDR_DATA3_Pos)           /*!< 0x00400000 */
8789 #define DSI_GPDR_DATA3_7              (0x80UL << DSI_GPDR_DATA3_Pos)           /*!< 0x00800000 */
8790 
8791 #define DSI_GPDR_DATA4_Pos            (24U)
8792 #define DSI_GPDR_DATA4_Msk            (0xFFUL << DSI_GPDR_DATA4_Pos)           /*!< 0xFF000000 */
8793 #define DSI_GPDR_DATA4                DSI_GPDR_DATA4_Msk                       /*!< Payload Byte 4 */
8794 #define DSI_GPDR_DATA4_0              (0x01UL << DSI_GPDR_DATA4_Pos)           /*!< 0x01000000 */
8795 #define DSI_GPDR_DATA4_1              (0x02UL << DSI_GPDR_DATA4_Pos)           /*!< 0x02000000 */
8796 #define DSI_GPDR_DATA4_2              (0x04UL << DSI_GPDR_DATA4_Pos)           /*!< 0x04000000 */
8797 #define DSI_GPDR_DATA4_3              (0x08UL << DSI_GPDR_DATA4_Pos)           /*!< 0x08000000 */
8798 #define DSI_GPDR_DATA4_4              (0x10UL << DSI_GPDR_DATA4_Pos)           /*!< 0x10000000 */
8799 #define DSI_GPDR_DATA4_5              (0x20UL << DSI_GPDR_DATA4_Pos)           /*!< 0x20000000 */
8800 #define DSI_GPDR_DATA4_6              (0x40UL << DSI_GPDR_DATA4_Pos)           /*!< 0x40000000 */
8801 #define DSI_GPDR_DATA4_7              (0x80UL << DSI_GPDR_DATA4_Pos)           /*!< 0x80000000 */
8802 
8803 /*******************  Bit definition for DSI_GPSR register  ***************/
8804 #define DSI_GPSR_CMDFE_Pos            (0U)
8805 #define DSI_GPSR_CMDFE_Msk            (0x1UL << DSI_GPSR_CMDFE_Pos)            /*!< 0x00000001 */
8806 #define DSI_GPSR_CMDFE                DSI_GPSR_CMDFE_Msk                       /*!< Command FIFO Empty */
8807 #define DSI_GPSR_CMDFF_Pos            (1U)
8808 #define DSI_GPSR_CMDFF_Msk            (0x1UL << DSI_GPSR_CMDFF_Pos)            /*!< 0x00000002 */
8809 #define DSI_GPSR_CMDFF                DSI_GPSR_CMDFF_Msk                       /*!< Command FIFO Full */
8810 #define DSI_GPSR_PWRFE_Pos            (2U)
8811 #define DSI_GPSR_PWRFE_Msk            (0x1UL << DSI_GPSR_PWRFE_Pos)            /*!< 0x00000004 */
8812 #define DSI_GPSR_PWRFE                DSI_GPSR_PWRFE_Msk                       /*!< Payload Write FIFO Empty */
8813 #define DSI_GPSR_PWRFF_Pos            (3U)
8814 #define DSI_GPSR_PWRFF_Msk            (0x1UL << DSI_GPSR_PWRFF_Pos)            /*!< 0x00000008 */
8815 #define DSI_GPSR_PWRFF                DSI_GPSR_PWRFF_Msk                       /*!< Payload Write FIFO Full */
8816 #define DSI_GPSR_PRDFE_Pos            (4U)
8817 #define DSI_GPSR_PRDFE_Msk            (0x1UL << DSI_GPSR_PRDFE_Pos)            /*!< 0x00000010 */
8818 #define DSI_GPSR_PRDFE                DSI_GPSR_PRDFE_Msk                       /*!< Payload Read FIFO Empty */
8819 #define DSI_GPSR_PRDFF_Pos            (5U)
8820 #define DSI_GPSR_PRDFF_Msk            (0x1UL << DSI_GPSR_PRDFF_Pos)            /*!< 0x00000020 */
8821 #define DSI_GPSR_PRDFF                DSI_GPSR_PRDFF_Msk                       /*!< Payload Read FIFO Full */
8822 #define DSI_GPSR_RCB_Pos              (6U)
8823 #define DSI_GPSR_RCB_Msk              (0x1UL << DSI_GPSR_RCB_Pos)              /*!< 0x00000040 */
8824 #define DSI_GPSR_RCB                  DSI_GPSR_RCB_Msk                         /*!< Read Command Busy */
8825 #define DSI_GPSR_CMDBE_Pos            (16U)
8826 #define DSI_GPSR_CMDBE_Msk            (0x1UL << DSI_GPSR_CMDBE_Pos)            /*!< 0x00010000 */
8827 #define DSI_GPSR_CMDBE                DSI_GPSR_CMDBE_Msk                       /*!< Command Buffer Empty */
8828 #define DSI_GPSR_CMDBF_Pos            (17U)
8829 #define DSI_GPSR_CMDBF_Msk            (0x1UL << DSI_GPSR_CMDBF_Pos)            /*!< 0x00020000 */
8830 #define DSI_GPSR_CMDBF                DSI_GPSR_CMDBF_Msk                       /*!< Command Buffer Full */
8831 #define DSI_GPSR_PBE_Pos              (18U)
8832 #define DSI_GPSR_PBE_Msk              (0x1UL << DSI_GPSR_PBE_Pos)              /*!< 0x00040000 */
8833 #define DSI_GPSR_PBE                  DSI_GPSR_PBE_Msk                         /*!< Payload Buffer Empty */
8834 #define DSI_GPSR_PBF_Pos              (19U)
8835 #define DSI_GPSR_PBF_Msk              (0x1UL << DSI_GPSR_PBF_Pos)              /*!< 0x00080000 */
8836 #define DSI_GPSR_PBF                  DSI_GPSR_PBF_Msk                         /*!< Payload Buffer Full */
8837 
8838 /*******************  Bit definition for DSI_TCCR0 register  **************/
8839 #define DSI_TCCR0_LPRX_TOCNT_Pos      (0U)
8840 #define DSI_TCCR0_LPRX_TOCNT_Msk      (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos)   /*!< 0x0000FFFF */
8841 #define DSI_TCCR0_LPRX_TOCNT          DSI_TCCR0_LPRX_TOCNT_Msk                 /*!< Low-power Reception Timeout Counter */
8842 #define DSI_TCCR0_LPRX_TOCNT0_Pos     (0U)
8843 #define DSI_TCCR0_LPRX_TOCNT0_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos)     /*!< 0x00000001 */
8844 #define DSI_TCCR0_LPRX_TOCNT0         DSI_TCCR0_LPRX_TOCNT0_Msk
8845 #define DSI_TCCR0_LPRX_TOCNT1_Pos     (1U)
8846 #define DSI_TCCR0_LPRX_TOCNT1_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos)     /*!< 0x00000002 */
8847 #define DSI_TCCR0_LPRX_TOCNT1         DSI_TCCR0_LPRX_TOCNT1_Msk
8848 #define DSI_TCCR0_LPRX_TOCNT2_Pos     (2U)
8849 #define DSI_TCCR0_LPRX_TOCNT2_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos)     /*!< 0x00000004 */
8850 #define DSI_TCCR0_LPRX_TOCNT2         DSI_TCCR0_LPRX_TOCNT2_Msk
8851 #define DSI_TCCR0_LPRX_TOCNT3_Pos     (3U)
8852 #define DSI_TCCR0_LPRX_TOCNT3_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos)     /*!< 0x00000008 */
8853 #define DSI_TCCR0_LPRX_TOCNT3         DSI_TCCR0_LPRX_TOCNT3_Msk
8854 #define DSI_TCCR0_LPRX_TOCNT4_Pos     (4U)
8855 #define DSI_TCCR0_LPRX_TOCNT4_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos)     /*!< 0x00000010 */
8856 #define DSI_TCCR0_LPRX_TOCNT4         DSI_TCCR0_LPRX_TOCNT4_Msk
8857 #define DSI_TCCR0_LPRX_TOCNT5_Pos     (5U)
8858 #define DSI_TCCR0_LPRX_TOCNT5_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos)     /*!< 0x00000020 */
8859 #define DSI_TCCR0_LPRX_TOCNT5         DSI_TCCR0_LPRX_TOCNT5_Msk
8860 #define DSI_TCCR0_LPRX_TOCNT6_Pos     (6U)
8861 #define DSI_TCCR0_LPRX_TOCNT6_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos)     /*!< 0x00000040 */
8862 #define DSI_TCCR0_LPRX_TOCNT6         DSI_TCCR0_LPRX_TOCNT6_Msk
8863 #define DSI_TCCR0_LPRX_TOCNT7_Pos     (7U)
8864 #define DSI_TCCR0_LPRX_TOCNT7_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos)     /*!< 0x00000080 */
8865 #define DSI_TCCR0_LPRX_TOCNT7         DSI_TCCR0_LPRX_TOCNT7_Msk
8866 #define DSI_TCCR0_LPRX_TOCNT8_Pos     (8U)
8867 #define DSI_TCCR0_LPRX_TOCNT8_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos)     /*!< 0x00000100 */
8868 #define DSI_TCCR0_LPRX_TOCNT8         DSI_TCCR0_LPRX_TOCNT8_Msk
8869 #define DSI_TCCR0_LPRX_TOCNT9_Pos     (9U)
8870 #define DSI_TCCR0_LPRX_TOCNT9_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos)     /*!< 0x00000200 */
8871 #define DSI_TCCR0_LPRX_TOCNT9         DSI_TCCR0_LPRX_TOCNT9_Msk
8872 #define DSI_TCCR0_LPRX_TOCNT10_Pos    (10U)
8873 #define DSI_TCCR0_LPRX_TOCNT10_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos)    /*!< 0x00000400 */
8874 #define DSI_TCCR0_LPRX_TOCNT10        DSI_TCCR0_LPRX_TOCNT10_Msk
8875 #define DSI_TCCR0_LPRX_TOCNT11_Pos    (11U)
8876 #define DSI_TCCR0_LPRX_TOCNT11_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos)    /*!< 0x00000800 */
8877 #define DSI_TCCR0_LPRX_TOCNT11        DSI_TCCR0_LPRX_TOCNT11_Msk
8878 #define DSI_TCCR0_LPRX_TOCNT12_Pos    (12U)
8879 #define DSI_TCCR0_LPRX_TOCNT12_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos)    /*!< 0x00001000 */
8880 #define DSI_TCCR0_LPRX_TOCNT12        DSI_TCCR0_LPRX_TOCNT12_Msk
8881 #define DSI_TCCR0_LPRX_TOCNT13_Pos    (13U)
8882 #define DSI_TCCR0_LPRX_TOCNT13_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos)    /*!< 0x00002000 */
8883 #define DSI_TCCR0_LPRX_TOCNT13        DSI_TCCR0_LPRX_TOCNT13_Msk
8884 #define DSI_TCCR0_LPRX_TOCNT14_Pos    (14U)
8885 #define DSI_TCCR0_LPRX_TOCNT14_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos)    /*!< 0x00004000 */
8886 #define DSI_TCCR0_LPRX_TOCNT14        DSI_TCCR0_LPRX_TOCNT14_Msk
8887 #define DSI_TCCR0_LPRX_TOCNT15_Pos    (15U)
8888 #define DSI_TCCR0_LPRX_TOCNT15_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos)    /*!< 0x00008000 */
8889 #define DSI_TCCR0_LPRX_TOCNT15        DSI_TCCR0_LPRX_TOCNT15_Msk
8890 
8891 #define DSI_TCCR0_HSTX_TOCNT_Pos      (16U)
8892 #define DSI_TCCR0_HSTX_TOCNT_Msk      (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos)   /*!< 0xFFFF0000 */
8893 #define DSI_TCCR0_HSTX_TOCNT          DSI_TCCR0_HSTX_TOCNT_Msk                 /*!< High-Speed Transmission Timeout Counter */
8894 #define DSI_TCCR0_HSTX_TOCNT0_Pos     (16U)
8895 #define DSI_TCCR0_HSTX_TOCNT0_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos)     /*!< 0x00010000 */
8896 #define DSI_TCCR0_HSTX_TOCNT0         DSI_TCCR0_HSTX_TOCNT0_Msk
8897 #define DSI_TCCR0_HSTX_TOCNT1_Pos     (17U)
8898 #define DSI_TCCR0_HSTX_TOCNT1_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos)     /*!< 0x00020000 */
8899 #define DSI_TCCR0_HSTX_TOCNT1         DSI_TCCR0_HSTX_TOCNT1_Msk
8900 #define DSI_TCCR0_HSTX_TOCNT2_Pos     (18U)
8901 #define DSI_TCCR0_HSTX_TOCNT2_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos)     /*!< 0x00040000 */
8902 #define DSI_TCCR0_HSTX_TOCNT2         DSI_TCCR0_HSTX_TOCNT2_Msk
8903 #define DSI_TCCR0_HSTX_TOCNT3_Pos     (19U)
8904 #define DSI_TCCR0_HSTX_TOCNT3_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos)     /*!< 0x00080000 */
8905 #define DSI_TCCR0_HSTX_TOCNT3         DSI_TCCR0_HSTX_TOCNT3_Msk
8906 #define DSI_TCCR0_HSTX_TOCNT4_Pos     (20U)
8907 #define DSI_TCCR0_HSTX_TOCNT4_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos)     /*!< 0x00100000 */
8908 #define DSI_TCCR0_HSTX_TOCNT4         DSI_TCCR0_HSTX_TOCNT4_Msk
8909 #define DSI_TCCR0_HSTX_TOCNT5_Pos     (21U)
8910 #define DSI_TCCR0_HSTX_TOCNT5_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos)     /*!< 0x00200000 */
8911 #define DSI_TCCR0_HSTX_TOCNT5         DSI_TCCR0_HSTX_TOCNT5_Msk
8912 #define DSI_TCCR0_HSTX_TOCNT6_Pos     (22U)
8913 #define DSI_TCCR0_HSTX_TOCNT6_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos)     /*!< 0x00400000 */
8914 #define DSI_TCCR0_HSTX_TOCNT6         DSI_TCCR0_HSTX_TOCNT6_Msk
8915 #define DSI_TCCR0_HSTX_TOCNT7_Pos     (23U)
8916 #define DSI_TCCR0_HSTX_TOCNT7_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos)     /*!< 0x00800000 */
8917 #define DSI_TCCR0_HSTX_TOCNT7         DSI_TCCR0_HSTX_TOCNT7_Msk
8918 #define DSI_TCCR0_HSTX_TOCNT8_Pos     (24U)
8919 #define DSI_TCCR0_HSTX_TOCNT8_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos)     /*!< 0x01000000 */
8920 #define DSI_TCCR0_HSTX_TOCNT8         DSI_TCCR0_HSTX_TOCNT8_Msk
8921 #define DSI_TCCR0_HSTX_TOCNT9_Pos     (25U)
8922 #define DSI_TCCR0_HSTX_TOCNT9_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos)     /*!< 0x02000000 */
8923 #define DSI_TCCR0_HSTX_TOCNT9         DSI_TCCR0_HSTX_TOCNT9_Msk
8924 #define DSI_TCCR0_HSTX_TOCNT10_Pos    (26U)
8925 #define DSI_TCCR0_HSTX_TOCNT10_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos)    /*!< 0x04000000 */
8926 #define DSI_TCCR0_HSTX_TOCNT10        DSI_TCCR0_HSTX_TOCNT10_Msk
8927 #define DSI_TCCR0_HSTX_TOCNT11_Pos    (27U)
8928 #define DSI_TCCR0_HSTX_TOCNT11_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos)    /*!< 0x08000000 */
8929 #define DSI_TCCR0_HSTX_TOCNT11        DSI_TCCR0_HSTX_TOCNT11_Msk
8930 #define DSI_TCCR0_HSTX_TOCNT12_Pos    (28U)
8931 #define DSI_TCCR0_HSTX_TOCNT12_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos)    /*!< 0x10000000 */
8932 #define DSI_TCCR0_HSTX_TOCNT12        DSI_TCCR0_HSTX_TOCNT12_Msk
8933 #define DSI_TCCR0_HSTX_TOCNT13_Pos    (29U)
8934 #define DSI_TCCR0_HSTX_TOCNT13_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos)    /*!< 0x20000000 */
8935 #define DSI_TCCR0_HSTX_TOCNT13        DSI_TCCR0_HSTX_TOCNT13_Msk
8936 #define DSI_TCCR0_HSTX_TOCNT14_Pos    (30U)
8937 #define DSI_TCCR0_HSTX_TOCNT14_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos)    /*!< 0x40000000 */
8938 #define DSI_TCCR0_HSTX_TOCNT14        DSI_TCCR0_HSTX_TOCNT14_Msk
8939 #define DSI_TCCR0_HSTX_TOCNT15_Pos    (31U)
8940 #define DSI_TCCR0_HSTX_TOCNT15_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos)    /*!< 0x80000000 */
8941 #define DSI_TCCR0_HSTX_TOCNT15        DSI_TCCR0_HSTX_TOCNT15_Msk
8942 
8943 /*******************  Bit definition for DSI_TCCR1 register  **************/
8944 #define DSI_TCCR1_HSRD_TOCNT_Pos      (0U)
8945 #define DSI_TCCR1_HSRD_TOCNT_Msk      (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos)   /*!< 0x0000FFFF */
8946 #define DSI_TCCR1_HSRD_TOCNT          DSI_TCCR1_HSRD_TOCNT_Msk                 /*!< High-Speed Read Timeout Counter */
8947 #define DSI_TCCR1_HSRD_TOCNT0_Pos     (0U)
8948 #define DSI_TCCR1_HSRD_TOCNT0_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos)     /*!< 0x00000001 */
8949 #define DSI_TCCR1_HSRD_TOCNT0         DSI_TCCR1_HSRD_TOCNT0_Msk
8950 #define DSI_TCCR1_HSRD_TOCNT1_Pos     (1U)
8951 #define DSI_TCCR1_HSRD_TOCNT1_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos)     /*!< 0x00000002 */
8952 #define DSI_TCCR1_HSRD_TOCNT1         DSI_TCCR1_HSRD_TOCNT1_Msk
8953 #define DSI_TCCR1_HSRD_TOCNT2_Pos     (2U)
8954 #define DSI_TCCR1_HSRD_TOCNT2_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos)     /*!< 0x00000004 */
8955 #define DSI_TCCR1_HSRD_TOCNT2         DSI_TCCR1_HSRD_TOCNT2_Msk
8956 #define DSI_TCCR1_HSRD_TOCNT3_Pos     (3U)
8957 #define DSI_TCCR1_HSRD_TOCNT3_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos)     /*!< 0x00000008 */
8958 #define DSI_TCCR1_HSRD_TOCNT3         DSI_TCCR1_HSRD_TOCNT3_Msk
8959 #define DSI_TCCR1_HSRD_TOCNT4_Pos     (4U)
8960 #define DSI_TCCR1_HSRD_TOCNT4_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos)     /*!< 0x00000010 */
8961 #define DSI_TCCR1_HSRD_TOCNT4         DSI_TCCR1_HSRD_TOCNT4_Msk
8962 #define DSI_TCCR1_HSRD_TOCNT5_Pos     (5U)
8963 #define DSI_TCCR1_HSRD_TOCNT5_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos)     /*!< 0x00000020 */
8964 #define DSI_TCCR1_HSRD_TOCNT5         DSI_TCCR1_HSRD_TOCNT5_Msk
8965 #define DSI_TCCR1_HSRD_TOCNT6_Pos     (6U)
8966 #define DSI_TCCR1_HSRD_TOCNT6_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos)     /*!< 0x00000040 */
8967 #define DSI_TCCR1_HSRD_TOCNT6         DSI_TCCR1_HSRD_TOCNT6_Msk
8968 #define DSI_TCCR1_HSRD_TOCNT7_Pos     (7U)
8969 #define DSI_TCCR1_HSRD_TOCNT7_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos)     /*!< 0x00000080 */
8970 #define DSI_TCCR1_HSRD_TOCNT7         DSI_TCCR1_HSRD_TOCNT7_Msk
8971 #define DSI_TCCR1_HSRD_TOCNT8_Pos     (8U)
8972 #define DSI_TCCR1_HSRD_TOCNT8_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos)     /*!< 0x00000100 */
8973 #define DSI_TCCR1_HSRD_TOCNT8         DSI_TCCR1_HSRD_TOCNT8_Msk
8974 #define DSI_TCCR1_HSRD_TOCNT9_Pos     (9U)
8975 #define DSI_TCCR1_HSRD_TOCNT9_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos)     /*!< 0x00000200 */
8976 #define DSI_TCCR1_HSRD_TOCNT9         DSI_TCCR1_HSRD_TOCNT9_Msk
8977 #define DSI_TCCR1_HSRD_TOCNT10_Pos    (10U)
8978 #define DSI_TCCR1_HSRD_TOCNT10_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos)    /*!< 0x00000400 */
8979 #define DSI_TCCR1_HSRD_TOCNT10        DSI_TCCR1_HSRD_TOCNT10_Msk
8980 #define DSI_TCCR1_HSRD_TOCNT11_Pos    (11U)
8981 #define DSI_TCCR1_HSRD_TOCNT11_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos)    /*!< 0x00000800 */
8982 #define DSI_TCCR1_HSRD_TOCNT11        DSI_TCCR1_HSRD_TOCNT11_Msk
8983 #define DSI_TCCR1_HSRD_TOCNT12_Pos    (12U)
8984 #define DSI_TCCR1_HSRD_TOCNT12_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos)    /*!< 0x00001000 */
8985 #define DSI_TCCR1_HSRD_TOCNT12        DSI_TCCR1_HSRD_TOCNT12_Msk
8986 #define DSI_TCCR1_HSRD_TOCNT13_Pos    (13U)
8987 #define DSI_TCCR1_HSRD_TOCNT13_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos)    /*!< 0x00002000 */
8988 #define DSI_TCCR1_HSRD_TOCNT13        DSI_TCCR1_HSRD_TOCNT13_Msk
8989 #define DSI_TCCR1_HSRD_TOCNT14_Pos    (14U)
8990 #define DSI_TCCR1_HSRD_TOCNT14_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos)    /*!< 0x00004000 */
8991 #define DSI_TCCR1_HSRD_TOCNT14        DSI_TCCR1_HSRD_TOCNT14_Msk
8992 #define DSI_TCCR1_HSRD_TOCNT15_Pos    (15U)
8993 #define DSI_TCCR1_HSRD_TOCNT15_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos)    /*!< 0x00008000 */
8994 #define DSI_TCCR1_HSRD_TOCNT15        DSI_TCCR1_HSRD_TOCNT15_Msk
8995 
8996 /*******************  Bit definition for DSI_TCCR2 register  **************/
8997 #define DSI_TCCR2_LPRD_TOCNT_Pos      (0U)
8998 #define DSI_TCCR2_LPRD_TOCNT_Msk      (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos)   /*!< 0x0000FFFF */
8999 #define DSI_TCCR2_LPRD_TOCNT          DSI_TCCR2_LPRD_TOCNT_Msk                 /*!< Low-Power Read Timeout Counter */
9000 #define DSI_TCCR2_LPRD_TOCNT0_Pos     (0U)
9001 #define DSI_TCCR2_LPRD_TOCNT0_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos)     /*!< 0x00000001 */
9002 #define DSI_TCCR2_LPRD_TOCNT0         DSI_TCCR2_LPRD_TOCNT0_Msk
9003 #define DSI_TCCR2_LPRD_TOCNT1_Pos     (1U)
9004 #define DSI_TCCR2_LPRD_TOCNT1_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos)     /*!< 0x00000002 */
9005 #define DSI_TCCR2_LPRD_TOCNT1         DSI_TCCR2_LPRD_TOCNT1_Msk
9006 #define DSI_TCCR2_LPRD_TOCNT2_Pos     (2U)
9007 #define DSI_TCCR2_LPRD_TOCNT2_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos)     /*!< 0x00000004 */
9008 #define DSI_TCCR2_LPRD_TOCNT2         DSI_TCCR2_LPRD_TOCNT2_Msk
9009 #define DSI_TCCR2_LPRD_TOCNT3_Pos     (3U)
9010 #define DSI_TCCR2_LPRD_TOCNT3_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos)     /*!< 0x00000008 */
9011 #define DSI_TCCR2_LPRD_TOCNT3         DSI_TCCR2_LPRD_TOCNT3_Msk
9012 #define DSI_TCCR2_LPRD_TOCNT4_Pos     (4U)
9013 #define DSI_TCCR2_LPRD_TOCNT4_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos)     /*!< 0x00000010 */
9014 #define DSI_TCCR2_LPRD_TOCNT4         DSI_TCCR2_LPRD_TOCNT4_Msk
9015 #define DSI_TCCR2_LPRD_TOCNT5_Pos     (5U)
9016 #define DSI_TCCR2_LPRD_TOCNT5_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos)     /*!< 0x00000020 */
9017 #define DSI_TCCR2_LPRD_TOCNT5         DSI_TCCR2_LPRD_TOCNT5_Msk
9018 #define DSI_TCCR2_LPRD_TOCNT6_Pos     (6U)
9019 #define DSI_TCCR2_LPRD_TOCNT6_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos)     /*!< 0x00000040 */
9020 #define DSI_TCCR2_LPRD_TOCNT6         DSI_TCCR2_LPRD_TOCNT6_Msk
9021 #define DSI_TCCR2_LPRD_TOCNT7_Pos     (7U)
9022 #define DSI_TCCR2_LPRD_TOCNT7_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos)     /*!< 0x00000080 */
9023 #define DSI_TCCR2_LPRD_TOCNT7         DSI_TCCR2_LPRD_TOCNT7_Msk
9024 #define DSI_TCCR2_LPRD_TOCNT8_Pos     (8U)
9025 #define DSI_TCCR2_LPRD_TOCNT8_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos)     /*!< 0x00000100 */
9026 #define DSI_TCCR2_LPRD_TOCNT8         DSI_TCCR2_LPRD_TOCNT8_Msk
9027 #define DSI_TCCR2_LPRD_TOCNT9_Pos     (9U)
9028 #define DSI_TCCR2_LPRD_TOCNT9_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos)     /*!< 0x00000200 */
9029 #define DSI_TCCR2_LPRD_TOCNT9         DSI_TCCR2_LPRD_TOCNT9_Msk
9030 #define DSI_TCCR2_LPRD_TOCNT10_Pos    (10U)
9031 #define DSI_TCCR2_LPRD_TOCNT10_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos)    /*!< 0x00000400 */
9032 #define DSI_TCCR2_LPRD_TOCNT10        DSI_TCCR2_LPRD_TOCNT10_Msk
9033 #define DSI_TCCR2_LPRD_TOCNT11_Pos    (11U)
9034 #define DSI_TCCR2_LPRD_TOCNT11_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos)    /*!< 0x00000800 */
9035 #define DSI_TCCR2_LPRD_TOCNT11        DSI_TCCR2_LPRD_TOCNT11_Msk
9036 #define DSI_TCCR2_LPRD_TOCNT12_Pos    (12U)
9037 #define DSI_TCCR2_LPRD_TOCNT12_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos)    /*!< 0x00001000 */
9038 #define DSI_TCCR2_LPRD_TOCNT12        DSI_TCCR2_LPRD_TOCNT12_Msk
9039 #define DSI_TCCR2_LPRD_TOCNT13_Pos    (13U)
9040 #define DSI_TCCR2_LPRD_TOCNT13_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos)    /*!< 0x00002000 */
9041 #define DSI_TCCR2_LPRD_TOCNT13        DSI_TCCR2_LPRD_TOCNT13_Msk
9042 #define DSI_TCCR2_LPRD_TOCNT14_Pos    (14U)
9043 #define DSI_TCCR2_LPRD_TOCNT14_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos)    /*!< 0x00004000 */
9044 #define DSI_TCCR2_LPRD_TOCNT14        DSI_TCCR2_LPRD_TOCNT14_Msk
9045 #define DSI_TCCR2_LPRD_TOCNT15_Pos    (15U)
9046 #define DSI_TCCR2_LPRD_TOCNT15_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos)    /*!< 0x00008000 */
9047 #define DSI_TCCR2_LPRD_TOCNT15        DSI_TCCR2_LPRD_TOCNT15_Msk
9048 
9049 /*******************  Bit definition for DSI_TCCR3 register  **************/
9050 #define DSI_TCCR3_HSWR_TOCNT_Pos      (0U)
9051 #define DSI_TCCR3_HSWR_TOCNT_Msk      (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos)   /*!< 0x0000FFFF */
9052 #define DSI_TCCR3_HSWR_TOCNT          DSI_TCCR3_HSWR_TOCNT_Msk                 /*!< High-Speed Write Timeout Counter */
9053 #define DSI_TCCR3_HSWR_TOCNT0_Pos     (0U)
9054 #define DSI_TCCR3_HSWR_TOCNT0_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos)     /*!< 0x00000001 */
9055 #define DSI_TCCR3_HSWR_TOCNT0         DSI_TCCR3_HSWR_TOCNT0_Msk
9056 #define DSI_TCCR3_HSWR_TOCNT1_Pos     (1U)
9057 #define DSI_TCCR3_HSWR_TOCNT1_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos)     /*!< 0x00000002 */
9058 #define DSI_TCCR3_HSWR_TOCNT1         DSI_TCCR3_HSWR_TOCNT1_Msk
9059 #define DSI_TCCR3_HSWR_TOCNT2_Pos     (2U)
9060 #define DSI_TCCR3_HSWR_TOCNT2_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos)     /*!< 0x00000004 */
9061 #define DSI_TCCR3_HSWR_TOCNT2         DSI_TCCR3_HSWR_TOCNT2_Msk
9062 #define DSI_TCCR3_HSWR_TOCNT3_Pos     (3U)
9063 #define DSI_TCCR3_HSWR_TOCNT3_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos)     /*!< 0x00000008 */
9064 #define DSI_TCCR3_HSWR_TOCNT3         DSI_TCCR3_HSWR_TOCNT3_Msk
9065 #define DSI_TCCR3_HSWR_TOCNT4_Pos     (4U)
9066 #define DSI_TCCR3_HSWR_TOCNT4_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos)     /*!< 0x00000010 */
9067 #define DSI_TCCR3_HSWR_TOCNT4         DSI_TCCR3_HSWR_TOCNT4_Msk
9068 #define DSI_TCCR3_HSWR_TOCNT5_Pos     (5U)
9069 #define DSI_TCCR3_HSWR_TOCNT5_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos)     /*!< 0x00000020 */
9070 #define DSI_TCCR3_HSWR_TOCNT5         DSI_TCCR3_HSWR_TOCNT5_Msk
9071 #define DSI_TCCR3_HSWR_TOCNT6_Pos     (6U)
9072 #define DSI_TCCR3_HSWR_TOCNT6_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos)     /*!< 0x00000040 */
9073 #define DSI_TCCR3_HSWR_TOCNT6         DSI_TCCR3_HSWR_TOCNT6_Msk
9074 #define DSI_TCCR3_HSWR_TOCNT7_Pos     (7U)
9075 #define DSI_TCCR3_HSWR_TOCNT7_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos)     /*!< 0x00000080 */
9076 #define DSI_TCCR3_HSWR_TOCNT7         DSI_TCCR3_HSWR_TOCNT7_Msk
9077 #define DSI_TCCR3_HSWR_TOCNT8_Pos     (8U)
9078 #define DSI_TCCR3_HSWR_TOCNT8_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos)     /*!< 0x00000100 */
9079 #define DSI_TCCR3_HSWR_TOCNT8         DSI_TCCR3_HSWR_TOCNT8_Msk
9080 #define DSI_TCCR3_HSWR_TOCNT9_Pos     (9U)
9081 #define DSI_TCCR3_HSWR_TOCNT9_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos)     /*!< 0x00000200 */
9082 #define DSI_TCCR3_HSWR_TOCNT9         DSI_TCCR3_HSWR_TOCNT9_Msk
9083 #define DSI_TCCR3_HSWR_TOCNT10_Pos    (10U)
9084 #define DSI_TCCR3_HSWR_TOCNT10_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos)    /*!< 0x00000400 */
9085 #define DSI_TCCR3_HSWR_TOCNT10        DSI_TCCR3_HSWR_TOCNT10_Msk
9086 #define DSI_TCCR3_HSWR_TOCNT11_Pos    (11U)
9087 #define DSI_TCCR3_HSWR_TOCNT11_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos)    /*!< 0x00000800 */
9088 #define DSI_TCCR3_HSWR_TOCNT11        DSI_TCCR3_HSWR_TOCNT11_Msk
9089 #define DSI_TCCR3_HSWR_TOCNT12_Pos    (12U)
9090 #define DSI_TCCR3_HSWR_TOCNT12_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos)    /*!< 0x00001000 */
9091 #define DSI_TCCR3_HSWR_TOCNT12        DSI_TCCR3_HSWR_TOCNT12_Msk
9092 #define DSI_TCCR3_HSWR_TOCNT13_Pos    (13U)
9093 #define DSI_TCCR3_HSWR_TOCNT13_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos)    /*!< 0x00002000 */
9094 #define DSI_TCCR3_HSWR_TOCNT13        DSI_TCCR3_HSWR_TOCNT13_Msk
9095 #define DSI_TCCR3_HSWR_TOCNT14_Pos    (14U)
9096 #define DSI_TCCR3_HSWR_TOCNT14_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos)    /*!< 0x00004000 */
9097 #define DSI_TCCR3_HSWR_TOCNT14        DSI_TCCR3_HSWR_TOCNT14_Msk
9098 #define DSI_TCCR3_HSWR_TOCNT15_Pos    (15U)
9099 #define DSI_TCCR3_HSWR_TOCNT15_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos)    /*!< 0x00008000 */
9100 #define DSI_TCCR3_HSWR_TOCNT15        DSI_TCCR3_HSWR_TOCNT15_Msk
9101 #define DSI_TCCR3_PM_Pos              (24U)
9102 #define DSI_TCCR3_PM_Msk              (0x1UL << DSI_TCCR3_PM_Pos)              /*!< 0x01000000 */
9103 #define DSI_TCCR3_PM                  DSI_TCCR3_PM_Msk                         /*!< Presp Mode */
9104 
9105 /*******************  Bit definition for DSI_TCCR4 register  **************/
9106 #define DSI_TCCR4_LPWR_TOCNT_Pos      (0U)
9107 #define DSI_TCCR4_LPWR_TOCNT_Msk      (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos)   /*!< 0x0000FFFF */
9108 #define DSI_TCCR4_LPWR_TOCNT          DSI_TCCR4_LPWR_TOCNT_Msk                 /*!< Low-Power Write Timeout Counter */
9109 #define DSI_TCCR4_LPWR_TOCNT0_Pos     (0U)
9110 #define DSI_TCCR4_LPWR_TOCNT0_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos)     /*!< 0x00000001 */
9111 #define DSI_TCCR4_LPWR_TOCNT0         DSI_TCCR4_LPWR_TOCNT0_Msk
9112 #define DSI_TCCR4_LPWR_TOCNT1_Pos     (1U)
9113 #define DSI_TCCR4_LPWR_TOCNT1_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos)     /*!< 0x00000002 */
9114 #define DSI_TCCR4_LPWR_TOCNT1         DSI_TCCR4_LPWR_TOCNT1_Msk
9115 #define DSI_TCCR4_LPWR_TOCNT2_Pos     (2U)
9116 #define DSI_TCCR4_LPWR_TOCNT2_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos)     /*!< 0x00000004 */
9117 #define DSI_TCCR4_LPWR_TOCNT2         DSI_TCCR4_LPWR_TOCNT2_Msk
9118 #define DSI_TCCR4_LPWR_TOCNT3_Pos     (3U)
9119 #define DSI_TCCR4_LPWR_TOCNT3_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos)     /*!< 0x00000008 */
9120 #define DSI_TCCR4_LPWR_TOCNT3         DSI_TCCR4_LPWR_TOCNT3_Msk
9121 #define DSI_TCCR4_LPWR_TOCNT4_Pos     (4U)
9122 #define DSI_TCCR4_LPWR_TOCNT4_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos)     /*!< 0x00000010 */
9123 #define DSI_TCCR4_LPWR_TOCNT4         DSI_TCCR4_LPWR_TOCNT4_Msk
9124 #define DSI_TCCR4_LPWR_TOCNT5_Pos     (5U)
9125 #define DSI_TCCR4_LPWR_TOCNT5_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos)     /*!< 0x00000020 */
9126 #define DSI_TCCR4_LPWR_TOCNT5         DSI_TCCR4_LPWR_TOCNT5_Msk
9127 #define DSI_TCCR4_LPWR_TOCNT6_Pos     (6U)
9128 #define DSI_TCCR4_LPWR_TOCNT6_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos)     /*!< 0x00000040 */
9129 #define DSI_TCCR4_LPWR_TOCNT6         DSI_TCCR4_LPWR_TOCNT6_Msk
9130 #define DSI_TCCR4_LPWR_TOCNT7_Pos     (7U)
9131 #define DSI_TCCR4_LPWR_TOCNT7_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos)     /*!< 0x00000080 */
9132 #define DSI_TCCR4_LPWR_TOCNT7         DSI_TCCR4_LPWR_TOCNT7_Msk
9133 #define DSI_TCCR4_LPWR_TOCNT8_Pos     (8U)
9134 #define DSI_TCCR4_LPWR_TOCNT8_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos)     /*!< 0x00000100 */
9135 #define DSI_TCCR4_LPWR_TOCNT8         DSI_TCCR4_LPWR_TOCNT8_Msk
9136 #define DSI_TCCR4_LPWR_TOCNT9_Pos     (9U)
9137 #define DSI_TCCR4_LPWR_TOCNT9_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos)     /*!< 0x00000200 */
9138 #define DSI_TCCR4_LPWR_TOCNT9         DSI_TCCR4_LPWR_TOCNT9_Msk
9139 #define DSI_TCCR4_LPWR_TOCNT10_Pos    (10U)
9140 #define DSI_TCCR4_LPWR_TOCNT10_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos)    /*!< 0x00000400 */
9141 #define DSI_TCCR4_LPWR_TOCNT10        DSI_TCCR4_LPWR_TOCNT10_Msk
9142 #define DSI_TCCR4_LPWR_TOCNT11_Pos    (11U)
9143 #define DSI_TCCR4_LPWR_TOCNT11_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos)    /*!< 0x00000800 */
9144 #define DSI_TCCR4_LPWR_TOCNT11        DSI_TCCR4_LPWR_TOCNT11_Msk
9145 #define DSI_TCCR4_LPWR_TOCNT12_Pos    (12U)
9146 #define DSI_TCCR4_LPWR_TOCNT12_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos)    /*!< 0x00001000 */
9147 #define DSI_TCCR4_LPWR_TOCNT12        DSI_TCCR4_LPWR_TOCNT12_Msk
9148 #define DSI_TCCR4_LPWR_TOCNT13_Pos    (13U)
9149 #define DSI_TCCR4_LPWR_TOCNT13_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos)    /*!< 0x00002000 */
9150 #define DSI_TCCR4_LPWR_TOCNT13        DSI_TCCR4_LPWR_TOCNT13_Msk
9151 #define DSI_TCCR4_LPWR_TOCNT14_Pos    (14U)
9152 #define DSI_TCCR4_LPWR_TOCNT14_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos)    /*!< 0x00004000 */
9153 #define DSI_TCCR4_LPWR_TOCNT14        DSI_TCCR4_LPWR_TOCNT14_Msk
9154 #define DSI_TCCR4_LPWR_TOCNT15_Pos    (15U)
9155 #define DSI_TCCR4_LPWR_TOCNT15_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos)    /*!< 0x00008000 */
9156 #define DSI_TCCR4_LPWR_TOCNT15        DSI_TCCR4_LPWR_TOCNT15_Msk
9157 
9158 /*******************  Bit definition for DSI_TCCR5 register  **************/
9159 #define DSI_TCCR5_BTA_TOCNT_Pos       (0U)
9160 #define DSI_TCCR5_BTA_TOCNT_Msk       (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos)    /*!< 0x0000FFFF */
9161 #define DSI_TCCR5_BTA_TOCNT           DSI_TCCR5_BTA_TOCNT_Msk                  /*!< Bus-Turn-Around Timeout Counter */
9162 #define DSI_TCCR5_BTA_TOCNT0_Pos      (0U)
9163 #define DSI_TCCR5_BTA_TOCNT0_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos)      /*!< 0x00000001 */
9164 #define DSI_TCCR5_BTA_TOCNT0          DSI_TCCR5_BTA_TOCNT0_Msk
9165 #define DSI_TCCR5_BTA_TOCNT1_Pos      (1U)
9166 #define DSI_TCCR5_BTA_TOCNT1_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos)      /*!< 0x00000002 */
9167 #define DSI_TCCR5_BTA_TOCNT1          DSI_TCCR5_BTA_TOCNT1_Msk
9168 #define DSI_TCCR5_BTA_TOCNT2_Pos      (2U)
9169 #define DSI_TCCR5_BTA_TOCNT2_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos)      /*!< 0x00000004 */
9170 #define DSI_TCCR5_BTA_TOCNT2          DSI_TCCR5_BTA_TOCNT2_Msk
9171 #define DSI_TCCR5_BTA_TOCNT3_Pos      (3U)
9172 #define DSI_TCCR5_BTA_TOCNT3_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos)      /*!< 0x00000008 */
9173 #define DSI_TCCR5_BTA_TOCNT3          DSI_TCCR5_BTA_TOCNT3_Msk
9174 #define DSI_TCCR5_BTA_TOCNT4_Pos      (4U)
9175 #define DSI_TCCR5_BTA_TOCNT4_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos)      /*!< 0x00000010 */
9176 #define DSI_TCCR5_BTA_TOCNT4          DSI_TCCR5_BTA_TOCNT4_Msk
9177 #define DSI_TCCR5_BTA_TOCNT5_Pos      (5U)
9178 #define DSI_TCCR5_BTA_TOCNT5_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos)      /*!< 0x00000020 */
9179 #define DSI_TCCR5_BTA_TOCNT5          DSI_TCCR5_BTA_TOCNT5_Msk
9180 #define DSI_TCCR5_BTA_TOCNT6_Pos      (6U)
9181 #define DSI_TCCR5_BTA_TOCNT6_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos)      /*!< 0x00000040 */
9182 #define DSI_TCCR5_BTA_TOCNT6          DSI_TCCR5_BTA_TOCNT6_Msk
9183 #define DSI_TCCR5_BTA_TOCNT7_Pos      (7U)
9184 #define DSI_TCCR5_BTA_TOCNT7_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos)      /*!< 0x00000080 */
9185 #define DSI_TCCR5_BTA_TOCNT7          DSI_TCCR5_BTA_TOCNT7_Msk
9186 #define DSI_TCCR5_BTA_TOCNT8_Pos      (8U)
9187 #define DSI_TCCR5_BTA_TOCNT8_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos)      /*!< 0x00000100 */
9188 #define DSI_TCCR5_BTA_TOCNT8          DSI_TCCR5_BTA_TOCNT8_Msk
9189 #define DSI_TCCR5_BTA_TOCNT9_Pos      (9U)
9190 #define DSI_TCCR5_BTA_TOCNT9_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos)      /*!< 0x00000200 */
9191 #define DSI_TCCR5_BTA_TOCNT9          DSI_TCCR5_BTA_TOCNT9_Msk
9192 #define DSI_TCCR5_BTA_TOCNT10_Pos     (10U)
9193 #define DSI_TCCR5_BTA_TOCNT10_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos)     /*!< 0x00000400 */
9194 #define DSI_TCCR5_BTA_TOCNT10         DSI_TCCR5_BTA_TOCNT10_Msk
9195 #define DSI_TCCR5_BTA_TOCNT11_Pos     (11U)
9196 #define DSI_TCCR5_BTA_TOCNT11_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos)     /*!< 0x00000800 */
9197 #define DSI_TCCR5_BTA_TOCNT11         DSI_TCCR5_BTA_TOCNT11_Msk
9198 #define DSI_TCCR5_BTA_TOCNT12_Pos     (12U)
9199 #define DSI_TCCR5_BTA_TOCNT12_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos)     /*!< 0x00001000 */
9200 #define DSI_TCCR5_BTA_TOCNT12         DSI_TCCR5_BTA_TOCNT12_Msk
9201 #define DSI_TCCR5_BTA_TOCNT13_Pos     (13U)
9202 #define DSI_TCCR5_BTA_TOCNT13_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos)     /*!< 0x00002000 */
9203 #define DSI_TCCR5_BTA_TOCNT13         DSI_TCCR5_BTA_TOCNT13_Msk
9204 #define DSI_TCCR5_BTA_TOCNT14_Pos     (14U)
9205 #define DSI_TCCR5_BTA_TOCNT14_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos)     /*!< 0x00004000 */
9206 #define DSI_TCCR5_BTA_TOCNT14         DSI_TCCR5_BTA_TOCNT14_Msk
9207 #define DSI_TCCR5_BTA_TOCNT15_Pos     (15U)
9208 #define DSI_TCCR5_BTA_TOCNT15_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos)     /*!< 0x00008000 */
9209 #define DSI_TCCR5_BTA_TOCNT15         DSI_TCCR5_BTA_TOCNT15_Msk
9210 
9211 /*******************  Bit definition for DSI_CLCR register  ***************/
9212 #define DSI_CLCR_DPCC_Pos             (0U)
9213 #define DSI_CLCR_DPCC_Msk             (0x1UL << DSI_CLCR_DPCC_Pos)             /*!< 0x00000001 */
9214 #define DSI_CLCR_DPCC                 DSI_CLCR_DPCC_Msk                        /*!< D-PHY Clock Control */
9215 #define DSI_CLCR_ACR_Pos              (1U)
9216 #define DSI_CLCR_ACR_Msk              (0x1UL << DSI_CLCR_ACR_Pos)              /*!< 0x00000002 */
9217 #define DSI_CLCR_ACR                  DSI_CLCR_ACR_Msk                         /*!< Automatic Clocklane Control */
9218 
9219 /*******************  Bit definition for DSI_CLTCR register  **************/
9220 #define DSI_CLTCR_LP2HS_TIME_Pos      (0U)
9221 #define DSI_CLTCR_LP2HS_TIME_Msk      (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos)    /*!< 0x000003FF */
9222 #define DSI_CLTCR_LP2HS_TIME          DSI_CLTCR_LP2HS_TIME_Msk                 /*!< Low-Power to High-Speed Time */
9223 #define DSI_CLTCR_LP2HS_TIME0_Pos     (0U)
9224 #define DSI_CLTCR_LP2HS_TIME0_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos)     /*!< 0x00000001 */
9225 #define DSI_CLTCR_LP2HS_TIME0         DSI_CLTCR_LP2HS_TIME0_Msk
9226 #define DSI_CLTCR_LP2HS_TIME1_Pos     (1U)
9227 #define DSI_CLTCR_LP2HS_TIME1_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos)     /*!< 0x00000002 */
9228 #define DSI_CLTCR_LP2HS_TIME1         DSI_CLTCR_LP2HS_TIME1_Msk
9229 #define DSI_CLTCR_LP2HS_TIME2_Pos     (2U)
9230 #define DSI_CLTCR_LP2HS_TIME2_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos)     /*!< 0x00000004 */
9231 #define DSI_CLTCR_LP2HS_TIME2         DSI_CLTCR_LP2HS_TIME2_Msk
9232 #define DSI_CLTCR_LP2HS_TIME3_Pos     (3U)
9233 #define DSI_CLTCR_LP2HS_TIME3_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos)     /*!< 0x00000008 */
9234 #define DSI_CLTCR_LP2HS_TIME3         DSI_CLTCR_LP2HS_TIME3_Msk
9235 #define DSI_CLTCR_LP2HS_TIME4_Pos     (4U)
9236 #define DSI_CLTCR_LP2HS_TIME4_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos)     /*!< 0x00000010 */
9237 #define DSI_CLTCR_LP2HS_TIME4         DSI_CLTCR_LP2HS_TIME4_Msk
9238 #define DSI_CLTCR_LP2HS_TIME5_Pos     (5U)
9239 #define DSI_CLTCR_LP2HS_TIME5_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos)     /*!< 0x00000020 */
9240 #define DSI_CLTCR_LP2HS_TIME5         DSI_CLTCR_LP2HS_TIME5_Msk
9241 #define DSI_CLTCR_LP2HS_TIME6_Pos     (6U)
9242 #define DSI_CLTCR_LP2HS_TIME6_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos)     /*!< 0x00000040 */
9243 #define DSI_CLTCR_LP2HS_TIME6         DSI_CLTCR_LP2HS_TIME6_Msk
9244 #define DSI_CLTCR_LP2HS_TIME7_Pos     (7U)
9245 #define DSI_CLTCR_LP2HS_TIME7_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos)     /*!< 0x00000080 */
9246 #define DSI_CLTCR_LP2HS_TIME7         DSI_CLTCR_LP2HS_TIME7_Msk
9247 #define DSI_CLTCR_LP2HS_TIME8_Pos     (8U)
9248 #define DSI_CLTCR_LP2HS_TIME8_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos)     /*!< 0x00000100 */
9249 #define DSI_CLTCR_LP2HS_TIME8         DSI_CLTCR_LP2HS_TIME8_Msk
9250 #define DSI_CLTCR_LP2HS_TIME9_Pos     (9U)
9251 #define DSI_CLTCR_LP2HS_TIME9_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos)     /*!< 0x00000200 */
9252 #define DSI_CLTCR_LP2HS_TIME9         DSI_CLTCR_LP2HS_TIME9_Msk
9253 #define DSI_CLTCR_HS2LP_TIME_Pos      (16U)
9254 #define DSI_CLTCR_HS2LP_TIME_Msk      (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos)    /*!< 0x03FF0000 */
9255 #define DSI_CLTCR_HS2LP_TIME          DSI_CLTCR_HS2LP_TIME_Msk                 /*!< High-Speed to Low-Power Time */
9256 #define DSI_CLTCR_HS2LP_TIME0_Pos     (16U)
9257 #define DSI_CLTCR_HS2LP_TIME0_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos)     /*!< 0x00010000 */
9258 #define DSI_CLTCR_HS2LP_TIME0         DSI_CLTCR_HS2LP_TIME0_Msk
9259 #define DSI_CLTCR_HS2LP_TIME1_Pos     (17U)
9260 #define DSI_CLTCR_HS2LP_TIME1_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos)     /*!< 0x00020000 */
9261 #define DSI_CLTCR_HS2LP_TIME1         DSI_CLTCR_HS2LP_TIME1_Msk
9262 #define DSI_CLTCR_HS2LP_TIME2_Pos     (18U)
9263 #define DSI_CLTCR_HS2LP_TIME2_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos)     /*!< 0x00040000 */
9264 #define DSI_CLTCR_HS2LP_TIME2         DSI_CLTCR_HS2LP_TIME2_Msk
9265 #define DSI_CLTCR_HS2LP_TIME3_Pos     (19U)
9266 #define DSI_CLTCR_HS2LP_TIME3_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos)     /*!< 0x00080000 */
9267 #define DSI_CLTCR_HS2LP_TIME3         DSI_CLTCR_HS2LP_TIME3_Msk
9268 #define DSI_CLTCR_HS2LP_TIME4_Pos     (20U)
9269 #define DSI_CLTCR_HS2LP_TIME4_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos)     /*!< 0x00100000 */
9270 #define DSI_CLTCR_HS2LP_TIME4         DSI_CLTCR_HS2LP_TIME4_Msk
9271 #define DSI_CLTCR_HS2LP_TIME5_Pos     (21U)
9272 #define DSI_CLTCR_HS2LP_TIME5_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos)     /*!< 0x00200000 */
9273 #define DSI_CLTCR_HS2LP_TIME5         DSI_CLTCR_HS2LP_TIME5_Msk
9274 #define DSI_CLTCR_HS2LP_TIME6_Pos     (22U)
9275 #define DSI_CLTCR_HS2LP_TIME6_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos)     /*!< 0x00400000 */
9276 #define DSI_CLTCR_HS2LP_TIME6         DSI_CLTCR_HS2LP_TIME6_Msk
9277 #define DSI_CLTCR_HS2LP_TIME7_Pos     (23U)
9278 #define DSI_CLTCR_HS2LP_TIME7_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos)     /*!< 0x00800000 */
9279 #define DSI_CLTCR_HS2LP_TIME7         DSI_CLTCR_HS2LP_TIME7_Msk
9280 #define DSI_CLTCR_HS2LP_TIME8_Pos     (24U)
9281 #define DSI_CLTCR_HS2LP_TIME8_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos)     /*!< 0x01000000 */
9282 #define DSI_CLTCR_HS2LP_TIME8         DSI_CLTCR_HS2LP_TIME8_Msk
9283 #define DSI_CLTCR_HS2LP_TIME9_Pos     (25U)
9284 #define DSI_CLTCR_HS2LP_TIME9_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos)     /*!< 0x02000000 */
9285 #define DSI_CLTCR_HS2LP_TIME9         DSI_CLTCR_HS2LP_TIME9_Msk
9286 
9287 /*******************  Bit definition for DSI_DLTCR register  **************/
9288 #define DSI_DLTCR_LP2HS_TIME_Pos      (0U)
9289 #define DSI_DLTCR_LP2HS_TIME_Msk      (0x3FFUL << DSI_DLTCR_LP2HS_TIME_Pos)    /*!< 0x000003FF */
9290 #define DSI_DLTCR_LP2HS_TIME          DSI_DLTCR_LP2HS_TIME_Msk                 /*!< Low-Power To High-Speed Time */
9291 #define DSI_DLTCR_LP2HS_TIME0_Pos     (0U)
9292 #define DSI_DLTCR_LP2HS_TIME0_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos)     /*!< 0x00000001 */
9293 #define DSI_DLTCR_LP2HS_TIME0         DSI_DLTCR_LP2HS_TIME0_Msk
9294 #define DSI_DLTCR_LP2HS_TIME1_Pos     (1U)
9295 #define DSI_DLTCR_LP2HS_TIME1_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos)     /*!< 0x00000002 */
9296 #define DSI_DLTCR_LP2HS_TIME1         DSI_DLTCR_LP2HS_TIME1_Msk
9297 #define DSI_DLTCR_LP2HS_TIME2_Pos     (2U)
9298 #define DSI_DLTCR_LP2HS_TIME2_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos)     /*!< 0x00000004 */
9299 #define DSI_DLTCR_LP2HS_TIME2         DSI_DLTCR_LP2HS_TIME2_Msk
9300 #define DSI_DLTCR_LP2HS_TIME3_Pos     (3U)
9301 #define DSI_DLTCR_LP2HS_TIME3_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos)     /*!< 0x00000008 */
9302 #define DSI_DLTCR_LP2HS_TIME3         DSI_DLTCR_LP2HS_TIME3_Msk
9303 #define DSI_DLTCR_LP2HS_TIME4_Pos     (4U)
9304 #define DSI_DLTCR_LP2HS_TIME4_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos)     /*!< 0x00000010 */
9305 #define DSI_DLTCR_LP2HS_TIME4         DSI_DLTCR_LP2HS_TIME4_Msk
9306 #define DSI_DLTCR_LP2HS_TIME5_Pos     (5U)
9307 #define DSI_DLTCR_LP2HS_TIME5_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos)     /*!< 0x00000020 */
9308 #define DSI_DLTCR_LP2HS_TIME5         DSI_DLTCR_LP2HS_TIME5_Msk
9309 #define DSI_DLTCR_LP2HS_TIME6_Pos     (6U)
9310 #define DSI_DLTCR_LP2HS_TIME6_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos)     /*!< 0x00000040 */
9311 #define DSI_DLTCR_LP2HS_TIME6         DSI_DLTCR_LP2HS_TIME6_Msk
9312 #define DSI_DLTCR_LP2HS_TIME7_Pos     (7U)
9313 #define DSI_DLTCR_LP2HS_TIME7_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos)     /*!< 0x00000080 */
9314 #define DSI_DLTCR_LP2HS_TIME7         DSI_DLTCR_LP2HS_TIME7_Msk
9315 #define DSI_DLTCR_LP2HS_TIME8_Pos     (8U)
9316 #define DSI_DLTCR_LP2HS_TIME8_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME8_Pos)     /*!< 0x00000100 */
9317 #define DSI_DLTCR_LP2HS_TIME8         DSI_DLTCR_LP2HS_TIME8_Msk
9318 #define DSI_DLTCR_LP2HS_TIME9_Pos     (9U)
9319 #define DSI_DLTCR_LP2HS_TIME9_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME9_Pos)     /*!< 0x00000200 */
9320 #define DSI_DLTCR_LP2HS_TIME9         DSI_DLTCR_LP2HS_TIME9_Msk
9321 #define DSI_DLTCR_HS2LP_TIME_Pos      (16U)
9322 #define DSI_DLTCR_HS2LP_TIME_Msk      (0x3FFUL << DSI_DLTCR_HS2LP_TIME_Pos)    /*!< 0x03FF0000 */
9323 #define DSI_DLTCR_HS2LP_TIME          DSI_DLTCR_HS2LP_TIME_Msk                 /*!< High-Speed To Low-Power Time */
9324 #define DSI_DLTCR_HS2LP_TIME0_Pos     (16U)
9325 #define DSI_DLTCR_HS2LP_TIME0_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos)     /*!< 0x00010000 */
9326 #define DSI_DLTCR_HS2LP_TIME0         DSI_DLTCR_HS2LP_TIME0_Msk
9327 #define DSI_DLTCR_HS2LP_TIME1_Pos     (17U)
9328 #define DSI_DLTCR_HS2LP_TIME1_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos)     /*!< 0x00020000 */
9329 #define DSI_DLTCR_HS2LP_TIME1         DSI_DLTCR_HS2LP_TIME1_Msk
9330 #define DSI_DLTCR_HS2LP_TIME2_Pos     (18U)
9331 #define DSI_DLTCR_HS2LP_TIME2_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos)     /*!< 0x00040000 */
9332 #define DSI_DLTCR_HS2LP_TIME2         DSI_DLTCR_HS2LP_TIME2_Msk
9333 #define DSI_DLTCR_HS2LP_TIME3_Pos     (19U)
9334 #define DSI_DLTCR_HS2LP_TIME3_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos)     /*!< 0x00080000 */
9335 #define DSI_DLTCR_HS2LP_TIME3         DSI_DLTCR_HS2LP_TIME3_Msk
9336 #define DSI_DLTCR_HS2LP_TIME4_Pos     (20U)
9337 #define DSI_DLTCR_HS2LP_TIME4_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos)     /*!< 0x00100000 */
9338 #define DSI_DLTCR_HS2LP_TIME4         DSI_DLTCR_HS2LP_TIME4_Msk
9339 #define DSI_DLTCR_HS2LP_TIME5_Pos     (21U)
9340 #define DSI_DLTCR_HS2LP_TIME5_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos)     /*!< 0x00200000 */
9341 #define DSI_DLTCR_HS2LP_TIME5         DSI_DLTCR_HS2LP_TIME5_Msk
9342 #define DSI_DLTCR_HS2LP_TIME6_Pos     (22U)
9343 #define DSI_DLTCR_HS2LP_TIME6_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos)     /*!< 0x00400000 */
9344 #define DSI_DLTCR_HS2LP_TIME6         DSI_DLTCR_HS2LP_TIME6_Msk
9345 #define DSI_DLTCR_HS2LP_TIME7_Pos     (23U)
9346 #define DSI_DLTCR_HS2LP_TIME7_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos)     /*!< 0x00800000 */
9347 #define DSI_DLTCR_HS2LP_TIME7         DSI_DLTCR_HS2LP_TIME7_Msk
9348 #define DSI_DLTCR_HS2LP_TIME8_Pos     (24U)
9349 #define DSI_DLTCR_HS2LP_TIME8_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME8_Pos)     /*!< 0x01000000 */
9350 #define DSI_DLTCR_HS2LP_TIME8         DSI_DLTCR_HS2LP_TIME8_Msk
9351 #define DSI_DLTCR_HS2LP_TIME9_Pos     (25U)
9352 #define DSI_DLTCR_HS2LP_TIME9_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME9_Pos)     /*!< 0x02000000 */
9353 #define DSI_DLTCR_HS2LP_TIME9         DSI_DLTCR_HS2LP_TIME9_Msk
9354 
9355 /*******************  Bit definition for DSI_PCTLR register  **************/
9356 #define DSI_PCTLR_DEN_Pos             (1U)
9357 #define DSI_PCTLR_DEN_Msk             (0x1UL << DSI_PCTLR_DEN_Pos)             /*!< 0x00000002 */
9358 #define DSI_PCTLR_DEN                 DSI_PCTLR_DEN_Msk                        /*!< Digital Enable */
9359 #define DSI_PCTLR_CKE_Pos             (2U)
9360 #define DSI_PCTLR_CKE_Msk             (0x1UL << DSI_PCTLR_CKE_Pos)             /*!< 0x00000004 */
9361 #define DSI_PCTLR_CKE                 DSI_PCTLR_CKE_Msk                        /*!< Clock Enable */
9362 
9363 /*******************  Bit definition for DSI_PCONFR register  *************/
9364 #define DSI_PCONFR_NL_Pos             (0U)
9365 #define DSI_PCONFR_NL_Msk             (0x3UL << DSI_PCONFR_NL_Pos)             /*!< 0x00000003 */
9366 #define DSI_PCONFR_NL                 DSI_PCONFR_NL_Msk                        /*!< Number of Lanes */
9367 #define DSI_PCONFR_NL0_Pos            (0U)
9368 #define DSI_PCONFR_NL0_Msk            (0x1UL << DSI_PCONFR_NL0_Pos)            /*!< 0x00000001 */
9369 #define DSI_PCONFR_NL0                DSI_PCONFR_NL0_Msk
9370 #define DSI_PCONFR_NL1_Pos            (1U)
9371 #define DSI_PCONFR_NL1_Msk            (0x1UL << DSI_PCONFR_NL1_Pos)            /*!< 0x00000002 */
9372 #define DSI_PCONFR_NL1                DSI_PCONFR_NL1_Msk
9373 
9374 #define DSI_PCONFR_SW_TIME_Pos        (8U)
9375 #define DSI_PCONFR_SW_TIME_Msk        (0xFFUL << DSI_PCONFR_SW_TIME_Pos)       /*!< 0x0000FF00 */
9376 #define DSI_PCONFR_SW_TIME            DSI_PCONFR_SW_TIME_Msk                   /*!< Stop Wait Time */
9377 #define DSI_PCONFR_SW_TIME0_Pos       (8U)
9378 #define DSI_PCONFR_SW_TIME0_Msk       (0x1UL << DSI_PCONFR_SW_TIME0_Pos)       /*!< 0x00000100 */
9379 #define DSI_PCONFR_SW_TIME0           DSI_PCONFR_SW_TIME0_Msk
9380 #define DSI_PCONFR_SW_TIME1_Pos       (9U)
9381 #define DSI_PCONFR_SW_TIME1_Msk       (0x1UL << DSI_PCONFR_SW_TIME1_Pos)       /*!< 0x00000200 */
9382 #define DSI_PCONFR_SW_TIME1           DSI_PCONFR_SW_TIME1_Msk
9383 #define DSI_PCONFR_SW_TIME2_Pos       (10U)
9384 #define DSI_PCONFR_SW_TIME2_Msk       (0x1UL << DSI_PCONFR_SW_TIME2_Pos)       /*!< 0x00000400 */
9385 #define DSI_PCONFR_SW_TIME2           DSI_PCONFR_SW_TIME2_Msk
9386 #define DSI_PCONFR_SW_TIME3_Pos       (11U)
9387 #define DSI_PCONFR_SW_TIME3_Msk       (0x1UL << DSI_PCONFR_SW_TIME3_Pos)       /*!< 0x00000800 */
9388 #define DSI_PCONFR_SW_TIME3           DSI_PCONFR_SW_TIME3_Msk
9389 #define DSI_PCONFR_SW_TIME4_Pos       (12U)
9390 #define DSI_PCONFR_SW_TIME4_Msk       (0x1UL << DSI_PCONFR_SW_TIME4_Pos)       /*!< 0x00001000 */
9391 #define DSI_PCONFR_SW_TIME4           DSI_PCONFR_SW_TIME4_Msk
9392 #define DSI_PCONFR_SW_TIME5_Pos       (13U)
9393 #define DSI_PCONFR_SW_TIME5_Msk       (0x1UL << DSI_PCONFR_SW_TIME5_Pos)       /*!< 0x00002000 */
9394 #define DSI_PCONFR_SW_TIME5           DSI_PCONFR_SW_TIME5_Msk
9395 #define DSI_PCONFR_SW_TIME6_Pos       (14U)
9396 #define DSI_PCONFR_SW_TIME6_Msk       (0x1UL << DSI_PCONFR_SW_TIME6_Pos)       /*!< 0x00004000 */
9397 #define DSI_PCONFR_SW_TIME6           DSI_PCONFR_SW_TIME6_Msk
9398 #define DSI_PCONFR_SW_TIME7_Pos       (15U)
9399 #define DSI_PCONFR_SW_TIME7_Msk       (0x1UL << DSI_PCONFR_SW_TIME7_Pos)       /*!< 0x00008000 */
9400 #define DSI_PCONFR_SW_TIME7           DSI_PCONFR_SW_TIME7_Msk
9401 
9402 /*******************  Bit definition for DSI_PUCR register  ***************/
9403 #define DSI_PUCR_URCL_Pos             (0U)
9404 #define DSI_PUCR_URCL_Msk             (0x1UL << DSI_PUCR_URCL_Pos)             /*!< 0x00000001 */
9405 #define DSI_PUCR_URCL                 DSI_PUCR_URCL_Msk                        /*!< ULPS Request on Clock Lane */
9406 #define DSI_PUCR_UECL_Pos             (1U)
9407 #define DSI_PUCR_UECL_Msk             (0x1UL << DSI_PUCR_UECL_Pos)             /*!< 0x00000002 */
9408 #define DSI_PUCR_UECL                 DSI_PUCR_UECL_Msk                        /*!< ULPS Exit on Clock Lane */
9409 #define DSI_PUCR_URDL_Pos             (2U)
9410 #define DSI_PUCR_URDL_Msk             (0x1UL << DSI_PUCR_URDL_Pos)             /*!< 0x00000004 */
9411 #define DSI_PUCR_URDL                 DSI_PUCR_URDL_Msk                        /*!< ULPS Request on Data Lane */
9412 #define DSI_PUCR_UEDL_Pos             (3U)
9413 #define DSI_PUCR_UEDL_Msk             (0x1UL << DSI_PUCR_UEDL_Pos)             /*!< 0x00000008 */
9414 #define DSI_PUCR_UEDL                 DSI_PUCR_UEDL_Msk                        /*!< ULPS Exit on Data Lane */
9415 
9416 /*******************  Bit definition for DSI_PTTCR register  **************/
9417 #define DSI_PTTCR_TX_TRIG_Pos         (0U)
9418 #define DSI_PTTCR_TX_TRIG_Msk         (0xFUL << DSI_PTTCR_TX_TRIG_Pos)         /*!< 0x0000000F */
9419 #define DSI_PTTCR_TX_TRIG             DSI_PTTCR_TX_TRIG_Msk                    /*!< Transmission Trigger */
9420 #define DSI_PTTCR_TX_TRIG0_Pos        (0U)
9421 #define DSI_PTTCR_TX_TRIG0_Msk        (0x1UL << DSI_PTTCR_TX_TRIG0_Pos)        /*!< 0x00000001 */
9422 #define DSI_PTTCR_TX_TRIG0            DSI_PTTCR_TX_TRIG0_Msk
9423 #define DSI_PTTCR_TX_TRIG1_Pos        (1U)
9424 #define DSI_PTTCR_TX_TRIG1_Msk        (0x1UL << DSI_PTTCR_TX_TRIG1_Pos)        /*!< 0x00000002 */
9425 #define DSI_PTTCR_TX_TRIG1            DSI_PTTCR_TX_TRIG1_Msk
9426 #define DSI_PTTCR_TX_TRIG2_Pos        (2U)
9427 #define DSI_PTTCR_TX_TRIG2_Msk        (0x1UL << DSI_PTTCR_TX_TRIG2_Pos)        /*!< 0x00000004 */
9428 #define DSI_PTTCR_TX_TRIG2            DSI_PTTCR_TX_TRIG2_Msk
9429 #define DSI_PTTCR_TX_TRIG3_Pos        (3U)
9430 #define DSI_PTTCR_TX_TRIG3_Msk        (0x1UL << DSI_PTTCR_TX_TRIG3_Pos)        /*!< 0x00000008 */
9431 #define DSI_PTTCR_TX_TRIG3            DSI_PTTCR_TX_TRIG3_Msk
9432 
9433 /*******************  Bit definition for DSI_PSR register  ****************/
9434 #define DSI_PSR_PD_Pos                (1U)
9435 #define DSI_PSR_PD_Msk                (0x1UL << DSI_PSR_PD_Pos)                /*!< 0x00000002 */
9436 #define DSI_PSR_PD                    DSI_PSR_PD_Msk                           /*!< PHY Direction */
9437 #define DSI_PSR_PSSC_Pos              (2U)
9438 #define DSI_PSR_PSSC_Msk              (0x1UL << DSI_PSR_PSSC_Pos)              /*!< 0x00000004 */
9439 #define DSI_PSR_PSSC                  DSI_PSR_PSSC_Msk                         /*!< PHY Stop State Clock lane */
9440 #define DSI_PSR_UANC_Pos              (3U)
9441 #define DSI_PSR_UANC_Msk              (0x1UL << DSI_PSR_UANC_Pos)              /*!< 0x00000008 */
9442 #define DSI_PSR_UANC                  DSI_PSR_UANC_Msk                         /*!< ULPS Active Not Clock lane */
9443 #define DSI_PSR_PSS0_Pos              (4U)
9444 #define DSI_PSR_PSS0_Msk              (0x1UL << DSI_PSR_PSS0_Pos)              /*!< 0x00000010 */
9445 #define DSI_PSR_PSS0                  DSI_PSR_PSS0_Msk                         /*!< PHY Stop State lane 0 */
9446 #define DSI_PSR_UAN0_Pos              (5U)
9447 #define DSI_PSR_UAN0_Msk              (0x1UL << DSI_PSR_UAN0_Pos)              /*!< 0x00000020 */
9448 #define DSI_PSR_UAN0                  DSI_PSR_UAN0_Msk                         /*!< ULPS Active Not lane 0 */
9449 #define DSI_PSR_RUE0_Pos              (6U)
9450 #define DSI_PSR_RUE0_Msk              (0x1UL << DSI_PSR_RUE0_Pos)              /*!< 0x00000040 */
9451 #define DSI_PSR_RUE0                  DSI_PSR_RUE0_Msk                         /*!< RX ULPS Escape lane 0 */
9452 #define DSI_PSR_PSS1_Pos              (7U)
9453 #define DSI_PSR_PSS1_Msk              (0x1UL << DSI_PSR_PSS1_Pos)              /*!< 0x00000080 */
9454 #define DSI_PSR_PSS1                  DSI_PSR_PSS1_Msk                         /*!< PHY Stop State lane 1 */
9455 #define DSI_PSR_UAN1_Pos              (8U)
9456 #define DSI_PSR_UAN1_Msk              (0x1UL << DSI_PSR_UAN1_Pos)              /*!< 0x00000100 */
9457 #define DSI_PSR_UAN1                  DSI_PSR_UAN1_Msk                         /*!< ULPS Active Not lane 1 */
9458 
9459 /*******************  Bit definition for DSI_ISR0 register  ***************/
9460 #define DSI_ISR0_AE0_Pos              (0U)
9461 #define DSI_ISR0_AE0_Msk              (0x1UL << DSI_ISR0_AE0_Pos)              /*!< 0x00000001 */
9462 #define DSI_ISR0_AE0                  DSI_ISR0_AE0_Msk                         /*!< Acknowledge Error 0 */
9463 #define DSI_ISR0_AE1_Pos              (1U)
9464 #define DSI_ISR0_AE1_Msk              (0x1UL << DSI_ISR0_AE1_Pos)              /*!< 0x00000002 */
9465 #define DSI_ISR0_AE1                  DSI_ISR0_AE1_Msk                         /*!< Acknowledge Error 1 */
9466 #define DSI_ISR0_AE2_Pos              (2U)
9467 #define DSI_ISR0_AE2_Msk              (0x1UL << DSI_ISR0_AE2_Pos)              /*!< 0x00000004 */
9468 #define DSI_ISR0_AE2                  DSI_ISR0_AE2_Msk                         /*!< Acknowledge Error 2 */
9469 #define DSI_ISR0_AE3_Pos              (3U)
9470 #define DSI_ISR0_AE3_Msk              (0x1UL << DSI_ISR0_AE3_Pos)              /*!< 0x00000008 */
9471 #define DSI_ISR0_AE3                  DSI_ISR0_AE3_Msk                         /*!< Acknowledge Error 3 */
9472 #define DSI_ISR0_AE4_Pos              (4U)
9473 #define DSI_ISR0_AE4_Msk              (0x1UL << DSI_ISR0_AE4_Pos)              /*!< 0x00000010 */
9474 #define DSI_ISR0_AE4                  DSI_ISR0_AE4_Msk                         /*!< Acknowledge Error 4 */
9475 #define DSI_ISR0_AE5_Pos              (5U)
9476 #define DSI_ISR0_AE5_Msk              (0x1UL << DSI_ISR0_AE5_Pos)              /*!< 0x00000020 */
9477 #define DSI_ISR0_AE5                  DSI_ISR0_AE5_Msk                         /*!< Acknowledge Error 5 */
9478 #define DSI_ISR0_AE6_Pos              (6U)
9479 #define DSI_ISR0_AE6_Msk              (0x1UL << DSI_ISR0_AE6_Pos)              /*!< 0x00000040 */
9480 #define DSI_ISR0_AE6                  DSI_ISR0_AE6_Msk                         /*!< Acknowledge Error 6 */
9481 #define DSI_ISR0_AE7_Pos              (7U)
9482 #define DSI_ISR0_AE7_Msk              (0x1UL << DSI_ISR0_AE7_Pos)              /*!< 0x00000080 */
9483 #define DSI_ISR0_AE7                  DSI_ISR0_AE7_Msk                         /*!< Acknowledge Error 7 */
9484 #define DSI_ISR0_AE8_Pos              (8U)
9485 #define DSI_ISR0_AE8_Msk              (0x1UL << DSI_ISR0_AE8_Pos)              /*!< 0x00000100 */
9486 #define DSI_ISR0_AE8                  DSI_ISR0_AE8_Msk                         /*!< Acknowledge Error 8 */
9487 #define DSI_ISR0_AE9_Pos              (9U)
9488 #define DSI_ISR0_AE9_Msk              (0x1UL << DSI_ISR0_AE9_Pos)              /*!< 0x00000200 */
9489 #define DSI_ISR0_AE9                  DSI_ISR0_AE9_Msk                         /*!< Acknowledge Error 9 */
9490 #define DSI_ISR0_AE10_Pos             (10U)
9491 #define DSI_ISR0_AE10_Msk             (0x1UL << DSI_ISR0_AE10_Pos)             /*!< 0x00000400 */
9492 #define DSI_ISR0_AE10                 DSI_ISR0_AE10_Msk                        /*!< Acknowledge Error 10 */
9493 #define DSI_ISR0_AE11_Pos             (11U)
9494 #define DSI_ISR0_AE11_Msk             (0x1UL << DSI_ISR0_AE11_Pos)             /*!< 0x00000800 */
9495 #define DSI_ISR0_AE11                 DSI_ISR0_AE11_Msk                        /*!< Acknowledge Error 11 */
9496 #define DSI_ISR0_AE12_Pos             (12U)
9497 #define DSI_ISR0_AE12_Msk             (0x1UL << DSI_ISR0_AE12_Pos)             /*!< 0x00001000 */
9498 #define DSI_ISR0_AE12                 DSI_ISR0_AE12_Msk                        /*!< Acknowledge Error 12 */
9499 #define DSI_ISR0_AE13_Pos             (13U)
9500 #define DSI_ISR0_AE13_Msk             (0x1UL << DSI_ISR0_AE13_Pos)             /*!< 0x00002000 */
9501 #define DSI_ISR0_AE13                 DSI_ISR0_AE13_Msk                        /*!< Acknowledge Error 13 */
9502 #define DSI_ISR0_AE14_Pos             (14U)
9503 #define DSI_ISR0_AE14_Msk             (0x1UL << DSI_ISR0_AE14_Pos)             /*!< 0x00004000 */
9504 #define DSI_ISR0_AE14                 DSI_ISR0_AE14_Msk                        /*!< Acknowledge Error 14 */
9505 #define DSI_ISR0_AE15_Pos             (15U)
9506 #define DSI_ISR0_AE15_Msk             (0x1UL << DSI_ISR0_AE15_Pos)             /*!< 0x00008000 */
9507 #define DSI_ISR0_AE15                 DSI_ISR0_AE15_Msk                        /*!< Acknowledge Error 15 */
9508 #define DSI_ISR0_PE0_Pos              (16U)
9509 #define DSI_ISR0_PE0_Msk              (0x1UL << DSI_ISR0_PE0_Pos)              /*!< 0x00010000 */
9510 #define DSI_ISR0_PE0                  DSI_ISR0_PE0_Msk                         /*!< PHY Error 0 */
9511 #define DSI_ISR0_PE1_Pos              (17U)
9512 #define DSI_ISR0_PE1_Msk              (0x1UL << DSI_ISR0_PE1_Pos)              /*!< 0x00020000 */
9513 #define DSI_ISR0_PE1                  DSI_ISR0_PE1_Msk                         /*!< PHY Error 1 */
9514 #define DSI_ISR0_PE2_Pos              (18U)
9515 #define DSI_ISR0_PE2_Msk              (0x1UL << DSI_ISR0_PE2_Pos)              /*!< 0x00040000 */
9516 #define DSI_ISR0_PE2                  DSI_ISR0_PE2_Msk                         /*!< PHY Error 2 */
9517 #define DSI_ISR0_PE3_Pos              (19U)
9518 #define DSI_ISR0_PE3_Msk              (0x1UL << DSI_ISR0_PE3_Pos)              /*!< 0x00080000 */
9519 #define DSI_ISR0_PE3                  DSI_ISR0_PE3_Msk                         /*!< PHY Error 3 */
9520 #define DSI_ISR0_PE4_Pos              (20U)
9521 #define DSI_ISR0_PE4_Msk              (0x1UL << DSI_ISR0_PE4_Pos)              /*!< 0x00100000 */
9522 #define DSI_ISR0_PE4                  DSI_ISR0_PE4_Msk                         /*!< PHY Error 4 */
9523 
9524 /*******************  Bit definition for DSI_ISR1 register  ***************/
9525 #define DSI_ISR1_TOHSTX_Pos           (0U)
9526 #define DSI_ISR1_TOHSTX_Msk           (0x1UL << DSI_ISR1_TOHSTX_Pos)           /*!< 0x00000001 */
9527 #define DSI_ISR1_TOHSTX               DSI_ISR1_TOHSTX_Msk                      /*!< Timeout High-Speed Transmission */
9528 #define DSI_ISR1_TOLPRX_Pos           (1U)
9529 #define DSI_ISR1_TOLPRX_Msk           (0x1UL << DSI_ISR1_TOLPRX_Pos)           /*!< 0x00000002 */
9530 #define DSI_ISR1_TOLPRX               DSI_ISR1_TOLPRX_Msk                      /*!< Timeout Low-Power Reception */
9531 #define DSI_ISR1_ECCSE_Pos            (2U)
9532 #define DSI_ISR1_ECCSE_Msk            (0x1UL << DSI_ISR1_ECCSE_Pos)            /*!< 0x00000004 */
9533 #define DSI_ISR1_ECCSE                DSI_ISR1_ECCSE_Msk                       /*!< ECC Single-bit Error */
9534 #define DSI_ISR1_ECCME_Pos            (3U)
9535 #define DSI_ISR1_ECCME_Msk            (0x1UL << DSI_ISR1_ECCME_Pos)            /*!< 0x00000008 */
9536 #define DSI_ISR1_ECCME                DSI_ISR1_ECCME_Msk                       /*!< ECC Multi-bit Error */
9537 #define DSI_ISR1_CRCE_Pos             (4U)
9538 #define DSI_ISR1_CRCE_Msk             (0x1UL << DSI_ISR1_CRCE_Pos)             /*!< 0x00000010 */
9539 #define DSI_ISR1_CRCE                 DSI_ISR1_CRCE_Msk                        /*!< CRC Error */
9540 #define DSI_ISR1_PSE_Pos              (5U)
9541 #define DSI_ISR1_PSE_Msk              (0x1UL << DSI_ISR1_PSE_Pos)              /*!< 0x00000020 */
9542 #define DSI_ISR1_PSE                  DSI_ISR1_PSE_Msk                         /*!< Packet Size Error */
9543 #define DSI_ISR1_EOTPE_Pos            (6U)
9544 #define DSI_ISR1_EOTPE_Msk            (0x1UL << DSI_ISR1_EOTPE_Pos)            /*!< 0x00000040 */
9545 #define DSI_ISR1_EOTPE                DSI_ISR1_EOTPE_Msk                       /*!< EoTp Error */
9546 #define DSI_ISR1_LPWRE_Pos            (7U)
9547 #define DSI_ISR1_LPWRE_Msk            (0x1UL << DSI_ISR1_LPWRE_Pos)            /*!< 0x00000080 */
9548 #define DSI_ISR1_LPWRE                DSI_ISR1_LPWRE_Msk                       /*!< LTDC Payload Write Error */
9549 #define DSI_ISR1_GCWRE_Pos            (8U)
9550 #define DSI_ISR1_GCWRE_Msk            (0x1UL << DSI_ISR1_GCWRE_Pos)            /*!< 0x00000100 */
9551 #define DSI_ISR1_GCWRE                DSI_ISR1_GCWRE_Msk                       /*!< Generic Command Write Error */
9552 #define DSI_ISR1_GPWRE_Pos            (9U)
9553 #define DSI_ISR1_GPWRE_Msk            (0x1UL << DSI_ISR1_GPWRE_Pos)            /*!< 0x00000200 */
9554 #define DSI_ISR1_GPWRE                DSI_ISR1_GPWRE_Msk                       /*!< Generic Payload Write Error */
9555 #define DSI_ISR1_GPTXE_Pos            (10U)
9556 #define DSI_ISR1_GPTXE_Msk            (0x1UL << DSI_ISR1_GPTXE_Pos)            /*!< 0x00000400 */
9557 #define DSI_ISR1_GPTXE                DSI_ISR1_GPTXE_Msk                       /*!< Generic Payload Transmit Error */
9558 #define DSI_ISR1_GPRDE_Pos            (11U)
9559 #define DSI_ISR1_GPRDE_Msk            (0x1UL << DSI_ISR1_GPRDE_Pos)            /*!< 0x00000800 */
9560 #define DSI_ISR1_GPRDE                DSI_ISR1_GPRDE_Msk                       /*!< Generic Payload Read Error */
9561 #define DSI_ISR1_GPRXE_Pos            (12U)
9562 #define DSI_ISR1_GPRXE_Msk            (0x1UL << DSI_ISR1_GPRXE_Pos)            /*!< 0x00001000 */
9563 #define DSI_ISR1_GPRXE                DSI_ISR1_GPRXE_Msk                       /*!< Generic Payload Receive Error */
9564 #define DSI_ISR1_PBUE_Pos             (19U)
9565 #define DSI_ISR1_PBUE_Msk             (0x1UL << DSI_ISR1_PBUE_Pos)             /*!< 0x00040000 */
9566 #define DSI_ISR1_PBUE                 DSI_ISR1_PBUE_Msk                        /*!< Payload Buffer Underflow Error */
9567 
9568 /*******************  Bit definition for DSI_IER0 register  ***************/
9569 #define DSI_IER0_AE0IE_Pos            (0U)
9570 #define DSI_IER0_AE0IE_Msk            (0x1UL << DSI_IER0_AE0IE_Pos)            /*!< 0x00000001 */
9571 #define DSI_IER0_AE0IE                DSI_IER0_AE0IE_Msk                       /*!< Acknowledge Error 0 Interrupt Enable */
9572 #define DSI_IER0_AE1IE_Pos            (1U)
9573 #define DSI_IER0_AE1IE_Msk            (0x1UL << DSI_IER0_AE1IE_Pos)            /*!< 0x00000002 */
9574 #define DSI_IER0_AE1IE                DSI_IER0_AE1IE_Msk                       /*!< Acknowledge Error 1 Interrupt Enable */
9575 #define DSI_IER0_AE2IE_Pos            (2U)
9576 #define DSI_IER0_AE2IE_Msk            (0x1UL << DSI_IER0_AE2IE_Pos)            /*!< 0x00000004 */
9577 #define DSI_IER0_AE2IE                DSI_IER0_AE2IE_Msk                       /*!< Acknowledge Error 2 Interrupt Enable */
9578 #define DSI_IER0_AE3IE_Pos            (3U)
9579 #define DSI_IER0_AE3IE_Msk            (0x1UL << DSI_IER0_AE3IE_Pos)            /*!< 0x00000008 */
9580 #define DSI_IER0_AE3IE                DSI_IER0_AE3IE_Msk                       /*!< Acknowledge Error 3 Interrupt Enable */
9581 #define DSI_IER0_AE4IE_Pos            (4U)
9582 #define DSI_IER0_AE4IE_Msk            (0x1UL << DSI_IER0_AE4IE_Pos)            /*!< 0x00000010 */
9583 #define DSI_IER0_AE4IE                DSI_IER0_AE4IE_Msk                       /*!< Acknowledge Error 4 Interrupt Enable */
9584 #define DSI_IER0_AE5IE_Pos            (5U)
9585 #define DSI_IER0_AE5IE_Msk            (0x1UL << DSI_IER0_AE5IE_Pos)            /*!< 0x00000020 */
9586 #define DSI_IER0_AE5IE                DSI_IER0_AE5IE_Msk                       /*!< Acknowledge Error 5 Interrupt Enable */
9587 #define DSI_IER0_AE6IE_Pos            (6U)
9588 #define DSI_IER0_AE6IE_Msk            (0x1UL << DSI_IER0_AE6IE_Pos)            /*!< 0x00000040 */
9589 #define DSI_IER0_AE6IE                DSI_IER0_AE6IE_Msk                       /*!< Acknowledge Error 6 Interrupt Enable */
9590 #define DSI_IER0_AE7IE_Pos            (7U)
9591 #define DSI_IER0_AE7IE_Msk            (0x1UL << DSI_IER0_AE7IE_Pos)            /*!< 0x00000080 */
9592 #define DSI_IER0_AE7IE                DSI_IER0_AE7IE_Msk                       /*!< Acknowledge Error 7 Interrupt Enable */
9593 #define DSI_IER0_AE8IE_Pos            (8U)
9594 #define DSI_IER0_AE8IE_Msk            (0x1UL << DSI_IER0_AE8IE_Pos)            /*!< 0x00000100 */
9595 #define DSI_IER0_AE8IE                DSI_IER0_AE8IE_Msk                       /*!< Acknowledge Error 8 Interrupt Enable */
9596 #define DSI_IER0_AE9IE_Pos            (9U)
9597 #define DSI_IER0_AE9IE_Msk            (0x1UL << DSI_IER0_AE9IE_Pos)            /*!< 0x00000200 */
9598 #define DSI_IER0_AE9IE                DSI_IER0_AE9IE_Msk                       /*!< Acknowledge Error 9 Interrupt Enable */
9599 #define DSI_IER0_AE10IE_Pos           (10U)
9600 #define DSI_IER0_AE10IE_Msk           (0x1UL << DSI_IER0_AE10IE_Pos)           /*!< 0x00000400 */
9601 #define DSI_IER0_AE10IE               DSI_IER0_AE10IE_Msk                      /*!< Acknowledge Error 10 Interrupt Enable */
9602 #define DSI_IER0_AE11IE_Pos           (11U)
9603 #define DSI_IER0_AE11IE_Msk           (0x1UL << DSI_IER0_AE11IE_Pos)           /*!< 0x00000800 */
9604 #define DSI_IER0_AE11IE               DSI_IER0_AE11IE_Msk                      /*!< Acknowledge Error 11 Interrupt Enable */
9605 #define DSI_IER0_AE12IE_Pos           (12U)
9606 #define DSI_IER0_AE12IE_Msk           (0x1UL << DSI_IER0_AE12IE_Pos)           /*!< 0x00001000 */
9607 #define DSI_IER0_AE12IE               DSI_IER0_AE12IE_Msk                      /*!< Acknowledge Error 12 Interrupt Enable */
9608 #define DSI_IER0_AE13IE_Pos           (13U)
9609 #define DSI_IER0_AE13IE_Msk           (0x1UL << DSI_IER0_AE13IE_Pos)           /*!< 0x00002000 */
9610 #define DSI_IER0_AE13IE               DSI_IER0_AE13IE_Msk                      /*!< Acknowledge Error 13 Interrupt Enable */
9611 #define DSI_IER0_AE14IE_Pos           (14U)
9612 #define DSI_IER0_AE14IE_Msk           (0x1UL << DSI_IER0_AE14IE_Pos)           /*!< 0x00004000 */
9613 #define DSI_IER0_AE14IE               DSI_IER0_AE14IE_Msk                      /*!< Acknowledge Error 14 Interrupt Enable */
9614 #define DSI_IER0_AE15IE_Pos           (15U)
9615 #define DSI_IER0_AE15IE_Msk           (0x1UL << DSI_IER0_AE15IE_Pos)           /*!< 0x00008000 */
9616 #define DSI_IER0_AE15IE               DSI_IER0_AE15IE_Msk                      /*!< Acknowledge Error 15 Interrupt Enable */
9617 #define DSI_IER0_PE0IE_Pos            (16U)
9618 #define DSI_IER0_PE0IE_Msk            (0x1UL << DSI_IER0_PE0IE_Pos)            /*!< 0x00010000 */
9619 #define DSI_IER0_PE0IE                DSI_IER0_PE0IE_Msk                       /*!< PHY Error 0 Interrupt Enable */
9620 #define DSI_IER0_PE1IE_Pos            (17U)
9621 #define DSI_IER0_PE1IE_Msk            (0x1UL << DSI_IER0_PE1IE_Pos)            /*!< 0x00020000 */
9622 #define DSI_IER0_PE1IE                DSI_IER0_PE1IE_Msk                       /*!< PHY Error 1 Interrupt Enable */
9623 #define DSI_IER0_PE2IE_Pos            (18U)
9624 #define DSI_IER0_PE2IE_Msk            (0x1UL << DSI_IER0_PE2IE_Pos)            /*!< 0x00040000 */
9625 #define DSI_IER0_PE2IE                DSI_IER0_PE2IE_Msk                       /*!< PHY Error 2 Interrupt Enable */
9626 #define DSI_IER0_PE3IE_Pos            (19U)
9627 #define DSI_IER0_PE3IE_Msk            (0x1UL << DSI_IER0_PE3IE_Pos)            /*!< 0x00080000 */
9628 #define DSI_IER0_PE3IE                DSI_IER0_PE3IE_Msk                       /*!< PHY Error 3 Interrupt Enable */
9629 #define DSI_IER0_PE4IE_Pos            (20U)
9630 #define DSI_IER0_PE4IE_Msk            (0x1UL << DSI_IER0_PE4IE_Pos)            /*!< 0x00100000 */
9631 #define DSI_IER0_PE4IE                DSI_IER0_PE4IE_Msk                       /*!< PHY Error 4 Interrupt Enable */
9632 
9633 /*******************  Bit definition for DSI_IER1 register  ***************/
9634 #define DSI_IER1_TOHSTXIE_Pos         (0U)
9635 #define DSI_IER1_TOHSTXIE_Msk         (0x1UL << DSI_IER1_TOHSTXIE_Pos)         /*!< 0x00000001 */
9636 #define DSI_IER1_TOHSTXIE             DSI_IER1_TOHSTXIE_Msk                    /*!< Timeout High-Speed Transmission Interrupt Enable */
9637 #define DSI_IER1_TOLPRXIE_Pos         (1U)
9638 #define DSI_IER1_TOLPRXIE_Msk         (0x1UL << DSI_IER1_TOLPRXIE_Pos)         /*!< 0x00000002 */
9639 #define DSI_IER1_TOLPRXIE             DSI_IER1_TOLPRXIE_Msk                    /*!< Timeout Low-Power Reception Interrupt Enable */
9640 #define DSI_IER1_ECCSEIE_Pos          (2U)
9641 #define DSI_IER1_ECCSEIE_Msk          (0x1UL << DSI_IER1_ECCSEIE_Pos)          /*!< 0x00000004 */
9642 #define DSI_IER1_ECCSEIE              DSI_IER1_ECCSEIE_Msk                     /*!< ECC Single-bit Error Interrupt Enable */
9643 #define DSI_IER1_ECCMEIE_Pos          (3U)
9644 #define DSI_IER1_ECCMEIE_Msk          (0x1UL << DSI_IER1_ECCMEIE_Pos)          /*!< 0x00000008 */
9645 #define DSI_IER1_ECCMEIE              DSI_IER1_ECCMEIE_Msk                     /*!< ECC Multi-bit Error Interrupt Enable */
9646 #define DSI_IER1_CRCEIE_Pos           (4U)
9647 #define DSI_IER1_CRCEIE_Msk           (0x1UL << DSI_IER1_CRCEIE_Pos)           /*!< 0x00000010 */
9648 #define DSI_IER1_CRCEIE               DSI_IER1_CRCEIE_Msk                      /*!< CRC Error Interrupt Enable */
9649 #define DSI_IER1_PSEIE_Pos            (5U)
9650 #define DSI_IER1_PSEIE_Msk            (0x1UL << DSI_IER1_PSEIE_Pos)            /*!< 0x00000020 */
9651 #define DSI_IER1_PSEIE                DSI_IER1_PSEIE_Msk                       /*!< Packet Size Error Interrupt Enable */
9652 #define DSI_IER1_EOTPEIE_Pos          (6U)
9653 #define DSI_IER1_EOTPEIE_Msk          (0x1UL << DSI_IER1_EOTPEIE_Pos)          /*!< 0x00000040 */
9654 #define DSI_IER1_EOTPEIE              DSI_IER1_EOTPEIE_Msk                     /*!< EoTp Error Interrupt Enable */
9655 #define DSI_IER1_LPWREIE_Pos          (7U)
9656 #define DSI_IER1_LPWREIE_Msk          (0x1UL << DSI_IER1_LPWREIE_Pos)          /*!< 0x00000080 */
9657 #define DSI_IER1_LPWREIE              DSI_IER1_LPWREIE_Msk                     /*!< LTDC Payload Write Error Interrupt Enable */
9658 #define DSI_IER1_GCWREIE_Pos          (8U)
9659 #define DSI_IER1_GCWREIE_Msk          (0x1UL << DSI_IER1_GCWREIE_Pos)          /*!< 0x00000100 */
9660 #define DSI_IER1_GCWREIE              DSI_IER1_GCWREIE_Msk                     /*!< Generic Command Write Error Interrupt Enable */
9661 #define DSI_IER1_GPWREIE_Pos          (9U)
9662 #define DSI_IER1_GPWREIE_Msk          (0x1UL << DSI_IER1_GPWREIE_Pos)          /*!< 0x00000200 */
9663 #define DSI_IER1_GPWREIE              DSI_IER1_GPWREIE_Msk                     /*!< Generic Payload Write Error Interrupt Enable */
9664 #define DSI_IER1_GPTXEIE_Pos          (10U)
9665 #define DSI_IER1_GPTXEIE_Msk          (0x1UL << DSI_IER1_GPTXEIE_Pos)          /*!< 0x00000400 */
9666 #define DSI_IER1_GPTXEIE              DSI_IER1_GPTXEIE_Msk                     /*!< Generic Payload Transmit Error Interrupt Enable */
9667 #define DSI_IER1_GPRDEIE_Pos          (11U)
9668 #define DSI_IER1_GPRDEIE_Msk          (0x1UL << DSI_IER1_GPRDEIE_Pos)          /*!< 0x00000800 */
9669 #define DSI_IER1_GPRDEIE              DSI_IER1_GPRDEIE_Msk                     /*!< Generic Payload Read Error Interrupt Enable */
9670 #define DSI_IER1_GPRXEIE_Pos          (12U)
9671 #define DSI_IER1_GPRXEIE_Msk          (0x1UL << DSI_IER1_GPRXEIE_Pos)          /*!< 0x00001000 */
9672 #define DSI_IER1_GPRXEIE              DSI_IER1_GPRXEIE_Msk                     /*!< Generic Payload Receive Error Interrupt Enable */
9673 #define DSI_IER1_PBUEIE_Pos           (19U)
9674 #define DSI_IER1_PBUEIE_Msk           (0x1UL << DSI_IER1_PBUEIE_Pos)           /*!< 0x00040000 */
9675 #define DSI_IER1_PBUEIE               DSI_IER1_PBUEIE_Msk                      /*!< Payload Buffer Underflow Error Interrupt Enable */
9676 
9677 /*******************  Bit definition for DSI_FIR0 register  ***************/
9678 #define DSI_FIR0_FAE0_Pos             (0U)
9679 #define DSI_FIR0_FAE0_Msk             (0x1UL << DSI_FIR0_FAE0_Pos)             /*!< 0x00000001 */
9680 #define DSI_FIR0_FAE0                 DSI_FIR0_FAE0_Msk                        /*!< Force Acknowledge Error 0 */
9681 #define DSI_FIR0_FAE1_Pos             (1U)
9682 #define DSI_FIR0_FAE1_Msk             (0x1UL << DSI_FIR0_FAE1_Pos)             /*!< 0x00000002 */
9683 #define DSI_FIR0_FAE1                 DSI_FIR0_FAE1_Msk                        /*!< Force Acknowledge Error 1 */
9684 #define DSI_FIR0_FAE2_Pos             (2U)
9685 #define DSI_FIR0_FAE2_Msk             (0x1UL << DSI_FIR0_FAE2_Pos)             /*!< 0x00000004 */
9686 #define DSI_FIR0_FAE2                 DSI_FIR0_FAE2_Msk                        /*!< Force Acknowledge Error 2 */
9687 #define DSI_FIR0_FAE3_Pos             (3U)
9688 #define DSI_FIR0_FAE3_Msk             (0x1UL << DSI_FIR0_FAE3_Pos)             /*!< 0x00000008 */
9689 #define DSI_FIR0_FAE3                 DSI_FIR0_FAE3_Msk                        /*!< Force Acknowledge Error 3 */
9690 #define DSI_FIR0_FAE4_Pos             (4U)
9691 #define DSI_FIR0_FAE4_Msk             (0x1UL << DSI_FIR0_FAE4_Pos)             /*!< 0x00000010 */
9692 #define DSI_FIR0_FAE4                 DSI_FIR0_FAE4_Msk                        /*!< Force Acknowledge Error 4 */
9693 #define DSI_FIR0_FAE5_Pos             (5U)
9694 #define DSI_FIR0_FAE5_Msk             (0x1UL << DSI_FIR0_FAE5_Pos)             /*!< 0x00000020 */
9695 #define DSI_FIR0_FAE5                 DSI_FIR0_FAE5_Msk                        /*!< Force Acknowledge Error 5 */
9696 #define DSI_FIR0_FAE6_Pos             (6U)
9697 #define DSI_FIR0_FAE6_Msk             (0x1UL << DSI_FIR0_FAE6_Pos)             /*!< 0x00000040 */
9698 #define DSI_FIR0_FAE6                 DSI_FIR0_FAE6_Msk                        /*!< Force Acknowledge Error 6 */
9699 #define DSI_FIR0_FAE7_Pos             (7U)
9700 #define DSI_FIR0_FAE7_Msk             (0x1UL << DSI_FIR0_FAE7_Pos)             /*!< 0x00000080 */
9701 #define DSI_FIR0_FAE7                 DSI_FIR0_FAE7_Msk                        /*!< Force Acknowledge Error 7 */
9702 #define DSI_FIR0_FAE8_Pos             (8U)
9703 #define DSI_FIR0_FAE8_Msk             (0x1UL << DSI_FIR0_FAE8_Pos)             /*!< 0x00000100 */
9704 #define DSI_FIR0_FAE8                 DSI_FIR0_FAE8_Msk                        /*!< Force Acknowledge Error 8 */
9705 #define DSI_FIR0_FAE9_Pos             (9U)
9706 #define DSI_FIR0_FAE9_Msk             (0x1UL << DSI_FIR0_FAE9_Pos)             /*!< 0x00000200 */
9707 #define DSI_FIR0_FAE9                 DSI_FIR0_FAE9_Msk                        /*!< Force Acknowledge Error 9 */
9708 #define DSI_FIR0_FAE10_Pos            (10U)
9709 #define DSI_FIR0_FAE10_Msk            (0x1UL << DSI_FIR0_FAE10_Pos)            /*!< 0x00000400 */
9710 #define DSI_FIR0_FAE10                DSI_FIR0_FAE10_Msk                       /*!< Force Acknowledge Error 10 */
9711 #define DSI_FIR0_FAE11_Pos            (11U)
9712 #define DSI_FIR0_FAE11_Msk            (0x1UL << DSI_FIR0_FAE11_Pos)            /*!< 0x00000800 */
9713 #define DSI_FIR0_FAE11                DSI_FIR0_FAE11_Msk                       /*!< Force Acknowledge Error 11 */
9714 #define DSI_FIR0_FAE12_Pos            (12U)
9715 #define DSI_FIR0_FAE12_Msk            (0x1UL << DSI_FIR0_FAE12_Pos)            /*!< 0x00001000 */
9716 #define DSI_FIR0_FAE12                DSI_FIR0_FAE12_Msk                       /*!< Force Acknowledge Error 12 */
9717 #define DSI_FIR0_FAE13_Pos            (13U)
9718 #define DSI_FIR0_FAE13_Msk            (0x1UL << DSI_FIR0_FAE13_Pos)            /*!< 0x00002000 */
9719 #define DSI_FIR0_FAE13                DSI_FIR0_FAE13_Msk                       /*!< Force Acknowledge Error 13 */
9720 #define DSI_FIR0_FAE14_Pos            (14U)
9721 #define DSI_FIR0_FAE14_Msk            (0x1UL << DSI_FIR0_FAE14_Pos)            /*!< 0x00004000 */
9722 #define DSI_FIR0_FAE14                DSI_FIR0_FAE14_Msk                       /*!< Force Acknowledge Error 14 */
9723 #define DSI_FIR0_FAE15_Pos            (15U)
9724 #define DSI_FIR0_FAE15_Msk            (0x1UL << DSI_FIR0_FAE15_Pos)            /*!< 0x00008000 */
9725 #define DSI_FIR0_FAE15                DSI_FIR0_FAE15_Msk                       /*!< Force Acknowledge Error 15 */
9726 #define DSI_FIR0_FPE0_Pos             (16U)
9727 #define DSI_FIR0_FPE0_Msk             (0x1UL << DSI_FIR0_FPE0_Pos)             /*!< 0x00010000 */
9728 #define DSI_FIR0_FPE0                 DSI_FIR0_FPE0_Msk                        /*!< Force PHY Error 0 */
9729 #define DSI_FIR0_FPE1_Pos             (17U)
9730 #define DSI_FIR0_FPE1_Msk             (0x1UL << DSI_FIR0_FPE1_Pos)             /*!< 0x00020000 */
9731 #define DSI_FIR0_FPE1                 DSI_FIR0_FPE1_Msk                        /*!< Force PHY Error 1 */
9732 #define DSI_FIR0_FPE2_Pos             (18U)
9733 #define DSI_FIR0_FPE2_Msk             (0x1UL << DSI_FIR0_FPE2_Pos)             /*!< 0x00040000 */
9734 #define DSI_FIR0_FPE2                 DSI_FIR0_FPE2_Msk                        /*!< Force PHY Error 2 */
9735 #define DSI_FIR0_FPE3_Pos             (19U)
9736 #define DSI_FIR0_FPE3_Msk             (0x1UL << DSI_FIR0_FPE3_Pos)             /*!< 0x00080000 */
9737 #define DSI_FIR0_FPE3                 DSI_FIR0_FPE3_Msk                        /*!< Force PHY Error 3 */
9738 #define DSI_FIR0_FPE4_Pos             (20U)
9739 #define DSI_FIR0_FPE4_Msk             (0x1UL << DSI_FIR0_FPE4_Pos)             /*!< 0x00100000 */
9740 #define DSI_FIR0_FPE4                 DSI_FIR0_FPE4_Msk                        /*!< Force PHY Error 4 */
9741 
9742 /*******************  Bit definition for DSI_FIR1 register  ***************/
9743 #define DSI_FIR1_FTOHSTX_Pos          (0U)
9744 #define DSI_FIR1_FTOHSTX_Msk          (0x1UL << DSI_FIR1_FTOHSTX_Pos)          /*!< 0x00000001 */
9745 #define DSI_FIR1_FTOHSTX              DSI_FIR1_FTOHSTX_Msk                     /*!< Force Timeout High-Speed Transmission */
9746 #define DSI_FIR1_FTOLPRX_Pos          (1U)
9747 #define DSI_FIR1_FTOLPRX_Msk          (0x1UL << DSI_FIR1_FTOLPRX_Pos)          /*!< 0x00000002 */
9748 #define DSI_FIR1_FTOLPRX              DSI_FIR1_FTOLPRX_Msk                     /*!< Force Timeout Low-Power Reception */
9749 #define DSI_FIR1_FECCSE_Pos           (2U)
9750 #define DSI_FIR1_FECCSE_Msk           (0x1UL << DSI_FIR1_FECCSE_Pos)           /*!< 0x00000004 */
9751 #define DSI_FIR1_FECCSE               DSI_FIR1_FECCSE_Msk                      /*!< Force ECC Single-bit Error */
9752 #define DSI_FIR1_FECCME_Pos           (3U)
9753 #define DSI_FIR1_FECCME_Msk           (0x1UL << DSI_FIR1_FECCME_Pos)           /*!< 0x00000008 */
9754 #define DSI_FIR1_FECCME               DSI_FIR1_FECCME_Msk                      /*!< Force ECC Multi-bit Error */
9755 #define DSI_FIR1_FCRCE_Pos            (4U)
9756 #define DSI_FIR1_FCRCE_Msk            (0x1UL << DSI_FIR1_FCRCE_Pos)            /*!< 0x00000010 */
9757 #define DSI_FIR1_FCRCE                DSI_FIR1_FCRCE_Msk                       /*!< Force CRC Error */
9758 #define DSI_FIR1_FPSE_Pos             (5U)
9759 #define DSI_FIR1_FPSE_Msk             (0x1UL << DSI_FIR1_FPSE_Pos)             /*!< 0x00000020 */
9760 #define DSI_FIR1_FPSE                 DSI_FIR1_FPSE_Msk                        /*!< Force Packet Size Error */
9761 #define DSI_FIR1_FEOTPE_Pos           (6U)
9762 #define DSI_FIR1_FEOTPE_Msk           (0x1UL << DSI_FIR1_FEOTPE_Pos)           /*!< 0x00000040 */
9763 #define DSI_FIR1_FEOTPE               DSI_FIR1_FEOTPE_Msk                      /*!< Force EoTp Error */
9764 #define DSI_FIR1_FLPWRE_Pos           (7U)
9765 #define DSI_FIR1_FLPWRE_Msk           (0x1UL << DSI_FIR1_FLPWRE_Pos)           /*!< 0x00000080 */
9766 #define DSI_FIR1_FLPWRE               DSI_FIR1_FLPWRE_Msk                      /*!< Force LTDC Payload Write Error */
9767 #define DSI_FIR1_FGCWRE_Pos           (8U)
9768 #define DSI_FIR1_FGCWRE_Msk           (0x1UL << DSI_FIR1_FGCWRE_Pos)           /*!< 0x00000100 */
9769 #define DSI_FIR1_FGCWRE               DSI_FIR1_FGCWRE_Msk                      /*!< Force Generic Command Write Error */
9770 #define DSI_FIR1_FGPWRE_Pos           (9U)
9771 #define DSI_FIR1_FGPWRE_Msk           (0x1UL << DSI_FIR1_FGPWRE_Pos)           /*!< 0x00000200 */
9772 #define DSI_FIR1_FGPWRE               DSI_FIR1_FGPWRE_Msk                      /*!< Force Generic Payload Write Error */
9773 #define DSI_FIR1_FGPTXE_Pos           (10U)
9774 #define DSI_FIR1_FGPTXE_Msk           (0x1UL << DSI_FIR1_FGPTXE_Pos)           /*!< 0x00000400 */
9775 #define DSI_FIR1_FGPTXE               DSI_FIR1_FGPTXE_Msk                      /*!< Force Generic Payload Transmit Error */
9776 #define DSI_FIR1_FGPRDE_Pos           (11U)
9777 #define DSI_FIR1_FGPRDE_Msk           (0x1UL << DSI_FIR1_FGPRDE_Pos)           /*!< 0x00000800 */
9778 #define DSI_FIR1_FGPRDE               DSI_FIR1_FGPRDE_Msk                      /*!< Force Generic Payload Read Error */
9779 #define DSI_FIR1_FGPRXE_Pos           (12U)
9780 #define DSI_FIR1_FGPRXE_Msk           (0x1UL << DSI_FIR1_FGPRXE_Pos)           /*!< 0x00001000 */
9781 #define DSI_FIR1_FGPRXE               DSI_FIR1_FGPRXE_Msk                      /*!< Force Generic Payload Receive Error */
9782 #define DSI_FIR1_FPBUE_Pos            (19U)
9783 #define DSI_FIR1_FPBUE_Msk            (0x1UL << DSI_FIR1_FPBUE_Pos)            /*!< 0x00040000 */
9784 #define DSI_FIR1_FPBUE                DSI_FIR1_FPBUE_Msk                       /*!< Force Payload Buffer Underflow Error */
9785 
9786 /*******************  Bit definition for DSI_DLTRCR register  *************/
9787 #define DSI_DLTRCR_MRD_TIME_Pos       (0U)
9788 #define DSI_DLTRCR_MRD_TIME_Msk       (0x7FFFUL << DSI_DLTRCR_MRD_TIME_Pos)    /*!< 0x00007FFF */
9789 #define DSI_DLTRCR_MRD_TIME           DSI_DLTRCR_MRD_TIME_Msk                  /*!< Maximum Read Time */
9790 #define DSI_DLTRCR_MRD_TIME0_Pos      (0U)
9791 #define DSI_DLTRCR_MRD_TIME0_Msk      (0x1UL << DSI_DLTRCR_MRD_TIME0_Pos)      /*!< 0x00000001 */
9792 #define DSI_DLTRCR_MRD_TIME0          DSI_DLTRCR_MRD_TIME0_Msk
9793 #define DSI_DLTRCR_MRD_TIME1_Pos      (1U)
9794 #define DSI_DLTRCR_MRD_TIME1_Msk      (0x1UL << DSI_DLTRCR_MRD_TIME1_Pos)      /*!< 0x00000002 */
9795 #define DSI_DLTRCR_MRD_TIME1          DSI_DLTRCR_MRD_TIME1_Msk
9796 #define DSI_DLTRCR_MRD_TIME2_Pos      (2U)
9797 #define DSI_DLTRCR_MRD_TIME2_Msk      (0x1UL << DSI_DLTRCR_MRD_TIME2_Pos)      /*!< 0x00000004 */
9798 #define DSI_DLTRCR_MRD_TIME2          DSI_DLTRCR_MRD_TIME2_Msk
9799 #define DSI_DLTRCR_MRD_TIME3_Pos      (3U)
9800 #define DSI_DLTRCR_MRD_TIME3_Msk      (0x1UL << DSI_DLTRCR_MRD_TIME3_Pos)      /*!< 0x00000008 */
9801 #define DSI_DLTRCR_MRD_TIME3          DSI_DLTRCR_MRD_TIME3_Msk
9802 #define DSI_DLTRCR_MRD_TIME4_Pos      (4U)
9803 #define DSI_DLTRCR_MRD_TIME4_Msk      (0x1UL << DSI_DLTRCR_MRD_TIME4_Pos)      /*!< 0x00000010 */
9804 #define DSI_DLTRCR_MRD_TIME4          DSI_DLTRCR_MRD_TIME4_Msk
9805 #define DSI_DLTRCR_MRD_TIME5_Pos      (5U)
9806 #define DSI_DLTRCR_MRD_TIME5_Msk      (0x1UL << DSI_DLTRCR_MRD_TIME5_Pos)      /*!< 0x00000020 */
9807 #define DSI_DLTRCR_MRD_TIME5          DSI_DLTRCR_MRD_TIME5_Msk
9808 #define DSI_DLTRCR_MRD_TIME6_Pos      (6U)
9809 #define DSI_DLTRCR_MRD_TIME6_Msk      (0x1UL << DSI_DLTRCR_MRD_TIME6_Pos)      /*!< 0x00000040 */
9810 #define DSI_DLTRCR_MRD_TIME6          DSI_DLTRCR_MRD_TIME6_Msk
9811 #define DSI_DLTRCR_MRD_TIME7_Pos      (7U)
9812 #define DSI_DLTRCR_MRD_TIME7_Msk      (0x1UL << DSI_DLTRCR_MRD_TIME7_Pos)      /*!< 0x00000080 */
9813 #define DSI_DLTRCR_MRD_TIME7          DSI_DLTRCR_MRD_TIME7_Msk
9814 #define DSI_DLTRCR_MRD_TIME8_Pos      (8U)
9815 #define DSI_DLTRCR_MRD_TIME8_Msk      (0x1UL << DSI_DLTRCR_MRD_TIME8_Pos)      /*!< 0x00000100 */
9816 #define DSI_DLTRCR_MRD_TIME8          DSI_DLTRCR_MRD_TIME8_Msk
9817 #define DSI_DLTRCR_MRD_TIME9_Pos      (9U)
9818 #define DSI_DLTRCR_MRD_TIME9_Msk      (0x1UL << DSI_DLTRCR_MRD_TIME9_Pos)      /*!< 0x00000200 */
9819 #define DSI_DLTRCR_MRD_TIME9          DSI_DLTRCR_MRD_TIME9_Msk
9820 #define DSI_DLTRCR_MRD_TIME10_Pos     (10U)
9821 #define DSI_DLTRCR_MRD_TIME10_Msk     (0x1UL << DSI_DLTRCR_MRD_TIME10_Pos)     /*!< 0x00000400 */
9822 #define DSI_DLTRCR_MRD_TIME10         DSI_DLTRCR_MRD_TIME10_Msk
9823 #define DSI_DLTRCR_MRD_TIME11_Pos     (11U)
9824 #define DSI_DLTRCR_MRD_TIME11_Msk     (0x1UL << DSI_DLTRCR_MRD_TIME11_Pos)     /*!< 0x00000800 */
9825 #define DSI_DLTRCR_MRD_TIME11         DSI_DLTRCR_MRD_TIME11_Msk
9826 #define DSI_DLTRCR_MRD_TIME12_Pos     (12U)
9827 #define DSI_DLTRCR_MRD_TIME12_Msk     (0x1UL << DSI_DLTRCR_MRD_TIME12_Pos)     /*!< 0x00001000 */
9828 #define DSI_DLTRCR_MRD_TIME12         DSI_DLTRCR_MRD_TIME12_Msk
9829 #define DSI_DLTRCR_MRD_TIME13_Pos     (13U)
9830 #define DSI_DLTRCR_MRD_TIME13_Msk     (0x1UL << DSI_DLTRCR_MRD_TIME13_Pos)     /*!< 0x00002000 */
9831 #define DSI_DLTRCR_MRD_TIME13         DSI_DLTRCR_MRD_TIME13_Msk
9832 #define DSI_DLTRCR_MRD_TIME14_Pos     (14U)
9833 #define DSI_DLTRCR_MRD_TIME14_Msk     (0x1UL << DSI_DLTRCR_MRD_TIME14_Pos)     /*!< 0x00004000 */
9834 #define DSI_DLTRCR_MRD_TIME14         DSI_DLTRCR_MRD_TIME14_Msk
9835 
9836 /*******************  Bit definition for DSI_VSCR register  ***************/
9837 #define DSI_VSCR_EN_Pos               (0U)
9838 #define DSI_VSCR_EN_Msk               (0x1UL << DSI_VSCR_EN_Pos)               /*!< 0x00000001 */
9839 #define DSI_VSCR_EN                   DSI_VSCR_EN_Msk                          /*!< Enable */
9840 #define DSI_VSCR_UR_Pos               (8U)
9841 #define DSI_VSCR_UR_Msk               (0x1UL << DSI_VSCR_UR_Pos)               /*!< 0x00000100 */
9842 #define DSI_VSCR_UR                   DSI_VSCR_UR_Msk                          /*!< Update Register */
9843 
9844 /*******************  Bit definition for DSI_LCVCIDR register  ************/
9845 #define DSI_LCVCIDR_VCID_Pos          (0U)
9846 #define DSI_LCVCIDR_VCID_Msk          (0x3UL << DSI_LCVCIDR_VCID_Pos)          /*!< 0x00000003 */
9847 #define DSI_LCVCIDR_VCID              DSI_LCVCIDR_VCID_Msk                     /*!< Virtual Channel ID */
9848 #define DSI_LCVCIDR_VCID0_Pos         (0U)
9849 #define DSI_LCVCIDR_VCID0_Msk         (0x1UL << DSI_LCVCIDR_VCID0_Pos)         /*!< 0x00000001 */
9850 #define DSI_LCVCIDR_VCID0             DSI_LCVCIDR_VCID0_Msk
9851 #define DSI_LCVCIDR_VCID1_Pos         (1U)
9852 #define DSI_LCVCIDR_VCID1_Msk         (0x1UL << DSI_LCVCIDR_VCID1_Pos)         /*!< 0x00000002 */
9853 #define DSI_LCVCIDR_VCID1             DSI_LCVCIDR_VCID1_Msk
9854 
9855 /*******************  Bit definition for DSI_LCCCR register  **************/
9856 #define DSI_LCCCR_COLC_Pos            (0U)
9857 #define DSI_LCCCR_COLC_Msk            (0xFUL << DSI_LCCCR_COLC_Pos)            /*!< 0x0000000F */
9858 #define DSI_LCCCR_COLC                DSI_LCCCR_COLC_Msk                       /*!< Color Coding */
9859 #define DSI_LCCCR_COLC0_Pos           (0U)
9860 #define DSI_LCCCR_COLC0_Msk           (0x1UL << DSI_LCCCR_COLC0_Pos)           /*!< 0x00000001 */
9861 #define DSI_LCCCR_COLC0               DSI_LCCCR_COLC0_Msk
9862 #define DSI_LCCCR_COLC1_Pos           (1U)
9863 #define DSI_LCCCR_COLC1_Msk           (0x1UL << DSI_LCCCR_COLC1_Pos)           /*!< 0x00000002 */
9864 #define DSI_LCCCR_COLC1               DSI_LCCCR_COLC1_Msk
9865 #define DSI_LCCCR_COLC2_Pos           (2U)
9866 #define DSI_LCCCR_COLC2_Msk           (0x1UL << DSI_LCCCR_COLC2_Pos)           /*!< 0x00000004 */
9867 #define DSI_LCCCR_COLC2               DSI_LCCCR_COLC2_Msk
9868 #define DSI_LCCCR_COLC3_Pos           (3U)
9869 #define DSI_LCCCR_COLC3_Msk           (0x1UL << DSI_LCCCR_COLC3_Pos)           /*!< 0x00000008 */
9870 #define DSI_LCCCR_COLC3               DSI_LCCCR_COLC3_Msk
9871 
9872 #define DSI_LCCCR_LPE_Pos             (8U)
9873 #define DSI_LCCCR_LPE_Msk             (0x1UL << DSI_LCCCR_LPE_Pos)             /*!< 0x00000100 */
9874 #define DSI_LCCCR_LPE                 DSI_LCCCR_LPE_Msk                        /*!< Loosely Packed Enable */
9875 
9876 /*******************  Bit definition for DSI_LPMCCR register  *************/
9877 #define DSI_LPMCCR_VLPSIZE_Pos        (0U)
9878 #define DSI_LPMCCR_VLPSIZE_Msk        (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos)       /*!< 0x000000FF */
9879 #define DSI_LPMCCR_VLPSIZE            DSI_LPMCCR_VLPSIZE_Msk                   /*!< VACT Largest Packet Size */
9880 #define DSI_LPMCCR_VLPSIZE0_Pos       (0U)
9881 #define DSI_LPMCCR_VLPSIZE0_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos)       /*!< 0x00000001 */
9882 #define DSI_LPMCCR_VLPSIZE0           DSI_LPMCCR_VLPSIZE0_Msk
9883 #define DSI_LPMCCR_VLPSIZE1_Pos       (1U)
9884 #define DSI_LPMCCR_VLPSIZE1_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos)       /*!< 0x00000002 */
9885 #define DSI_LPMCCR_VLPSIZE1           DSI_LPMCCR_VLPSIZE1_Msk
9886 #define DSI_LPMCCR_VLPSIZE2_Pos       (2U)
9887 #define DSI_LPMCCR_VLPSIZE2_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos)       /*!< 0x00000004 */
9888 #define DSI_LPMCCR_VLPSIZE2           DSI_LPMCCR_VLPSIZE2_Msk
9889 #define DSI_LPMCCR_VLPSIZE3_Pos       (3U)
9890 #define DSI_LPMCCR_VLPSIZE3_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos)       /*!< 0x00000008 */
9891 #define DSI_LPMCCR_VLPSIZE3           DSI_LPMCCR_VLPSIZE3_Msk
9892 #define DSI_LPMCCR_VLPSIZE4_Pos       (4U)
9893 #define DSI_LPMCCR_VLPSIZE4_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos)       /*!< 0x00000010 */
9894 #define DSI_LPMCCR_VLPSIZE4           DSI_LPMCCR_VLPSIZE4_Msk
9895 #define DSI_LPMCCR_VLPSIZE5_Pos       (5U)
9896 #define DSI_LPMCCR_VLPSIZE5_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos)       /*!< 0x00000020 */
9897 #define DSI_LPMCCR_VLPSIZE5           DSI_LPMCCR_VLPSIZE5_Msk
9898 #define DSI_LPMCCR_VLPSIZE6_Pos       (6U)
9899 #define DSI_LPMCCR_VLPSIZE6_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos)       /*!< 0x00000040 */
9900 #define DSI_LPMCCR_VLPSIZE6           DSI_LPMCCR_VLPSIZE6_Msk
9901 #define DSI_LPMCCR_VLPSIZE7_Pos       (7U)
9902 #define DSI_LPMCCR_VLPSIZE7_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos)       /*!< 0x00000080 */
9903 #define DSI_LPMCCR_VLPSIZE7           DSI_LPMCCR_VLPSIZE7_Msk
9904 
9905 #define DSI_LPMCCR_LPSIZE_Pos         (16U)
9906 #define DSI_LPMCCR_LPSIZE_Msk         (0xFFUL << DSI_LPMCCR_LPSIZE_Pos)        /*!< 0x00FF0000 */
9907 #define DSI_LPMCCR_LPSIZE             DSI_LPMCCR_LPSIZE_Msk                    /*!< Largest Packet Size */
9908 #define DSI_LPMCCR_LPSIZE0_Pos        (16U)
9909 #define DSI_LPMCCR_LPSIZE0_Msk        (0x1UL << DSI_LPMCCR_LPSIZE0_Pos)        /*!< 0x00010000 */
9910 #define DSI_LPMCCR_LPSIZE0            DSI_LPMCCR_LPSIZE0_Msk
9911 #define DSI_LPMCCR_LPSIZE1_Pos        (17U)
9912 #define DSI_LPMCCR_LPSIZE1_Msk        (0x1UL << DSI_LPMCCR_LPSIZE1_Pos)        /*!< 0x00020000 */
9913 #define DSI_LPMCCR_LPSIZE1            DSI_LPMCCR_LPSIZE1_Msk
9914 #define DSI_LPMCCR_LPSIZE2_Pos        (18U)
9915 #define DSI_LPMCCR_LPSIZE2_Msk        (0x1UL << DSI_LPMCCR_LPSIZE2_Pos)        /*!< 0x00040000 */
9916 #define DSI_LPMCCR_LPSIZE2            DSI_LPMCCR_LPSIZE2_Msk
9917 #define DSI_LPMCCR_LPSIZE3_Pos        (19U)
9918 #define DSI_LPMCCR_LPSIZE3_Msk        (0x1UL << DSI_LPMCCR_LPSIZE3_Pos)        /*!< 0x00080000 */
9919 #define DSI_LPMCCR_LPSIZE3            DSI_LPMCCR_LPSIZE3_Msk
9920 #define DSI_LPMCCR_LPSIZE4_Pos        (20U)
9921 #define DSI_LPMCCR_LPSIZE4_Msk        (0x1UL << DSI_LPMCCR_LPSIZE4_Pos)        /*!< 0x00100000 */
9922 #define DSI_LPMCCR_LPSIZE4            DSI_LPMCCR_LPSIZE4_Msk
9923 #define DSI_LPMCCR_LPSIZE5_Pos        (21U)
9924 #define DSI_LPMCCR_LPSIZE5_Msk        (0x1UL << DSI_LPMCCR_LPSIZE5_Pos)        /*!< 0x00200000 */
9925 #define DSI_LPMCCR_LPSIZE5            DSI_LPMCCR_LPSIZE5_Msk
9926 #define DSI_LPMCCR_LPSIZE6_Pos        (22U)
9927 #define DSI_LPMCCR_LPSIZE6_Msk        (0x1UL << DSI_LPMCCR_LPSIZE6_Pos)        /*!< 0x00400000 */
9928 #define DSI_LPMCCR_LPSIZE6            DSI_LPMCCR_LPSIZE6_Msk
9929 #define DSI_LPMCCR_LPSIZE7_Pos        (23U)
9930 #define DSI_LPMCCR_LPSIZE7_Msk        (0x1UL << DSI_LPMCCR_LPSIZE7_Pos)        /*!< 0x00800000 */
9931 #define DSI_LPMCCR_LPSIZE7            DSI_LPMCCR_LPSIZE7_Msk
9932 
9933 /*******************  Bit definition for DSI_VMCCR register  **************/
9934 #define DSI_VMCCR_VMT_Pos             (0U)
9935 #define DSI_VMCCR_VMT_Msk             (0x3UL << DSI_VMCCR_VMT_Pos)             /*!< 0x00000003 */
9936 #define DSI_VMCCR_VMT                 DSI_VMCCR_VMT_Msk                        /*!< Video Mode Type */
9937 #define DSI_VMCCR_VMT0_Pos            (0U)
9938 #define DSI_VMCCR_VMT0_Msk            (0x1UL << DSI_VMCCR_VMT0_Pos)            /*!< 0x00000001 */
9939 #define DSI_VMCCR_VMT0                DSI_VMCCR_VMT0_Msk
9940 #define DSI_VMCCR_VMT1_Pos            (1U)
9941 #define DSI_VMCCR_VMT1_Msk            (0x1UL << DSI_VMCCR_VMT1_Pos)            /*!< 0x00000002 */
9942 #define DSI_VMCCR_VMT1                DSI_VMCCR_VMT1_Msk
9943 
9944 #define DSI_VMCCR_LPVSAE_Pos          (8U)
9945 #define DSI_VMCCR_LPVSAE_Msk          (0x1UL << DSI_VMCCR_LPVSAE_Pos)          /*!< 0x00000100 */
9946 #define DSI_VMCCR_LPVSAE              DSI_VMCCR_LPVSAE_Msk                     /*!< Low-power Vertical Sync time Enable */
9947 #define DSI_VMCCR_LPVBPE_Pos          (9U)
9948 #define DSI_VMCCR_LPVBPE_Msk          (0x1UL << DSI_VMCCR_LPVBPE_Pos)          /*!< 0x00000200 */
9949 #define DSI_VMCCR_LPVBPE              DSI_VMCCR_LPVBPE_Msk                     /*!< Low-power Vertical Back-porch Enable */
9950 #define DSI_VMCCR_LPVFPE_Pos          (10U)
9951 #define DSI_VMCCR_LPVFPE_Msk          (0x1UL << DSI_VMCCR_LPVFPE_Pos)          /*!< 0x00000400 */
9952 #define DSI_VMCCR_LPVFPE              DSI_VMCCR_LPVFPE_Msk                     /*!< Low-power Vertical Front-porch Enable */
9953 #define DSI_VMCCR_LPVAE_Pos           (11U)
9954 #define DSI_VMCCR_LPVAE_Msk           (0x1UL << DSI_VMCCR_LPVAE_Pos)           /*!< 0x00000800 */
9955 #define DSI_VMCCR_LPVAE               DSI_VMCCR_LPVAE_Msk                      /*!< Low-power Vertical Active Enable */
9956 #define DSI_VMCCR_LPHBPE_Pos          (12U)
9957 #define DSI_VMCCR_LPHBPE_Msk          (0x1UL << DSI_VMCCR_LPHBPE_Pos)          /*!< 0x00001000 */
9958 #define DSI_VMCCR_LPHBPE              DSI_VMCCR_LPHBPE_Msk                     /*!< Low-power Horizontal Back-porch Enable */
9959 #define DSI_VMCCR_LPHFE_Pos           (13U)
9960 #define DSI_VMCCR_LPHFE_Msk           (0x1UL << DSI_VMCCR_LPHFE_Pos)           /*!< 0x00002000 */
9961 #define DSI_VMCCR_LPHFE               DSI_VMCCR_LPHFE_Msk                      /*!< Low-power Horizontal Front-porch Enable */
9962 #define DSI_VMCCR_FBTAAE_Pos          (14U)
9963 #define DSI_VMCCR_FBTAAE_Msk          (0x1UL << DSI_VMCCR_FBTAAE_Pos)          /*!< 0x00004000 */
9964 #define DSI_VMCCR_FBTAAE              DSI_VMCCR_FBTAAE_Msk                     /*!< Frame BTA Acknowledge Enable */
9965 #define DSI_VMCCR_LPCE_Pos            (15U)
9966 #define DSI_VMCCR_LPCE_Msk            (0x1UL << DSI_VMCCR_LPCE_Pos)            /*!< 0x00008000 */
9967 #define DSI_VMCCR_LPCE                DSI_VMCCR_LPCE_Msk                       /*!< Low-power Command Enable */
9968 
9969 /*******************  Bit definition for DSI_VPCCR register  **************/
9970 #define DSI_VPCCR_VPSIZE_Pos          (0U)
9971 #define DSI_VPCCR_VPSIZE_Msk          (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos)       /*!< 0x00003FFF */
9972 #define DSI_VPCCR_VPSIZE              DSI_VPCCR_VPSIZE_Msk                     /*!< Video Packet Size */
9973 #define DSI_VPCCR_VPSIZE0_Pos         (0U)
9974 #define DSI_VPCCR_VPSIZE0_Msk         (0x1UL << DSI_VPCCR_VPSIZE0_Pos)         /*!< 0x00000001 */
9975 #define DSI_VPCCR_VPSIZE0             DSI_VPCCR_VPSIZE0_Msk
9976 #define DSI_VPCCR_VPSIZE1_Pos         (1U)
9977 #define DSI_VPCCR_VPSIZE1_Msk         (0x1UL << DSI_VPCCR_VPSIZE1_Pos)         /*!< 0x00000002 */
9978 #define DSI_VPCCR_VPSIZE1             DSI_VPCCR_VPSIZE1_Msk
9979 #define DSI_VPCCR_VPSIZE2_Pos         (2U)
9980 #define DSI_VPCCR_VPSIZE2_Msk         (0x1UL << DSI_VPCCR_VPSIZE2_Pos)         /*!< 0x00000004 */
9981 #define DSI_VPCCR_VPSIZE2             DSI_VPCCR_VPSIZE2_Msk
9982 #define DSI_VPCCR_VPSIZE3_Pos         (3U)
9983 #define DSI_VPCCR_VPSIZE3_Msk         (0x1UL << DSI_VPCCR_VPSIZE3_Pos)         /*!< 0x00000008 */
9984 #define DSI_VPCCR_VPSIZE3             DSI_VPCCR_VPSIZE3_Msk
9985 #define DSI_VPCCR_VPSIZE4_Pos         (4U)
9986 #define DSI_VPCCR_VPSIZE4_Msk         (0x1UL << DSI_VPCCR_VPSIZE4_Pos)         /*!< 0x00000010 */
9987 #define DSI_VPCCR_VPSIZE4             DSI_VPCCR_VPSIZE4_Msk
9988 #define DSI_VPCCR_VPSIZE5_Pos         (5U)
9989 #define DSI_VPCCR_VPSIZE5_Msk         (0x1UL << DSI_VPCCR_VPSIZE5_Pos)         /*!< 0x00000020 */
9990 #define DSI_VPCCR_VPSIZE5             DSI_VPCCR_VPSIZE5_Msk
9991 #define DSI_VPCCR_VPSIZE6_Pos         (6U)
9992 #define DSI_VPCCR_VPSIZE6_Msk         (0x1UL << DSI_VPCCR_VPSIZE6_Pos)         /*!< 0x00000040 */
9993 #define DSI_VPCCR_VPSIZE6             DSI_VPCCR_VPSIZE6_Msk
9994 #define DSI_VPCCR_VPSIZE7_Pos         (7U)
9995 #define DSI_VPCCR_VPSIZE7_Msk         (0x1UL << DSI_VPCCR_VPSIZE7_Pos)         /*!< 0x00000080 */
9996 #define DSI_VPCCR_VPSIZE7             DSI_VPCCR_VPSIZE7_Msk
9997 #define DSI_VPCCR_VPSIZE8_Pos         (8U)
9998 #define DSI_VPCCR_VPSIZE8_Msk         (0x1UL << DSI_VPCCR_VPSIZE8_Pos)         /*!< 0x00000100 */
9999 #define DSI_VPCCR_VPSIZE8             DSI_VPCCR_VPSIZE8_Msk
10000 #define DSI_VPCCR_VPSIZE9_Pos         (9U)
10001 #define DSI_VPCCR_VPSIZE9_Msk         (0x1UL << DSI_VPCCR_VPSIZE9_Pos)         /*!< 0x00000200 */
10002 #define DSI_VPCCR_VPSIZE9             DSI_VPCCR_VPSIZE9_Msk
10003 #define DSI_VPCCR_VPSIZE10_Pos        (10U)
10004 #define DSI_VPCCR_VPSIZE10_Msk        (0x1UL << DSI_VPCCR_VPSIZE10_Pos)        /*!< 0x00000400 */
10005 #define DSI_VPCCR_VPSIZE10            DSI_VPCCR_VPSIZE10_Msk
10006 #define DSI_VPCCR_VPSIZE11_Pos        (11U)
10007 #define DSI_VPCCR_VPSIZE11_Msk        (0x1UL << DSI_VPCCR_VPSIZE11_Pos)        /*!< 0x00000800 */
10008 #define DSI_VPCCR_VPSIZE11            DSI_VPCCR_VPSIZE11_Msk
10009 #define DSI_VPCCR_VPSIZE12_Pos        (12U)
10010 #define DSI_VPCCR_VPSIZE12_Msk        (0x1UL << DSI_VPCCR_VPSIZE12_Pos)        /*!< 0x00001000 */
10011 #define DSI_VPCCR_VPSIZE12            DSI_VPCCR_VPSIZE12_Msk
10012 #define DSI_VPCCR_VPSIZE13_Pos        (13U)
10013 #define DSI_VPCCR_VPSIZE13_Msk        (0x1UL << DSI_VPCCR_VPSIZE13_Pos)        /*!< 0x00002000 */
10014 #define DSI_VPCCR_VPSIZE13            DSI_VPCCR_VPSIZE13_Msk
10015 
10016 /*******************  Bit definition for DSI_VCCCR register  **************/
10017 #define DSI_VCCCR_NUMC_Pos            (0U)
10018 #define DSI_VCCCR_NUMC_Msk            (0x1FFFUL << DSI_VCCCR_NUMC_Pos)         /*!< 0x00001FFF */
10019 #define DSI_VCCCR_NUMC                DSI_VCCCR_NUMC_Msk                       /*!< Number of Chunks */
10020 #define DSI_VCCCR_NUMC0_Pos           (0U)
10021 #define DSI_VCCCR_NUMC0_Msk           (0x1UL << DSI_VCCCR_NUMC0_Pos)           /*!< 0x00000001 */
10022 #define DSI_VCCCR_NUMC0               DSI_VCCCR_NUMC0_Msk
10023 #define DSI_VCCCR_NUMC1_Pos           (1U)
10024 #define DSI_VCCCR_NUMC1_Msk           (0x1UL << DSI_VCCCR_NUMC1_Pos)           /*!< 0x00000002 */
10025 #define DSI_VCCCR_NUMC1               DSI_VCCCR_NUMC1_Msk
10026 #define DSI_VCCCR_NUMC2_Pos           (2U)
10027 #define DSI_VCCCR_NUMC2_Msk           (0x1UL << DSI_VCCCR_NUMC2_Pos)           /*!< 0x00000004 */
10028 #define DSI_VCCCR_NUMC2               DSI_VCCCR_NUMC2_Msk
10029 #define DSI_VCCCR_NUMC3_Pos           (3U)
10030 #define DSI_VCCCR_NUMC3_Msk           (0x1UL << DSI_VCCCR_NUMC3_Pos)           /*!< 0x00000008 */
10031 #define DSI_VCCCR_NUMC3               DSI_VCCCR_NUMC3_Msk
10032 #define DSI_VCCCR_NUMC4_Pos           (4U)
10033 #define DSI_VCCCR_NUMC4_Msk           (0x1UL << DSI_VCCCR_NUMC4_Pos)           /*!< 0x00000010 */
10034 #define DSI_VCCCR_NUMC4               DSI_VCCCR_NUMC4_Msk
10035 #define DSI_VCCCR_NUMC5_Pos           (5U)
10036 #define DSI_VCCCR_NUMC5_Msk           (0x1UL << DSI_VCCCR_NUMC5_Pos)           /*!< 0x00000020 */
10037 #define DSI_VCCCR_NUMC5               DSI_VCCCR_NUMC5_Msk
10038 #define DSI_VCCCR_NUMC6_Pos           (6U)
10039 #define DSI_VCCCR_NUMC6_Msk           (0x1UL << DSI_VCCCR_NUMC6_Pos)           /*!< 0x00000040 */
10040 #define DSI_VCCCR_NUMC6               DSI_VCCCR_NUMC6_Msk
10041 #define DSI_VCCCR_NUMC7_Pos           (7U)
10042 #define DSI_VCCCR_NUMC7_Msk           (0x1UL << DSI_VCCCR_NUMC7_Pos)           /*!< 0x00000080 */
10043 #define DSI_VCCCR_NUMC7               DSI_VCCCR_NUMC7_Msk
10044 #define DSI_VCCCR_NUMC8_Pos           (8U)
10045 #define DSI_VCCCR_NUMC8_Msk           (0x1UL << DSI_VCCCR_NUMC8_Pos)           /*!< 0x00000100 */
10046 #define DSI_VCCCR_NUMC8               DSI_VCCCR_NUMC8_Msk
10047 #define DSI_VCCCR_NUMC9_Pos           (9U)
10048 #define DSI_VCCCR_NUMC9_Msk           (0x1UL << DSI_VCCCR_NUMC9_Pos)           /*!< 0x00000200 */
10049 #define DSI_VCCCR_NUMC9               DSI_VCCCR_NUMC9_Msk
10050 #define DSI_VCCCR_NUMC10_Pos          (10U)
10051 #define DSI_VCCCR_NUMC10_Msk          (0x1UL << DSI_VCCCR_NUMC10_Pos)          /*!< 0x00000400 */
10052 #define DSI_VCCCR_NUMC10              DSI_VCCCR_NUMC10_Msk
10053 #define DSI_VCCCR_NUMC11_Pos          (11U)
10054 #define DSI_VCCCR_NUMC11_Msk          (0x1UL << DSI_VCCCR_NUMC11_Pos)          /*!< 0x00000800 */
10055 #define DSI_VCCCR_NUMC11              DSI_VCCCR_NUMC11_Msk
10056 #define DSI_VCCCR_NUMC12_Pos          (12U)
10057 #define DSI_VCCCR_NUMC12_Msk          (0x1UL << DSI_VCCCR_NUMC12_Pos)          /*!< 0x00001000 */
10058 #define DSI_VCCCR_NUMC12              DSI_VCCCR_NUMC12_Msk
10059 
10060 /*******************  Bit definition for DSI_VNPCCR register  *************/
10061 #define DSI_VNPCCR_NPSIZE_Pos         (0U)
10062 #define DSI_VNPCCR_NPSIZE_Msk         (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos)      /*!< 0x00001FFF */
10063 #define DSI_VNPCCR_NPSIZE             DSI_VNPCCR_NPSIZE_Msk                    /*!< Number of Chunks */
10064 #define DSI_VNPCCR_NPSIZE0_Pos        (0U)
10065 #define DSI_VNPCCR_NPSIZE0_Msk        (0x1UL << DSI_VNPCCR_NPSIZE0_Pos)        /*!< 0x00000001 */
10066 #define DSI_VNPCCR_NPSIZE0            DSI_VNPCCR_NPSIZE0_Msk
10067 #define DSI_VNPCCR_NPSIZE1_Pos        (1U)
10068 #define DSI_VNPCCR_NPSIZE1_Msk        (0x1UL << DSI_VNPCCR_NPSIZE1_Pos)        /*!< 0x00000002 */
10069 #define DSI_VNPCCR_NPSIZE1            DSI_VNPCCR_NPSIZE1_Msk
10070 #define DSI_VNPCCR_NPSIZE2_Pos        (2U)
10071 #define DSI_VNPCCR_NPSIZE2_Msk        (0x1UL << DSI_VNPCCR_NPSIZE2_Pos)        /*!< 0x00000004 */
10072 #define DSI_VNPCCR_NPSIZE2            DSI_VNPCCR_NPSIZE2_Msk
10073 #define DSI_VNPCCR_NPSIZE3_Pos        (3U)
10074 #define DSI_VNPCCR_NPSIZE3_Msk        (0x1UL << DSI_VNPCCR_NPSIZE3_Pos)        /*!< 0x00000008 */
10075 #define DSI_VNPCCR_NPSIZE3            DSI_VNPCCR_NPSIZE3_Msk
10076 #define DSI_VNPCCR_NPSIZE4_Pos        (4U)
10077 #define DSI_VNPCCR_NPSIZE4_Msk        (0x1UL << DSI_VNPCCR_NPSIZE4_Pos)        /*!< 0x00000010 */
10078 #define DSI_VNPCCR_NPSIZE4            DSI_VNPCCR_NPSIZE4_Msk
10079 #define DSI_VNPCCR_NPSIZE5_Pos        (5U)
10080 #define DSI_VNPCCR_NPSIZE5_Msk        (0x1UL << DSI_VNPCCR_NPSIZE5_Pos)        /*!< 0x00000020 */
10081 #define DSI_VNPCCR_NPSIZE5            DSI_VNPCCR_NPSIZE5_Msk
10082 #define DSI_VNPCCR_NPSIZE6_Pos        (6U)
10083 #define DSI_VNPCCR_NPSIZE6_Msk        (0x1UL << DSI_VNPCCR_NPSIZE6_Pos)        /*!< 0x00000040 */
10084 #define DSI_VNPCCR_NPSIZE6            DSI_VNPCCR_NPSIZE6_Msk
10085 #define DSI_VNPCCR_NPSIZE7_Pos        (7U)
10086 #define DSI_VNPCCR_NPSIZE7_Msk        (0x1UL << DSI_VNPCCR_NPSIZE7_Pos)        /*!< 0x00000080 */
10087 #define DSI_VNPCCR_NPSIZE7            DSI_VNPCCR_NPSIZE7_Msk
10088 #define DSI_VNPCCR_NPSIZE8_Pos        (8U)
10089 #define DSI_VNPCCR_NPSIZE8_Msk        (0x1UL << DSI_VNPCCR_NPSIZE8_Pos)        /*!< 0x00000100 */
10090 #define DSI_VNPCCR_NPSIZE8            DSI_VNPCCR_NPSIZE8_Msk
10091 #define DSI_VNPCCR_NPSIZE9_Pos        (9U)
10092 #define DSI_VNPCCR_NPSIZE9_Msk        (0x1UL << DSI_VNPCCR_NPSIZE9_Pos)        /*!< 0x00000200 */
10093 #define DSI_VNPCCR_NPSIZE9            DSI_VNPCCR_NPSIZE9_Msk
10094 #define DSI_VNPCCR_NPSIZE10_Pos       (10U)
10095 #define DSI_VNPCCR_NPSIZE10_Msk       (0x1UL << DSI_VNPCCR_NPSIZE10_Pos)       /*!< 0x00000400 */
10096 #define DSI_VNPCCR_NPSIZE10           DSI_VNPCCR_NPSIZE10_Msk
10097 #define DSI_VNPCCR_NPSIZE11_Pos       (11U)
10098 #define DSI_VNPCCR_NPSIZE11_Msk       (0x1UL << DSI_VNPCCR_NPSIZE11_Pos)       /*!< 0x00000800 */
10099 #define DSI_VNPCCR_NPSIZE11           DSI_VNPCCR_NPSIZE11_Msk
10100 #define DSI_VNPCCR_NPSIZE12_Pos       (12U)
10101 #define DSI_VNPCCR_NPSIZE12_Msk       (0x1UL << DSI_VNPCCR_NPSIZE12_Pos)       /*!< 0x00001000 */
10102 #define DSI_VNPCCR_NPSIZE12           DSI_VNPCCR_NPSIZE12_Msk
10103 
10104 /*******************  Bit definition for DSI_VHSACCR register  ************/
10105 #define DSI_VHSACCR_HSA_Pos           (0U)
10106 #define DSI_VHSACCR_HSA_Msk           (0xFFFUL << DSI_VHSACCR_HSA_Pos)         /*!< 0x00000FFF */
10107 #define DSI_VHSACCR_HSA               DSI_VHSACCR_HSA_Msk                      /*!< Horizontal Synchronism Active duration */
10108 #define DSI_VHSACCR_HSA0_Pos          (0U)
10109 #define DSI_VHSACCR_HSA0_Msk          (0x1UL << DSI_VHSACCR_HSA0_Pos)          /*!< 0x00000001 */
10110 #define DSI_VHSACCR_HSA0              DSI_VHSACCR_HSA0_Msk
10111 #define DSI_VHSACCR_HSA1_Pos          (1U)
10112 #define DSI_VHSACCR_HSA1_Msk          (0x1UL << DSI_VHSACCR_HSA1_Pos)          /*!< 0x00000002 */
10113 #define DSI_VHSACCR_HSA1              DSI_VHSACCR_HSA1_Msk
10114 #define DSI_VHSACCR_HSA2_Pos          (2U)
10115 #define DSI_VHSACCR_HSA2_Msk          (0x1UL << DSI_VHSACCR_HSA2_Pos)          /*!< 0x00000004 */
10116 #define DSI_VHSACCR_HSA2              DSI_VHSACCR_HSA2_Msk
10117 #define DSI_VHSACCR_HSA3_Pos          (3U)
10118 #define DSI_VHSACCR_HSA3_Msk          (0x1UL << DSI_VHSACCR_HSA3_Pos)          /*!< 0x00000008 */
10119 #define DSI_VHSACCR_HSA3              DSI_VHSACCR_HSA3_Msk
10120 #define DSI_VHSACCR_HSA4_Pos          (4U)
10121 #define DSI_VHSACCR_HSA4_Msk          (0x1UL << DSI_VHSACCR_HSA4_Pos)          /*!< 0x00000010 */
10122 #define DSI_VHSACCR_HSA4              DSI_VHSACCR_HSA4_Msk
10123 #define DSI_VHSACCR_HSA5_Pos          (5U)
10124 #define DSI_VHSACCR_HSA5_Msk          (0x1UL << DSI_VHSACCR_HSA5_Pos)          /*!< 0x00000020 */
10125 #define DSI_VHSACCR_HSA5              DSI_VHSACCR_HSA5_Msk
10126 #define DSI_VHSACCR_HSA6_Pos          (6U)
10127 #define DSI_VHSACCR_HSA6_Msk          (0x1UL << DSI_VHSACCR_HSA6_Pos)          /*!< 0x00000040 */
10128 #define DSI_VHSACCR_HSA6              DSI_VHSACCR_HSA6_Msk
10129 #define DSI_VHSACCR_HSA7_Pos          (7U)
10130 #define DSI_VHSACCR_HSA7_Msk          (0x1UL << DSI_VHSACCR_HSA7_Pos)          /*!< 0x00000080 */
10131 #define DSI_VHSACCR_HSA7              DSI_VHSACCR_HSA7_Msk
10132 #define DSI_VHSACCR_HSA8_Pos          (8U)
10133 #define DSI_VHSACCR_HSA8_Msk          (0x1UL << DSI_VHSACCR_HSA8_Pos)          /*!< 0x00000100 */
10134 #define DSI_VHSACCR_HSA8              DSI_VHSACCR_HSA8_Msk
10135 #define DSI_VHSACCR_HSA9_Pos          (9U)
10136 #define DSI_VHSACCR_HSA9_Msk          (0x1UL << DSI_VHSACCR_HSA9_Pos)          /*!< 0x00000200 */
10137 #define DSI_VHSACCR_HSA9              DSI_VHSACCR_HSA9_Msk
10138 #define DSI_VHSACCR_HSA10_Pos         (10U)
10139 #define DSI_VHSACCR_HSA10_Msk         (0x1UL << DSI_VHSACCR_HSA10_Pos)         /*!< 0x00000400 */
10140 #define DSI_VHSACCR_HSA10             DSI_VHSACCR_HSA10_Msk
10141 #define DSI_VHSACCR_HSA11_Pos         (11U)
10142 #define DSI_VHSACCR_HSA11_Msk         (0x1UL << DSI_VHSACCR_HSA11_Pos)         /*!< 0x00000800 */
10143 #define DSI_VHSACCR_HSA11             DSI_VHSACCR_HSA11_Msk
10144 
10145 /*******************  Bit definition for DSI_VHBPCCR register  ************/
10146 #define DSI_VHBPCCR_HBP_Pos           (0U)
10147 #define DSI_VHBPCCR_HBP_Msk           (0xFFFUL << DSI_VHBPCCR_HBP_Pos)         /*!< 0x00000FFF */
10148 #define DSI_VHBPCCR_HBP               DSI_VHBPCCR_HBP_Msk                      /*!< Horizontal Back-Porch duration */
10149 #define DSI_VHBPCCR_HBP0_Pos          (0U)
10150 #define DSI_VHBPCCR_HBP0_Msk          (0x1UL << DSI_VHBPCCR_HBP0_Pos)          /*!< 0x00000001 */
10151 #define DSI_VHBPCCR_HBP0              DSI_VHBPCCR_HBP0_Msk
10152 #define DSI_VHBPCCR_HBP1_Pos          (1U)
10153 #define DSI_VHBPCCR_HBP1_Msk          (0x1UL << DSI_VHBPCCR_HBP1_Pos)          /*!< 0x00000002 */
10154 #define DSI_VHBPCCR_HBP1              DSI_VHBPCCR_HBP1_Msk
10155 #define DSI_VHBPCCR_HBP2_Pos          (2U)
10156 #define DSI_VHBPCCR_HBP2_Msk          (0x1UL << DSI_VHBPCCR_HBP2_Pos)          /*!< 0x00000004 */
10157 #define DSI_VHBPCCR_HBP2              DSI_VHBPCCR_HBP2_Msk
10158 #define DSI_VHBPCCR_HBP3_Pos          (3U)
10159 #define DSI_VHBPCCR_HBP3_Msk          (0x1UL << DSI_VHBPCCR_HBP3_Pos)          /*!< 0x00000008 */
10160 #define DSI_VHBPCCR_HBP3              DSI_VHBPCCR_HBP3_Msk
10161 #define DSI_VHBPCCR_HBP4_Pos          (4U)
10162 #define DSI_VHBPCCR_HBP4_Msk          (0x1UL << DSI_VHBPCCR_HBP4_Pos)          /*!< 0x00000010 */
10163 #define DSI_VHBPCCR_HBP4              DSI_VHBPCCR_HBP4_Msk
10164 #define DSI_VHBPCCR_HBP5_Pos          (5U)
10165 #define DSI_VHBPCCR_HBP5_Msk          (0x1UL << DSI_VHBPCCR_HBP5_Pos)          /*!< 0x00000020 */
10166 #define DSI_VHBPCCR_HBP5              DSI_VHBPCCR_HBP5_Msk
10167 #define DSI_VHBPCCR_HBP6_Pos          (6U)
10168 #define DSI_VHBPCCR_HBP6_Msk          (0x1UL << DSI_VHBPCCR_HBP6_Pos)          /*!< 0x00000040 */
10169 #define DSI_VHBPCCR_HBP6              DSI_VHBPCCR_HBP6_Msk
10170 #define DSI_VHBPCCR_HBP7_Pos          (7U)
10171 #define DSI_VHBPCCR_HBP7_Msk          (0x1UL << DSI_VHBPCCR_HBP7_Pos)          /*!< 0x00000080 */
10172 #define DSI_VHBPCCR_HBP7              DSI_VHBPCCR_HBP7_Msk
10173 #define DSI_VHBPCCR_HBP8_Pos          (8U)
10174 #define DSI_VHBPCCR_HBP8_Msk          (0x1UL << DSI_VHBPCCR_HBP8_Pos)          /*!< 0x00000100 */
10175 #define DSI_VHBPCCR_HBP8              DSI_VHBPCCR_HBP8_Msk
10176 #define DSI_VHBPCCR_HBP9_Pos          (9U)
10177 #define DSI_VHBPCCR_HBP9_Msk          (0x1UL << DSI_VHBPCCR_HBP9_Pos)          /*!< 0x00000200 */
10178 #define DSI_VHBPCCR_HBP9              DSI_VHBPCCR_HBP9_Msk
10179 #define DSI_VHBPCCR_HBP10_Pos         (10U)
10180 #define DSI_VHBPCCR_HBP10_Msk         (0x1UL << DSI_VHBPCCR_HBP10_Pos)         /*!< 0x00000400 */
10181 #define DSI_VHBPCCR_HBP10             DSI_VHBPCCR_HBP10_Msk
10182 #define DSI_VHBPCCR_HBP11_Pos         (11U)
10183 #define DSI_VHBPCCR_HBP11_Msk         (0x1UL << DSI_VHBPCCR_HBP11_Pos)         /*!< 0x00000800 */
10184 #define DSI_VHBPCCR_HBP11             DSI_VHBPCCR_HBP11_Msk
10185 
10186 /*******************  Bit definition for DSI_VLCCR register  **************/
10187 #define DSI_VLCCR_HLINE_Pos           (0U)
10188 #define DSI_VLCCR_HLINE_Msk           (0x7FFFUL << DSI_VLCCR_HLINE_Pos)        /*!< 0x00007FFF */
10189 #define DSI_VLCCR_HLINE               DSI_VLCCR_HLINE_Msk                      /*!< Horizontal Line duration */
10190 #define DSI_VLCCR_HLINE0_Pos          (0U)
10191 #define DSI_VLCCR_HLINE0_Msk          (0x1UL << DSI_VLCCR_HLINE0_Pos)          /*!< 0x00000001 */
10192 #define DSI_VLCCR_HLINE0              DSI_VLCCR_HLINE0_Msk
10193 #define DSI_VLCCR_HLINE1_Pos          (1U)
10194 #define DSI_VLCCR_HLINE1_Msk          (0x1UL << DSI_VLCCR_HLINE1_Pos)          /*!< 0x00000002 */
10195 #define DSI_VLCCR_HLINE1              DSI_VLCCR_HLINE1_Msk
10196 #define DSI_VLCCR_HLINE2_Pos          (2U)
10197 #define DSI_VLCCR_HLINE2_Msk          (0x1UL << DSI_VLCCR_HLINE2_Pos)          /*!< 0x00000004 */
10198 #define DSI_VLCCR_HLINE2              DSI_VLCCR_HLINE2_Msk
10199 #define DSI_VLCCR_HLINE3_Pos          (3U)
10200 #define DSI_VLCCR_HLINE3_Msk          (0x1UL << DSI_VLCCR_HLINE3_Pos)          /*!< 0x00000008 */
10201 #define DSI_VLCCR_HLINE3              DSI_VLCCR_HLINE3_Msk
10202 #define DSI_VLCCR_HLINE4_Pos          (4U)
10203 #define DSI_VLCCR_HLINE4_Msk          (0x1UL << DSI_VLCCR_HLINE4_Pos)          /*!< 0x00000010 */
10204 #define DSI_VLCCR_HLINE4              DSI_VLCCR_HLINE4_Msk
10205 #define DSI_VLCCR_HLINE5_Pos          (5U)
10206 #define DSI_VLCCR_HLINE5_Msk          (0x1UL << DSI_VLCCR_HLINE5_Pos)          /*!< 0x00000020 */
10207 #define DSI_VLCCR_HLINE5              DSI_VLCCR_HLINE5_Msk
10208 #define DSI_VLCCR_HLINE6_Pos          (6U)
10209 #define DSI_VLCCR_HLINE6_Msk          (0x1UL << DSI_VLCCR_HLINE6_Pos)          /*!< 0x00000040 */
10210 #define DSI_VLCCR_HLINE6              DSI_VLCCR_HLINE6_Msk
10211 #define DSI_VLCCR_HLINE7_Pos          (7U)
10212 #define DSI_VLCCR_HLINE7_Msk          (0x1UL << DSI_VLCCR_HLINE7_Pos)          /*!< 0x00000080 */
10213 #define DSI_VLCCR_HLINE7              DSI_VLCCR_HLINE7_Msk
10214 #define DSI_VLCCR_HLINE8_Pos          (8U)
10215 #define DSI_VLCCR_HLINE8_Msk          (0x1UL << DSI_VLCCR_HLINE8_Pos)          /*!< 0x00000100 */
10216 #define DSI_VLCCR_HLINE8              DSI_VLCCR_HLINE8_Msk
10217 #define DSI_VLCCR_HLINE9_Pos          (9U)
10218 #define DSI_VLCCR_HLINE9_Msk          (0x1UL << DSI_VLCCR_HLINE9_Pos)          /*!< 0x00000200 */
10219 #define DSI_VLCCR_HLINE9              DSI_VLCCR_HLINE9_Msk
10220 #define DSI_VLCCR_HLINE10_Pos         (10U)
10221 #define DSI_VLCCR_HLINE10_Msk         (0x1UL << DSI_VLCCR_HLINE10_Pos)         /*!< 0x00000400 */
10222 #define DSI_VLCCR_HLINE10             DSI_VLCCR_HLINE10_Msk
10223 #define DSI_VLCCR_HLINE11_Pos         (11U)
10224 #define DSI_VLCCR_HLINE11_Msk         (0x1UL << DSI_VLCCR_HLINE11_Pos)         /*!< 0x00000800 */
10225 #define DSI_VLCCR_HLINE11             DSI_VLCCR_HLINE11_Msk
10226 #define DSI_VLCCR_HLINE12_Pos         (12U)
10227 #define DSI_VLCCR_HLINE12_Msk         (0x1UL << DSI_VLCCR_HLINE12_Pos)         /*!< 0x00001000 */
10228 #define DSI_VLCCR_HLINE12             DSI_VLCCR_HLINE12_Msk
10229 #define DSI_VLCCR_HLINE13_Pos         (13U)
10230 #define DSI_VLCCR_HLINE13_Msk         (0x1UL << DSI_VLCCR_HLINE13_Pos)         /*!< 0x00002000 */
10231 #define DSI_VLCCR_HLINE13             DSI_VLCCR_HLINE13_Msk
10232 #define DSI_VLCCR_HLINE14_Pos         (14U)
10233 #define DSI_VLCCR_HLINE14_Msk         (0x1UL << DSI_VLCCR_HLINE14_Pos)         /*!< 0x00004000 */
10234 #define DSI_VLCCR_HLINE14             DSI_VLCCR_HLINE14_Msk
10235 
10236 /*******************  Bit definition for DSI_VVSACCR register  ***************/
10237 #define DSI_VVSACCR_VSA_Pos           (0U)
10238 #define DSI_VVSACCR_VSA_Msk           (0x3FFUL << DSI_VVSACCR_VSA_Pos)         /*!< 0x000003FF */
10239 #define DSI_VVSACCR_VSA               DSI_VVSACCR_VSA_Msk                      /*!< Vertical Synchronism Active duration */
10240 #define DSI_VVSACCR_VSA0_Pos          (0U)
10241 #define DSI_VVSACCR_VSA0_Msk          (0x1UL << DSI_VVSACCR_VSA0_Pos)          /*!< 0x00000001 */
10242 #define DSI_VVSACCR_VSA0              DSI_VVSACCR_VSA0_Msk
10243 #define DSI_VVSACCR_VSA1_Pos          (1U)
10244 #define DSI_VVSACCR_VSA1_Msk          (0x1UL << DSI_VVSACCR_VSA1_Pos)          /*!< 0x00000002 */
10245 #define DSI_VVSACCR_VSA1              DSI_VVSACCR_VSA1_Msk
10246 #define DSI_VVSACCR_VSA2_Pos          (2U)
10247 #define DSI_VVSACCR_VSA2_Msk          (0x1UL << DSI_VVSACCR_VSA2_Pos)          /*!< 0x00000004 */
10248 #define DSI_VVSACCR_VSA2              DSI_VVSACCR_VSA2_Msk
10249 #define DSI_VVSACCR_VSA3_Pos          (3U)
10250 #define DSI_VVSACCR_VSA3_Msk          (0x1UL << DSI_VVSACCR_VSA3_Pos)          /*!< 0x00000008 */
10251 #define DSI_VVSACCR_VSA3              DSI_VVSACCR_VSA3_Msk
10252 #define DSI_VVSACCR_VSA4_Pos          (4U)
10253 #define DSI_VVSACCR_VSA4_Msk          (0x1UL << DSI_VVSACCR_VSA4_Pos)          /*!< 0x00000010 */
10254 #define DSI_VVSACCR_VSA4              DSI_VVSACCR_VSA4_Msk
10255 #define DSI_VVSACCR_VSA5_Pos          (5U)
10256 #define DSI_VVSACCR_VSA5_Msk          (0x1UL << DSI_VVSACCR_VSA5_Pos)          /*!< 0x00000020 */
10257 #define DSI_VVSACCR_VSA5              DSI_VVSACCR_VSA5_Msk
10258 #define DSI_VVSACCR_VSA6_Pos          (6U)
10259 #define DSI_VVSACCR_VSA6_Msk          (0x1UL << DSI_VVSACCR_VSA6_Pos)          /*!< 0x00000040 */
10260 #define DSI_VVSACCR_VSA6              DSI_VVSACCR_VSA6_Msk
10261 #define DSI_VVSACCR_VSA7_Pos          (7U)
10262 #define DSI_VVSACCR_VSA7_Msk          (0x1UL << DSI_VVSACCR_VSA7_Pos)          /*!< 0x00000080 */
10263 #define DSI_VVSACCR_VSA7              DSI_VVSACCR_VSA7_Msk
10264 #define DSI_VVSACCR_VSA8_Pos          (8U)
10265 #define DSI_VVSACCR_VSA8_Msk          (0x1UL << DSI_VVSACCR_VSA8_Pos)          /*!< 0x00000100 */
10266 #define DSI_VVSACCR_VSA8              DSI_VVSACCR_VSA8_Msk
10267 #define DSI_VVSACCR_VSA9_Pos          (9U)
10268 #define DSI_VVSACCR_VSA9_Msk          (0x1UL << DSI_VVSACCR_VSA9_Pos)          /*!< 0x00000200 */
10269 #define DSI_VVSACCR_VSA9              DSI_VVSACCR_VSA9_Msk
10270 
10271 /*******************  Bit definition for DSI_VVBPCCR register  ************/
10272 #define DSI_VVBPCCR_VBP_Pos           (0U)
10273 #define DSI_VVBPCCR_VBP_Msk           (0x3FFUL << DSI_VVBPCCR_VBP_Pos)         /*!< 0x000003FF */
10274 #define DSI_VVBPCCR_VBP               DSI_VVBPCCR_VBP_Msk                      /*!< Vertical Back-Porch duration */
10275 #define DSI_VVBPCCR_VBP0_Pos          (0U)
10276 #define DSI_VVBPCCR_VBP0_Msk          (0x1UL << DSI_VVBPCCR_VBP0_Pos)          /*!< 0x00000001 */
10277 #define DSI_VVBPCCR_VBP0              DSI_VVBPCCR_VBP0_Msk
10278 #define DSI_VVBPCCR_VBP1_Pos          (1U)
10279 #define DSI_VVBPCCR_VBP1_Msk          (0x1UL << DSI_VVBPCCR_VBP1_Pos)          /*!< 0x00000002 */
10280 #define DSI_VVBPCCR_VBP1              DSI_VVBPCCR_VBP1_Msk
10281 #define DSI_VVBPCCR_VBP2_Pos          (2U)
10282 #define DSI_VVBPCCR_VBP2_Msk          (0x1UL << DSI_VVBPCCR_VBP2_Pos)          /*!< 0x00000004 */
10283 #define DSI_VVBPCCR_VBP2              DSI_VVBPCCR_VBP2_Msk
10284 #define DSI_VVBPCCR_VBP3_Pos          (3U)
10285 #define DSI_VVBPCCR_VBP3_Msk          (0x1UL << DSI_VVBPCCR_VBP3_Pos)          /*!< 0x00000008 */
10286 #define DSI_VVBPCCR_VBP3              DSI_VVBPCCR_VBP3_Msk
10287 #define DSI_VVBPCCR_VBP4_Pos          (4U)
10288 #define DSI_VVBPCCR_VBP4_Msk          (0x1UL << DSI_VVBPCCR_VBP4_Pos)          /*!< 0x00000010 */
10289 #define DSI_VVBPCCR_VBP4              DSI_VVBPCCR_VBP4_Msk
10290 #define DSI_VVBPCCR_VBP5_Pos          (5U)
10291 #define DSI_VVBPCCR_VBP5_Msk          (0x1UL << DSI_VVBPCCR_VBP5_Pos)          /*!< 0x00000020 */
10292 #define DSI_VVBPCCR_VBP5              DSI_VVBPCCR_VBP5_Msk
10293 #define DSI_VVBPCCR_VBP6_Pos          (6U)
10294 #define DSI_VVBPCCR_VBP6_Msk          (0x1UL << DSI_VVBPCCR_VBP6_Pos)          /*!< 0x00000040 */
10295 #define DSI_VVBPCCR_VBP6              DSI_VVBPCCR_VBP6_Msk
10296 #define DSI_VVBPCCR_VBP7_Pos          (7U)
10297 #define DSI_VVBPCCR_VBP7_Msk          (0x1UL << DSI_VVBPCCR_VBP7_Pos)          /*!< 0x00000080 */
10298 #define DSI_VVBPCCR_VBP7              DSI_VVBPCCR_VBP7_Msk
10299 #define DSI_VVBPCCR_VBP8_Pos          (8U)
10300 #define DSI_VVBPCCR_VBP8_Msk          (0x1UL << DSI_VVBPCCR_VBP8_Pos)          /*!< 0x00000100 */
10301 #define DSI_VVBPCCR_VBP8              DSI_VVBPCCR_VBP8_Msk
10302 #define DSI_VVBPCCR_VBP9_Pos          (9U)
10303 #define DSI_VVBPCCR_VBP9_Msk          (0x1UL << DSI_VVBPCCR_VBP9_Pos)          /*!< 0x00000200 */
10304 #define DSI_VVBPCCR_VBP9              DSI_VVBPCCR_VBP9_Msk
10305 
10306 /*******************  Bit definition for DSI_VVFPCCR register  ************/
10307 #define DSI_VVFPCCR_VFP_Pos           (0U)
10308 #define DSI_VVFPCCR_VFP_Msk           (0x3FFUL << DSI_VVFPCCR_VFP_Pos)         /*!< 0x000003FF */
10309 #define DSI_VVFPCCR_VFP               DSI_VVFPCCR_VFP_Msk                      /*!< Vertical Front-Porch duration */
10310 #define DSI_VVFPCCR_VFP0_Pos          (0U)
10311 #define DSI_VVFPCCR_VFP0_Msk          (0x1UL << DSI_VVFPCCR_VFP0_Pos)          /*!< 0x00000001 */
10312 #define DSI_VVFPCCR_VFP0              DSI_VVFPCCR_VFP0_Msk
10313 #define DSI_VVFPCCR_VFP1_Pos          (1U)
10314 #define DSI_VVFPCCR_VFP1_Msk          (0x1UL << DSI_VVFPCCR_VFP1_Pos)          /*!< 0x00000002 */
10315 #define DSI_VVFPCCR_VFP1              DSI_VVFPCCR_VFP1_Msk
10316 #define DSI_VVFPCCR_VFP2_Pos          (2U)
10317 #define DSI_VVFPCCR_VFP2_Msk          (0x1UL << DSI_VVFPCCR_VFP2_Pos)          /*!< 0x00000004 */
10318 #define DSI_VVFPCCR_VFP2              DSI_VVFPCCR_VFP2_Msk
10319 #define DSI_VVFPCCR_VFP3_Pos          (3U)
10320 #define DSI_VVFPCCR_VFP3_Msk          (0x1UL << DSI_VVFPCCR_VFP3_Pos)          /*!< 0x00000008 */
10321 #define DSI_VVFPCCR_VFP3              DSI_VVFPCCR_VFP3_Msk
10322 #define DSI_VVFPCCR_VFP4_Pos          (4U)
10323 #define DSI_VVFPCCR_VFP4_Msk          (0x1UL << DSI_VVFPCCR_VFP4_Pos)          /*!< 0x00000010 */
10324 #define DSI_VVFPCCR_VFP4              DSI_VVFPCCR_VFP4_Msk
10325 #define DSI_VVFPCCR_VFP5_Pos          (5U)
10326 #define DSI_VVFPCCR_VFP5_Msk          (0x1UL << DSI_VVFPCCR_VFP5_Pos)          /*!< 0x00000020 */
10327 #define DSI_VVFPCCR_VFP5              DSI_VVFPCCR_VFP5_Msk
10328 #define DSI_VVFPCCR_VFP6_Pos          (6U)
10329 #define DSI_VVFPCCR_VFP6_Msk          (0x1UL << DSI_VVFPCCR_VFP6_Pos)          /*!< 0x00000040 */
10330 #define DSI_VVFPCCR_VFP6              DSI_VVFPCCR_VFP6_Msk
10331 #define DSI_VVFPCCR_VFP7_Pos          (7U)
10332 #define DSI_VVFPCCR_VFP7_Msk          (0x1UL << DSI_VVFPCCR_VFP7_Pos)          /*!< 0x00000080 */
10333 #define DSI_VVFPCCR_VFP7              DSI_VVFPCCR_VFP7_Msk
10334 #define DSI_VVFPCCR_VFP8_Pos          (8U)
10335 #define DSI_VVFPCCR_VFP8_Msk          (0x1UL << DSI_VVFPCCR_VFP8_Pos)          /*!< 0x00000100 */
10336 #define DSI_VVFPCCR_VFP8              DSI_VVFPCCR_VFP8_Msk
10337 #define DSI_VVFPCCR_VFP9_Pos          (9U)
10338 #define DSI_VVFPCCR_VFP9_Msk          (0x1UL << DSI_VVFPCCR_VFP9_Pos)          /*!< 0x00000200 */
10339 #define DSI_VVFPCCR_VFP9              DSI_VVFPCCR_VFP9_Msk
10340 
10341 /*******************  Bit definition for DSI_VVACCR register  *************/
10342 #define DSI_VVACCR_VA_Pos             (0U)
10343 #define DSI_VVACCR_VA_Msk             (0x3FFFUL << DSI_VVACCR_VA_Pos)          /*!< 0x00003FFF */
10344 #define DSI_VVACCR_VA                 DSI_VVACCR_VA_Msk                        /*!< Vertical Active duration */
10345 #define DSI_VVACCR_VA0_Pos            (0U)
10346 #define DSI_VVACCR_VA0_Msk            (0x1UL << DSI_VVACCR_VA0_Pos)            /*!< 0x00000001 */
10347 #define DSI_VVACCR_VA0                DSI_VVACCR_VA0_Msk
10348 #define DSI_VVACCR_VA1_Pos            (1U)
10349 #define DSI_VVACCR_VA1_Msk            (0x1UL << DSI_VVACCR_VA1_Pos)            /*!< 0x00000002 */
10350 #define DSI_VVACCR_VA1                DSI_VVACCR_VA1_Msk
10351 #define DSI_VVACCR_VA2_Pos            (2U)
10352 #define DSI_VVACCR_VA2_Msk            (0x1UL << DSI_VVACCR_VA2_Pos)            /*!< 0x00000004 */
10353 #define DSI_VVACCR_VA2                DSI_VVACCR_VA2_Msk
10354 #define DSI_VVACCR_VA3_Pos            (3U)
10355 #define DSI_VVACCR_VA3_Msk            (0x1UL << DSI_VVACCR_VA3_Pos)            /*!< 0x00000008 */
10356 #define DSI_VVACCR_VA3                DSI_VVACCR_VA3_Msk
10357 #define DSI_VVACCR_VA4_Pos            (4U)
10358 #define DSI_VVACCR_VA4_Msk            (0x1UL << DSI_VVACCR_VA4_Pos)            /*!< 0x00000010 */
10359 #define DSI_VVACCR_VA4                DSI_VVACCR_VA4_Msk
10360 #define DSI_VVACCR_VA5_Pos            (5U)
10361 #define DSI_VVACCR_VA5_Msk            (0x1UL << DSI_VVACCR_VA5_Pos)            /*!< 0x00000020 */
10362 #define DSI_VVACCR_VA5                DSI_VVACCR_VA5_Msk
10363 #define DSI_VVACCR_VA6_Pos            (6U)
10364 #define DSI_VVACCR_VA6_Msk            (0x1UL << DSI_VVACCR_VA6_Pos)            /*!< 0x00000040 */
10365 #define DSI_VVACCR_VA6                DSI_VVACCR_VA6_Msk
10366 #define DSI_VVACCR_VA7_Pos            (7U)
10367 #define DSI_VVACCR_VA7_Msk            (0x1UL << DSI_VVACCR_VA7_Pos)            /*!< 0x00000080 */
10368 #define DSI_VVACCR_VA7                DSI_VVACCR_VA7_Msk
10369 #define DSI_VVACCR_VA8_Pos            (8U)
10370 #define DSI_VVACCR_VA8_Msk            (0x1UL << DSI_VVACCR_VA8_Pos)            /*!< 0x00000100 */
10371 #define DSI_VVACCR_VA8                DSI_VVACCR_VA8_Msk
10372 #define DSI_VVACCR_VA9_Pos            (9U)
10373 #define DSI_VVACCR_VA9_Msk            (0x1UL << DSI_VVACCR_VA9_Pos)            /*!< 0x00000200 */
10374 #define DSI_VVACCR_VA9                DSI_VVACCR_VA9_Msk
10375 #define DSI_VVACCR_VA10_Pos           (10U)
10376 #define DSI_VVACCR_VA10_Msk           (0x1UL << DSI_VVACCR_VA10_Pos)           /*!< 0x00000400 */
10377 #define DSI_VVACCR_VA10               DSI_VVACCR_VA10_Msk
10378 #define DSI_VVACCR_VA11_Pos           (11U)
10379 #define DSI_VVACCR_VA11_Msk           (0x1UL << DSI_VVACCR_VA11_Pos)           /*!< 0x00000800 */
10380 #define DSI_VVACCR_VA11               DSI_VVACCR_VA11_Msk
10381 #define DSI_VVACCR_VA12_Pos           (12U)
10382 #define DSI_VVACCR_VA12_Msk           (0x1UL << DSI_VVACCR_VA12_Pos)           /*!< 0x00001000 */
10383 #define DSI_VVACCR_VA12               DSI_VVACCR_VA12_Msk
10384 #define DSI_VVACCR_VA13_Pos           (13U)
10385 #define DSI_VVACCR_VA13_Msk           (0x1UL << DSI_VVACCR_VA13_Pos)           /*!< 0x00002000 */
10386 #define DSI_VVACCR_VA13               DSI_VVACCR_VA13_Msk
10387 
10388 /*******************  Bit definition for DSI_FBSR register  ****************/
10389 #define DSI_FBSR_VCWFE_Pos            (0U)
10390 #define DSI_FBSR_VCWFE_Msk            (0x1UL << DSI_FBSR_VCWFE_Pos)            /*!< 0x00000001 */
10391 #define DSI_FBSR_VCWFE                DSI_FBSR_VCWFE_Msk                       /*!< Video mode Command Write FIFO Empty */
10392 #define DSI_FBSR_VCWFF_Pos            (1U)
10393 #define DSI_FBSR_VCWFF_Msk            (0x1UL << DSI_FBSR_VCWFF_Pos)            /*!< 0x00000002 */
10394 #define DSI_FBSR_VCWFF                DSI_FBSR_VCWFF_Msk                       /*!< Video mode Command Write FIFO Full */
10395 #define DSI_FBSR_VPWFE_Pos            (2U)
10396 #define DSI_FBSR_VPWFE_Msk            (0x1UL << DSI_FBSR_VPWFE_Pos)            /*!< 0x00000004 */
10397 #define DSI_FBSR_VPWFE                DSI_FBSR_VPWFE_Msk                       /*!< Video mode Payload Write FIFO Empty */
10398 #define DSI_FBSR_VPWFF_Pos            (3U)
10399 #define DSI_FBSR_VPWFF_Msk            (0x1UL << DSI_FBSR_VPWFF_Pos)            /*!< 0x00000008 */
10400 #define DSI_FBSR_VPWFF                DSI_FBSR_VPWFF_Msk                       /*!< Video mode Payload Write FIFO Full */
10401 #define DSI_FBSR_ACWFE_Pos            (4U)
10402 #define DSI_FBSR_ACWFE_Msk            (0x1UL << DSI_FBSR_ACWFE_Pos)            /*!< 0x00000010 */
10403 #define DSI_FBSR_ACWFE                DSI_FBSR_ACWFE_Msk                       /*!< Adapted mode Command Write FIFO Empty */
10404 #define DSI_FBSR_ACWFF_Pos            (5U)
10405 #define DSI_FBSR_ACWFF_Msk            (0x1UL << DSI_FBSR_ACWFF_Pos)            /*!< 0x00000020 */
10406 #define DSI_FBSR_ACWFF                DSI_FBSR_ACWFF_Msk                       /*!< Adapted mode Command Write FIFO Full */
10407 #define DSI_FBSR_APWFE_Pos            (6U)
10408 #define DSI_FBSR_APWFE_Msk            (0x1UL << DSI_FBSR_APWFE_Pos)            /*!< 0x00000040 */
10409 #define DSI_FBSR_APWFE                DSI_FBSR_APWFE_Msk                       /*!< Adapted mode Payload Write FIFO Empty */
10410 #define DSI_FBSR_APWFF_Pos            (7U)
10411 #define DSI_FBSR_APWFF_Msk            (0x1UL << DSI_FBSR_APWFF_Pos)            /*!< 0x00000080 */
10412 #define DSI_FBSR_APWFF                DSI_FBSR_APWFF_Msk                       /*!< Adapted mode Payload Write FIFO Full */
10413 #define DSI_FBSR_VPBE_Pos             (16U)
10414 #define DSI_FBSR_VPBE_Msk             (0x1UL << DSI_FBSR_VPBE_Pos)             /*!< 0x00010000 */
10415 #define DSI_FBSR_VPBE                 DSI_FBSR_VPBE_Msk                        /*!< Video mode Payload Buffer Empty */
10416 #define DSI_FBSR_VPBF_Pos             (17U)
10417 #define DSI_FBSR_VPBF_Msk             (0x1UL << DSI_FBSR_VPBF_Pos)             /*!< 0x00020000 */
10418 #define DSI_FBSR_VPBF                 DSI_FBSR_VPBF_Msk                        /*!< Video mode Payload Buffer Full */
10419 #define DSI_FBSR_ACBE_Pos             (20U)
10420 #define DSI_FBSR_ACBE_Msk             (0x1UL << DSI_FBSR_ACBE_Pos)             /*!< 0x00100000 */
10421 #define DSI_FBSR_ACBE                 DSI_FBSR_ACBE_Msk                        /*!< Adapted mode Command Buffer Empty */
10422 #define DSI_FBSR_ACBF_Pos             (21U)
10423 #define DSI_FBSR_ACBF_Msk             (0x1UL << DSI_FBSR_ACBF_Pos)             /*!< 0x00200000 */
10424 #define DSI_FBSR_ACBF                 DSI_FBSR_ACBF_Msk                        /*!< Adapted mode Command Buffer Full */
10425 #define DSI_FBSR_APBE_Pos             (22U)
10426 #define DSI_FBSR_APBE_Msk             (0x1UL << DSI_FBSR_APBE_Pos)             /*!< 0x00400000 */
10427 #define DSI_FBSR_APBE                 DSI_FBSR_APBE_Msk                        /*!< Adapted mode Payload Buffer Empty */
10428 #define DSI_FBSR_APBF_Pos             (23U)
10429 #define DSI_FBSR_APBF_Msk             (0x1UL << DSI_FBSR_APBF_Pos)             /*!< 0x00800000 */
10430 #define DSI_FBSR_APBF                 DSI_FBSR_APBF_Msk                        /*!< Adapted mode Payload Buffer Full */
10431 
10432 /*******************  Bit definition for DSI_WCFGR register  ***************/
10433 #define DSI_WCFGR_DSIM_Pos            (0U)
10434 #define DSI_WCFGR_DSIM_Msk            (0x1UL << DSI_WCFGR_DSIM_Pos)            /*!< 0x00000001 */
10435 #define DSI_WCFGR_DSIM                DSI_WCFGR_DSIM_Msk                       /*!< DSI Mode */
10436 #define DSI_WCFGR_COLMUX_Pos          (1U)
10437 #define DSI_WCFGR_COLMUX_Msk          (0x7UL << DSI_WCFGR_COLMUX_Pos)          /*!< 0x0000000E */
10438 #define DSI_WCFGR_COLMUX              DSI_WCFGR_COLMUX_Msk                     /*!< Color Multiplexing */
10439 #define DSI_WCFGR_COLMUX0_Pos         (1U)
10440 #define DSI_WCFGR_COLMUX0_Msk         (0x1UL << DSI_WCFGR_COLMUX0_Pos)         /*!< 0x00000002 */
10441 #define DSI_WCFGR_COLMUX0             DSI_WCFGR_COLMUX0_Msk
10442 #define DSI_WCFGR_COLMUX1_Pos         (2U)
10443 #define DSI_WCFGR_COLMUX1_Msk         (0x1UL << DSI_WCFGR_COLMUX1_Pos)         /*!< 0x00000004 */
10444 #define DSI_WCFGR_COLMUX1             DSI_WCFGR_COLMUX1_Msk
10445 #define DSI_WCFGR_COLMUX2_Pos         (3U)
10446 #define DSI_WCFGR_COLMUX2_Msk         (0x1UL << DSI_WCFGR_COLMUX2_Pos)         /*!< 0x00000008 */
10447 #define DSI_WCFGR_COLMUX2             DSI_WCFGR_COLMUX2_Msk
10448 
10449 #define DSI_WCFGR_TESRC_Pos           (4U)
10450 #define DSI_WCFGR_TESRC_Msk           (0x1UL << DSI_WCFGR_TESRC_Pos)           /*!< 0x00000010 */
10451 #define DSI_WCFGR_TESRC               DSI_WCFGR_TESRC_Msk                      /*!< Tearing Effect Source */
10452 #define DSI_WCFGR_TEPOL_Pos           (5U)
10453 #define DSI_WCFGR_TEPOL_Msk           (0x1UL << DSI_WCFGR_TEPOL_Pos)           /*!< 0x00000020 */
10454 #define DSI_WCFGR_TEPOL               DSI_WCFGR_TEPOL_Msk                      /*!< Tearing Effect Polarity */
10455 #define DSI_WCFGR_AR_Pos              (6U)
10456 #define DSI_WCFGR_AR_Msk              (0x1UL << DSI_WCFGR_AR_Pos)              /*!< 0x00000040 */
10457 #define DSI_WCFGR_AR                  DSI_WCFGR_AR_Msk                         /*!< Automatic Refresh */
10458 #define DSI_WCFGR_VSPOL_Pos           (7U)
10459 #define DSI_WCFGR_VSPOL_Msk           (0x1UL << DSI_WCFGR_VSPOL_Pos)           /*!< 0x00000080 */
10460 #define DSI_WCFGR_VSPOL               DSI_WCFGR_VSPOL_Msk                      /*!< VSync Polarity */
10461 
10462 /*******************  Bit definition for DSI_WCR register  *****************/
10463 #define DSI_WCR_COLM_Pos              (0U)
10464 #define DSI_WCR_COLM_Msk              (0x1UL << DSI_WCR_COLM_Pos)              /*!< 0x00000001 */
10465 #define DSI_WCR_COLM                  DSI_WCR_COLM_Msk                         /*!< Color Mode */
10466 #define DSI_WCR_SHTDN_Pos             (1U)
10467 #define DSI_WCR_SHTDN_Msk             (0x1UL << DSI_WCR_SHTDN_Pos)             /*!< 0x00000002 */
10468 #define DSI_WCR_SHTDN                 DSI_WCR_SHTDN_Msk                        /*!< Shutdown */
10469 #define DSI_WCR_LTDCEN_Pos            (2U)
10470 #define DSI_WCR_LTDCEN_Msk            (0x1UL << DSI_WCR_LTDCEN_Pos)            /*!< 0x00000004 */
10471 #define DSI_WCR_LTDCEN                DSI_WCR_LTDCEN_Msk                       /*!< LTDC Enable */
10472 #define DSI_WCR_DSIEN_Pos             (3U)
10473 #define DSI_WCR_DSIEN_Msk             (0x1UL << DSI_WCR_DSIEN_Pos)             /*!< 0x00000008 */
10474 #define DSI_WCR_DSIEN                 DSI_WCR_DSIEN_Msk                        /*!< DSI Enable */
10475 
10476 /*******************  Bit definition for DSI_WIER register  ****************/
10477 #define DSI_WIER_TEIE_Pos             (0U)
10478 #define DSI_WIER_TEIE_Msk             (0x1UL << DSI_WIER_TEIE_Pos)             /*!< 0x00000001 */
10479 #define DSI_WIER_TEIE                 DSI_WIER_TEIE_Msk                        /*!< Tearing Effect Interrupt Enable */
10480 #define DSI_WIER_ERIE_Pos             (1U)
10481 #define DSI_WIER_ERIE_Msk             (0x1UL << DSI_WIER_ERIE_Pos)             /*!< 0x00000002 */
10482 #define DSI_WIER_ERIE                 DSI_WIER_ERIE_Msk                        /*!< End of Refresh Interrupt Enable */
10483 #define DSI_WIER_PLLLIE_Pos           (9U)
10484 #define DSI_WIER_PLLLIE_Msk           (0x1UL << DSI_WIER_PLLLIE_Pos)           /*!< 0x00000200 */
10485 #define DSI_WIER_PLLLIE               DSI_WIER_PLLLIE_Msk                      /*!< PLL Lock Interrupt Enable */
10486 #define DSI_WIER_PLLUIE_Pos           (10U)
10487 #define DSI_WIER_PLLUIE_Msk           (0x1UL << DSI_WIER_PLLUIE_Pos)           /*!< 0x00000400 */
10488 #define DSI_WIER_PLLUIE               DSI_WIER_PLLUIE_Msk                      /*!< PLL Unlock Interrupt Enable */
10489 
10490 /*******************  Bit definition for DSI_WISR register  ****************/
10491 #define DSI_WISR_TEIF_Pos             (0U)
10492 #define DSI_WISR_TEIF_Msk             (0x1UL << DSI_WISR_TEIF_Pos)             /*!< 0x00000001 */
10493 #define DSI_WISR_TEIF                 DSI_WISR_TEIF_Msk                        /*!< Tearing Effect Interrupt Flag */
10494 #define DSI_WISR_ERIF_Pos             (1U)
10495 #define DSI_WISR_ERIF_Msk             (0x1UL << DSI_WISR_ERIF_Pos)             /*!< 0x00000002 */
10496 #define DSI_WISR_ERIF                 DSI_WISR_ERIF_Msk                        /*!< End of Refresh Interrupt Flag */
10497 #define DSI_WISR_BUSY_Pos             (2U)
10498 #define DSI_WISR_BUSY_Msk             (0x1UL << DSI_WISR_BUSY_Pos)             /*!< 0x00000004 */
10499 #define DSI_WISR_BUSY                 DSI_WISR_BUSY_Msk                        /*!< Busy Flag */
10500 #define DSI_WISR_PLLLS_Pos            (8U)
10501 #define DSI_WISR_PLLLS_Msk            (0x1UL << DSI_WISR_PLLLS_Pos)            /*!< 0x00000100 */
10502 #define DSI_WISR_PLLLS                DSI_WISR_PLLLS_Msk                       /*!< PLL Lock Status */
10503 #define DSI_WISR_PLLLIF_Pos           (9U)
10504 #define DSI_WISR_PLLLIF_Msk           (0x1UL << DSI_WISR_PLLLIF_Pos)           /*!< 0x00000200 */
10505 #define DSI_WISR_PLLLIF               DSI_WISR_PLLLIF_Msk                      /*!< PLL Lock Interrupt Flag */
10506 #define DSI_WISR_PLLUIF_Pos           (10U)
10507 #define DSI_WISR_PLLUIF_Msk           (0x1UL << DSI_WISR_PLLUIF_Pos)           /*!< 0x00000400 */
10508 #define DSI_WISR_PLLUIF               DSI_WISR_PLLUIF_Msk                      /*!< PLL Unlock Interrupt Flag */
10509 
10510 /*******************  Bit definition for DSI_WIFCR register  ***************/
10511 #define DSI_WIFCR_CTEIF_Pos           (0U)
10512 #define DSI_WIFCR_CTEIF_Msk           (0x1UL << DSI_WIFCR_CTEIF_Pos)           /*!< 0x00000001 */
10513 #define DSI_WIFCR_CTEIF               DSI_WIFCR_CTEIF_Msk                      /*!< Clear Tearing Effect Interrupt Flag */
10514 #define DSI_WIFCR_CERIF_Pos           (1U)
10515 #define DSI_WIFCR_CERIF_Msk           (0x1UL << DSI_WIFCR_CERIF_Pos)           /*!< 0x00000002 */
10516 #define DSI_WIFCR_CERIF               DSI_WIFCR_CERIF_Msk                      /*!< Clear End of Refresh Interrupt Flag */
10517 #define DSI_WIFCR_CPLLLIF_Pos         (9U)
10518 #define DSI_WIFCR_CPLLLIF_Msk         (0x1UL << DSI_WIFCR_CPLLLIF_Pos)         /*!< 0x00000200 */
10519 #define DSI_WIFCR_CPLLLIF             DSI_WIFCR_CPLLLIF_Msk                    /*!< Clear PLL Lock Interrupt Flag */
10520 #define DSI_WIFCR_CPLLUIF_Pos         (10U)
10521 #define DSI_WIFCR_CPLLUIF_Msk         (0x1UL << DSI_WIFCR_CPLLUIF_Pos)         /*!< 0x00000400 */
10522 #define DSI_WIFCR_CPLLUIF             DSI_WIFCR_CPLLUIF_Msk                    /*!< Clear PLL Unlock Interrupt Flag */
10523 
10524 /*******************  Bit definition for DSI_WPCR0 register  ***************/
10525 #define DSI_WPCR0_SWCL_Pos            (6U)
10526 #define DSI_WPCR0_SWCL_Msk            (0x1UL << DSI_WPCR0_SWCL_Pos)            /*!< 0x00000040 */
10527 #define DSI_WPCR0_SWCL                DSI_WPCR0_SWCL_Msk                       /*!< Swap pins on clock lane */
10528 #define DSI_WPCR0_SWDL0_Pos           (7U)
10529 #define DSI_WPCR0_SWDL0_Msk           (0x1UL << DSI_WPCR0_SWDL0_Pos)           /*!< 0x00000080 */
10530 #define DSI_WPCR0_SWDL0               DSI_WPCR0_SWDL0_Msk                      /*!< Swap pins on data lane 1 */
10531 #define DSI_WPCR0_SWDL1_Pos           (8U)
10532 #define DSI_WPCR0_SWDL1_Msk           (0x1UL << DSI_WPCR0_SWDL1_Pos)           /*!< 0x00000100 */
10533 #define DSI_WPCR0_SWDL1               DSI_WPCR0_SWDL1_Msk                      /*!< Swap pins on data lane 2 */
10534 #define DSI_WPCR0_FTXSMCL_Pos         (12U)
10535 #define DSI_WPCR0_FTXSMCL_Msk         (0x1UL << DSI_WPCR0_FTXSMCL_Pos)         /*!< 0x00001000 */
10536 #define DSI_WPCR0_FTXSMCL             DSI_WPCR0_FTXSMCL_Msk                    /*!< Force clock lane in TX stop mode */
10537 #define DSI_WPCR0_FTXSMDL_Pos         (13U)
10538 #define DSI_WPCR0_FTXSMDL_Msk         (0x1UL << DSI_WPCR0_FTXSMDL_Pos)         /*!< 0x00002000 */
10539 #define DSI_WPCR0_FTXSMDL             DSI_WPCR0_FTXSMDL_Msk                    /*!< Force data lanes in TX stop mode */
10540 
10541 /*******************  Bit definition for DSI_WRPCR register  ***************/
10542 #define DSI_WRPCR_PLLEN_Pos           (0U)
10543 #define DSI_WRPCR_PLLEN_Msk           (0x1UL << DSI_WRPCR_PLLEN_Pos)           /*!< 0x00000001 */
10544 #define DSI_WRPCR_PLLEN               DSI_WRPCR_PLLEN_Msk                      /*!< PLL Enable */
10545 #define DSI_WRPCR_PLL_NDIV_Pos        (2U)
10546 #define DSI_WRPCR_PLL_NDIV_Msk        (0x1FFUL << DSI_WRPCR_PLL_NDIV_Pos)      /*!< 0x000007FC */
10547 #define DSI_WRPCR_PLL_NDIV            DSI_WRPCR_PLL_NDIV_Msk                   /*!< PLL Loop Division Factor */
10548 #define DSI_WRPCR_PLL_NDIV0_Pos       (2U)
10549 #define DSI_WRPCR_PLL_NDIV0_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos)       /*!< 0x00000004 */
10550 #define DSI_WRPCR_PLL_NDIV0           DSI_WRPCR_PLL_NDIV0_Msk
10551 #define DSI_WRPCR_PLL_NDIV1_Pos       (3U)
10552 #define DSI_WRPCR_PLL_NDIV1_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos)       /*!< 0x00000008 */
10553 #define DSI_WRPCR_PLL_NDIV1           DSI_WRPCR_PLL_NDIV1_Msk
10554 #define DSI_WRPCR_PLL_NDIV2_Pos       (4U)
10555 #define DSI_WRPCR_PLL_NDIV2_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos)       /*!< 0x00000010 */
10556 #define DSI_WRPCR_PLL_NDIV2           DSI_WRPCR_PLL_NDIV2_Msk
10557 #define DSI_WRPCR_PLL_NDIV3_Pos       (5U)
10558 #define DSI_WRPCR_PLL_NDIV3_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos)       /*!< 0x00000020 */
10559 #define DSI_WRPCR_PLL_NDIV3           DSI_WRPCR_PLL_NDIV3_Msk
10560 #define DSI_WRPCR_PLL_NDIV4_Pos       (6U)
10561 #define DSI_WRPCR_PLL_NDIV4_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos)       /*!< 0x00000040 */
10562 #define DSI_WRPCR_PLL_NDIV4           DSI_WRPCR_PLL_NDIV4_Msk
10563 #define DSI_WRPCR_PLL_NDIV5_Pos       (7U)
10564 #define DSI_WRPCR_PLL_NDIV5_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos)       /*!< 0x00000080 */
10565 #define DSI_WRPCR_PLL_NDIV5           DSI_WRPCR_PLL_NDIV5_Msk
10566 #define DSI_WRPCR_PLL_NDIV6_Pos       (8U)
10567 #define DSI_WRPCR_PLL_NDIV6_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos)       /*!< 0x00000100 */
10568 #define DSI_WRPCR_PLL_NDIV6           DSI_WRPCR_PLL_NDIV6_Msk
10569 #define DSI_WRPCR_PLL_NDIV7_Pos       (9U)
10570 #define DSI_WRPCR_PLL_NDIV7_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV7_Pos)       /*!< 0x00000200 */
10571 #define DSI_WRPCR_PLL_NDIV7           DSI_WRPCR_PLL_NDIV7_Msk
10572 #define DSI_WRPCR_PLL_NDIV8_Pos       (10U)
10573 #define DSI_WRPCR_PLL_NDIV8_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV8_Pos)       /*!< 0x00000400 */
10574 #define DSI_WRPCR_PLL_NDIV8           DSI_WRPCR_PLL_NDIV8_Msk
10575 
10576 #define DSI_WRPCR_PLL_IDF_Pos         (11U)
10577 #define DSI_WRPCR_PLL_IDF_Msk         (0x1FFUL << DSI_WRPCR_PLL_IDF_Pos)       /*!< 0x000FF800 */
10578 #define DSI_WRPCR_PLL_IDF             DSI_WRPCR_PLL_IDF_Msk                    /*!< PLL Input Division Factor */
10579 #define DSI_WRPCR_PLL_IDF0_Pos        (11U)
10580 #define DSI_WRPCR_PLL_IDF0_Msk        (0x1UL << DSI_WRPCR_PLL_IDF0_Pos)        /*!< 0x00000800 */
10581 #define DSI_WRPCR_PLL_IDF0            DSI_WRPCR_PLL_IDF0_Msk
10582 #define DSI_WRPCR_PLL_IDF1_Pos        (12U)
10583 #define DSI_WRPCR_PLL_IDF1_Msk        (0x1UL << DSI_WRPCR_PLL_IDF1_Pos)        /*!< 0x00001000 */
10584 #define DSI_WRPCR_PLL_IDF1            DSI_WRPCR_PLL_IDF1_Msk
10585 #define DSI_WRPCR_PLL_IDF2_Pos        (13U)
10586 #define DSI_WRPCR_PLL_IDF2_Msk        (0x1UL << DSI_WRPCR_PLL_IDF2_Pos)        /*!< 0x00002000 */
10587 #define DSI_WRPCR_PLL_IDF2            DSI_WRPCR_PLL_IDF2_Msk
10588 #define DSI_WRPCR_PLL_IDF3_Pos        (14U)
10589 #define DSI_WRPCR_PLL_IDF3_Msk        (0x1UL << DSI_WRPCR_PLL_IDF3_Pos)        /*!< 0x00004000 */
10590 #define DSI_WRPCR_PLL_IDF3            DSI_WRPCR_PLL_IDF3_Msk
10591 #define DSI_WRPCR_PLL_IDF4_Pos        (15U)
10592 #define DSI_WRPCR_PLL_IDF4_Msk        (0x1UL << DSI_WRPCR_PLL_IDF4_Pos)        /*!< 0x00008000 */
10593 #define DSI_WRPCR_PLL_IDF4            DSI_WRPCR_PLL_IDF4_Msk
10594 #define DSI_WRPCR_PLL_IDF5_Pos        (16U)
10595 #define DSI_WRPCR_PLL_IDF5_Msk        (0x1UL << DSI_WRPCR_PLL_IDF5_Pos)        /*!< 0x00010000 */
10596 #define DSI_WRPCR_PLL_IDF5            DSI_WRPCR_PLL_IDF5_Msk
10597 #define DSI_WRPCR_PLL_IDF6_Pos        (17U)
10598 #define DSI_WRPCR_PLL_IDF6_Msk        (0x1UL << DSI_WRPCR_PLL_IDF6_Pos)        /*!< 0x00020000 */
10599 #define DSI_WRPCR_PLL_IDF6            DSI_WRPCR_PLL_IDF6_Msk
10600 #define DSI_WRPCR_PLL_IDF7_Pos        (18U)
10601 #define DSI_WRPCR_PLL_IDF7_Msk        (0x1UL << DSI_WRPCR_PLL_IDF7_Pos)        /*!< 0x00040000 */
10602 #define DSI_WRPCR_PLL_IDF7            DSI_WRPCR_PLL_IDF7_Msk
10603 #define DSI_WRPCR_PLL_IDF8_Pos        (19U)
10604 #define DSI_WRPCR_PLL_IDF8_Msk        (0x1UL << DSI_WRPCR_PLL_IDF8_Pos)        /*!< 0x00080000 */
10605 #define DSI_WRPCR_PLL_IDF8            DSI_WRPCR_PLL_IDF8_Msk
10606 
10607 #define DSI_WRPCR_PLL_ODF_Pos         (20U)
10608 #define DSI_WRPCR_PLL_ODF_Msk         (0x1FFUL << DSI_WRPCR_PLL_ODF_Pos)       /*!< 0x1FF00000 */
10609 #define DSI_WRPCR_PLL_ODF             DSI_WRPCR_PLL_ODF_Msk                    /*!< PLL Output Division Factor */
10610 #define DSI_WRPCR_PLL_ODF0_Pos        (20U)
10611 #define DSI_WRPCR_PLL_ODF0_Msk        (0x1UL << DSI_WRPCR_PLL_ODF0_Pos)        /*!< 0x00100000 */
10612 #define DSI_WRPCR_PLL_ODF0            DSI_WRPCR_PLL_ODF0_Msk
10613 #define DSI_WRPCR_PLL_ODF1_Pos        (21U)
10614 #define DSI_WRPCR_PLL_ODF1_Msk        (0x1UL << DSI_WRPCR_PLL_ODF1_Pos)        /*!< 0x00200000 */
10615 #define DSI_WRPCR_PLL_ODF1            DSI_WRPCR_PLL_ODF1_Msk
10616 #define DSI_WRPCR_PLL_ODF2_Pos        (22U)
10617 #define DSI_WRPCR_PLL_ODF2_Msk        (0x1UL << DSI_WRPCR_PLL_ODF2_Pos)        /*!< 0x00400000 */
10618 #define DSI_WRPCR_PLL_ODF2            DSI_WRPCR_PLL_ODF2_Msk
10619 #define DSI_WRPCR_PLL_ODF3_Pos        (23U)
10620 #define DSI_WRPCR_PLL_ODF3_Msk        (0x1UL << DSI_WRPCR_PLL_ODF3_Pos)        /*!< 0x00800000 */
10621 #define DSI_WRPCR_PLL_ODF3            DSI_WRPCR_PLL_ODF3_Msk
10622 #define DSI_WRPCR_PLL_ODF4_Pos        (24U)
10623 #define DSI_WRPCR_PLL_ODF4_Msk        (0x1UL << DSI_WRPCR_PLL_ODF4_Pos)        /*!< 0x01000000 */
10624 #define DSI_WRPCR_PLL_ODF4            DSI_WRPCR_PLL_ODF4_Msk
10625 #define DSI_WRPCR_PLL_ODF5_Pos        (25U)
10626 #define DSI_WRPCR_PLL_ODF5_Msk        (0x1UL << DSI_WRPCR_PLL_ODF5_Pos)        /*!< 0x02000000 */
10627 #define DSI_WRPCR_PLL_ODF5            DSI_WRPCR_PLL_ODF5_Msk
10628 #define DSI_WRPCR_PLL_ODF6_Pos        (26U)
10629 #define DSI_WRPCR_PLL_ODF6_Msk        (0x1UL << DSI_WRPCR_PLL_ODF6_Pos)        /*!< 0x04000000 */
10630 #define DSI_WRPCR_PLL_ODF6            DSI_WRPCR_PLL_ODF6_Msk
10631 #define DSI_WRPCR_PLL_ODF7_Pos        (27U)
10632 #define DSI_WRPCR_PLL_ODF7_Msk        (0x1UL << DSI_WRPCR_PLL_ODF7_Pos)        /*!< 0x08000000 */
10633 #define DSI_WRPCR_PLL_ODF7            DSI_WRPCR_PLL_ODF7_Msk
10634 #define DSI_WRPCR_PLL_ODF8_Pos        (28U)
10635 #define DSI_WRPCR_PLL_ODF8_Msk        (0x1UL << DSI_WRPCR_PLL_ODF8_Pos)        /*!< 0x10000000 */
10636 #define DSI_WRPCR_PLL_ODF8            DSI_WRPCR_PLL_ODF8_Msk
10637 #define DSI_WRPCR_BC_Pos              (29U)
10638 #define DSI_WRPCR_BC_Msk              (0x1UL << DSI_WRPCR_BC_Pos)              /*!< 0x10000000 */
10639 #define DSI_WRPCR_BC                  DSI_WRPCR_BC_Msk
10640 /*******************  Bit definition for DSI_WPTR register  ***************/
10641 #define DSI_WPTR_CP_Pos              (8U)
10642 #define DSI_WPTR_CP_Msk              (0xFUL << DSI_WPTR_CP_Pos)                /*!< 0x00000F00 */
10643 #define DSI_WPTR_CP                  DSI_WPTR_CP_Msk                           /*!< Wrapper PLL tuning charge pump */
10644 #define DSI_WPTR_CP0_Pos             (8U)
10645 #define DSI_WPTR_CP0_Msk             (0x1UL << DSI_WPTR_CP0_Pos)               /*!< 0x00000100 */
10646 #define DSI_WPTR_CP0                  DSI_WPTR_CP0_Msk
10647 #define DSI_WPTR_CP1_Pos             (9U)
10648 #define DSI_WPTR_CP1_Msk             (0x1UL << DSI_WPTR_CP1_Pos)               /*!< 0x00000200 */
10649 #define DSI_WPTR_CP1                  DSI_WPTR_CP1_Msk
10650 #define DSI_WPTR_CP2_Pos             (10U)
10651 #define DSI_WPTR_CP2_Msk             (0x1UL << DSI_WPTR_CP2_Pos)               /*!< 0x00000400 */
10652 #define DSI_WPTR_CP2                  DSI_WPTR_CP2_Msk
10653 #define DSI_WPTR_CP3_Pos             (11U)
10654 #define DSI_WPTR_CP3_Msk             (0x1UL << DSI_WPTR_CP3_Pos)               /*!< 0x00000800 */
10655 #define DSI_WPTR_CP3                  DSI_WPTR_CP3_Msk
10656 #define DSI_WPTR_LPF_Pos             (12U)
10657 #define DSI_WPTR_LPF_Msk             (0xFUL << DSI_WPTR_LPF_Pos)               /*!< 0x0000F000 */
10658 #define DSI_WPTR_LPF                  DSI_WPTR_LPF_Msk                         /*!< Wrapper PLL tuning loop filter */
10659 #define DSI_WPTR_LPF0_Pos            (12U)
10660 #define DSI_WPTR_LPF0_Msk            (0x1UL << DSI_WPTR_LPF0_Pos)              /*!< 0x00001000 */
10661 #define DSI_WPTR_LPF0                DSI_WPTR_LPF0_Msk
10662 #define DSI_WPTR_LPF1_Pos            (13U)
10663 #define DSI_WPTR_LPF1_Msk            (0x1UL << DSI_WPTR_LPF1_Pos)              /*!< 0x00002000 */
10664 #define DSI_WPTR_LPF1                 DSI_WPTR_LPF1_Msk
10665 #define DSI_WPTR_LPF2_Pos            (14U)
10666 #define DSI_WPTR_LPF2_Msk            (0x1UL << DSI_WPTR_LPF2_Pos)              /*!< 0x00004000 */
10667 #define DSI_WPTR_LPF2                 DSI_WPTR_LPF2_Msk
10668 #define DSI_WPTR_LPF3_Pos            (15U)
10669 #define DSI_WPTR_LPF3_Msk            (0x1UL << DSI_WPTR_LPF3_Pos)              /*!< 0x00008000 */
10670 #define DSI_WPTR_LPF3                 DSI_WPTR_LPF3_Msk
10671 
10672 /*******************  Bit definition for DSI_BCFGR register  ***************/
10673 #define DSI_BCFGR_PWRUP_Pos           (6U)
10674 #define DSI_BCFGR_PWRUP_Msk           (0x1UL << DSI_BCFGR_PWRUP_Pos)           /*!< 0x00000040 */
10675 #define DSI_BCFGR_PWRUP               DSI_BCFGR_PWRUP_Msk                      /*!< Reference bias power up */
10676 
10677 /*******************  Bit definition for DSI_D-PHY registers  ***************/
10678 /*******************  Bit definition for DSI_DPCBCR register  ***************/
10679 #define DSI_DPCBCR_Pos                (3U)
10680 #define DSI_DPCBCR_Msk                (0x1FUL << DSI_DPCBCR_Pos)               /*!< 0x000000F8 */
10681 #define DSI_DPCBCR                    DSI_DPCBCR_Msk                           /*!< clock band control register */
10682 #define DSI_DPCBCR0_Pos               (3U)
10683 #define DSI_DPCBCR0_Msk               (0x1UL << DSI_DPCBCR0_Pos)               /*!< 0x00000008 */
10684 #define DSI_DPCBCR0                   DSI_DPCBCR0_Msk
10685 #define DSI_DPCBCR1_Pos               (4U)
10686 #define DSI_DPCBCR1_Msk               (0x1UL << DSI_DPCBCR1_Pos)               /*!< 0x00000010 */
10687 #define DSI_DPCBCR1                   DSI_DPCBCR1_Msk
10688 #define DSI_DPCBCR2_Pos               (5U)
10689 #define DSI_DPCBCR2_Msk               (0x1UL << DSI_DPCBCR2_Pos)               /*!< 0x00000020 */
10690 #define DSI_DPCBCR2                   DSI_DPCBCR2_Msk
10691 #define DSI_DPCBCR3_Pos               (6U)
10692 #define DSI_DPCBCR3_Msk               (0x1UL << DSI_DPCBCR3_Pos)               /*!< 0x00000040 */
10693 #define DSI_DPCBCR3                   DSI_DPCBCR3_Msk
10694 #define DSI_DPCBCR4_Pos               (7U)
10695 #define DSI_DPCBCR4_Msk               (0x1UL << DSI_DPCBCR4_Pos)               /*!< 0x00000080 */
10696 #define DSI_DPCBCR4                   DSI_DPCBCR4_Msk
10697 
10698 /*******************  Bit definition for DSI_DPCSRCR register  ***************/
10699 #define DSI_DPCSRCR_Pos                (0U)
10700 #define DSI_DPCSRCR_Msk                (0xFFUL << DSI_DPCSRCR_Pos)          /*!< 0x000000FF */
10701 #define DSI_DPCSRCR                    DSI_DPCSRCR_Msk                      /*!< clock slew rate control register*/
10702 #define DSI_DPCSRCR0_Pos               (0U)
10703 #define DSI_DPCSRCR0_Msk               (0x1UL << DSI_DPCSRCR0_Pos)         /*!< 0x00000001 */
10704 #define DSI_DPCSRCR0                   DSI_DPCSRCR0_Msk
10705 #define DSI_DPCSRCR1_Pos               (1U)
10706 #define DSI_DPCSRCR1_Msk               (0x1UL << DSI_DPCSRCR1_Pos)         /*!< 0x00000002 */
10707 #define DSI_DPCSRCR1                   DSI_DPCSRCR1_Msk
10708 #define DSI_DPCSRCR2_Pos               (2U)
10709 #define DSI_DPCSRCR2_Msk               (0x1UL << DSI_DPCSRCR2_Pos)         /*!< 0x00000004 */
10710 #define DSI_DPCSRCR2                   DSI_DPCSRCR2_Msk
10711 #define DSI_DPCSRCR3_Pos               (3U)
10712 #define DSI_DPCSRCR3_Msk               (0x1UL << DSI_DPCSRCR3_Pos)         /*!< 0x00000008 */
10713 #define DSI_DPCSRCR3                   DSI_DPCSRCR3_Msk
10714 #define DSI_DPCSRCR4_Pos               (4U)
10715 #define DSI_DPCSRCR4_Msk               (0x1UL << DSI_DPCSRCR4_Pos)         /*!< 0x00000010 */
10716 #define DSI_DPCSRCR4                   DSI_DPCSRCR4_Msk
10717 #define DSI_DPCSRCR5_Pos               (5U)
10718 #define DSI_DPCSRCR5_Msk               (0x1UL << DSI_DPCSRCR5_Pos)         /*!< 0x00000020 */
10719 #define DSI_DPCSRCR5                   DSI_DPCSRCR5_Msk
10720 #define DSI_DPCSRCR6_Pos               (6U)
10721 #define DSI_DPCSRCR6_Msk               (0x1UL << DSI_DPCSRCR6_Pos)         /*!< 0x00000040 */
10722 #define DSI_DPCSRCR6                   DSI_DPCSRCR6_Msk
10723 #define DSI_DPCSRCR7_Pos               (7U)
10724 #define DSI_DPCSRCR7_Msk               (0x1UL << DSI_DPCSRCR7_Pos)         /*!< 0x00000080 */
10725 #define DSI_DPCSRCR7                   DSI_DPCSRCR7_Msk
10726 
10727 /*******************  Bit definition for DSI_DPDL0HSOCR register  ***************/
10728 #define DSI_DPDL0HSOCR_Pos             (4U)
10729 #define DSI_DPDL0HSOCR_Msk             (0xFUL << DSI_DPDL0HSOCR_Pos)         /*!< 0x000000F0 */
10730 #define DSI_DPDL0HSOCR                 DSI_DPDL0HSOCR_Msk                    /*!< data lane0 HS Prepare offset */
10731 #define DSI_DPDL0HSOCR_HSPRPO0_Pos     (4U)
10732 #define DSI_DPDL0HSOCR_HSPRPO0_Msk     (0x1UL << DSI_DPDL0HSOCR_HSPRPO0_Pos) /*!< 0x00000010 */
10733 #define DSI_DPDL0HSOCR_HSPRPO0         DSI_DPDL0HSOCR_HSPRPO0_Msk
10734 #define DSI_DPDL0HSOCR_HSPRPO1_Pos     (5U)
10735 #define DSI_DPDL0HSOCR_HSPRPO1_Msk     (0x1UL << DSI_DPDL0HSOCR_HSPRPO1_Pos) /*!< 0x00000020 */
10736 #define DSI_DPDL0HSOCR_HSPRPO1         DSI_DPDL0HSOCR_HSPRPO1_Msk
10737 #define DSI_DPDL0HSOCR_HSPRPO2_Pos     (6U)
10738 #define DSI_DPDL0HSOCR_HSPRPO2_Msk     (0x1UL << DSI_DPDL0HSOCR_HSPRPO2_Pos) /*!< 0x00000040 */
10739 #define DSI_DPDL0HSOCR_HSPRPO2         DSI_DPDL0HSOCR_HSPRPO2_Msk
10740 #define DSI_DPDL0HSOCR_HSPRPO3_Pos     (7U)
10741 #define DSI_DPDL0HSOCR_HSPRPO3_Msk     (0x1UL << DSI_DPDL0HSOCR_HSPRPO3_Pos) /*!< 0x00000080 */
10742 #define DSI_DPDL0HSOCR_HSPRPO3         DSI_DPDL0HSOCR_HSPRPO3_Msk
10743 
10744 /*******************  Bit definition for DSI_DPDL0LPXOCR register  ***************/
10745 #define DSI_DPDL0LPXOCR_Pos            (0U)
10746 #define DSI_DPDL0LPXOCR_Msk            (0xFUL << DSI_DPDL0LPXOCR_Pos)         /*!< 0x0000000F */
10747 #define DSI_DPDL0LPXOCR                DSI_DPDL0LPXOCR_Msk                    /*!< data lane 0 LPX Offset */
10748 #define DSI_DPDL0LPXOCR_LPXO0_Pos      (0U)
10749 #define DSI_DPDL0LPXOCR_LPXO0_Msk      (0x1UL << DSI_DPDL0LPXOCR_LPXO0_Pos)   /*!< 0x00000001 */
10750 #define DSI_DPDL0LPXOCR_LPXO0          DSI_DPDL0LPXOCR_LPXO0_Msk
10751 #define DSI_DPDL0LPXOCR_LPXO1_Pos      (1U)
10752 #define DSI_DPDL0LPXOCR_LPXO1_Msk      (0x1UL << DSI_DPDL0LPXOCR_LPXO1_Pos)   /*!< 0x00000002 */
10753 #define DSI_DPDL0LPXOCR_LPXO1          DSI_DPDL0LPXOCR_LPXO1_Msk
10754 #define DSI_DPDL0LPXOCR_LPXO2_Pos      (2U)
10755 #define DSI_DPDL0LPXOCR_LPXO2_Msk      (0x1UL << DSI_DPDL0LPXOCR_LPXO2_Pos)   /*!< 0x00000004 */
10756 #define DSI_DPDL0LPXOCR_LPXO2          DSI_DPDL0LPXOCR_LPXO2_Msk
10757 #define DSI_DPDL0LPXOCR_LPXO3_Pos      (3U)
10758 #define DSI_DPDL0LPXOCR_LPXO3_Msk      (0x1UL << DSI_DPDL0LPXOCR_LPXO3_Pos)   /*!< 0x00000008 */
10759 #define DSI_DPDL0LPXOCR_LPXO3          DSI_DPDL0LPXOCR_LPXO3_Msk
10760 
10761 /*******************  Bit definition for DSI_DPDL0BCR register  ***************/
10762 #define DSI_DPDL0BCR_Pos                (0U)
10763 #define DSI_DPDL0BCR_Msk                (0x1FUL << DSI_DPDL0BCR_Pos)         /*!< 0x0000001F */
10764 #define DSI_DPDL0BCR                    DSI_DPDL0BCR_Msk                     /*!< data lane 0 band control register */
10765 #define DSI_DPDL0BCR0_Pos               (0U)
10766 #define DSI_DPDL0BCR0_Msk               (0x1UL << DSI_DPDL0BCR0_Pos)         /*!< 0x00000001 */
10767 #define DSI_DPDL0BCR0                   DSI_DPDL0BCR0_Msk
10768 #define DSI_DPDL0BCR1_Pos               (1U)
10769 #define DSI_DPDL0BCR1_Msk               (0x1UL << DSI_DPDL0BCR1_Pos)         /*!< 0x00000002 */
10770 #define DSI_DPDL0BCR1                   DSI_DPDL0BCR1_Msk
10771 #define DSI_DPDL0BCR2_Pos               (2U)
10772 #define DSI_DPDL0BCR2_Msk               (0x1UL << DSI_DPDL0BCR2_Pos)         /*!< 0x00000004 */
10773 #define DSI_DPDL0BCR2                   DSI_DPDL0BCR2_Msk
10774 #define DSI_DPDL0BCR3_Pos               (3U)
10775 #define DSI_DPDL0BCR3_Msk               (0x1UL << DSI_DPDL0BCR3_Pos)         /*!< 0x00000008 */
10776 #define DSI_DPDL0BCR3                   DSI_DPDL0BCR3_Msk
10777 #define DSI_DPDL0BCR4_Pos               (4U)
10778 #define DSI_DPDL0BCR4_Msk               (0x1UL << DSI_DPDL0BCR4_Pos)         /*!< 0x00000010 */
10779 #define DSI_DPDL0BCR4                   DSI_DPDL0BCR4_Msk
10780 
10781 /*******************  Bit definition for DSI_DPDL0SRCR register  ***************/
10782 #define DSI_DPDL0SRCR_Pos                (0U)
10783 #define DSI_DPDL0SRCR_Msk                (0xFFUL << DSI_DPDL0SRCR_Pos)         /*!< 0x000000FF */
10784 #define DSI_DPDL0SRCR                    DSI_DPDL0SRCR_Msk                     /*!< data lane 0 slew rate control register */
10785 #define DSI_DPDL0SRCR0_Pos               (0U)
10786 #define DSI_DPDL0SRCR0_Msk               (0x1UL << DSI_DPDL0SRCR0_Pos)         /*!< 0x00000001 */
10787 #define DSI_DPDL0SRCR0                   DSI_DPDL0SRCR0_Msk
10788 #define DSI_DPDL0SRCR1_Pos               (1U)
10789 #define DSI_DPDL0SRCR1_Msk               (0x1UL << DSI_DPDL0SRCR1_Pos)         /*!< 0x00000002 */
10790 #define DSI_DPDL0SRCR1                   DSI_DPDL0SRCR1_Msk
10791 #define DSI_DPDL0SRCR2_Pos               (2U)
10792 #define DSI_DPDL0SRCR2_Msk               (0x1UL << DSI_DPDL0SRCR2_Pos)         /*!< 0x00000004 */
10793 #define DSI_DPDL0SRCR2                   DSI_DPDL0SRCR2_Msk
10794 #define DSI_DPDL0SRCR3_Pos               (3U)
10795 #define DSI_DPDL0SRCR3_Msk               (0x1UL << DSI_DPDL0SRCR3_Pos)         /*!< 0x00000008 */
10796 #define DSI_DPDL0SRCR3                   DSI_DPDL0SRCR3_Msk
10797 #define DSI_DPDL0SRCR4_Pos               (4U)
10798 #define DSI_DPDL0SRCR4_Msk               (0x1UL << DSI_DPDL0SRCR4_Pos)         /*!< 0x00000010 */
10799 #define DSI_DPDL0SRCR4                   DSI_DPDL0SRCR4_Msk
10800 #define DSI_DPDL0SRCR5_Pos               (5U)
10801 #define DSI_DPDL0SRCR5_Msk               (0x1UL << DSI_DPDL0SRCR5_Pos)         /*!< 0x00000020 */
10802 #define DSI_DPDL0SRCR5                   DSI_DPDL0SRCR5_Msk
10803 #define DSI_DPDL0SRCR6_Pos               (6U)
10804 #define DSI_DPDL0SRCR6_Msk               (0x1UL << DSI_DPDL0SRCR6_Pos)         /*!< 0x00000040 */
10805 #define DSI_DPDL0SRCR6                   DSI_DPDL0SRCR6_Msk
10806 #define DSI_DPDL0SRCR7_Pos               (7U)
10807 #define DSI_DPDL0SRCR7_Msk               (0x1UL << DSI_DPDL0SRCR7_Pos)         /*!< 0x00000080 */
10808 #define DSI_DPDL0SRCR7                   DSI_DPDL0SRCR7_Msk
10809 
10810 /*******************  Bit definition for DSI_DPDL1HSOCR register  ***************/
10811 #define DSI_DPDL1HSOCR_Pos             (4U)
10812 #define DSI_DPDL1HSOCR_Msk             (0xFUL << DSI_DPDL1HSOCR_Pos)           /*!< 0x000000F0 */
10813 #define DSI_DPDL1HSOCR                 DSI_DPDL1HSOCR_Msk                      /*!< data lane1 HS Prepare offset */
10814 #define DSI_DPDL1HSOCR_HSPRPO00_Pos    (4U)
10815 #define DSI_DPDL1HSOCR_HSPRPO00_Msk    (0x1UL << DSI_DPDL1HSOCR_HSPRPO00_Pos)  /*!< 0x00000010 */
10816 #define DSI_DPDL1HSOCR_HSPRPO00        DSI_DPDL1HSOCR_HSPRPO00_Msk
10817 #define DSI_DPDL1HSOCR_HSPRPO01_Pos    (5U)
10818 #define DSI_DPDL1HSOCR_HSPRPO01_Msk    (0x1UL << DSI_DPDL1HSOCR_HSPRPO01_Pos)  /*!< 0x00000020 */
10819 #define DSI_DPDL1HSOCR_HSPRPO01        DSI_DPDL1HSOCR_HSPRPO01_Msk
10820 #define DSI_DPDL1HSOCR_HSPRPO02_Pos    (6U)
10821 #define DSI_DPDL1HSOCR_HSPRPO02_Msk    (0x1UL << DSI_DPDL1HSOCR_HSPRPO02_Pos)  /*!< 0x00000040 */
10822 #define DSI_DPDL1HSOCR_HSPRPO02        DSI_DPDL1HSOCR_HSPRPO02_Msk
10823 #define DSI_DPDL1HSOCR_HSPRPO03_Pos    (7U)
10824 #define DSI_DPDL1HSOCR_HSPRPO03_Msk    (0x1UL << DSI_DPDL1HSOCR_HSPRPO03_Pos)  /*!< 0x00000080 */
10825 #define DSI_DPDL1HSOCR_HSPRPO03        DSI_DPDL1HSOCR_HSPRPO03_Msk
10826 
10827 /*******************  Bit definition for DSI_DPDL1LPXOCR register  ***************/
10828 #define DSI_DPDL1LPXOCR_Pos            (0U)
10829 #define DSI_DPDL1LPXOCR_Msk            (0xFUL << DSI_DPDL1LPXOCR_Pos)          /*!< 0x0000000F */
10830 #define DSI_DPDL1LPXOCR                DSI_DPDL1LPXOCR_Msk                     /*!< data lane1 LPX Offset*/
10831 #define DSI_DPDL1LPXOCR_LPXO0_Pos      (0U)
10832 #define DSI_DPDL1LPXOCR_LPXO0_Msk      (0x1UL << DSI_DPDL1LPXOCR_LPXO0_Pos)    /*!< 0x00000010 */
10833 #define DSI_DPDL1LPXOCR_LPXO0          DSI_DPDL1LPXOCR_LPXO0_Msk
10834 #define DSI_DPDL1LPXOCR_LPXO1_Pos      (1U)
10835 #define DSI_DPDL1LPXOCR_LPXO1_Msk      (0x1UL << DSI_DPDL1LPXOCR_LPXO1_Pos)    /*!< 0x00000020 */
10836 #define DSI_DPDL1LPXOCR_LPXO1          DSI_DPDL1LPXOCR_LPXO1_Msk
10837 #define DSI_DPDL1LPXOCR_LPXO2_Pos      (2U)
10838 #define DSI_DPDL1LPXOCR_LPXO2_Msk      (0x1UL << DSI_DPDL1LPXOCR_LPXO2_Pos)    /*!< 0x00000040 */
10839 #define DSI_DPDL1LPXOCR_LPXO2          DSI_DPDL1LPXOCR_LPXO2_Msk
10840 #define DSI_DPDL1LPXOCR_LPXO3_Pos      (3U)
10841 #define DSI_DPDL1LPXOCR_LPXO3_Msk      (0x1UL << DSI_DPDL1LPXOCR_LPXO3_Pos)    /*!< 0x00000080 */
10842 #define DSI_DPDL1LPXOCR_LPXO3          DSI_DPDL1LPXOCR_LPXO3_Msk
10843 
10844 /*******************  Bit definition for DSI_DPDL1BCR register  ***************/
10845 #define DSI_DPDL1BCR_Pos                (0U)
10846 #define DSI_DPDL1BCR_Msk                (0x1FUL << DSI_DPDL1BCR_Pos)         /*!< 0x0000001F */
10847 #define DSI_DPDL1BCR                    DSI_DPDL1BCR_Msk                     /*!< data lane 1 band control register */
10848 #define DSI_DPDL1BCR0_Pos               (0U)
10849 #define DSI_DPDL1BCR0_Msk               (0x1UL << DSI_DPDL1BCR0_Pos)         /*!< 0x00000001 */
10850 #define DSI_DPDL1BCR0                   DSI_DPDL1BCR0_Msk
10851 #define DSI_DPDL1BCR1_Pos               (1U)
10852 #define DSI_DPDL1BCR1_Msk               (0x1UL << DSI_DPDL1BCR1_Pos)         /*!< 0x00000002 */
10853 #define DSI_DPDL1BCR1                   DSI_DPDL1BCR1_Msk
10854 #define DSI_DPDL1BCR2_Pos               (2U)
10855 #define DSI_DPDL1BCR2_Msk               (0x1UL << DSI_DPDL1BCR2_Pos)         /*!< 0x00000004 */
10856 #define DSI_DPDL1BCR2                   DSI_DPDL1BCR2_Msk
10857 #define DSI_DPDL1BCR3_Pos               (3U)
10858 #define DSI_DPDL1BCR3_Msk               (0x1UL << DSI_DPDL1BCR3_Pos)         /*!< 0x00000008 */
10859 #define DSI_DPDL1BCR3                   DSI_DPDL1BCR3_Msk
10860 #define DSI_DPDL1BCR4_Pos               (4U)
10861 #define DSI_DPDL1BCR4_Msk               (0x1UL << DSI_DPDL1BCR4_Pos)         /*!< 0x00000010 */
10862 #define DSI_DPDL1BCR4                   DSI_DPDL1BCR4_Msk
10863 
10864 /*******************  Bit definition for DSI_DPDL1SRCR register  ***************/
10865 #define DSI_DPDL1SRCR_Pos                (0U)
10866 #define DSI_DPDL1SRCR_Msk                (0xFFUL << DSI_DPDL1SRCR_Pos)         /*!< 0x000000FF */
10867 #define DSI_DPDL1SRCR                    DSI_DPDL1SRCR_Msk                     /*!< data lane 1 slew rate control register */
10868 #define DSI_DPDL1SRCR0_Pos               (0U)
10869 #define DSI_DPDL1SRCR0_Msk               (0x1UL << DSI_DPDL1SRCR0_Pos)         /*!< 0x00000001 */
10870 #define DSI_DPDL1SRCR0                   DSI_DPDL1SRCR0_Msk
10871 #define DSI_DPDL1SRCR1_Pos               (1U)
10872 #define DSI_DPDL1SRCR1_Msk               (0x1UL << DSI_DPDL1SRCR1_Pos)         /*!< 0x00000002 */
10873 #define DSI_DPDL1SRCR1                   DSI_DPDL1SRCR1_Msk
10874 #define DSI_DPDL1SRCR2_Pos               (2U)
10875 #define DSI_DPDL1SRCR2_Msk               (0x1UL << DSI_DPDL1SRCR2_Pos)         /*!< 0x00000004 */
10876 #define DSI_DPDL1SRCR2                   DSI_DPDL1SRCR2_Msk
10877 #define DSI_DPDL1SRCR3_Pos               (3U)
10878 #define DSI_DPDL1SRCR3_Msk               (0x1UL << DSI_DPDL1SRCR3_Pos)         /*!< 0x00000008 */
10879 #define DSI_DPDL1SRCR3                   DSI_DPDL1SRCR3_Msk
10880 #define DSI_DPDL1SRCR4_Pos               (4U)
10881 #define DSI_DPDL1SRCR4_Msk               (0x1UL << DSI_DPDL1SRCR4_Pos)         /*!< 0x00000010 */
10882 #define DSI_DPDL1SRCR4                   DSI_DPDL1SRCR4_Msk
10883 #define DSI_DPDL1SRCR5_Pos               (5U)
10884 #define DSI_DPDL1SRCR5_Msk               (0x1UL << DSI_DPDL1SRCR5_Pos)         /*!< 0x00000020 */
10885 #define DSI_DPDL1SRCR5                   DSI_DPDL1SRCR5_Msk
10886 #define DSI_DPDL1SRCR6_Pos               (6U)
10887 #define DSI_DPDL1SRCR6_Msk               (0x1UL << DSI_DPDL1SRCR6_Pos)         /*!< 0x00000040 */
10888 #define DSI_DPDL1SRCR6                   DSI_DPDL1SRCR6_Msk
10889 #define DSI_DPDL1SRCR7_Pos               (7U)
10890 #define DSI_DPDL1SRCR7_Msk               (0x1UL << DSI_DPDL1SRCR7_Pos)         /*!< 0x00000080 */
10891 #define DSI_DPDL1SRCR7                   DSI_DPDL1SRCR7_Msk
10892 
10893 /******************************************************************************/
10894 /*                                                                            */
10895 /*                    External Interrupt/Event Controller                     */
10896 /*                                                                            */
10897 /******************************************************************************/
10898 /******************  Bit definition for EXTI_RTSR1 register  ******************/
10899 #define EXTI_RTSR1_RT0_Pos                  (0U)
10900 #define EXTI_RTSR1_RT0_Msk                  (0x1UL << EXTI_RTSR1_RT0_Pos)           /*!< 0x00000001 */
10901 #define EXTI_RTSR1_RT0                      EXTI_RTSR1_RT0_Msk                      /*!< Rising trigger configuration for input line 0 */
10902 #define EXTI_RTSR1_RT1_Pos                  (1U)
10903 #define EXTI_RTSR1_RT1_Msk                  (0x1UL << EXTI_RTSR1_RT1_Pos)           /*!< 0x00000002 */
10904 #define EXTI_RTSR1_RT1                      EXTI_RTSR1_RT1_Msk                      /*!< Rising trigger configuration for input line 1 */
10905 #define EXTI_RTSR1_RT2_Pos                  (2U)
10906 #define EXTI_RTSR1_RT2_Msk                  (0x1UL << EXTI_RTSR1_RT2_Pos)           /*!< 0x00000004 */
10907 #define EXTI_RTSR1_RT2                      EXTI_RTSR1_RT2_Msk                      /*!< Rising trigger configuration for input line 2 */
10908 #define EXTI_RTSR1_RT3_Pos                  (3U)
10909 #define EXTI_RTSR1_RT3_Msk                  (0x1UL << EXTI_RTSR1_RT3_Pos)           /*!< 0x00000008 */
10910 #define EXTI_RTSR1_RT3                      EXTI_RTSR1_RT3_Msk                      /*!< Rising trigger configuration for input line 3 */
10911 #define EXTI_RTSR1_RT4_Pos                  (4U)
10912 #define EXTI_RTSR1_RT4_Msk                  (0x1UL << EXTI_RTSR1_RT4_Pos)           /*!< 0x00000010 */
10913 #define EXTI_RTSR1_RT4                      EXTI_RTSR1_RT4_Msk                      /*!< Rising trigger configuration for input line 4 */
10914 #define EXTI_RTSR1_RT5_Pos                  (5U)
10915 #define EXTI_RTSR1_RT5_Msk                  (0x1UL << EXTI_RTSR1_RT5_Pos)           /*!< 0x00000020 */
10916 #define EXTI_RTSR1_RT5                      EXTI_RTSR1_RT5_Msk                      /*!< Rising trigger configuration for input line 5 */
10917 #define EXTI_RTSR1_RT6_Pos                  (6U)
10918 #define EXTI_RTSR1_RT6_Msk                  (0x1UL << EXTI_RTSR1_RT6_Pos)           /*!< 0x00000040 */
10919 #define EXTI_RTSR1_RT6                      EXTI_RTSR1_RT6_Msk                      /*!< Rising trigger configuration for input line 6 */
10920 #define EXTI_RTSR1_RT7_Pos                  (7U)
10921 #define EXTI_RTSR1_RT7_Msk                  (0x1UL << EXTI_RTSR1_RT7_Pos)           /*!< 0x00000080 */
10922 #define EXTI_RTSR1_RT7                      EXTI_RTSR1_RT7_Msk                      /*!< Rising trigger configuration for input line 7 */
10923 #define EXTI_RTSR1_RT8_Pos                  (8U)
10924 #define EXTI_RTSR1_RT8_Msk                  (0x1UL << EXTI_RTSR1_RT8_Pos)           /*!< 0x00000100 */
10925 #define EXTI_RTSR1_RT8                      EXTI_RTSR1_RT8_Msk                      /*!< Rising trigger configuration for input line 8 */
10926 #define EXTI_RTSR1_RT9_Pos                  (9U)
10927 #define EXTI_RTSR1_RT9_Msk                  (0x1UL << EXTI_RTSR1_RT9_Pos)           /*!< 0x00000200 */
10928 #define EXTI_RTSR1_RT9                      EXTI_RTSR1_RT9_Msk                      /*!< Rising trigger configuration for input line 9 */
10929 #define EXTI_RTSR1_RT10_Pos                 (10U)
10930 #define EXTI_RTSR1_RT10_Msk                 (0x1UL << EXTI_RTSR1_RT10_Pos)          /*!< 0x00000400 */
10931 #define EXTI_RTSR1_RT10                     EXTI_RTSR1_RT10_Msk                     /*!< Rising trigger configuration for input line 10 */
10932 #define EXTI_RTSR1_RT11_Pos                 (11U)
10933 #define EXTI_RTSR1_RT11_Msk                 (0x1UL << EXTI_RTSR1_RT11_Pos)          /*!< 0x00000800 */
10934 #define EXTI_RTSR1_RT11                     EXTI_RTSR1_RT11_Msk                     /*!< Rising trigger configuration for input line 11 */
10935 #define EXTI_RTSR1_RT12_Pos                 (12U)
10936 #define EXTI_RTSR1_RT12_Msk                 (0x1UL << EXTI_RTSR1_RT12_Pos)          /*!< 0x00001000 */
10937 #define EXTI_RTSR1_RT12                     EXTI_RTSR1_RT12_Msk                     /*!< Rising trigger configuration for input line 12 */
10938 #define EXTI_RTSR1_RT13_Pos                 (13U)
10939 #define EXTI_RTSR1_RT13_Msk                 (0x1UL << EXTI_RTSR1_RT13_Pos)          /*!< 0x00002000 */
10940 #define EXTI_RTSR1_RT13                     EXTI_RTSR1_RT13_Msk                     /*!< Rising trigger configuration for input line 13 */
10941 #define EXTI_RTSR1_RT14_Pos                 (14U)
10942 #define EXTI_RTSR1_RT14_Msk                 (0x1UL << EXTI_RTSR1_RT14_Pos)          /*!< 0x00004000 */
10943 #define EXTI_RTSR1_RT14                     EXTI_RTSR1_RT14_Msk                     /*!< Rising trigger configuration for input line 14 */
10944 #define EXTI_RTSR1_RT15_Pos                 (15U)
10945 #define EXTI_RTSR1_RT15_Msk                 (0x1UL << EXTI_RTSR1_RT15_Pos)          /*!< 0x00008000 */
10946 #define EXTI_RTSR1_RT15                     EXTI_RTSR1_RT15_Msk                     /*!< Rising trigger configuration for input line 15 */
10947 #define EXTI_RTSR1_RT16_Pos                 (16U)
10948 #define EXTI_RTSR1_RT16_Msk                 (0x1UL << EXTI_RTSR1_RT16_Pos)          /*!< 0x00010000 */
10949 #define EXTI_RTSR1_RT16                     EXTI_RTSR1_RT16_Msk                     /*!< Rising trigger configuration for input line 16 */
10950 #define EXTI_RTSR1_RT17_Pos                 (17U)
10951 #define EXTI_RTSR1_RT17_Msk                 (0x1UL << EXTI_RTSR1_RT17_Pos)          /*!< 0x00020000 */
10952 #define EXTI_RTSR1_RT17                     EXTI_RTSR1_RT17_Msk                     /*!< Rising trigger configuration for input line 17 */
10953 #define EXTI_RTSR1_RT18_Pos                 (18U)
10954 #define EXTI_RTSR1_RT18_Msk                 (0x1UL << EXTI_RTSR1_RT18_Pos)          /*!< 0x00040000 */
10955 #define EXTI_RTSR1_RT18                     EXTI_RTSR1_RT18_Msk                     /*!< Rising trigger configuration for input line 18 */
10956 #define EXTI_RTSR1_RT19_Pos                 (19U)
10957 #define EXTI_RTSR1_RT19_Msk                 (0x1UL << EXTI_RTSR1_RT19_Pos)          /*!< 0x00080000 */
10958 #define EXTI_RTSR1_RT19                     EXTI_RTSR1_RT19_Msk                     /*!< Rising trigger configuration for input line 19 */
10959 #define EXTI_RTSR1_RT20_Pos                 (20U)
10960 #define EXTI_RTSR1_RT20_Msk                 (0x1UL << EXTI_RTSR1_RT20_Pos)          /*!< 0x00100000 */
10961 #define EXTI_RTSR1_RT20                     EXTI_RTSR1_RT20_Msk                     /*!< Rising trigger configuration for input line 20 */
10962 #define EXTI_RTSR1_RT21_Pos                 (21U)
10963 #define EXTI_RTSR1_RT21_Msk                 (0x1UL << EXTI_RTSR1_RT21_Pos)          /*!< 0x00200000 */
10964 #define EXTI_RTSR1_RT21                     EXTI_RTSR1_RT21_Msk                     /*!< Rising trigger configuration for input line 21 */
10965 #define EXTI_RTSR1_RT22_Pos                 (22U)
10966 #define EXTI_RTSR1_RT22_Msk                 (0x1UL << EXTI_RTSR1_RT22_Pos)          /*!< 0x00400000 */
10967 #define EXTI_RTSR1_RT22                     EXTI_RTSR1_RT22_Msk                     /*!< Rising trigger configuration for input line 22 */
10968 #define EXTI_RTSR1_RT23_Pos                 (23U)
10969 #define EXTI_RTSR1_RT23_Msk                 (0x1UL << EXTI_RTSR1_RT23_Pos)          /*!< 0x00800000 */
10970 #define EXTI_RTSR1_RT23                     EXTI_RTSR1_RT23_Msk                     /*!< Rising trigger configuration for input line 23 */
10971 #define EXTI_RTSR1_RT24_Pos                 (24U)
10972 #define EXTI_RTSR1_RT24_Msk                 (0x1UL << EXTI_RTSR1_RT24_Pos)          /*!< 0x01000000 */
10973 #define EXTI_RTSR1_RT24                     EXTI_RTSR1_RT24_Msk                     /*!< Rising trigger configuration for input line 24 */
10974 #define EXTI_RTSR1_RT25_Pos                  (25U)
10975 #define EXTI_RTSR1_RT25_Msk                 (0x1UL << EXTI_RTSR1_RT25_Pos)          /*!< 0x02000000 */
10976 #define EXTI_RTSR1_RT25                     EXTI_RTSR1_RT25_Msk                     /*!< Rising trigger configuration for input line 24 */
10977 
10978 /******************  Bit definition for EXTI_FTSR1 register  ******************/
10979 #define EXTI_FTSR1_FT0_Pos                  (0U)
10980 #define EXTI_FTSR1_FT0_Msk                  (0x1UL << EXTI_FTSR1_FT0_Pos)           /*!< 0x00000001 */
10981 #define EXTI_FTSR1_FT0                      EXTI_FTSR1_FT0_Msk                      /*!< Falling trigger configuration for input line 0 */
10982 #define EXTI_FTSR1_FT1_Pos                  (1U)
10983 #define EXTI_FTSR1_FT1_Msk                  (0x1UL << EXTI_FTSR1_FT1_Pos)           /*!< 0x00000002 */
10984 #define EXTI_FTSR1_FT1                      EXTI_FTSR1_FT1_Msk                      /*!< Falling trigger configuration for input line 1 */
10985 #define EXTI_FTSR1_FT2_Pos                  (2U)
10986 #define EXTI_FTSR1_FT2_Msk                  (0x1UL << EXTI_FTSR1_FT2_Pos)           /*!< 0x00000004 */
10987 #define EXTI_FTSR1_FT2                      EXTI_FTSR1_FT2_Msk                      /*!< Falling trigger configuration for input line 2 */
10988 #define EXTI_FTSR1_FT3_Pos                  (3U)
10989 #define EXTI_FTSR1_FT3_Msk                  (0x1UL << EXTI_FTSR1_FT3_Pos)           /*!< 0x00000008 */
10990 #define EXTI_FTSR1_FT3                      EXTI_FTSR1_FT3_Msk                      /*!< Falling trigger configuration for input line 3 */
10991 #define EXTI_FTSR1_FT4_Pos                  (4U)
10992 #define EXTI_FTSR1_FT4_Msk                  (0x1UL << EXTI_FTSR1_FT4_Pos)           /*!< 0x00000010 */
10993 #define EXTI_FTSR1_FT4                      EXTI_FTSR1_FT4_Msk                      /*!< Falling trigger configuration for input line 4 */
10994 #define EXTI_FTSR1_FT5_Pos                  (5U)
10995 #define EXTI_FTSR1_FT5_Msk                  (0x1UL << EXTI_FTSR1_FT5_Pos)           /*!< 0x00000020 */
10996 #define EXTI_FTSR1_FT5                      EXTI_FTSR1_FT5_Msk                      /*!< Falling trigger configuration for input line 5 */
10997 #define EXTI_FTSR1_FT6_Pos                  (6U)
10998 #define EXTI_FTSR1_FT6_Msk                  (0x1UL << EXTI_FTSR1_FT6_Pos)           /*!< 0x00000040 */
10999 #define EXTI_FTSR1_FT6                      EXTI_FTSR1_FT6_Msk                      /*!< Falling trigger configuration for input line 6 */
11000 #define EXTI_FTSR1_FT7_Pos                  (7U)
11001 #define EXTI_FTSR1_FT7_Msk                  (0x1UL << EXTI_FTSR1_FT7_Pos)           /*!< 0x00000080 */
11002 #define EXTI_FTSR1_FT7                      EXTI_FTSR1_FT7_Msk                      /*!< Falling trigger configuration for input line 7 */
11003 #define EXTI_FTSR1_FT8_Pos                  (8U)
11004 #define EXTI_FTSR1_FT8_Msk                  (0x1UL << EXTI_FTSR1_FT8_Pos)           /*!< 0x00000100 */
11005 #define EXTI_FTSR1_FT8                      EXTI_FTSR1_FT8_Msk                      /*!< Falling trigger configuration for input line 8 */
11006 #define EXTI_FTSR1_FT9_Pos                  (9U)
11007 #define EXTI_FTSR1_FT9_Msk                  (0x1UL << EXTI_FTSR1_FT9_Pos)           /*!< 0x00000200 */
11008 #define EXTI_FTSR1_FT9                      EXTI_FTSR1_FT9_Msk                      /*!< Falling trigger configuration for input line 9 */
11009 #define EXTI_FTSR1_FT10_Pos                 (10U)
11010 #define EXTI_FTSR1_FT10_Msk                 (0x1UL << EXTI_FTSR1_FT10_Pos)          /*!< 0x00000400 */
11011 #define EXTI_FTSR1_FT10                     EXTI_FTSR1_FT10_Msk                     /*!< Falling trigger configuration for input line 10 */
11012 #define EXTI_FTSR1_FT11_Pos                 (11U)
11013 #define EXTI_FTSR1_FT11_Msk                 (0x1UL << EXTI_FTSR1_FT11_Pos)          /*!< 0x00000800 */
11014 #define EXTI_FTSR1_FT11                     EXTI_FTSR1_FT11_Msk                     /*!< Falling trigger configuration for input line 11 */
11015 #define EXTI_FTSR1_FT12_Pos                 (12U)
11016 #define EXTI_FTSR1_FT12_Msk                 (0x1UL << EXTI_FTSR1_FT12_Pos)          /*!< 0x00001000 */
11017 #define EXTI_FTSR1_FT12                     EXTI_FTSR1_FT12_Msk                     /*!< Falling trigger configuration for input line 12 */
11018 #define EXTI_FTSR1_FT13_Pos                 (13U)
11019 #define EXTI_FTSR1_FT13_Msk                 (0x1UL << EXTI_FTSR1_FT13_Pos)          /*!< 0x00002000 */
11020 #define EXTI_FTSR1_FT13                     EXTI_FTSR1_FT13_Msk                     /*!< Falling trigger configuration for input line 13 */
11021 #define EXTI_FTSR1_FT14_Pos                 (14U)
11022 #define EXTI_FTSR1_FT14_Msk                 (0x1UL << EXTI_FTSR1_FT14_Pos)          /*!< 0x00004000 */
11023 #define EXTI_FTSR1_FT14                     EXTI_FTSR1_FT14_Msk                     /*!< Falling trigger configuration for input line 14 */
11024 #define EXTI_FTSR1_FT15_Pos                 (15U)
11025 #define EXTI_FTSR1_FT15_Msk                 (0x1UL << EXTI_FTSR1_FT15_Pos)          /*!< 0x00008000 */
11026 #define EXTI_FTSR1_FT15                     EXTI_FTSR1_FT15_Msk                     /*!< Falling trigger configuration for input line 15 */
11027 #define EXTI_FTSR1_FT16_Pos                 (16U)
11028 #define EXTI_FTSR1_FT16_Msk                 (0x1UL << EXTI_FTSR1_FT16_Pos)          /*!< 0x00010000 */
11029 #define EXTI_FTSR1_FT16                     EXTI_FTSR1_FT16_Msk                     /*!< Falling trigger configuration for input line 16 */
11030 #define EXTI_FTSR1_FT17_Pos                 (17U)
11031 #define EXTI_FTSR1_FT17_Msk                 (0x1UL << EXTI_FTSR1_FT17_Pos)          /*!< 0x00020000 */
11032 #define EXTI_FTSR1_FT17                     EXTI_FTSR1_FT17_Msk                     /*!< Falling trigger configuration for input line 17 */
11033 #define EXTI_FTSR1_FT18_Pos                 (18U)
11034 #define EXTI_FTSR1_FT18_Msk                 (0x1UL << EXTI_FTSR1_FT18_Pos)          /*!< 0x00040000 */
11035 #define EXTI_FTSR1_FT18                     EXTI_FTSR1_FT18_Msk                     /*!< Falling trigger configuration for input line 18 */
11036 #define EXTI_FTSR1_FT19_Pos                 (19U)
11037 #define EXTI_FTSR1_FT19_Msk                 (0x1UL << EXTI_FTSR1_FT19_Pos)          /*!< 0x00080000 */
11038 #define EXTI_FTSR1_FT19                     EXTI_FTSR1_FT19_Msk                     /*!< Falling trigger configuration for input line 19 */
11039 #define EXTI_FTSR1_FT20_Pos                 (20U)
11040 #define EXTI_FTSR1_FT20_Msk                 (0x1UL << EXTI_FTSR1_FT20_Pos)          /*!< 0x00100000 */
11041 #define EXTI_FTSR1_FT20                     EXTI_FTSR1_FT20_Msk                     /*!< Falling trigger configuration for input line 20 */
11042 #define EXTI_FTSR1_FT21_Pos                 (21U)
11043 #define EXTI_FTSR1_FT21_Msk                 (0x1UL << EXTI_FTSR1_FT21_Pos)          /*!< 0x00200000 */
11044 #define EXTI_FTSR1_FT21                     EXTI_FTSR1_FT21_Msk                     /*!< Falling trigger configuration for input line 21 */
11045 #define EXTI_FTSR1_FT22_Pos                 (22U)
11046 #define EXTI_FTSR1_FT22_Msk                 (0x1UL << EXTI_FTSR1_FT22_Pos)          /*!< 0x00400000 */
11047 #define EXTI_FTSR1_FT22                     EXTI_FTSR1_FT22_Msk                     /*!< Falling trigger configuration for input line 22 */
11048 #define EXTI_FTSR1_FT23_Pos                 (23U)
11049 #define EXTI_FTSR1_FT23_Msk                 (0x1UL << EXTI_FTSR1_FT23_Pos)          /*!< 0x00800000 */
11050 #define EXTI_FTSR1_FT23                     EXTI_FTSR1_FT23_Msk                     /*!< Falling trigger configuration for input line 23 */
11051 #define EXTI_FTSR1_FT24_Pos                 (24U)
11052 #define EXTI_FTSR1_FT24_Msk                 (0x1UL << EXTI_FTSR1_FT24_Pos)          /*!< 0x01000000 */
11053 #define EXTI_FTSR1_FT24                     EXTI_FTSR1_FT24_Msk                     /*!< Falling trigger configuration for input line 24 */
11054 #define EXTI_FTSR1_FT25_Pos                 (25U)
11055 #define EXTI_FTSR1_FT25_Msk                 (0x1UL << EXTI_FTSR1_FT25_Pos)          /*!< 0x02000000 */
11056 #define EXTI_FTSR1_FT25                     EXTI_FTSR1_FT25_Msk                     /*!< Falling trigger configuration for input line 25 */
11057 
11058 /******************  Bit definition for EXTI_SWIER1 register  *****************/
11059 #define EXTI_SWIER1_SWI0_Pos                (0U)
11060 #define EXTI_SWIER1_SWI0_Msk                (0x1UL << EXTI_SWIER1_SWI0_Pos)         /*!< 0x00000001 */
11061 #define EXTI_SWIER1_SWI0                    EXTI_SWIER1_SWI0_Msk                    /*!< Software Interrupt on line 0 */
11062 #define EXTI_SWIER1_SWI1_Pos                (1U)
11063 #define EXTI_SWIER1_SWI1_Msk                (0x1UL << EXTI_SWIER1_SWI1_Pos)         /*!< 0x00000002 */
11064 #define EXTI_SWIER1_SWI1                    EXTI_SWIER1_SWI1_Msk                    /*!< Software Interrupt on line 1 */
11065 #define EXTI_SWIER1_SWI2_Pos                (2U)
11066 #define EXTI_SWIER1_SWI2_Msk                (0x1UL << EXTI_SWIER1_SWI2_Pos)         /*!< 0x00000004 */
11067 #define EXTI_SWIER1_SWI2                    EXTI_SWIER1_SWI2_Msk                    /*!< Software Interrupt on line 2 */
11068 #define EXTI_SWIER1_SWI3_Pos                (3U)
11069 #define EXTI_SWIER1_SWI3_Msk                (0x1UL << EXTI_SWIER1_SWI3_Pos)         /*!< 0x00000008 */
11070 #define EXTI_SWIER1_SWI3                    EXTI_SWIER1_SWI3_Msk                    /*!< Software Interrupt on line 3 */
11071 #define EXTI_SWIER1_SWI4_Pos                (4U)
11072 #define EXTI_SWIER1_SWI4_Msk                (0x1UL << EXTI_SWIER1_SWI4_Pos)         /*!< 0x00000010 */
11073 #define EXTI_SWIER1_SWI4                    EXTI_SWIER1_SWI4_Msk                    /*!< Software Interrupt on line 4 */
11074 #define EXTI_SWIER1_SWI5_Pos                (5U)
11075 #define EXTI_SWIER1_SWI5_Msk                (0x1UL << EXTI_SWIER1_SWI5_Pos)         /*!< 0x00000020 */
11076 #define EXTI_SWIER1_SWI5                    EXTI_SWIER1_SWI5_Msk                    /*!< Software Interrupt on line 5 */
11077 #define EXTI_SWIER1_SWI6_Pos                (6U)
11078 #define EXTI_SWIER1_SWI6_Msk                (0x1UL << EXTI_SWIER1_SWI6_Pos)         /*!< 0x00000040 */
11079 #define EXTI_SWIER1_SWI6                    EXTI_SWIER1_SWI6_Msk                    /*!< Software Interrupt on line 6 */
11080 #define EXTI_SWIER1_SWI7_Pos                (7U)
11081 #define EXTI_SWIER1_SWI7_Msk                (0x1UL << EXTI_SWIER1_SWI7_Pos)         /*!< 0x00000080 */
11082 #define EXTI_SWIER1_SWI7                    EXTI_SWIER1_SWI7_Msk                    /*!< Software Interrupt on line 7 */
11083 #define EXTI_SWIER1_SWI8_Pos                (8U)
11084 #define EXTI_SWIER1_SWI8_Msk                (0x1UL << EXTI_SWIER1_SWI8_Pos)         /*!< 0x00000100 */
11085 #define EXTI_SWIER1_SWI8                    EXTI_SWIER1_SWI8_Msk                    /*!< Software Interrupt on line 8 */
11086 #define EXTI_SWIER1_SWI9_Pos                (9U)
11087 #define EXTI_SWIER1_SWI9_Msk                (0x1UL << EXTI_SWIER1_SWI9_Pos)         /*!< 0x00000200 */
11088 #define EXTI_SWIER1_SWI9                    EXTI_SWIER1_SWI9_Msk                    /*!< Software Interrupt on line 9 */
11089 #define EXTI_SWIER1_SWI10_Pos               (10U)
11090 #define EXTI_SWIER1_SWI10_Msk               (0x1UL << EXTI_SWIER1_SWI10_Pos)        /*!< 0x00000400 */
11091 #define EXTI_SWIER1_SWI10                   EXTI_SWIER1_SWI10_Msk                   /*!< Software Interrupt on line 10 */
11092 #define EXTI_SWIER1_SWI11_Pos               (11U)
11093 #define EXTI_SWIER1_SWI11_Msk               (0x1UL << EXTI_SWIER1_SWI11_Pos)        /*!< 0x00000800 */
11094 #define EXTI_SWIER1_SWI11                   EXTI_SWIER1_SWI11_Msk                   /*!< Software Interrupt on line 11 */
11095 #define EXTI_SWIER1_SWI12_Pos               (12U)
11096 #define EXTI_SWIER1_SWI12_Msk               (0x1UL << EXTI_SWIER1_SWI12_Pos)        /*!< 0x00001000 */
11097 #define EXTI_SWIER1_SWI12                   EXTI_SWIER1_SWI12_Msk                   /*!< Software Interrupt on line 12 */
11098 #define EXTI_SWIER1_SWI13_Pos               (13U)
11099 #define EXTI_SWIER1_SWI13_Msk               (0x1UL << EXTI_SWIER1_SWI13_Pos)        /*!< 0x00002000 */
11100 #define EXTI_SWIER1_SWI13                   EXTI_SWIER1_SWI13_Msk                   /*!< Software Interrupt on line 13 */
11101 #define EXTI_SWIER1_SWI14_Pos               (14U)
11102 #define EXTI_SWIER1_SWI14_Msk               (0x1UL << EXTI_SWIER1_SWI14_Pos)        /*!< 0x00004000 */
11103 #define EXTI_SWIER1_SWI14                   EXTI_SWIER1_SWI14_Msk                   /*!< Software Interrupt on line 14 */
11104 #define EXTI_SWIER1_SWI15_Pos               (15U)
11105 #define EXTI_SWIER1_SWI15_Msk               (0x1UL << EXTI_SWIER1_SWI15_Pos)        /*!< 0x00008000 */
11106 #define EXTI_SWIER1_SWI15                   EXTI_SWIER1_SWI15_Msk                   /*!< Software Interrupt on line 15 */
11107 #define EXTI_SWIER1_SWI16_Pos               (16U)
11108 #define EXTI_SWIER1_SWI16_Msk               (0x1UL << EXTI_SWIER1_SWI16_Pos)        /*!< 0x00010000 */
11109 #define EXTI_SWIER1_SWI16                   EXTI_SWIER1_SWI16_Msk                   /*!< Software Interrupt on line 16 */
11110 #define EXTI_SWIER1_SWI17_Pos               (17U)
11111 #define EXTI_SWIER1_SWI17_Msk               (0x1UL << EXTI_SWIER1_SWI17_Pos)        /*!< 0x00020000 */
11112 #define EXTI_SWIER1_SWI17                   EXTI_SWIER1_SWI17_Msk                   /*!< Software Interrupt on line 17 */
11113 #define EXTI_SWIER1_SWI18_Pos               (18U)
11114 #define EXTI_SWIER1_SWI18_Msk               (0x1UL << EXTI_SWIER1_SWI18_Pos)        /*!< 0x00040000 */
11115 #define EXTI_SWIER1_SWI18                   EXTI_SWIER1_SWI18_Msk                   /*!< Software Interrupt on line 18 */
11116 #define EXTI_SWIER1_SWI19_Pos               (19U)
11117 #define EXTI_SWIER1_SWI19_Msk               (0x1UL << EXTI_SWIER1_SWI19_Pos)        /*!< 0x00080000 */
11118 #define EXTI_SWIER1_SWI19                   EXTI_SWIER1_SWI19_Msk                   /*!< Software Interrupt on line 19 */
11119 #define EXTI_SWIER1_SWI20_Pos               (20U)
11120 #define EXTI_SWIER1_SWI20_Msk               (0x1UL << EXTI_SWIER1_SWI20_Pos)        /*!< 0x00100000 */
11121 #define EXTI_SWIER1_SWI20                   EXTI_SWIER1_SWI20_Msk                   /*!< Software Interrupt on line 20 */
11122 #define EXTI_SWIER1_SWI21_Pos               (21U)
11123 #define EXTI_SWIER1_SWI21_Msk               (0x1UL << EXTI_SWIER1_SWI21_Pos)        /*!< 0x00200000 */
11124 #define EXTI_SWIER1_SWI21                   EXTI_SWIER1_SWI21_Msk                   /*!< Software Interrupt on line 21 */
11125 #define EXTI_SWIER1_SWI22_Pos               (22U)
11126 #define EXTI_SWIER1_SWI22_Msk               (0x1UL << EXTI_SWIER1_SWI22_Pos)        /*!< 0x00400000 */
11127 #define EXTI_SWIER1_SWI22                   EXTI_SWIER1_SWI22_Msk                   /*!< Software Interrupt on line 22 */
11128 #define EXTI_SWIER1_SWI23_Pos               (23U)
11129 #define EXTI_SWIER1_SWI23_Msk               (0x1UL << EXTI_SWIER1_SWI23_Pos)        /*!< 0x00800000 */
11130 #define EXTI_SWIER1_SWI23                   EXTI_SWIER1_SWI23_Msk                   /*!< Software Interrupt on line 23 */
11131 #define EXTI_SWIER1_SWI24_Pos               (24U)
11132 #define EXTI_SWIER1_SWI24_Msk               (0x1UL << EXTI_SWIER1_SWI24_Pos)        /*!< 0x01000000 */
11133 #define EXTI_SWIER1_SWI24                   EXTI_SWIER1_SWI24_Msk                   /*!< Software Interrupt on line 24 */
11134 #define EXTI_SWIER1_SWI25_Pos               (25U)
11135 #define EXTI_SWIER1_SWI25_Msk               (0x1UL << EXTI_SWIER1_SWI25_Pos)        /*!< 0x02000000 */
11136 #define EXTI_SWIER1_SWI25                   EXTI_SWIER1_SWI25_Msk                   /*!< Software Interrupt on line 25 */
11137 
11138 /*******************  Bit definition for EXTI_RPR1 register  ******************/
11139 #define EXTI_RPR1_RPIF0_Pos                 (0U)
11140 #define EXTI_RPR1_RPIF0_Msk                 (0x1UL << EXTI_RPR1_RPIF0_Pos)          /*!< 0x00000001 */
11141 #define EXTI_RPR1_RPIF0                     EXTI_RPR1_RPIF0_Msk                     /*!< Rising Pending Interrupt Flag on line 0 */
11142 #define EXTI_RPR1_RPIF1_Pos                 (1U)
11143 #define EXTI_RPR1_RPIF1_Msk                 (0x1UL << EXTI_RPR1_RPIF1_Pos)          /*!< 0x00000002 */
11144 #define EXTI_RPR1_RPIF1                     EXTI_RPR1_RPIF1_Msk                     /*!< Rising Pending Interrupt Flag on line 1 */
11145 #define EXTI_RPR1_RPIF2_Pos                 (2U)
11146 #define EXTI_RPR1_RPIF2_Msk                 (0x1UL << EXTI_RPR1_RPIF2_Pos)          /*!< 0x00000004 */
11147 #define EXTI_RPR1_RPIF2                     EXTI_RPR1_RPIF2_Msk                     /*!< Rising Pending Interrupt Flag on line 2 */
11148 #define EXTI_RPR1_RPIF3_Pos                 (3U)
11149 #define EXTI_RPR1_RPIF3_Msk                 (0x1UL << EXTI_RPR1_RPIF3_Pos)          /*!< 0x00000008 */
11150 #define EXTI_RPR1_RPIF3                     EXTI_RPR1_RPIF3_Msk                     /*!< Rising Pending Interrupt Flag on line 3 */
11151 #define EXTI_RPR1_RPIF4_Pos                 (4U)
11152 #define EXTI_RPR1_RPIF4_Msk                 (0x1UL << EXTI_RPR1_RPIF4_Pos)          /*!< 0x00000010 */
11153 #define EXTI_RPR1_RPIF4                     EXTI_RPR1_RPIF4_Msk                     /*!< Rising Pending Interrupt Flag on line 4 */
11154 #define EXTI_RPR1_RPIF5_Pos                 (5U)
11155 #define EXTI_RPR1_RPIF5_Msk                 (0x1UL << EXTI_RPR1_RPIF5_Pos)          /*!< 0x00000020 */
11156 #define EXTI_RPR1_RPIF5                     EXTI_RPR1_RPIF5_Msk                     /*!< Rising Pending Interrupt Flag on line 5 */
11157 #define EXTI_RPR1_RPIF6_Pos                 (6U)
11158 #define EXTI_RPR1_RPIF6_Msk                 (0x1UL << EXTI_RPR1_RPIF6_Pos)          /*!< 0x00000040 */
11159 #define EXTI_RPR1_RPIF6                     EXTI_RPR1_RPIF6_Msk                     /*!< Rising Pending Interrupt Flag on line 6 */
11160 #define EXTI_RPR1_RPIF7_Pos                 (7U)
11161 #define EXTI_RPR1_RPIF7_Msk                 (0x1UL << EXTI_RPR1_RPIF7_Pos)          /*!< 0x00000080 */
11162 #define EXTI_RPR1_RPIF7                     EXTI_RPR1_RPIF7_Msk                     /*!< Rising Pending Interrupt Flag on line 7 */
11163 #define EXTI_RPR1_RPIF8_Pos                 (8U)
11164 #define EXTI_RPR1_RPIF8_Msk                 (0x1UL << EXTI_RPR1_RPIF8_Pos)          /*!< 0x00000100 */
11165 #define EXTI_RPR1_RPIF8                     EXTI_RPR1_RPIF8_Msk                     /*!< Rising Pending Interrupt Flag on line 8 */
11166 #define EXTI_RPR1_RPIF9_Pos                 (9U)
11167 #define EXTI_RPR1_RPIF9_Msk                 (0x1UL << EXTI_RPR1_RPIF9_Pos)          /*!< 0x00000200 */
11168 #define EXTI_RPR1_RPIF9                     EXTI_RPR1_RPIF9_Msk                     /*!< Rising Pending Interrupt Flag on line 9 */
11169 #define EXTI_RPR1_RPIF10_Pos                (10U)
11170 #define EXTI_RPR1_RPIF10_Msk                (0x1UL << EXTI_RPR1_RPIF10_Pos)         /*!< 0x00000400 */
11171 #define EXTI_RPR1_RPIF10                    EXTI_RPR1_RPIF10_Msk                    /*!< Rising Pending Interrupt Flag on line 10 */
11172 #define EXTI_RPR1_RPIF11_Pos                (11U)
11173 #define EXTI_RPR1_RPIF11_Msk                (0x1UL << EXTI_RPR1_RPIF11_Pos)         /*!< 0x00000800 */
11174 #define EXTI_RPR1_RPIF11                    EXTI_RPR1_RPIF11_Msk                    /*!< Rising Pending Interrupt Flag on line 11 */
11175 #define EXTI_RPR1_RPIF12_Pos                (12U)
11176 #define EXTI_RPR1_RPIF12_Msk                (0x1UL << EXTI_RPR1_RPIF12_Pos)         /*!< 0x00001000 */
11177 #define EXTI_RPR1_RPIF12                    EXTI_RPR1_RPIF12_Msk                    /*!< Rising Pending Interrupt Flag on line 12 */
11178 #define EXTI_RPR1_RPIF13_Pos                (13U)
11179 #define EXTI_RPR1_RPIF13_Msk                (0x1UL << EXTI_RPR1_RPIF13_Pos)         /*!< 0x00002000 */
11180 #define EXTI_RPR1_RPIF13                    EXTI_RPR1_RPIF13_Msk                    /*!< Rising Pending Interrupt Flag on line 13 */
11181 #define EXTI_RPR1_RPIF14_Pos                (14U)
11182 #define EXTI_RPR1_RPIF14_Msk                (0x1UL << EXTI_RPR1_RPIF14_Pos)         /*!< 0x00004000 */
11183 #define EXTI_RPR1_RPIF14                    EXTI_RPR1_RPIF14_Msk                    /*!< Rising Pending Interrupt Flag on line 14 */
11184 #define EXTI_RPR1_RPIF15_Pos                (15U)
11185 #define EXTI_RPR1_RPIF15_Msk                (0x1UL << EXTI_RPR1_RPIF15_Pos)         /*!< 0x00008000 */
11186 #define EXTI_RPR1_RPIF15                    EXTI_RPR1_RPIF15_Msk                    /*!< Rising Pending Interrupt Flag on line 15 */
11187 #define EXTI_RPR1_RPIF16_Pos                (16U)
11188 #define EXTI_RPR1_RPIF16_Msk                (0x1UL << EXTI_RPR1_RPIF16_Pos)         /*!< 0x00010000 */
11189 #define EXTI_RPR1_RPIF16                    EXTI_RPR1_RPIF16_Msk                    /*!< Rising Pending Interrupt Flag on line 16 */
11190 #define EXTI_RPR1_RPIF17_Pos                (17U)
11191 #define EXTI_RPR1_RPIF17_Msk                (0x1UL << EXTI_RPR1_RPIF17_Pos)         /*!< 0x00020000 */
11192 #define EXTI_RPR1_RPIF17                    EXTI_RPR1_RPIF17_Msk                    /*!< Rising Pending Interrupt Flag on line 17 */
11193 #define EXTI_RPR1_RPIF18_Pos                (18U)
11194 #define EXTI_RPR1_RPIF18_Msk                (0x1UL << EXTI_RPR1_RPIF18_Pos)         /*!< 0x00040000 */
11195 #define EXTI_RPR1_RPIF18                    EXTI_RPR1_RPIF18_Msk                    /*!< Rising Pending Interrupt Flag on line 18 */
11196 #define EXTI_RPR1_RPIF19_Pos                (19U)
11197 #define EXTI_RPR1_RPIF19_Msk                (0x1UL << EXTI_RPR1_RPIF19_Pos)         /*!< 0x00080000 */
11198 #define EXTI_RPR1_RPIF19                    EXTI_RPR1_RPIF19_Msk                    /*!< Rising Pending Interrupt Flag on line 19 */
11199 #define EXTI_RPR1_RPIF20_Pos                (20U)
11200 #define EXTI_RPR1_RPIF20_Msk                (0x1UL << EXTI_RPR1_RPIF20_Pos)         /*!< 0x00100000 */
11201 #define EXTI_RPR1_RPIF20                    EXTI_RPR1_RPIF20_Msk                    /*!< Rising Pending Interrupt Flag on line 20 */
11202 #define EXTI_RPR1_RPIF21_Pos                (21U)
11203 #define EXTI_RPR1_RPIF21_Msk                (0x1UL << EXTI_RPR1_RPIF21_Pos)         /*!< 0x00200000 */
11204 #define EXTI_RPR1_RPIF21                    EXTI_RPR1_RPIF21_Msk                    /*!< Rising Pending Interrupt Flag on line 21 */
11205 #define EXTI_RPR1_RPIF22_Pos                (22U)
11206 #define EXTI_RPR1_RPIF22_Msk                (0x1UL << EXTI_RPR1_RPIF22_Pos)         /*!< 0x00400000 */
11207 #define EXTI_RPR1_RPIF22                    EXTI_RPR1_RPIF22_Msk                    /*!< Rising Pending Interrupt Flag on line 22 */
11208 #define EXTI_RPR1_RPIF23_Pos                (23U)
11209 #define EXTI_RPR1_RPIF23_Msk                (0x1UL << EXTI_RPR1_RPIF23_Pos)         /*!< 0x00800000 */
11210 #define EXTI_RPR1_RPIF23                    EXTI_RPR1_RPIF23_Msk                    /*!< Rising Pending Interrupt Flag on line 23 */
11211 #define EXTI_RPR1_RPIF24_Pos                (24U)
11212 #define EXTI_RPR1_RPIF24_Msk                (0x1UL << EXTI_RPR1_RPIF24_Pos)         /*!< 0x01000000 */
11213 #define EXTI_RPR1_RPIF24                    EXTI_RPR1_RPIF24_Msk                    /*!< Rising Pending Interrupt Flag on line 24 */
11214 #define EXTI_RPR1_RPIF25_Pos                (25U)
11215 #define EXTI_RPR1_RPIF25_Msk                (0x1UL << EXTI_RPR1_RPIF25_Pos)         /*!< 0x02000000 */
11216 #define EXTI_RPR1_RPIF25                    EXTI_RPR1_RPIF25_Msk                    /*!< Rising Pending Interrupt Flag on line 25 */
11217 
11218 /*******************  Bit definition for EXTI_FPR1 register  ******************/
11219 #define EXTI_FPR1_FPIF0_Pos                 (0U)
11220 #define EXTI_FPR1_FPIF0_Msk                 (0x1UL << EXTI_FPR1_FPIF0_Pos)          /*!< 0x00000001 */
11221 #define EXTI_FPR1_FPIF0                     EXTI_FPR1_FPIF0_Msk                     /*!< Falling Pending Interrupt Flag on line 0 */
11222 #define EXTI_FPR1_FPIF1_Pos                 (1U)
11223 #define EXTI_FPR1_FPIF1_Msk                 (0x1UL << EXTI_FPR1_FPIF1_Pos)          /*!< 0x00000002 */
11224 #define EXTI_FPR1_FPIF1                     EXTI_FPR1_FPIF1_Msk                     /*!< Falling Pending Interrupt Flag on line 1 */
11225 #define EXTI_FPR1_FPIF2_Pos                 (2U)
11226 #define EXTI_FPR1_FPIF2_Msk                 (0x1UL << EXTI_FPR1_FPIF2_Pos)          /*!< 0x00000004 */
11227 #define EXTI_FPR1_FPIF2                     EXTI_FPR1_FPIF2_Msk                     /*!< Falling Pending Interrupt Flag on line 2 */
11228 #define EXTI_FPR1_FPIF3_Pos                 (3U)
11229 #define EXTI_FPR1_FPIF3_Msk                 (0x1UL << EXTI_FPR1_FPIF3_Pos)          /*!< 0x00000008 */
11230 #define EXTI_FPR1_FPIF3                     EXTI_FPR1_FPIF3_Msk                     /*!< Falling Pending Interrupt Flag on line 3 */
11231 #define EXTI_FPR1_FPIF4_Pos                 (4U)
11232 #define EXTI_FPR1_FPIF4_Msk                 (0x1UL << EXTI_FPR1_FPIF4_Pos)          /*!< 0x00000010 */
11233 #define EXTI_FPR1_FPIF4                     EXTI_FPR1_FPIF4_Msk                     /*!< Falling Pending Interrupt Flag on line 4 */
11234 #define EXTI_FPR1_FPIF5_Pos                 (5U)
11235 #define EXTI_FPR1_FPIF5_Msk                 (0x1UL << EXTI_FPR1_FPIF5_Pos)          /*!< 0x00000020 */
11236 #define EXTI_FPR1_FPIF5                     EXTI_FPR1_FPIF5_Msk                     /*!< Falling Pending Interrupt Flag on line 5 */
11237 #define EXTI_FPR1_FPIF6_Pos                 (6U)
11238 #define EXTI_FPR1_FPIF6_Msk                 (0x1UL << EXTI_FPR1_FPIF6_Pos)          /*!< 0x00000040 */
11239 #define EXTI_FPR1_FPIF6                     EXTI_FPR1_FPIF6_Msk                     /*!< Falling Pending Interrupt Flag on line 6 */
11240 #define EXTI_FPR1_FPIF7_Pos                 (7U)
11241 #define EXTI_FPR1_FPIF7_Msk                 (0x1UL << EXTI_FPR1_FPIF7_Pos)          /*!< 0x00000080 */
11242 #define EXTI_FPR1_FPIF7                     EXTI_FPR1_FPIF7_Msk                     /*!< Falling Pending Interrupt Flag on line 7 */
11243 #define EXTI_FPR1_FPIF8_Pos                 (8U)
11244 #define EXTI_FPR1_FPIF8_Msk                 (0x1UL << EXTI_FPR1_FPIF8_Pos)          /*!< 0x00000100 */
11245 #define EXTI_FPR1_FPIF8                     EXTI_FPR1_FPIF8_Msk                     /*!< Falling Pending Interrupt Flag on line 8 */
11246 #define EXTI_FPR1_FPIF9_Pos                 (9U)
11247 #define EXTI_FPR1_FPIF9_Msk                 (0x1UL << EXTI_FPR1_FPIF9_Pos)          /*!< 0x00000200 */
11248 #define EXTI_FPR1_FPIF9                     EXTI_FPR1_FPIF9_Msk                     /*!< Falling Pending Interrupt Flag on line 9 */
11249 #define EXTI_FPR1_FPIF10_Pos                (10U)
11250 #define EXTI_FPR1_FPIF10_Msk                (0x1UL << EXTI_FPR1_FPIF10_Pos)         /*!< 0x00000400 */
11251 #define EXTI_FPR1_FPIF10                    EXTI_FPR1_FPIF10_Msk                    /*!< Falling Pending Interrupt Flag on line 10 */
11252 #define EXTI_FPR1_FPIF11_Pos                (11U)
11253 #define EXTI_FPR1_FPIF11_Msk                (0x1UL << EXTI_FPR1_FPIF11_Pos)         /*!< 0x00000800 */
11254 #define EXTI_FPR1_FPIF11                    EXTI_FPR1_FPIF11_Msk                    /*!< Falling Pending Interrupt Flag on line 11 */
11255 #define EXTI_FPR1_FPIF12_Pos                (12U)
11256 #define EXTI_FPR1_FPIF12_Msk                (0x1UL << EXTI_FPR1_FPIF12_Pos)         /*!< 0x00001000 */
11257 #define EXTI_FPR1_FPIF12                    EXTI_FPR1_FPIF12_Msk                    /*!< Falling Pending Interrupt Flag on line 12 */
11258 #define EXTI_FPR1_FPIF13_Pos                (13U)
11259 #define EXTI_FPR1_FPIF13_Msk                (0x1UL << EXTI_FPR1_FPIF13_Pos)         /*!< 0x00002000 */
11260 #define EXTI_FPR1_FPIF13                    EXTI_FPR1_FPIF13_Msk                    /*!< Falling Pending Interrupt Flag on line 13 */
11261 #define EXTI_FPR1_FPIF14_Pos                (14U)
11262 #define EXTI_FPR1_FPIF14_Msk                (0x1UL << EXTI_FPR1_FPIF14_Pos)         /*!< 0x00004000 */
11263 #define EXTI_FPR1_FPIF14                    EXTI_FPR1_FPIF14_Msk                    /*!< Falling Pending Interrupt Flag on line 14 */
11264 #define EXTI_FPR1_FPIF15_Pos                (15U)
11265 #define EXTI_FPR1_FPIF15_Msk                (0x1UL << EXTI_FPR1_FPIF15_Pos)         /*!< 0x00008000 */
11266 #define EXTI_FPR1_FPIF15                    EXTI_FPR1_FPIF15_Msk                    /*!< Falling Pending Interrupt Flag on line 15 */
11267 #define EXTI_FPR1_FPIF16_Pos                (16U)
11268 #define EXTI_FPR1_FPIF16_Msk                (0x1UL << EXTI_FPR1_FPIF16_Pos)         /*!< 0x00010000 */
11269 #define EXTI_FPR1_FPIF16                    EXTI_FPR1_FPIF16_Msk                    /*!< Falling Pending Interrupt Flag on line 16 */
11270 #define EXTI_FPR1_FPIF17_Pos                (17U)
11271 #define EXTI_FPR1_FPIF17_Msk                (0x1UL << EXTI_FPR1_FPIF17_Pos)         /*!< 0x00020000 */
11272 #define EXTI_FPR1_FPIF17                    EXTI_FPR1_FPIF17_Msk                    /*!< Falling Pending Interrupt Flag on line 17 */
11273 #define EXTI_FPR1_FPIF18_Pos                (18U)
11274 #define EXTI_FPR1_FPIF18_Msk                (0x1UL << EXTI_FPR1_FPIF18_Pos)         /*!< 0x00040000 */
11275 #define EXTI_FPR1_FPIF18                    EXTI_FPR1_FPIF18_Msk                    /*!< Falling Pending Interrupt Flag on line 18 */
11276 #define EXTI_FPR1_FPIF19_Pos                (19U)
11277 #define EXTI_FPR1_FPIF19_Msk                (0x1UL << EXTI_FPR1_FPIF19_Pos)         /*!< 0x00080000 */
11278 #define EXTI_FPR1_FPIF19                    EXTI_FPR1_FPIF19_Msk                    /*!< Falling Pending Interrupt Flag on line 19 */
11279 #define EXTI_FPR1_FPIF20_Pos                (20U)
11280 #define EXTI_FPR1_FPIF20_Msk                (0x1UL << EXTI_FPR1_FPIF20_Pos)         /*!< 0x00100000 */
11281 #define EXTI_FPR1_FPIF20                    EXTI_FPR1_FPIF20_Msk                    /*!< Falling Pending Interrupt Flag on line 20 */
11282 #define EXTI_FPR1_FPIF21_Pos                (21U)
11283 #define EXTI_FPR1_FPIF21_Msk                (0x1UL << EXTI_FPR1_FPIF21_Pos)         /*!< 0x00200000 */
11284 #define EXTI_FPR1_FPIF21                    EXTI_FPR1_FPIF21_Msk                    /*!< Falling Pending Interrupt Flag on line 21 */
11285 #define EXTI_FPR1_FPIF22_Pos                (22U)
11286 #define EXTI_FPR1_FPIF22_Msk                (0x1UL << EXTI_FPR1_FPIF22_Pos)         /*!< 0x00400000 */
11287 #define EXTI_FPR1_FPIF22                    EXTI_FPR1_FPIF22_Msk                    /*!< Falling Pending Interrupt Flag on line 22 */
11288 #define EXTI_FPR1_FPIF23_Pos                (23U)
11289 #define EXTI_FPR1_FPIF23_Msk                (0x1UL << EXTI_FPR1_FPIF23_Pos)         /*!< 0x00800000 */
11290 #define EXTI_FPR1_FPIF23                    EXTI_FPR1_FPIF23_Msk                    /*!< Falling Pending Interrupt Flag on line 23 */
11291 #define EXTI_FPR1_FPIF24_Pos                (24U)
11292 #define EXTI_FPR1_FPIF24_Msk                (0x1UL << EXTI_FPR1_FPIF24_Pos)         /*!< 0x01000000 */
11293 #define EXTI_FPR1_FPIF24                    EXTI_FPR1_FPIF24_Msk                    /*!< Falling Pending Interrupt Flag on line 24 */
11294 #define EXTI_FPR1_FPIF25_Pos                (25U)
11295 #define EXTI_FPR1_FPIF25_Msk                (0x1UL << EXTI_FPR1_FPIF25_Pos)         /*!< 0x02000000 */
11296 #define EXTI_FPR1_FPIF25                    EXTI_FPR1_FPIF25_Msk                    /*!< Falling Pending Interrupt Flag on line 25 */
11297 
11298 /*******************  Bit definition for EXTI_SECCFGR1 register  ******************/
11299 #define EXTI_SECCFGR1_SEC0_Pos              (0U)
11300 #define EXTI_SECCFGR1_SEC0_Msk              (0x1UL << EXTI_SECCFGR1_SEC0_Pos)       /*!< 0x00000001 */
11301 #define EXTI_SECCFGR1_SEC0                  EXTI_SECCFGR1_SEC0_Msk                  /*!< Security enable on line 0 */
11302 #define EXTI_SECCFGR1_SEC1_Pos              (1U)
11303 #define EXTI_SECCFGR1_SEC1_Msk              (0x1UL << EXTI_SECCFGR1_SEC1_Pos)       /*!< 0x00000002 */
11304 #define EXTI_SECCFGR1_SEC1                  EXTI_SECCFGR1_SEC1_Msk                  /*!< Security enable on line 1 */
11305 #define EXTI_SECCFGR1_SEC2_Pos              (2U)
11306 #define EXTI_SECCFGR1_SEC2_Msk              (0x1UL << EXTI_SECCFGR1_SEC2_Pos)       /*!< 0x00000004 */
11307 #define EXTI_SECCFGR1_SEC2                  EXTI_SECCFGR1_SEC2_Msk                  /*!< Security enable on line 2 */
11308 #define EXTI_SECCFGR1_SEC3_Pos              (3U)
11309 #define EXTI_SECCFGR1_SEC3_Msk              (0x1UL << EXTI_SECCFGR1_SEC3_Pos)       /*!< 0x00000008 */
11310 #define EXTI_SECCFGR1_SEC3                  EXTI_SECCFGR1_SEC3_Msk                  /*!< Security enable on line 3 */
11311 #define EXTI_SECCFGR1_SEC4_Pos              (4U)
11312 #define EXTI_SECCFGR1_SEC4_Msk              (0x1UL << EXTI_SECCFGR1_SEC4_Pos)       /*!< 0x00000010 */
11313 #define EXTI_SECCFGR1_SEC4                  EXTI_SECCFGR1_SEC4_Msk                  /*!< Security enable on line 4 */
11314 #define EXTI_SECCFGR1_SEC5_Pos              (5U)
11315 #define EXTI_SECCFGR1_SEC5_Msk              (0x1UL << EXTI_SECCFGR1_SEC5_Pos)       /*!< 0x00000020 */
11316 #define EXTI_SECCFGR1_SEC5                  EXTI_SECCFGR1_SEC5_Msk                  /*!< Security enable on line 5 */
11317 #define EXTI_SECCFGR1_SEC6_Pos              (6U)
11318 #define EXTI_SECCFGR1_SEC6_Msk              (0x1UL << EXTI_SECCFGR1_SEC6_Pos)       /*!< 0x00000040 */
11319 #define EXTI_SECCFGR1_SEC6                  EXTI_SECCFGR1_SEC6_Msk                  /*!< Security enable on line 6 */
11320 #define EXTI_SECCFGR1_SEC7_Pos              (7U)
11321 #define EXTI_SECCFGR1_SEC7_Msk              (0x1UL << EXTI_SECCFGR1_SEC7_Pos)       /*!< 0x00000080 */
11322 #define EXTI_SECCFGR1_SEC7                  EXTI_SECCFGR1_SEC7_Msk                  /*!< Security enable on line 7 */
11323 #define EXTI_SECCFGR1_SEC8_Pos              (8U)
11324 #define EXTI_SECCFGR1_SEC8_Msk              (0x1UL << EXTI_SECCFGR1_SEC8_Pos)       /*!< 0x00000100 */
11325 #define EXTI_SECCFGR1_SEC8                  EXTI_SECCFGR1_SEC8_Msk                  /*!< Security enable on line 8 */
11326 #define EXTI_SECCFGR1_SEC9_Pos              (9U)
11327 #define EXTI_SECCFGR1_SEC9_Msk              (0x1UL << EXTI_SECCFGR1_SEC9_Pos)       /*!< 0x00000200 */
11328 #define EXTI_SECCFGR1_SEC9                  EXTI_SECCFGR1_SEC9_Msk                  /*!< Security enable on line 9 */
11329 #define EXTI_SECCFGR1_SEC10_Pos             (10U)
11330 #define EXTI_SECCFGR1_SEC10_Msk             (0x1UL << EXTI_SECCFGR1_SEC10_Pos)      /*!< 0x00000400 */
11331 #define EXTI_SECCFGR1_SEC10                 EXTI_SECCFGR1_SEC10_Msk                 /*!< Security enable on line 10 */
11332 #define EXTI_SECCFGR1_SEC11_Pos             (11U)
11333 #define EXTI_SECCFGR1_SEC11_Msk             (0x1UL << EXTI_SECCFGR1_SEC11_Pos)      /*!< 0x00000800 */
11334 #define EXTI_SECCFGR1_SEC11                 EXTI_SECCFGR1_SEC11_Msk                 /*!< Security enable on line 11 */
11335 #define EXTI_SECCFGR1_SEC12_Pos             (12U)
11336 #define EXTI_SECCFGR1_SEC12_Msk             (0x1UL << EXTI_SECCFGR1_SEC12_Pos)      /*!< 0x00001000 */
11337 #define EXTI_SECCFGR1_SEC12                 EXTI_SECCFGR1_SEC12_Msk                 /*!< Security enable on line 12 */
11338 #define EXTI_SECCFGR1_SEC13_Pos             (13U)
11339 #define EXTI_SECCFGR1_SEC13_Msk             (0x1UL << EXTI_SECCFGR1_SEC13_Pos)      /*!< 0x00002000 */
11340 #define EXTI_SECCFGR1_SEC13                 EXTI_SECCFGR1_SEC13_Msk                 /*!< Security enable on line 13 */
11341 #define EXTI_SECCFGR1_SEC14_Pos             (14U)
11342 #define EXTI_SECCFGR1_SEC14_Msk             (0x1UL << EXTI_SECCFGR1_SEC14_Pos)      /*!< 0x00004000 */
11343 #define EXTI_SECCFGR1_SEC14                 EXTI_SECCFGR1_SEC14_Msk                 /*!< Security enable on line 14 */
11344 #define EXTI_SECCFGR1_SEC15_Pos             (15U)
11345 #define EXTI_SECCFGR1_SEC15_Msk             (0x1UL << EXTI_SECCFGR1_SEC15_Pos)      /*!< 0x00008000 */
11346 #define EXTI_SECCFGR1_SEC15                 EXTI_SECCFGR1_SEC15_Msk                 /*!< Security enable on line 15 */
11347 #define EXTI_SECCFGR1_SEC16_Pos             (16U)
11348 #define EXTI_SECCFGR1_SEC16_Msk             (0x1UL << EXTI_SECCFGR1_SEC16_Pos)      /*!< 0x00010000 */
11349 #define EXTI_SECCFGR1_SEC16                 EXTI_SECCFGR1_SEC16_Msk                 /*!< Security enable on line 16 */
11350 #define EXTI_SECCFGR1_SEC17_Pos             (17U)
11351 #define EXTI_SECCFGR1_SEC17_Msk             (0x1UL << EXTI_SECCFGR1_SEC17_Pos)      /*!< 0x00020000 */
11352 #define EXTI_SECCFGR1_SEC17                 EXTI_SECCFGR1_SEC17_Msk                 /*!< Security enable on line 17 */
11353 #define EXTI_SECCFGR1_SEC18_Pos             (18U)
11354 #define EXTI_SECCFGR1_SEC18_Msk             (0x1UL << EXTI_SECCFGR1_SEC18_Pos)      /*!< 0x00040000 */
11355 #define EXTI_SECCFGR1_SEC18                 EXTI_SECCFGR1_SEC18_Msk                 /*!< Security enable on line 18 */
11356 #define EXTI_SECCFGR1_SEC19_Pos             (19U)
11357 #define EXTI_SECCFGR1_SEC19_Msk             (0x1UL << EXTI_SECCFGR1_SEC19_Pos)      /*!< 0x00080000 */
11358 #define EXTI_SECCFGR1_SEC19                 EXTI_SECCFGR1_SEC19_Msk                 /*!< Security enable on line 19 */
11359 #define EXTI_SECCFGR1_SEC20_Pos             (20U)
11360 #define EXTI_SECCFGR1_SEC20_Msk             (0x1UL << EXTI_SECCFGR1_SEC20_Pos)      /*!< 0x00100000 */
11361 #define EXTI_SECCFGR1_SEC20                 EXTI_SECCFGR1_SEC20_Msk                 /*!< Security enable on line 20 */
11362 #define EXTI_SECCFGR1_SEC21_Pos             (21U)
11363 #define EXTI_SECCFGR1_SEC21_Msk             (0x1UL << EXTI_SECCFGR1_SEC21_Pos)      /*!< 0x00200000 */
11364 #define EXTI_SECCFGR1_SEC21                 EXTI_SECCFGR1_SEC21_Msk                 /*!< Security enable on line 21 */
11365 #define EXTI_SECCFGR1_SEC22_Pos             (22U)
11366 #define EXTI_SECCFGR1_SEC22_Msk             (0x1UL << EXTI_SECCFGR1_SEC22_Pos)      /*!< 0x00400000 */
11367 #define EXTI_SECCFGR1_SEC22                 EXTI_SECCFGR1_SEC22_Msk                 /*!< Security enable on line 22 */
11368 #define EXTI_SECCFGR1_SEC23_Pos             (23U)
11369 #define EXTI_SECCFGR1_SEC23_Msk             (0x1UL << EXTI_SECCFGR1_SEC23_Pos)      /*!< 0x00800000 */
11370 #define EXTI_SECCFGR1_SEC23                 EXTI_SECCFGR1_SEC23_Msk                 /*!< Security enable on line 23 */
11371 #define EXTI_SECCFGR1_SEC24_Pos             (24U)
11372 #define EXTI_SECCFGR1_SEC24_Msk             (0x1UL << EXTI_SECCFGR1_SEC24_Pos)      /*!< 0x01000000 */
11373 #define EXTI_SECCFGR1_SEC24                 EXTI_SECCFGR1_SEC24_Msk                 /*!< Security enable on line 24 */
11374 #define EXTI_SECCFGR1_SEC25_Pos             (25U)
11375 #define EXTI_SECCFGR1_SEC25_Msk             (0x1UL << EXTI_SECCFGR1_SEC25_Pos)      /*!< 0x02000000 */
11376 #define EXTI_SECCFGR1_SEC25                 EXTI_SECCFGR1_SEC25_Msk                 /*!< Security enable on line 25 */
11377 
11378 /*******************  Bit definition for EXTI_PRIVCFGR1 register  ******************/
11379 #define EXTI_PRIVCFGR1_PRIV0_Pos             (0U)
11380 #define EXTI_PRIVCFGR1_PRIV0_Msk             (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos)      /*!< 0x00000001 */
11381 #define EXTI_PRIVCFGR1_PRIV0                 EXTI_PRIVCFGR1_PRIV0_Msk                 /*!< Privilege enable on line 0 */
11382 #define EXTI_PRIVCFGR1_PRIV1_Pos             (1U)
11383 #define EXTI_PRIVCFGR1_PRIV1_Msk             (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos)      /*!< 0x00000002 */
11384 #define EXTI_PRIVCFGR1_PRIV1                 EXTI_PRIVCFGR1_PRIV1_Msk                 /*!< Privilege enable on line 1 */
11385 #define EXTI_PRIVCFGR1_PRIV2_Pos             (2U)
11386 #define EXTI_PRIVCFGR1_PRIV2_Msk             (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos)      /*!< 0x00000004 */
11387 #define EXTI_PRIVCFGR1_PRIV2                 EXTI_PRIVCFGR1_PRIV2_Msk                 /*!< Privilege enable on line 2 */
11388 #define EXTI_PRIVCFGR1_PRIV3_Pos             (3U)
11389 #define EXTI_PRIVCFGR1_PRIV3_Msk             (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos)      /*!< 0x00000008 */
11390 #define EXTI_PRIVCFGR1_PRIV3                 EXTI_PRIVCFGR1_PRIV3_Msk                 /*!< Privilege enable on line 3 */
11391 #define EXTI_PRIVCFGR1_PRIV4_Pos             (4U)
11392 #define EXTI_PRIVCFGR1_PRIV4_Msk             (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos)      /*!< 0x00000010 */
11393 #define EXTI_PRIVCFGR1_PRIV4                 EXTI_PRIVCFGR1_PRIV4_Msk                 /*!< Privilege enable on line 4 */
11394 #define EXTI_PRIVCFGR1_PRIV5_Pos             (5U)
11395 #define EXTI_PRIVCFGR1_PRIV5_Msk             (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos)      /*!< 0x00000020 */
11396 #define EXTI_PRIVCFGR1_PRIV5                 EXTI_PRIVCFGR1_PRIV5_Msk                 /*!< Privilege enable on line 5 */
11397 #define EXTI_PRIVCFGR1_PRIV6_Pos             (6U)
11398 #define EXTI_PRIVCFGR1_PRIV6_Msk             (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos)      /*!< 0x00000040 */
11399 #define EXTI_PRIVCFGR1_PRIV6                 EXTI_PRIVCFGR1_PRIV6_Msk                 /*!< Privilege enable on line 6 */
11400 #define EXTI_PRIVCFGR1_PRIV7_Pos             (7U)
11401 #define EXTI_PRIVCFGR1_PRIV7_Msk             (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos)      /*!< 0x00000080 */
11402 #define EXTI_PRIVCFGR1_PRIV7                 EXTI_PRIVCFGR1_PRIV7_Msk                 /*!< Privilege enable on line 7 */
11403 #define EXTI_PRIVCFGR1_PRIV8_Pos             (8U)
11404 #define EXTI_PRIVCFGR1_PRIV8_Msk             (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos)      /*!< 0x00000100 */
11405 #define EXTI_PRIVCFGR1_PRIV8                 EXTI_PRIVCFGR1_PRIV8_Msk                 /*!< Privilege enable on line 8 */
11406 #define EXTI_PRIVCFGR1_PRIV9_Pos             (9U)
11407 #define EXTI_PRIVCFGR1_PRIV9_Msk             (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos)      /*!< 0x00000200 */
11408 #define EXTI_PRIVCFGR1_PRIV9                 EXTI_PRIVCFGR1_PRIV9_Msk                 /*!< Privilege enable on line 9 */
11409 #define EXTI_PRIVCFGR1_PRIV10_Pos            (10U)
11410 #define EXTI_PRIVCFGR1_PRIV10_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos)     /*!< 0x00000400 */
11411 #define EXTI_PRIVCFGR1_PRIV10                EXTI_PRIVCFGR1_PRIV10_Msk                /*!< Privilege enable on line 10 */
11412 #define EXTI_PRIVCFGR1_PRIV11_Pos            (11U)
11413 #define EXTI_PRIVCFGR1_PRIV11_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos)     /*!< 0x00000800 */
11414 #define EXTI_PRIVCFGR1_PRIV11                EXTI_PRIVCFGR1_PRIV11_Msk                /*!< Privilege enable on line 11 */
11415 #define EXTI_PRIVCFGR1_PRIV12_Pos            (12U)
11416 #define EXTI_PRIVCFGR1_PRIV12_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos)     /*!< 0x00001000 */
11417 #define EXTI_PRIVCFGR1_PRIV12                EXTI_PRIVCFGR1_PRIV12_Msk                /*!< Privilege enable on line 12 */
11418 #define EXTI_PRIVCFGR1_PRIV13_Pos            (13U)
11419 #define EXTI_PRIVCFGR1_PRIV13_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos)     /*!< 0x00002000 */
11420 #define EXTI_PRIVCFGR1_PRIV13                EXTI_PRIVCFGR1_PRIV13_Msk                /*!< Privilege enable on line 13 */
11421 #define EXTI_PRIVCFGR1_PRIV14_Pos            (14U)
11422 #define EXTI_PRIVCFGR1_PRIV14_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos)     /*!< 0x00004000 */
11423 #define EXTI_PRIVCFGR1_PRIV14                EXTI_PRIVCFGR1_PRIV14_Msk                /*!< Privilege enable on line 14 */
11424 #define EXTI_PRIVCFGR1_PRIV15_Pos            (15U)
11425 #define EXTI_PRIVCFGR1_PRIV15_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos)     /*!< 0x00008000 */
11426 #define EXTI_PRIVCFGR1_PRIV15                EXTI_PRIVCFGR1_PRIV15_Msk                /*!< Privilege enable on line 15 */
11427 #define EXTI_PRIVCFGR1_PRIV16_Pos            (16U)
11428 #define EXTI_PRIVCFGR1_PRIV16_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos)     /*!< 0x00010000 */
11429 #define EXTI_PRIVCFGR1_PRIV16                EXTI_PRIVCFGR1_PRIV16_Msk                /*!< Privilege enable on line 16 */
11430 #define EXTI_PRIVCFGR1_PRIV17_Pos            (17U)
11431 #define EXTI_PRIVCFGR1_PRIV17_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos)     /*!< 0x00020000 */
11432 #define EXTI_PRIVCFGR1_PRIV17                EXTI_PRIVCFGR1_PRIV17_Msk                /*!< Privilege enable on line 17 */
11433 #define EXTI_PRIVCFGR1_PRIV18_Pos            (18U)
11434 #define EXTI_PRIVCFGR1_PRIV18_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos)     /*!< 0x00040000 */
11435 #define EXTI_PRIVCFGR1_PRIV18                EXTI_PRIVCFGR1_PRIV18_Msk                /*!< Privilege enable on line 18 */
11436 #define EXTI_PRIVCFGR1_PRIV19_Pos            (19U)
11437 #define EXTI_PRIVCFGR1_PRIV19_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos)     /*!< 0x00080000 */
11438 #define EXTI_PRIVCFGR1_PRIV19                EXTI_PRIVCFGR1_PRIV19_Msk                /*!< Privilege enable on line 19 */
11439 #define EXTI_PRIVCFGR1_PRIV20_Pos            (20U)
11440 #define EXTI_PRIVCFGR1_PRIV20_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos)     /*!< 0x00100000 */
11441 #define EXTI_PRIVCFGR1_PRIV20                EXTI_PRIVCFGR1_PRIV20_Msk                /*!< Privilege enable on line 20 */
11442 #define EXTI_PRIVCFGR1_PRIV21_Pos            (21U)
11443 #define EXTI_PRIVCFGR1_PRIV21_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos)     /*!< 0x00200000 */
11444 #define EXTI_PRIVCFGR1_PRIV21                EXTI_PRIVCFGR1_PRIV21_Msk                /*!< Privilege enable on line 21 */
11445 #define EXTI_PRIVCFGR1_PRIV22_Pos            (22U)
11446 #define EXTI_PRIVCFGR1_PRIV22_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos)     /*!< 0x00400000 */
11447 #define EXTI_PRIVCFGR1_PRIV22                EXTI_PRIVCFGR1_PRIV22_Msk                /*!< Privilege enable on line 22 */
11448 #define EXTI_PRIVCFGR1_PRIV23_Pos            (23U)
11449 #define EXTI_PRIVCFGR1_PRIV23_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos)     /*!< 0x00800000 */
11450 #define EXTI_PRIVCFGR1_PRIV23                EXTI_PRIVCFGR1_PRIV23_Msk                /*!< Privilege enable on line 23 */
11451 #define EXTI_PRIVCFGR1_PRIV24_Pos            (24U)
11452 #define EXTI_PRIVCFGR1_PRIV24_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos)     /*!< 0x01000000 */
11453 #define EXTI_PRIVCFGR1_PRIV24                EXTI_PRIVCFGR1_PRIV24_Msk                /*!< Privilege enable on line 24 */
11454 #define EXTI_PRIVCFGR1_PRIV25_Pos            (25U)
11455 #define EXTI_PRIVCFGR1_PRIV25_Msk            (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos)     /*!< 0x02000000 */
11456 #define EXTI_PRIVCFGR1_PRIV25                EXTI_PRIVCFGR1_PRIV25_Msk                /*!< Privilege enable on line 25 */
11457 
11458 /*****************  Bit definition for EXTI_EXTICR1 register  **************/
11459 #define EXTI_EXTICR1_EXTI0_Pos              (0U)
11460 #define EXTI_EXTICR1_EXTI0_Msk              (0xFUL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000007 */
11461 #define EXTI_EXTICR1_EXTI0                  EXTI_EXTICR1_EXTI0_Msk                  /*!< EXTI 0 configuration */
11462 #define EXTI_EXTICR1_EXTI0_0                (0x1UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000001 */
11463 #define EXTI_EXTICR1_EXTI0_1                (0x2UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000002 */
11464 #define EXTI_EXTICR1_EXTI0_2                (0x4UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000004 */
11465 #define EXTI_EXTICR1_EXTI0_3                (0x8UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000008 */
11466 #define EXTI_EXTICR1_EXTI1_Pos              (8U)
11467 #define EXTI_EXTICR1_EXTI1_Msk              (0xFUL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000700 */
11468 #define EXTI_EXTICR1_EXTI1                  EXTI_EXTICR1_EXTI1_Msk                  /*!< EXTI 1 configuration */
11469 #define EXTI_EXTICR1_EXTI1_0                (0x1UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000100 */
11470 #define EXTI_EXTICR1_EXTI1_1                (0x2UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000200 */
11471 #define EXTI_EXTICR1_EXTI1_2                (0x4UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000400 */
11472 #define EXTI_EXTICR1_EXTI1_3                (0x8UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000800 */
11473 #define EXTI_EXTICR1_EXTI2_Pos              (16U)
11474 #define EXTI_EXTICR1_EXTI2_Msk              (0xFUL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00070000 */
11475 #define EXTI_EXTICR1_EXTI2                  EXTI_EXTICR1_EXTI2_Msk                  /*!< EXTI 2 configuration */
11476 #define EXTI_EXTICR1_EXTI2_0                (0x1UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00010000 */
11477 #define EXTI_EXTICR1_EXTI2_1                (0x2UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00020000 */
11478 #define EXTI_EXTICR1_EXTI2_2                (0x4UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00040000 */
11479 #define EXTI_EXTICR1_EXTI2_3                (0x8UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00080000 */
11480 #define EXTI_EXTICR1_EXTI3_Pos              (24U)
11481 #define EXTI_EXTICR1_EXTI3_Msk              (0xFUL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x07000000 */
11482 #define EXTI_EXTICR1_EXTI3                  EXTI_EXTICR1_EXTI3_Msk                  /*!< EXTI 3 configuration */
11483 #define EXTI_EXTICR1_EXTI3_0                (0x1UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x01000000 */
11484 #define EXTI_EXTICR1_EXTI3_1                (0x2UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x02000000 */
11485 #define EXTI_EXTICR1_EXTI3_2                (0x4UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x04000000 */
11486 #define EXTI_EXTICR1_EXTI3_3                (0x8UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x08000000 */
11487 
11488 /*****************  Bit definition for EXTI_EXTICR2 register  **************/
11489 #define EXTI_EXTICR2_EXTI4_Pos              (0U)
11490 #define EXTI_EXTICR2_EXTI4_Msk              (0xFUL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000007 */
11491 #define EXTI_EXTICR2_EXTI4                  EXTI_EXTICR2_EXTI4_Msk                  /*!< EXTI 4 configuration */
11492 #define EXTI_EXTICR2_EXTI4_0                (0x1UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000001 */
11493 #define EXTI_EXTICR2_EXTI4_1                (0x2UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000002 */
11494 #define EXTI_EXTICR2_EXTI4_2                (0x4UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000004 */
11495 #define EXTI_EXTICR2_EXTI4_3                (0x8UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000008 */
11496 #define EXTI_EXTICR2_EXTI5_Pos              (8U)
11497 #define EXTI_EXTICR2_EXTI5_Msk              (0xFUL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000700 */
11498 #define EXTI_EXTICR2_EXTI5                  EXTI_EXTICR2_EXTI5_Msk                  /*!< EXTI 5 configuration */
11499 #define EXTI_EXTICR2_EXTI5_0                (0x1UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000100 */
11500 #define EXTI_EXTICR2_EXTI5_1                (0x2UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000200 */
11501 #define EXTI_EXTICR2_EXTI5_2                (0x4UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000400 */
11502 #define EXTI_EXTICR2_EXTI5_3                (0x8UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000800 */
11503 #define EXTI_EXTICR2_EXTI6_Pos              (16U)
11504 #define EXTI_EXTICR2_EXTI6_Msk              (0xFUL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00070000 */
11505 #define EXTI_EXTICR2_EXTI6                  EXTI_EXTICR2_EXTI6_Msk                  /*!< EXTI 6 configuration */
11506 #define EXTI_EXTICR2_EXTI6_0                (0x1UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00010000 */
11507 #define EXTI_EXTICR2_EXTI6_1                (0x2UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00020000 */
11508 #define EXTI_EXTICR2_EXTI6_2                (0x4UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00040000 */
11509 #define EXTI_EXTICR2_EXTI6_3                (0x8UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00080000 */
11510 #define EXTI_EXTICR2_EXTI7_Pos              (24U)
11511 #define EXTI_EXTICR2_EXTI7_Msk              (0xFUL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x07000000 */
11512 #define EXTI_EXTICR2_EXTI7                  EXTI_EXTICR2_EXTI7_Msk                  /*!< EXTI 7 configuration */
11513 #define EXTI_EXTICR2_EXTI7_0                (0x1UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x01000000 */
11514 #define EXTI_EXTICR2_EXTI7_1                (0x2UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x02000000 */
11515 #define EXTI_EXTICR2_EXTI7_2                (0x4UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x04000000 */
11516 #define EXTI_EXTICR2_EXTI7_3                (0x8UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x08000000 */
11517 
11518 /*****************  Bit definition for EXTI_EXTICR3 register  **************/
11519 #define EXTI_EXTICR3_EXTI8_Pos              (0U)
11520 #define EXTI_EXTICR3_EXTI8_Msk              (0xFUL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000007 */
11521 #define EXTI_EXTICR3_EXTI8                  EXTI_EXTICR3_EXTI8_Msk                  /*!< EXTI 8 configuration */
11522 #define EXTI_EXTICR3_EXTI8_0                (0x1UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000001 */
11523 #define EXTI_EXTICR3_EXTI8_1                (0x2UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000002 */
11524 #define EXTI_EXTICR3_EXTI8_2                (0x4UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000004 */
11525 #define EXTI_EXTICR3_EXTI8_3                (0x8UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000008 */
11526 #define EXTI_EXTICR3_EXTI9_Pos              (8U)
11527 #define EXTI_EXTICR3_EXTI9_Msk              (0xFUL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000700 */
11528 #define EXTI_EXTICR3_EXTI9                  EXTI_EXTICR3_EXTI9_Msk                  /*!< EXTI 9 configuration */
11529 #define EXTI_EXTICR3_EXTI9_0                (0x1UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000100 */
11530 #define EXTI_EXTICR3_EXTI9_1                (0x2UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000200 */
11531 #define EXTI_EXTICR3_EXTI9_2                (0x4UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000400 */
11532 #define EXTI_EXTICR3_EXTI9_3                (0x8UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000800 */
11533 #define EXTI_EXTICR3_EXTI10_Pos             (16U)
11534 #define EXTI_EXTICR3_EXTI10_Msk             (0xFUL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00070000 */
11535 #define EXTI_EXTICR3_EXTI10                 EXTI_EXTICR3_EXTI10_Msk                 /*!< EXTI 10 configuration */
11536 #define EXTI_EXTICR3_EXTI10_0               (0x1UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00010000 */
11537 #define EXTI_EXTICR3_EXTI10_1               (0x2UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00020000 */
11538 #define EXTI_EXTICR3_EXTI10_2               (0x4UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00040000 */
11539 #define EXTI_EXTICR3_EXTI10_3               (0x8UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00080000 */
11540 #define EXTI_EXTICR3_EXTI11_Pos             (24U)
11541 #define EXTI_EXTICR3_EXTI11_Msk             (0xFUL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x07000000 */
11542 #define EXTI_EXTICR3_EXTI11                 EXTI_EXTICR3_EXTI11_Msk                 /*!< EXTI 11 configuration */
11543 #define EXTI_EXTICR3_EXTI11_0               (0x1UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x01000000 */
11544 #define EXTI_EXTICR3_EXTI11_1               (0x2UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x02000000 */
11545 #define EXTI_EXTICR3_EXTI11_2               (0x4UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x04000000 */
11546 #define EXTI_EXTICR3_EXTI11_3               (0x8UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x08000000 */
11547 
11548 /*****************  Bit definition for EXTI_EXTICR4 register  **************/
11549 #define EXTI_EXTICR4_EXTI12_Pos             (0U)
11550 #define EXTI_EXTICR4_EXTI12_Msk             (0xFUL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000007 */
11551 #define EXTI_EXTICR4_EXTI12                 EXTI_EXTICR4_EXTI12_Msk                 /*!< EXTI 12 configuration */
11552 #define EXTI_EXTICR4_EXTI12_0               (0x1UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000001 */
11553 #define EXTI_EXTICR4_EXTI12_1               (0x2UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000002 */
11554 #define EXTI_EXTICR4_EXTI12_2               (0x4UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000004 */
11555 #define EXTI_EXTICR4_EXTI12_3               (0x8UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000008 */
11556 #define EXTI_EXTICR4_EXTI13_Pos             (8U)
11557 #define EXTI_EXTICR4_EXTI13_Msk             (0xFUL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000700 */
11558 #define EXTI_EXTICR4_EXTI13                 EXTI_EXTICR4_EXTI13_Msk                 /*!< EXTI 13 configuration */
11559 #define EXTI_EXTICR4_EXTI13_0               (0x1UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000100 */
11560 #define EXTI_EXTICR4_EXTI13_1               (0x2UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000200 */
11561 #define EXTI_EXTICR4_EXTI13_2               (0x4UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000400 */
11562 #define EXTI_EXTICR4_EXTI13_3               (0x8UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000800 */
11563 #define EXTI_EXTICR4_EXTI14_Pos             (16U)
11564 #define EXTI_EXTICR4_EXTI14_Msk             (0xFUL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00070000 */
11565 #define EXTI_EXTICR4_EXTI14                 EXTI_EXTICR4_EXTI14_Msk                 /*!< EXTI 14 configuration */
11566 #define EXTI_EXTICR4_EXTI14_0               (0x1UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00010000 */
11567 #define EXTI_EXTICR4_EXTI14_1               (0x2UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00020000 */
11568 #define EXTI_EXTICR4_EXTI14_2               (0x4UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00040000 */
11569 #define EXTI_EXTICR4_EXTI14_3               (0x8UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00080000 */
11570 #define EXTI_EXTICR4_EXTI15_Pos             (24U)
11571 #define EXTI_EXTICR4_EXTI15_Msk             (0xFUL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x07000000 */
11572 #define EXTI_EXTICR4_EXTI15                 EXTI_EXTICR4_EXTI15_Msk                 /*!< EXTI 15 configuration */
11573 #define EXTI_EXTICR4_EXTI15_0               (0x1UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x01000000 */
11574 #define EXTI_EXTICR4_EXTI15_1               (0x2UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x02000000 */
11575 #define EXTI_EXTICR4_EXTI15_2               (0x4UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x04000000 */
11576 #define EXTI_EXTICR4_EXTI15_3               (0x8UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x08000000 */
11577 
11578 /*****************  Bit definition for EXTI_LOCKR register  **************/
11579 #define EXTI_LOCKR_LOCK_Pos                 (0U)
11580 #define EXTI_LOCKR_LOCK_Msk                 (0x1UL << EXTI_LOCKR_LOCK_Pos)          /*!< 0x00000001 */
11581 #define EXTI_LOCKR_LOCK                     EXTI_LOCKR_LOCK_Msk                     /*!< Global security and privilege configuration registers lock */
11582 
11583 /*******************  Bit definition for EXTI_IMR1 register  ******************/
11584 #define EXTI_IMR1_IM0_Pos                   (0U)
11585 #define EXTI_IMR1_IM0_Msk                   (0x1UL << EXTI_IMR1_IM0_Pos)            /*!< 0x00000001 */
11586 #define EXTI_IMR1_IM0                       EXTI_IMR1_IM0_Msk                       /*!< Interrupt Mask on line 0 */
11587 #define EXTI_IMR1_IM1_Pos                   (1U)
11588 #define EXTI_IMR1_IM1_Msk                   (0x1UL << EXTI_IMR1_IM1_Pos)            /*!< 0x00000002 */
11589 #define EXTI_IMR1_IM1                       EXTI_IMR1_IM1_Msk                       /*!< Interrupt Mask on line 1 */
11590 #define EXTI_IMR1_IM2_Pos                   (2U)
11591 #define EXTI_IMR1_IM2_Msk                   (0x1UL << EXTI_IMR1_IM2_Pos)            /*!< 0x00000004 */
11592 #define EXTI_IMR1_IM2                       EXTI_IMR1_IM2_Msk                       /*!< Interrupt Mask on line 2 */
11593 #define EXTI_IMR1_IM3_Pos                   (3U)
11594 #define EXTI_IMR1_IM3_Msk                   (0x1UL << EXTI_IMR1_IM3_Pos)            /*!< 0x00000008 */
11595 #define EXTI_IMR1_IM3                       EXTI_IMR1_IM3_Msk                       /*!< Interrupt Mask on line 3 */
11596 #define EXTI_IMR1_IM4_Pos                   (4U)
11597 #define EXTI_IMR1_IM4_Msk                   (0x1UL << EXTI_IMR1_IM4_Pos)            /*!< 0x00000010 */
11598 #define EXTI_IMR1_IM4                       EXTI_IMR1_IM4_Msk                       /*!< Interrupt Mask on line 4 */
11599 #define EXTI_IMR1_IM5_Pos                   (5U)
11600 #define EXTI_IMR1_IM5_Msk                   (0x1UL << EXTI_IMR1_IM5_Pos)            /*!< 0x00000020 */
11601 #define EXTI_IMR1_IM5                       EXTI_IMR1_IM5_Msk                       /*!< Interrupt Mask on line 5 */
11602 #define EXTI_IMR1_IM6_Pos                   (6U)
11603 #define EXTI_IMR1_IM6_Msk                   (0x1UL << EXTI_IMR1_IM6_Pos)            /*!< 0x00000040 */
11604 #define EXTI_IMR1_IM6                       EXTI_IMR1_IM6_Msk                       /*!< Interrupt Mask on line 6 */
11605 #define EXTI_IMR1_IM7_Pos                   (7U)
11606 #define EXTI_IMR1_IM7_Msk                   (0x1UL << EXTI_IMR1_IM7_Pos)            /*!< 0x00000080 */
11607 #define EXTI_IMR1_IM7                       EXTI_IMR1_IM7_Msk                       /*!< Interrupt Mask on line 7 */
11608 #define EXTI_IMR1_IM8_Pos                   (8U)
11609 #define EXTI_IMR1_IM8_Msk                   (0x1UL << EXTI_IMR1_IM8_Pos)            /*!< 0x00000100 */
11610 #define EXTI_IMR1_IM8                       EXTI_IMR1_IM8_Msk                       /*!< Interrupt Mask on line 8 */
11611 #define EXTI_IMR1_IM9_Pos                   (9U)
11612 #define EXTI_IMR1_IM9_Msk                   (0x1UL << EXTI_IMR1_IM9_Pos)            /*!< 0x00000200 */
11613 #define EXTI_IMR1_IM9                       EXTI_IMR1_IM9_Msk                       /*!< Interrupt Mask on line 9 */
11614 #define EXTI_IMR1_IM10_Pos                  (10U)
11615 #define EXTI_IMR1_IM10_Msk                  (0x1UL << EXTI_IMR1_IM10_Pos)           /*!< 0x00000400 */
11616 #define EXTI_IMR1_IM10                      EXTI_IMR1_IM10_Msk                      /*!< Interrupt Mask on line 10 */
11617 #define EXTI_IMR1_IM11_Pos                  (11U)
11618 #define EXTI_IMR1_IM11_Msk                  (0x1UL << EXTI_IMR1_IM11_Pos)           /*!< 0x00000800 */
11619 #define EXTI_IMR1_IM11                      EXTI_IMR1_IM11_Msk                      /*!< Interrupt Mask on line 11 */
11620 #define EXTI_IMR1_IM12_Pos                  (12U)
11621 #define EXTI_IMR1_IM12_Msk                  (0x1UL << EXTI_IMR1_IM12_Pos)           /*!< 0x00001000 */
11622 #define EXTI_IMR1_IM12                      EXTI_IMR1_IM12_Msk                      /*!< Interrupt Mask on line 12 */
11623 #define EXTI_IMR1_IM13_Pos                  (13U)
11624 #define EXTI_IMR1_IM13_Msk                  (0x1UL << EXTI_IMR1_IM13_Pos)           /*!< 0x00002000 */
11625 #define EXTI_IMR1_IM13                      EXTI_IMR1_IM13_Msk                      /*!< Interrupt Mask on line 13 */
11626 #define EXTI_IMR1_IM14_Pos                  (14U)
11627 #define EXTI_IMR1_IM14_Msk                  (0x1UL << EXTI_IMR1_IM14_Pos)           /*!< 0x00004000 */
11628 #define EXTI_IMR1_IM14                      EXTI_IMR1_IM14_Msk                      /*!< Interrupt Mask on line 14 */
11629 #define EXTI_IMR1_IM15_Pos                  (15U)
11630 #define EXTI_IMR1_IM15_Msk                  (0x1UL << EXTI_IMR1_IM15_Pos)           /*!< 0x00008000 */
11631 #define EXTI_IMR1_IM15                      EXTI_IMR1_IM15_Msk                      /*!< Interrupt Mask on line 15 */
11632 #define EXTI_IMR1_IM16_Pos                  (16U)
11633 #define EXTI_IMR1_IM16_Msk                  (0x1UL << EXTI_IMR1_IM16_Pos)           /*!< 0x00010000 */
11634 #define EXTI_IMR1_IM16                      EXTI_IMR1_IM16_Msk                      /*!< Interrupt Mask on line 16 */
11635 #define EXTI_IMR1_IM17_Pos                  (17U)
11636 #define EXTI_IMR1_IM17_Msk                  (0x1UL << EXTI_IMR1_IM17_Pos)           /*!< 0x00020000 */
11637 #define EXTI_IMR1_IM17                      EXTI_IMR1_IM17_Msk                      /*!< Interrupt Mask on line 17 */
11638 #define EXTI_IMR1_IM18_Pos                  (18U)
11639 #define EXTI_IMR1_IM18_Msk                  (0x1UL << EXTI_IMR1_IM18_Pos)           /*!< 0x00040000 */
11640 #define EXTI_IMR1_IM18                      EXTI_IMR1_IM18_Msk                      /*!< Interrupt Mask on line 18 */
11641 #define EXTI_IMR1_IM19_Pos                  (19U)
11642 #define EXTI_IMR1_IM19_Msk                  (0x1UL << EXTI_IMR1_IM19_Pos)           /*!< 0x00080000 */
11643 #define EXTI_IMR1_IM19                      EXTI_IMR1_IM19_Msk                      /*!< Interrupt Mask on line 19 */
11644 #define EXTI_IMR1_IM20_Pos                  (20U)
11645 #define EXTI_IMR1_IM20_Msk                  (0x1UL << EXTI_IMR1_IM20_Pos)           /*!< 0x00100000 */
11646 #define EXTI_IMR1_IM20                      EXTI_IMR1_IM20_Msk                      /*!< Interrupt Mask on line 20 */
11647 #define EXTI_IMR1_IM21_Pos                  (21U)
11648 #define EXTI_IMR1_IM21_Msk                  (0x1UL << EXTI_IMR1_IM21_Pos)           /*!< 0x00200000 */
11649 #define EXTI_IMR1_IM21                      EXTI_IMR1_IM21_Msk                      /*!< Interrupt Mask on line 21 */
11650 #define EXTI_IMR1_IM22_Pos                  (22U)
11651 #define EXTI_IMR1_IM22_Msk                  (0x1UL << EXTI_IMR1_IM22_Pos)           /*!< 0x00400000 */
11652 #define EXTI_IMR1_IM22                      EXTI_IMR1_IM22_Msk                      /*!< Interrupt Mask on line 22 */
11653 #define EXTI_IMR1_IM23_Pos                  (23U)
11654 #define EXTI_IMR1_IM23_Msk                  (0x1UL << EXTI_IMR1_IM23_Pos)           /*!< 0x00800000 */
11655 #define EXTI_IMR1_IM23                      EXTI_IMR1_IM23_Msk                      /*!< Interrupt Mask on line 23 */
11656 #define EXTI_IMR1_IM24_Pos                  (24U)
11657 #define EXTI_IMR1_IM24_Msk                  (0x1UL << EXTI_IMR1_IM24_Pos)           /*!< 0x01000000 */
11658 #define EXTI_IMR1_IM24                      EXTI_IMR1_IM24_Msk                      /*!< Interrupt Mask on line 24 */
11659 #define EXTI_IMR1_IM25_Pos                  (25U)
11660 #define EXTI_IMR1_IM25_Msk                  (0x1UL << EXTI_IMR1_IM25_Pos)           /*!< 0x02000000 */
11661 #define EXTI_IMR1_IM25                      EXTI_IMR1_IM25_Msk                      /*!< Interrupt Mask on line 25 */
11662 
11663 /*******************  Bit definition for EXTI_EMR1 register  ******************/
11664 #define EXTI_EMR1_EM0_Pos                   (0U)
11665 #define EXTI_EMR1_EM0_Msk                   (0x1UL << EXTI_EMR1_EM0_Pos)            /*!< 0x00000001 */
11666 #define EXTI_EMR1_EM0                       EXTI_EMR1_EM0_Msk                       /*!< Event Mask on line 0 */
11667 #define EXTI_EMR1_EM1_Pos                   (1U)
11668 #define EXTI_EMR1_EM1_Msk                   (0x1UL << EXTI_EMR1_EM1_Pos)            /*!< 0x00000002 */
11669 #define EXTI_EMR1_EM1                       EXTI_EMR1_EM1_Msk                       /*!< Event Mask on line 1 */
11670 #define EXTI_EMR1_EM2_Pos                   (2U)
11671 #define EXTI_EMR1_EM2_Msk                   (0x1UL << EXTI_EMR1_EM2_Pos)            /*!< 0x00000004 */
11672 #define EXTI_EMR1_EM2                       EXTI_EMR1_EM2_Msk                       /*!< Event Mask on line 2 */
11673 #define EXTI_EMR1_EM3_Pos                   (3U)
11674 #define EXTI_EMR1_EM3_Msk                   (0x1UL << EXTI_EMR1_EM3_Pos)            /*!< 0x00000008 */
11675 #define EXTI_EMR1_EM3                       EXTI_EMR1_EM3_Msk                       /*!< Event Mask on line 3 */
11676 #define EXTI_EMR1_EM4_Pos                   (4U)
11677 #define EXTI_EMR1_EM4_Msk                   (0x1UL << EXTI_EMR1_EM4_Pos)            /*!< 0x00000010 */
11678 #define EXTI_EMR1_EM4                       EXTI_EMR1_EM4_Msk                       /*!< Event Mask on line 4 */
11679 #define EXTI_EMR1_EM5_Pos                   (5U)
11680 #define EXTI_EMR1_EM5_Msk                   (0x1UL << EXTI_EMR1_EM5_Pos)            /*!< 0x00000020 */
11681 #define EXTI_EMR1_EM5                       EXTI_EMR1_EM5_Msk                       /*!< Event Mask on line 5 */
11682 #define EXTI_EMR1_EM6_Pos                   (6U)
11683 #define EXTI_EMR1_EM6_Msk                   (0x1UL << EXTI_EMR1_EM6_Pos)            /*!< 0x00000040 */
11684 #define EXTI_EMR1_EM6                       EXTI_EMR1_EM6_Msk                       /*!< Event Mask on line 6 */
11685 #define EXTI_EMR1_EM7_Pos                   (7U)
11686 #define EXTI_EMR1_EM7_Msk                   (0x1UL << EXTI_EMR1_EM7_Pos)            /*!< 0x00000080 */
11687 #define EXTI_EMR1_EM7                       EXTI_EMR1_EM7_Msk                       /*!< Event Mask on line 7 */
11688 #define EXTI_EMR1_EM8_Pos                   (8U)
11689 #define EXTI_EMR1_EM8_Msk                   (0x1UL << EXTI_EMR1_EM8_Pos)            /*!< 0x00000100 */
11690 #define EXTI_EMR1_EM8                       EXTI_EMR1_EM8_Msk                       /*!< Event Mask on line 8 */
11691 #define EXTI_EMR1_EM9_Pos                   (9U)
11692 #define EXTI_EMR1_EM9_Msk                   (0x1UL << EXTI_EMR1_EM9_Pos)            /*!< 0x00000200 */
11693 #define EXTI_EMR1_EM9                       EXTI_EMR1_EM9_Msk                       /*!< Event Mask on line 9 */
11694 #define EXTI_EMR1_EM10_Pos                  (10U)
11695 #define EXTI_EMR1_EM10_Msk                  (0x1UL << EXTI_EMR1_EM10_Pos)           /*!< 0x00000400 */
11696 #define EXTI_EMR1_EM10                      EXTI_EMR1_EM10_Msk                      /*!< Event Mask on line 10 */
11697 #define EXTI_EMR1_EM11_Pos                  (11U)
11698 #define EXTI_EMR1_EM11_Msk                  (0x1UL << EXTI_EMR1_EM11_Pos)           /*!< 0x00000800 */
11699 #define EXTI_EMR1_EM11                      EXTI_EMR1_EM11_Msk                      /*!< Event Mask on line 11 */
11700 #define EXTI_EMR1_EM12_Pos                  (12U)
11701 #define EXTI_EMR1_EM12_Msk                  (0x1UL << EXTI_EMR1_EM12_Pos)           /*!< 0x00001000 */
11702 #define EXTI_EMR1_EM12                      EXTI_EMR1_EM12_Msk                      /*!< Event Mask on line 12 */
11703 #define EXTI_EMR1_EM13_Pos                  (13U)
11704 #define EXTI_EMR1_EM13_Msk                  (0x1UL << EXTI_EMR1_EM13_Pos)           /*!< 0x00002000 */
11705 #define EXTI_EMR1_EM13                      EXTI_EMR1_EM13_Msk                      /*!< Event Mask on line 13 */
11706 #define EXTI_EMR1_EM14_Pos                  (14U)
11707 #define EXTI_EMR1_EM14_Msk                  (0x1UL << EXTI_EMR1_EM14_Pos)           /*!< 0x00004000 */
11708 #define EXTI_EMR1_EM14                      EXTI_EMR1_EM14_Msk                      /*!< Event Mask on line 14 */
11709 #define EXTI_EMR1_EM15_Pos                  (15U)
11710 #define EXTI_EMR1_EM15_Msk                  (0x1UL << EXTI_EMR1_EM15_Pos)           /*!< 0x00008000 */
11711 #define EXTI_EMR1_EM15                      EXTI_EMR1_EM15_Msk                      /*!< Event Mask on line 15 */
11712 #define EXTI_EMR1_EM16_Pos                  (16U)
11713 #define EXTI_EMR1_EM16_Msk                  (0x1UL << EXTI_EMR1_EM16_Pos)           /*!< 0x00010000 */
11714 #define EXTI_EMR1_EM16                      EXTI_EMR1_EM16_Msk                      /*!< Event Mask on line 16 */
11715 #define EXTI_EMR1_EM17_Pos                  (17U)
11716 #define EXTI_EMR1_EM17_Msk                  (0x1UL << EXTI_EMR1_EM17_Pos)           /*!< 0x00020000 */
11717 #define EXTI_EMR1_EM17                      EXTI_EMR1_EM17_Msk                      /*!< Event Mask on line 17 */
11718 #define EXTI_EMR1_EM18_Pos                  (18U)
11719 #define EXTI_EMR1_EM18_Msk                  (0x1UL << EXTI_EMR1_EM18_Pos)           /*!< 0x00040000 */
11720 #define EXTI_EMR1_EM18                      EXTI_EMR1_EM18_Msk                      /*!< Event Mask on line 18 */
11721 #define EXTI_EMR1_EM19_Pos                  (19U)
11722 #define EXTI_EMR1_EM19_Msk                  (0x1UL << EXTI_EMR1_EM19_Pos)           /*!< 0x00080000 */
11723 #define EXTI_EMR1_EM19                      EXTI_EMR1_EM19_Msk                      /*!< Event Mask on line 19 */
11724 #define EXTI_EMR1_EM20_Pos                  (20U)
11725 #define EXTI_EMR1_EM20_Msk                  (0x1UL << EXTI_EMR1_EM20_Pos)           /*!< 0x00100000 */
11726 #define EXTI_EMR1_EM20                      EXTI_EMR1_EM20_Msk                      /*!< Event Mask on line 20 */
11727 #define EXTI_EMR1_EM21_Pos                  (21U)
11728 #define EXTI_EMR1_EM21_Msk                  (0x1UL << EXTI_EMR1_EM21_Pos)           /*!< 0x00200000 */
11729 #define EXTI_EMR1_EM21                      EXTI_EMR1_EM21_Msk                      /*!< Event Mask on line 21 */
11730 #define EXTI_EMR1_EM22_Pos                  (22U)
11731 #define EXTI_EMR1_EM22_Msk                  (0x1UL << EXTI_EMR1_EM22_Pos)           /*!< 0x00400000 */
11732 #define EXTI_EMR1_EM22                      EXTI_EMR1_EM22_Msk                      /*!< Event Mask on line 22 */
11733 #define EXTI_EMR1_EM23_Pos                  (23U)
11734 #define EXTI_EMR1_EM23_Msk                  (0x1UL << EXTI_EMR1_EM23_Pos)           /*!< 0x00800000 */
11735 #define EXTI_EMR1_EM23                      EXTI_EMR1_EM23_Msk                      /*!< Event Mask on line 23 */
11736 #define EXTI_EMR1_EM24_Pos                  (24U)
11737 #define EXTI_EMR1_EM24_Msk                  (0x1UL << EXTI_EMR1_EM24_Pos)           /*!< 0x01000000 */
11738 #define EXTI_EMR1_EM24                      EXTI_EMR1_EM24_Msk                      /*!< Event Mask on line 24 */
11739 #define EXTI_EMR1_EM25_Pos                  (25U)
11740 #define EXTI_EMR1_EM25_Msk                  (0x1UL << EXTI_EMR1_EM25_Pos)           /*!< 0x02000000 */
11741 #define EXTI_EMR1_EM25                      EXTI_EMR1_EM25_Msk                      /*!< Event Mask on line 25 */
11742 
11743 /******************************************************************************/
11744 /*                                                                            */
11745 /*                 Flexible Datarate Controller Area Network                  */
11746 /*                                                                            */
11747 /******************************************************************************/
11748 /*!<FDCAN control and status registers */
11749 /*****************  Bit definition for FDCAN_CREL register  *******************/
11750 #define FDCAN_CREL_DAY_Pos                  (0U)
11751 #define FDCAN_CREL_DAY_Msk                  (0xFFUL << FDCAN_CREL_DAY_Pos)          /*!< 0x000000FF */
11752 #define FDCAN_CREL_DAY                      FDCAN_CREL_DAY_Msk                      /*!<Timestamp Day                           */
11753 #define FDCAN_CREL_MON_Pos                  (8U)
11754 #define FDCAN_CREL_MON_Msk                  (0xFFUL << FDCAN_CREL_MON_Pos)          /*!< 0x0000FF00 */
11755 #define FDCAN_CREL_MON                      FDCAN_CREL_MON_Msk                      /*!<Timestamp Month                         */
11756 #define FDCAN_CREL_YEAR_Pos                 (16U)
11757 #define FDCAN_CREL_YEAR_Msk                 (0xFUL << FDCAN_CREL_YEAR_Pos)          /*!< 0x000F0000 */
11758 #define FDCAN_CREL_YEAR                     FDCAN_CREL_YEAR_Msk                     /*!<Timestamp Year                          */
11759 #define FDCAN_CREL_SUBSTEP_Pos              (20U)
11760 #define FDCAN_CREL_SUBSTEP_Msk              (0xFUL << FDCAN_CREL_SUBSTEP_Pos)       /*!< 0x00F00000 */
11761 #define FDCAN_CREL_SUBSTEP                  FDCAN_CREL_SUBSTEP_Msk                  /*!<Sub-step of Core release                */
11762 #define FDCAN_CREL_STEP_Pos                 (24U)
11763 #define FDCAN_CREL_STEP_Msk                 (0xFUL << FDCAN_CREL_STEP_Pos)          /*!< 0x0F000000 */
11764 #define FDCAN_CREL_STEP                     FDCAN_CREL_STEP_Msk                     /*!<Step of Core release                    */
11765 #define FDCAN_CREL_REL_Pos                  (28U)
11766 #define FDCAN_CREL_REL_Msk                  (0xFUL << FDCAN_CREL_REL_Pos)           /*!< 0xF0000000 */
11767 #define FDCAN_CREL_REL                      FDCAN_CREL_REL_Msk                      /*!<Core release                            */
11768 
11769 /*****************  Bit definition for FDCAN_ENDN register  *******************/
11770 #define FDCAN_ENDN_ETV_Pos                  (0U)
11771 #define FDCAN_ENDN_ETV_Msk                  (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)    /*!< 0xFFFFFFFF */
11772 #define FDCAN_ENDN_ETV                      FDCAN_ENDN_ETV_Msk                      /*!<Endianness Test Value                    */
11773 
11774 /*****************  Bit definition for FDCAN_DBTP register  *******************/
11775 #define FDCAN_DBTP_DSJW_Pos                 (0U)
11776 #define FDCAN_DBTP_DSJW_Msk                 (0xFUL << FDCAN_DBTP_DSJW_Pos)          /*!< 0x0000000F */
11777 #define FDCAN_DBTP_DSJW                     FDCAN_DBTP_DSJW_Msk                     /*!<Synchronization Jump Width              */
11778 #define FDCAN_DBTP_DTSEG2_Pos               (4U)
11779 #define FDCAN_DBTP_DTSEG2_Msk               (0xFUL << FDCAN_DBTP_DTSEG2_Pos)        /*!< 0x000000F0 */
11780 #define FDCAN_DBTP_DTSEG2                   FDCAN_DBTP_DTSEG2_Msk                   /*!<Data time segment after sample point    */
11781 #define FDCAN_DBTP_DTSEG1_Pos               (8U)
11782 #define FDCAN_DBTP_DTSEG1_Msk               (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)       /*!< 0x00001F00 */
11783 #define FDCAN_DBTP_DTSEG1                   FDCAN_DBTP_DTSEG1_Msk                   /*!<Data time segment before sample point   */
11784 #define FDCAN_DBTP_DBRP_Pos                 (16U)
11785 #define FDCAN_DBTP_DBRP_Msk                 (0x1FUL << FDCAN_DBTP_DBRP_Pos)         /*!< 0x001F0000 */
11786 #define FDCAN_DBTP_DBRP                     FDCAN_DBTP_DBRP_Msk                     /*!<Data BIt Rate Prescaler                 */
11787 #define FDCAN_DBTP_TDC_Pos                  (23U)
11788 #define FDCAN_DBTP_TDC_Msk                  (0x1UL << FDCAN_DBTP_TDC_Pos)           /*!< 0x00800000 */
11789 #define FDCAN_DBTP_TDC                      FDCAN_DBTP_TDC_Msk                      /*!<Transceiver Delay Compensation          */
11790 
11791 /*****************  Bit definition for FDCAN_TEST register  *******************/
11792 #define FDCAN_TEST_LBCK_Pos                 (4U)
11793 #define FDCAN_TEST_LBCK_Msk                 (0x1UL << FDCAN_TEST_LBCK_Pos)          /*!< 0x00000010 */
11794 #define FDCAN_TEST_LBCK                     FDCAN_TEST_LBCK_Msk                     /*!<Loop Back mode                           */
11795 #define FDCAN_TEST_TX_Pos                   (5U)
11796 #define FDCAN_TEST_TX_Msk                   (0x3UL << FDCAN_TEST_TX_Pos)            /*!< 0x00000060 */
11797 #define FDCAN_TEST_TX                       FDCAN_TEST_TX_Msk                       /*!<Control of Transmit Pin                  */
11798 #define FDCAN_TEST_RX_Pos                   (7U)
11799 #define FDCAN_TEST_RX_Msk                   (0x1UL << FDCAN_TEST_RX_Pos)            /*!< 0x00000080 */
11800 #define FDCAN_TEST_RX                       FDCAN_TEST_RX_Msk                       /*!<Receive Pin                              */
11801 
11802 /*****************  Bit definition for FDCAN_RWD register  ********************/
11803 #define FDCAN_RWD_WDC_Pos                   (0U)
11804 #define FDCAN_RWD_WDC_Msk                   (0xFFUL << FDCAN_RWD_WDC_Pos)           /*!< 0x000000FF */
11805 #define FDCAN_RWD_WDC                       FDCAN_RWD_WDC_Msk                       /*!<Watchdog configuration                   */
11806 #define FDCAN_RWD_WDV_Pos                   (8U)
11807 #define FDCAN_RWD_WDV_Msk                   (0xFFUL << FDCAN_RWD_WDV_Pos)           /*!< 0x0000FF00 */
11808 #define FDCAN_RWD_WDV                       FDCAN_RWD_WDV_Msk                       /*!<Watchdog value                           */
11809 
11810 /*****************  Bit definition for FDCAN_CCCR register  ********************/
11811 #define FDCAN_CCCR_INIT_Pos                 (0U)
11812 #define FDCAN_CCCR_INIT_Msk                 (0x1UL << FDCAN_CCCR_INIT_Pos)          /*!< 0x00000001 */
11813 #define FDCAN_CCCR_INIT                     FDCAN_CCCR_INIT_Msk                     /*!<Initialization                           */
11814 #define FDCAN_CCCR_CCE_Pos                  (1U)
11815 #define FDCAN_CCCR_CCE_Msk                  (0x1UL << FDCAN_CCCR_CCE_Pos)           /*!< 0x00000002 */
11816 #define FDCAN_CCCR_CCE                      FDCAN_CCCR_CCE_Msk                      /*!<Configuration Change Enable              */
11817 #define FDCAN_CCCR_ASM_Pos                  (2U)
11818 #define FDCAN_CCCR_ASM_Msk                  (0x1UL << FDCAN_CCCR_ASM_Pos)           /*!< 0x00000004 */
11819 #define FDCAN_CCCR_ASM                      FDCAN_CCCR_ASM_Msk                      /*!<ASM Restricted Operation Mode            */
11820 #define FDCAN_CCCR_CSA_Pos                  (3U)
11821 #define FDCAN_CCCR_CSA_Msk                  (0x1UL << FDCAN_CCCR_CSA_Pos)           /*!< 0x00000008 */
11822 #define FDCAN_CCCR_CSA                      FDCAN_CCCR_CSA_Msk                      /*!<Clock Stop Acknowledge                   */
11823 #define FDCAN_CCCR_CSR_Pos                  (4U)
11824 #define FDCAN_CCCR_CSR_Msk                  (0x1UL << FDCAN_CCCR_CSR_Pos)           /*!< 0x00000010 */
11825 #define FDCAN_CCCR_CSR                      FDCAN_CCCR_CSR_Msk                      /*!<Clock Stop Request                       */
11826 #define FDCAN_CCCR_MON_Pos                  (5U)
11827 #define FDCAN_CCCR_MON_Msk                  (0x1UL << FDCAN_CCCR_MON_Pos)           /*!< 0x00000020 */
11828 #define FDCAN_CCCR_MON                      FDCAN_CCCR_MON_Msk                      /*!<Bus Monitoring Mode                      */
11829 #define FDCAN_CCCR_DAR_Pos                  (6U)
11830 #define FDCAN_CCCR_DAR_Msk                  (0x1UL << FDCAN_CCCR_DAR_Pos)           /*!< 0x00000040 */
11831 #define FDCAN_CCCR_DAR                      FDCAN_CCCR_DAR_Msk                      /*!<Disable Automatic Retransmission         */
11832 #define FDCAN_CCCR_TEST_Pos                 (7U)
11833 #define FDCAN_CCCR_TEST_Msk                 (0x1UL << FDCAN_CCCR_TEST_Pos)          /*!< 0x00000080 */
11834 #define FDCAN_CCCR_TEST                     FDCAN_CCCR_TEST_Msk                     /*!<Test Mode Enable                         */
11835 #define FDCAN_CCCR_FDOE_Pos                 (8U)
11836 #define FDCAN_CCCR_FDOE_Msk                 (0x1UL << FDCAN_CCCR_FDOE_Pos)          /*!< 0x00000100 */
11837 #define FDCAN_CCCR_FDOE                     FDCAN_CCCR_FDOE_Msk                     /*!<FD Operation Enable                      */
11838 #define FDCAN_CCCR_BRSE_Pos                 (9U)
11839 #define FDCAN_CCCR_BRSE_Msk                 (0x1UL << FDCAN_CCCR_BRSE_Pos)          /*!< 0x00000200 */
11840 #define FDCAN_CCCR_BRSE                     FDCAN_CCCR_BRSE_Msk                     /*!<FDCAN Bit Rate Switching                 */
11841 #define FDCAN_CCCR_PXHD_Pos                 (12U)
11842 #define FDCAN_CCCR_PXHD_Msk                 (0x1UL << FDCAN_CCCR_PXHD_Pos)          /*!< 0x00001000 */
11843 #define FDCAN_CCCR_PXHD                     FDCAN_CCCR_PXHD_Msk                     /*!<Protocol Exception Handling Disable      */
11844 #define FDCAN_CCCR_EFBI_Pos                 (13U)
11845 #define FDCAN_CCCR_EFBI_Msk                 (0x1UL << FDCAN_CCCR_EFBI_Pos)          /*!< 0x00002000 */
11846 #define FDCAN_CCCR_EFBI                     FDCAN_CCCR_EFBI_Msk                     /*!<Edge Filtering during Bus Integration    */
11847 #define FDCAN_CCCR_TXP_Pos                  (14U)
11848 #define FDCAN_CCCR_TXP_Msk                  (0x1UL << FDCAN_CCCR_TXP_Pos)           /*!< 0x00004000 */
11849 #define FDCAN_CCCR_TXP                      FDCAN_CCCR_TXP_Msk                      /*!<Two CAN bit times Pause                  */
11850 #define FDCAN_CCCR_NISO_Pos                 (15U)
11851 #define FDCAN_CCCR_NISO_Msk                 (0x1UL << FDCAN_CCCR_NISO_Pos)          /*!< 0x00008000 */
11852 #define FDCAN_CCCR_NISO                     FDCAN_CCCR_NISO_Msk                     /*!<Non ISO Operation                        */
11853 
11854 /*****************  Bit definition for FDCAN_NBTP register  ******************* */
11855 #define FDCAN_NBTP_NTSEG2_Pos               (0U)
11856 #define FDCAN_NBTP_NTSEG2_Msk               (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)       /*!< 0x0000007F */
11857 #define FDCAN_NBTP_NTSEG2                   FDCAN_NBTP_NTSEG2_Msk                   /*!<Nominal Time segment after sample point  */
11858 #define FDCAN_NBTP_NTSEG1_Pos               (8U)
11859 #define FDCAN_NBTP_NTSEG1_Msk               (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)       /*!< 0x0000FF00 */
11860 #define FDCAN_NBTP_NTSEG1                   FDCAN_NBTP_NTSEG1_Msk                   /*!<Nominal Time segment before sample point */
11861 #define FDCAN_NBTP_NBRP_Pos                 (16U)
11862 #define FDCAN_NBTP_NBRP_Msk                 (0x1FFUL << FDCAN_NBTP_NBRP_Pos)        /*!< 0x01FF0000 */
11863 #define FDCAN_NBTP_NBRP                     FDCAN_NBTP_NBRP_Msk                     /*!<Bit Rate Prescaler                       */
11864 #define FDCAN_NBTP_NSJW_Pos                 (25U)
11865 #define FDCAN_NBTP_NSJW_Msk                 (0x7FUL << FDCAN_NBTP_NSJW_Pos)         /*!< 0xFE000000 */
11866 #define FDCAN_NBTP_NSJW                     FDCAN_NBTP_NSJW_Msk                     /*!<Nominal (Re)Synchronization Jump Width   */
11867 
11868 /*****************  Bit definition for FDCAN_TSCC register  ********************/
11869 #define FDCAN_TSCC_TSS_Pos                  (0U)
11870 #define FDCAN_TSCC_TSS_Msk                  (0x3UL << FDCAN_TSCC_TSS_Pos)           /*!< 0x00000003 */
11871 #define FDCAN_TSCC_TSS                      FDCAN_TSCC_TSS_Msk                      /*!<Timestamp Select                         */
11872 #define FDCAN_TSCC_TCP_Pos                  (16U)
11873 #define FDCAN_TSCC_TCP_Msk                  (0xFUL << FDCAN_TSCC_TCP_Pos)           /*!< 0x000F0000 */
11874 #define FDCAN_TSCC_TCP                      FDCAN_TSCC_TCP_Msk                      /*!<Timestamp Counter Prescaler              */
11875 
11876 /*****************  Bit definition for FDCAN_TSCV register  ********************/
11877 #define FDCAN_TSCV_TSC_Pos                  (0U)
11878 #define FDCAN_TSCV_TSC_Msk                  (0xFFFFUL << FDCAN_TSCV_TSC_Pos)        /*!< 0x0000FFFF */
11879 #define FDCAN_TSCV_TSC                      FDCAN_TSCV_TSC_Msk                      /*!<Timestamp Counter                        */
11880 
11881 /*****************  Bit definition for FDCAN_TOCC register  ********************/
11882 #define FDCAN_TOCC_ETOC_Pos                 (0U)
11883 #define FDCAN_TOCC_ETOC_Msk                 (0x1UL << FDCAN_TOCC_ETOC_Pos)          /*!< 0x00000001 */
11884 #define FDCAN_TOCC_ETOC                     FDCAN_TOCC_ETOC_Msk                     /*!<Enable Timeout Counter                   */
11885 #define FDCAN_TOCC_TOS_Pos                  (1U)
11886 #define FDCAN_TOCC_TOS_Msk                  (0x3UL << FDCAN_TOCC_TOS_Pos)           /*!< 0x00000006 */
11887 #define FDCAN_TOCC_TOS                      FDCAN_TOCC_TOS_Msk                      /*!<Timeout Select                           */
11888 #define FDCAN_TOCC_TOP_Pos                  (16U)
11889 #define FDCAN_TOCC_TOP_Msk                  (0xFFFFUL << FDCAN_TOCC_TOP_Pos)        /*!< 0xFFFF0000 */
11890 #define FDCAN_TOCC_TOP                      FDCAN_TOCC_TOP_Msk                      /*!<Timeout Period                           */
11891 
11892 /*****************  Bit definition for FDCAN_TOCV register  ******************* */
11893 #define FDCAN_TOCV_TOC_Pos                  (0U)
11894 #define FDCAN_TOCV_TOC_Msk                  (0xFFFFUL << FDCAN_TOCV_TOC_Pos)        /*!< 0x0000FFFF */
11895 #define FDCAN_TOCV_TOC                      FDCAN_TOCV_TOC_Msk                      /*!<Timeout Counter                          */
11896 
11897 /*****************  Bit definition for FDCAN_ECR register  ******************** */
11898 #define FDCAN_ECR_TEC_Pos                   (0U)
11899 #define FDCAN_ECR_TEC_Msk                   (0xFFUL << FDCAN_ECR_TEC_Pos)           /*!< 0x000000FF */
11900 #define FDCAN_ECR_TEC                       FDCAN_ECR_TEC_Msk                       /*!<Transmit Error Counter                   */
11901 #define FDCAN_ECR_REC_Pos                   (8U)
11902 #define FDCAN_ECR_REC_Msk                   (0x7FUL << FDCAN_ECR_REC_Pos)           /*!< 0x00007F00 */
11903 #define FDCAN_ECR_REC                       FDCAN_ECR_REC_Msk                       /*!<Receive Error Counter                    */
11904 #define FDCAN_ECR_RP_Pos                    (15U)
11905 #define FDCAN_ECR_RP_Msk                    (0x1UL << FDCAN_ECR_RP_Pos)             /*!< 0x00008000 */
11906 #define FDCAN_ECR_RP                        FDCAN_ECR_RP_Msk                        /*!<Receive Error Passive                    */
11907 #define FDCAN_ECR_CEL_Pos                   (16U)
11908 #define FDCAN_ECR_CEL_Msk                   (0xFFUL << FDCAN_ECR_CEL_Pos)           /*!< 0x00FF0000 */
11909 #define FDCAN_ECR_CEL                       FDCAN_ECR_CEL_Msk                       /*!<CAN Error Logging                        */
11910 
11911 /*****************  Bit definition for FDCAN_PSR register  ******************** */
11912 #define FDCAN_PSR_LEC_Pos                   (0U)
11913 #define FDCAN_PSR_LEC_Msk                   (0x7UL << FDCAN_PSR_LEC_Pos)            /*!< 0x00000007 */
11914 #define FDCAN_PSR_LEC                       FDCAN_PSR_LEC_Msk                       /*!<Last Error Code                          */
11915 #define FDCAN_PSR_ACT_Pos                   (3U)
11916 #define FDCAN_PSR_ACT_Msk                   (0x3UL << FDCAN_PSR_ACT_Pos)            /*!< 0x00000018 */
11917 #define FDCAN_PSR_ACT                       FDCAN_PSR_ACT_Msk                       /*!<Activity                                 */
11918 #define FDCAN_PSR_EP_Pos                    (5U)
11919 #define FDCAN_PSR_EP_Msk                    (0x1UL << FDCAN_PSR_EP_Pos)             /*!< 0x00000020 */
11920 #define FDCAN_PSR_EP                        FDCAN_PSR_EP_Msk                        /*!<Error Passive                            */
11921 #define FDCAN_PSR_EW_Pos                    (6U)
11922 #define FDCAN_PSR_EW_Msk                    (0x1UL << FDCAN_PSR_EW_Pos)             /*!< 0x00000040 */
11923 #define FDCAN_PSR_EW                        FDCAN_PSR_EW_Msk                        /*!<Warning Status                           */
11924 #define FDCAN_PSR_BO_Pos                    (7U)
11925 #define FDCAN_PSR_BO_Msk                    (0x1UL << FDCAN_PSR_BO_Pos)             /*!< 0x00000080 */
11926 #define FDCAN_PSR_BO                        FDCAN_PSR_BO_Msk                        /*!<Bus_Off Status                           */
11927 #define FDCAN_PSR_DLEC_Pos                  (8U)
11928 #define FDCAN_PSR_DLEC_Msk                  (0x7UL << FDCAN_PSR_DLEC_Pos)           /*!< 0x00000700 */
11929 #define FDCAN_PSR_DLEC                      FDCAN_PSR_DLEC_Msk                      /*!<Data Last Error Code                     */
11930 #define FDCAN_PSR_RESI_Pos                  (11U)
11931 #define FDCAN_PSR_RESI_Msk                  (0x1UL << FDCAN_PSR_RESI_Pos)           /*!< 0x00000800 */
11932 #define FDCAN_PSR_RESI                      FDCAN_PSR_RESI_Msk                      /*!<ESI flag of last received FDCAN Message  */
11933 #define FDCAN_PSR_RBRS_Pos                  (12U)
11934 #define FDCAN_PSR_RBRS_Msk                  (0x1UL << FDCAN_PSR_RBRS_Pos)           /*!< 0x00001000 */
11935 #define FDCAN_PSR_RBRS                      FDCAN_PSR_RBRS_Msk                      /*!<BRS flag of last received FDCAN Message  */
11936 #define FDCAN_PSR_REDL_Pos                  (13U)
11937 #define FDCAN_PSR_REDL_Msk                  (0x1UL << FDCAN_PSR_REDL_Pos)           /*!< 0x00002000 */
11938 #define FDCAN_PSR_REDL                      FDCAN_PSR_REDL_Msk                      /*!<Received FDCAN Message                   */
11939 #define FDCAN_PSR_PXE_Pos                   (14U)
11940 #define FDCAN_PSR_PXE_Msk                   (0x1UL << FDCAN_PSR_PXE_Pos)            /*!< 0x00004000 */
11941 #define FDCAN_PSR_PXE                       FDCAN_PSR_PXE_Msk                       /*!<Protocol Exception Event                 */
11942 #define FDCAN_PSR_TDCV_Pos                  (16U)
11943 #define FDCAN_PSR_TDCV_Msk                  (0x7FUL << FDCAN_PSR_TDCV_Pos)          /*!< 0x007F0000 */
11944 #define FDCAN_PSR_TDCV                      FDCAN_PSR_TDCV_Msk                      /*!<Transmitter Delay Compensation Value     */
11945 
11946 /*****************  Bit definition for FDCAN_TDCR register  ******************* */
11947 #define FDCAN_TDCR_TDCF_Pos                 (0U)
11948 #define FDCAN_TDCR_TDCF_Msk                 (0x7FUL << FDCAN_TDCR_TDCF_Pos)         /*!< 0x0000007F */
11949 #define FDCAN_TDCR_TDCF                     FDCAN_TDCR_TDCF_Msk                     /*!<Transmitter Delay Compensation Filter    */
11950 #define FDCAN_TDCR_TDCO_Pos                 (8U)
11951 #define FDCAN_TDCR_TDCO_Msk                 (0x7FUL << FDCAN_TDCR_TDCO_Pos)         /*!< 0x00007F00 */
11952 #define FDCAN_TDCR_TDCO                     FDCAN_TDCR_TDCO_Msk                     /*!<Transmitter Delay Compensation Offset    */
11953 
11954 /*****************  Bit definition for FDCAN_IR register  ********************* */
11955 #define FDCAN_IR_RF0N_Pos                   (0U)
11956 #define FDCAN_IR_RF0N_Msk                   (0x1UL << FDCAN_IR_RF0N_Pos)            /*!< 0x00000001 */
11957 #define FDCAN_IR_RF0N                       FDCAN_IR_RF0N_Msk                       /*!<Rx FIFO 0 New Message                    */
11958 #define FDCAN_IR_RF0F_Pos                   (1U)
11959 #define FDCAN_IR_RF0F_Msk                   (0x1UL << FDCAN_IR_RF0F_Pos)            /*!< 0x00000002 */
11960 #define FDCAN_IR_RF0F                       FDCAN_IR_RF0F_Msk                       /*!<Rx FIFO 0 Full                           */
11961 #define FDCAN_IR_RF0L_Pos                   (2U)
11962 #define FDCAN_IR_RF0L_Msk                   (0x1UL << FDCAN_IR_RF0L_Pos)            /*!< 0x00000004 */
11963 #define FDCAN_IR_RF0L                       FDCAN_IR_RF0L_Msk                       /*!<Rx FIFO 0 Message Lost                   */
11964 #define FDCAN_IR_RF1N_Pos                   (3U)
11965 #define FDCAN_IR_RF1N_Msk                   (0x1UL << FDCAN_IR_RF1N_Pos)            /*!< 0x00000008 */
11966 #define FDCAN_IR_RF1N                       FDCAN_IR_RF1N_Msk                       /*!<Rx FIFO 1 New Message                    */
11967 #define FDCAN_IR_RF1F_Pos                   (4U)
11968 #define FDCAN_IR_RF1F_Msk                   (0x1UL << FDCAN_IR_RF1F_Pos)            /*!< 0x00000010 */
11969 #define FDCAN_IR_RF1F                       FDCAN_IR_RF1F_Msk                       /*!<Rx FIFO 1 Full                           */
11970 #define FDCAN_IR_RF1L_Pos                   (5U)
11971 #define FDCAN_IR_RF1L_Msk                   (0x1UL << FDCAN_IR_RF1L_Pos)            /*!< 0x00000020 */
11972 #define FDCAN_IR_RF1L                       FDCAN_IR_RF1L_Msk                       /*!<Rx FIFO 1 Message Lost                   */
11973 #define FDCAN_IR_HPM_Pos                    (6U)
11974 #define FDCAN_IR_HPM_Msk                    (0x1UL << FDCAN_IR_HPM_Pos)             /*!< 0x00000040 */
11975 #define FDCAN_IR_HPM                        FDCAN_IR_HPM_Msk                        /*!<High Priority Message                    */
11976 #define FDCAN_IR_TC_Pos                     (7U)
11977 #define FDCAN_IR_TC_Msk                     (0x1UL << FDCAN_IR_TC_Pos)              /*!< 0x00000080 */
11978 #define FDCAN_IR_TC                         FDCAN_IR_TC_Msk                         /*!<Transmission Completed                   */
11979 #define FDCAN_IR_TCF_Pos                    (8U)
11980 #define FDCAN_IR_TCF_Msk                    (0x1UL << FDCAN_IR_TCF_Pos)             /*!< 0x00000100 */
11981 #define FDCAN_IR_TCF                        FDCAN_IR_TCF_Msk                        /*!<Transmission Cancellation Finished       */
11982 #define FDCAN_IR_TFE_Pos                    (9U)
11983 #define FDCAN_IR_TFE_Msk                    (0x1UL << FDCAN_IR_TFE_Pos)             /*!< 0x00000200 */
11984 #define FDCAN_IR_TFE                        FDCAN_IR_TFE_Msk                        /*!<Tx FIFO Empty                            */
11985 #define FDCAN_IR_TEFN_Pos                   (10U)
11986 #define FDCAN_IR_TEFN_Msk                   (0x1UL << FDCAN_IR_TEFN_Pos)            /*!< 0x00000400 */
11987 #define FDCAN_IR_TEFN                       FDCAN_IR_TEFN_Msk                       /*!<Tx Event FIFO New Entry                  */
11988 #define FDCAN_IR_TEFF_Pos                   (11U)
11989 #define FDCAN_IR_TEFF_Msk                   (0x1UL << FDCAN_IR_TEFF_Pos)            /*!< 0x00000800 */
11990 #define FDCAN_IR_TEFF                       FDCAN_IR_TEFF_Msk                       /*!<Tx Event FIFO Full                       */
11991 #define FDCAN_IR_TEFL_Pos                   (12U)
11992 #define FDCAN_IR_TEFL_Msk                   (0x1UL << FDCAN_IR_TEFL_Pos)            /*!< 0x00001000 */
11993 #define FDCAN_IR_TEFL                       FDCAN_IR_TEFL_Msk                       /*!<Tx Event FIFO Element Lost               */
11994 #define FDCAN_IR_TSW_Pos                    (13U)
11995 #define FDCAN_IR_TSW_Msk                    (0x1UL << FDCAN_IR_TSW_Pos)             /*!< 0x00002000 */
11996 #define FDCAN_IR_TSW                        FDCAN_IR_TSW_Msk                        /*!<Timestamp Wraparound                     */
11997 #define FDCAN_IR_MRAF_Pos                   (14U)
11998 #define FDCAN_IR_MRAF_Msk                   (0x1UL << FDCAN_IR_MRAF_Pos)            /*!< 0x00004000 */
11999 #define FDCAN_IR_MRAF                       FDCAN_IR_MRAF_Msk                       /*!<Message RAM Access Failure               */
12000 #define FDCAN_IR_TOO_Pos                    (15U)
12001 #define FDCAN_IR_TOO_Msk                    (0x1UL << FDCAN_IR_TOO_Pos)             /*!< 0x00008000 */
12002 #define FDCAN_IR_TOO                        FDCAN_IR_TOO_Msk                        /*!<Timeout Occurred                         */
12003 #define FDCAN_IR_ELO_Pos                    (16U)
12004 #define FDCAN_IR_ELO_Msk                    (0x1UL << FDCAN_IR_ELO_Pos)             /*!< 0x00010000 */
12005 #define FDCAN_IR_ELO                        FDCAN_IR_ELO_Msk                        /*!<Error Logging Overflow                   */
12006 #define FDCAN_IR_EP_Pos                     (17U)
12007 #define FDCAN_IR_EP_Msk                     (0x1UL << FDCAN_IR_EP_Pos)              /*!< 0x00020000 */
12008 #define FDCAN_IR_EP                         FDCAN_IR_EP_Msk                         /*!<Error Passive                            */
12009 #define FDCAN_IR_EW_Pos                     (18U)
12010 #define FDCAN_IR_EW_Msk                     (0x1UL << FDCAN_IR_EW_Pos)              /*!< 0x00040000 */
12011 #define FDCAN_IR_EW                         FDCAN_IR_EW_Msk                         /*!<Warning Status                           */
12012 #define FDCAN_IR_BO_Pos                     (19U)
12013 #define FDCAN_IR_BO_Msk                     (0x1UL << FDCAN_IR_BO_Pos)              /*!< 0x00080000 */
12014 #define FDCAN_IR_BO                         FDCAN_IR_BO_Msk                         /*!<Bus_Off Status                           */
12015 #define FDCAN_IR_WDI_Pos                    (20U)
12016 #define FDCAN_IR_WDI_Msk                    (0x1UL << FDCAN_IR_WDI_Pos)             /*!< 0x00100000 */
12017 #define FDCAN_IR_WDI                        FDCAN_IR_WDI_Msk                        /*!<Watchdog Interrupt                       */
12018 #define FDCAN_IR_PEA_Pos                    (21U)
12019 #define FDCAN_IR_PEA_Msk                    (0x1UL << FDCAN_IR_PEA_Pos)             /*!< 0x00200000 */
12020 #define FDCAN_IR_PEA                        FDCAN_IR_PEA_Msk                        /*!<Protocol Error in Arbitration Phase      */
12021 #define FDCAN_IR_PED_Pos                    (22U)
12022 #define FDCAN_IR_PED_Msk                    (0x1UL << FDCAN_IR_PED_Pos)             /*!< 0x00400000 */
12023 #define FDCAN_IR_PED                        FDCAN_IR_PED_Msk                        /*!<Protocol Error in Data Phase             */
12024 #define FDCAN_IR_ARA_Pos                    (23U)
12025 #define FDCAN_IR_ARA_Msk                    (0x1UL << FDCAN_IR_ARA_Pos)             /*!< 0x00800000 */
12026 #define FDCAN_IR_ARA                        FDCAN_IR_ARA_Msk                        /*!<Access to Reserved Address               */
12027 
12028 /*****************  Bit definition for FDCAN_IE register  ********************* */
12029 #define FDCAN_IE_RF0NE_Pos                  (0U)
12030 #define FDCAN_IE_RF0NE_Msk                  (0x1UL << FDCAN_IE_RF0NE_Pos)           /*!< 0x00000001 */
12031 #define FDCAN_IE_RF0NE                      FDCAN_IE_RF0NE_Msk                      /*!<Rx FIFO 0 New Message Enable             */
12032 #define FDCAN_IE_RF0FE_Pos                  (1U)
12033 #define FDCAN_IE_RF0FE_Msk                  (0x1UL << FDCAN_IE_RF0FE_Pos)           /*!< 0x00000002 */
12034 #define FDCAN_IE_RF0FE                      FDCAN_IE_RF0FE_Msk                      /*!<Rx FIFO 0 Full Enable                    */
12035 #define FDCAN_IE_RF0LE_Pos                  (2U)
12036 #define FDCAN_IE_RF0LE_Msk                  (0x1UL << FDCAN_IE_RF0LE_Pos)           /*!< 0x00000004 */
12037 #define FDCAN_IE_RF0LE                      FDCAN_IE_RF0LE_Msk                      /*!<Rx FIFO 0 Message Lost Enable            */
12038 #define FDCAN_IE_RF1NE_Pos                  (3U)
12039 #define FDCAN_IE_RF1NE_Msk                  (0x1UL << FDCAN_IE_RF1NE_Pos)           /*!< 0x00000008 */
12040 #define FDCAN_IE_RF1NE                      FDCAN_IE_RF1NE_Msk                      /*!<Rx FIFO 1 New Message Enable             */
12041 #define FDCAN_IE_RF1FE_Pos                  (4U)
12042 #define FDCAN_IE_RF1FE_Msk                  (0x1UL << FDCAN_IE_RF1FE_Pos)           /*!< 0x00000010 */
12043 #define FDCAN_IE_RF1FE                      FDCAN_IE_RF1FE_Msk                      /*!<Rx FIFO 1 Full Enable                    */
12044 #define FDCAN_IE_RF1LE_Pos                  (5U)
12045 #define FDCAN_IE_RF1LE_Msk                  (0x1UL << FDCAN_IE_RF1LE_Pos)           /*!< 0x00000020 */
12046 #define FDCAN_IE_RF1LE                      FDCAN_IE_RF1LE_Msk                      /*!<Rx FIFO 1 Message Lost Enable            */
12047 #define FDCAN_IE_HPME_Pos                   (6U)
12048 #define FDCAN_IE_HPME_Msk                   (0x1UL << FDCAN_IE_HPME_Pos)            /*!< 0x00000040 */
12049 #define FDCAN_IE_HPME                       FDCAN_IE_HPME_Msk                       /*!<High Priority Message Enable             */
12050 #define FDCAN_IE_TCE_Pos                    (7U)
12051 #define FDCAN_IE_TCE_Msk                    (0x1UL << FDCAN_IE_TCE_Pos)             /*!< 0x00000080 */
12052 #define FDCAN_IE_TCE                        FDCAN_IE_TCE_Msk                        /*!<Transmission Completed Enable            */
12053 #define FDCAN_IE_TCFE_Pos                   (8U)
12054 #define FDCAN_IE_TCFE_Msk                   (0x1UL << FDCAN_IE_TCFE_Pos)            /*!< 0x00000100 */
12055 #define FDCAN_IE_TCFE                       FDCAN_IE_TCFE_Msk                       /*!<Transmission Cancellation Finished Enable*/
12056 #define FDCAN_IE_TFEE_Pos                   (9U)
12057 #define FDCAN_IE_TFEE_Msk                   (0x1UL << FDCAN_IE_TFEE_Pos)            /*!< 0x00000200 */
12058 #define FDCAN_IE_TFEE                       FDCAN_IE_TFEE_Msk                       /*!<Tx FIFO Empty Enable                     */
12059 #define FDCAN_IE_TEFNE_Pos                  (10U)
12060 #define FDCAN_IE_TEFNE_Msk                  (0x1UL << FDCAN_IE_TEFNE_Pos)           /*!< 0x00000400 */
12061 #define FDCAN_IE_TEFNE                      FDCAN_IE_TEFNE_Msk                      /*!<Tx Event FIFO New Entry Enable           */
12062 #define FDCAN_IE_TEFFE_Pos                  (11U)
12063 #define FDCAN_IE_TEFFE_Msk                  (0x1UL << FDCAN_IE_TEFFE_Pos)           /*!< 0x00000800 */
12064 #define FDCAN_IE_TEFFE                      FDCAN_IE_TEFFE_Msk                      /*!<Tx Event FIFO Full Enable                */
12065 #define FDCAN_IE_TEFLE_Pos                  (12U)
12066 #define FDCAN_IE_TEFLE_Msk                  (0x1UL << FDCAN_IE_TEFLE_Pos)           /*!< 0x00001000 */
12067 #define FDCAN_IE_TEFLE                      FDCAN_IE_TEFLE_Msk                      /*!<Tx Event FIFO Element Lost Enable        */
12068 #define FDCAN_IE_TSWE_Pos                   (13U)
12069 #define FDCAN_IE_TSWE_Msk                   (0x1UL << FDCAN_IE_TSWE_Pos)            /*!< 0x00002000 */
12070 #define FDCAN_IE_TSWE                       FDCAN_IE_TSWE_Msk                       /*!<Timestamp Wraparound Enable              */
12071 #define FDCAN_IE_MRAFE_Pos                  (14U)
12072 #define FDCAN_IE_MRAFE_Msk                  (0x1UL << FDCAN_IE_MRAFE_Pos)           /*!< 0x00004000 */
12073 #define FDCAN_IE_MRAFE                      FDCAN_IE_MRAFE_Msk                      /*!<Message RAM Access Failure Enable        */
12074 #define FDCAN_IE_TOOE_Pos                   (15U)
12075 #define FDCAN_IE_TOOE_Msk                   (0x1UL << FDCAN_IE_TOOE_Pos)            /*!< 0x00008000 */
12076 #define FDCAN_IE_TOOE                       FDCAN_IE_TOOE_Msk                       /*!<Timeout Occurred Enable                  */
12077 #define FDCAN_IE_ELOE_Pos                   (16U)
12078 #define FDCAN_IE_ELOE_Msk                   (0x1UL << FDCAN_IE_ELOE_Pos)            /*!< 0x00010000 */
12079 #define FDCAN_IE_ELOE                       FDCAN_IE_ELOE_Msk                       /*!<Error Logging Overflow Enable            */
12080 #define FDCAN_IE_EPE_Pos                    (17U)
12081 #define FDCAN_IE_EPE_Msk                    (0x1UL << FDCAN_IE_EPE_Pos)             /*!< 0x00020000 */
12082 #define FDCAN_IE_EPE                        FDCAN_IE_EPE_Msk                        /*!<Error Passive Enable                     */
12083 #define FDCAN_IE_EWE_Pos                    (18U)
12084 #define FDCAN_IE_EWE_Msk                    (0x1UL << FDCAN_IE_EWE_Pos)             /*!< 0x00040000 */
12085 #define FDCAN_IE_EWE                        FDCAN_IE_EWE_Msk                        /*!<Warning Status Enable                    */
12086 #define FDCAN_IE_BOE_Pos                    (19U)
12087 #define FDCAN_IE_BOE_Msk                    (0x1UL << FDCAN_IE_BOE_Pos)             /*!< 0x00080000 */
12088 #define FDCAN_IE_BOE                        FDCAN_IE_BOE_Msk                        /*!<Bus_Off Status Enable                    */
12089 #define FDCAN_IE_WDIE_Pos                   (20U)
12090 #define FDCAN_IE_WDIE_Msk                   (0x1UL << FDCAN_IE_WDIE_Pos)            /*!< 0x00100000 */
12091 #define FDCAN_IE_WDIE                       FDCAN_IE_WDIE_Msk                       /*!<Watchdog Interrupt Enable                */
12092 #define FDCAN_IE_PEAE_Pos                   (21U)
12093 #define FDCAN_IE_PEAE_Msk                   (0x1UL << FDCAN_IE_PEAE_Pos)            /*!< 0x00200000 */
12094 #define FDCAN_IE_PEAE                       FDCAN_IE_PEAE_Msk                       /*!<Protocol Error in Arbitration Phase Enable*/
12095 #define FDCAN_IE_PEDE_Pos                   (22U)
12096 #define FDCAN_IE_PEDE_Msk                   (0x1UL << FDCAN_IE_PEDE_Pos)            /*!< 0x00400000 */
12097 #define FDCAN_IE_PEDE                       FDCAN_IE_PEDE_Msk                       /*!<Protocol Error in Data Phase Enable      */
12098 #define FDCAN_IE_ARAE_Pos                   (23U)
12099 #define FDCAN_IE_ARAE_Msk                   (0x1UL << FDCAN_IE_ARAE_Pos)            /*!< 0x00800000 */
12100 #define FDCAN_IE_ARAE                       FDCAN_IE_ARAE_Msk                       /*!<Access to Reserved Address Enable        */
12101 
12102 /*****************  Bit definition for FDCAN_ILS register  ******************** **/
12103 #define FDCAN_ILS_RXFIFO0_Pos               (0U)
12104 #define FDCAN_ILS_RXFIFO0_Msk               (0x1UL << FDCAN_ILS_RXFIFO0_Pos)        /*!< 0x00000001 */
12105 #define FDCAN_ILS_RXFIFO0                   FDCAN_ILS_RXFIFO0_Msk                   /*!<Rx FIFO 0 Message Lost
12106                                                                                         Rx FIFO 0 is Full
12107                                                                                         Rx FIFO 0 Has New Message                */
12108 #define FDCAN_ILS_RXFIFO1_Pos               (1U)
12109 #define FDCAN_ILS_RXFIFO1_Msk               (0x1UL << FDCAN_ILS_RXFIFO1_Pos)        /*!< 0x00000002 */
12110 #define FDCAN_ILS_RXFIFO1                   FDCAN_ILS_RXFIFO1_Msk                   /*!<Rx FIFO 1 Message Lost
12111                                                                                         Rx FIFO 1 is Full
12112                                                                                         Rx FIFO 1 Has New Message                */
12113 #define FDCAN_ILS_SMSG_Pos                  (2U)
12114 #define FDCAN_ILS_SMSG_Msk                  (0x1UL << FDCAN_ILS_SMSG_Pos)           /*!< 0x00000004 */
12115 #define FDCAN_ILS_SMSG                      FDCAN_ILS_SMSG_Msk                      /*!<Transmission Cancellation Finished
12116                                                                                         Transmission Completed
12117                                                                                         High Priority Message                    */
12118 #define FDCAN_ILS_TFERR_Pos                 (3U)
12119 #define FDCAN_ILS_TFERR_Msk                 (0x1UL << FDCAN_ILS_TFERR_Pos)          /*!< 0x00000008 */
12120 #define FDCAN_ILS_TFERR                     FDCAN_ILS_TFERR_Msk                     /*!<Tx Event FIFO Element Lost
12121                                                                                         Tx Event FIFO Full
12122                                                                                         Tx Event FIFO New Entry
12123                                                                                         Tx FIFO Empty Interrupt Line             */
12124 #define FDCAN_ILS_MISC_Pos                  (4U)
12125 #define FDCAN_ILS_MISC_Msk                  (0x1UL << FDCAN_ILS_MISC_Pos)           /*!< 0x00000010 */
12126 #define FDCAN_ILS_MISC                      FDCAN_ILS_MISC_Msk                      /*!<Timeout Occurred
12127                                                                                         Message RAM Access Failure
12128                                                                                         Timestamp Wraparound                    */
12129 #define FDCAN_ILS_BERR_Pos                  (5U)
12130 #define FDCAN_ILS_BERR_Msk                  (0x1UL << FDCAN_ILS_BERR_Pos)           /*!< 0x00000020 */
12131 #define FDCAN_ILS_BERR                      FDCAN_ILS_BERR_Msk                      /*!<Error Passive
12132                                                                                         Error Logging Overflow                   */
12133 #define FDCAN_ILS_PERR_Pos                  (6U)
12134 #define FDCAN_ILS_PERR_Msk                  (0x1UL << FDCAN_ILS_PERR_Pos)           /*!< 0x00000040 */
12135 #define FDCAN_ILS_PERR                      FDCAN_ILS_PERR_Msk                      /*!<Access to Reserved Address Line
12136                                                                                         Protocol Error in Data Phase Line
12137                                                                                         Protocol Error in Arbitration Phase Line
12138                                                                                         Watchdog Interrupt Line
12139                                                                                         Bus_Off Status
12140                                                                                         Warning Status                           */
12141 
12142 /*****************  Bit definition for FDCAN_ILE register  ******************** **/
12143 #define FDCAN_ILE_EINT0_Pos                 (0U)
12144 #define FDCAN_ILE_EINT0_Msk                 (0x1UL << FDCAN_ILE_EINT0_Pos)          /*!< 0x00000001 */
12145 #define FDCAN_ILE_EINT0                     FDCAN_ILE_EINT0_Msk                     /*!<Enable Interrupt Line 0                  */
12146 #define FDCAN_ILE_EINT1_Pos                 (1U)
12147 #define FDCAN_ILE_EINT1_Msk                 (0x1UL << FDCAN_ILE_EINT1_Pos)          /*!< 0x00000002 */
12148 #define FDCAN_ILE_EINT1                     FDCAN_ILE_EINT1_Msk                     /*!<Enable Interrupt Line 1                  */
12149 
12150 /*****************  Bit definition for FDCAN_RXGFC register  ****************** **/
12151 #define FDCAN_RXGFC_RRFE_Pos                (0U)
12152 #define FDCAN_RXGFC_RRFE_Msk                (0x1UL << FDCAN_RXGFC_RRFE_Pos)         /*!< 0x00000001 */
12153 #define FDCAN_RXGFC_RRFE                    FDCAN_RXGFC_RRFE_Msk                    /*!<Reject Remote Frames Extended            */
12154 #define FDCAN_RXGFC_RRFS_Pos                (1U)
12155 #define FDCAN_RXGFC_RRFS_Msk                (0x1UL << FDCAN_RXGFC_RRFS_Pos)         /*!< 0x00000002 */
12156 #define FDCAN_RXGFC_RRFS                    FDCAN_RXGFC_RRFS_Msk                    /*!<Reject Remote Frames Standard            */
12157 #define FDCAN_RXGFC_ANFE_Pos                (2U)
12158 #define FDCAN_RXGFC_ANFE_Msk                (0x3UL << FDCAN_RXGFC_ANFE_Pos)         /*!< 0x0000000C */
12159 #define FDCAN_RXGFC_ANFE                    FDCAN_RXGFC_ANFE_Msk                    /*!<Accept Non-matching Frames Extended      */
12160 #define FDCAN_RXGFC_ANFS_Pos                (4U)
12161 #define FDCAN_RXGFC_ANFS_Msk                (0x3UL << FDCAN_RXGFC_ANFS_Pos)         /*!< 0x00000030 */
12162 #define FDCAN_RXGFC_ANFS                    FDCAN_RXGFC_ANFS_Msk                    /*!<Accept Non-matching Frames Standard      */
12163 #define FDCAN_RXGFC_F1OM_Pos                (8U)
12164 #define FDCAN_RXGFC_F1OM_Msk                (0x1UL << FDCAN_RXGFC_F1OM_Pos)         /*!< 0x00000100 */
12165 #define FDCAN_RXGFC_F1OM                    FDCAN_RXGFC_F1OM_Msk                    /*!<FIFO 1 operation mode                    */
12166 #define FDCAN_RXGFC_F0OM_Pos                (9U)
12167 #define FDCAN_RXGFC_F0OM_Msk                (0x1UL << FDCAN_RXGFC_F0OM_Pos)         /*!< 0x00000200 */
12168 #define FDCAN_RXGFC_F0OM                    FDCAN_RXGFC_F0OM_Msk                    /*!<FIFO 0 operation mode                    */
12169 #define FDCAN_RXGFC_LSS_Pos                 (16U)
12170 #define FDCAN_RXGFC_LSS_Msk                 (0x1FUL << FDCAN_RXGFC_LSS_Pos)         /*!< 0x001F0000 */
12171 #define FDCAN_RXGFC_LSS                     FDCAN_RXGFC_LSS_Msk                     /*!<List Size Standard                       */
12172 #define FDCAN_RXGFC_LSE_Pos                 (24U)
12173 #define FDCAN_RXGFC_LSE_Msk                 (0xFUL << FDCAN_RXGFC_LSE_Pos)          /*!< 0x0F000000 */
12174 #define FDCAN_RXGFC_LSE                     FDCAN_RXGFC_LSE_Msk                     /*!<List Size Extended                       */
12175 
12176 /*****************  Bit definition for FDCAN_XIDAM register  ****************** **/
12177 #define FDCAN_XIDAM_EIDM_Pos                (0U)
12178 #define FDCAN_XIDAM_EIDM_Msk                (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)  /*!< 0x1FFFFFFF */
12179 #define FDCAN_XIDAM_EIDM                    FDCAN_XIDAM_EIDM_Msk                    /*!<Extended ID Mask                         */
12180 
12181 /*****************  Bit definition for FDCAN_HPMS register  ******************* **/
12182 #define FDCAN_HPMS_BIDX_Pos                 (0U)
12183 #define FDCAN_HPMS_BIDX_Msk                 (0x7UL << FDCAN_HPMS_BIDX_Pos)          /*!< 0x00000007 */
12184 #define FDCAN_HPMS_BIDX                     FDCAN_HPMS_BIDX_Msk                     /*!<Buffer Index                             */
12185 #define FDCAN_HPMS_MSI_Pos                  (6U)
12186 #define FDCAN_HPMS_MSI_Msk                  (0x3UL << FDCAN_HPMS_MSI_Pos)           /*!< 0x000000C0 */
12187 #define FDCAN_HPMS_MSI                      FDCAN_HPMS_MSI_Msk                      /*!<Message Storage Indicator                */
12188 #define FDCAN_HPMS_FIDX_Pos                 (8U)
12189 #define FDCAN_HPMS_FIDX_Msk                 (0x1FUL << FDCAN_HPMS_FIDX_Pos)         /*!< 0x00001F00 */
12190 #define FDCAN_HPMS_FIDX                     FDCAN_HPMS_FIDX_Msk                     /*!<Filter Index                             */
12191 #define FDCAN_HPMS_FLST_Pos                 (15U)
12192 #define FDCAN_HPMS_FLST_Msk                 (0x1UL << FDCAN_HPMS_FLST_Pos)          /*!< 0x00008000 */
12193 #define FDCAN_HPMS_FLST                     FDCAN_HPMS_FLST_Msk                     /*!<Filter List                              */
12194 
12195 /*****************  Bit definition for FDCAN_RXF0S register  ****************** **/
12196 #define FDCAN_RXF0S_F0FL_Pos                (0U)
12197 #define FDCAN_RXF0S_F0FL_Msk                (0xFUL << FDCAN_RXF0S_F0FL_Pos)         /*!< 0x0000000F */
12198 #define FDCAN_RXF0S_F0FL                    FDCAN_RXF0S_F0FL_Msk                    /*!<Rx FIFO 0 Fill Level                     */
12199 #define FDCAN_RXF0S_F0GI_Pos                (8U)
12200 #define FDCAN_RXF0S_F0GI_Msk                (0x3UL << FDCAN_RXF0S_F0GI_Pos)         /*!< 0x00000300 */
12201 #define FDCAN_RXF0S_F0GI                    FDCAN_RXF0S_F0GI_Msk                    /*!<Rx FIFO 0 Get Index                      */
12202 #define FDCAN_RXF0S_F0PI_Pos                (16U)
12203 #define FDCAN_RXF0S_F0PI_Msk                (0x3UL << FDCAN_RXF0S_F0PI_Pos)         /*!< 0x00030000 */
12204 #define FDCAN_RXF0S_F0PI                    FDCAN_RXF0S_F0PI_Msk                    /*!<Rx FIFO 0 Put Index                      */
12205 #define FDCAN_RXF0S_F0F_Pos                 (24U)
12206 #define FDCAN_RXF0S_F0F_Msk                 (0x1UL << FDCAN_RXF0S_F0F_Pos)          /*!< 0x01000000 */
12207 #define FDCAN_RXF0S_F0F                     FDCAN_RXF0S_F0F_Msk                     /*!<Rx FIFO 0 Full                           */
12208 #define FDCAN_RXF0S_RF0L_Pos                (25U)
12209 #define FDCAN_RXF0S_RF0L_Msk                (0x1UL << FDCAN_RXF0S_RF0L_Pos)         /*!< 0x02000000 */
12210 #define FDCAN_RXF0S_RF0L                    FDCAN_RXF0S_RF0L_Msk                    /*!<Rx FIFO 0 Message Lost                   */
12211 
12212 /*****************  Bit definition for FDCAN_RXF0A register  ****************** **/
12213 #define FDCAN_RXF0A_F0AI_Pos                (0U)
12214 #define FDCAN_RXF0A_F0AI_Msk                (0x7UL << FDCAN_RXF0A_F0AI_Pos)         /*!< 0x00000007 */
12215 #define FDCAN_RXF0A_F0AI                    FDCAN_RXF0A_F0AI_Msk                    /*!<Rx FIFO 0 Acknowledge Index              */
12216 
12217 /*****************  Bit definition for FDCAN_RXF1S register  ****************** **/
12218 #define FDCAN_RXF1S_F1FL_Pos                (0U)
12219 #define FDCAN_RXF1S_F1FL_Msk                (0xFUL << FDCAN_RXF1S_F1FL_Pos)         /*!< 0x0000000F */
12220 #define FDCAN_RXF1S_F1FL                    FDCAN_RXF1S_F1FL_Msk                    /*!<Rx FIFO 1 Fill Level                     */
12221 #define FDCAN_RXF1S_F1GI_Pos                (8U)
12222 #define FDCAN_RXF1S_F1GI_Msk                (0x3UL << FDCAN_RXF1S_F1GI_Pos)         /*!< 0x00000300 */
12223 #define FDCAN_RXF1S_F1GI                    FDCAN_RXF1S_F1GI_Msk                    /*!<Rx FIFO 1 Get Index                      */
12224 #define FDCAN_RXF1S_F1PI_Pos                (16U)
12225 #define FDCAN_RXF1S_F1PI_Msk                (0x3UL << FDCAN_RXF1S_F1PI_Pos)         /*!< 0x00030000 */
12226 #define FDCAN_RXF1S_F1PI                    FDCAN_RXF1S_F1PI_Msk                    /*!<Rx FIFO 1 Put Index                      */
12227 #define FDCAN_RXF1S_F1F_Pos                 (24U)
12228 #define FDCAN_RXF1S_F1F_Msk                 (0x1UL << FDCAN_RXF1S_F1F_Pos)          /*!< 0x01000000 */
12229 #define FDCAN_RXF1S_F1F                     FDCAN_RXF1S_F1F_Msk                     /*!<Rx FIFO 1 Full                           */
12230 #define FDCAN_RXF1S_RF1L_Pos                (25U)
12231 #define FDCAN_RXF1S_RF1L_Msk                (0x1UL << FDCAN_RXF1S_RF1L_Pos)         /*!< 0x02000000 */
12232 #define FDCAN_RXF1S_RF1L                    FDCAN_RXF1S_RF1L_Msk                    /*!<Rx FIFO 1 Message Lost                   */
12233 
12234 /*****************  Bit definition for FDCAN_RXF1A register  ****************** **/
12235 #define FDCAN_RXF1A_F1AI_Pos                (0U)
12236 #define FDCAN_RXF1A_F1AI_Msk                (0x7UL << FDCAN_RXF1A_F1AI_Pos)         /*!< 0x00000007 */
12237 #define FDCAN_RXF1A_F1AI                    FDCAN_RXF1A_F1AI_Msk                    /*!<Rx FIFO 1 Acknowledge Index              */
12238 
12239 /*****************  Bit definition for FDCAN_TXBC register  ******************* **/
12240 #define FDCAN_TXBC_TFQM_Pos                 (24U)
12241 #define FDCAN_TXBC_TFQM_Msk                 (0x1UL << FDCAN_TXBC_TFQM_Pos)          /*!< 0x01000000 */
12242 #define FDCAN_TXBC_TFQM                     FDCAN_TXBC_TFQM_Msk                     /*!<Tx FIFO/Queue Mode                       */
12243 
12244 /*****************  Bit definition for FDCAN_TXFQS register  ****************** ***/
12245 #define FDCAN_TXFQS_TFFL_Pos                (0U)
12246 #define FDCAN_TXFQS_TFFL_Msk                (0x7UL << FDCAN_TXFQS_TFFL_Pos)         /*!< 0x00000007 */
12247 #define FDCAN_TXFQS_TFFL                    FDCAN_TXFQS_TFFL_Msk                    /*!<Tx FIFO Free Level                       */
12248 #define FDCAN_TXFQS_TFGI_Pos                (8U)
12249 #define FDCAN_TXFQS_TFGI_Msk                (0x3UL << FDCAN_TXFQS_TFGI_Pos)         /*!< 0x00000300 */
12250 #define FDCAN_TXFQS_TFGI                    FDCAN_TXFQS_TFGI_Msk                    /*!<Tx FIFO Get Index                        */
12251 #define FDCAN_TXFQS_TFQPI_Pos               (16U)
12252 #define FDCAN_TXFQS_TFQPI_Msk               (0x3UL << FDCAN_TXFQS_TFQPI_Pos)        /*!< 0x00030000 */
12253 #define FDCAN_TXFQS_TFQPI                   FDCAN_TXFQS_TFQPI_Msk                   /*!<Tx FIFO/Queue Put Index                  */
12254 #define FDCAN_TXFQS_TFQF_Pos                (21U)
12255 #define FDCAN_TXFQS_TFQF_Msk                (0x1UL << FDCAN_TXFQS_TFQF_Pos)         /*!< 0x00200000 */
12256 #define FDCAN_TXFQS_TFQF                    FDCAN_TXFQS_TFQF_Msk                    /*!<Tx FIFO/Queue Full                       */
12257 
12258 /*****************  Bit definition for FDCAN_TXBRP register  ****************** ***/
12259 #define FDCAN_TXBRP_TRP_Pos                 (0U)
12260 #define FDCAN_TXBRP_TRP_Msk                 (0x7UL << FDCAN_TXBRP_TRP_Pos)          /*!< 0x00000007 */
12261 #define FDCAN_TXBRP_TRP                     FDCAN_TXBRP_TRP_Msk                     /*!<Transmission Request Pending             */
12262 
12263 /*****************  Bit definition for FDCAN_TXBAR register  ****************** ***/
12264 #define FDCAN_TXBAR_AR_Pos                  (0U)
12265 #define FDCAN_TXBAR_AR_Msk                  (0x7UL << FDCAN_TXBAR_AR_Pos)           /*!< 0x00000007 */
12266 #define FDCAN_TXBAR_AR                      FDCAN_TXBAR_AR_Msk                      /*!<Add Request                              */
12267 
12268 /*****************  Bit definition for FDCAN_TXBCR register  ****************** ***/
12269 #define FDCAN_TXBCR_CR_Pos                  (0U)
12270 #define FDCAN_TXBCR_CR_Msk                  (0x7UL << FDCAN_TXBCR_CR_Pos)           /*!< 0x00000007 */
12271 #define FDCAN_TXBCR_CR                      FDCAN_TXBCR_CR_Msk                      /*!<Cancellation Request                     */
12272 
12273 /*****************  Bit definition for FDCAN_TXBTO register  ****************** ***/
12274 #define FDCAN_TXBTO_TO_Pos                  (0U)
12275 #define FDCAN_TXBTO_TO_Msk                  (0x7UL << FDCAN_TXBTO_TO_Pos)           /*!< 0x00000007 */
12276 #define FDCAN_TXBTO_TO                      FDCAN_TXBTO_TO_Msk                      /*!<Transmission Occurred                    */
12277 
12278 /*****************  Bit definition for FDCAN_TXBCF register  ****************** ***/
12279 #define FDCAN_TXBCF_CF_Pos                  (0U)
12280 #define FDCAN_TXBCF_CF_Msk                  (0x7UL << FDCAN_TXBCF_CF_Pos)           /*!< 0x00000007 */
12281 #define FDCAN_TXBCF_CF                      FDCAN_TXBCF_CF_Msk                      /*!<Cancellation Finished                    */
12282 
12283 /*****************  Bit definition for FDCAN_TXBTIE register  ***************** ***/
12284 #define FDCAN_TXBTIE_TIE_Pos                (0U)
12285 #define FDCAN_TXBTIE_TIE_Msk                (0x7UL << FDCAN_TXBTIE_TIE_Pos)         /*!< 0x00000007 */
12286 #define FDCAN_TXBTIE_TIE                    FDCAN_TXBTIE_TIE_Msk                    /*!<Transmission Interrupt Enable            */
12287 
12288 /*****************  Bit definition for FDCAN_ TXBCIE register  **************** ***/
12289 #define FDCAN_TXBCIE_CFIE_Pos               (0U)
12290 #define FDCAN_TXBCIE_CFIE_Msk               (0x7UL << FDCAN_TXBCIE_CFIE_Pos)        /*!< 0x00000007 */
12291 #define FDCAN_TXBCIE_CFIE                   FDCAN_TXBCIE_CFIE_Msk                   /*!<Cancellation Finished Interrupt Enable   */
12292 
12293 /*****************  Bit definition for FDCAN_TXEFS register  ****************** ***/
12294 #define FDCAN_TXEFS_EFFL_Pos                (0U)
12295 #define FDCAN_TXEFS_EFFL_Msk                (0x7UL << FDCAN_TXEFS_EFFL_Pos)         /*!< 0x00000007 */
12296 #define FDCAN_TXEFS_EFFL                    FDCAN_TXEFS_EFFL_Msk                    /*!<Event FIFO Fill Level                    */
12297 #define FDCAN_TXEFS_EFGI_Pos                (8U)
12298 #define FDCAN_TXEFS_EFGI_Msk                (0x3UL << FDCAN_TXEFS_EFGI_Pos)         /*!< 0x00000300 */
12299 #define FDCAN_TXEFS_EFGI                    FDCAN_TXEFS_EFGI_Msk                    /*!<Event FIFO Get Index                     */
12300 #define FDCAN_TXEFS_EFPI_Pos                (16U)
12301 #define FDCAN_TXEFS_EFPI_Msk                (0x3UL << FDCAN_TXEFS_EFPI_Pos)         /*!< 0x00030000 */
12302 #define FDCAN_TXEFS_EFPI                    FDCAN_TXEFS_EFPI_Msk                    /*!<Event FIFO Put Index                     */
12303 #define FDCAN_TXEFS_EFF_Pos                 (24U)
12304 #define FDCAN_TXEFS_EFF_Msk                 (0x1UL << FDCAN_TXEFS_EFF_Pos)          /*!< 0x01000000 */
12305 #define FDCAN_TXEFS_EFF                     FDCAN_TXEFS_EFF_Msk                     /*!<Event FIFO Full                          */
12306 #define FDCAN_TXEFS_TEFL_Pos                (25U)
12307 #define FDCAN_TXEFS_TEFL_Msk                (0x1UL << FDCAN_TXEFS_TEFL_Pos)         /*!< 0x02000000 */
12308 #define FDCAN_TXEFS_TEFL                    FDCAN_TXEFS_TEFL_Msk                    /*!<Tx Event FIFO Element Lost               */
12309 
12310 /*****************  Bit definition for FDCAN_TXEFA register  ****************** ***/
12311 #define FDCAN_TXEFA_EFAI_Pos                (0U)
12312 #define FDCAN_TXEFA_EFAI_Msk                (0x3UL << FDCAN_TXEFA_EFAI_Pos)         /*!< 0x00000003 */
12313 #define FDCAN_TXEFA_EFAI                    FDCAN_TXEFA_EFAI_Msk                    /*!<Event FIFO Acknowledge Index             */
12314 
12315 /*!<FDCAN config registers */
12316 /*****************  Bit definition for FDCAN_CKDIV register  ****************** ***/
12317 #define FDCAN_CKDIV_PDIV_Pos                (0U)
12318 #define FDCAN_CKDIV_PDIV_Msk                (0xFUL << FDCAN_CKDIV_PDIV_Pos)         /*!< 0x0000000F */
12319 #define FDCAN_CKDIV_PDIV                    FDCAN_CKDIV_PDIV_Msk                    /*!<Input Clock Divider                      */
12320 
12321 /******************************************************************************/
12322 /*                                                                            */
12323 /*                                    FLASH                                   */
12324 /*                                                                            */
12325 /******************************************************************************/
12326 #define FLASH_LATENCY_DEFAULT               FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycles   */
12327 
12328 #define FLASH_SIZE_DEFAULT                  0x400000U               /*!< Flash memory default size */
12329 #define FLASH_BLOCKBASED_NB_REG             (8U)                    /*!< 8 Block-based registers for each Flash bank */
12330 
12331 #define FLASH_SIZE                          ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \
12332                                              ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \
12333                                               (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U)))
12334 
12335 #define FLASH_BANK_SIZE                     (FLASH_SIZE >> 1U)
12336 
12337 #define FLASH_PAGE_SIZE                     0x2000U  /* 8 KB */
12338 
12339 #define FLASH_PAGE_NB                       (FLASH_BANK_SIZE / FLASH_PAGE_SIZE)
12340 
12341 /*******************  Bits definition for FLASH_ACR register  *****************/
12342 #define FLASH_ACR_LATENCY_Pos               (0U)
12343 #define FLASH_ACR_LATENCY_Msk               (0xFUL << FLASH_ACR_LATENCY_Pos)        /*!< 0x0000000F */
12344 #define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk                   /*!< Latency    */
12345 #define FLASH_ACR_LATENCY_0WS               (0x00000000U)
12346 #define FLASH_ACR_LATENCY_1WS               (0x00000001U)
12347 #define FLASH_ACR_LATENCY_2WS               (0x00000002U)
12348 #define FLASH_ACR_LATENCY_3WS               (0x00000003U)
12349 #define FLASH_ACR_LATENCY_4WS               (0x00000004U)
12350 #define FLASH_ACR_LATENCY_5WS               (0x00000005U)
12351 #define FLASH_ACR_LATENCY_6WS               (0x00000006U)
12352 #define FLASH_ACR_LATENCY_7WS               (0x00000007U)
12353 #define FLASH_ACR_LATENCY_8WS               (0x00000008U)
12354 #define FLASH_ACR_LATENCY_9WS               (0x00000009U)
12355 #define FLASH_ACR_LATENCY_10WS              (0x0000000AU)
12356 #define FLASH_ACR_LATENCY_11WS              (0x0000000BU)
12357 #define FLASH_ACR_LATENCY_12WS              (0x0000000CU)
12358 #define FLASH_ACR_LATENCY_13WS              (0x0000000DU)
12359 #define FLASH_ACR_LATENCY_14WS              (0x0000000EU)
12360 #define FLASH_ACR_LATENCY_15WS              (0x0000000FU)
12361 #define FLASH_ACR_PRFTEN_Pos                (8U)
12362 #define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)         /*!< 0x00000100 */
12363 #define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk                    /*!< Prefetch enable */
12364 #define FLASH_ACR_LPM_Pos                   (11U)
12365 #define FLASH_ACR_LPM_Msk                   (0x1UL << FLASH_ACR_LPM_Pos)            /*!< 0x00000800 */
12366 #define FLASH_ACR_LPM                       FLASH_ACR_LPM_Msk                       /*!< Low-Power read mode */
12367 #define FLASH_ACR_PDREQ1_Pos                (12U)
12368 #define FLASH_ACR_PDREQ1_Msk                (0x1UL << FLASH_ACR_PDREQ1_Pos)         /*!< 0x00001000 */
12369 #define FLASH_ACR_PDREQ1                    FLASH_ACR_PDREQ1_Msk                    /*!< Bank 1 power-down mode request */
12370 #define FLASH_ACR_PDREQ2_Pos                (13U)
12371 #define FLASH_ACR_PDREQ2_Msk                (0x1UL << FLASH_ACR_PDREQ2_Pos)         /*!< 0x00002000 */
12372 #define FLASH_ACR_PDREQ2                    FLASH_ACR_PDREQ2_Msk                    /*!< Bank 2 power-down mode request */
12373 #define FLASH_ACR_SLEEP_PD_Pos              (14U)
12374 #define FLASH_ACR_SLEEP_PD_Msk              (0x1UL << FLASH_ACR_SLEEP_PD_Pos)       /*!< 0x00004000 */
12375 #define FLASH_ACR_SLEEP_PD                  FLASH_ACR_SLEEP_PD_Msk                  /*!< Flash power-down mode during sleep */
12376 
12377 /******************  Bits definition for FLASH_NSSR register  *****************/
12378 #define FLASH_NSSR_EOP_Pos                  (0U)
12379 #define FLASH_NSSR_EOP_Msk                  (0x1UL << FLASH_NSSR_EOP_Pos)           /*!< 0x00000001 */
12380 #define FLASH_NSSR_EOP                      FLASH_NSSR_EOP_Msk                      /*!< Non-secure end of operation */
12381 #define FLASH_NSSR_OPERR_Pos                (1U)
12382 #define FLASH_NSSR_OPERR_Msk                (0x1UL << FLASH_NSSR_OPERR_Pos)         /*!< 0x00000002 */
12383 #define FLASH_NSSR_OPERR                    FLASH_NSSR_OPERR_Msk                    /*!< Non-secure operation error */
12384 #define FLASH_NSSR_PROGERR_Pos              (3U)
12385 #define FLASH_NSSR_PROGERR_Msk              (0x1UL << FLASH_NSSR_PROGERR_Pos)       /*!< 0x00000008 */
12386 #define FLASH_NSSR_PROGERR                  FLASH_NSSR_PROGERR_Msk                  /*!< Non-secure programming error */
12387 #define FLASH_NSSR_WRPERR_Pos               (4U)
12388 #define FLASH_NSSR_WRPERR_Msk               (0x1UL << FLASH_NSSR_WRPERR_Pos)        /*!< 0x00000010 */
12389 #define FLASH_NSSR_WRPERR                   FLASH_NSSR_WRPERR_Msk                   /*!< Non-secure write protection error */
12390 #define FLASH_NSSR_PGAERR_Pos               (5U)
12391 #define FLASH_NSSR_PGAERR_Msk               (0x1UL << FLASH_NSSR_PGAERR_Pos)        /*!< 0x00000020 */
12392 #define FLASH_NSSR_PGAERR                   FLASH_NSSR_PGAERR_Msk                   /*!< Non-secure programming alignment error */
12393 #define FLASH_NSSR_SIZERR_Pos               (6U)
12394 #define FLASH_NSSR_SIZERR_Msk               (0x1UL << FLASH_NSSR_SIZERR_Pos)        /*!< 0x00000040 */
12395 #define FLASH_NSSR_SIZERR                   FLASH_NSSR_SIZERR_Msk                   /*!< Non-secure size error */
12396 #define FLASH_NSSR_PGSERR_Pos               (7U)
12397 #define FLASH_NSSR_PGSERR_Msk               (0x1UL << FLASH_NSSR_PGSERR_Pos)        /*!< 0x00000080 */
12398 #define FLASH_NSSR_PGSERR                   FLASH_NSSR_PGSERR_Msk                   /*!< Non-secure programming sequence error */
12399 #define FLASH_NSSR_OPTWERR_Pos              (13U)
12400 #define FLASH_NSSR_OPTWERR_Msk              (0x1UL << FLASH_NSSR_OPTWERR_Pos)       /*!< 0x00002000 */
12401 #define FLASH_NSSR_OPTWERR                  FLASH_NSSR_OPTWERR_Msk                  /*!< Option write error */
12402 #define FLASH_NSSR_BSY_Pos                  (16U)
12403 #define FLASH_NSSR_BSY_Msk                  (0x1UL << FLASH_NSSR_BSY_Pos)           /*!< 0x00010000 */
12404 #define FLASH_NSSR_BSY                      FLASH_NSSR_BSY_Msk                      /*!< Non-secure busy */
12405 #define FLASH_NSSR_WDW_Pos                  (17U)
12406 #define FLASH_NSSR_WDW_Msk                  (0x1UL << FLASH_NSSR_WDW_Pos)           /*!< 0x00020000 */
12407 #define FLASH_NSSR_WDW                      FLASH_NSSR_WDW_Msk                      /*!< Non-secure wait data to write */
12408 #define FLASH_NSSR_OEM1LOCK_Pos             (18U)
12409 #define FLASH_NSSR_OEM1LOCK_Msk             (0x1UL << FLASH_NSSR_OEM1LOCK_Pos)      /*!< 0x00040000 */
12410 #define FLASH_NSSR_OEM1LOCK                 FLASH_NSSR_OEM1LOCK_Msk                 /*!< OEM1 lock */
12411 #define FLASH_NSSR_OEM2LOCK_Pos             (19U)
12412 #define FLASH_NSSR_OEM2LOCK_Msk             (0x1UL << FLASH_NSSR_OEM2LOCK_Pos)      /*!< 0x00080000 */
12413 #define FLASH_NSSR_OEM2LOCK                 FLASH_NSSR_OEM2LOCK_Msk                 /*!< OEM2 lock */
12414 #define FLASH_NSSR_PD1_Pos                  (20U)
12415 #define FLASH_NSSR_PD1_Msk                  (0x1UL << FLASH_NSSR_PD1_Pos)           /*!< 0x00100000 */
12416 #define FLASH_NSSR_PD1                      FLASH_NSSR_PD1_Msk                      /*!< Bank 1 in power-down mode */
12417 #define FLASH_NSSR_PD2_Pos                  (21U)
12418 #define FLASH_NSSR_PD2_Msk                  (0x1UL << FLASH_NSSR_PD2_Pos)           /*!< 0x00200000 */
12419 #define FLASH_NSSR_PD2                      FLASH_NSSR_PD2_Msk                      /*!< Bank 2 in power-down mode */
12420 
12421 /******************  Bits definition for FLASH_SECSR register  ****************/
12422 #define FLASH_SECSR_EOP_Pos                 (0U)
12423 #define FLASH_SECSR_EOP_Msk                 (0x1UL << FLASH_SECSR_EOP_Pos)          /*!< 0x00000001 */
12424 #define FLASH_SECSR_EOP                     FLASH_SECSR_EOP_Msk                     /*!< Secure end of operation */
12425 #define FLASH_SECSR_OPERR_Pos               (1U)
12426 #define FLASH_SECSR_OPERR_Msk               (0x1UL << FLASH_SECSR_OPERR_Pos)        /*!< 0x00000002 */
12427 #define FLASH_SECSR_OPERR                   FLASH_SECSR_OPERR_Msk                   /*!< Secure operation error */
12428 #define FLASH_SECSR_PROGERR_Pos             (3U)
12429 #define FLASH_SECSR_PROGERR_Msk             (0x1UL << FLASH_SECSR_PROGERR_Pos)      /*!< 0x00000008 */
12430 #define FLASH_SECSR_PROGERR                 FLASH_SECSR_PROGERR_Msk                 /*!< Secure programming error */
12431 #define FLASH_SECSR_WRPERR_Pos              (4U)
12432 #define FLASH_SECSR_WRPERR_Msk              (0x1UL << FLASH_SECSR_WRPERR_Pos)       /*!< 0x00000010 */
12433 #define FLASH_SECSR_WRPERR                  FLASH_SECSR_WRPERR_Msk                  /*!< Secure write protection error */
12434 #define FLASH_SECSR_PGAERR_Pos              (5U)
12435 #define FLASH_SECSR_PGAERR_Msk              (0x1UL << FLASH_SECSR_PGAERR_Pos)       /*!< 0x00000020 */
12436 #define FLASH_SECSR_PGAERR                  FLASH_SECSR_PGAERR_Msk                  /*!< Secure programming alignment error */
12437 #define FLASH_SECSR_SIZERR_Pos              (6U)
12438 #define FLASH_SECSR_SIZERR_Msk              (0x1UL << FLASH_SECSR_SIZERR_Pos)       /*!< 0x00000040 */
12439 #define FLASH_SECSR_SIZERR                  FLASH_SECSR_SIZERR_Msk                  /*!< Secure size error */
12440 #define FLASH_SECSR_PGSERR_Pos              (7U)
12441 #define FLASH_SECSR_PGSERR_Msk              (0x1UL << FLASH_SECSR_PGSERR_Pos)       /*!< 0x00000080 */
12442 #define FLASH_SECSR_PGSERR                  FLASH_SECSR_PGSERR_Msk                  /*!< Secure programming sequence error */
12443 #define FLASH_SECSR_BSY_Pos                 (16U)
12444 #define FLASH_SECSR_BSY_Msk                 (0x1UL << FLASH_SECSR_BSY_Pos)          /*!< 0x00010000 */
12445 #define FLASH_SECSR_BSY                     FLASH_SECSR_BSY_Msk                     /*!< Secure busy */
12446 #define FLASH_SECSR_WDW_Pos                 (17U)
12447 #define FLASH_SECSR_WDW_Msk                 (0x1UL << FLASH_SECSR_WDW_Pos)          /*!< 0x00020000 */
12448 #define FLASH_SECSR_WDW                     FLASH_SECSR_WDW_Msk                     /*!< Secure wait data to write */
12449 
12450 /******************  Bits definition for FLASH_NSCR register  *****************/
12451 #define FLASH_NSCR_PG_Pos                   (0U)
12452 #define FLASH_NSCR_PG_Msk                   (0x1UL << FLASH_NSCR_PG_Pos)            /*!< 0x00000001 */
12453 #define FLASH_NSCR_PG                       FLASH_NSCR_PG_Msk                       /*!< Non-secure Programming */
12454 #define FLASH_NSCR_PER_Pos                  (1U)
12455 #define FLASH_NSCR_PER_Msk                  (0x1UL << FLASH_NSCR_PER_Pos)           /*!< 0x00000002 */
12456 #define FLASH_NSCR_PER                      FLASH_NSCR_PER_Msk                      /*!< Non-secure Page Erase */
12457 #define FLASH_NSCR_MER1_Pos                 (2U)
12458 #define FLASH_NSCR_MER1_Msk                 (0x1UL << FLASH_NSCR_MER1_Pos)          /*!< 0x00000004 */
12459 #define FLASH_NSCR_MER1                     FLASH_NSCR_MER1_Msk                     /*!< Non-secure Bank 1 Mass Erase */
12460 #define FLASH_NSCR_PNB_Pos                  (3U)
12461 #define FLASH_NSCR_PNB_Msk                  (0xFFUL << FLASH_NSCR_PNB_Pos)          /*!< 0x000007F8 */
12462 #define FLASH_NSCR_PNB                      FLASH_NSCR_PNB_Msk                      /*!< Non-secure Page Number selection */
12463 #define FLASH_NSCR_BKER_Pos                 (11U)
12464 #define FLASH_NSCR_BKER_Msk                 (0x1UL << FLASH_NSCR_BKER_Pos)          /*!< 0x00000800 */
12465 #define FLASH_NSCR_BKER                     FLASH_NSCR_BKER_Msk                     /*!< Non-secure Bank Selection for Page Erase */
12466 #define FLASH_NSCR_BWR_Pos                  (14U)
12467 #define FLASH_NSCR_BWR_Msk                  (0x1UL << FLASH_NSCR_BWR_Pos)           /*!< 0x00004000 */
12468 #define FLASH_NSCR_BWR                      FLASH_NSCR_BWR_Msk                      /*!< Non-secure Burst Write Programming mode */
12469 #define FLASH_NSCR_MER2_Pos                 (15U)
12470 #define FLASH_NSCR_MER2_Msk                 (0x1UL << FLASH_NSCR_MER2_Pos)          /*!< 0x00008000 */
12471 #define FLASH_NSCR_MER2                     FLASH_NSCR_MER2_Msk                     /*!< Non-secure Bank 2 Mass Erase */
12472 #define FLASH_NSCR_STRT_Pos                 (16U)
12473 #define FLASH_NSCR_STRT_Msk                 (0x1UL << FLASH_NSCR_STRT_Pos)          /*!< 0x00010000 */
12474 #define FLASH_NSCR_STRT                     FLASH_NSCR_STRT_Msk                     /*!< Non-secure Start */
12475 #define FLASH_NSCR_OPTSTRT_Pos              (17U)
12476 #define FLASH_NSCR_OPTSTRT_Msk              (0x1UL << FLASH_NSCR_OPTSTRT_Pos)       /*!< 0x00020000 */
12477 #define FLASH_NSCR_OPTSTRT                  FLASH_NSCR_OPTSTRT_Msk                  /*!< Option Modification Start */
12478 #define FLASH_NSCR_EOPIE_Pos                (24U)
12479 #define FLASH_NSCR_EOPIE_Msk                (0x1UL << FLASH_NSCR_EOPIE_Pos)         /*!< 0x01000000 */
12480 #define FLASH_NSCR_EOPIE                    FLASH_NSCR_EOPIE_Msk                    /*!< Non-secure End of operation interrupt enable */
12481 #define FLASH_NSCR_ERRIE_Pos                (25U)
12482 #define FLASH_NSCR_ERRIE_Msk                (0x1UL << FLASH_NSCR_ERRIE_Pos)         /*!< 0x02000000 */
12483 #define FLASH_NSCR_ERRIE                    FLASH_NSCR_ERRIE_Msk                    /*!< Non-secure error interrupt enable */
12484 #define FLASH_NSCR_OBL_LAUNCH_Pos           (27U)
12485 #define FLASH_NSCR_OBL_LAUNCH_Msk           (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos)    /*!< 0x08000000 */
12486 #define FLASH_NSCR_OBL_LAUNCH               FLASH_NSCR_OBL_LAUNCH_Msk               /*!< Force the option byte loading */
12487 #define FLASH_NSCR_OPTLOCK_Pos              (30U)
12488 #define FLASH_NSCR_OPTLOCK_Msk              (0x1UL << FLASH_NSCR_OPTLOCK_Pos)       /*!< 0x40000000 */
12489 #define FLASH_NSCR_OPTLOCK                  FLASH_NSCR_OPTLOCK_Msk                  /*!< Option Lock */
12490 #define FLASH_NSCR_LOCK_Pos                 (31U)
12491 #define FLASH_NSCR_LOCK_Msk                 (0x1UL << FLASH_NSCR_LOCK_Pos)          /*!< 0x80000000 */
12492 #define FLASH_NSCR_LOCK                     FLASH_NSCR_LOCK_Msk                     /*!< Non-secure Lock */
12493 
12494 /******************  Bits definition for FLASH_SECCR register  ****************/
12495 #define FLASH_SECCR_PG_Pos                  (0U)
12496 #define FLASH_SECCR_PG_Msk                  (0x1UL << FLASH_SECCR_PG_Pos)           /*!< 0x00000001 */
12497 #define FLASH_SECCR_PG                      FLASH_SECCR_PG_Msk                      /*!< Secure Programming */
12498 #define FLASH_SECCR_PER_Pos                 (1U)
12499 #define FLASH_SECCR_PER_Msk                 (0x1UL << FLASH_SECCR_PER_Pos)          /*!< 0x00000002 */
12500 #define FLASH_SECCR_PER                     FLASH_SECCR_PER_Msk                     /*!< Secure Page Erase */
12501 #define FLASH_SECCR_MER1_Pos                (2U)
12502 #define FLASH_SECCR_MER1_Msk                (0x1UL << FLASH_SECCR_MER1_Pos)         /*!< 0x00000004 */
12503 #define FLASH_SECCR_MER1                    FLASH_SECCR_MER1_Msk                    /*!< Secure Bank 1 Mass Erase */
12504 #define FLASH_SECCR_PNB_Pos                 (3U)
12505 #define FLASH_SECCR_PNB_Msk                 (0xFFUL << FLASH_SECCR_PNB_Pos)         /*!< 0x000007F8 */
12506 #define FLASH_SECCR_PNB                     FLASH_SECCR_PNB_Msk                     /*!< Secure Page Number selection */
12507 #define FLASH_SECCR_BKER_Pos                (11U)
12508 #define FLASH_SECCR_BKER_Msk                (0x1UL << FLASH_SECCR_BKER_Pos)         /*!< 0x00000800 */
12509 #define FLASH_SECCR_BKER                    FLASH_SECCR_BKER_Msk                    /*!< Secure Bank Selection for Page Erase */
12510 #define FLASH_SECCR_BWR_Pos                 (14U)
12511 #define FLASH_SECCR_BWR_Msk                 (0x1UL << FLASH_SECCR_BWR_Pos)          /*!< 0x00004000 */
12512 #define FLASH_SECCR_BWR                     FLASH_SECCR_BWR_Msk                     /*!< Secure Burst Write programming mode */
12513 #define FLASH_SECCR_MER2_Pos                (15U)
12514 #define FLASH_SECCR_MER2_Msk                (0x1UL << FLASH_SECCR_MER2_Pos)         /*!< 0x00008000 */
12515 #define FLASH_SECCR_MER2                    FLASH_SECCR_MER2_Msk                    /*!< Secure Bank 2 Mass Erase */
12516 #define FLASH_SECCR_STRT_Pos                (16U)
12517 #define FLASH_SECCR_STRT_Msk                (0x1UL << FLASH_SECCR_STRT_Pos)         /*!< 0x00010000 */
12518 #define FLASH_SECCR_STRT                    FLASH_SECCR_STRT_Msk                    /*!< Secure Start */
12519 #define FLASH_SECCR_EOPIE_Pos               (24U)
12520 #define FLASH_SECCR_EOPIE_Msk               (0x1UL << FLASH_SECCR_EOPIE_Pos)        /*!< 0x01000000 */
12521 #define FLASH_SECCR_EOPIE                   FLASH_SECCR_EOPIE_Msk                   /*!< Secure end of operation interrupt enable */
12522 #define FLASH_SECCR_ERRIE_Pos               (25U)
12523 #define FLASH_SECCR_ERRIE_Msk               (0x1UL << FLASH_SECCR_ERRIE_Pos)        /*!< 0x02000000 */
12524 #define FLASH_SECCR_ERRIE                   FLASH_SECCR_ERRIE_Msk                   /*!< Secure error interrupt enable */
12525 #define FLASH_SECCR_INV_Pos                 (29U)
12526 #define FLASH_SECCR_INV_Msk                 (0x1UL << FLASH_SECCR_INV_Pos)          /*!< 0x20000000 */
12527 #define FLASH_SECCR_INV                     FLASH_SECCR_INV_Msk                     /*!< Flash Security State Invert */
12528 #define FLASH_SECCR_LOCK_Pos                (31U)
12529 #define FLASH_SECCR_LOCK_Msk                (0x1UL << FLASH_SECCR_LOCK_Pos)         /*!< 0x80000000 */
12530 #define FLASH_SECCR_LOCK                    FLASH_SECCR_LOCK_Msk                    /*!< Secure Lock */
12531 
12532 /*******************  Bits definition for FLASH_ECCR register  ***************/
12533 #define FLASH_ECCR_ADDR_ECC_Pos             (0U)
12534 #define FLASH_ECCR_ADDR_ECC_Msk             (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */
12535 #define FLASH_ECCR_ADDR_ECC                 FLASH_ECCR_ADDR_ECC_Msk                 /*!< ECC fail address */
12536 #define FLASH_ECCR_BK_ECC_Pos               (21U)
12537 #define FLASH_ECCR_BK_ECC_Msk               (0x1UL << FLASH_ECCR_BK_ECC_Pos)        /*!< 0x00200000 */
12538 #define FLASH_ECCR_BK_ECC                   FLASH_ECCR_BK_ECC_Msk                   /*!< ECC fail bank */
12539 #define FLASH_ECCR_SYSF_ECC_Pos             (22U)
12540 #define FLASH_ECCR_SYSF_ECC_Msk             (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)      /*!< 0x00400000 */
12541 #define FLASH_ECCR_SYSF_ECC                 FLASH_ECCR_SYSF_ECC_Msk                 /*!< System Flash ECC fail */
12542 #define FLASH_ECCR_ECCIE_Pos                (24U)
12543 #define FLASH_ECCR_ECCIE_Msk                (0x1UL << FLASH_ECCR_ECCIE_Pos)         /*!< 0x01000000 */
12544 #define FLASH_ECCR_ECCIE                    FLASH_ECCR_ECCIE_Msk                    /*!< ECC correction interrupt enable */
12545 #define FLASH_ECCR_ECCC_Pos                 (30U)
12546 #define FLASH_ECCR_ECCC_Msk                 (0x1UL << FLASH_ECCR_ECCC_Pos)          /*!< 0x40000000 */
12547 #define FLASH_ECCR_ECCC                     FLASH_ECCR_ECCC_Msk                     /*!< ECC correction */
12548 #define FLASH_ECCR_ECCD_Pos                 (31U)
12549 #define FLASH_ECCR_ECCD_Msk                 (0x1UL << FLASH_ECCR_ECCD_Pos)          /*!< 0x80000000 */
12550 #define FLASH_ECCR_ECCD                     FLASH_ECCR_ECCD_Msk                     /*!< ECC detection */
12551 
12552 /*******************  Bits definition for FLASH_OPSR register  ***************/
12553 #define FLASH_OPSR_ADDR_OP_Pos              (0U)
12554 #define FLASH_OPSR_ADDR_OP_Msk              (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos)  /*!< 0x001FFFFF */
12555 #define FLASH_OPSR_ADDR_OP                  FLASH_OPSR_ADDR_OP_Msk                  /*!< Flash operation address */
12556 #define FLASH_OPSR_BK_OP_Pos                (21U)
12557 #define FLASH_OPSR_BK_OP_Msk                (0x1UL << FLASH_OPSR_BK_OP_Pos)         /*!< 0x00200000 */
12558 #define FLASH_OPSR_BK_OP                    FLASH_OPSR_BK_OP_Msk                    /*!< Interrupted operation bank */
12559 #define FLASH_OPSR_SYSF_OP_Pos              (22U)
12560 #define FLASH_OPSR_SYSF_OP_Msk              (0x1UL << FLASH_OPSR_SYSF_OP_Pos)       /*!< 0x00400000 */
12561 #define FLASH_OPSR_SYSF_OP                  FLASH_OPSR_SYSF_OP_Msk                  /*!< Operation in System Flash interrupted */
12562 #define FLASH_OPSR_CODE_OP_Pos              (29U)
12563 #define FLASH_OPSR_CODE_OP_Msk              (0x7UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0xE0000000 */
12564 #define FLASH_OPSR_CODE_OP                  FLASH_OPSR_CODE_OP_Msk                  /*!< Flash operation code */
12565 #define FLASH_OPSR_CODE_OP_0                (0x1UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x20000000 */
12566 #define FLASH_OPSR_CODE_OP_1                (0x2UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x40000000 */
12567 #define FLASH_OPSR_CODE_OP_2                (0x4UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x80000000 */
12568 
12569 /*******************  Bits definition for FLASH_OPTR register  ***************/
12570 #define FLASH_OPTR_RDP_Pos                  (0U)
12571 #define FLASH_OPTR_RDP_Msk                  (0xFFUL << FLASH_OPTR_RDP_Pos)          /*!< 0x000000FF */
12572 #define FLASH_OPTR_RDP                      FLASH_OPTR_RDP_Msk                      /*!< Readout protection level */
12573 #define FLASH_OPTR_BOR_LEV_Pos              (8U)
12574 #define FLASH_OPTR_BOR_LEV_Msk              (0x7UL << FLASH_OPTR_BOR_LEV_Pos)       /*!< 0x00000700 */
12575 #define FLASH_OPTR_BOR_LEV                  FLASH_OPTR_BOR_LEV_Msk                  /*!< BOR reset Level */
12576 #define FLASH_OPTR_BOR_LEV_0                (0x1UL << FLASH_OPTR_BOR_LEV_Pos)       /*!< 0x00000100 */
12577 #define FLASH_OPTR_BOR_LEV_1                (0x2UL << FLASH_OPTR_BOR_LEV_Pos)       /*!< 0x00000200 */
12578 #define FLASH_OPTR_BOR_LEV_2                (0x4UL << FLASH_OPTR_BOR_LEV_Pos)       /*!< 0x00000400 */
12579 #define FLASH_OPTR_nRST_STOP_Pos            (12U)
12580 #define FLASH_OPTR_nRST_STOP_Msk            (0x1UL << FLASH_OPTR_nRST_STOP_Pos)     /*!< 0x00001000 */
12581 #define FLASH_OPTR_nRST_STOP                FLASH_OPTR_nRST_STOP_Msk                /*!< nRST_STOP */
12582 #define FLASH_OPTR_nRST_STDBY_Pos           (13U)
12583 #define FLASH_OPTR_nRST_STDBY_Msk           (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)    /*!< 0x00002000 */
12584 #define FLASH_OPTR_nRST_STDBY               FLASH_OPTR_nRST_STDBY_Msk               /*!< nRST_STDBY */
12585 #define FLASH_OPTR_nRST_SHDW_Pos            (14U)
12586 #define FLASH_OPTR_nRST_SHDW_Msk            (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)     /*!< 0x00004000 */
12587 #define FLASH_OPTR_nRST_SHDW                FLASH_OPTR_nRST_SHDW_Msk                /*!< nRST_SHDW */
12588 #define FLASH_OPTR_SRAM_RST_Pos             (15U)
12589 #define FLASH_OPTR_SRAM_RST_Msk             (0x1UL << FLASH_OPTR_SRAM_RST_Pos)      /*!< 0x00008000 */
12590 #define FLASH_OPTR_SRAM_RST                 FLASH_OPTR_SRAM_RST_Msk                 /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */
12591 #define FLASH_OPTR_IWDG_SW_Pos              (16U)
12592 #define FLASH_OPTR_IWDG_SW_Msk              (0x1UL << FLASH_OPTR_IWDG_SW_Pos)       /*!< 0x00010000 */
12593 #define FLASH_OPTR_IWDG_SW                  FLASH_OPTR_IWDG_SW_Msk                  /*!< Independent watchdog selection */
12594 #define FLASH_OPTR_IWDG_STOP_Pos            (17U)
12595 #define FLASH_OPTR_IWDG_STOP_Msk            (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)     /*!< 0x00020000 */
12596 #define FLASH_OPTR_IWDG_STOP                FLASH_OPTR_IWDG_STOP_Msk                /*!< Independent watchdog counter freeze in Stop mode */
12597 #define FLASH_OPTR_IWDG_STDBY_Pos           (18U)
12598 #define FLASH_OPTR_IWDG_STDBY_Msk           (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)    /*!< 0x00040000 */
12599 #define FLASH_OPTR_IWDG_STDBY               FLASH_OPTR_IWDG_STDBY_Msk               /*!< Independent watchdog counter freeze in Standby mode */
12600 #define FLASH_OPTR_WWDG_SW_Pos              (19U)
12601 #define FLASH_OPTR_WWDG_SW_Msk              (0x1UL << FLASH_OPTR_WWDG_SW_Pos)       /*!< 0x00080000 */
12602 #define FLASH_OPTR_WWDG_SW                  FLASH_OPTR_WWDG_SW_Msk                  /*!< Window watchdog selection */
12603 #define FLASH_OPTR_SWAP_BANK_Pos            (20U)
12604 #define FLASH_OPTR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTR_SWAP_BANK_Pos)     /*!< 0x00100000 */
12605 #define FLASH_OPTR_SWAP_BANK                FLASH_OPTR_SWAP_BANK_Msk                /*!< Swap banks */
12606 #define FLASH_OPTR_DUALBANK_Pos             (21U)
12607 #define FLASH_OPTR_DUALBANK_Msk             (0x1UL << FLASH_OPTR_DUALBANK_Pos)      /*!< 0x00200000 */
12608 #define FLASH_OPTR_DUALBANK                 FLASH_OPTR_DUALBANK_Msk                 /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */
12609 #define FLASH_OPTR_BKPRAM_ECC_Pos           (22U)
12610 #define FLASH_OPTR_BKPRAM_ECC_Msk           (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos)    /*!< 0x00400000 */
12611 #define FLASH_OPTR_BKPRAM_ECC               FLASH_OPTR_BKPRAM_ECC_Msk               /*!< Backup RAM ECC detection and correction enable */
12612 #define FLASH_OPTR_SRAM3_ECC_Pos            (23U)
12613 #define FLASH_OPTR_SRAM3_ECC_Msk            (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos)     /*!< 0x00800000 */
12614 #define FLASH_OPTR_SRAM3_ECC                FLASH_OPTR_SRAM3_ECC_Msk                /*!< SRAM3 ECC detection and correction enable */
12615 #define FLASH_OPTR_SRAM2_ECC_Pos            (24U)
12616 #define FLASH_OPTR_SRAM2_ECC_Msk            (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos)     /*!< 0x01000000 */
12617 #define FLASH_OPTR_SRAM2_ECC                FLASH_OPTR_SRAM2_ECC_Msk                /*!< SRAM2 ECC detection and correction enable*/
12618 #define FLASH_OPTR_SRAM2_RST_Pos            (25U)
12619 #define FLASH_OPTR_SRAM2_RST_Msk            (0x1UL << FLASH_OPTR_SRAM2_RST_Pos)     /*!< 0x02000000 */
12620 #define FLASH_OPTR_SRAM2_RST                FLASH_OPTR_SRAM2_RST_Msk                /*!< SRAM2 erase when system reset */
12621 #define FLASH_OPTR_nSWBOOT0_Pos             (26U)
12622 #define FLASH_OPTR_nSWBOOT0_Msk             (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)      /*!< 0x04000000 */
12623 #define FLASH_OPTR_nSWBOOT0                 FLASH_OPTR_nSWBOOT0_Msk                 /*!< Software BOOT0 */
12624 #define FLASH_OPTR_nBOOT0_Pos               (27U)
12625 #define FLASH_OPTR_nBOOT0_Msk               (0x1UL << FLASH_OPTR_nBOOT0_Pos)        /*!< 0x08000000 */
12626 #define FLASH_OPTR_nBOOT0                   FLASH_OPTR_nBOOT0_Msk                   /*!< nBOOT0 option bit */
12627 #define FLASH_OPTR_PA15_PUPEN_Pos           (28U)
12628 #define FLASH_OPTR_PA15_PUPEN_Msk           (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos)    /*!< 0x10000000 */
12629 #define FLASH_OPTR_PA15_PUPEN               FLASH_OPTR_PA15_PUPEN_Msk               /*!< PA15 pull-up enable */
12630 #define FLASH_OPTR_IO_VDD_HSLV_Pos          (29U)
12631 #define FLASH_OPTR_IO_VDD_HSLV_Msk          (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos)   /*!< 0x20000000 */
12632 #define FLASH_OPTR_IO_VDD_HSLV              FLASH_OPTR_IO_VDD_HSLV_Msk              /*!< High speed IO at low voltage configuration bit */
12633 #define FLASH_OPTR_IO_VDDIO2_HSLV_Pos       (30U)
12634 #define FLASH_OPTR_IO_VDDIO2_HSLV_Msk       (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */
12635 #define FLASH_OPTR_IO_VDDIO2_HSLV           FLASH_OPTR_IO_VDDIO2_HSLV_Msk           /*!< High speed IO at low VDDIO2 voltage configuration bit */
12636 #define FLASH_OPTR_TZEN_Pos                 (31U)
12637 #define FLASH_OPTR_TZEN_Msk                 (0x1UL << FLASH_OPTR_TZEN_Pos)          /*!< 0x80000000 */
12638 #define FLASH_OPTR_TZEN                     FLASH_OPTR_TZEN_Msk                     /*!< Global TrustZone security enable */
12639 
12640 /****************  Bits definition for FLASH_NSBOOTADD0R register  ************/
12641 #define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos    (7U)
12642 #define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk    (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */
12643 #define FLASH_NSBOOTADD0R_NSBOOTADD0        FLASH_NSBOOTADD0R_NSBOOTADD0_Msk        /*!< Non-secure boot address 0 */
12644 
12645 /****************  Bits definition for FLASH_NSBOOTADD1R register  ************/
12646 #define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos    (7U)
12647 #define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk    (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */
12648 #define FLASH_NSBOOTADD1R_NSBOOTADD1        FLASH_NSBOOTADD1R_NSBOOTADD1_Msk        /*!< Non-secure boot address 1 */
12649 
12650 /****************  Bits definition for FLASH_SECBOOTADD0R register  ***********/
12651 #define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos    (0U)
12652 #define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk    (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */
12653 #define FLASH_SECBOOTADD0R_BOOT_LOCK        FLASH_SECBOOTADD0R_BOOT_LOCK_Msk        /*!< Boot Lock */
12654 #define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos  (7U)
12655 #define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk  (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */
12656 #define FLASH_SECBOOTADD0R_SECBOOTADD0      FLASH_SECBOOTADD0R_SECBOOTADD0_Msk      /*!< Secure boot address 0 */
12657 
12658 /*****************  Bits definition for FLASH_SECWM1R1 register  **************/
12659 #define FLASH_SECWM1R1_SECWM1_PSTRT_Pos     (0U)
12660 #define FLASH_SECWM1R1_SECWM1_PSTRT_Msk     (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */
12661 #define FLASH_SECWM1R1_SECWM1_PSTRT         FLASH_SECWM1R1_SECWM1_PSTRT_Msk         /*!< Start page of first secure area */
12662 #define FLASH_SECWM1R1_SECWM1_PEND_Pos      (16U)
12663 #define FLASH_SECWM1R1_SECWM1_PEND_Msk      (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */
12664 #define FLASH_SECWM1R1_SECWM1_PEND          FLASH_SECWM1R1_SECWM1_PEND_Msk          /*!< End page of first secure area */
12665 
12666 /*****************  Bits definition for FLASH_SECWM1R2 register  **************/
12667 #define FLASH_SECWM1R2_HDP1_PEND_Pos        (16U)
12668 #define FLASH_SECWM1R2_HDP1_PEND_Msk        (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */
12669 #define FLASH_SECWM1R2_HDP1_PEND            FLASH_SECWM1R2_HDP1_PEND_Msk            /*!< End page of first hide protection area */
12670 #define FLASH_SECWM1R2_HDP1EN_Pos           (31U)
12671 #define FLASH_SECWM1R2_HDP1EN_Msk           (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos)    /*!< 0x80000000 */
12672 #define FLASH_SECWM1R2_HDP1EN               FLASH_SECWM1R2_HDP1EN_Msk               /*!< Hide protection first area enable */
12673 
12674 /******************  Bits definition for FLASH_WRP1AR register  ***************/
12675 #define FLASH_WRP1AR_WRP1A_PSTRT_Pos        (0U)
12676 #define FLASH_WRP1AR_WRP1A_PSTRT_Msk        (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */
12677 #define FLASH_WRP1AR_WRP1A_PSTRT            FLASH_WRP1AR_WRP1A_PSTRT_Msk            /*!< Bank 1 WPR first area A start page */
12678 #define FLASH_WRP1AR_WRP1A_PEND_Pos         (16U)
12679 #define FLASH_WRP1AR_WRP1A_PEND_Msk         (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */
12680 #define FLASH_WRP1AR_WRP1A_PEND             FLASH_WRP1AR_WRP1A_PEND_Msk             /*!< Bank 1 WPR first area A end page */
12681 #define FLASH_WRP1AR_UNLOCK_Pos             (31U)
12682 #define FLASH_WRP1AR_UNLOCK_Msk             (0x1UL << FLASH_WRP1AR_UNLOCK_Pos)      /*!< 0x80000000 */
12683 #define FLASH_WRP1AR_UNLOCK                 FLASH_WRP1AR_UNLOCK_Msk                 /*!< Bank 1 WPR first area A unlock */
12684 
12685 /******************  Bits definition for FLASH_WRP1BR register  ***************/
12686 #define FLASH_WRP1BR_WRP1B_PSTRT_Pos        (0U)
12687 #define FLASH_WRP1BR_WRP1B_PSTRT_Msk        (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */
12688 #define FLASH_WRP1BR_WRP1B_PSTRT            FLASH_WRP1BR_WRP1B_PSTRT_Msk            /*!< Bank 1 WPR second area B start page */
12689 #define FLASH_WRP1BR_WRP1B_PEND_Pos         (16U)
12690 #define FLASH_WRP1BR_WRP1B_PEND_Msk         (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */
12691 #define FLASH_WRP1BR_WRP1B_PEND             FLASH_WRP1BR_WRP1B_PEND_Msk             /*!< Bank 1 WPR second area B end page */
12692 #define FLASH_WRP1BR_UNLOCK_Pos             (31U)
12693 #define FLASH_WRP1BR_UNLOCK_Msk             (0x1UL << FLASH_WRP1BR_UNLOCK_Pos)      /*!< 0x80000000 */
12694 #define FLASH_WRP1BR_UNLOCK                 FLASH_WRP1BR_UNLOCK_Msk                 /*!< Bank 1 WPR first area B unlock */
12695 
12696 /*****************  Bits definition for FLASH_SECWM2R1 register  **************/
12697 #define FLASH_SECWM2R1_SECWM2_PSTRT_Pos     (0U)
12698 #define FLASH_SECWM2R1_SECWM2_PSTRT_Msk     (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */
12699 #define FLASH_SECWM2R1_SECWM2_PSTRT         FLASH_SECWM2R1_SECWM2_PSTRT_Msk         /*!< Start page of second secure area */
12700 #define FLASH_SECWM2R1_SECWM2_PEND_Pos      (16U)
12701 #define FLASH_SECWM2R1_SECWM2_PEND_Msk      (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */
12702 #define FLASH_SECWM2R1_SECWM2_PEND          FLASH_SECWM2R1_SECWM2_PEND_Msk          /*!< End page of second secure area */
12703 
12704 /*****************  Bits definition for FLASH_SECWM2R2 register  **************/
12705 #define FLASH_SECWM2R2_HDP2_PEND_Pos        (16U)
12706 #define FLASH_SECWM2R2_HDP2_PEND_Msk        (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */
12707 #define FLASH_SECWM2R2_HDP2_PEND            FLASH_SECWM2R2_HDP2_PEND_Msk            /*!< End page of hide protection second area */
12708 #define FLASH_SECWM2R2_HDP2EN_Pos           (31U)
12709 #define FLASH_SECWM2R2_HDP2EN_Msk           (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos)    /*!< 0x80000000 */
12710 #define FLASH_SECWM2R2_HDP2EN               FLASH_SECWM2R2_HDP2EN_Msk               /*!< Hide protection second area enable */
12711 
12712 /******************  Bits definition for FLASH_WRP2AR register  ***************/
12713 #define FLASH_WRP2AR_WRP2A_PSTRT_Pos        (0U)
12714 #define FLASH_WRP2AR_WRP2A_PSTRT_Msk        (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */
12715 #define FLASH_WRP2AR_WRP2A_PSTRT            FLASH_WRP2AR_WRP2A_PSTRT_Msk            /*!< Bank 2 WPR first area A start page */
12716 #define FLASH_WRP2AR_WRP2A_PEND_Pos         (16U)
12717 #define FLASH_WRP2AR_WRP2A_PEND_Msk         (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */
12718 #define FLASH_WRP2AR_WRP2A_PEND             FLASH_WRP2AR_WRP2A_PEND_Msk             /*!< Bank 2 WPR first area A end page */
12719 #define FLASH_WRP2AR_UNLOCK_Pos             (31U)
12720 #define FLASH_WRP2AR_UNLOCK_Msk             (0x1UL << FLASH_WRP2AR_UNLOCK_Pos)      /*!< 0x80000000 */
12721 #define FLASH_WRP2AR_UNLOCK                 FLASH_WRP2AR_UNLOCK_Msk                 /*!< Bank 2 WPR first area A unlock */
12722 
12723 /******************  Bits definition for FLASH_WRP2BR register  ***************/
12724 #define FLASH_WRP2BR_WRP2B_PSTRT_Pos        (0U)
12725 #define FLASH_WRP2BR_WRP2B_PSTRT_Msk        (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */
12726 #define FLASH_WRP2BR_WRP2B_PSTRT            FLASH_WRP2BR_WRP2B_PSTRT_Msk            /*!< Bank 2 WPR first area B start page */
12727 #define FLASH_WRP2BR_WRP2B_PEND_Pos         (16U)
12728 #define FLASH_WRP2BR_WRP2B_PEND_Msk         (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */
12729 #define FLASH_WRP2BR_WRP2B_PEND             FLASH_WRP2BR_WRP2B_PEND_Msk             /*!< Bank 2 WPR first area B end page */
12730 #define FLASH_WRP2BR_UNLOCK_Pos             (31U)
12731 #define FLASH_WRP2BR_UNLOCK_Msk             (0x1UL << FLASH_WRP2BR_UNLOCK_Pos)      /*!< 0x80000000 */
12732 #define FLASH_WRP2BR_UNLOCK                 FLASH_WRP2BR_UNLOCK_Msk                 /*!< Bank 2 WPR first area B unlock */
12733 
12734 /******************  Bits definition for FLASH_SECHDPCR register  ***********/
12735 #define FLASH_SECHDPCR_HDP1_ACCDIS_Pos      (0U)
12736 #define FLASH_SECHDPCR_HDP1_ACCDIS_Msk      (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */
12737 #define FLASH_SECHDPCR_HDP1_ACCDIS          FLASH_SECHDPCR_HDP1_ACCDIS_Msk          /*!< HDP1 area access disable */
12738 #define FLASH_SECHDPCR_HDP2_ACCDIS_Pos      (1U)
12739 #define FLASH_SECHDPCR_HDP2_ACCDIS_Msk      (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */
12740 #define FLASH_SECHDPCR_HDP2_ACCDIS          FLASH_SECHDPCR_HDP2_ACCDIS_Msk          /*!< HDP2 area access disable */
12741 
12742 /******************  Bits definition for FLASH_PRIVCFGR register  ***********/
12743 #define FLASH_PRIVCFGR_SPRIV_Pos            (0U)
12744 #define FLASH_PRIVCFGR_SPRIV_Msk            (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos)     /*!< 0x00000001 */
12745 #define FLASH_PRIVCFGR_SPRIV                FLASH_PRIVCFGR_SPRIV_Msk                /*!< Privilege protection for secure registers */
12746 #define FLASH_PRIVCFGR_NSPRIV_Pos           (1U)
12747 #define FLASH_PRIVCFGR_NSPRIV_Msk           (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos)    /*!< 0x00000002 */
12748 #define FLASH_PRIVCFGR_NSPRIV               FLASH_PRIVCFGR_NSPRIV_Msk               /*!< Privilege protection for non-secure registers */
12749 
12750 /******************************************************************************/
12751 /*                                                                            */
12752 /*                Filter Mathematical ACcelerator unit (FMAC)                 */
12753 /*                                                                            */
12754 /******************************************************************************/
12755 /*****************  Bit definition for FMAC_X1BUFCFG register  ****************/
12756 #define FMAC_X1BUFCFG_X1_BASE_Pos           (0U)
12757 #define FMAC_X1BUFCFG_X1_BASE_Msk           (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)   /*!< 0x000000FF */
12758 #define FMAC_X1BUFCFG_X1_BASE               FMAC_X1BUFCFG_X1_BASE_Msk               /*!< Base address of X1 buffer */
12759 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos       (8U)
12760 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk       (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */
12761 #define FMAC_X1BUFCFG_X1_BUF_SIZE           FMAC_X1BUFCFG_X1_BUF_SIZE_Msk           /*!< Allocated size of X1 buffer in 16-bit words */
12762 #define FMAC_X1BUFCFG_FULL_WM_Pos           (24U)
12763 #define FMAC_X1BUFCFG_FULL_WM_Msk           (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos)    /*!< 0x03000000 */
12764 #define FMAC_X1BUFCFG_FULL_WM               FMAC_X1BUFCFG_FULL_WM_Msk               /*!< Watermark for buffer full flag */
12765 
12766 /*****************  Bit definition for FMAC_X2BUFCFG register  ****************/
12767 #define FMAC_X2BUFCFG_X2_BASE_Pos           (0U)
12768 #define FMAC_X2BUFCFG_X2_BASE_Msk           (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)   /*!< 0x000000FF */
12769 #define FMAC_X2BUFCFG_X2_BASE               FMAC_X2BUFCFG_X2_BASE_Msk               /*!< Base address of X2 buffer */
12770 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos       (8U)
12771 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk       (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */
12772 #define FMAC_X2BUFCFG_X2_BUF_SIZE           FMAC_X2BUFCFG_X2_BUF_SIZE_Msk           /*!< Size of X2 buffer in 16-bit words */
12773 
12774 /*****************  Bit definition for FMAC_YBUFCFG register  *****************/
12775 #define FMAC_YBUFCFG_Y_BASE_Pos             (0U)
12776 #define FMAC_YBUFCFG_Y_BASE_Msk             (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)     /*!< 0x000000FF */
12777 #define FMAC_YBUFCFG_Y_BASE                 FMAC_YBUFCFG_Y_BASE_Msk                 /*!< Base address of Y buffer */
12778 #define FMAC_YBUFCFG_Y_BUF_SIZE_Pos         (8U)
12779 #define FMAC_YBUFCFG_Y_BUF_SIZE_Msk         (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
12780 #define FMAC_YBUFCFG_Y_BUF_SIZE             FMAC_YBUFCFG_Y_BUF_SIZE_Msk             /*!< Size of Y buffer in 16-bit words */
12781 #define FMAC_YBUFCFG_EMPTY_WM_Pos           (24U)
12782 #define FMAC_YBUFCFG_EMPTY_WM_Msk           (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos)    /*!< 0x03000000 */
12783 #define FMAC_YBUFCFG_EMPTY_WM               FMAC_YBUFCFG_EMPTY_WM_Msk               /*!< Watermark for buffer empty flag */
12784 
12785 /******************  Bit definition for FMAC_PARAM register  ******************/
12786 #define FMAC_PARAM_P_Pos                    (0U)
12787 #define FMAC_PARAM_P_Msk                    (0xFFUL << FMAC_PARAM_P_Pos)            /*!< 0x000000FF */
12788 #define FMAC_PARAM_P                        FMAC_PARAM_P_Msk                        /*!< Input parameter P */
12789 #define FMAC_PARAM_Q_Pos                    (8U)
12790 #define FMAC_PARAM_Q_Msk                    (0xFFUL << FMAC_PARAM_Q_Pos)            /*!< 0x0000FF00 */
12791 #define FMAC_PARAM_Q                        FMAC_PARAM_Q_Msk                        /*!< Input parameter Q */
12792 #define FMAC_PARAM_R_Pos                    (16U)
12793 #define FMAC_PARAM_R_Msk                    (0xFFUL << FMAC_PARAM_R_Pos)            /*!< 0x00FF0000 */
12794 #define FMAC_PARAM_R                        FMAC_PARAM_R_Msk                        /*!< Input parameter R */
12795 #define FMAC_PARAM_FUNC_Pos                 (24U)
12796 #define FMAC_PARAM_FUNC_Msk                 (0x7FUL << FMAC_PARAM_FUNC_Pos)         /*!< 0x7F000000 */
12797 #define FMAC_PARAM_FUNC                     FMAC_PARAM_FUNC_Msk                     /*!< Function */
12798 #define FMAC_PARAM_FUNC_0                   (0x1UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x01000000 */
12799 #define FMAC_PARAM_FUNC_1                   (0x2UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x02000000 */
12800 #define FMAC_PARAM_FUNC_2                   (0x4UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x04000000 */
12801 #define FMAC_PARAM_FUNC_3                   (0x8UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x08000000 */
12802 #define FMAC_PARAM_FUNC_4                   (0x10UL << FMAC_PARAM_FUNC_Pos)         /*!< 0x10000000 */
12803 #define FMAC_PARAM_FUNC_5                   (0x20UL << FMAC_PARAM_FUNC_Pos)         /*!< 0x20000000 */
12804 #define FMAC_PARAM_FUNC_6                   (0x40UL << FMAC_PARAM_FUNC_Pos)         /*!< 0x40000000 */
12805 #define FMAC_PARAM_START_Pos                (31U)
12806 #define FMAC_PARAM_START_Msk                (0x1UL << FMAC_PARAM_START_Pos)         /*!< 0x80000000 */
12807 #define FMAC_PARAM_START                    FMAC_PARAM_START_Msk                    /*!< Enable execution */
12808 
12809 /********************  Bit definition for FMAC_CR register  *******************/
12810 #define FMAC_CR_RIEN_Pos                    (0U)
12811 #define FMAC_CR_RIEN_Msk                    (0x1UL << FMAC_CR_RIEN_Pos)             /*!< 0x00000001 */
12812 #define FMAC_CR_RIEN                        FMAC_CR_RIEN_Msk                        /*!< Enable read interrupt */
12813 #define FMAC_CR_WIEN_Pos                    (1U)
12814 #define FMAC_CR_WIEN_Msk                    (0x1UL << FMAC_CR_WIEN_Pos)             /*!< 0x00000002 */
12815 #define FMAC_CR_WIEN                        FMAC_CR_WIEN_Msk                        /*!< Enable write interrupt */
12816 #define FMAC_CR_OVFLIEN_Pos                 (2U)
12817 #define FMAC_CR_OVFLIEN_Msk                 (0x1UL << FMAC_CR_OVFLIEN_Pos)          /*!< 0x00000004 */
12818 #define FMAC_CR_OVFLIEN                     FMAC_CR_OVFLIEN_Msk                     /*!< Enable overflow error interrupts */
12819 #define FMAC_CR_UNFLIEN_Pos                 (3U)
12820 #define FMAC_CR_UNFLIEN_Msk                 (0x1UL << FMAC_CR_UNFLIEN_Pos)          /*!< 0x00000008 */
12821 #define FMAC_CR_UNFLIEN                     FMAC_CR_UNFLIEN_Msk                     /*!< Enable underflow error interrupts */
12822 #define FMAC_CR_SATIEN_Pos                  (4U)
12823 #define FMAC_CR_SATIEN_Msk                  (0x1UL << FMAC_CR_SATIEN_Pos)           /*!< 0x00000010 */
12824 #define FMAC_CR_SATIEN                      FMAC_CR_SATIEN_Msk                      /*!< Enable saturation error interrupts */
12825 #define FMAC_CR_DMAREN_Pos                  (8U)
12826 #define FMAC_CR_DMAREN_Msk                  (0x1UL << FMAC_CR_DMAREN_Pos)           /*!< 0x00000100 */
12827 #define FMAC_CR_DMAREN                      FMAC_CR_DMAREN_Msk                      /*!< Enable DMA read channel requests */
12828 #define FMAC_CR_DMAWEN_Pos                  (9U)
12829 #define FMAC_CR_DMAWEN_Msk                  (0x1UL << FMAC_CR_DMAWEN_Pos)           /*!< 0x00000200 */
12830 #define FMAC_CR_DMAWEN                      FMAC_CR_DMAWEN_Msk                      /*!< Enable DMA write channel requests */
12831 #define FMAC_CR_CLIPEN_Pos                  (15U)
12832 #define FMAC_CR_CLIPEN_Msk                  (0x1UL << FMAC_CR_CLIPEN_Pos)           /*!< 0x00008000 */
12833 #define FMAC_CR_CLIPEN                      FMAC_CR_CLIPEN_Msk                      /*!< Enable clipping */
12834 #define FMAC_CR_RESET_Pos                   (16U)
12835 #define FMAC_CR_RESET_Msk                   (0x1UL << FMAC_CR_RESET_Pos)            /*!< 0x00010000 */
12836 #define FMAC_CR_RESET                       FMAC_CR_RESET_Msk                       /*!< Reset filter mathematical accelerator unit */
12837 
12838 /*******************  Bit definition for FMAC_SR register  ********************/
12839 #define FMAC_SR_YEMPTY_Pos                  (0U)
12840 #define FMAC_SR_YEMPTY_Msk                  (0x1UL << FMAC_SR_YEMPTY_Pos)           /*!< 0x00000001 */
12841 #define FMAC_SR_YEMPTY                      FMAC_SR_YEMPTY_Msk                      /*!< Y buffer empty flag */
12842 #define FMAC_SR_X1FULL_Pos                  (1U)
12843 #define FMAC_SR_X1FULL_Msk                  (0x1UL << FMAC_SR_X1FULL_Pos)           /*!< 0x00000002 */
12844 #define FMAC_SR_X1FULL                      FMAC_SR_X1FULL_Msk                      /*!< X1 buffer full flag */
12845 #define FMAC_SR_OVFL_Pos                    (8U)
12846 #define FMAC_SR_OVFL_Msk                    (0x1UL << FMAC_SR_OVFL_Pos)             /*!< 0x00000100 */
12847 #define FMAC_SR_OVFL                        FMAC_SR_OVFL_Msk                        /*!< Overflow error flag */
12848 #define FMAC_SR_UNFL_Pos                    (9U)
12849 #define FMAC_SR_UNFL_Msk                    (0x1UL << FMAC_SR_UNFL_Pos)             /*!< 0x00000200 */
12850 #define FMAC_SR_UNFL                        FMAC_SR_UNFL_Msk                        /*!< Underflow error flag */
12851 #define FMAC_SR_SAT_Pos                     (10U)
12852 #define FMAC_SR_SAT_Msk                     (0x1UL << FMAC_SR_SAT_Pos)              /*!< 0x00000400 */
12853 #define FMAC_SR_SAT                         FMAC_SR_SAT_Msk                         /*!< Saturation error flag */
12854 
12855 /******************  Bit definition for FMAC_WDATA register  ******************/
12856 #define FMAC_WDATA_WDATA_Pos                (0U)
12857 #define FMAC_WDATA_WDATA_Msk                (0xFFFFUL << FMAC_WDATA_WDATA_Pos)      /*!< 0x0000FFFF */
12858 #define FMAC_WDATA_WDATA                    FMAC_WDATA_WDATA_Msk                    /*!< Write data */
12859 
12860 /******************  Bit definition for FMACX_RDATA register  *****************/
12861 #define FMAC_RDATA_RDATA_Pos                (0U)
12862 #define FMAC_RDATA_RDATA_Msk                (0xFFFFUL << FMAC_RDATA_RDATA_Pos)      /*!< 0x0000FFFF */
12863 #define FMAC_RDATA_RDATA                    FMAC_RDATA_RDATA_Msk                    /*!< Read data */
12864 
12865 /******************************************************************************/
12866 /*                                                                            */
12867 /*                          Flexible Memory Controller                        */
12868 /*                                                                            */
12869 /******************************************************************************/
12870 /******************  Bit definition for FMC_BCR1 register  *******************/
12871 #define FMC_BCR1_CCLKEN_Pos                 (20U)
12872 #define FMC_BCR1_CCLKEN_Msk                 (0x1UL << FMC_BCR1_CCLKEN_Pos)          /*!< 0x00100000 */
12873 #define FMC_BCR1_CCLKEN                     FMC_BCR1_CCLKEN_Msk                     /*!<Continuous clock enable     */
12874 #define FMC_BCR1_WFDIS_Pos                  (21U)
12875 #define FMC_BCR1_WFDIS_Msk                  (0x1UL << FMC_BCR1_WFDIS_Pos)           /*!< 0x00200000 */
12876 #define FMC_BCR1_WFDIS                      FMC_BCR1_WFDIS_Msk                      /*!<Write FIFO Disable         */
12877 #define FMC_BCR1_FMCEN_Pos                  (31U)
12878 #define FMC_BCR1_FMCEN_Msk                  (0x1UL << FMC_BCR1_FMCEN_Pos)           /*!< 0x80000000 */
12879 #define FMC_BCR1_FMCEN                      FMC_BCR1_FMCEN_Msk                      /*!<FMC controller Enable */
12880 
12881 /******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
12882 #define FMC_BCRx_MBKEN_Pos                  (0U)
12883 #define FMC_BCRx_MBKEN_Msk                  (0x1UL << FMC_BCRx_MBKEN_Pos)           /*!< 0x00000001 */
12884 #define FMC_BCRx_MBKEN                      FMC_BCRx_MBKEN_Msk                      /*!<Memory bank enable bit                 */
12885 #define FMC_BCRx_MUXEN_Pos                  (1U)
12886 #define FMC_BCRx_MUXEN_Msk                  (0x1UL << FMC_BCRx_MUXEN_Pos)           /*!< 0x00000002 */
12887 #define FMC_BCRx_MUXEN                      FMC_BCRx_MUXEN_Msk                      /*!<Address/data multiplexing enable bit   */
12888 #define FMC_BCRx_MTYP_Pos                   (2U)
12889 #define FMC_BCRx_MTYP_Msk                   (0x3UL << FMC_BCRx_MTYP_Pos)            /*!< 0x0000000C */
12890 #define FMC_BCRx_MTYP                       FMC_BCRx_MTYP_Msk                       /*!<MTYP[1:0] bits (Memory type)           */
12891 #define FMC_BCRx_MTYP_0                     (0x1UL << FMC_BCRx_MTYP_Pos)            /*!< 0x00000004 */
12892 #define FMC_BCRx_MTYP_1                     (0x2UL << FMC_BCRx_MTYP_Pos)            /*!< 0x00000008 */
12893 #define FMC_BCRx_MWID_Pos                   (4U)
12894 #define FMC_BCRx_MWID_Msk                   (0x3UL << FMC_BCRx_MWID_Pos)            /*!< 0x00000030 */
12895 #define FMC_BCRx_MWID                       FMC_BCRx_MWID_Msk                       /*!<MWID[1:0] bits (Memory data bus width) */
12896 #define FMC_BCRx_MWID_0                     (0x1UL << FMC_BCRx_MWID_Pos)            /*!< 0x00000010 */
12897 #define FMC_BCRx_MWID_1                     (0x2UL << FMC_BCRx_MWID_Pos)            /*!< 0x00000020 */
12898 #define FMC_BCRx_FACCEN_Pos                 (6U)
12899 #define FMC_BCRx_FACCEN_Msk                 (0x1UL << FMC_BCRx_FACCEN_Pos)          /*!< 0x00000040 */
12900 #define FMC_BCRx_FACCEN                     FMC_BCRx_FACCEN_Msk                     /*!<Flash access enable        */
12901 #define FMC_BCRx_BURSTEN_Pos                (8U)
12902 #define FMC_BCRx_BURSTEN_Msk                (0x1UL << FMC_BCRx_BURSTEN_Pos)         /*!< 0x00000100 */
12903 #define FMC_BCRx_BURSTEN                    FMC_BCRx_BURSTEN_Msk                    /*!<Burst enable bit           */
12904 #define FMC_BCRx_WAITPOL_Pos                (9U)
12905 #define FMC_BCRx_WAITPOL_Msk                (0x1UL << FMC_BCRx_WAITPOL_Pos)         /*!< 0x00000200 */
12906 #define FMC_BCRx_WAITPOL                    FMC_BCRx_WAITPOL_Msk                    /*!<Wait signal polarity bit   */
12907 #define FMC_BCRx_WAITCFG_Pos                (11U)
12908 #define FMC_BCRx_WAITCFG_Msk                (0x1UL << FMC_BCRx_WAITCFG_Pos)         /*!< 0x00000800 */
12909 #define FMC_BCRx_WAITCFG                    FMC_BCRx_WAITCFG_Msk                    /*!<Wait timing configuration  */
12910 #define FMC_BCRx_WREN_Pos                   (12U)
12911 #define FMC_BCRx_WREN_Msk                   (0x1UL << FMC_BCRx_WREN_Pos)            /*!< 0x00001000 */
12912 #define FMC_BCRx_WREN                       FMC_BCRx_WREN_Msk                       /*!<Write enable bit           */
12913 #define FMC_BCRx_WAITEN_Pos                 (13U)
12914 #define FMC_BCRx_WAITEN_Msk                 (0x1UL << FMC_BCRx_WAITEN_Pos)          /*!< 0x00002000 */
12915 #define FMC_BCRx_WAITEN                     FMC_BCRx_WAITEN_Msk                     /*!<Wait enable bit            */
12916 #define FMC_BCRx_EXTMOD_Pos                 (14U)
12917 #define FMC_BCRx_EXTMOD_Msk                 (0x1UL << FMC_BCRx_EXTMOD_Pos)          /*!< 0x00004000 */
12918 #define FMC_BCRx_EXTMOD                     FMC_BCRx_EXTMOD_Msk                     /*!<Extended mode enable       */
12919 #define FMC_BCRx_ASYNCWAIT_Pos              (15U)
12920 #define FMC_BCRx_ASYNCWAIT_Msk              (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)       /*!< 0x00008000 */
12921 #define FMC_BCRx_ASYNCWAIT                  FMC_BCRx_ASYNCWAIT_Msk                  /*!<Asynchronous wait          */
12922 #define FMC_BCRx_CPSIZE_Pos                 (16U)
12923 #define FMC_BCRx_CPSIZE_Msk                 (0x7UL << FMC_BCRx_CPSIZE_Pos)          /*!< 0x00070000 */
12924 #define FMC_BCRx_CPSIZE                     FMC_BCRx_CPSIZE_Msk                     /*!<PSIZE[2:0] bits CRAM Page Size */
12925 #define FMC_BCRx_CPSIZE_0                   (0x1UL << FMC_BCRx_CPSIZE_Pos)          /*!< 0x00010000 */
12926 #define FMC_BCRx_CPSIZE_1                   (0x2UL << FMC_BCRx_CPSIZE_Pos)          /*!< 0x00020000 */
12927 #define FMC_BCRx_CPSIZE_2                   (0x4UL << FMC_BCRx_CPSIZE_Pos)          /*!< 0x00040000 */
12928 #define FMC_BCRx_CBURSTRW_Pos               (19U)
12929 #define FMC_BCRx_CBURSTRW_Msk               (0x1UL << FMC_BCRx_CBURSTRW_Pos)        /*!< 0x00080000 */
12930 #define FMC_BCRx_CBURSTRW                   FMC_BCRx_CBURSTRW_Msk                   /*!<Write burst enable         */
12931 #define FMC_BCRx_NBLSET_Pos                 (22U)
12932 #define FMC_BCRx_NBLSET_Msk                 (0x3UL << FMC_BCRx_NBLSET_Pos)          /*!< 0x00C00000 */
12933 #define FMC_BCRx_NBLSET                     FMC_BCRx_NBLSET_Msk                     /*!<Byte lane (NBL) setup      */
12934 #define FMC_BCRx_NBLSET_0                   (0x1UL << FMC_BCRx_NBLSET_Pos)          /*!< 0x00400000 */
12935 #define FMC_BCRx_NBLSET_1                   (0x2UL << FMC_BCRx_NBLSET_Pos)          /*!< 0x00800000 */
12936 
12937 /******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
12938 #define FMC_BTRx_ADDSET_Pos                 (0U)
12939 #define FMC_BTRx_ADDSET_Msk                 (0xFUL << FMC_BTRx_ADDSET_Pos)          /*!< 0x0000000F */
12940 #define FMC_BTRx_ADDSET                     FMC_BTRx_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
12941 #define FMC_BTRx_ADDSET_0                   (0x1UL << FMC_BTRx_ADDSET_Pos)          /*!< 0x00000001 */
12942 #define FMC_BTRx_ADDSET_1                   (0x2UL << FMC_BTRx_ADDSET_Pos)          /*!< 0x00000002 */
12943 #define FMC_BTRx_ADDSET_2                   (0x4UL << FMC_BTRx_ADDSET_Pos)          /*!< 0x00000004 */
12944 #define FMC_BTRx_ADDSET_3                   (0x8UL << FMC_BTRx_ADDSET_Pos)          /*!< 0x00000008 */
12945 #define FMC_BTRx_ADDHLD_Pos                 (4U)
12946 #define FMC_BTRx_ADDHLD_Msk                 (0xFUL << FMC_BTRx_ADDHLD_Pos)          /*!< 0x000000F0 */
12947 #define FMC_BTRx_ADDHLD                     FMC_BTRx_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
12948 #define FMC_BTRx_ADDHLD_0                   (0x1UL << FMC_BTRx_ADDHLD_Pos)          /*!< 0x00000010 */
12949 #define FMC_BTRx_ADDHLD_1                   (0x2UL << FMC_BTRx_ADDHLD_Pos)          /*!< 0x00000020 */
12950 #define FMC_BTRx_ADDHLD_2                   (0x4UL << FMC_BTRx_ADDHLD_Pos)          /*!< 0x00000040 */
12951 #define FMC_BTRx_ADDHLD_3                   (0x8UL << FMC_BTRx_ADDHLD_Pos)          /*!< 0x00000080 */
12952 #define FMC_BTRx_DATAST_Pos                 (8U)
12953 #define FMC_BTRx_DATAST_Msk                 (0xFFUL << FMC_BTRx_DATAST_Pos)         /*!< 0x0000FF00 */
12954 #define FMC_BTRx_DATAST                     FMC_BTRx_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */
12955 #define FMC_BTRx_DATAST_0                   (0x01UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00000100 */
12956 #define FMC_BTRx_DATAST_1                   (0x02UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00000200 */
12957 #define FMC_BTRx_DATAST_2                   (0x04UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00000400 */
12958 #define FMC_BTRx_DATAST_3                   (0x08UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00000800 */
12959 #define FMC_BTRx_DATAST_4                   (0x10UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00001000 */
12960 #define FMC_BTRx_DATAST_5                   (0x20UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00002000 */
12961 #define FMC_BTRx_DATAST_6                   (0x40UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00004000 */
12962 #define FMC_BTRx_DATAST_7                   (0x80UL << FMC_BTRx_DATAST_Pos)         /*!< 0x00008000 */
12963 #define FMC_BTRx_BUSTURN_Pos                (16U)
12964 #define FMC_BTRx_BUSTURN_Msk                (0xFUL << FMC_BTRx_BUSTURN_Pos)         /*!< 0x000F0000 */
12965 #define FMC_BTRx_BUSTURN                    FMC_BTRx_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
12966 #define FMC_BTRx_BUSTURN_0                  (0x1UL << FMC_BTRx_BUSTURN_Pos)         /*!< 0x00010000 */
12967 #define FMC_BTRx_BUSTURN_1                  (0x2UL << FMC_BTRx_BUSTURN_Pos)         /*!< 0x00020000 */
12968 #define FMC_BTRx_BUSTURN_2                  (0x4UL << FMC_BTRx_BUSTURN_Pos)         /*!< 0x00040000 */
12969 #define FMC_BTRx_BUSTURN_3                  (0x8UL << FMC_BTRx_BUSTURN_Pos)         /*!< 0x00080000 */
12970 #define FMC_BTRx_CLKDIV_Pos                 (20U)
12971 #define FMC_BTRx_CLKDIV_Msk                 (0xFUL << FMC_BTRx_CLKDIV_Pos)          /*!< 0x00F00000 */
12972 #define FMC_BTRx_CLKDIV                     FMC_BTRx_CLKDIV_Msk                     /*!<CLKDIV[3:0] bits (Clock divide ratio) */
12973 #define FMC_BTRx_CLKDIV_0                   (0x1UL << FMC_BTRx_CLKDIV_Pos)          /*!< 0x00100000 */
12974 #define FMC_BTRx_CLKDIV_1                   (0x2UL << FMC_BTRx_CLKDIV_Pos)          /*!< 0x00200000 */
12975 #define FMC_BTRx_CLKDIV_2                   (0x4UL << FMC_BTRx_CLKDIV_Pos)          /*!< 0x00400000 */
12976 #define FMC_BTRx_CLKDIV_3                   (0x8UL << FMC_BTRx_CLKDIV_Pos)          /*!< 0x00800000 */
12977 #define FMC_BTRx_DATLAT_Pos                 (24U)
12978 #define FMC_BTRx_DATLAT_Msk                 (0xFUL << FMC_BTRx_DATLAT_Pos)          /*!< 0x0F000000 */
12979 #define FMC_BTRx_DATLAT                     FMC_BTRx_DATLAT_Msk                     /*!<DATLA[3:0] bits (Data latency) */
12980 #define FMC_BTRx_DATLAT_0                   (0x1UL << FMC_BTRx_DATLAT_Pos)          /*!< 0x01000000 */
12981 #define FMC_BTRx_DATLAT_1                   (0x2UL << FMC_BTRx_DATLAT_Pos)          /*!< 0x02000000 */
12982 #define FMC_BTRx_DATLAT_2                   (0x4UL << FMC_BTRx_DATLAT_Pos)          /*!< 0x04000000 */
12983 #define FMC_BTRx_DATLAT_3                   (0x8UL << FMC_BTRx_DATLAT_Pos)          /*!< 0x08000000 */
12984 #define FMC_BTRx_ACCMOD_Pos                 (28U)
12985 #define FMC_BTRx_ACCMOD_Msk                 (0x3UL << FMC_BTRx_ACCMOD_Pos)          /*!< 0x30000000 */
12986 #define FMC_BTRx_ACCMOD                     FMC_BTRx_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
12987 #define FMC_BTRx_ACCMOD_0                   (0x1UL << FMC_BTRx_ACCMOD_Pos)          /*!< 0x10000000 */
12988 #define FMC_BTRx_ACCMOD_1                   (0x2UL << FMC_BTRx_ACCMOD_Pos)          /*!< 0x20000000 */
12989 #define FMC_BTRx_DATAHLD_Pos                (30U)
12990 #define FMC_BTRx_DATAHLD_Msk                (0x3UL << FMC_BTRx_DATAHLD_Pos)         /*!< 0xC0000000 */
12991 #define FMC_BTRx_DATAHLD                    FMC_BTRx_DATAHLD_Msk                    /*!<DATAHLD[1:0] bits (Data hold phase duration) */
12992 #define FMC_BTRx_DATAHLD_0                  (0x1UL << FMC_BTRx_DATAHLD_Pos)         /*!< 0x40000000 */
12993 #define FMC_BTRx_DATAHLD_1                  (0x2UL << FMC_BTRx_DATAHLD_Pos)         /*!< 0x80000000 */
12994 
12995 /******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
12996 #define FMC_BWTRx_ADDSET_Pos                (0U)
12997 #define FMC_BWTRx_ADDSET_Msk                (0xFUL << FMC_BWTRx_ADDSET_Pos)         /*!< 0x0000000F */
12998 #define FMC_BWTRx_ADDSET                    FMC_BWTRx_ADDSET_Msk                    /*!<ADDSET[3:0] bits (Address setup phase duration) */
12999 #define FMC_BWTRx_ADDSET_0                  (0x1UL << FMC_BWTRx_ADDSET_Pos)         /*!< 0x00000001 */
13000 #define FMC_BWTRx_ADDSET_1                  (0x2UL << FMC_BWTRx_ADDSET_Pos)         /*!< 0x00000002 */
13001 #define FMC_BWTRx_ADDSET_2                  (0x4UL << FMC_BWTRx_ADDSET_Pos)         /*!< 0x00000004 */
13002 #define FMC_BWTRx_ADDSET_3                  (0x8UL << FMC_BWTRx_ADDSET_Pos)         /*!< 0x00000008 */
13003 #define FMC_BWTRx_ADDHLD_Pos                (4U)
13004 #define FMC_BWTRx_ADDHLD_Msk                (0xFUL << FMC_BWTRx_ADDHLD_Pos)         /*!< 0x000000F0 */
13005 #define FMC_BWTRx_ADDHLD                    FMC_BWTRx_ADDHLD_Msk                    /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
13006 #define FMC_BWTRx_ADDHLD_0                  (0x1UL << FMC_BWTRx_ADDHLD_Pos)         /*!< 0x00000010 */
13007 #define FMC_BWTRx_ADDHLD_1                  (0x2UL << FMC_BWTRx_ADDHLD_Pos)         /*!< 0x00000020 */
13008 #define FMC_BWTRx_ADDHLD_2                  (0x4UL << FMC_BWTRx_ADDHLD_Pos)         /*!< 0x00000040 */
13009 #define FMC_BWTRx_ADDHLD_3                  (0x8UL << FMC_BWTRx_ADDHLD_Pos)         /*!< 0x00000080 */
13010 #define FMC_BWTRx_DATAST_Pos                (8U)
13011 #define FMC_BWTRx_DATAST_Msk                (0xFFUL << FMC_BWTRx_DATAST_Pos)        /*!< 0x0000FF00 */
13012 #define FMC_BWTRx_DATAST                    FMC_BWTRx_DATAST_Msk                    /*!<DATAST [3:0] bits (Data-phase duration) */
13013 #define FMC_BWTRx_DATAST_0                  (0x01UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00000100 */
13014 #define FMC_BWTRx_DATAST_1                  (0x02UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00000200 */
13015 #define FMC_BWTRx_DATAST_2                  (0x04UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00000400 */
13016 #define FMC_BWTRx_DATAST_3                  (0x08UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00000800 */
13017 #define FMC_BWTRx_DATAST_4                  (0x10UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00001000 */
13018 #define FMC_BWTRx_DATAST_5                  (0x20UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00002000 */
13019 #define FMC_BWTRx_DATAST_6                  (0x40UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00004000 */
13020 #define FMC_BWTRx_DATAST_7                  (0x80UL << FMC_BWTRx_DATAST_Pos)        /*!< 0x00008000 */
13021 #define FMC_BWTRx_BUSTURN_Pos               (16U)
13022 #define FMC_BWTRx_BUSTURN_Msk               (0xFUL << FMC_BWTRx_BUSTURN_Pos)        /*!< 0x000F0000 */
13023 #define FMC_BWTRx_BUSTURN                   FMC_BWTRx_BUSTURN_Msk                   /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
13024 #define FMC_BWTRx_BUSTURN_0                 (0x1UL << FMC_BWTRx_BUSTURN_Pos)        /*!< 0x00010000 */
13025 #define FMC_BWTRx_BUSTURN_1                 (0x2UL << FMC_BWTRx_BUSTURN_Pos)        /*!< 0x00020000 */
13026 #define FMC_BWTRx_BUSTURN_2                 (0x4UL << FMC_BWTRx_BUSTURN_Pos)        /*!< 0x00040000 */
13027 #define FMC_BWTRx_BUSTURN_3                 (0x8UL << FMC_BWTRx_BUSTURN_Pos)        /*!< 0x00080000 */
13028 #define FMC_BWTRx_ACCMOD_Pos                (28U)
13029 #define FMC_BWTRx_ACCMOD_Msk                (0x3UL << FMC_BWTRx_ACCMOD_Pos)         /*!< 0x30000000 */
13030 #define FMC_BWTRx_ACCMOD                    FMC_BWTRx_ACCMOD_Msk                    /*!<ACCMOD[1:0] bits (Access mode) */
13031 #define FMC_BWTRx_ACCMOD_0                  (0x1UL << FMC_BWTRx_ACCMOD_Pos)         /*!< 0x10000000 */
13032 #define FMC_BWTRx_ACCMOD_1                  (0x2UL << FMC_BWTRx_ACCMOD_Pos)         /*!< 0x20000000 */
13033 #define FMC_BWTRx_DATAHLD_Pos               (30U)
13034 #define FMC_BWTRx_DATAHLD_Msk               (0x3UL << FMC_BWTRx_DATAHLD_Pos)        /*!< 0xC0000000 */
13035 #define FMC_BWTRx_DATAHLD                   FMC_BWTRx_DATAHLD_Msk                   /*!<DATAHLD[1:0] bits (Data hold phase duration) */
13036 #define FMC_BWTRx_DATAHLD_0                 (0x1UL << FMC_BWTRx_DATAHLD_Pos)        /*!< 0x40000000 */
13037 #define FMC_BWTRx_DATAHLD_1                 (0x2UL << FMC_BWTRx_DATAHLD_Pos)        /*!< 0x80000000 */
13038 
13039 /******************  Bit definition for FMC_PCSCNTR register ******************/
13040 #define FMC_PCSCNTR_CSCOUNT_Pos             (0U)
13041 #define FMC_PCSCNTR_CSCOUNT_Msk             (0xFFFFUL << FMC_PCSCNTR_CSCOUNT_Pos)   /*!< 0x0000FFFF */
13042 #define FMC_PCSCNTR_CSCOUNT                 FMC_PCSCNTR_CSCOUNT_Msk                 /*!<CSCOUNT[15:0] bits (Chip select counter) */
13043 #define FMC_PCSCNTR_CNTB1EN_Pos             (16U)
13044 #define FMC_PCSCNTR_CNTB1EN_Msk             (0x1UL << FMC_PCSCNTR_CNTB1EN_Pos)      /*!< 0x00010000 */
13045 #define FMC_PCSCNTR_CNTB1EN                 FMC_PCSCNTR_CNTB1EN_Msk                 /*!<Counter PSRAM/NOR Bank1_1 enable */
13046 #define FMC_PCSCNTR_CNTB2EN_Pos             (17U)
13047 #define FMC_PCSCNTR_CNTB2EN_Msk             (0x1UL << FMC_PCSCNTR_CNTB2EN_Pos)      /*!< 0x00020000 */
13048 #define FMC_PCSCNTR_CNTB2EN                 FMC_PCSCNTR_CNTB2EN_Msk                 /*!<Counter PSRAM/NOR Bank1_2 enable */
13049 #define FMC_PCSCNTR_CNTB3EN_Pos             (18U)
13050 #define FMC_PCSCNTR_CNTB3EN_Msk             (0x1UL << FMC_PCSCNTR_CNTB3EN_Pos)      /*!< 0x00040000 */
13051 #define FMC_PCSCNTR_CNTB3EN                 FMC_PCSCNTR_CNTB3EN_Msk                 /*!<Counter PSRAM/NOR Bank1_3 enable */
13052 #define FMC_PCSCNTR_CNTB4EN_Pos             (19U)
13053 #define FMC_PCSCNTR_CNTB4EN_Msk             (0x1UL << FMC_PCSCNTR_CNTB4EN_Pos)      /*!< 0x00080000 */
13054 #define FMC_PCSCNTR_CNTB4EN                 FMC_PCSCNTR_CNTB4EN_Msk                 /*!<Counter PSRAM/NOR Bank1_4 enable */
13055 
13056 /******************  Bit definition for FMC_PCR register  *******************/
13057 #define FMC_PCR_PWAITEN_Pos                 (1U)
13058 #define FMC_PCR_PWAITEN_Msk                 (0x1UL << FMC_PCR_PWAITEN_Pos)          /*!< 0x00000002 */
13059 #define FMC_PCR_PWAITEN                     FMC_PCR_PWAITEN_Msk                     /*!<Wait feature enable bit                   */
13060 #define FMC_PCR_PBKEN_Pos                   (2U)
13061 #define FMC_PCR_PBKEN_Msk                   (0x1UL << FMC_PCR_PBKEN_Pos)            /*!< 0x00000004 */
13062 #define FMC_PCR_PBKEN                       FMC_PCR_PBKEN_Msk                       /*!<NAND Flash memory bank enable bit */
13063 #define FMC_PCR_PTYP_Pos                    (3U)
13064 #define FMC_PCR_PTYP_Msk                    (0x1UL << FMC_PCR_PTYP_Pos)             /*!< 0x00000008 */
13065 #define FMC_PCR_PTYP                        FMC_PCR_PTYP_Msk                        /*!<Memory type                               */
13066 #define FMC_PCR_PWID_Pos                    (4U)
13067 #define FMC_PCR_PWID_Msk                    (0x3UL << FMC_PCR_PWID_Pos)             /*!< 0x00000030 */
13068 #define FMC_PCR_PWID                        FMC_PCR_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */
13069 #define FMC_PCR_PWID_0                      (0x1UL << FMC_PCR_PWID_Pos)             /*!< 0x00000010 */
13070 #define FMC_PCR_PWID_1                      (0x2UL << FMC_PCR_PWID_Pos)             /*!< 0x00000020 */
13071 #define FMC_PCR_ECCEN_Pos                   (6U)
13072 #define FMC_PCR_ECCEN_Msk                   (0x1UL << FMC_PCR_ECCEN_Pos)            /*!< 0x00000040 */
13073 #define FMC_PCR_ECCEN                       FMC_PCR_ECCEN_Msk                       /*!<ECC computation logic enable bit          */
13074 #define FMC_PCR_TCLR_Pos                    (9U)
13075 #define FMC_PCR_TCLR_Msk                    (0xFUL << FMC_PCR_TCLR_Pos)             /*!< 0x00001E00 */
13076 #define FMC_PCR_TCLR                        FMC_PCR_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay)          */
13077 #define FMC_PCR_TCLR_0                      (0x1UL << FMC_PCR_TCLR_Pos)             /*!< 0x00000200 */
13078 #define FMC_PCR_TCLR_1                      (0x2UL << FMC_PCR_TCLR_Pos)             /*!< 0x00000400 */
13079 #define FMC_PCR_TCLR_2                      (0x4UL << FMC_PCR_TCLR_Pos)             /*!< 0x00000800 */
13080 #define FMC_PCR_TCLR_3                      (0x8UL << FMC_PCR_TCLR_Pos)             /*!< 0x00001000 */
13081 #define FMC_PCR_TAR_Pos                     (13U)
13082 #define FMC_PCR_TAR_Msk                     (0xFUL << FMC_PCR_TAR_Pos)              /*!< 0x0001E000 */
13083 #define FMC_PCR_TAR                         FMC_PCR_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay)           */
13084 #define FMC_PCR_TAR_0                       (0x1UL << FMC_PCR_TAR_Pos)              /*!< 0x00002000 */
13085 #define FMC_PCR_TAR_1                       (0x2UL << FMC_PCR_TAR_Pos)              /*!< 0x00004000 */
13086 #define FMC_PCR_TAR_2                       (0x4UL << FMC_PCR_TAR_Pos)              /*!< 0x00008000 */
13087 #define FMC_PCR_TAR_3                       (0x8UL << FMC_PCR_TAR_Pos)              /*!< 0x00010000 */
13088 #define FMC_PCR_ECCPS_Pos                   (17U)
13089 #define FMC_PCR_ECCPS_Msk                   (0x7UL << FMC_PCR_ECCPS_Pos)            /*!< 0x000E0000 */
13090 #define FMC_PCR_ECCPS                       FMC_PCR_ECCPS_Msk                       /*!<ECCPS[1:0] bits (ECC page size)           */
13091 #define FMC_PCR_ECCPS_0                     (0x1UL << FMC_PCR_ECCPS_Pos)            /*!< 0x00020000 */
13092 #define FMC_PCR_ECCPS_1                     (0x2UL << FMC_PCR_ECCPS_Pos)            /*!< 0x00040000 */
13093 #define FMC_PCR_ECCPS_2                     (0x4UL << FMC_PCR_ECCPS_Pos)            /*!< 0x00080000 */
13094 
13095 /*******************  Bit definition for FMC_SR register  *******************/
13096 #define FMC_SR_IRS_Pos                      (0U)
13097 #define FMC_SR_IRS_Msk                      (0x1UL << FMC_SR_IRS_Pos)               /*!< 0x00000001 */
13098 #define FMC_SR_IRS                          FMC_SR_IRS_Msk                          /*!<Interrupt Rising Edge status                */
13099 #define FMC_SR_ILS_Pos                      (1U)
13100 #define FMC_SR_ILS_Msk                      (0x1UL << FMC_SR_ILS_Pos)               /*!< 0x00000002 */
13101 #define FMC_SR_ILS                          FMC_SR_ILS_Msk                          /*!<Interrupt Level status                      */
13102 #define FMC_SR_IFS_Pos                      (2U)
13103 #define FMC_SR_IFS_Msk                      (0x1UL << FMC_SR_IFS_Pos)               /*!< 0x00000004 */
13104 #define FMC_SR_IFS                          FMC_SR_IFS_Msk                          /*!<Interrupt Falling Edge status               */
13105 #define FMC_SR_IREN_Pos                     (3U)
13106 #define FMC_SR_IREN_Msk                     (0x1UL << FMC_SR_IREN_Pos)              /*!< 0x00000008 */
13107 #define FMC_SR_IREN                         FMC_SR_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit  */
13108 #define FMC_SR_ILEN_Pos                     (4U)
13109 #define FMC_SR_ILEN_Msk                     (0x1UL << FMC_SR_ILEN_Pos)              /*!< 0x00000010 */
13110 #define FMC_SR_ILEN                         FMC_SR_ILEN_Msk                         /*!<Interrupt Level detection Enable bit        */
13111 #define FMC_SR_IFEN_Pos                     (5U)
13112 #define FMC_SR_IFEN_Msk                     (0x1UL << FMC_SR_IFEN_Pos)              /*!< 0x00000020 */
13113 #define FMC_SR_IFEN                         FMC_SR_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */
13114 #define FMC_SR_FEMPT_Pos                    (6U)
13115 #define FMC_SR_FEMPT_Msk                    (0x1UL << FMC_SR_FEMPT_Pos)             /*!< 0x00000040 */
13116 #define FMC_SR_FEMPT                        FMC_SR_FEMPT_Msk                        /*!<FIFO empty                                  */
13117 
13118 /******************  Bit definition for FMC_PMEM register  ******************/
13119 #define FMC_PMEM_MEMSET_Pos                 (0U)
13120 #define FMC_PMEM_MEMSET_Msk                 (0xFFUL << FMC_PMEM_MEMSET_Pos)         /*!< 0x000000FF */
13121 #define FMC_PMEM_MEMSET                     FMC_PMEM_MEMSET_Msk                     /*!<MEMSET[7:0] bits (Common memory setup time) */
13122 #define FMC_PMEM_MEMSET_0                   (0x01UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000001 */
13123 #define FMC_PMEM_MEMSET_1                   (0x02UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000002 */
13124 #define FMC_PMEM_MEMSET_2                   (0x04UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000004 */
13125 #define FMC_PMEM_MEMSET_3                   (0x08UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000008 */
13126 #define FMC_PMEM_MEMSET_4                   (0x10UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000010 */
13127 #define FMC_PMEM_MEMSET_5                   (0x20UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000020 */
13128 #define FMC_PMEM_MEMSET_6                   (0x40UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000040 */
13129 #define FMC_PMEM_MEMSET_7                   (0x80UL << FMC_PMEM_MEMSET_Pos)         /*!< 0x00000080 */
13130 #define FMC_PMEM_MEMWAIT_Pos                (8U)
13131 #define FMC_PMEM_MEMWAIT_Msk                (0xFFUL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x0000FF00 */
13132 #define FMC_PMEM_MEMWAIT                    FMC_PMEM_MEMWAIT_Msk                    /*!<MEMWAIT[7:0] bits (Common memory wait time) */
13133 #define FMC_PMEM_MEMWAIT_0                  (0x01UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00000100 */
13134 #define FMC_PMEM_MEMWAIT_1                  (0x02UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00000200 */
13135 #define FMC_PMEM_MEMWAIT_2                  (0x04UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00000400 */
13136 #define FMC_PMEM_MEMWAIT_3                  (0x08UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00000800 */
13137 #define FMC_PMEM_MEMWAIT_4                  (0x10UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00001000 */
13138 #define FMC_PMEM_MEMWAIT_5                  (0x20UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00002000 */
13139 #define FMC_PMEM_MEMWAIT_6                  (0x40UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00004000 */
13140 #define FMC_PMEM_MEMWAIT_7                  (0x80UL << FMC_PMEM_MEMWAIT_Pos)        /*!< 0x00008000 */
13141 #define FMC_PMEM_MEMHOLD_Pos                (16U)
13142 #define FMC_PMEM_MEMHOLD_Msk                (0xFFUL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00FF0000 */
13143 #define FMC_PMEM_MEMHOLD                    FMC_PMEM_MEMHOLD_Msk                    /*!<MEMHOLD[7:0] bits (Common memory hold time) */
13144 #define FMC_PMEM_MEMHOLD_0                  (0x01UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00010000 */
13145 #define FMC_PMEM_MEMHOLD_1                  (0x02UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00020000 */
13146 #define FMC_PMEM_MEMHOLD_2                  (0x04UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00040000 */
13147 #define FMC_PMEM_MEMHOLD_3                  (0x08UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00080000 */
13148 #define FMC_PMEM_MEMHOLD_4                  (0x10UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00100000 */
13149 #define FMC_PMEM_MEMHOLD_5                  (0x20UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00200000 */
13150 #define FMC_PMEM_MEMHOLD_6                  (0x40UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00400000 */
13151 #define FMC_PMEM_MEMHOLD_7                  (0x80UL << FMC_PMEM_MEMHOLD_Pos)        /*!< 0x00800000 */
13152 #define FMC_PMEM_MEMHIZ_Pos                 (24U)
13153 #define FMC_PMEM_MEMHIZ_Msk                 (0xFFUL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0xFF000000 */
13154 #define FMC_PMEM_MEMHIZ                     FMC_PMEM_MEMHIZ_Msk                     /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
13155 #define FMC_PMEM_MEMHIZ_0                   (0x01UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x01000000 */
13156 #define FMC_PMEM_MEMHIZ_1                   (0x02UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x02000000 */
13157 #define FMC_PMEM_MEMHIZ_2                   (0x04UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x04000000 */
13158 #define FMC_PMEM_MEMHIZ_3                   (0x08UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x08000000 */
13159 #define FMC_PMEM_MEMHIZ_4                   (0x10UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x10000000 */
13160 #define FMC_PMEM_MEMHIZ_5                   (0x20UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x20000000 */
13161 #define FMC_PMEM_MEMHIZ_6                   (0x40UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x40000000 */
13162 #define FMC_PMEM_MEMHIZ_7                   (0x80UL << FMC_PMEM_MEMHIZ_Pos)         /*!< 0x80000000 */
13163 
13164 /******************  Bit definition for FMC_PATT register  ******************/
13165 #define FMC_PATT_ATTSET_Pos                 (0U)
13166 #define FMC_PATT_ATTSET_Msk                 (0xFFUL << FMC_PATT_ATTSET_Pos)         /*!< 0x000000FF */
13167 #define FMC_PATT_ATTSET                     FMC_PATT_ATTSET_Msk                     /*!<ATTSET[7:0] bits (Attribute memory setup time) */
13168 #define FMC_PATT_ATTSET_0                   (0x01UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000001 */
13169 #define FMC_PATT_ATTSET_1                   (0x02UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000002 */
13170 #define FMC_PATT_ATTSET_2                   (0x04UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000004 */
13171 #define FMC_PATT_ATTSET_3                   (0x08UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000008 */
13172 #define FMC_PATT_ATTSET_4                   (0x10UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000010 */
13173 #define FMC_PATT_ATTSET_5                   (0x20UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000020 */
13174 #define FMC_PATT_ATTSET_6                   (0x40UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000040 */
13175 #define FMC_PATT_ATTSET_7                   (0x80UL << FMC_PATT_ATTSET_Pos)         /*!< 0x00000080 */
13176 #define FMC_PATT_ATTWAIT_Pos                (8U)
13177 #define FMC_PATT_ATTWAIT_Msk                (0xFFUL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x0000FF00 */
13178 #define FMC_PATT_ATTWAIT                    FMC_PATT_ATTWAIT_Msk                    /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
13179 #define FMC_PATT_ATTWAIT_0                  (0x01UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00000100 */
13180 #define FMC_PATT_ATTWAIT_1                  (0x02UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00000200 */
13181 #define FMC_PATT_ATTWAIT_2                  (0x04UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00000400 */
13182 #define FMC_PATT_ATTWAIT_3                  (0x08UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00000800 */
13183 #define FMC_PATT_ATTWAIT_4                  (0x10UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00001000 */
13184 #define FMC_PATT_ATTWAIT_5                  (0x20UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00002000 */
13185 #define FMC_PATT_ATTWAIT_6                  (0x40UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00004000 */
13186 #define FMC_PATT_ATTWAIT_7                  (0x80UL << FMC_PATT_ATTWAIT_Pos)        /*!< 0x00008000 */
13187 #define FMC_PATT_ATTHOLD_Pos                (16U)
13188 #define FMC_PATT_ATTHOLD_Msk                (0xFFUL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00FF0000 */
13189 #define FMC_PATT_ATTHOLD                    FMC_PATT_ATTHOLD_Msk                    /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
13190 #define FMC_PATT_ATTHOLD_0                  (0x01UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00010000 */
13191 #define FMC_PATT_ATTHOLD_1                  (0x02UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00020000 */
13192 #define FMC_PATT_ATTHOLD_2                  (0x04UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00040000 */
13193 #define FMC_PATT_ATTHOLD_3                  (0x08UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00080000 */
13194 #define FMC_PATT_ATTHOLD_4                  (0x10UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00100000 */
13195 #define FMC_PATT_ATTHOLD_5                  (0x20UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00200000 */
13196 #define FMC_PATT_ATTHOLD_6                  (0x40UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00400000 */
13197 #define FMC_PATT_ATTHOLD_7                  (0x80UL << FMC_PATT_ATTHOLD_Pos)        /*!< 0x00800000 */
13198 #define FMC_PATT_ATTHIZ_Pos                 (24U)
13199 #define FMC_PATT_ATTHIZ_Msk                 (0xFFUL << FMC_PATT_ATTHIZ_Pos)         /*!< 0xFF000000 */
13200 #define FMC_PATT_ATTHIZ                     FMC_PATT_ATTHIZ_Msk                     /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
13201 #define FMC_PATT_ATTHIZ_0                   (0x01UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x01000000 */
13202 #define FMC_PATT_ATTHIZ_1                   (0x02UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x02000000 */
13203 #define FMC_PATT_ATTHIZ_2                   (0x04UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x04000000 */
13204 #define FMC_PATT_ATTHIZ_3                   (0x08UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x08000000 */
13205 #define FMC_PATT_ATTHIZ_4                   (0x10UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x10000000 */
13206 #define FMC_PATT_ATTHIZ_5                   (0x20UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x20000000 */
13207 #define FMC_PATT_ATTHIZ_6                   (0x40UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x40000000 */
13208 #define FMC_PATT_ATTHIZ_7                   (0x80UL << FMC_PATT_ATTHIZ_Pos)         /*!< 0x80000000 */
13209 
13210 /******************  Bit definition for FMC_ECCR3 register  ******************/
13211 #define FMC_ECCR3_ECC3_Pos                  (0U)
13212 #define FMC_ECCR3_ECC3_Msk                  (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)    /*!< 0xFFFFFFFF */
13213 #define FMC_ECCR3_ECC3                      FMC_ECCR3_ECC3_Msk                      /*!<ECC result */
13214 
13215 /******************************************************************************/
13216 /*                                                                            */
13217 /*                       Graphic MMU (GFXMMU)                                 */
13218 /*                                                                            */
13219 /******************************************************************************/
13220 /****************** Bits definition for GFXMMU_CR register ********************/
13221 #define GFXMMU_CR_B0OIE_Pos                (0U)
13222 #define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)       /*!< 0x00000001 */
13223 #define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                  /*!< Buffer 0 overflow interrupt enable */
13224 #define GFXMMU_CR_B1OIE_Pos                (1U)
13225 #define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)       /*!< 0x00000002 */
13226 #define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                  /*!< Buffer 1 overflow interrupt enable */
13227 #define GFXMMU_CR_B2OIE_Pos                (2U)
13228 #define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)       /*!< 0x00000004 */
13229 #define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                  /*!< Buffer 2 overflow interrupt enable */
13230 #define GFXMMU_CR_B3OIE_Pos                (3U)
13231 #define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)       /*!< 0x00000008 */
13232 #define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                  /*!< Buffer 3 overflow interrupt enable */
13233 #define GFXMMU_CR_AMEIE_Pos                (4U)
13234 #define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)       /*!< 0x00000010 */
13235 #define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                  /*!< AHB master error interrupt enable */
13236 #define GFXMMU_CR_192BM_Pos                (6U)
13237 #define GFXMMU_CR_192BM_Msk                (0x1UL << GFXMMU_CR_192BM_Pos)       /*!< 0x00000040 */
13238 #define GFXMMU_CR_192BM                    GFXMMU_CR_192BM_Msk                  /*!< 192 block mode */
13239 #define GFXMMU_CR_ACE_Pos                  (20U)
13240 #define GFXMMU_CR_ACE_Msk                  (0x1UL << GFXMMU_CR_ACE_Pos)         /*!< 0x00100000 */
13241 #define GFXMMU_CR_ACE                      GFXMMU_CR_ACE_Msk                    /*!< Address cache enable */
13242 #define GFXMMU_CR_ACLB_Pos                 (21U)
13243 #define GFXMMU_CR_ACLB_Msk                 (0x3UL << GFXMMU_CR_ACLB_Pos)        /*!< 0x00600000 */
13244 #define GFXMMU_CR_ACLB                     GFXMMU_CR_ACLB_Msk                   /*!< ACLB[1:0]: Address cache lock buffer */
13245 #define GFXMMU_CR_ACLB_0                   (0x1UL << GFXMMU_CR_ACLB_Pos)        /*!< Address cache locked bit 0 */
13246 #define GFXMMU_CR_ACLB_1                   (0x2UL << GFXMMU_CR_ACLB_Pos)        /*!< Address cache locked bit 1 */
13247 
13248 /****************** Bits definition for GFXMMU_SR register ********************/
13249 #define GFXMMU_SR_B0OF_Pos                 (0U)
13250 #define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)        /*!< 0x00000001 */
13251 #define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                   /*!< Buffer 0 overflow flag */
13252 #define GFXMMU_SR_B1OF_Pos                 (1U)
13253 #define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)        /*!< 0x00000002 */
13254 #define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                   /*!< Buffer 1 overflow flag */
13255 #define GFXMMU_SR_B2OF_Pos                 (2U)
13256 #define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)        /*!< 0x00000004 */
13257 #define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                   /*!< Buffer 2 overflow flag */
13258 #define GFXMMU_SR_B3OF_Pos                 (3U)
13259 #define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)        /*!< 0x00000008 */
13260 #define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                   /*!< Buffer 3 overflow flag */
13261 #define GFXMMU_SR_AMEF_Pos                 (4U)
13262 #define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)        /*!< 0x00000010 */
13263 #define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                   /*!< AHB master error flag */
13264 
13265 /****************** Bits definition for GFXMMU_FCR register *******************/
13266 #define GFXMMU_FCR_CB0OF_Pos               (0U)
13267 #define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)      /*!< 0x00000001 */
13268 #define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                 /*!< Clear buffer 0 overflow flag */
13269 #define GFXMMU_FCR_CB1OF_Pos               (1U)
13270 #define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)      /*!< 0x00000002 */
13271 #define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                 /*!< Clear buffer 1 overflow flag */
13272 #define GFXMMU_FCR_CB2OF_Pos               (2U)
13273 #define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)      /*!< 0x00000004 */
13274 #define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                 /*!< Clear buffer 2 overflow flag */
13275 #define GFXMMU_FCR_CB3OF_Pos               (3U)
13276 #define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)      /*!< 0x00000008 */
13277 #define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                 /*!< Clear buffer 3 overflow flag */
13278 #define GFXMMU_FCR_CAMEF_Pos               (4U)
13279 #define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)      /*!< 0x00000010 */
13280 #define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                 /*!< Clear AHB master error flag */
13281 
13282 /****************** Bits definition for GFXMMU_CCR register *******************/
13283 #define GFXMMU_CCR_FF_Pos                  (0U)
13284 #define GFXMMU_CCR_FF_Msk                  (0x1UL << GFXMMU_CCR_FF_Pos)         /*!< 0x00000001 */
13285 #define GFXMMU_CCR_FF                      GFXMMU_CCR_FF_Msk                    /*!< Clear buffer 0 overflow flag */
13286 #define GFXMMU_CCR_FI_Pos                  (1U)
13287 #define GFXMMU_CCR_FI_Msk                  (0x1UL << GFXMMU_CCR_FI_Pos)         /*!< 0x00000002 */
13288 #define GFXMMU_CCR_FI                      GFXMMU_CCR_FI_Msk                    /*!< Clear buffer 1 overflow flag */
13289 
13290 /****************** Bits definition for GFXMMU_DVR register *******************/
13291 #define GFXMMU_DVR_DV_Pos                  (0U)
13292 #define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos)  /*!< 0xFFFFFFFF */
13293 #define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                    /*!< DV[31:0] bits (Default value) */
13294 
13295 /****************** Bits definition for GFXMMU_B0CR register ******************/
13296 #define GFXMMU_B0CR_PBO_Pos                (4U)
13297 #define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)   /*!< 0x007FFFF0 */
13298 #define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                  /*!< PB0[22:4] bits (Physical buffer offset) */
13299 #define GFXMMU_B0CR_PBBA_Pos               (23U)
13300 #define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)    /*!< 0xFF800000 */
13301 #define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                 /*!< PBBA[31:23] bits (Physical buffer base address) */
13302 
13303 /****************** Bits definition for GFXMMU_B1CR register ******************/
13304 #define GFXMMU_B1CR_PBO_Pos                (4U)
13305 #define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)   /*!< 0x007FFFF0 */
13306 #define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                  /*!< PB0[22:4] bits (Physical buffer offset) */
13307 #define GFXMMU_B1CR_PBBA_Pos               (23U)
13308 #define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)    /*!< 0xFF800000 */
13309 #define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                 /*!< PBBA[31:23] bits (Physical buffer base address) */
13310 
13311 /****************** Bits definition for GFXMMU_B2CR register ******************/
13312 #define GFXMMU_B2CR_PBO_Pos                (4U)
13313 #define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)   /*!< 0x007FFFF0 */
13314 #define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                  /*!< PB0[22:4] bits (Physical buffer offset) */
13315 #define GFXMMU_B2CR_PBBA_Pos               (23U)
13316 #define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)    /*!< 0xFF800000 */
13317 #define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                 /*!< PBBA[31:23] bits (Physical buffer base address) */
13318 
13319 /****************** Bits definition for GFXMMU_B3CR register ******************/
13320 #define GFXMMU_B3CR_PBO_Pos                (4U)
13321 #define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)   /*!< 0x007FFFF0 */
13322 #define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                  /*!< PB0[22:4] bits (Physical buffer offset) */
13323 #define GFXMMU_B3CR_PBBA_Pos               (23U)
13324 #define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)    /*!< 0xFF800000 */
13325 #define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                 /*!< PBBA[31:23] bits (Physical buffer base address) */
13326 
13327 /****************** Bits definition for GFXMMU_LUTxL register *****************/
13328 #define GFXMMU_LUTxL_EN_Pos                (0U)
13329 #define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)       /*!< 0x00000001 */
13330 #define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                  /*!< Enable */
13331 #define GFXMMU_LUTxL_FVB_Pos               (8U)
13332 #define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)     /*!< 0x0000FF00 */
13333 #define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                 /*!< FVB[7:0] bits (First visible block) */
13334 #define GFXMMU_LUTxL_LVB_Pos               (16U)
13335 #define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)     /*!< 0x00FF0000 */
13336 #define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                 /*!< LVB[7:0] bits (Last visible block) */
13337 
13338 /****************** Bits definition for GFXMMU_LUTxH register *****************/
13339 #define GFXMMU_LUTxH_LO_Pos                (4U)
13340 #define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)   /*!< 0x003FFFF0 */
13341 #define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                  /*!< LO[21:4] bits (Line offset) */
13342 
13343 /******************************************************************************/
13344 /*                                                                            */
13345 /*                       Graphic Timer (GFXTIM)                               */
13346 /*                                                                            */
13347 /******************************************************************************/
13348 /******************  Bits definition for GFXTIM_CR register  ******************/
13349 #define GFXTIM_CR_TES_Pos              (0U)
13350 #define GFXTIM_CR_TES_Msk              (0x3UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000003 */
13351 #define GFXTIM_CR_TES                  GFXTIM_CR_TES_Msk
13352 #define GFXTIM_CR_TES_0                (0x1UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000001 */
13353 #define GFXTIM_CR_TES_1                (0x2UL << GFXTIM_CR_TES_Pos)            /*!< 0x00000002 */
13354 
13355 #define GFXTIM_CR_TEPOL_Pos            (4U)
13356 #define GFXTIM_CR_TEPOL_Msk            (0x1UL << GFXTIM_CR_TEPOL_Pos)          /*!< 0x00000010 */
13357 #define GFXTIM_CR_TEPOL                GFXTIM_CR_TEPOL_Msk
13358 
13359 #define GFXTIM_CR_SYNCS_Pos            (8U)
13360 #define GFXTIM_CR_SYNCS_Msk            (0x3UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000300 */
13361 #define GFXTIM_CR_SYNCS                GFXTIM_CR_SYNCS_Msk
13362 #define GFXTIM_CR_SYNCS_0              (0x1UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000100 */
13363 #define GFXTIM_CR_SYNCS_1              (0x2UL << GFXTIM_CR_SYNCS_Pos)          /*!< 0x00000200 */
13364 
13365 #define GFXTIM_CR_FCCOE_Pos            (16U)
13366 #define GFXTIM_CR_FCCOE_Msk            (0x1UL << GFXTIM_CR_FCCOE_Pos)          /*!< 0x00010000 */
13367 #define GFXTIM_CR_FCCOE                GFXTIM_CR_FCCOE_Msk
13368 
13369 #define GFXTIM_CR_LCCOE_Pos            (17U)
13370 #define GFXTIM_CR_LCCOE_Msk            (0x1UL << GFXTIM_CR_LCCOE_Pos)          /*!< 0x00020000 */
13371 #define GFXTIM_CR_LCCOE                GFXTIM_CR_LCCOE_Msk
13372 
13373 /******************  Bits definition for GFXTIM_CR register  ******************/
13374 #define GFXTIM_CGCR_LCS_Pos           (0U)
13375 #define GFXTIM_CGCR_LCS_Msk           (0x7UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000007 */
13376 #define GFXTIM_CGCR_LCS               GFXTIM_CGCR_LCS_Msk
13377 #define GFXTIM_CGCR_LCS_0             (0x1UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000001 */
13378 #define GFXTIM_CGCR_LCS_1             (0x2UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000002 */
13379 #define GFXTIM_CGCR_LCS_2             (0x4UL << GFXTIM_CGCR_LCS_Pos)           /*!< 0x00000004 */
13380 
13381 #define GFXTIM_CGCR_LCCCS_Pos         (4U)
13382 #define GFXTIM_CGCR_LCCCS_Msk         (0x1UL << GFXTIM_CGCR_LCCCS_Pos)         /*!< 0x00000010 */
13383 #define GFXTIM_CGCR_LCCCS             GFXTIM_CGCR_LCCCS_Msk
13384 
13385 #define GFXTIM_CGCR_LCCFR_Pos         (8U)
13386 #define GFXTIM_CGCR_LCCFR_Msk         (0x1UL << GFXTIM_CGCR_LCCFR_Pos)         /*!< 0x00000100 */
13387 #define GFXTIM_CGCR_LCCFR             GFXTIM_CGCR_LCCFR_Msk
13388 
13389 #define GFXTIM_CGCR_LCCHRS_Pos        (12U)
13390 #define GFXTIM_CGCR_LCCHRS_Msk        (0x7UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00007000 */
13391 #define GFXTIM_CGCR_LCCHRS            GFXTIM_CGCR_LCCHRS_Msk
13392 #define GFXTIM_CGCR_LCCHRS_0          (0x1UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00001000 */
13393 #define GFXTIM_CGCR_LCCHRS_1          (0x2UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00002000 */
13394 #define GFXTIM_CGCR_LCCHRS_2          (0x4UL << GFXTIM_CGCR_LCCHRS_Pos)        /*!< 0x00004000 */
13395 
13396 #define GFXTIM_CGCR_FCS_Pos           (16U)
13397 #define GFXTIM_CGCR_FCS_Msk           (0x7UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00000007 */
13398 #define GFXTIM_CGCR_FCS               GFXTIM_CGCR_FCS_Msk
13399 #define GFXTIM_CGCR_FCS_0             (0x1UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00001000 */
13400 #define GFXTIM_CGCR_FCS_1             (0x2UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00002000 */
13401 #define GFXTIM_CGCR_FCS_2             (0x4UL << GFXTIM_CGCR_FCS_Pos)           /*!< 0x00004000 */
13402 
13403 #define GFXTIM_CGCR_FCCCS_Pos         (20U)
13404 #define GFXTIM_CGCR_FCCCS_Msk         (0x7UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00070000 */
13405 #define GFXTIM_CGCR_FCCCS             GFXTIM_CGCR_FCCCS_Msk
13406 #define GFXTIM_CGCR_FCCCS_0           (0x1UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00010000 */
13407 #define GFXTIM_CGCR_FCCCS_1           (0x2UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00020000 */
13408 #define GFXTIM_CGCR_FCCCS_2           (0x4UL << GFXTIM_CGCR_FCCCS_Pos)         /*!< 0x00040000 */
13409 
13410 #define GFXTIM_CGCR_FCCFR_Pos         (24U)
13411 #define GFXTIM_CGCR_FCCFR_Msk         (0x1UL << GFXTIM_CGCR_FCCFR_Pos)         /*!< 0x00100000 */
13412 #define GFXTIM_CGCR_FCCFR             GFXTIM_CGCR_FCCFR_Msk
13413 
13414 #define GFXTIM_CGCR_FCCHRS_Pos        (28U)
13415 #define GFXTIM_CGCR_FCCHRS_Msk        (0x7UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x70000000 */
13416 #define GFXTIM_CGCR_FCCHRS            GFXTIM_CGCR_FCCHRS_Msk
13417 #define GFXTIM_CGCR_FCCHRS_0          (0x1UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x10000000 */
13418 #define GFXTIM_CGCR_FCCHRS_1          (0x2UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x20000000 */
13419 #define GFXTIM_CGCR_FCCHRS_2          (0x4UL << GFXTIM_CGCR_FCCHRS_Pos)        /*!< 0x40000000 */
13420 
13421 /******************  Bits definition for GFXTIM_TCR register  *****************/
13422 #define GFXTIM_TCR_AFCEN_Pos           (0U)
13423 #define GFXTIM_TCR_AFCEN_Msk           (0x1UL << GFXTIM_TCR_AFCEN_Pos)         /*!< 0x00000001 */
13424 #define GFXTIM_TCR_AFCEN               GFXTIM_TCR_AFCEN_Msk
13425 
13426 #define GFXTIM_TCR_FAFCR_Pos           (1U)
13427 #define GFXTIM_TCR_FAFCR_Msk           (0x1UL << GFXTIM_TCR_FAFCR_Pos)         /*!< 0x00000002 */
13428 #define GFXTIM_TCR_FAFCR               GFXTIM_TCR_FAFCR_Msk
13429 
13430 #define GFXTIM_TCR_ALCEN_Pos           (4U)
13431 #define GFXTIM_TCR_ALCEN_Msk           (0x1UL << GFXTIM_TCR_ALCEN_Pos)         /*!< 0x00000010 */
13432 #define GFXTIM_TCR_ALCEN               GFXTIM_TCR_ALCEN_Msk
13433 
13434 #define GFXTIM_TCR_FALCR_Pos           (5U)
13435 #define GFXTIM_TCR_FALCR_Msk           (0x1UL << GFXTIM_TCR_FALCR_Pos)         /*!< 0x00000020 */
13436 #define GFXTIM_TCR_FALCR               GFXTIM_TCR_FALCR_Msk
13437 
13438 #define GFXTIM_TCR_RFC1EN_Pos          (16U)
13439 #define GFXTIM_TCR_RFC1EN_Msk          (0x1UL << GFXTIM_TCR_RFC1EN_Pos)        /*!< 0x00010000 */
13440 #define GFXTIM_TCR_RFC1EN              GFXTIM_TCR_RFC1EN_Msk
13441 
13442 #define GFXTIM_TCR_RFC1CM_Pos          (17U)
13443 #define GFXTIM_TCR_RFC1CM_Msk          (0x1UL << GFXTIM_TCR_RFC1CM_Pos)        /*!< 0x00020000 */
13444 #define GFXTIM_TCR_RFC1CM              GFXTIM_TCR_RFC1CM_Msk
13445 
13446 #define GFXTIM_TCR_FRFC1R_Pos          (18U)
13447 #define GFXTIM_TCR_FRFC1R_Msk          (0x1UL << GFXTIM_TCR_FRFC1R_Pos)        /*!< 0x00040000 */
13448 #define GFXTIM_TCR_FRFC1R              GFXTIM_TCR_FRFC1R_Msk
13449 
13450 #define GFXTIM_TCR_RFC2EN_Pos          (20U)
13451 #define GFXTIM_TCR_RFC2EN_Msk          (0x1UL << GFXTIM_TCR_RFC2EN_Pos)        /*!< 0x00100000 */
13452 #define GFXTIM_TCR_RFC2EN              GFXTIM_TCR_RFC2EN_Msk
13453 
13454 #define GFXTIM_TCR_RFC2CM_Pos          (21U)
13455 #define GFXTIM_TCR_RFC2CM_Msk          (0x1UL << GFXTIM_TCR_RFC2CM_Pos)        /*!< 0x00200000 */
13456 #define GFXTIM_TCR_RFC2CM              GFXTIM_TCR_RFC2CM_Msk
13457 
13458 #define GFXTIM_TCR_FRFC2R_Pos          (22U)
13459 #define GFXTIM_TCR_FRFC2R_Msk          (0x1UL << GFXTIM_TCR_FRFC2R_Pos)        /*!< 0x00400000 */
13460 #define GFXTIM_TCR_FRFC2R              GFXTIM_TCR_FRFC2R_Msk
13461 
13462 /******************  Bits definition for GFXTIM_TDR register  *****************/
13463 #define GFXTIM_TDR_AFCDIS_Pos          (0U)
13464 #define GFXTIM_TDR_AFCDIS_Msk          (0x1UL << GFXTIM_TDR_AFCDIS_Pos)        /*!< 0x00000001 */
13465 #define GFXTIM_TDR_AFCDIS              GFXTIM_TDR_AFCDIS_Msk
13466 
13467 #define GFXTIM_TDR_ALCDIS_Pos          (4U)
13468 #define GFXTIM_TDR_ALCDIS_Msk          (0x1UL << GFXTIM_TDR_ALCDIS_Pos)        /*!< 0x00000010 */
13469 #define GFXTIM_TDR_ALCDIS              GFXTIM_TDR_ALCDIS_Msk
13470 
13471 #define GFXTIM_TDR_RFC1DIS_Pos         (16U)
13472 #define GFXTIM_TDR_RFC1DIS_Msk         (0x1UL << GFXTIM_TDR_RFC1DIS_Pos)       /*!< 0x00010000 */
13473 #define GFXTIM_TDR_RFC1DIS             GFXTIM_TDR_RFC1DIS_Msk
13474 
13475 #define GFXTIM_TDR_RFC2DIS_Pos         (20U)
13476 #define GFXTIM_TDR_RFC2DIS_Msk         (0x1UL << GFXTIM_TDR_RFC2DIS_Pos)       /*!< 0x00100000 */
13477 #define GFXTIM_TDR_RFC2DIS             GFXTIM_TDR_RFC2DIS_Msk
13478 
13479 /******************  Bits definition for GFXTIM_EVCR register  ****************/
13480 #define GFXTIM_EVCR_EV1EN_Pos          (0U)
13481 #define GFXTIM_EVCR_EV1EN_Msk          (0x1UL << GFXTIM_EVCR_EV1EN_Pos)        /*!< 0x00000001 */
13482 #define GFXTIM_EVCR_EV1EN              GFXTIM_EVCR_EV1EN_Msk
13483 
13484 #define GFXTIM_EVCR_EV2EN_Pos          (1U)
13485 #define GFXTIM_EVCR_EV2EN_Msk          (0x1UL << GFXTIM_EVCR_EV2EN_Pos)        /*!< 0x00000002 */
13486 #define GFXTIM_EVCR_EV2EN              GFXTIM_EVCR_EV2EN_Msk
13487 
13488 #define GFXTIM_EVCR_EV3EN_Pos          (2U)
13489 #define GFXTIM_EVCR_EV3EN_Msk          (0x1UL << GFXTIM_EVCR_EV3EN_Pos)        /*!< 0x00000004 */
13490 #define GFXTIM_EVCR_EV3EN              GFXTIM_EVCR_EV3EN_Msk
13491 
13492 #define GFXTIM_EVCR_EV4EN_Pos          (3U)
13493 #define GFXTIM_EVCR_EV4EN_Msk          (0x1UL << GFXTIM_EVCR_EV4EN_Pos)        /*!< 0x00000008 */
13494 #define GFXTIM_EVCR_EV4EN              GFXTIM_EVCR_EV4EN_Msk
13495 
13496 /******************  Bits definition for GFXTIM_EVSR register  ****************/
13497 #define GFXTIM_EVSR_LES1_Pos           (0U)
13498 #define GFXTIM_EVSR_LES1_Msk           (0x7UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000007 */
13499 #define GFXTIM_EVSR_LES1               GFXTIM_EVSR_LES1_Msk
13500 #define GFXTIM_EVSR_LES1_0             (0x1UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000001 */
13501 #define GFXTIM_EVSR_LES1_1             (0x2UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000002 */
13502 #define GFXTIM_EVSR_LES1_2             (0x4UL << GFXTIM_EVSR_LES1_Pos)         /*!< 0x00000004 */
13503 
13504 #define GFXTIM_EVSR_FES1_Pos           (4U)
13505 #define GFXTIM_EVSR_FES1_Msk           (0x7UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000070 */
13506 #define GFXTIM_EVSR_FES1               GFXTIM_EVSR_FES1_Msk
13507 #define GFXTIM_EVSR_FES1_0             (0x1UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000010 */
13508 #define GFXTIM_EVSR_FES1_1             (0x2UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000020 */
13509 #define GFXTIM_EVSR_FES1_2             (0x4UL << GFXTIM_EVSR_FES1_Pos)         /*!< 0x00000040 */
13510 
13511 #define GFXTIM_EVSR_LES2_Pos           (8U)
13512 #define GFXTIM_EVSR_LES2_Msk           (0x7UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000700 */
13513 #define GFXTIM_EVSR_LES2               GFXTIM_EVSR_LES2_Msk
13514 #define GFXTIM_EVSR_LES2_0             (0x1UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000100 */
13515 #define GFXTIM_EVSR_LES2_1             (0x2UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000200 */
13516 #define GFXTIM_EVSR_LES2_2             (0x4UL << GFXTIM_EVSR_LES2_Pos)         /*!< 0x00000400 */
13517 
13518 #define GFXTIM_EVSR_FES2_Pos           (12U)
13519 #define GFXTIM_EVSR_FES2_Msk           (0x7UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00007000 */
13520 #define GFXTIM_EVSR_FES2               GFXTIM_EVSR_FES2_Msk
13521 #define GFXTIM_EVSR_FES2_0             (0x1UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00001000 */
13522 #define GFXTIM_EVSR_FES2_1             (0x2UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00002000 */
13523 #define GFXTIM_EVSR_FES2_2             (0x4UL << GFXTIM_EVSR_FES2_Pos)         /*!< 0x00004000 */
13524 
13525 #define GFXTIM_EVSR_LES3_Pos           (16U)
13526 #define GFXTIM_EVSR_LES3_Msk           (0x7UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00070000 */
13527 #define GFXTIM_EVSR_LES3               GFXTIM_EVSR_LES3_Msk
13528 #define GFXTIM_EVSR_LES3_0             (0x1UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00010000 */
13529 #define GFXTIM_EVSR_LES3_1             (0x2UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00020000 */
13530 #define GFXTIM_EVSR_LES3_2             (0x4UL << GFXTIM_EVSR_LES3_Pos)         /*!< 0x00040000 */
13531 
13532 #define GFXTIM_EVSR_FES3_Pos           (20U)
13533 #define GFXTIM_EVSR_FES3_Msk           (0x7UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00700000 */
13534 #define GFXTIM_EVSR_FES3               GFXTIM_EVSR_FES3_Msk
13535 #define GFXTIM_EVSR_FES3_0             (0x1UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00100000 */
13536 #define GFXTIM_EVSR_FES3_1             (0x2UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00200000 */
13537 #define GFXTIM_EVSR_FES3_2             (0x4UL << GFXTIM_EVSR_FES3_Pos)         /*!< 0x00400000 */
13538 
13539 #define GFXTIM_EVSR_LES4_Pos           (24U)
13540 #define GFXTIM_EVSR_LES4_Msk           (0x7UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x07000000 */
13541 #define GFXTIM_EVSR_LES4               GFXTIM_EVSR_LES4_Msk
13542 #define GFXTIM_EVSR_LES4_0             (0x1UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x01000000 */
13543 #define GFXTIM_EVSR_LES4_1             (0x2UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x02000000 */
13544 #define GFXTIM_EVSR_LES4_2             (0x4UL << GFXTIM_EVSR_LES4_Pos)         /*!< 0x04000000 */
13545 
13546 #define GFXTIM_EVSR_FES4_Pos           (28U)
13547 #define GFXTIM_EVSR_FES4_Msk           (0x7UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x70000000 */
13548 #define GFXTIM_EVSR_FES4               GFXTIM_EVSR_FES4_Msk
13549 #define GFXTIM_EVSR_FES4_0             (0x1UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x10000000 */
13550 #define GFXTIM_EVSR_FES4_1             (0x2UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x20000000 */
13551 #define GFXTIM_EVSR_FES4_2             (0x4UL << GFXTIM_EVSR_FES4_Pos)         /*!< 0x40000000 */
13552 
13553 /******************  Bits definition for GFXTIM_WDGTCR register  **************/
13554 #define GFXTIM_WDGTCR_WDGEN_Pos        (0U)
13555 #define GFXTIM_WDGTCR_WDGEN_Msk        (0x1UL << GFXTIM_WDGTCR_WDGEN_Pos)      /*!< 0x00000001 */
13556 #define GFXTIM_WDGTCR_WDGEN            GFXTIM_WDGTCR_WDGEN_Msk
13557 
13558 #define GFXTIM_WDGTCR_WDGDIS_Pos       (1U)
13559 #define GFXTIM_WDGTCR_WDGDIS_Msk       (0x1UL << GFXTIM_WDGTCR_WDGDIS_Pos)     /*!< 0x00000002 */
13560 #define GFXTIM_WDGTCR_WDGDIS           GFXTIM_WDGTCR_WDGDIS_Msk
13561 
13562 #define GFXTIM_WDGTCR_WDGS_Pos         (2U)
13563 #define GFXTIM_WDGTCR_WDGS_Msk         (0x1UL << GFXTIM_WDGTCR_WDGS_Pos)       /*!< 0x00000004 */
13564 #define GFXTIM_WDGTCR_WDGS             GFXTIM_WDGTCR_WDGS_Msk
13565 
13566 #define GFXTIM_WDGTCR_WDGHRC_Pos       (4U)
13567 #define GFXTIM_WDGTCR_WDGHRC_Msk       (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000030 */
13568 #define GFXTIM_WDGTCR_WDGHRC           GFXTIM_WDGTCR_WDGHRC_Msk
13569 #define GFXTIM_WDGTCR_WDGHRC_0         (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000010 */
13570 #define GFXTIM_WDGTCR_WDGHRC_1         (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos)     /*!< 0x00000020 */
13571 
13572 #define GFXTIM_WDGTCR_WDGCS_Pos        (8U)
13573 #define GFXTIM_WDGTCR_WDGCS_Msk        (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000700 */
13574 #define GFXTIM_WDGTCR_WDGCS            GFXTIM_WDGTCR_WDGCS_Msk
13575 #define GFXTIM_WDGTCR_WDGCS_0          (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000100 */
13576 #define GFXTIM_WDGTCR_WDGCS_1          (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000200 */
13577 #define GFXTIM_WDGTCR_WDGCS_2          (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000400 */
13578 #define GFXTIM_WDGTCR_WDGCS_3          (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos)      /*!< 0x00000800 */
13579 
13580 #define GFXTIM_WDGTCR_FWDGR_Pos        (16U)
13581 #define GFXTIM_WDGTCR_FWDGR_Msk        (0x1UL << GFXTIM_WDGTCR_FWDGR_Pos)      /*!< 0x00010000 */
13582 #define GFXTIM_WDGTCR_FWDGR            GFXTIM_WDGTCR_FWDGR_Msk
13583 
13584 /******************  Bits definition for GFXTIM_ISR register  *****************/
13585 #define GFXTIM_ISR_AFCOF_Pos           (0U)
13586 #define GFXTIM_ISR_AFCOF_Msk           (0x1UL << GFXTIM_ISR_AFCOF_Pos)         /*!< 0x00000001 */
13587 #define GFXTIM_ISR_AFCOF               GFXTIM_ISR_AFCOF_Msk
13588 
13589 #define GFXTIM_ISR_ALCOF_Pos           (1U)
13590 #define GFXTIM_ISR_ALCOF_Msk           (0x1UL << GFXTIM_ISR_ALCOF_Pos)         /*!< 0x00000002 */
13591 #define GFXTIM_ISR_ALCOF               GFXTIM_ISR_ALCOF_Msk
13592 
13593 #define GFXTIM_ISR_TEF_Pos             (2U)
13594 #define GFXTIM_ISR_TEF_Msk             (0x1UL << GFXTIM_ISR_TEF_Pos)           /*!< 0x00000004 */
13595 #define GFXTIM_ISR_TEF                 GFXTIM_ISR_TEF_Msk
13596 
13597 #define GFXTIM_ISR_AFCC1F_Pos          (4U)
13598 #define GFXTIM_ISR_AFCC1F_Msk          (0x1UL << GFXTIM_ISR_AFCC1F_Pos)        /*!< 0x00000010 */
13599 #define GFXTIM_ISR_AFCC1F              GFXTIM_ISR_AFCC1F_Msk
13600 
13601 #define GFXTIM_ISR_ALCC1F_Pos          (8U)
13602 #define GFXTIM_ISR_ALCC1F_Msk          (0x1UL << GFXTIM_ISR_ALCC1F_Pos)        /*!< 0x00000100 */
13603 #define GFXTIM_ISR_ALCC1F              GFXTIM_ISR_ALCC1F_Msk
13604 
13605 #define GFXTIM_ISR_ALCC2F_Pos          (9U)
13606 #define GFXTIM_ISR_ALCC2F_Msk          (0x1UL << GFXTIM_ISR_ALCC2F_Pos)        /*!< 0x00000200 */
13607 #define GFXTIM_ISR_ALCC2F              GFXTIM_ISR_ALCC2F_Msk
13608 
13609 #define GFXTIM_ISR_RFC1RF_Pos          (12U)
13610 #define GFXTIM_ISR_RFC1RF_Msk          (0x1UL << GFXTIM_ISR_RFC1RF_Pos)        /*!< 0x00001000 */
13611 #define GFXTIM_ISR_RFC1RF              GFXTIM_ISR_RFC1RF_Msk
13612 
13613 #define GFXTIM_ISR_RFC2RF_Pos          (13U)
13614 #define GFXTIM_ISR_RFC2RF_Msk          (0x1UL << GFXTIM_ISR_RFC2RF_Pos)        /*!< 0x00002000 */
13615 #define GFXTIM_ISR_RFC2RF              GFXTIM_ISR_RFC2RF_Msk
13616 
13617 #define GFXTIM_ISR_EV1F_Pos            (16U)
13618 #define GFXTIM_ISR_EV1F_Msk            (0x1UL << GFXTIM_ISR_EV1F_Pos)          /*!< 0x00010000 */
13619 #define GFXTIM_ISR_EV1F                GFXTIM_ISR_EV1F_Msk
13620 
13621 #define GFXTIM_ISR_EV2F_Pos            (17U)
13622 #define GFXTIM_ISR_EV2F_Msk            (0x1UL << GFXTIM_ISR_EV2F_Pos)          /*!< 0x00020000 */
13623 #define GFXTIM_ISR_EV2F                GFXTIM_ISR_EV2F_Msk
13624 
13625 #define GFXTIM_ISR_EV3F_Pos            (18U)
13626 #define GFXTIM_ISR_EV3F_Msk            (0x1UL << GFXTIM_ISR_EV3F_Pos)          /*!< 0x00040000 */
13627 #define GFXTIM_ISR_EV3F                GFXTIM_ISR_EV3F_Msk
13628 
13629 #define GFXTIM_ISR_EV4F_Pos            (19U)
13630 #define GFXTIM_ISR_EV4F_Msk            (0x1UL << GFXTIM_ISR_EV4F_Pos)          /*!< 0x00080000 */
13631 #define GFXTIM_ISR_EV4F                GFXTIM_ISR_EV4F_Msk
13632 
13633 #define GFXTIM_ISR_WDGAF_Pos           (24U)
13634 #define GFXTIM_ISR_WDGAF_Msk           (0x1UL << GFXTIM_ISR_WDGAF_Pos)         /*!< 0x01000000 */
13635 #define GFXTIM_ISR_WDGAF               GFXTIM_ISR_WDGAF_Msk
13636 
13637 #define GFXTIM_ISR_WDGPF_Pos           (25U)
13638 #define GFXTIM_ISR_WDGPF_Msk           (0x1UL << GFXTIM_ISR_WDGPF_Pos)         /*!< 0x02000000 */
13639 #define GFXTIM_ISR_WDGPF               GFXTIM_ISR_WDGPF_Msk
13640 
13641 /******************  Bits definition for GFXTIM_ICR register  *****************/
13642 #define GFXTIM_ICR_CAFCOF_Pos          (0U)
13643 #define GFXTIM_ICR_CAFCOF_Msk          (0x1UL << GFXTIM_ICR_CAFCOF_Pos)        /*!< 0x00000001 */
13644 #define GFXTIM_ICR_CAFCOF              GFXTIM_ICR_CAFCOF_Msk
13645 
13646 #define GFXTIM_ICR_CALCOF_Pos          (1U)
13647 #define GFXTIM_ICR_CALCOF_Msk          (0x1UL << GFXTIM_ICR_CALCOF_Pos)        /*!< 0x00000002 */
13648 #define GFXTIM_ICR_CALCOF              GFXTIM_ICR_CALCOF_Msk
13649 
13650 #define GFXTIM_ICR_CTEF_Pos            (2U)
13651 #define GFXTIM_ICR_CTEF_Msk            (0x1UL << GFXTIM_ICR_CTEF_Pos)          /*!< 0x00000004 */
13652 #define GFXTIM_ICR_CTEF                GFXTIM_ICR_CTEF_Msk
13653 
13654 #define GFXTIM_ICR_CAFCC1F_Pos         (4U)
13655 #define GFXTIM_ICR_CAFCC1F_Msk         (0x1UL << GFXTIM_ICR_CAFCC1F_Pos)       /*!< 0x00000010 */
13656 #define GFXTIM_ICR_CAFCC1F             GFXTIM_ICR_CAFCC1F_Msk
13657 
13658 #define GFXTIM_ICR_CALCC1F_Pos         (8U)
13659 #define GFXTIM_ICR_CALCC1F_Msk         (0x1UL << GFXTIM_ICR_CALCC1F_Pos)       /*!< 0x00000100 */
13660 #define GFXTIM_ICR_CALCC1F             GFXTIM_ICR_CALCC1F_Msk
13661 
13662 #define GFXTIM_ICR_CALCC2F_Pos         (9U)
13663 #define GFXTIM_ICR_CALCC2F_Msk         (0x1UL << GFXTIM_ICR_CALCC2F_Pos)       /*!< 0x00000200 */
13664 #define GFXTIM_ICR_CALCC2F             GFXTIM_ICR_CALCC2F_Msk
13665 
13666 #define GFXTIM_ICR_CRFC1RF_Pos         (12U)
13667 #define GFXTIM_ICR_CRFC1RF_Msk         (0x1UL << GFXTIM_ICR_CRFC1RF_Pos)       /*!< 0x00001000 */
13668 #define GFXTIM_ICR_CRFC1RF             GFXTIM_ICR_CRFC1RF_Msk
13669 
13670 #define GFXTIM_ICR_CRFC2RF_Pos         (13U)
13671 #define GFXTIM_ICR_CRFC2RF_Msk         (0x1UL << GFXTIM_ICR_CRFC2RF_Pos)       /*!< 0x00002000 */
13672 #define GFXTIM_ICR_CRFC2RF             GFXTIM_ICR_CRFC2RF_Msk
13673 
13674 #define GFXTIM_ICR_CEV1F_Pos           (16U)
13675 #define GFXTIM_ICR_CEV1F_Msk           (0x1UL << GFXTIM_ICR_CEV1F_Pos)         /*!< 0x00010000 */
13676 #define GFXTIM_ICR_CEV1F               GFXTIM_ICR_CEV1F_Msk
13677 
13678 #define GFXTIM_ICR_CEV2F_Pos           (17U)
13679 #define GFXTIM_ICR_CEV2F_Msk           (0x1UL << GFXTIM_ICR_CEV2F_Pos)         /*!< 0x00020000 */
13680 #define GFXTIM_ICR_CEV2F               GFXTIM_ICR_CEV2F_Msk
13681 
13682 #define GFXTIM_ICR_CEV3F_Pos           (18U)
13683 #define GFXTIM_ICR_CEV3F_Msk           (0x1UL << GFXTIM_ICR_CEV3F_Pos)         /*!< 0x00040000 */
13684 #define GFXTIM_ICR_CEV3F               GFXTIM_ICR_CEV3F_Msk
13685 
13686 #define GFXTIM_ICR_CEV4F_Pos           (19U)
13687 #define GFXTIM_ICR_CEV4F_Msk           (0x1UL << GFXTIM_ICR_CEV4F_Pos)         /*!< 0x00080000 */
13688 #define GFXTIM_ICR_CEV4F               GFXTIM_ICR_CEV4F_Msk
13689 
13690 #define GFXTIM_ICR_CWDGAF_Pos          (24U)
13691 #define GFXTIM_ICR_CWDGAF_Msk          (0x1UL << GFXTIM_ICR_CWDGAF_Pos)        /*!< 0x01000000 */
13692 #define GFXTIM_ICR_CWDGAF              GFXTIM_ICR_CWDGAF_Msk
13693 
13694 #define GFXTIM_ICR_CWDGPF_Pos          (25U)
13695 #define GFXTIM_ICR_CWDGPF_Msk          (0x1UL << GFXTIM_ICR_CWDGPF_Pos)        /*!< 0x02000000 */
13696 #define GFXTIM_ICR_CWDGPF              GFXTIM_ICR_CWDGPF_Msk
13697 
13698 /******************  Bits definition for GFXTIM_IER register  *****************/
13699 #define GFXTIM_IER_AFCOIE_Pos          (0U)
13700 #define GFXTIM_IER_AFCOIE_Msk          (0x1UL << GFXTIM_IER_AFCOIE_Pos)        /*!< 0x00000001 */
13701 #define GFXTIM_IER_AFCOIE              GFXTIM_IER_AFCOIE_Msk
13702 
13703 #define GFXTIM_IER_ALCOIE_Pos          (1U)
13704 #define GFXTIM_IER_ALCOIE_Msk          (0x1UL << GFXTIM_IER_ALCOIE_Pos)        /*!< 0x00000002 */
13705 #define GFXTIM_IER_ALCOIE              GFXTIM_IER_ALCOIE_Msk
13706 
13707 #define GFXTIM_IER_TEIE_Pos            (2U)
13708 #define GFXTIM_IER_TEIE_Msk            (0x1UL << GFXTIM_IER_TEIE_Pos)          /*!< 0x00000004 */
13709 #define GFXTIM_IER_TEIE                GFXTIM_IER_TEIE_Msk
13710 
13711 #define GFXTIM_IER_AFCC1IE_Pos         (4U)
13712 #define GFXTIM_IER_AFCC1IE_Msk         (0x1UL << GFXTIM_IER_AFCC1IE_Pos)       /*!< 0x00000010 */
13713 #define GFXTIM_IER_AFCC1IE             GFXTIM_IER_AFCC1IE_Msk
13714 
13715 #define GFXTIM_IER_ALCC1IE_Pos         (8U)
13716 #define GFXTIM_IER_ALCC1IE_Msk         (0x1UL << GFXTIM_IER_ALCC1IE_Pos)       /*!< 0x00000100 */
13717 #define GFXTIM_IER_ALCC1IE             GFXTIM_IER_ALCC1IE_Msk
13718 
13719 #define GFXTIM_IER_ALCC2IE_Pos         (9U)
13720 #define GFXTIM_IER_ALCC2IE_Msk         (0x1UL << GFXTIM_IER_ALCC2IE_Pos)       /*!< 0x00000200 */
13721 #define GFXTIM_IER_ALCC2IE             GFXTIM_IER_ALCC2IE_Msk
13722 
13723 #define GFXTIM_IER_RFC1RIE_Pos         (12U)
13724 #define GFXTIM_IER_RFC1RIE_Msk         (0x1UL << GFXTIM_IER_RFC1RIE_Pos)       /*!< 0x00001000 */
13725 #define GFXTIM_IER_RFC1RIE             GFXTIM_IER_RFC1RIE_Msk
13726 
13727 #define GFXTIM_IER_RFC2RIE_Pos         (13U)
13728 #define GFXTIM_IER_RFC2RIE_Msk         (0x1UL << GFXTIM_IER_RFC2RIE_Pos)       /*!< 0x00002000 */
13729 #define GFXTIM_IER_RFC2RIE             GFXTIM_IER_RFC2RIE_Msk
13730 
13731 #define GFXTIM_IER_EV1IE_Pos           (16U)
13732 #define GFXTIM_IER_EV1IE_Msk           (0x1UL << GFXTIM_IER_EV1IE_Pos)         /*!< 0x00010000 */
13733 #define GFXTIM_IER_EV1IE               GFXTIM_IER_EV1IE_Msk
13734 
13735 #define GFXTIM_IER_EV2IE_Pos           (17U)
13736 #define GFXTIM_IER_EV2IE_Msk           (0x1UL << GFXTIM_IER_EV2IE_Pos)         /*!< 0x00020000 */
13737 #define GFXTIM_IER_EV2IE               GFXTIM_IER_EV2IE_Msk
13738 
13739 #define GFXTIM_IER_EV3IE_Pos           (18U)
13740 #define GFXTIM_IER_EV3IE_Msk           (0x1UL << GFXTIM_IER_EV3IE_Pos)         /*!< 0x00040000 */
13741 #define GFXTIM_IER_EV3IE               GFXTIM_IER_EV3IE_Msk
13742 
13743 #define GFXTIM_IER_EV4IE_Pos           (19U)
13744 #define GFXTIM_IER_EV4IE_Msk           (0x1UL << GFXTIM_IER_EV4IE_Pos)         /*!< 0x00080000 */
13745 #define GFXTIM_IER_EV4IE               GFXTIM_IER_EV4IE_Msk
13746 
13747 #define GFXTIM_IER_WDGAIE_Pos          (24U)
13748 #define GFXTIM_IER_WDGAIE_Msk          (0x1UL << GFXTIM_IER_WDGAIE_Pos)        /*!< 0x01000000 */
13749 #define GFXTIM_IER_WDGAIE              GFXTIM_IER_WDGAIE_Msk
13750 
13751 #define GFXTIM_IER_WDGPIE_Pos          (25U)
13752 #define GFXTIM_IER_WDGPIE_Msk          (0x1UL << GFXTIM_IER_WDGPIE_Pos)        /*!< 0x02000000 */
13753 #define GFXTIM_IER_WDGPIE              GFXTIM_IER_WDGPIE_Msk
13754 
13755 /******************  Bits definition for GFXTIM_TSR register  *****************/
13756 #define GFXTIM_TSR_AFCS_Pos            (0U)
13757 #define GFXTIM_TSR_AFCS_Msk            (0x1UL << GFXTIM_TSR_AFCS_Pos)          /*!< 0x00000001 */
13758 #define GFXTIM_TSR_AFCS                GFXTIM_TSR_AFCS_Msk
13759 
13760 #define GFXTIM_TSR_ALCS_Pos            (4U)
13761 #define GFXTIM_TSR_ALCS_Msk            (0x1UL << GFXTIM_TSR_ALCS_Pos)          /*!< 0x00000010 */
13762 #define GFXTIM_TSR_ALCS                GFXTIM_TSR_ALCS_Msk
13763 
13764 #define GFXTIM_TSR_RFC1S_Pos           (16U)
13765 #define GFXTIM_TSR_RFC1S_Msk           (0x1UL << GFXTIM_TSR_RFC1S_Pos)         /*!< 0x00010000 */
13766 #define GFXTIM_TSR_RFC1S               GFXTIM_TSR_RFC1S_Msk
13767 
13768 #define GFXTIM_TSR_RFC2S_Pos           (20U)
13769 #define GFXTIM_TSR_RFC2S_Msk           (0x1UL << GFXTIM_TSR_RFC2S_Pos)         /*!< 0x00100000 */
13770 #define GFXTIM_TSR_RFC2S               GFXTIM_TSR_RFC2S_Msk
13771 
13772 /******************  Bits definition for GFXTIM_LCCRR register  ***************/
13773 #define GFXTIM_LCCRR_RELOAD_Pos        (0U)
13774 #define GFXTIM_LCCRR_RELOAD_Msk        (0x3FFFFFUL << GFXTIM_LCCRR_RELOAD_Pos) /*!< 0x003FFFFF */
13775 #define GFXTIM_LCCRR_RELOAD            GFXTIM_LCCRR_RELOAD_Msk
13776 
13777 /******************  Bits definition for GFXTIM_FCCRR register  ***************/
13778 #define GFXTIM_FCCRR_RELOAD_Pos        (0U)
13779 #define GFXTIM_FCCRR_RELOAD_Msk        (0xFFFUL << GFXTIM_FCCRR_RELOAD_Pos)    /*!< 0x00000FFF */
13780 #define GFXTIM_FCCRR_RELOAD            GFXTIM_FCCRR_RELOAD_Msk
13781 
13782 /******************  Bits definition for GFXTIM_ATR register  *****************/
13783 #define GFXTIM_ATR_LINE_Pos            (0U)
13784 #define GFXTIM_ATR_LINE_Msk            (0xFFFUL << GFXTIM_ATR_LINE_Pos)        /*!< 0x00000FFF */
13785 #define GFXTIM_ATR_LINE                GFXTIM_ATR_LINE_Msk
13786 
13787 #define GFXTIM_ATR_FRAME_Pos           (12U)
13788 #define GFXTIM_ATR_FRAME_Msk           (0xFFFFFUL << GFXTIM_ATR_FRAME_Pos)     /*!< 0xFFFFF000 */
13789 #define GFXTIM_ATR_FRAME               GFXTIM_ATR_FRAME_Msk
13790 
13791 /******************  Bits definition for GFXTIM_AFCR register  ****************/
13792 #define GFXTIM_AFCR_FRAME_Pos          (0U)
13793 #define GFXTIM_AFCR_FRAME_Msk          (0xFFFFFUL << GFXTIM_AFCR_FRAME_Pos)    /*!< 0x000FFFFF */
13794 #define GFXTIM_AFCR_FRAME              GFXTIM_AFCR_FRAME_Msk
13795 
13796 /******************  Bits definition for GFXTIM_ALCR register  ****************/
13797 #define GFXTIM_ALCR_LINE_Pos           (0U)
13798 #define GFXTIM_ALCR_LINE_Msk           (0xFFFUL << GFXTIM_ALCR_LINE_Pos)       /*!< 0x00000FFF */
13799 #define GFXTIM_ALCR_LINE               GFXTIM_ALCR_LINE_Msk
13800 
13801 /******************  Bits definition for GFXTIM_AFCC1R register  **************/
13802 #define GFXTIM_AFCC1R_FRAME_Pos        (0U)
13803 #define GFXTIM_AFCC1R_FRAME_Msk        (0xFFFFFUL << GFXTIM_AFCC1R_FRAME_Pos)  /*!< 0x000FFFFF */
13804 #define GFXTIM_AFCC1R_FRAME            GFXTIM_AFCC1R_FRAME_Msk
13805 
13806 /******************  Bits definition for GFXTIM_ALCC1R register  **************/
13807 #define GFXTIM_ALCC1R_LINE_Pos         (0U)
13808 #define GFXTIM_ALCC1R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC1R_LINE_Pos)     /*!< 0x00000FFF */
13809 #define GFXTIM_ALCC1R_LINE             GFXTIM_ALCC1R_LINE_Msk
13810 
13811 /******************  Bits definition for GFXTIM_ALCC2R register  **************/
13812 #define GFXTIM_ALCC2R_LINE_Pos         (0U)
13813 #define GFXTIM_ALCC2R_LINE_Msk         (0xFFFUL << GFXTIM_ALCC2R_LINE_Pos)     /*!< 0x00000FFF */
13814 #define GFXTIM_ALCC2R_LINE             GFXTIM_ALCC2R_LINE_Msk
13815 
13816 /******************  Bits definition for GFXTIM_RFC1R register  ***************/
13817 #define GFXTIM_RFC1R_FRAME_Pos         (0U)
13818 #define GFXTIM_RFC1R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC1R_FRAME_Pos)     /*!< 0x00000FFF */
13819 #define GFXTIM_RFC1R_FRAME             GFXTIM_RFC1R_FRAME_Msk
13820 
13821 /******************  Bits definition for GFXTIM_RFC1RR register  **************/
13822 #define GFXTIM_RFC1RR_FRAME_Pos        (0U)
13823 #define GFXTIM_RFC1RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC1RR_FRAME_Pos)    /*!< 0x00000FFF */
13824 #define GFXTIM_RFC1RR_FRAME            GFXTIM_RFC1RR_FRAME_Msk
13825 
13826 /******************  Bits definition for GFXTIM_RFC2R register  ***************/
13827 #define GFXTIM_RFC2R_FRAME_Pos         (0U)
13828 #define GFXTIM_RFC2R_FRAME_Msk         (0xFFFUL << GFXTIM_RFC2R_FRAME_Pos)     /*!< 0x00000FFF */
13829 #define GFXTIM_RFC2R_FRAME             GFXTIM_RFC2R_FRAME_Msk
13830 
13831 /******************  Bits definition for GFXTIM_RFC2RR register  **************/
13832 #define GFXTIM_RFC2RR_FRAME_Pos        (0U)
13833 #define GFXTIM_RFC2RR_FRAME_Msk        (0xFFFUL << GFXTIM_RFC2RR_FRAME_Pos)    /*!< 0x00000FFF */
13834 #define GFXTIM_RFC2RR_FRAME            GFXTIM_RFC2RR_FRAME_Msk
13835 
13836 /******************  Bits definition for GFXTIM_WDGCR register  ***************/
13837 #define GFXTIM_WDGCR_VALUE_Pos         (0U)
13838 #define GFXTIM_WDGCR_VALUE_Msk         (0xFFFFUL << GFXTIM_WDGCR_VALUE_Pos)    /*!< 0x0000FFFF */
13839 #define GFXTIM_WDGCR_VALUE             GFXTIM_WDGCR_VALUE_Msk
13840 
13841 /******************  Bits definition for GFXTIM_WDGRR register  ***************/
13842 #define GFXTIM_WDGRR_RELOAD_Pos        (0U)
13843 #define GFXTIM_WDGRR_RELOAD_Msk        (0xFFFFUL << GFXTIM_WDGRR_RELOAD_Pos)   /*!< 0x0000FFFF */
13844 #define GFXTIM_WDGRR_RELOAD            GFXTIM_WDGRR_RELOAD_Msk
13845 
13846 /******************  Bits definition for GFXTIM_WDGPAR register  **************/
13847 #define GFXTIM_WDGPAR_PREALARM_Pos      (0U)
13848 #define GFXTIM_WDGPAR_PREALARM_Msk     (0xFFFFUL << GFXTIM_WDGPAR_PREALARM_Pos)/*!< 0x0000FFFF */
13849 #define GFXTIM_WDGPAR_PREALARM          GFXTIM_WDGPAR_PREALARM_Msk
13850 
13851 /******************  Bits definition for GFXTIM_HWCFGR register  **************/
13852 
13853 /******************  Bits definition for GFXTIM_VERR register  ****************/
13854 #define GFXTIM_VERR_MINREV_Pos         (0U)
13855 #define GFXTIM_VERR_MINREV_Msk         (0xFUL << GFXTIM_VERR_MINREV_Pos)       /*!< 0x0000000F */
13856 #define GFXTIM_VERR_MINREV             GFXTIM_VERR_MINREV_Msk
13857 
13858 #define GFXTIM_VERR_MAJREV_Pos         (4U)
13859 #define GFXTIM_VERR_MAJREV_Msk         (0xFUL << GFXTIM_VERR_MAJREV_Pos)       /*!< 0x000000F0 */
13860 #define GFXTIM_VERR_MAJREV             GFXTIM_VERR_MAJREV_Msk
13861 
13862 /******************  Bits definition for GFXTIM_IPIDR register  ***************/
13863 #define GFXTIM_IPIDR_ID_Pos            (0U)
13864 #define GFXTIM_IPIDR_ID_Msk            (0xFFFFFFFFUL << GFXTIM_IPIDR_ID_Pos)   /*!< 0xFFFFFFFF */
13865 #define GFXTIM_IPIDR_ID                GFXTIM_IPIDR_ID_Msk
13866 
13867 /******************  Bits definition for GFXTIM_SIDR register  ****************/
13868 #define GFXTIM_SIDR_SID_Pos            (0U)
13869 #define GFXTIM_SIDR_SID_Msk            (0xFFFFFFFFUL << GFXTIM_SIDR_SID_Pos)   /*!< 0xFFFFFFFF */
13870 #define GFXTIM_SIDR_SID                GFXTIM_SIDR_SID_Msk
13871 
13872 /******************************************************************************/
13873 /*                                                                            */
13874 /*                       General Purpose IOs (GPIO)                           */
13875 /*                                                                            */
13876 /******************************************************************************/
13877 /******************  Bits definition for GPIO_MODER register  *****************/
13878 #define GPIO_MODER_MODE0_Pos                (0U)
13879 #define GPIO_MODER_MODE0_Msk                (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
13880 #define GPIO_MODER_MODE0                    GPIO_MODER_MODE0_Msk
13881 #define GPIO_MODER_MODE0_0                  (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
13882 #define GPIO_MODER_MODE0_1                  (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
13883 #define GPIO_MODER_MODE1_Pos                (2U)
13884 #define GPIO_MODER_MODE1_Msk                (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
13885 #define GPIO_MODER_MODE1                    GPIO_MODER_MODE1_Msk
13886 #define GPIO_MODER_MODE1_0                  (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
13887 #define GPIO_MODER_MODE1_1                  (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
13888 #define GPIO_MODER_MODE2_Pos                (4U)
13889 #define GPIO_MODER_MODE2_Msk                (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
13890 #define GPIO_MODER_MODE2                    GPIO_MODER_MODE2_Msk
13891 #define GPIO_MODER_MODE2_0                  (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
13892 #define GPIO_MODER_MODE2_1                  (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
13893 #define GPIO_MODER_MODE3_Pos                (6U)
13894 #define GPIO_MODER_MODE3_Msk                (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
13895 #define GPIO_MODER_MODE3                    GPIO_MODER_MODE3_Msk
13896 #define GPIO_MODER_MODE3_0                  (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
13897 #define GPIO_MODER_MODE3_1                  (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
13898 #define GPIO_MODER_MODE4_Pos                (8U)
13899 #define GPIO_MODER_MODE4_Msk                (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
13900 #define GPIO_MODER_MODE4                    GPIO_MODER_MODE4_Msk
13901 #define GPIO_MODER_MODE4_0                  (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
13902 #define GPIO_MODER_MODE4_1                  (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
13903 #define GPIO_MODER_MODE5_Pos                (10U)
13904 #define GPIO_MODER_MODE5_Msk                (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
13905 #define GPIO_MODER_MODE5                    GPIO_MODER_MODE5_Msk
13906 #define GPIO_MODER_MODE5_0                  (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
13907 #define GPIO_MODER_MODE5_1                  (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
13908 #define GPIO_MODER_MODE6_Pos                (12U)
13909 #define GPIO_MODER_MODE6_Msk                (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
13910 #define GPIO_MODER_MODE6                    GPIO_MODER_MODE6_Msk
13911 #define GPIO_MODER_MODE6_0                  (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
13912 #define GPIO_MODER_MODE6_1                  (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
13913 #define GPIO_MODER_MODE7_Pos                (14U)
13914 #define GPIO_MODER_MODE7_Msk                (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
13915 #define GPIO_MODER_MODE7                    GPIO_MODER_MODE7_Msk
13916 #define GPIO_MODER_MODE7_0                  (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
13917 #define GPIO_MODER_MODE7_1                  (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
13918 #define GPIO_MODER_MODE8_Pos                (16U)
13919 #define GPIO_MODER_MODE8_Msk                (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
13920 #define GPIO_MODER_MODE8                    GPIO_MODER_MODE8_Msk
13921 #define GPIO_MODER_MODE8_0                  (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
13922 #define GPIO_MODER_MODE8_1                  (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
13923 #define GPIO_MODER_MODE9_Pos                (18U)
13924 #define GPIO_MODER_MODE9_Msk                (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
13925 #define GPIO_MODER_MODE9                    GPIO_MODER_MODE9_Msk
13926 #define GPIO_MODER_MODE9_0                  (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
13927 #define GPIO_MODER_MODE9_1                  (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
13928 #define GPIO_MODER_MODE10_Pos               (20U)
13929 #define GPIO_MODER_MODE10_Msk               (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
13930 #define GPIO_MODER_MODE10                   GPIO_MODER_MODE10_Msk
13931 #define GPIO_MODER_MODE10_0                 (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
13932 #define GPIO_MODER_MODE10_1                 (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
13933 #define GPIO_MODER_MODE11_Pos               (22U)
13934 #define GPIO_MODER_MODE11_Msk               (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
13935 #define GPIO_MODER_MODE11                   GPIO_MODER_MODE11_Msk
13936 #define GPIO_MODER_MODE11_0                 (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
13937 #define GPIO_MODER_MODE11_1                 (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
13938 #define GPIO_MODER_MODE12_Pos               (24U)
13939 #define GPIO_MODER_MODE12_Msk               (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
13940 #define GPIO_MODER_MODE12                   GPIO_MODER_MODE12_Msk
13941 #define GPIO_MODER_MODE12_0                 (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
13942 #define GPIO_MODER_MODE12_1                 (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
13943 #define GPIO_MODER_MODE13_Pos               (26U)
13944 #define GPIO_MODER_MODE13_Msk               (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
13945 #define GPIO_MODER_MODE13                   GPIO_MODER_MODE13_Msk
13946 #define GPIO_MODER_MODE13_0                 (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
13947 #define GPIO_MODER_MODE13_1                 (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
13948 #define GPIO_MODER_MODE14_Pos               (28U)
13949 #define GPIO_MODER_MODE14_Msk               (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
13950 #define GPIO_MODER_MODE14                   GPIO_MODER_MODE14_Msk
13951 #define GPIO_MODER_MODE14_0                 (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
13952 #define GPIO_MODER_MODE14_1                 (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
13953 #define GPIO_MODER_MODE15_Pos               (30U)
13954 #define GPIO_MODER_MODE15_Msk               (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
13955 #define GPIO_MODER_MODE15                   GPIO_MODER_MODE15_Msk
13956 #define GPIO_MODER_MODE15_0                 (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
13957 #define GPIO_MODER_MODE15_1                 (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
13958 
13959 /******************  Bits definition for GPIO_OTYPER register  ****************/
13960 #define GPIO_OTYPER_OT0_Pos                 (0U)
13961 #define GPIO_OTYPER_OT0_Msk                 (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
13962 #define GPIO_OTYPER_OT0                     GPIO_OTYPER_OT0_Msk
13963 #define GPIO_OTYPER_OT1_Pos                 (1U)
13964 #define GPIO_OTYPER_OT1_Msk                 (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
13965 #define GPIO_OTYPER_OT1                     GPIO_OTYPER_OT1_Msk
13966 #define GPIO_OTYPER_OT2_Pos                 (2U)
13967 #define GPIO_OTYPER_OT2_Msk                 (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
13968 #define GPIO_OTYPER_OT2                     GPIO_OTYPER_OT2_Msk
13969 #define GPIO_OTYPER_OT3_Pos                 (3U)
13970 #define GPIO_OTYPER_OT3_Msk                 (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
13971 #define GPIO_OTYPER_OT3                     GPIO_OTYPER_OT3_Msk
13972 #define GPIO_OTYPER_OT4_Pos                 (4U)
13973 #define GPIO_OTYPER_OT4_Msk                 (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
13974 #define GPIO_OTYPER_OT4                     GPIO_OTYPER_OT4_Msk
13975 #define GPIO_OTYPER_OT5_Pos                 (5U)
13976 #define GPIO_OTYPER_OT5_Msk                 (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
13977 #define GPIO_OTYPER_OT5                     GPIO_OTYPER_OT5_Msk
13978 #define GPIO_OTYPER_OT6_Pos                 (6U)
13979 #define GPIO_OTYPER_OT6_Msk                 (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
13980 #define GPIO_OTYPER_OT6                     GPIO_OTYPER_OT6_Msk
13981 #define GPIO_OTYPER_OT7_Pos                 (7U)
13982 #define GPIO_OTYPER_OT7_Msk                 (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
13983 #define GPIO_OTYPER_OT7                     GPIO_OTYPER_OT7_Msk
13984 #define GPIO_OTYPER_OT8_Pos                 (8U)
13985 #define GPIO_OTYPER_OT8_Msk                 (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
13986 #define GPIO_OTYPER_OT8                     GPIO_OTYPER_OT8_Msk
13987 #define GPIO_OTYPER_OT9_Pos                 (9U)
13988 #define GPIO_OTYPER_OT9_Msk                 (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
13989 #define GPIO_OTYPER_OT9                     GPIO_OTYPER_OT9_Msk
13990 #define GPIO_OTYPER_OT10_Pos                (10U)
13991 #define GPIO_OTYPER_OT10_Msk                (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
13992 #define GPIO_OTYPER_OT10                    GPIO_OTYPER_OT10_Msk
13993 #define GPIO_OTYPER_OT11_Pos                (11U)
13994 #define GPIO_OTYPER_OT11_Msk                (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
13995 #define GPIO_OTYPER_OT11                    GPIO_OTYPER_OT11_Msk
13996 #define GPIO_OTYPER_OT12_Pos                (12U)
13997 #define GPIO_OTYPER_OT12_Msk                (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
13998 #define GPIO_OTYPER_OT12                    GPIO_OTYPER_OT12_Msk
13999 #define GPIO_OTYPER_OT13_Pos                (13U)
14000 #define GPIO_OTYPER_OT13_Msk                (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
14001 #define GPIO_OTYPER_OT13                    GPIO_OTYPER_OT13_Msk
14002 #define GPIO_OTYPER_OT14_Pos                (14U)
14003 #define GPIO_OTYPER_OT14_Msk                (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
14004 #define GPIO_OTYPER_OT14                    GPIO_OTYPER_OT14_Msk
14005 #define GPIO_OTYPER_OT15_Pos                (15U)
14006 #define GPIO_OTYPER_OT15_Msk                (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
14007 #define GPIO_OTYPER_OT15                    GPIO_OTYPER_OT15_Msk
14008 
14009 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
14010 #define GPIO_OSPEEDR_OSPEED0_Pos            (0U)
14011 #define GPIO_OSPEEDR_OSPEED0_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
14012 #define GPIO_OSPEEDR_OSPEED0                GPIO_OSPEEDR_OSPEED0_Msk
14013 #define GPIO_OSPEEDR_OSPEED0_0              (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
14014 #define GPIO_OSPEEDR_OSPEED0_1              (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
14015 #define GPIO_OSPEEDR_OSPEED1_Pos            (2U)
14016 #define GPIO_OSPEEDR_OSPEED1_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
14017 #define GPIO_OSPEEDR_OSPEED1                GPIO_OSPEEDR_OSPEED1_Msk
14018 #define GPIO_OSPEEDR_OSPEED1_0              (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
14019 #define GPIO_OSPEEDR_OSPEED1_1              (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
14020 #define GPIO_OSPEEDR_OSPEED2_Pos            (4U)
14021 #define GPIO_OSPEEDR_OSPEED2_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
14022 #define GPIO_OSPEEDR_OSPEED2                GPIO_OSPEEDR_OSPEED2_Msk
14023 #define GPIO_OSPEEDR_OSPEED2_0              (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
14024 #define GPIO_OSPEEDR_OSPEED2_1              (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
14025 #define GPIO_OSPEEDR_OSPEED3_Pos            (6U)
14026 #define GPIO_OSPEEDR_OSPEED3_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
14027 #define GPIO_OSPEEDR_OSPEED3                GPIO_OSPEEDR_OSPEED3_Msk
14028 #define GPIO_OSPEEDR_OSPEED3_0              (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
14029 #define GPIO_OSPEEDR_OSPEED3_1              (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
14030 #define GPIO_OSPEEDR_OSPEED4_Pos            (8U)
14031 #define GPIO_OSPEEDR_OSPEED4_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
14032 #define GPIO_OSPEEDR_OSPEED4                GPIO_OSPEEDR_OSPEED4_Msk
14033 #define GPIO_OSPEEDR_OSPEED4_0              (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
14034 #define GPIO_OSPEEDR_OSPEED4_1              (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
14035 #define GPIO_OSPEEDR_OSPEED5_Pos            (10U)
14036 #define GPIO_OSPEEDR_OSPEED5_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
14037 #define GPIO_OSPEEDR_OSPEED5                GPIO_OSPEEDR_OSPEED5_Msk
14038 #define GPIO_OSPEEDR_OSPEED5_0              (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
14039 #define GPIO_OSPEEDR_OSPEED5_1              (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
14040 #define GPIO_OSPEEDR_OSPEED6_Pos            (12U)
14041 #define GPIO_OSPEEDR_OSPEED6_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
14042 #define GPIO_OSPEEDR_OSPEED6                GPIO_OSPEEDR_OSPEED6_Msk
14043 #define GPIO_OSPEEDR_OSPEED6_0              (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
14044 #define GPIO_OSPEEDR_OSPEED6_1              (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
14045 #define GPIO_OSPEEDR_OSPEED7_Pos            (14U)
14046 #define GPIO_OSPEEDR_OSPEED7_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
14047 #define GPIO_OSPEEDR_OSPEED7                GPIO_OSPEEDR_OSPEED7_Msk
14048 #define GPIO_OSPEEDR_OSPEED7_0              (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
14049 #define GPIO_OSPEEDR_OSPEED7_1              (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
14050 #define GPIO_OSPEEDR_OSPEED8_Pos            (16U)
14051 #define GPIO_OSPEEDR_OSPEED8_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
14052 #define GPIO_OSPEEDR_OSPEED8                GPIO_OSPEEDR_OSPEED8_Msk
14053 #define GPIO_OSPEEDR_OSPEED8_0              (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
14054 #define GPIO_OSPEEDR_OSPEED8_1              (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
14055 #define GPIO_OSPEEDR_OSPEED9_Pos            (18U)
14056 #define GPIO_OSPEEDR_OSPEED9_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
14057 #define GPIO_OSPEEDR_OSPEED9                GPIO_OSPEEDR_OSPEED9_Msk
14058 #define GPIO_OSPEEDR_OSPEED9_0              (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
14059 #define GPIO_OSPEEDR_OSPEED9_1              (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
14060 #define GPIO_OSPEEDR_OSPEED10_Pos           (20U)
14061 #define GPIO_OSPEEDR_OSPEED10_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
14062 #define GPIO_OSPEEDR_OSPEED10               GPIO_OSPEEDR_OSPEED10_Msk
14063 #define GPIO_OSPEEDR_OSPEED10_0             (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
14064 #define GPIO_OSPEEDR_OSPEED10_1             (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
14065 #define GPIO_OSPEEDR_OSPEED11_Pos           (22U)
14066 #define GPIO_OSPEEDR_OSPEED11_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
14067 #define GPIO_OSPEEDR_OSPEED11               GPIO_OSPEEDR_OSPEED11_Msk
14068 #define GPIO_OSPEEDR_OSPEED11_0             (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
14069 #define GPIO_OSPEEDR_OSPEED11_1             (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
14070 #define GPIO_OSPEEDR_OSPEED12_Pos           (24U)
14071 #define GPIO_OSPEEDR_OSPEED12_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
14072 #define GPIO_OSPEEDR_OSPEED12               GPIO_OSPEEDR_OSPEED12_Msk
14073 #define GPIO_OSPEEDR_OSPEED12_0             (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
14074 #define GPIO_OSPEEDR_OSPEED12_1             (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
14075 #define GPIO_OSPEEDR_OSPEED13_Pos           (26U)
14076 #define GPIO_OSPEEDR_OSPEED13_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
14077 #define GPIO_OSPEEDR_OSPEED13               GPIO_OSPEEDR_OSPEED13_Msk
14078 #define GPIO_OSPEEDR_OSPEED13_0             (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
14079 #define GPIO_OSPEEDR_OSPEED13_1             (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
14080 #define GPIO_OSPEEDR_OSPEED14_Pos           (28U)
14081 #define GPIO_OSPEEDR_OSPEED14_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
14082 #define GPIO_OSPEEDR_OSPEED14               GPIO_OSPEEDR_OSPEED14_Msk
14083 #define GPIO_OSPEEDR_OSPEED14_0             (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
14084 #define GPIO_OSPEEDR_OSPEED14_1             (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
14085 #define GPIO_OSPEEDR_OSPEED15_Pos           (30U)
14086 #define GPIO_OSPEEDR_OSPEED15_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
14087 #define GPIO_OSPEEDR_OSPEED15               GPIO_OSPEEDR_OSPEED15_Msk
14088 #define GPIO_OSPEEDR_OSPEED15_0             (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
14089 #define GPIO_OSPEEDR_OSPEED15_1             (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
14090 
14091 /******************  Bits definition for GPIO_PUPDR register  *****************/
14092 #define GPIO_PUPDR_PUPD0_Pos                (0U)
14093 #define GPIO_PUPDR_PUPD0_Msk                (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
14094 #define GPIO_PUPDR_PUPD0                    GPIO_PUPDR_PUPD0_Msk
14095 #define GPIO_PUPDR_PUPD0_0                  (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
14096 #define GPIO_PUPDR_PUPD0_1                  (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
14097 #define GPIO_PUPDR_PUPD1_Pos                (2U)
14098 #define GPIO_PUPDR_PUPD1_Msk                (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
14099 #define GPIO_PUPDR_PUPD1                    GPIO_PUPDR_PUPD1_Msk
14100 #define GPIO_PUPDR_PUPD1_0                  (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
14101 #define GPIO_PUPDR_PUPD1_1                  (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
14102 #define GPIO_PUPDR_PUPD2_Pos                (4U)
14103 #define GPIO_PUPDR_PUPD2_Msk                (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
14104 #define GPIO_PUPDR_PUPD2                    GPIO_PUPDR_PUPD2_Msk
14105 #define GPIO_PUPDR_PUPD2_0                  (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
14106 #define GPIO_PUPDR_PUPD2_1                  (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
14107 #define GPIO_PUPDR_PUPD3_Pos                (6U)
14108 #define GPIO_PUPDR_PUPD3_Msk                (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
14109 #define GPIO_PUPDR_PUPD3                    GPIO_PUPDR_PUPD3_Msk
14110 #define GPIO_PUPDR_PUPD3_0                  (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
14111 #define GPIO_PUPDR_PUPD3_1                  (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
14112 #define GPIO_PUPDR_PUPD4_Pos                (8U)
14113 #define GPIO_PUPDR_PUPD4_Msk                (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
14114 #define GPIO_PUPDR_PUPD4                    GPIO_PUPDR_PUPD4_Msk
14115 #define GPIO_PUPDR_PUPD4_0                  (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
14116 #define GPIO_PUPDR_PUPD4_1                  (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
14117 #define GPIO_PUPDR_PUPD5_Pos                (10U)
14118 #define GPIO_PUPDR_PUPD5_Msk                (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
14119 #define GPIO_PUPDR_PUPD5                    GPIO_PUPDR_PUPD5_Msk
14120 #define GPIO_PUPDR_PUPD5_0                  (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
14121 #define GPIO_PUPDR_PUPD5_1                  (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
14122 #define GPIO_PUPDR_PUPD6_Pos                (12U)
14123 #define GPIO_PUPDR_PUPD6_Msk                (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
14124 #define GPIO_PUPDR_PUPD6                    GPIO_PUPDR_PUPD6_Msk
14125 #define GPIO_PUPDR_PUPD6_0                  (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
14126 #define GPIO_PUPDR_PUPD6_1                  (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
14127 #define GPIO_PUPDR_PUPD7_Pos                (14U)
14128 #define GPIO_PUPDR_PUPD7_Msk                (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
14129 #define GPIO_PUPDR_PUPD7                    GPIO_PUPDR_PUPD7_Msk
14130 #define GPIO_PUPDR_PUPD7_0                  (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
14131 #define GPIO_PUPDR_PUPD7_1                  (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
14132 #define GPIO_PUPDR_PUPD8_Pos                (16U)
14133 #define GPIO_PUPDR_PUPD8_Msk                (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
14134 #define GPIO_PUPDR_PUPD8                    GPIO_PUPDR_PUPD8_Msk
14135 #define GPIO_PUPDR_PUPD8_0                  (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
14136 #define GPIO_PUPDR_PUPD8_1                  (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
14137 #define GPIO_PUPDR_PUPD9_Pos                (18U)
14138 #define GPIO_PUPDR_PUPD9_Msk                (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
14139 #define GPIO_PUPDR_PUPD9                    GPIO_PUPDR_PUPD9_Msk
14140 #define GPIO_PUPDR_PUPD9_0                  (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
14141 #define GPIO_PUPDR_PUPD9_1                  (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
14142 #define GPIO_PUPDR_PUPD10_Pos               (20U)
14143 #define GPIO_PUPDR_PUPD10_Msk               (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
14144 #define GPIO_PUPDR_PUPD10                   GPIO_PUPDR_PUPD10_Msk
14145 #define GPIO_PUPDR_PUPD10_0                 (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
14146 #define GPIO_PUPDR_PUPD10_1                 (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
14147 #define GPIO_PUPDR_PUPD11_Pos               (22U)
14148 #define GPIO_PUPDR_PUPD11_Msk               (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
14149 #define GPIO_PUPDR_PUPD11                   GPIO_PUPDR_PUPD11_Msk
14150 #define GPIO_PUPDR_PUPD11_0                 (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
14151 #define GPIO_PUPDR_PUPD11_1                 (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
14152 #define GPIO_PUPDR_PUPD12_Pos               (24U)
14153 #define GPIO_PUPDR_PUPD12_Msk               (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
14154 #define GPIO_PUPDR_PUPD12                   GPIO_PUPDR_PUPD12_Msk
14155 #define GPIO_PUPDR_PUPD12_0                 (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
14156 #define GPIO_PUPDR_PUPD12_1                 (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
14157 #define GPIO_PUPDR_PUPD13_Pos               (26U)
14158 #define GPIO_PUPDR_PUPD13_Msk               (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
14159 #define GPIO_PUPDR_PUPD13                   GPIO_PUPDR_PUPD13_Msk
14160 #define GPIO_PUPDR_PUPD13_0                 (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
14161 #define GPIO_PUPDR_PUPD13_1                 (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
14162 #define GPIO_PUPDR_PUPD14_Pos               (28U)
14163 #define GPIO_PUPDR_PUPD14_Msk               (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
14164 #define GPIO_PUPDR_PUPD14                   GPIO_PUPDR_PUPD14_Msk
14165 #define GPIO_PUPDR_PUPD14_0                 (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
14166 #define GPIO_PUPDR_PUPD14_1                 (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
14167 #define GPIO_PUPDR_PUPD15_Pos               (30U)
14168 #define GPIO_PUPDR_PUPD15_Msk               (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
14169 #define GPIO_PUPDR_PUPD15                   GPIO_PUPDR_PUPD15_Msk
14170 #define GPIO_PUPDR_PUPD15_0                 (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
14171 #define GPIO_PUPDR_PUPD15_1                 (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
14172 
14173 /******************  Bits definition for GPIO_IDR register  *******************/
14174 #define GPIO_IDR_ID0_Pos                    (0U)
14175 #define GPIO_IDR_ID0_Msk                    (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
14176 #define GPIO_IDR_ID0                        GPIO_IDR_ID0_Msk
14177 #define GPIO_IDR_ID1_Pos                    (1U)
14178 #define GPIO_IDR_ID1_Msk                    (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
14179 #define GPIO_IDR_ID1                        GPIO_IDR_ID1_Msk
14180 #define GPIO_IDR_ID2_Pos                    (2U)
14181 #define GPIO_IDR_ID2_Msk                    (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
14182 #define GPIO_IDR_ID2                        GPIO_IDR_ID2_Msk
14183 #define GPIO_IDR_ID3_Pos                    (3U)
14184 #define GPIO_IDR_ID3_Msk                    (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
14185 #define GPIO_IDR_ID3                        GPIO_IDR_ID3_Msk
14186 #define GPIO_IDR_ID4_Pos                    (4U)
14187 #define GPIO_IDR_ID4_Msk                    (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
14188 #define GPIO_IDR_ID4                        GPIO_IDR_ID4_Msk
14189 #define GPIO_IDR_ID5_Pos                    (5U)
14190 #define GPIO_IDR_ID5_Msk                    (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
14191 #define GPIO_IDR_ID5                        GPIO_IDR_ID5_Msk
14192 #define GPIO_IDR_ID6_Pos                    (6U)
14193 #define GPIO_IDR_ID6_Msk                    (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
14194 #define GPIO_IDR_ID6                        GPIO_IDR_ID6_Msk
14195 #define GPIO_IDR_ID7_Pos                    (7U)
14196 #define GPIO_IDR_ID7_Msk                    (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
14197 #define GPIO_IDR_ID7                        GPIO_IDR_ID7_Msk
14198 #define GPIO_IDR_ID8_Pos                    (8U)
14199 #define GPIO_IDR_ID8_Msk                    (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
14200 #define GPIO_IDR_ID8                        GPIO_IDR_ID8_Msk
14201 #define GPIO_IDR_ID9_Pos                    (9U)
14202 #define GPIO_IDR_ID9_Msk                    (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
14203 #define GPIO_IDR_ID9                        GPIO_IDR_ID9_Msk
14204 #define GPIO_IDR_ID10_Pos                   (10U)
14205 #define GPIO_IDR_ID10_Msk                   (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
14206 #define GPIO_IDR_ID10                       GPIO_IDR_ID10_Msk
14207 #define GPIO_IDR_ID11_Pos                   (11U)
14208 #define GPIO_IDR_ID11_Msk                   (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
14209 #define GPIO_IDR_ID11                       GPIO_IDR_ID11_Msk
14210 #define GPIO_IDR_ID12_Pos                   (12U)
14211 #define GPIO_IDR_ID12_Msk                   (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
14212 #define GPIO_IDR_ID12                       GPIO_IDR_ID12_Msk
14213 #define GPIO_IDR_ID13_Pos                   (13U)
14214 #define GPIO_IDR_ID13_Msk                   (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
14215 #define GPIO_IDR_ID13                       GPIO_IDR_ID13_Msk
14216 #define GPIO_IDR_ID14_Pos                   (14U)
14217 #define GPIO_IDR_ID14_Msk                   (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
14218 #define GPIO_IDR_ID14                       GPIO_IDR_ID14_Msk
14219 #define GPIO_IDR_ID15_Pos                   (15U)
14220 #define GPIO_IDR_ID15_Msk                   (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
14221 #define GPIO_IDR_ID15                       GPIO_IDR_ID15_Msk
14222 
14223 /******************  Bits definition for GPIO_ODR register  *******************/
14224 #define GPIO_ODR_OD0_Pos                    (0U)
14225 #define GPIO_ODR_OD0_Msk                    (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
14226 #define GPIO_ODR_OD0                        GPIO_ODR_OD0_Msk
14227 #define GPIO_ODR_OD1_Pos                    (1U)
14228 #define GPIO_ODR_OD1_Msk                    (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
14229 #define GPIO_ODR_OD1                        GPIO_ODR_OD1_Msk
14230 #define GPIO_ODR_OD2_Pos                    (2U)
14231 #define GPIO_ODR_OD2_Msk                    (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
14232 #define GPIO_ODR_OD2                        GPIO_ODR_OD2_Msk
14233 #define GPIO_ODR_OD3_Pos                    (3U)
14234 #define GPIO_ODR_OD3_Msk                    (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
14235 #define GPIO_ODR_OD3                        GPIO_ODR_OD3_Msk
14236 #define GPIO_ODR_OD4_Pos                    (4U)
14237 #define GPIO_ODR_OD4_Msk                    (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
14238 #define GPIO_ODR_OD4                        GPIO_ODR_OD4_Msk
14239 #define GPIO_ODR_OD5_Pos                    (5U)
14240 #define GPIO_ODR_OD5_Msk                    (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
14241 #define GPIO_ODR_OD5                        GPIO_ODR_OD5_Msk
14242 #define GPIO_ODR_OD6_Pos                    (6U)
14243 #define GPIO_ODR_OD6_Msk                    (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
14244 #define GPIO_ODR_OD6                        GPIO_ODR_OD6_Msk
14245 #define GPIO_ODR_OD7_Pos                    (7U)
14246 #define GPIO_ODR_OD7_Msk                    (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
14247 #define GPIO_ODR_OD7                        GPIO_ODR_OD7_Msk
14248 #define GPIO_ODR_OD8_Pos                    (8U)
14249 #define GPIO_ODR_OD8_Msk                    (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
14250 #define GPIO_ODR_OD8                        GPIO_ODR_OD8_Msk
14251 #define GPIO_ODR_OD9_Pos                    (9U)
14252 #define GPIO_ODR_OD9_Msk                    (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
14253 #define GPIO_ODR_OD9                        GPIO_ODR_OD9_Msk
14254 #define GPIO_ODR_OD10_Pos                   (10U)
14255 #define GPIO_ODR_OD10_Msk                   (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
14256 #define GPIO_ODR_OD10                       GPIO_ODR_OD10_Msk
14257 #define GPIO_ODR_OD11_Pos                   (11U)
14258 #define GPIO_ODR_OD11_Msk                   (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
14259 #define GPIO_ODR_OD11                       GPIO_ODR_OD11_Msk
14260 #define GPIO_ODR_OD12_Pos                   (12U)
14261 #define GPIO_ODR_OD12_Msk                   (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
14262 #define GPIO_ODR_OD12                       GPIO_ODR_OD12_Msk
14263 #define GPIO_ODR_OD13_Pos                   (13U)
14264 #define GPIO_ODR_OD13_Msk                   (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
14265 #define GPIO_ODR_OD13                       GPIO_ODR_OD13_Msk
14266 #define GPIO_ODR_OD14_Pos                   (14U)
14267 #define GPIO_ODR_OD14_Msk                   (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
14268 #define GPIO_ODR_OD14                       GPIO_ODR_OD14_Msk
14269 #define GPIO_ODR_OD15_Pos                   (15U)
14270 #define GPIO_ODR_OD15_Msk                   (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
14271 #define GPIO_ODR_OD15                       GPIO_ODR_OD15_Msk
14272 
14273 /******************  Bits definition for GPIO_BSRR register  ******************/
14274 #define GPIO_BSRR_BS0_Pos                   (0U)
14275 #define GPIO_BSRR_BS0_Msk                   (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
14276 #define GPIO_BSRR_BS0                       GPIO_BSRR_BS0_Msk
14277 #define GPIO_BSRR_BS1_Pos                   (1U)
14278 #define GPIO_BSRR_BS1_Msk                   (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
14279 #define GPIO_BSRR_BS1                       GPIO_BSRR_BS1_Msk
14280 #define GPIO_BSRR_BS2_Pos                   (2U)
14281 #define GPIO_BSRR_BS2_Msk                   (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
14282 #define GPIO_BSRR_BS2                       GPIO_BSRR_BS2_Msk
14283 #define GPIO_BSRR_BS3_Pos                   (3U)
14284 #define GPIO_BSRR_BS3_Msk                   (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
14285 #define GPIO_BSRR_BS3                       GPIO_BSRR_BS3_Msk
14286 #define GPIO_BSRR_BS4_Pos                   (4U)
14287 #define GPIO_BSRR_BS4_Msk                   (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
14288 #define GPIO_BSRR_BS4                       GPIO_BSRR_BS4_Msk
14289 #define GPIO_BSRR_BS5_Pos                   (5U)
14290 #define GPIO_BSRR_BS5_Msk                   (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
14291 #define GPIO_BSRR_BS5                       GPIO_BSRR_BS5_Msk
14292 #define GPIO_BSRR_BS6_Pos                   (6U)
14293 #define GPIO_BSRR_BS6_Msk                   (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
14294 #define GPIO_BSRR_BS6                       GPIO_BSRR_BS6_Msk
14295 #define GPIO_BSRR_BS7_Pos                   (7U)
14296 #define GPIO_BSRR_BS7_Msk                   (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
14297 #define GPIO_BSRR_BS7                       GPIO_BSRR_BS7_Msk
14298 #define GPIO_BSRR_BS8_Pos                   (8U)
14299 #define GPIO_BSRR_BS8_Msk                   (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
14300 #define GPIO_BSRR_BS8                       GPIO_BSRR_BS8_Msk
14301 #define GPIO_BSRR_BS9_Pos                   (9U)
14302 #define GPIO_BSRR_BS9_Msk                   (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
14303 #define GPIO_BSRR_BS9                       GPIO_BSRR_BS9_Msk
14304 #define GPIO_BSRR_BS10_Pos                  (10U)
14305 #define GPIO_BSRR_BS10_Msk                  (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
14306 #define GPIO_BSRR_BS10                      GPIO_BSRR_BS10_Msk
14307 #define GPIO_BSRR_BS11_Pos                  (11U)
14308 #define GPIO_BSRR_BS11_Msk                  (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
14309 #define GPIO_BSRR_BS11                      GPIO_BSRR_BS11_Msk
14310 #define GPIO_BSRR_BS12_Pos                  (12U)
14311 #define GPIO_BSRR_BS12_Msk                  (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
14312 #define GPIO_BSRR_BS12                      GPIO_BSRR_BS12_Msk
14313 #define GPIO_BSRR_BS13_Pos                  (13U)
14314 #define GPIO_BSRR_BS13_Msk                  (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
14315 #define GPIO_BSRR_BS13                      GPIO_BSRR_BS13_Msk
14316 #define GPIO_BSRR_BS14_Pos                  (14U)
14317 #define GPIO_BSRR_BS14_Msk                  (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
14318 #define GPIO_BSRR_BS14                      GPIO_BSRR_BS14_Msk
14319 #define GPIO_BSRR_BS15_Pos                  (15U)
14320 #define GPIO_BSRR_BS15_Msk                  (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
14321 #define GPIO_BSRR_BS15                      GPIO_BSRR_BS15_Msk
14322 #define GPIO_BSRR_BR0_Pos                   (16U)
14323 #define GPIO_BSRR_BR0_Msk                   (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
14324 #define GPIO_BSRR_BR0                       GPIO_BSRR_BR0_Msk
14325 #define GPIO_BSRR_BR1_Pos                   (17U)
14326 #define GPIO_BSRR_BR1_Msk                   (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
14327 #define GPIO_BSRR_BR1                       GPIO_BSRR_BR1_Msk
14328 #define GPIO_BSRR_BR2_Pos                   (18U)
14329 #define GPIO_BSRR_BR2_Msk                   (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
14330 #define GPIO_BSRR_BR2                       GPIO_BSRR_BR2_Msk
14331 #define GPIO_BSRR_BR3_Pos                   (19U)
14332 #define GPIO_BSRR_BR3_Msk                   (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
14333 #define GPIO_BSRR_BR3                       GPIO_BSRR_BR3_Msk
14334 #define GPIO_BSRR_BR4_Pos                   (20U)
14335 #define GPIO_BSRR_BR4_Msk                   (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
14336 #define GPIO_BSRR_BR4                       GPIO_BSRR_BR4_Msk
14337 #define GPIO_BSRR_BR5_Pos                   (21U)
14338 #define GPIO_BSRR_BR5_Msk                   (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
14339 #define GPIO_BSRR_BR5                       GPIO_BSRR_BR5_Msk
14340 #define GPIO_BSRR_BR6_Pos                   (22U)
14341 #define GPIO_BSRR_BR6_Msk                   (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
14342 #define GPIO_BSRR_BR6                       GPIO_BSRR_BR6_Msk
14343 #define GPIO_BSRR_BR7_Pos                   (23U)
14344 #define GPIO_BSRR_BR7_Msk                   (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
14345 #define GPIO_BSRR_BR7                       GPIO_BSRR_BR7_Msk
14346 #define GPIO_BSRR_BR8_Pos                   (24U)
14347 #define GPIO_BSRR_BR8_Msk                   (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
14348 #define GPIO_BSRR_BR8                       GPIO_BSRR_BR8_Msk
14349 #define GPIO_BSRR_BR9_Pos                   (25U)
14350 #define GPIO_BSRR_BR9_Msk                   (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
14351 #define GPIO_BSRR_BR9                       GPIO_BSRR_BR9_Msk
14352 #define GPIO_BSRR_BR10_Pos                  (26U)
14353 #define GPIO_BSRR_BR10_Msk                  (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
14354 #define GPIO_BSRR_BR10                      GPIO_BSRR_BR10_Msk
14355 #define GPIO_BSRR_BR11_Pos                  (27U)
14356 #define GPIO_BSRR_BR11_Msk                  (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
14357 #define GPIO_BSRR_BR11                      GPIO_BSRR_BR11_Msk
14358 #define GPIO_BSRR_BR12_Pos                  (28U)
14359 #define GPIO_BSRR_BR12_Msk                  (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
14360 #define GPIO_BSRR_BR12                      GPIO_BSRR_BR12_Msk
14361 #define GPIO_BSRR_BR13_Pos                  (29U)
14362 #define GPIO_BSRR_BR13_Msk                  (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
14363 #define GPIO_BSRR_BR13                      GPIO_BSRR_BR13_Msk
14364 #define GPIO_BSRR_BR14_Pos                  (30U)
14365 #define GPIO_BSRR_BR14_Msk                  (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
14366 #define GPIO_BSRR_BR14                      GPIO_BSRR_BR14_Msk
14367 #define GPIO_BSRR_BR15_Pos                  (31U)
14368 #define GPIO_BSRR_BR15_Msk                  (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
14369 #define GPIO_BSRR_BR15                      GPIO_BSRR_BR15_Msk
14370 
14371 /****************** Bit definition for GPIO_LCKR register *********************/
14372 #define GPIO_LCKR_LCK0_Pos                  (0U)
14373 #define GPIO_LCKR_LCK0_Msk                  (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
14374 #define GPIO_LCKR_LCK0                      GPIO_LCKR_LCK0_Msk
14375 #define GPIO_LCKR_LCK1_Pos                  (1U)
14376 #define GPIO_LCKR_LCK1_Msk                  (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
14377 #define GPIO_LCKR_LCK1                      GPIO_LCKR_LCK1_Msk
14378 #define GPIO_LCKR_LCK2_Pos                  (2U)
14379 #define GPIO_LCKR_LCK2_Msk                  (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
14380 #define GPIO_LCKR_LCK2                      GPIO_LCKR_LCK2_Msk
14381 #define GPIO_LCKR_LCK3_Pos                  (3U)
14382 #define GPIO_LCKR_LCK3_Msk                  (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
14383 #define GPIO_LCKR_LCK3                      GPIO_LCKR_LCK3_Msk
14384 #define GPIO_LCKR_LCK4_Pos                  (4U)
14385 #define GPIO_LCKR_LCK4_Msk                  (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
14386 #define GPIO_LCKR_LCK4                      GPIO_LCKR_LCK4_Msk
14387 #define GPIO_LCKR_LCK5_Pos                  (5U)
14388 #define GPIO_LCKR_LCK5_Msk                  (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
14389 #define GPIO_LCKR_LCK5                      GPIO_LCKR_LCK5_Msk
14390 #define GPIO_LCKR_LCK6_Pos                  (6U)
14391 #define GPIO_LCKR_LCK6_Msk                  (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
14392 #define GPIO_LCKR_LCK6                      GPIO_LCKR_LCK6_Msk
14393 #define GPIO_LCKR_LCK7_Pos                  (7U)
14394 #define GPIO_LCKR_LCK7_Msk                  (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
14395 #define GPIO_LCKR_LCK7                      GPIO_LCKR_LCK7_Msk
14396 #define GPIO_LCKR_LCK8_Pos                  (8U)
14397 #define GPIO_LCKR_LCK8_Msk                  (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
14398 #define GPIO_LCKR_LCK8                      GPIO_LCKR_LCK8_Msk
14399 #define GPIO_LCKR_LCK9_Pos                  (9U)
14400 #define GPIO_LCKR_LCK9_Msk                  (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
14401 #define GPIO_LCKR_LCK9                      GPIO_LCKR_LCK9_Msk
14402 #define GPIO_LCKR_LCK10_Pos                 (10U)
14403 #define GPIO_LCKR_LCK10_Msk                 (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
14404 #define GPIO_LCKR_LCK10                     GPIO_LCKR_LCK10_Msk
14405 #define GPIO_LCKR_LCK11_Pos                 (11U)
14406 #define GPIO_LCKR_LCK11_Msk                 (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
14407 #define GPIO_LCKR_LCK11                     GPIO_LCKR_LCK11_Msk
14408 #define GPIO_LCKR_LCK12_Pos                 (12U)
14409 #define GPIO_LCKR_LCK12_Msk                 (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
14410 #define GPIO_LCKR_LCK12                     GPIO_LCKR_LCK12_Msk
14411 #define GPIO_LCKR_LCK13_Pos                 (13U)
14412 #define GPIO_LCKR_LCK13_Msk                 (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
14413 #define GPIO_LCKR_LCK13                     GPIO_LCKR_LCK13_Msk
14414 #define GPIO_LCKR_LCK14_Pos                 (14U)
14415 #define GPIO_LCKR_LCK14_Msk                 (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
14416 #define GPIO_LCKR_LCK14                     GPIO_LCKR_LCK14_Msk
14417 #define GPIO_LCKR_LCK15_Pos                 (15U)
14418 #define GPIO_LCKR_LCK15_Msk                 (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
14419 #define GPIO_LCKR_LCK15                     GPIO_LCKR_LCK15_Msk
14420 #define GPIO_LCKR_LCKK_Pos                  (16U)
14421 #define GPIO_LCKR_LCKK_Msk                  (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
14422 #define GPIO_LCKR_LCKK                      GPIO_LCKR_LCKK_Msk
14423 
14424 /****************** Bit definition for GPIO_AFRL register *********************/
14425 #define GPIO_AFRL_AFSEL0_Pos                (0U)
14426 #define GPIO_AFRL_AFSEL0_Msk                (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
14427 #define GPIO_AFRL_AFSEL0                    GPIO_AFRL_AFSEL0_Msk
14428 #define GPIO_AFRL_AFSEL0_0                  (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
14429 #define GPIO_AFRL_AFSEL0_1                  (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
14430 #define GPIO_AFRL_AFSEL0_2                  (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
14431 #define GPIO_AFRL_AFSEL0_3                  (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
14432 #define GPIO_AFRL_AFSEL1_Pos                (4U)
14433 #define GPIO_AFRL_AFSEL1_Msk                (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
14434 #define GPIO_AFRL_AFSEL1                    GPIO_AFRL_AFSEL1_Msk
14435 #define GPIO_AFRL_AFSEL1_0                  (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
14436 #define GPIO_AFRL_AFSEL1_1                  (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
14437 #define GPIO_AFRL_AFSEL1_2                  (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
14438 #define GPIO_AFRL_AFSEL1_3                  (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
14439 #define GPIO_AFRL_AFSEL2_Pos                (8U)
14440 #define GPIO_AFRL_AFSEL2_Msk                (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
14441 #define GPIO_AFRL_AFSEL2                    GPIO_AFRL_AFSEL2_Msk
14442 #define GPIO_AFRL_AFSEL2_0                  (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
14443 #define GPIO_AFRL_AFSEL2_1                  (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
14444 #define GPIO_AFRL_AFSEL2_2                  (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
14445 #define GPIO_AFRL_AFSEL2_3                  (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
14446 #define GPIO_AFRL_AFSEL3_Pos                (12U)
14447 #define GPIO_AFRL_AFSEL3_Msk                (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
14448 #define GPIO_AFRL_AFSEL3                    GPIO_AFRL_AFSEL3_Msk
14449 #define GPIO_AFRL_AFSEL3_0                  (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
14450 #define GPIO_AFRL_AFSEL3_1                  (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
14451 #define GPIO_AFRL_AFSEL3_2                  (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
14452 #define GPIO_AFRL_AFSEL3_3                  (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
14453 #define GPIO_AFRL_AFSEL4_Pos                (16U)
14454 #define GPIO_AFRL_AFSEL4_Msk                (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
14455 #define GPIO_AFRL_AFSEL4                    GPIO_AFRL_AFSEL4_Msk
14456 #define GPIO_AFRL_AFSEL4_0                  (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
14457 #define GPIO_AFRL_AFSEL4_1                  (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
14458 #define GPIO_AFRL_AFSEL4_2                  (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
14459 #define GPIO_AFRL_AFSEL4_3                  (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
14460 #define GPIO_AFRL_AFSEL5_Pos                (20U)
14461 #define GPIO_AFRL_AFSEL5_Msk                (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
14462 #define GPIO_AFRL_AFSEL5                    GPIO_AFRL_AFSEL5_Msk
14463 #define GPIO_AFRL_AFSEL5_0                  (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
14464 #define GPIO_AFRL_AFSEL5_1                  (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
14465 #define GPIO_AFRL_AFSEL5_2                  (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
14466 #define GPIO_AFRL_AFSEL5_3                  (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
14467 #define GPIO_AFRL_AFSEL6_Pos                (24U)
14468 #define GPIO_AFRL_AFSEL6_Msk                (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
14469 #define GPIO_AFRL_AFSEL6                    GPIO_AFRL_AFSEL6_Msk
14470 #define GPIO_AFRL_AFSEL6_0                  (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
14471 #define GPIO_AFRL_AFSEL6_1                  (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
14472 #define GPIO_AFRL_AFSEL6_2                  (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
14473 #define GPIO_AFRL_AFSEL6_3                  (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
14474 #define GPIO_AFRL_AFSEL7_Pos                (28U)
14475 #define GPIO_AFRL_AFSEL7_Msk                (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
14476 #define GPIO_AFRL_AFSEL7                    GPIO_AFRL_AFSEL7_Msk
14477 #define GPIO_AFRL_AFSEL7_0                  (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
14478 #define GPIO_AFRL_AFSEL7_1                  (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
14479 #define GPIO_AFRL_AFSEL7_2                  (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
14480 #define GPIO_AFRL_AFSEL7_3                  (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
14481 
14482 /****************** Bit definition for GPIO_AFRH register *********************/
14483 #define GPIO_AFRH_AFSEL8_Pos                (0U)
14484 #define GPIO_AFRH_AFSEL8_Msk                (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
14485 #define GPIO_AFRH_AFSEL8                    GPIO_AFRH_AFSEL8_Msk
14486 #define GPIO_AFRH_AFSEL8_0                  (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
14487 #define GPIO_AFRH_AFSEL8_1                  (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
14488 #define GPIO_AFRH_AFSEL8_2                  (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
14489 #define GPIO_AFRH_AFSEL8_3                  (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
14490 #define GPIO_AFRH_AFSEL9_Pos                (4U)
14491 #define GPIO_AFRH_AFSEL9_Msk                (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
14492 #define GPIO_AFRH_AFSEL9                    GPIO_AFRH_AFSEL9_Msk
14493 #define GPIO_AFRH_AFSEL9_0                  (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
14494 #define GPIO_AFRH_AFSEL9_1                  (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
14495 #define GPIO_AFRH_AFSEL9_2                  (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
14496 #define GPIO_AFRH_AFSEL9_3                  (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
14497 #define GPIO_AFRH_AFSEL10_Pos               (8U)
14498 #define GPIO_AFRH_AFSEL10_Msk               (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
14499 #define GPIO_AFRH_AFSEL10                   GPIO_AFRH_AFSEL10_Msk
14500 #define GPIO_AFRH_AFSEL10_0                 (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
14501 #define GPIO_AFRH_AFSEL10_1                 (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
14502 #define GPIO_AFRH_AFSEL10_2                 (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
14503 #define GPIO_AFRH_AFSEL10_3                 (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
14504 #define GPIO_AFRH_AFSEL11_Pos               (12U)
14505 #define GPIO_AFRH_AFSEL11_Msk               (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
14506 #define GPIO_AFRH_AFSEL11                   GPIO_AFRH_AFSEL11_Msk
14507 #define GPIO_AFRH_AFSEL11_0                 (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
14508 #define GPIO_AFRH_AFSEL11_1                 (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
14509 #define GPIO_AFRH_AFSEL11_2                 (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
14510 #define GPIO_AFRH_AFSEL11_3                 (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
14511 #define GPIO_AFRH_AFSEL12_Pos               (16U)
14512 #define GPIO_AFRH_AFSEL12_Msk               (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
14513 #define GPIO_AFRH_AFSEL12                   GPIO_AFRH_AFSEL12_Msk
14514 #define GPIO_AFRH_AFSEL12_0                 (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
14515 #define GPIO_AFRH_AFSEL12_1                 (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
14516 #define GPIO_AFRH_AFSEL12_2                 (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
14517 #define GPIO_AFRH_AFSEL12_3                 (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
14518 #define GPIO_AFRH_AFSEL13_Pos               (20U)
14519 #define GPIO_AFRH_AFSEL13_Msk               (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
14520 #define GPIO_AFRH_AFSEL13                   GPIO_AFRH_AFSEL13_Msk
14521 #define GPIO_AFRH_AFSEL13_0                 (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
14522 #define GPIO_AFRH_AFSEL13_1                 (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
14523 #define GPIO_AFRH_AFSEL13_2                 (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
14524 #define GPIO_AFRH_AFSEL13_3                 (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
14525 #define GPIO_AFRH_AFSEL14_Pos               (24U)
14526 #define GPIO_AFRH_AFSEL14_Msk               (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
14527 #define GPIO_AFRH_AFSEL14                   GPIO_AFRH_AFSEL14_Msk
14528 #define GPIO_AFRH_AFSEL14_0                 (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
14529 #define GPIO_AFRH_AFSEL14_1                 (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
14530 #define GPIO_AFRH_AFSEL14_2                 (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
14531 #define GPIO_AFRH_AFSEL14_3                 (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
14532 #define GPIO_AFRH_AFSEL15_Pos               (28U)
14533 #define GPIO_AFRH_AFSEL15_Msk               (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
14534 #define GPIO_AFRH_AFSEL15                   GPIO_AFRH_AFSEL15_Msk
14535 #define GPIO_AFRH_AFSEL15_0                 (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
14536 #define GPIO_AFRH_AFSEL15_1                 (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
14537 #define GPIO_AFRH_AFSEL15_2                 (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
14538 #define GPIO_AFRH_AFSEL15_3                 (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
14539 
14540 /******************  Bits definition for GPIO_BRR register  ******************/
14541 #define GPIO_BRR_BR0_Pos                    (0U)
14542 #define GPIO_BRR_BR0_Msk                    (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
14543 #define GPIO_BRR_BR0                        GPIO_BRR_BR0_Msk
14544 #define GPIO_BRR_BR1_Pos                    (1U)
14545 #define GPIO_BRR_BR1_Msk                    (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
14546 #define GPIO_BRR_BR1                        GPIO_BRR_BR1_Msk
14547 #define GPIO_BRR_BR2_Pos                    (2U)
14548 #define GPIO_BRR_BR2_Msk                    (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
14549 #define GPIO_BRR_BR2                        GPIO_BRR_BR2_Msk
14550 #define GPIO_BRR_BR3_Pos                    (3U)
14551 #define GPIO_BRR_BR3_Msk                    (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
14552 #define GPIO_BRR_BR3                        GPIO_BRR_BR3_Msk
14553 #define GPIO_BRR_BR4_Pos                    (4U)
14554 #define GPIO_BRR_BR4_Msk                    (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
14555 #define GPIO_BRR_BR4                        GPIO_BRR_BR4_Msk
14556 #define GPIO_BRR_BR5_Pos                    (5U)
14557 #define GPIO_BRR_BR5_Msk                    (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
14558 #define GPIO_BRR_BR5                        GPIO_BRR_BR5_Msk
14559 #define GPIO_BRR_BR6_Pos                    (6U)
14560 #define GPIO_BRR_BR6_Msk                    (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
14561 #define GPIO_BRR_BR6                        GPIO_BRR_BR6_Msk
14562 #define GPIO_BRR_BR7_Pos                    (7U)
14563 #define GPIO_BRR_BR7_Msk                    (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
14564 #define GPIO_BRR_BR7                        GPIO_BRR_BR7_Msk
14565 #define GPIO_BRR_BR8_Pos                    (8U)
14566 #define GPIO_BRR_BR8_Msk                    (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
14567 #define GPIO_BRR_BR8                        GPIO_BRR_BR8_Msk
14568 #define GPIO_BRR_BR9_Pos                    (9U)
14569 #define GPIO_BRR_BR9_Msk                    (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
14570 #define GPIO_BRR_BR9                        GPIO_BRR_BR9_Msk
14571 #define GPIO_BRR_BR10_Pos                   (10U)
14572 #define GPIO_BRR_BR10_Msk                   (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
14573 #define GPIO_BRR_BR10                       GPIO_BRR_BR10_Msk
14574 #define GPIO_BRR_BR11_Pos                   (11U)
14575 #define GPIO_BRR_BR11_Msk                   (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
14576 #define GPIO_BRR_BR11                       GPIO_BRR_BR11_Msk
14577 #define GPIO_BRR_BR12_Pos                   (12U)
14578 #define GPIO_BRR_BR12_Msk                   (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
14579 #define GPIO_BRR_BR12                       GPIO_BRR_BR12_Msk
14580 #define GPIO_BRR_BR13_Pos                   (13U)
14581 #define GPIO_BRR_BR13_Msk                   (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
14582 #define GPIO_BRR_BR13                       GPIO_BRR_BR13_Msk
14583 #define GPIO_BRR_BR14_Pos                   (14U)
14584 #define GPIO_BRR_BR14_Msk                   (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
14585 #define GPIO_BRR_BR14                       GPIO_BRR_BR14_Msk
14586 #define GPIO_BRR_BR15_Pos                   (15U)
14587 #define GPIO_BRR_BR15_Msk                   (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
14588 #define GPIO_BRR_BR15                       GPIO_BRR_BR15_Msk
14589 
14590 /******************  Bits definition for GPIO_HSLVR register  ******************/
14591 #define GPIO_HSLVR_HSLV0_Pos                (0U)
14592 #define GPIO_HSLVR_HSLV0_Msk                (0x1UL << GPIO_HSLVR_HSLV0_Pos)         /*!< 0x00000001 */
14593 #define GPIO_HSLVR_HSLV0                    GPIO_HSLVR_HSLV0_Msk
14594 #define GPIO_HSLVR_HSLV1_Pos                (1U)
14595 #define GPIO_HSLVR_HSLV1_Msk                (0x1UL << GPIO_HSLVR_HSLV1_Pos)         /*!< 0x00000002 */
14596 #define GPIO_HSLVR_HSLV1                    GPIO_HSLVR_HSLV1_Msk
14597 #define GPIO_HSLVR_HSLV2_Pos                (2U)
14598 #define GPIO_HSLVR_HSLV2_Msk                (0x1UL << GPIO_HSLVR_HSLV2_Pos)         /*!< 0x00000004 */
14599 #define GPIO_HSLVR_HSLV2                    GPIO_HSLVR_HSLV2_Msk
14600 #define GPIO_HSLVR_HSLV3_Pos                (3U)
14601 #define GPIO_HSLVR_HSLV3_Msk                (0x1UL << GPIO_HSLVR_HSLV3_Pos)         /*!< 0x00000008 */
14602 #define GPIO_HSLVR_HSLV3                    GPIO_HSLVR_HSLV3_Msk
14603 #define GPIO_HSLVR_HSLV4_Pos                (4U)
14604 #define GPIO_HSLVR_HSLV4_Msk                (0x1UL << GPIO_HSLVR_HSLV4_Pos)         /*!< 0x00000010 */
14605 #define GPIO_HSLVR_HSLV4                    GPIO_HSLVR_HSLV4_Msk
14606 #define GPIO_HSLVR_HSLV5_Pos                (5U)
14607 #define GPIO_HSLVR_HSLV5_Msk                (0x1UL << GPIO_HSLVR_HSLV5_Pos)         /*!< 0x00000020 */
14608 #define GPIO_HSLVR_HSLV5                    GPIO_HSLVR_HSLV5_Msk
14609 #define GPIO_HSLVR_HSLV6_Pos                (6U)
14610 #define GPIO_HSLVR_HSLV6_Msk                (0x1UL << GPIO_HSLVR_HSLV6_Pos)         /*!< 0x00000040 */
14611 #define GPIO_HSLVR_HSLV6                    GPIO_HSLVR_HSLV6_Msk
14612 #define GPIO_HSLVR_HSLV7_Pos                (7U)
14613 #define GPIO_HSLVR_HSLV7_Msk                (0x1UL << GPIO_HSLVR_HSLV7_Pos)         /*!< 0x00000080 */
14614 #define GPIO_HSLVR_HSLV7                    GPIO_HSLVR_HSLV7_Msk
14615 #define GPIO_HSLVR_HSLV8_Pos                (8U)
14616 #define GPIO_HSLVR_HSLV8_Msk                (0x1UL << GPIO_HSLVR_HSLV8_Pos)         /*!< 0x00000100 */
14617 #define GPIO_HSLVR_HSLV8                    GPIO_HSLVR_HSLV8_Msk
14618 #define GPIO_HSLVR_HSLV9_Pos                (9U)
14619 #define GPIO_HSLVR_HSLV9_Msk                (0x1UL << GPIO_HSLVR_HSLV9_Pos)         /*!< 0x00000200 */
14620 #define GPIO_HSLVR_HSLV9                    GPIO_HSLVR_HSLV9_Msk
14621 #define GPIO_HSLVR_HSLV10_Pos               (10U)
14622 #define GPIO_HSLVR_HSLV10_Msk               (0x1UL << GPIO_HSLVR_HSLV10_Pos)        /*!< 0x00000400 */
14623 #define GPIO_HSLVR_HSLV10                   GPIO_HSLVR_HSLV10_Msk
14624 #define GPIO_HSLVR_HSLV11_Pos               (11U)
14625 #define GPIO_HSLVR_HSLV11_Msk               (x1UL << GPIO_HSLVR_HSLV11_Pos)         /*!< 0x00000800 */
14626 #define GPIO_HSLVR_HSLV11                   GPIO_HSLVR_HSLV11_Msk
14627 #define GPIO_HSLVR_HSLV12_Pos               (12U)
14628 #define GPIO_HSLVR_HSLV12_Msk               (0x1UL << GPIO_HSLVR_HSLV12_Pos)        /*!< 0x00001000 */
14629 #define GPIO_HSLVR_HSLV12                   GPIO_HSLVR_HSLV12_Msk
14630 #define GPIO_HSLVR_HSLV13_Pos               (13U)
14631 #define GPIO_HSLVR_HSLV13_Msk               (0x1UL << GPIO_HSLVR_HSLV13_Pos)        /*!< 0x00002000 */
14632 #define GPIO_HSLVR_HSLV13                   GPIO_HSLVR_HSLV13_Msk
14633 #define GPIO_HSLVR_HSLV14_Pos               (14U)
14634 #define GPIO_HSLVR_HSLV14_Msk               (0x1UL << GPIO_HSLVR_HSLV14_Pos)        /*!< 0x00004000 */
14635 #define GPIO_HSLVR_HSLV14                   GPIO_HSLVR_HSLV14_Msk
14636 #define GPIO_HSLVR_HSLV15_Pos               (15U)
14637 #define GPIO_HSLVR_HSLV15_Msk               (0x1UL << GPIO_HSLVR_HSLV15_Pos)        /*!< 0x00008000 */
14638 #define GPIO_HSLVR_HSLV15                   GPIO_HSLVR_HSLV15_Msk
14639 
14640 /******************  Bits definition for GPIO_SECCFGR register  ******************/
14641 #define GPIO_SECCFGR_SEC0_Pos               (0U)
14642 #define GPIO_SECCFGR_SEC0_Msk               (0x1UL << GPIO_SECCFGR_SEC0_Pos)        /*!< 0x00000001 */
14643 #define GPIO_SECCFGR_SEC0                   GPIO_SECCFGR_SEC0_Msk
14644 #define GPIO_SECCFGR_SEC1_Pos               (1U)
14645 #define GPIO_SECCFGR_SEC1_Msk               (0x1UL << GPIO_SECCFGR_SEC1_Pos)        /*!< 0x00000002 */
14646 #define GPIO_SECCFGR_SEC1                   GPIO_SECCFGR_SEC1_Msk
14647 #define GPIO_SECCFGR_SEC2_Pos               (2U)
14648 #define GPIO_SECCFGR_SEC2_Msk               (0x1UL << GPIO_SECCFGR_SEC2_Pos)        /*!< 0x00000004 */
14649 #define GPIO_SECCFGR_SEC2                   GPIO_SECCFGR_SEC2_Msk
14650 #define GPIO_SECCFGR_SEC3_Pos               (3U)
14651 #define GPIO_SECCFGR_SEC3_Msk               (0x1UL << GPIO_SECCFGR_SEC3_Pos)        /*!< 0x00000008 */
14652 #define GPIO_SECCFGR_SEC3                   GPIO_SECCFGR_SEC3_Msk
14653 #define GPIO_SECCFGR_SEC4_Pos               (4U)
14654 #define GPIO_SECCFGR_SEC4_Msk               (0x1UL << GPIO_SECCFGR_SEC4_Pos)        /*!< 0x00000010 */
14655 #define GPIO_SECCFGR_SEC4                   GPIO_SECCFGR_SEC4_Msk
14656 #define GPIO_SECCFGR_SEC5_Pos               (5U)
14657 #define GPIO_SECCFGR_SEC5_Msk               (0x1UL << GPIO_SECCFGR_SEC5_Pos)        /*!< 0x00000020 */
14658 #define GPIO_SECCFGR_SEC5                   GPIO_SECCFGR_SEC5_Msk
14659 #define GPIO_SECCFGR_SEC6_Pos               (6U)
14660 #define GPIO_SECCFGR_SEC6_Msk               (0x1UL << GPIO_SECCFGR_SEC6_Pos)        /*!< 0x00000040 */
14661 #define GPIO_SECCFGR_SEC6                   GPIO_SECCFGR_SEC6_Msk
14662 #define GPIO_SECCFGR_SEC7_Pos               (7U)
14663 #define GPIO_SECCFGR_SEC7_Msk               (0x1UL << GPIO_SECCFGR_SEC7_Pos)        /*!< 0x00000080 */
14664 #define GPIO_SECCFGR_SEC7                   GPIO_SECCFGR_SEC7_Msk
14665 #define GPIO_SECCFGR_SEC8_Pos               (8U)
14666 #define GPIO_SECCFGR_SEC8_Msk               (0x1UL << GPIO_SECCFGR_SEC8_Pos)        /*!< 0x00000100 */
14667 #define GPIO_SECCFGR_SEC8                   GPIO_SECCFGR_SEC8_Msk
14668 #define GPIO_SECCFGR_SEC9_Pos               (9U)
14669 #define GPIO_SECCFGR_SEC9_Msk               (0x1UL << GPIO_SECCFGR_SEC9_Pos)        /*!< 0x00000200 */
14670 #define GPIO_SECCFGR_SEC9                   GPIO_SECCFGR_SEC9_Msk
14671 #define GPIO_SECCFGR_SEC10_Pos              (10U)
14672 #define GPIO_SECCFGR_SEC10_Msk              (0x1UL << GPIO_SECCFGR_SEC10_Pos)       /*!< 0x00000400 */
14673 #define GPIO_SECCFGR_SEC10                  GPIO_SECCFGR_SEC10_Msk
14674 #define GPIO_SECCFGR_SEC11_Pos              (11U)
14675 #define GPIO_SECCFGR_SEC11_Msk              (x1UL << GPIO_SECCFGR_SEC11_Pos)        /*!< 0x00000800 */
14676 #define GPIO_SECCFGR_SEC11                  GPIO_SECCFGR_SEC11_Msk
14677 #define GPIO_SECCFGR_SEC12_Pos              (12U)
14678 #define GPIO_SECCFGR_SEC12_Msk              (0x1UL << GPIO_SECCFGR_SEC12_Pos)       /*!< 0x00001000 */
14679 #define GPIO_SECCFGR_SEC12                  GPIO_SECCFGR_SEC12_Msk
14680 #define GPIO_SECCFGR_SEC13_Pos              (13U)
14681 #define GPIO_SECCFGR_SEC13_Msk              (0x1UL << GPIO_SECCFGR_SEC13_Pos)       /*!< 0x00002000 */
14682 #define GPIO_SECCFGR_SEC13                  GPIO_SECCFGR_SEC13_Msk
14683 #define GPIO_SECCFGR_SEC14_Pos              (14U)
14684 #define GPIO_SECCFGR_SEC14_Msk              (0x1UL << GPIO_SECCFGR_SEC14_Pos)       /*!< 0x00004000 */
14685 #define GPIO_SECCFGR_SEC14                  GPIO_SECCFGR_SEC14_Msk
14686 #define GPIO_SECCFGR_SEC15_Pos              (15U)
14687 #define GPIO_SECCFGR_SEC15_Msk              (0x1UL << GPIO_SECCFGR_SEC15_Pos)       /*!< 0x00008000 */
14688 #define GPIO_SECCFGR_SEC15                  GPIO_SECCFGR_SEC15_Msk
14689 
14690 /******************************************************************************/
14691 /*                                                                            */
14692 /*                        JPEG Encoder/Decoder                                */
14693 /*                                                                            */
14694 /******************************************************************************/
14695 /********************  Bit definition for CONFR0 register  ********************/
14696 #define JPEG_CONFR0_START_Pos           (0U)
14697 #define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */
14698 #define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */
14699 
14700 /********************  Bit definition for CONFR1 register  ********************/
14701 #define JPEG_CONFR1_NF_Pos              (0U)
14702 #define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */
14703 #define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */
14704 #define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */
14705 #define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */
14706 #define JPEG_CONFR1_DE_Pos              (3U)
14707 #define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */
14708 #define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */
14709 #define JPEG_CONFR1_COLORSPACE_Pos      (4U)
14710 #define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */
14711 #define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */
14712 #define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */
14713 #define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */
14714 #define JPEG_CONFR1_NS_Pos              (6U)
14715 #define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */
14716 #define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */
14717 #define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */
14718 #define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */
14719 #define JPEG_CONFR1_HDR_Pos             (8U)
14720 #define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */
14721 #define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */
14722 #define JPEG_CONFR1_YSIZE_Pos           (16U)
14723 #define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */
14724 #define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */
14725 
14726 /********************  Bit definition for CONFR2 register  ********************/
14727 #define JPEG_CONFR2_NMCU_Pos            (0U)
14728 #define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */
14729 #define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */
14730 
14731 /********************  Bit definition for CONFR3 register  ********************/
14732 #define JPEG_CONFR3_XSIZE_Pos           (16U)
14733 #define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */
14734 #define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */
14735 
14736 /********************  Bit definition for CONFR4 register  ********************/
14737 #define JPEG_CONFR4_HD_Pos              (0U)
14738 #define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */
14739 #define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
14740 #define JPEG_CONFR4_HA_Pos              (1U)
14741 #define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */
14742 #define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
14743 #define JPEG_CONFR4_QT_Pos              (2U)
14744 #define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */
14745 #define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */
14746 #define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */
14747 #define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */
14748 #define JPEG_CONFR4_NB_Pos              (4U)
14749 #define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */
14750 #define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
14751 #define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */
14752 #define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */
14753 #define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */
14754 #define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */
14755 #define JPEG_CONFR4_VSF_Pos             (8U)
14756 #define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */
14757 #define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */
14758 #define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */
14759 #define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */
14760 #define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */
14761 #define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */
14762 #define JPEG_CONFR4_HSF_Pos             (12U)
14763 #define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */
14764 #define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */
14765 #define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */
14766 #define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */
14767 #define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */
14768 #define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */
14769 
14770 /********************  Bit definition for CONFR5 register  ********************/
14771 #define JPEG_CONFR5_HD_Pos              (0U)
14772 #define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */
14773 #define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
14774 #define JPEG_CONFR5_HA_Pos              (1U)
14775 #define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */
14776 #define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
14777 #define JPEG_CONFR5_QT_Pos              (2U)
14778 #define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */
14779 #define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */
14780 #define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */
14781 #define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */
14782 #define JPEG_CONFR5_NB_Pos              (4U)
14783 #define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */
14784 #define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
14785 #define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */
14786 #define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */
14787 #define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */
14788 #define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */
14789 #define JPEG_CONFR5_VSF_Pos             (8U)
14790 #define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */
14791 #define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
14792 #define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */
14793 #define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */
14794 #define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */
14795 #define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */
14796 #define JPEG_CONFR5_HSF_Pos             (12U)
14797 #define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */
14798 #define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
14799 #define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */
14800 #define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */
14801 #define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */
14802 #define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */
14803 
14804 /********************  Bit definition for CONFR6 register  ********************/
14805 #define JPEG_CONFR6_HD_Pos              (0U)
14806 #define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */
14807 #define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
14808 #define JPEG_CONFR6_HA_Pos              (1U)
14809 #define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */
14810 #define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
14811 #define JPEG_CONFR6_QT_Pos              (2U)
14812 #define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */
14813 #define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */
14814 #define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */
14815 #define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */
14816 #define JPEG_CONFR6_NB_Pos              (4U)
14817 #define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */
14818 #define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
14819 #define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */
14820 #define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */
14821 #define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */
14822 #define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */
14823 #define JPEG_CONFR6_VSF_Pos             (8U)
14824 #define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */
14825 #define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
14826 #define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */
14827 #define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */
14828 #define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */
14829 #define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */
14830 #define JPEG_CONFR6_HSF_Pos             (12U)
14831 #define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */
14832 #define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
14833 #define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */
14834 #define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */
14835 #define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */
14836 #define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */
14837 
14838 /********************  Bit definition for CONFR7 register  ********************/
14839 #define JPEG_CONFR7_HD_Pos              (0U)
14840 #define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */
14841 #define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
14842 #define JPEG_CONFR7_HA_Pos              (1U)
14843 #define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */
14844 #define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
14845 #define JPEG_CONFR7_QT_Pos              (2U)
14846 #define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */
14847 #define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */
14848 #define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */
14849 #define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */
14850 #define JPEG_CONFR7_NB_Pos              (4U)
14851 #define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */
14852 #define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
14853 #define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */
14854 #define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */
14855 #define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */
14856 #define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */
14857 #define JPEG_CONFR7_VSF_Pos             (8U)
14858 #define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */
14859 #define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
14860 #define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */
14861 #define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */
14862 #define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */
14863 #define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */
14864 #define JPEG_CONFR7_HSF_Pos             (12U)
14865 #define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */
14866 #define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
14867 #define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */
14868 #define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */
14869 #define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */
14870 #define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */
14871 
14872 /********************  Bit definition for CR register  ********************/
14873 #define JPEG_CR_JCEN_Pos                (0U)
14874 #define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */
14875 #define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */
14876 #define JPEG_CR_IFTIE_Pos               (1U)
14877 #define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */
14878 #define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */
14879 #define JPEG_CR_IFNFIE_Pos              (2U)
14880 #define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */
14881 #define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */
14882 #define JPEG_CR_OFTIE_Pos               (3U)
14883 #define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */
14884 #define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */
14885 #define JPEG_CR_OFNEIE_Pos              (4U)
14886 #define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */
14887 #define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */
14888 #define JPEG_CR_EOCIE_Pos               (5U)
14889 #define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */
14890 #define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */
14891 #define JPEG_CR_HPDIE_Pos               (6U)
14892 #define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */
14893 #define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */
14894 #define JPEG_CR_IDMAEN_Pos              (11U)
14895 #define JPEG_CR_IDMAEN_Msk              (0x1UL << JPEG_CR_IDMAEN_Pos)           /*!< 0x00000800 */
14896 #define JPEG_CR_IDMAEN                  JPEG_CR_IDMAEN_Msk                     /*!<Enable the DMA request generation for the input FIFO */
14897 #define JPEG_CR_ODMAEN_Pos              (12U)
14898 #define JPEG_CR_ODMAEN_Msk              (0x1UL << JPEG_CR_ODMAEN_Pos)           /*!< 0x00001000 */
14899 #define JPEG_CR_ODMAEN                  JPEG_CR_ODMAEN_Msk                     /*!<Enable the DMA request generation for the output FIFO */
14900 #define JPEG_CR_IFF_Pos                 (13U)
14901 #define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */
14902 #define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */
14903 #define JPEG_CR_OFF_Pos                 (14U)
14904 #define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */
14905 #define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */
14906 
14907 /********************  Bit definition for SR register  ********************/
14908 #define JPEG_SR_IFTF_Pos                (1U)
14909 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
14910 #define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
14911 #define JPEG_SR_IFNFF_Pos               (2U)
14912 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
14913 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
14914 #define JPEG_SR_OFTF_Pos                (3U)
14915 #define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */
14916 #define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */
14917 #define JPEG_SR_OFNEF_Pos               (4U)
14918 #define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */
14919 #define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */
14920 #define JPEG_SR_EOCF_Pos                (5U)
14921 #define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */
14922 #define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
14923 #define JPEG_SR_HPDF_Pos                (6U)
14924 #define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */
14925 #define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
14926 #define JPEG_SR_COF_Pos                 (7U)
14927 #define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */
14928 #define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */
14929 
14930 /********************  Bit definition for CFR register  ********************/
14931 #define JPEG_CFR_CEOCF_Pos              (4U)
14932 #define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */
14933 #define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */
14934 #define JPEG_CFR_CHPDF_Pos              (5U)
14935 #define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */
14936 #define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */
14937 
14938 /********************  Bit definition for DIR register  ********************/
14939 #define JPEG_DIR_DATAIN_Pos             (0U)
14940 #define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */
14941 #define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */
14942 
14943 /********************  Bit definition for DOR register  ********************/
14944 #define JPEG_DOR_DATAOUT_Pos            (0U)
14945 #define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
14946 #define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */
14947 
14948 /******************************************************************************/
14949 /*                                                                            */
14950 /*                       Low Power General Purpose IOs (LPGPIO)               */
14951 /*                                                                            */
14952 /******************************************************************************/
14953 /******************  Bits definition for LPGPIO_MODER register  *****************/
14954 #define LPGPIO_MODER_MOD0_Pos               (0U)
14955 #define LPGPIO_MODER_MOD0_Msk               (0x1UL << LPGPIO_MODER_MOD0_Pos)        /*!< 0x00000001 */
14956 #define LPGPIO_MODER_MOD0                   LPGPIO_MODER_MOD0_Msk
14957 #define LPGPIO_MODER_MOD1_Pos               (1U)
14958 #define LPGPIO_MODER_MOD1_Msk               (0x1UL << LPGPIO_MODER_MOD1_Pos)        /*!< 0x00000002 */
14959 #define LPGPIO_MODER_MOD1                   LPGPIO_MODER_MOD1_Msk
14960 #define LPGPIO_MODER_MOD2_Pos               (2U)
14961 #define LPGPIO_MODER_MOD2_Msk               (0x1UL << LPGPIO_MODER_MOD2_Pos)        /*!< 0x00000004 */
14962 #define LPGPIO_MODER_MOD2                   LPGPIO_MODER_MOD2_Msk
14963 #define LPGPIO_MODER_MOD3_Pos               (3U)
14964 #define LPGPIO_MODER_MOD3_Msk               (0x1UL << LPGPIO_MODER_MOD3_Pos)        /*!< 0x00000008 */
14965 #define LPGPIO_MODER_MOD3                   LPGPIO_MODER_MOD3_Msk
14966 #define LPGPIO_MODER_MOD4_Pos               (4U)
14967 #define LPGPIO_MODER_MOD4_Msk               (0x1UL << LPGPIO_MODER_MOD4_Pos)        /*!< 0x00000010 */
14968 #define LPGPIO_MODER_MOD4                   LPGPIO_MODER_MOD4_Msk
14969 #define LPGPIO_MODER_MOD5_Pos               (5U)
14970 #define LPGPIO_MODER_MOD5_Msk               (0x1UL << LPGPIO_MODER_MOD5_Pos)        /*!< 0x00000020 */
14971 #define LPGPIO_MODER_MOD5                   LPGPIO_MODER_MOD5_Msk
14972 #define LPGPIO_MODER_MOD6_Pos               (6U)
14973 #define LPGPIO_MODER_MOD6_Msk               (0x1UL << LPGPIO_MODER_MOD6_Pos)        /*!< 0x00000040 */
14974 #define LPGPIO_MODER_MOD6                   LPGPIO_MODER_MOD6_Msk
14975 #define LPGPIO_MODER_MOD7_Pos               (7U)
14976 #define LPGPIO_MODER_MOD7_Msk               (0x1UL << LPGPIO_MODER_MOD7_Pos)        /*!< 0x00000080 */
14977 #define LPGPIO_MODER_MOD7                   LPGPIO_MODER_MOD7_Msk
14978 #define LPGPIO_MODER_MOD8_Pos               (8U)
14979 #define LPGPIO_MODER_MOD8_Msk               (0x1UL << LPGPIO_MODER_MOD8_Pos)        /*!< 0x00000100 */
14980 #define LPGPIO_MODER_MOD8                   LPGPIO_MODER_MOD8_Msk
14981 #define LPGPIO_MODER_MOD9_Pos               (9U)
14982 #define LPGPIO_MODER_MOD9_Msk               (0x1UL << LPGPIO_MODER_MOD9_Pos)        /*!< 0x00000200 */
14983 #define LPGPIO_MODER_MOD9                   LPGPIO_MODER_MOD9_Msk
14984 #define LPGPIO_MODER_MOD10_Pos              (10U)
14985 #define LPGPIO_MODER_MOD10_Msk              (0x1UL << LPGPIO_MODER_MOD10_Pos)       /*!< 0x00000400 */
14986 #define LPGPIO_MODER_MOD10                  LPGPIO_MODER_MOD10_Msk
14987 #define LPGPIO_MODER_MOD11_Pos              (11U)
14988 #define LPGPIO_MODER_MOD11_Msk              (0x1UL << LPGPIO_MODER_MOD11_Pos)       /*!< 0x00000800 */
14989 #define LPGPIO_MODER_MOD11                  LPGPIO_MODER_MOD11_Msk
14990 #define LPGPIO_MODER_MOD12_Pos              (12U)
14991 #define LPGPIO_MODER_MOD12_Msk              (0x1UL << LPGPIO_MODER_MOD12_Pos)       /*!< 0x00001000 */
14992 #define LPGPIO_MODER_MOD12                  LPGPIO_MODER_MOD12_Msk
14993 #define LPGPIO_MODER_MOD13_Pos              (13U)
14994 #define LPGPIO_MODER_MOD13_Msk              (0x1UL << LPGPIO_MODER_MOD13_Pos)       /*!< 0x00002000 */
14995 #define LPGPIO_MODER_MOD13                  LPGPIO_MODER_MOD13_Msk
14996 #define LPGPIO_MODER_MOD14_Pos              (14U)
14997 #define LPGPIO_MODER_MOD14_Msk              (0x1UL << LPGPIO_MODER_MOD14_Pos)       /*!< 0x00004000 */
14998 #define LPGPIO_MODER_MOD14                  LPGPIO_MODER_MOD14_Msk
14999 #define LPGPIO_MODER_MOD15_Pos              (15U)
15000 #define LPGPIO_MODER_MOD15_Msk              (0x1UL << LPGPIO_MODER_MOD15_Pos)       /*!< 0x00008000 */
15001 #define LPGPIO_MODER_MOD15                  LPGPIO_MODER_MOD15_Msk
15002 
15003 /******************  Bits definition for LPGPIO_IDR register  *******************/
15004 #define LPGPIO_IDR_ID0_Pos                  (0U)
15005 #define LPGPIO_IDR_ID0_Msk                  (0x1UL << LPGPIO_IDR_ID0_Pos)           /*!< 0x00000001 */
15006 #define LPGPIO_IDR_ID0                      LPGPIO_IDR_ID0_Msk
15007 #define LPGPIO_IDR_ID1_Pos                  (1U)
15008 #define LPGPIO_IDR_ID1_Msk                  (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
15009 #define LPGPIO_IDR_ID1                      LPGPIO_IDR_ID1_Msk
15010 #define LPGPIO_IDR_ID2_Pos                  (2U)
15011 #define LPGPIO_IDR_ID2_Msk                  (0x1UL << LPGPIO_IDR_ID2_Pos)           /*!< 0x00000004 */
15012 #define LPGPIO_IDR_ID2                      LPGPIO_IDR_ID2_Msk
15013 #define LPGPIO_IDR_ID3_Pos                  (3U)
15014 #define LPGPIO_IDR_ID3_Msk                  (0x1UL << LPGPIO_IDR_ID3_Pos)           /*!< 0x00000008 */
15015 #define LPGPIO_IDR_ID3                      LPGPIO_IDR_ID3_Msk
15016 #define LPGPIO_IDR_ID4_Pos                  (4U)
15017 #define LPGPIO_IDR_ID4_Msk                  (0x1UL << LPGPIO_IDR_ID4_Pos)           /*!< 0x00000010 */
15018 #define LPGPIO_IDR_ID4                      LPGPIO_IDR_ID4_Msk
15019 #define LPGPIO_IDR_ID5_Pos                  (5U)
15020 #define LPGPIO_IDR_ID5_Msk                  (0x1UL << LPGPIO_IDR_ID5_Pos)           /*!< 0x00000020 */
15021 #define LPGPIO_IDR_ID5                      LPGPIO_IDR_ID5_Msk
15022 #define LPGPIO_IDR_ID6_Pos                  (6U)
15023 #define LPGPIO_IDR_ID6_Msk                  (0x1UL << LPGPIO_IDR_ID6_Pos)           /*!< 0x00000040 */
15024 #define LPGPIO_IDR_ID6                      LPGPIO_IDR_ID6_Msk
15025 #define LPGPIO_IDR_ID7_Pos                  (7U)
15026 #define LPGPIO_IDR_ID7_Msk                  (0x1UL << LPGPIO_IDR_ID7_Pos)           /*!< 0x00000080 */
15027 #define LPGPIO_IDR_ID7                      LPGPIO_IDR_ID7_Msk
15028 #define LPGPIO_IDR_ID8_Pos                  (8U)
15029 #define LPGPIO_IDR_ID8_Msk                  (0x1UL << LPGPIO_IDR_ID8_Pos)           /*!< 0x00000100 */
15030 #define LPGPIO_IDR_ID8                      LPGPIO_IDR_ID8_Msk
15031 #define LPGPIO_IDR_ID9_Pos                  (9U)
15032 #define LPGPIO_IDR_ID9_Msk                  (0x1UL << LPGPIO_IDR_ID9_Pos)           /*!< 0x00000200 */
15033 #define LPGPIO_IDR_ID9                      LPGPIO_IDR_ID9_Msk
15034 #define LPGPIO_IDR_ID10_Pos                 (10U)
15035 #define LPGPIO_IDR_ID10_Msk                 (0x1UL << LPGPIO_IDR_ID10_Pos)          /*!< 0x00000400 */
15036 #define LPGPIO_IDR_ID10                     LPGPIO_IDR_ID10_Msk
15037 #define LPGPIO_IDR_ID11_Pos                 (11U)
15038 #define LPGPIO_IDR_ID11_Msk                 (0x1UL << LPGPIO_IDR_ID11_Pos)          /*!< 0x00000800 */
15039 #define LPGPIO_IDR_ID11                     LPGPIO_IDR_ID11_Msk
15040 #define LPGPIO_IDR_ID12_Pos                 (12U)
15041 #define LPGPIO_IDR_ID12_Msk                 (0x1UL << LPGPIO_IDR_ID12_Pos)          /*!< 0x00001000 */
15042 #define LPGPIO_IDR_ID12                     LPGPIO_IDR_ID12_Msk
15043 #define LPGPIO_IDR_ID13_Pos                 (13U)
15044 #define LPGPIO_IDR_ID13_Msk                 (0x1UL << LPGPIO_IDR_ID13_Pos)          /*!< 0x00002000 */
15045 #define LPGPIO_IDR_ID13                     LPGPIO_IDR_ID13_Msk
15046 #define LPGPIO_IDR_ID14_Pos                 (14U)
15047 #define LPGPIO_IDR_ID14_Msk                 (0x1UL << LPGPIO_IDR_ID14_Pos)          /*!< 0x00004000 */
15048 #define LPGPIO_IDR_ID14                     LPGPIO_IDR_ID14_Msk
15049 #define LPGPIO_IDR_ID15_Pos                 (15U)
15050 #define LPGPIO_IDR_ID15_Msk                 (0x1UL << LPGPIO_IDR_ID15_Pos)          /*!< 0x00008000 */
15051 #define LPGPIO_IDR_ID15                     LPGPIO_IDR_ID15_Msk
15052 
15053 /******************  Bits definition for LPGPIO_ODR register  *******************/
15054 #define LPGPIO_ODR_OD0_Pos                  (0U)
15055 #define LPGPIO_ODR_OD0_Msk                  (0x1UL << LPGPIO_ODR_OD0_Pos)           /*!< 0x00000001 */
15056 #define LPGPIO_ODR_OD0                      LPGPIO_ODR_OD0_Msk
15057 #define LPGPIO_ODR_OD1_Pos                  (1U)
15058 #define LPGPIO_ODR_OD1_Msk                  (0x1UL << LPGPIO_ODR_OD1_Pos)           /*!< 0x00000002 */
15059 #define LPGPIO_ODR_OD1                      LPGPIO_ODR_OD1_Msk
15060 #define LPGPIO_ODR_OD2_Pos                  (2U)
15061 #define LPGPIO_ODR_OD2_Msk                  (0x1UL << LPGPIO_ODR_OD2_Pos)           /*!< 0x00000004 */
15062 #define LPGPIO_ODR_OD2                      LPGPIO_ODR_OD2_Msk
15063 #define LPGPIO_ODR_OD3_Pos                  (3U)
15064 #define LPGPIO_ODR_OD3_Msk                  (0x1UL << LPGPIO_ODR_OD3_Pos)           /*!< 0x00000008 */
15065 #define LPGPIO_ODR_OD3                      LPGPIO_ODR_OD3_Msk
15066 #define LPGPIO_ODR_OD4_Pos                  (4U)
15067 #define LPGPIO_ODR_OD4_Msk                  (0x1UL << LPGPIO_ODR_OD4_Pos)           /*!< 0x00000010 */
15068 #define LPGPIO_ODR_OD4                      LPGPIO_ODR_OD4_Msk
15069 #define LPGPIO_ODR_OD5_Pos                  (5U)
15070 #define LPGPIO_ODR_OD5_Msk                  (0x1UL << LPGPIO_ODR_OD5_Pos)           /*!< 0x00000020 */
15071 #define LPGPIO_ODR_OD5                      LPGPIO_ODR_OD5_Msk
15072 #define LPGPIO_ODR_OD6_Pos                  (6U)
15073 #define LPGPIO_ODR_OD6_Msk                  (0x1UL << LPGPIO_ODR_OD6_Pos)           /*!< 0x00000040 */
15074 #define LPGPIO_ODR_OD6                      LPGPIO_ODR_OD6_Msk
15075 #define LPGPIO_ODR_OD7_Pos                  (7U)
15076 #define LPGPIO_ODR_OD7_Msk                  (0x1UL << LPGPIO_ODR_OD7_Pos)           /*!< 0x00000080 */
15077 #define LPGPIO_ODR_OD7                      LPGPIO_ODR_OD7_Msk
15078 #define LPGPIO_ODR_OD8_Pos                  (8U)
15079 #define LPGPIO_ODR_OD8_Msk                  (0x1UL << LPGPIO_ODR_OD8_Pos)           /*!< 0x00000100 */
15080 #define LPGPIO_ODR_OD8                      LPGPIO_ODR_OD8_Msk
15081 #define LPGPIO_ODR_OD9_Pos                  (9U)
15082 #define LPGPIO_ODR_OD9_Msk                  (0x1UL << LPGPIO_ODR_OD9_Pos)           /*!< 0x00000200 */
15083 #define LPGPIO_ODR_OD9                      LPGPIO_ODR_OD9_Msk
15084 #define LPGPIO_ODR_OD10_Pos                 (10U)
15085 #define LPGPIO_ODR_OD10_Msk                 (0x1UL << LPGPIO_ODR_OD10_Pos)          /*!< 0x00000400 */
15086 #define LPGPIO_ODR_OD10                     LPGPIO_ODR_OD10_Msk
15087 #define LPGPIO_ODR_OD11_Pos                 (11U)
15088 #define LPGPIO_ODR_OD11_Msk                 (0x1UL << LPGPIO_ODR_OD11_Pos)          /*!< 0x00000800 */
15089 #define LPGPIO_ODR_OD11                     LPGPIO_ODR_OD11_Msk
15090 #define LPGPIO_ODR_OD12_Pos                 (12U)
15091 #define LPGPIO_ODR_OD12_Msk                 (0x1UL << LPGPIO_ODR_OD12_Pos)          /*!< 0x00001000 */
15092 #define LPGPIO_ODR_OD12                     LPGPIO_ODR_OD12_Msk
15093 #define LPGPIO_ODR_OD13_Pos                 (13U)
15094 #define LPGPIO_ODR_OD13_Msk                 (0x1UL << LPGPIO_ODR_OD13_Pos)          /*!< 0x00002000 */
15095 #define LPGPIO_ODR_OD13                     LPGPIO_ODR_OD13_Msk
15096 #define LPGPIO_ODR_OD14_Pos                 (14U)
15097 #define LPGPIO_ODR_OD14_Msk                 (0x1UL << LPGPIO_ODR_OD14_Pos)          /*!< 0x00004000 */
15098 #define LPGPIO_ODR_OD14                     LPGPIO_ODR_OD14_Msk
15099 #define LPGPIO_ODR_OD15_Pos                 (15U)
15100 #define LPGPIO_ODR_OD15_Msk                 (0x1UL << LPGPIO_ODR_OD15_Pos)          /*!< 0x00008000 */
15101 #define LPGPIO_ODR_OD15                     LPGPIO_ODR_OD15_Msk
15102 
15103 /******************  Bits definition for LPGPIO_BSRR register  ******************/
15104 #define LPGPIO_BSRR_BS0_Pos                 (0U)
15105 #define LPGPIO_BSRR_BS0_Msk                 (0x1UL << LPGPIO_BSRR_BS0_Pos)          /*!< 0x00000001 */
15106 #define LPGPIO_BSRR_BS0                     LPGPIO_BSRR_BS0_Msk
15107 #define LPGPIO_BSRR_BS1_Pos                 (1U)
15108 #define LPGPIO_BSRR_BS1_Msk                 (0x1UL << LPGPIO_BSRR_BS1_Pos)          /*!< 0x00000002 */
15109 #define LPGPIO_BSRR_BS1                     LPGPIO_BSRR_BS1_Msk
15110 #define LPGPIO_BSRR_BS2_Pos                 (2U)
15111 #define LPGPIO_BSRR_BS2_Msk                 (0x1UL << LPGPIO_BSRR_BS2_Pos)          /*!< 0x00000004 */
15112 #define LPGPIO_BSRR_BS2                     LPGPIO_BSRR_BS2_Msk
15113 #define LPGPIO_BSRR_BS3_Pos                 (3U)
15114 #define LPGPIO_BSRR_BS3_Msk                 (0x1UL << LPGPIO_BSRR_BS3_Pos)          /*!< 0x00000008 */
15115 #define LPGPIO_BSRR_BS3                     LPGPIO_BSRR_BS3_Msk
15116 #define LPGPIO_BSRR_BS4_Pos                 (4U)
15117 #define LPGPIO_BSRR_BS4_Msk                 (0x1UL << LPGPIO_BSRR_BS4_Pos)          /*!< 0x00000010 */
15118 #define LPGPIO_BSRR_BS4                     LPGPIO_BSRR_BS4_Msk
15119 #define LPGPIO_BSRR_BS5_Pos                 (5U)
15120 #define LPGPIO_BSRR_BS5_Msk                 (0x1UL << LPGPIO_BSRR_BS5_Pos)          /*!< 0x00000020 */
15121 #define LPGPIO_BSRR_BS5                     LPGPIO_BSRR_BS5_Msk
15122 #define LPGPIO_BSRR_BS6_Pos                 (6U)
15123 #define LPGPIO_BSRR_BS6_Msk                 (0x1UL << LPGPIO_BSRR_BS6_Pos)          /*!< 0x00000040 */
15124 #define LPGPIO_BSRR_BS6                     LPGPIO_BSRR_BS6_Msk
15125 #define LPGPIO_BSRR_BS7_Pos                 (7U)
15126 #define LPGPIO_BSRR_BS7_Msk                 (0x1UL << LPGPIO_BSRR_BS7_Pos)          /*!< 0x00000080 */
15127 #define LPGPIO_BSRR_BS7                     LPGPIO_BSRR_BS7_Msk
15128 #define LPGPIO_BSRR_BS8_Pos                 (8U)
15129 #define LPGPIO_BSRR_BS8_Msk                 (0x1UL << LPGPIO_BSRR_BS8_Pos)          /*!< 0x00000100 */
15130 #define LPGPIO_BSRR_BS8                     LPGPIO_BSRR_BS8_Msk
15131 #define LPGPIO_BSRR_BS9_Pos                 (9U)
15132 #define LPGPIO_BSRR_BS9_Msk                 (0x1UL << LPGPIO_BSRR_BS9_Pos)          /*!< 0x00000200 */
15133 #define LPGPIO_BSRR_BS9                     LPGPIO_BSRR_BS9_Msk
15134 #define LPGPIO_BSRR_BS10_Pos                (10U)
15135 #define LPGPIO_BSRR_BS10_Msk                (0x1UL << LPGPIO_BSRR_BS10_Pos)         /*!< 0x00000400 */
15136 #define LPGPIO_BSRR_BS10                    LPGPIO_BSRR_BS10_Msk
15137 #define LPGPIO_BSRR_BS11_Pos                (11U)
15138 #define LPGPIO_BSRR_BS11_Msk                (0x1UL << LPGPIO_BSRR_BS11_Pos)         /*!< 0x00000800 */
15139 #define LPGPIO_BSRR_BS11                    LPGPIO_BSRR_BS11_Msk
15140 #define LPGPIO_BSRR_BS12_Pos                (12U)
15141 #define LPGPIO_BSRR_BS12_Msk                (0x1UL << LPGPIO_BSRR_BS12_Pos)         /*!< 0x00001000 */
15142 #define LPGPIO_BSRR_BS12                    LPGPIO_BSRR_BS12_Msk
15143 #define LPGPIO_BSRR_BS13_Pos                (13U)
15144 #define LPGPIO_BSRR_BS13_Msk                (0x1UL << LPGPIO_BSRR_BS13_Pos)         /*!< 0x00002000 */
15145 #define LPGPIO_BSRR_BS13                    LPGPIO_BSRR_BS13_Msk
15146 #define LPGPIO_BSRR_BS14_Pos                (14U)
15147 #define LPGPIO_BSRR_BS14_Msk                (0x1UL << LPGPIO_BSRR_BS14_Pos)         /*!< 0x00004000 */
15148 #define LPGPIO_BSRR_BS14                    LPGPIO_BSRR_BS14_Msk
15149 #define LPGPIO_BSRR_BS15_Pos                (15U)
15150 #define LPGPIO_BSRR_BS15_Msk                (0x1UL << LPGPIO_BSRR_BS15_Pos)         /*!< 0x00008000 */
15151 #define LPGPIO_BSRR_BS15                    LPGPIO_BSRR_BS15_Msk
15152 #define LPGPIO_BSRR_BR0_Pos                 (16U)
15153 #define LPGPIO_BSRR_BR0_Msk                 (0x1UL << LPGPIO_BSRR_BR0_Pos)          /*!< 0x00010000 */
15154 #define LPGPIO_BSRR_BR0                     LPGPIO_BSRR_BR0_Msk
15155 #define LPGPIO_BSRR_BR1_Pos                 (17U)
15156 #define LPGPIO_BSRR_BR1_Msk                 (0x1UL << LPGPIO_BSRR_BR1_Pos)          /*!< 0x00020000 */
15157 #define LPGPIO_BSRR_BR1                     LPGPIO_BSRR_BR1_Msk
15158 #define LPGPIO_BSRR_BR2_Pos                 (18U)
15159 #define LPGPIO_BSRR_BR2_Msk                 (0x1UL << LPGPIO_BSRR_BR2_Pos)          /*!< 0x00040000 */
15160 #define LPGPIO_BSRR_BR2                     LPGPIO_BSRR_BR2_Msk
15161 #define LPGPIO_BSRR_BR3_Pos                 (19U)
15162 #define LPGPIO_BSRR_BR3_Msk                 (0x1UL << LPGPIO_BSRR_BR3_Pos)          /*!< 0x00080000 */
15163 #define LPGPIO_BSRR_BR3                     LPGPIO_BSRR_BR3_Msk
15164 #define LPGPIO_BSRR_BR4_Pos                 (20U)
15165 #define LPGPIO_BSRR_BR4_Msk                 (0x1UL << LPGPIO_BSRR_BR4_Pos)          /*!< 0x00100000 */
15166 #define LPGPIO_BSRR_BR4                     LPGPIO_BSRR_BR4_Msk
15167 #define LPGPIO_BSRR_BR5_Pos                 (21U)
15168 #define LPGPIO_BSRR_BR5_Msk                 (0x1UL << LPGPIO_BSRR_BR5_Pos)          /*!< 0x00200000 */
15169 #define LPGPIO_BSRR_BR5                     LPGPIO_BSRR_BR5_Msk
15170 #define LPGPIO_BSRR_BR6_Pos                 (22U)
15171 #define LPGPIO_BSRR_BR6_Msk                 (0x1UL << LPGPIO_BSRR_BR6_Pos)          /*!< 0x00400000 */
15172 #define LPGPIO_BSRR_BR6                     LPGPIO_BSRR_BR6_Msk
15173 #define LPGPIO_BSRR_BR7_Pos                 (23U)
15174 #define LPGPIO_BSRR_BR7_Msk                 (0x1UL << LPGPIO_BSRR_BR7_Pos)          /*!< 0x00800000 */
15175 #define LPGPIO_BSRR_BR7                     LPGPIO_BSRR_BR7_Msk
15176 #define LPGPIO_BSRR_BR8_Pos                 (24U)
15177 #define LPGPIO_BSRR_BR8_Msk                 (0x1UL << LPGPIO_BSRR_BR8_Pos)          /*!< 0x01000000 */
15178 #define LPGPIO_BSRR_BR8                     LPGPIO_BSRR_BR8_Msk
15179 #define LPGPIO_BSRR_BR9_Pos                 (25U)
15180 #define LPGPIO_BSRR_BR9_Msk                 (0x1UL << LPGPIO_BSRR_BR9_Pos)          /*!< 0x02000000 */
15181 #define LPGPIO_BSRR_BR9                     LPGPIO_BSRR_BR9_Msk
15182 #define LPGPIO_BSRR_BR10_Pos                (26U)
15183 #define LPGPIO_BSRR_BR10_Msk                (0x1UL << LPGPIO_BSRR_BR10_Pos)         /*!< 0x04000000 */
15184 #define LPGPIO_BSRR_BR10                    LPGPIO_BSRR_BR10_Msk
15185 #define LPGPIO_BSRR_BR11_Pos                (27U)
15186 #define LPGPIO_BSRR_BR11_Msk                (0x1UL << LPGPIO_BSRR_BR11_Pos)         /*!< 0x08000000 */
15187 #define LPGPIO_BSRR_BR11                    LPGPIO_BSRR_BR11_Msk
15188 #define LPGPIO_BSRR_BR12_Pos                (28U)
15189 #define LPGPIO_BSRR_BR12_Msk                (0x1UL << LPGPIO_BSRR_BR12_Pos)         /*!< 0x10000000 */
15190 #define LPGPIO_BSRR_BR12                    LPGPIO_BSRR_BR12_Msk
15191 #define LPGPIO_BSRR_BR13_Pos                (29U)
15192 #define LPGPIO_BSRR_BR13_Msk                (0x1UL << LPGPIO_BSRR_BR13_Pos)         /*!< 0x20000000 */
15193 #define LPGPIO_BSRR_BR13                    LPGPIO_BSRR_BR13_Msk
15194 #define LPGPIO_BSRR_BR14_Pos                (30U)
15195 #define LPGPIO_BSRR_BR14_Msk                (0x1UL << LPGPIO_BSRR_BR14_Pos)         /*!< 0x40000000 */
15196 #define LPGPIO_BSRR_BR14                    LPGPIO_BSRR_BR14_Msk
15197 #define LPGPIO_BSRR_BR15_Pos                (31U)
15198 #define LPGPIO_BSRR_BR15_Msk                (0x1UL << LPGPIO_BSRR_BR15_Pos)         /*!< 0x80000000 */
15199 #define LPGPIO_BSRR_BR15                    LPGPIO_BSRR_BR15_Msk
15200 
15201 /******************  Bits definition for LPGPIO_BRR register  ******************/
15202 #define LPGPIO_BRR_BR0_Pos                  (0U)
15203 #define LPGPIO_BRR_BR0_Msk                  (0x1UL << LPGPIO_BRR_BR0_Pos)           /*!< 0x00000001 */
15204 #define LPGPIO_BRR_BR0                      LPGPIO_BRR_BR0_Msk
15205 #define LPGPIO_BRR_BR1_Pos                  (1U)
15206 #define LPGPIO_BRR_BR1_Msk                  (0x1UL << LPGPIO_BRR_BR1_Pos)           /*!< 0x00000002 */
15207 #define LPGPIO_BRR_BR1                      LPGPIO_BRR_BR1_Msk
15208 #define LPGPIO_BRR_BR2_Pos                  (2U)
15209 #define LPGPIO_BRR_BR2_Msk                  (0x1UL << LPGPIO_BRR_BR2_Pos)           /*!< 0x00000004 */
15210 #define LPGPIO_BRR_BR2                      LPGPIO_BRR_BR2_Msk
15211 #define LPGPIO_BRR_BR3_Pos                  (3U)
15212 #define LPGPIO_BRR_BR3_Msk                  (0x1UL << LPGPIO_BRR_BR3_Pos)           /*!< 0x00000008 */
15213 #define LPGPIO_BRR_BR3                      LPGPIO_BRR_BR3_Msk
15214 #define LPGPIO_BRR_BR4_Pos                  (4U)
15215 #define LPGPIO_BRR_BR4_Msk                  (0x1UL << LPGPIO_BRR_BR4_Pos)           /*!< 0x00000010 */
15216 #define LPGPIO_BRR_BR4                      LPGPIO_BRR_BR4_Msk
15217 #define LPGPIO_BRR_BR5_Pos                  (5U)
15218 #define LPGPIO_BRR_BR5_Msk                  (0x1UL << LPGPIO_BRR_BR5_Pos)           /*!< 0x00000020 */
15219 #define LPGPIO_BRR_BR5                      LPGPIO_BRR_BR5_Msk
15220 #define LPGPIO_BRR_BR6_Pos                  (6U)
15221 #define LPGPIO_BRR_BR6_Msk                  (0x1UL << LPGPIO_BRR_BR6_Pos)           /*!< 0x00000040 */
15222 #define LPGPIO_BRR_BR6                      LPGPIO_BRR_BR6_Msk
15223 #define LPGPIO_BRR_BR7_Pos                  (7U)
15224 #define LPGPIO_BRR_BR7_Msk                  (0x1UL << LPGPIO_BRR_BR7_Pos)           /*!< 0x00000080 */
15225 #define LPGPIO_BRR_BR7                      LPGPIO_BRR_BR7_Msk
15226 #define LPGPIO_BRR_BR8_Pos                  (8U)
15227 #define LPGPIO_BRR_BR8_Msk                  (0x1UL << LPGPIO_BRR_BR8_Pos)           /*!< 0x00000100 */
15228 #define LPGPIO_BRR_BR8                      LPGPIO_BRR_BR8_Msk
15229 #define LPGPIO_BRR_BR9_Pos                  (9U)
15230 #define LPGPIO_BRR_BR9_Msk                  (0x1UL << LPGPIO_BRR_BR9_Pos)           /*!< 0x00000200 */
15231 #define LPGPIO_BRR_BR9                      LPGPIO_BRR_BR9_Msk
15232 #define LPGPIO_BRR_BR10_Pos                 (10U)
15233 #define LPGPIO_BRR_BR10_Msk                 (0x1UL << LPGPIO_BRR_BR10_Pos)          /*!< 0x00000400 */
15234 #define LPGPIO_BRR_BR10                     LPGPIO_BRR_BR10_Msk
15235 #define LPGPIO_BRR_BR11_Pos                 (11U)
15236 #define LPGPIO_BRR_BR11_Msk                 (0x1UL << LPGPIO_BRR_BR11_Pos)          /*!< 0x00000800 */
15237 #define LPGPIO_BRR_BR11                     LPGPIO_BRR_BR11_Msk
15238 #define LPGPIO_BRR_BR12_Pos                 (12U)
15239 #define LPGPIO_BRR_BR12_Msk                 (0x1UL << LPGPIO_BRR_BR12_Pos)          /*!< 0x00001000 */
15240 #define LPGPIO_BRR_BR12                     LPGPIO_BRR_BR12_Msk
15241 #define LPGPIO_BRR_BR13_Pos                 (13U)
15242 #define LPGPIO_BRR_BR13_Msk                 (0x1UL << LPGPIO_BRR_BR13_Pos)          /*!< 0x00002000 */
15243 #define LPGPIO_BRR_BR13                     LPGPIO_BRR_BR13_Msk
15244 #define LPGPIO_BRR_BR14_Pos                 (14U)
15245 #define LPGPIO_BRR_BR14_Msk                 (0x1UL << LPGPIO_BRR_BR14_Pos)          /*!< 0x00004000 */
15246 #define LPGPIO_BRR_BR14                     LPGPIO_BRR_BR14_Msk
15247 #define LPGPIO_BRR_BR15_Pos                 (15U)
15248 #define LPGPIO_BRR_BR15_Msk                 (0x1UL << LPGPIO_BRR_BR15_Pos)          /*!< 0x00008000 */
15249 #define LPGPIO_BRR_BR15                     LPGPIO_BRR_BR15_Msk
15250 
15251 /******************************************************************************/
15252 /*                                                                            */
15253 /*                      LCD-TFT Display Controller (LTDC)                     */
15254 /*                                                                            */
15255 /******************************************************************************/
15256 
15257 /********************  Bit definition for LTDC_SSCR register  *****************/
15258 
15259 #define LTDC_SSCR_VSH_Pos            (0U)
15260 #define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */
15261 #define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */
15262 #define LTDC_SSCR_HSW_Pos            (16U)
15263 #define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */
15264 #define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
15265 
15266 /********************  Bit definition for LTDC_BPCR register  *****************/
15267 
15268 #define LTDC_BPCR_AVBP_Pos           (0U)
15269 #define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */
15270 #define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */
15271 #define LTDC_BPCR_AHBP_Pos           (16U)
15272 #define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */
15273 #define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
15274 
15275 /********************  Bit definition for LTDC_AWCR register  *****************/
15276 
15277 #define LTDC_AWCR_AAH_Pos            (0U)
15278 #define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */
15279 #define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active height */
15280 #define LTDC_AWCR_AAW_Pos            (16U)
15281 #define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */
15282 #define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
15283 
15284 /********************  Bit definition for LTDC_TWCR register  *****************/
15285 
15286 #define LTDC_TWCR_TOTALH_Pos         (0U)
15287 #define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */
15288 #define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Height */
15289 #define LTDC_TWCR_TOTALW_Pos         (16U)
15290 #define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */
15291 #define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
15292 
15293 /********************  Bit definition for LTDC_GCR register  ******************/
15294 
15295 #define LTDC_GCR_LTDCEN_Pos          (0U)
15296 #define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */
15297 #define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */
15298 #define LTDC_GCR_DBW_Pos             (4U)
15299 #define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */
15300 #define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */
15301 #define LTDC_GCR_DGW_Pos             (8U)
15302 #define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */
15303 #define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */
15304 #define LTDC_GCR_DRW_Pos             (12U)
15305 #define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */
15306 #define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */
15307 #define LTDC_GCR_DEN_Pos             (16U)
15308 #define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */
15309 #define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */
15310 #define LTDC_GCR_PCPOL_Pos           (28U)
15311 #define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */
15312 #define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */
15313 #define LTDC_GCR_DEPOL_Pos           (29U)
15314 #define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */
15315 #define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */
15316 #define LTDC_GCR_VSPOL_Pos           (30U)
15317 #define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */
15318 #define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */
15319 #define LTDC_GCR_HSPOL_Pos           (31U)
15320 #define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */
15321 #define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
15322 
15323 /********************  Bit definition for LTDC_SRCR register  *****************/
15324 
15325 #define LTDC_SRCR_IMR_Pos            (0U)
15326 #define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */
15327 #define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */
15328 #define LTDC_SRCR_VBR_Pos            (1U)
15329 #define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */
15330 #define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
15331 
15332 /********************  Bit definition for LTDC_BCCR register  *****************/
15333 
15334 #define LTDC_BCCR_BCBLUE_Pos         (0U)
15335 #define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */
15336 #define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */
15337 #define LTDC_BCCR_BCGREEN_Pos        (8U)
15338 #define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */
15339 #define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
15340 #define LTDC_BCCR_BCRED_Pos          (16U)
15341 #define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */
15342 #define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */
15343 
15344 /********************  Bit definition for LTDC_IER register  ******************/
15345 
15346 #define LTDC_IER_LIE_Pos             (0U)
15347 #define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */
15348 #define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */
15349 #define LTDC_IER_FUIE_Pos            (1U)
15350 #define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */
15351 #define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */
15352 #define LTDC_IER_TERRIE_Pos          (2U)
15353 #define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */
15354 #define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */
15355 #define LTDC_IER_RRIE_Pos            (3U)
15356 #define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */
15357 #define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
15358 
15359 /********************  Bit definition for LTDC_ISR register  ******************/
15360 
15361 #define LTDC_ISR_LIF_Pos             (0U)
15362 #define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */
15363 #define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
15364 #define LTDC_ISR_FUIF_Pos            (1U)
15365 #define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */
15366 #define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
15367 #define LTDC_ISR_TERRIF_Pos          (2U)
15368 #define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */
15369 #define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
15370 #define LTDC_ISR_RRIF_Pos            (3U)
15371 #define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */
15372 #define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
15373 
15374 /********************  Bit definition for LTDC_ICR register  ******************/
15375 
15376 #define LTDC_ICR_CLIF_Pos            (0U)
15377 #define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */
15378 #define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
15379 #define LTDC_ICR_CFUIF_Pos           (1U)
15380 #define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */
15381 #define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
15382 #define LTDC_ICR_CTERRIF_Pos         (2U)
15383 #define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */
15384 #define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
15385 #define LTDC_ICR_CRRIF_Pos           (3U)
15386 #define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */
15387 #define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
15388 
15389 /********************  Bit definition for LTDC_LIPCR register  ****************/
15390 
15391 #define LTDC_LIPCR_LIPOS_Pos         (0U)
15392 #define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */
15393 #define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
15394 
15395 /********************  Bit definition for LTDC_CPSR register  *****************/
15396 
15397 #define LTDC_CPSR_CYPOS_Pos          (0U)
15398 #define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */
15399 #define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
15400 #define LTDC_CPSR_CXPOS_Pos          (16U)
15401 #define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */
15402 #define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
15403 
15404 /********************  Bit definition for LTDC_CDSR register  *****************/
15405 
15406 #define LTDC_CDSR_VDES_Pos           (0U)
15407 #define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */
15408 #define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */
15409 #define LTDC_CDSR_HDES_Pos           (1U)
15410 #define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */
15411 #define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */
15412 #define LTDC_CDSR_VSYNCS_Pos         (2U)
15413 #define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */
15414 #define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */
15415 #define LTDC_CDSR_HSYNCS_Pos         (3U)
15416 #define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */
15417 #define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
15418 
15419 /********************  Bit definition for LTDC_LxCR register  *****************/
15420 
15421 #define LTDC_LxCR_LEN_Pos            (0U)
15422 #define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */
15423 #define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */
15424 #define LTDC_LxCR_COLKEN_Pos         (1U)
15425 #define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */
15426 #define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */
15427 #define LTDC_LxCR_CLUTEN_Pos         (4U)
15428 #define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */
15429 #define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
15430 
15431 /********************  Bit definition for LTDC_LxWHPCR register  **************/
15432 
15433 #define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)
15434 #define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */
15435 #define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
15436 #define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)
15437 #define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)     /*!< 0x0FFF0000 */
15438 #define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */
15439 
15440 /********************  Bit definition for LTDC_LxWVPCR register  **************/
15441 
15442 #define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)
15443 #define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */
15444 #define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
15445 #define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)
15446 #define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)     /*!< 0x0FFF0000 */
15447 #define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */
15448 
15449 /********************  Bit definition for LTDC_LxCKCR register  ***************/
15450 
15451 #define LTDC_LxCKCR_CKBLUE_Pos       (0U)
15452 #define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */
15453 #define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */
15454 #define LTDC_LxCKCR_CKGREEN_Pos      (8U)
15455 #define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */
15456 #define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
15457 #define LTDC_LxCKCR_CKRED_Pos        (16U)
15458 #define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */
15459 #define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */
15460 
15461 /********************  Bit definition for LTDC_LxPFCR register  ***************/
15462 
15463 #define LTDC_LxPFCR_PF_Pos           (0U)
15464 #define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */
15465 #define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
15466 
15467 /********************  Bit definition for LTDC_LxCACR register  ***************/
15468 
15469 #define LTDC_LxCACR_CONSTA_Pos       (0U)
15470 #define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */
15471 #define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
15472 
15473 /********************  Bit definition for LTDC_LxDCCR register  ***************/
15474 
15475 #define LTDC_LxDCCR_DCBLUE_Pos       (0U)
15476 #define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */
15477 #define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */
15478 #define LTDC_LxDCCR_DCGREEN_Pos      (8U)
15479 #define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */
15480 #define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
15481 #define LTDC_LxDCCR_DCRED_Pos        (16U)
15482 #define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */
15483 #define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */
15484 #define LTDC_LxDCCR_DCALPHA_Pos      (24U)
15485 #define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */
15486 #define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
15487 
15488 /********************  Bit definition for LTDC_LxBFCR register  ***************/
15489 
15490 #define LTDC_LxBFCR_BF2_Pos          (0U)
15491 #define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */
15492 #define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
15493 #define LTDC_LxBFCR_BF1_Pos          (8U)
15494 #define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */
15495 #define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
15496 
15497 /********************  Bit definition for LTDC_LxCFBAR register  **************/
15498 
15499 #define LTDC_LxCFBAR_CFBADD_Pos      (0U)
15500 #define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
15501 #define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
15502 
15503 /********************  Bit definition for LTDC_LxCFBLR register  **************/
15504 
15505 #define LTDC_LxCFBLR_CFBLL_Pos       (0U)
15506 #define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */
15507 #define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */
15508 #define LTDC_LxCFBLR_CFBP_Pos        (16U)
15509 #define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */
15510 #define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
15511 
15512 /********************  Bit definition for LTDC_LxCFBLNR register  *************/
15513 
15514 #define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)
15515 #define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */
15516 #define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
15517 
15518 /********************  Bit definition for LTDC_LxCLUTWR register  *************/
15519 
15520 #define LTDC_LxCLUTWR_BLUE_Pos       (0U)
15521 #define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */
15522 #define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */
15523 #define LTDC_LxCLUTWR_GREEN_Pos      (8U)
15524 #define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */
15525 #define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */
15526 #define LTDC_LxCLUTWR_RED_Pos        (16U)
15527 #define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */
15528 #define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */
15529 #define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)
15530 #define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */
15531 #define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
15532 
15533 /******************************************************************************/
15534 /*                                                                            */
15535 /*                                 ICACHE                                     */
15536 /*                                                                            */
15537 /******************************************************************************/
15538 /******************  Bit definition for ICACHE_CR register  *******************/
15539 #define ICACHE_CR_EN_Pos                    (0U)
15540 #define ICACHE_CR_EN_Msk                    (0x1UL << ICACHE_CR_EN_Pos)             /*!< 0x00000001 */
15541 #define ICACHE_CR_EN                        ICACHE_CR_EN_Msk                        /*!< Enable */
15542 #define ICACHE_CR_CACHEINV_Pos              (1U)
15543 #define ICACHE_CR_CACHEINV_Msk              (0x1UL << ICACHE_CR_CACHEINV_Pos)       /*!< 0x00000002 */
15544 #define ICACHE_CR_CACHEINV                  ICACHE_CR_CACHEINV_Msk                  /*!< Cache invalidation */
15545 #define ICACHE_CR_WAYSEL_Pos                (2U)
15546 #define ICACHE_CR_WAYSEL_Msk                (0x1UL << ICACHE_CR_WAYSEL_Pos)         /*!< 0x00000004 */
15547 #define ICACHE_CR_WAYSEL                    ICACHE_CR_WAYSEL_Msk                    /*!< Ways selection */
15548 #define ICACHE_CR_HITMEN_Pos                (16U)
15549 #define ICACHE_CR_HITMEN_Msk                (0x1UL << ICACHE_CR_HITMEN_Pos)         /*!< 0x00010000 */
15550 #define ICACHE_CR_HITMEN                    ICACHE_CR_HITMEN_Msk                    /*!< Hit monitor enable */
15551 #define ICACHE_CR_MISSMEN_Pos               (17U)
15552 #define ICACHE_CR_MISSMEN_Msk               (0x1UL << ICACHE_CR_MISSMEN_Pos)        /*!< 0x00020000 */
15553 #define ICACHE_CR_MISSMEN                   ICACHE_CR_MISSMEN_Msk                   /*!< Miss monitor enable */
15554 #define ICACHE_CR_HITMRST_Pos               (18U)
15555 #define ICACHE_CR_HITMRST_Msk               (0x1UL << ICACHE_CR_HITMRST_Pos)        /*!< 0x00040000 */
15556 #define ICACHE_CR_HITMRST                   ICACHE_CR_HITMRST_Msk                   /*!< Hit monitor reset */
15557 #define ICACHE_CR_MISSMRST_Pos              (19U)
15558 #define ICACHE_CR_MISSMRST_Msk              (0x1UL << ICACHE_CR_MISSMRST_Pos)       /*!< 0x00080000 */
15559 #define ICACHE_CR_MISSMRST                  ICACHE_CR_MISSMRST_Msk                  /*!< Miss monitor reset */
15560 
15561 /******************  Bit definition for ICACHE_SR register  *******************/
15562 #define ICACHE_SR_BUSYF_Pos                 (0U)
15563 #define ICACHE_SR_BUSYF_Msk                 (0x1UL << ICACHE_SR_BUSYF_Pos)          /*!< 0x00000001 */
15564 #define ICACHE_SR_BUSYF                     ICACHE_SR_BUSYF_Msk                     /*!< Busy flag */
15565 #define ICACHE_SR_BSYENDF_Pos               (1U)
15566 #define ICACHE_SR_BSYENDF_Msk               (0x1UL << ICACHE_SR_BSYENDF_Pos)        /*!< 0x00000002 */
15567 #define ICACHE_SR_BSYENDF                   ICACHE_SR_BSYENDF_Msk                   /*!< Busy end flag */
15568 #define ICACHE_SR_ERRF_Pos                  (2U)
15569 #define ICACHE_SR_ERRF_Msk                  (0x1UL << ICACHE_SR_ERRF_Pos)           /*!< 0x00000004 */
15570 #define ICACHE_SR_ERRF                      ICACHE_SR_ERRF_Msk                      /*!< Cache error flag */
15571 
15572 /******************  Bit definition for ICACHE_IER register  ******************/
15573 #define ICACHE_IER_BSYENDIE_Pos             (1U)
15574 #define ICACHE_IER_BSYENDIE_Msk             (0x1UL << ICACHE_IER_BSYENDIE_Pos)      /*!< 0x00000002 */
15575 #define ICACHE_IER_BSYENDIE                 ICACHE_IER_BSYENDIE_Msk                 /*!< Busy end interrupt enable */
15576 #define ICACHE_IER_ERRIE_Pos                (2U)
15577 #define ICACHE_IER_ERRIE_Msk                (0x1UL << ICACHE_IER_ERRIE_Pos)         /*!< 0x00000004 */
15578 #define ICACHE_IER_ERRIE                    ICACHE_IER_ERRIE_Msk                    /*!< Cache error interrupt enable */
15579 
15580 /******************  Bit definition for ICACHE_FCR register  ******************/
15581 #define ICACHE_FCR_CBSYENDF_Pos             (1U)
15582 #define ICACHE_FCR_CBSYENDF_Msk             (0x1UL << ICACHE_FCR_CBSYENDF_Pos)      /*!< 0x00000002 */
15583 #define ICACHE_FCR_CBSYENDF                 ICACHE_FCR_CBSYENDF_Msk                 /*!< Busy end flag clear */
15584 #define ICACHE_FCR_CERRF_Pos                (2U)
15585 #define ICACHE_FCR_CERRF_Msk                (0x1UL << ICACHE_FCR_CERRF_Pos)         /*!< 0x00000004 */
15586 #define ICACHE_FCR_CERRF                    ICACHE_FCR_CERRF_Msk                    /*!< Cache error flag clear */
15587 
15588 /******************  Bit definition for ICACHE_HMONR register  ****************/
15589 #define ICACHE_HMONR_HITMON_Pos             (0U)
15590 #define ICACHE_HMONR_HITMON_Msk             (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */
15591 #define ICACHE_HMONR_HITMON                 ICACHE_HMONR_HITMON_Msk                 /*!< Cache hit monitor register */
15592 
15593 /******************  Bit definition for ICACHE_MMONR register  ****************/
15594 #define ICACHE_MMONR_MISSMON_Pos            (0U)
15595 #define ICACHE_MMONR_MISSMON_Msk            (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos)  /*!< 0x0000FFFF */
15596 #define ICACHE_MMONR_MISSMON                ICACHE_MMONR_MISSMON_Msk                /*!< Cache miss monitor register */
15597 
15598 /******************  Bit definition for ICACHE_CRRx register  *****************/
15599 #define ICACHE_CRRx_BASEADDR_Pos            (0U)
15600 #define ICACHE_CRRx_BASEADDR_Msk            (0xFFUL << ICACHE_CRRx_BASEADDR_Pos)    /*!< 0x000000FF */
15601 #define ICACHE_CRRx_BASEADDR                ICACHE_CRRx_BASEADDR_Msk                /*!< Base address of region X to remap */
15602 #define ICACHE_CRRx_RSIZE_Pos               (9U)
15603 #define ICACHE_CRRx_RSIZE_Msk               (0x7UL << ICACHE_CRRx_RSIZE_Pos)        /*!< 0x00000E00 */
15604 #define ICACHE_CRRx_RSIZE                   ICACHE_CRRx_RSIZE_Msk                   /*!< Region X size */
15605 #define ICACHE_CRRx_RSIZE_0                 (0x1UL << ICACHE_CRRx_RSIZE_Pos)        /*!< 0x00000200 */
15606 #define ICACHE_CRRx_RSIZE_1                 (0x2UL << ICACHE_CRRx_RSIZE_Pos)        /*!< 0x00000400 */
15607 #define ICACHE_CRRx_RSIZE_2                 (0x4UL << ICACHE_CRRx_RSIZE_Pos)        /*!< 0x00000800 */
15608 #define ICACHE_CRRx_REN_Pos                 (15U)
15609 #define ICACHE_CRRx_REN_Msk                 (0x1UL << ICACHE_CRRx_REN_Pos)          /*!< 0x00008000 */
15610 #define ICACHE_CRRx_REN                     ICACHE_CRRx_REN_Msk                     /*!< Region X enable */
15611 #define ICACHE_CRRx_REMAPADDR_Pos           (16U)
15612 #define ICACHE_CRRx_REMAPADDR_Msk           (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos)  /*!< 0x07FF0000 */
15613 #define ICACHE_CRRx_REMAPADDR               ICACHE_CRRx_REMAPADDR_Msk               /*!< Remap address of Region X to be remapped */
15614 #define ICACHE_CRRx_MSTSEL_Pos              (28U)
15615 #define ICACHE_CRRx_MSTSEL_Msk              (0x1UL << ICACHE_CRRx_MSTSEL_Pos)       /*!< 0x10000000 */
15616 #define ICACHE_CRRx_MSTSEL                  ICACHE_CRRx_MSTSEL_Msk                  /*!< Region X AHB cache master selection */
15617 #define ICACHE_CRRx_HBURST_Pos              (31U)
15618 #define ICACHE_CRRx_HBURST_Msk              (0x1UL << ICACHE_CRRx_HBURST_Pos)       /*!< 0x80000000 */
15619 #define ICACHE_CRRx_HBURST                  ICACHE_CRRx_HBURST_Msk                  /*!< Region X output burst type */
15620 
15621 /******************************************************************************/
15622 /*                                                                            */
15623 /*                                 DCACHE                                     */
15624 /*                                                                            */
15625 /******************************************************************************/
15626 /******************  Bit definition for DCACHE_CR register  *******************/
15627 #define DCACHE_CR_EN_Pos                    (0U)
15628 #define DCACHE_CR_EN_Msk                    (0x1UL << DCACHE_CR_EN_Pos)             /*!< 0x00000001 */
15629 #define DCACHE_CR_EN                        DCACHE_CR_EN_Msk                        /*!< Enable */
15630 #define DCACHE_CR_CACHEINV_Pos              (1U)
15631 #define DCACHE_CR_CACHEINV_Msk              (0x1UL << DCACHE_CR_CACHEINV_Pos)       /*!< 0x00000002 */
15632 #define DCACHE_CR_CACHEINV                  DCACHE_CR_CACHEINV_Msk                  /*!< Cache invalidation */
15633 #define DCACHE_CR_CACHECMD_Pos              (8U)
15634 #define DCACHE_CR_CACHECMD_Msk              (0x7UL << DCACHE_CR_CACHECMD_Pos)       /*!< 0x00000700 */
15635 #define DCACHE_CR_CACHECMD                  DCACHE_CR_CACHECMD_Msk                  /*!< Cache command */
15636 #define DCACHE_CR_CACHECMD_0                (0x1UL << DCACHE_CR_CACHECMD_Pos)       /*!< 0x00000100 */
15637 #define DCACHE_CR_CACHECMD_1                (0x2UL << DCACHE_CR_CACHECMD_Pos)       /*!< 0x00000200 */
15638 #define DCACHE_CR_CACHECMD_2                (0x4UL << DCACHE_CR_CACHECMD_Pos)       /*!< 0x00000400 */
15639 #define DCACHE_CR_STARTCMD_Pos              (11U)
15640 #define DCACHE_CR_STARTCMD_Msk              (0x1UL << DCACHE_CR_STARTCMD_Pos)       /*!< 0x00000800 */
15641 #define DCACHE_CR_STARTCMD                  DCACHE_CR_STARTCMD_Msk                  /*!< Start command */
15642 #define DCACHE_CR_RHITMEN_Pos               (16U)
15643 #define DCACHE_CR_RHITMEN_Msk               (0x1UL << DCACHE_CR_RHITMEN_Pos)        /*!< 0x00010000 */
15644 #define DCACHE_CR_RHITMEN                   DCACHE_CR_RHITMEN_Msk                   /*!< Read Hit monitor enable */
15645 #define DCACHE_CR_RMISSMEN_Pos              (17U)
15646 #define DCACHE_CR_RMISSMEN_Msk              (0x1UL << DCACHE_CR_RMISSMEN_Pos)       /*!< 0x00020000 */
15647 #define DCACHE_CR_RMISSMEN                  DCACHE_CR_RMISSMEN_Msk                  /*!< Read Miss monitor enable */
15648 #define DCACHE_CR_RHITMRST_Pos              (18U)
15649 #define DCACHE_CR_RHITMRST_Msk              (0x1UL << DCACHE_CR_RHITMRST_Pos)       /*!< 0x00040000 */
15650 #define DCACHE_CR_RHITMRST                  DCACHE_CR_RHITMRST_Msk                  /*!< Read Hit monitor reset */
15651 #define DCACHE_CR_RMISSMRST_Pos             (19U)
15652 #define DCACHE_CR_RMISSMRST_Msk             (0x1UL << DCACHE_CR_RMISSMRST_Pos)      /*!< 0x00080000 */
15653 #define DCACHE_CR_RMISSMRST                 DCACHE_CR_RMISSMRST_Msk                 /*!< Read Miss monitor reset */
15654 #define DCACHE_CR_WHITMEN_Pos               (20U)
15655 #define DCACHE_CR_WHITMEN_Msk               (0x1UL << DCACHE_CR_WHITMEN_Pos)        /*!< 0x00100000 */
15656 #define DCACHE_CR_WHITMEN                   DCACHE_CR_WHITMEN_Msk                   /*!< Write Hit monitor enable */
15657 #define DCACHE_CR_WMISSMEN_Pos              (21U)
15658 #define DCACHE_CR_WMISSMEN_Msk              (0x1UL << DCACHE_CR_WMISSMEN_Pos)       /*!< 0x00200000 */
15659 #define DCACHE_CR_WMISSMEN                  DCACHE_CR_WMISSMEN_Msk                  /*!< Write Miss monitor enable */
15660 #define DCACHE_CR_WHITMRST_Pos              (22U)
15661 #define DCACHE_CR_WHITMRST_Msk              (0x1UL << DCACHE_CR_WHITMRST_Pos)       /*!< 0x00400000 */
15662 #define DCACHE_CR_WHITMRST                  DCACHE_CR_WHITMRST_Msk                  /*!< Write Hit monitor reset */
15663 #define DCACHE_CR_WMISSMRST_Pos             (23U)
15664 #define DCACHE_CR_WMISSMRST_Msk             (0x1UL << DCACHE_CR_WMISSMRST_Pos)      /*!< 0x00800000 */
15665 #define DCACHE_CR_WMISSMRST                 DCACHE_CR_WMISSMRST_Msk                 /*!< Write Miss monitor reset */
15666 #define DCACHE_CR_HBURST_Pos                (31U)
15667 #define DCACHE_CR_HBURST_Msk                (0x1UL << DCACHE_CR_HBURST_Pos)         /*!< 0x80000000 */
15668 #define DCACHE_CR_HBURST                    DCACHE_CR_HBURST_Msk                    /*!< Read burst type */
15669 
15670 /******************  Bit definition for DCACHE_SR register  *******************/
15671 #define DCACHE_SR_BUSYF_Pos                 (0U)
15672 #define DCACHE_SR_BUSYF_Msk                 (0x1UL << DCACHE_SR_BUSYF_Pos)          /*!< 0x00000001 */
15673 #define DCACHE_SR_BUSYF                     DCACHE_SR_BUSYF_Msk                     /*!< Busy flag */
15674 #define DCACHE_SR_BSYENDF_Pos               (1U)
15675 #define DCACHE_SR_BSYENDF_Msk               (0x1UL << DCACHE_SR_BSYENDF_Pos)        /*!< 0x00000002 */
15676 #define DCACHE_SR_BSYENDF                   DCACHE_SR_BSYENDF_Msk                   /*!< Busy end flag */
15677 #define DCACHE_SR_ERRF_Pos                  (2U)
15678 #define DCACHE_SR_ERRF_Msk                  (0x1UL << DCACHE_SR_ERRF_Pos)           /*!< 0x00000004 */
15679 #define DCACHE_SR_ERRF                      DCACHE_SR_ERRF_Msk                      /*!< Cache error flag */
15680 #define DCACHE_SR_BUSYCMDF_Pos              (3U)
15681 #define DCACHE_SR_BUSYCMDF_Msk              (0x1UL << DCACHE_SR_BUSYCMDF_Pos)       /*!< 0x00000008 */
15682 #define DCACHE_SR_BUSYCMDF                  DCACHE_SR_BUSYCMDF_Msk                  /*!< Busy command flag */
15683 #define DCACHE_SR_CMDENDF_Pos               (4U)
15684 #define DCACHE_SR_CMDENDF_Msk               (0x1UL << DCACHE_SR_CMDENDF_Pos)        /*!< 0x00000010 */
15685 #define DCACHE_SR_CMDENDF                   DCACHE_SR_CMDENDF_Msk                   /*!< Command end flag */
15686 
15687 /******************  Bit definition for DCACHE_IER register  ******************/
15688 #define DCACHE_IER_BSYENDIE_Pos             (1U)
15689 #define DCACHE_IER_BSYENDIE_Msk             (0x1UL << DCACHE_IER_BSYENDIE_Pos)      /*!< 0x00000002 */
15690 #define DCACHE_IER_BSYENDIE                 DCACHE_IER_BSYENDIE_Msk                 /*!< Busy end interrupt enable */
15691 #define DCACHE_IER_ERRIE_Pos                (2U)
15692 #define DCACHE_IER_ERRIE_Msk                (0x1UL << DCACHE_IER_ERRIE_Pos)         /*!< 0x00000004 */
15693 #define DCACHE_IER_ERRIE                    DCACHE_IER_ERRIE_Msk                    /*!< Cache error interrupt enable */
15694 #define DCACHE_IER_CMDENDIE_Pos             (4U)
15695 #define DCACHE_IER_CMDENDIE_Msk             (0x1UL << DCACHE_IER_CMDENDIE_Pos)      /*!< 0x00000010 */
15696 #define DCACHE_IER_CMDENDIE                 DCACHE_IER_CMDENDIE_Msk                 /*!< Command end interrupt enable */
15697 
15698 /******************  Bit definition for DCACHE_FCR register  ******************/
15699 #define DCACHE_FCR_CBSYENDF_Pos             (1U)
15700 #define DCACHE_FCR_CBSYENDF_Msk             (0x1UL << DCACHE_FCR_CBSYENDF_Pos)       /*!< 0x00000002 */
15701 #define DCACHE_FCR_CBSYENDF                 DCACHE_FCR_CBSYENDF_Msk                  /*!< Busy end flag clear */
15702 #define DCACHE_FCR_CERRF_Pos                (2U)
15703 #define DCACHE_FCR_CERRF_Msk                (0x1UL << DCACHE_FCR_CERRF_Pos)          /*!< 0x00000004 */
15704 #define DCACHE_FCR_CERRF                    DCACHE_FCR_CERRF_Msk                     /*!< Cache error flag clear */
15705 #define DCACHE_FCR_CCMDENDF_Pos             (4U)
15706 #define DCACHE_FCR_CCMDENDF_Msk             (0x1UL << DCACHE_FCR_CCMDENDF_Pos)       /*!< 0x00000010 */
15707 #define DCACHE_FCR_CCMDENDF                 DCACHE_FCR_CCMDENDF_Msk                  /*!< Command end flag clear */
15708 
15709 /******************  Bit definition for DCACHE_RHMONR register  ****************/
15710 #define DCACHE_RHMONR_RHITMON_Pos           (0U)
15711 #define DCACHE_RHMONR_RHITMON_Msk           (0xFFFFFFFFUL << DCACHE_RHMONR_RHITMON_Pos) /*!< 0xFFFFFFFF */
15712 #define DCACHE_RHMONR_RHITMON               DCACHE_RHMONR_RHITMON_Msk               /*!< Cache Read hit monitor register */
15713 
15714 /******************  Bit definition for DCACHE_RMMONR register  ****************/
15715 #define DCACHE_RMMONR_RMISSMON_Pos          (0U)
15716 #define DCACHE_RMMONR_RMISSMON_Msk          (0xFFFFUL << DCACHE_RMMONR_RMISSMON_Pos) /*!< 0x0000FFFF */
15717 #define DCACHE_RMMONR_RMISSMON              DCACHE_RMMONR_RMISSMON_Msk              /*!< Cache Read miss monitor register */
15718 
15719 /******************  Bit definition for DCACHE_WHMONR register  ****************/
15720 #define DCACHE_WHMONR_WHITMON_Pos           (0U)
15721 #define DCACHE_WHMONR_WHITMON_Msk           (0xFFFFFFFFUL << DCACHE_WHMONR_WHITMON_Pos) /*!< 0xFFFFFFFF */
15722 #define DCACHE_WHMONR_WHITMON               DCACHE_WHMONR_WHITMON_Msk               /*!< Cache Read hit monitor register */
15723 
15724 /******************  Bit definition for DCACHE_WMMONR register  ****************/
15725 #define DCACHE_WMMONR_WMISSMON_Pos          (0U)
15726 #define DCACHE_WMMONR_WMISSMON_Msk          (0xFFFFUL << DCACHE_WMMONR_WMISSMON_Pos) /*!< 0x0000FFFF */
15727 #define DCACHE_WMMONR_WMISSMON              DCACHE_WMMONR_WMISSMON_Msk              /*!< Cache Read miss monitor register */
15728 
15729 /******************  Bit definition for DCACHE_CMDRSADDRR register  ****************/
15730 #define DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos  (0U)
15731 #define DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk  (0xFFFFFFE0UL << DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFE0 */
15732 #define DCACHE_CMDRSADDRR_CMDSTARTADDR      DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk      /*!< Command start address */
15733 
15734 /******************  Bit definition for DCACHE_CMDREADDRR register  ****************/
15735 #define DCACHE_CMDREADDRR_CMDENDADDR_Pos    (0U)
15736 #define DCACHE_CMDREADDRR_CMDENDADDR_Msk    (0xFFFFFFE0UL << DCACHE_CMDREADDRR_CMDENDADDR_Pos) /*!< 0xFFFFFFE0 */
15737 #define DCACHE_CMDREADDRR_CMDENDADDR        DCACHE_CMDREADDRR_CMDENDADDR_Msk        /*!< Command end address */
15738 
15739 /******************************************************************************/
15740 /*                                                                            */
15741 /*                      Analog Comparators (COMP)                             */
15742 /*                                                                            */
15743 /******************************************************************************/
15744 
15745 #define COMP_WINDOW_MODE_SUPPORT  /*!< COMP feature available only on specific devices */
15746 
15747 /**********************  Bit definition for COMP_CSR register  ****************/
15748 #define COMP_CSR_EN_Pos                     (0U)
15749 #define COMP_CSR_EN_Msk                     (0x1UL << COMP_CSR_EN_Pos)              /*!< 0x00000001 */
15750 #define COMP_CSR_EN                         COMP_CSR_EN_Msk                         /*!< Comparator enable */
15751 #define COMP_CSR_INMSEL_Pos                 (4U)
15752 #define COMP_CSR_INMSEL_Msk                 (0xFUL << COMP_CSR_INMSEL_Pos)          /*!< 0x000000F0 */
15753 #define COMP_CSR_INMSEL                     COMP_CSR_INMSEL_Msk                     /*!< Comparator input minus selection */
15754 #define COMP_CSR_INMSEL_0                   (0x1UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00000010 */
15755 #define COMP_CSR_INMSEL_1                   (0x2UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00000020 */
15756 #define COMP_CSR_INMSEL_2                   (0x4UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00000040 */
15757 #define COMP_CSR_INMSEL_3                   (0x8UL << COMP_CSR_INMSEL_Pos)          /*!< 0x00000080 */
15758 #define COMP_CSR_INPSEL_Pos                 (8U)
15759 #define COMP_CSR_INPSEL_Msk                 (0x3UL << COMP_CSR_INPSEL_Pos)          /*!< 0x00000300 */
15760 #define COMP_CSR_INPSEL                     COMP_CSR_INPSEL_Msk                     /*!< Comparator input plus selection */
15761 #define COMP_CSR_INPSEL_0                   (0x1UL << COMP_CSR_INPSEL_Pos)          /*!< 0x00000100 */
15762 #define COMP_CSR_INPSEL_1                   (0x2UL << COMP_CSR_INPSEL_Pos)          /*!< 0x00000200 */
15763 #define COMP_CSR_WINMODE_Pos                (11U)
15764 #define COMP_CSR_WINMODE_Msk                (0x1UL << COMP_CSR_WINMODE_Pos)         /*!< 0x00000800 */
15765 #define COMP_CSR_WINMODE                    COMP_CSR_WINMODE_Msk                    /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
15766 #define COMP_CSR_WINOUT_Pos                 (14U)
15767 #define COMP_CSR_WINOUT_Msk                 (0x1UL << COMP_CSR_WINOUT_Pos)          /*!< 0x00004000 */
15768 #define COMP_CSR_WINOUT                     COMP_CSR_WINOUT_Msk                     /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
15769 #define COMP_CSR_POLARITY_Pos               (15U)
15770 #define COMP_CSR_POLARITY_Msk               (0x1UL << COMP_CSR_POLARITY_Pos)        /*!< 0x00008000 */
15771 #define COMP_CSR_POLARITY                   COMP_CSR_POLARITY_Msk                   /*!< Comparator output polarity */
15772 #define COMP_CSR_HYST_Pos                   (16U)
15773 #define COMP_CSR_HYST_Msk                   (0x3UL << COMP_CSR_HYST_Pos)            /*!< 0x00030000 */
15774 #define COMP_CSR_HYST                       COMP_CSR_HYST_Msk                       /*!< Comparator input hysteresis */
15775 #define COMP_CSR_HYST_0                     (0x1UL << COMP_CSR_HYST_Pos)            /*!< 0x00010000 */
15776 #define COMP_CSR_HYST_1                     (0x2UL << COMP_CSR_HYST_Pos)            /*!< 0x00020000 */
15777 #define COMP_CSR_PWRMODE_Pos                (18U)
15778 #define COMP_CSR_PWRMODE_Msk                (0x3UL << COMP_CSR_PWRMODE_Pos)         /*!< 0x000C0000 */
15779 #define COMP_CSR_PWRMODE                    COMP_CSR_PWRMODE_Msk                    /*!< Comparator power mode */
15780 #define COMP_CSR_PWRMODE_0                  (0x1UL << COMP_CSR_PWRMODE_Pos)         /*!< 0x00040000 */
15781 #define COMP_CSR_PWRMODE_1                  (0x2UL << COMP_CSR_PWRMODE_Pos)         /*!< 0x00080000 */
15782 #define COMP_CSR_BLANKSEL_Pos               (20U)
15783 #define COMP_CSR_BLANKSEL_Msk               (0x1FUL << COMP_CSR_BLANKSEL_Pos)       /*!< 0x01F00000 */
15784 #define COMP_CSR_BLANKSEL                   COMP_CSR_BLANKSEL_Msk                   /*!< Comparator blanking source */
15785 #define COMP_CSR_BLANKSEL_0                 (0x01UL << COMP_CSR_BLANKSEL_Pos)       /*!< 0x00100000 */
15786 #define COMP_CSR_BLANKSEL_1                 (0x02UL << COMP_CSR_BLANKSEL_Pos)       /*!< 0x00200000 */
15787 #define COMP_CSR_BLANKSEL_2                 (0x04UL << COMP_CSR_BLANKSEL_Pos)       /*!< 0x00400000 */
15788 #define COMP_CSR_BLANKSEL_3                 (0x08UL << COMP_CSR_BLANKSEL_Pos)       /*!< 0x00800000 */
15789 #define COMP_CSR_BLANKSEL_4                 (0x10UL << COMP_CSR_BLANKSEL_Pos)       /*!< 0x01000000 */
15790 #define COMP_CSR_VALUE_Pos                  (30U)
15791 #define COMP_CSR_VALUE_Msk                  (0x1UL << COMP_CSR_VALUE_Pos)           /*!< 0x40000000 */
15792 #define COMP_CSR_VALUE                      COMP_CSR_VALUE_Msk                      /*!< Comparator output level */
15793 #define COMP_CSR_LOCK_Pos                   (31U)
15794 #define COMP_CSR_LOCK_Msk                   (0x1UL << COMP_CSR_LOCK_Pos)            /*!< 0x80000000 */
15795 #define COMP_CSR_LOCK                       COMP_CSR_LOCK_Msk                       /*!< Comparator lock */
15796 
15797 /******************************************************************************/
15798 /*                                                                            */
15799 /*                         Operational Amplifier (OPAMP)                      */
15800 /*                                                                            */
15801 /******************************************************************************/
15802 /*********************  Bit definition for OPAMPx_CSR register  ***************/
15803 #define OPAMP_CSR_OPAEN_Pos                 (0U)
15804 #define OPAMP_CSR_OPAEN_Msk                 (0x1UL << OPAMP_CSR_OPAEN_Pos)            /*!< 0x00000001 */
15805 #define OPAMP_CSR_OPAEN                     OPAMP_CSR_OPAEN_Msk                       /*!< OPAMP enable */
15806 #define OPAMP_CSR_OPALPM_Pos                (1U)
15807 #define OPAMP_CSR_OPALPM_Msk                (0x1UL << OPAMP_CSR_OPALPM_Pos)           /*!< 0x00000002 */
15808 #define OPAMP_CSR_OPALPM                    OPAMP_CSR_OPALPM_Msk                      /*!< Operational amplifier Low Power Mode */
15809 #define OPAMP_CSR_OPAMODE_Pos               (2U)
15810 #define OPAMP_CSR_OPAMODE_Msk               (0x3UL << OPAMP_CSR_OPAMODE_Pos)          /*!< 0x0000000C */
15811 #define OPAMP_CSR_OPAMODE                   OPAMP_CSR_OPAMODE_Msk                     /*!< Operational amplifier PGA mode */
15812 #define OPAMP_CSR_OPAMODE_0                 (0x1UL << OPAMP_CSR_OPAMODE_Pos)          /*!< 0x00000004 */
15813 #define OPAMP_CSR_OPAMODE_1                 (0x2UL << OPAMP_CSR_OPAMODE_Pos)          /*!< 0x00000008 */
15814 #define OPAMP_CSR_PGA_GAIN_Pos              (4U)
15815 #define OPAMP_CSR_PGA_GAIN_Msk              (0x3UL << OPAMP_CSR_PGA_GAIN_Pos)         /*!< 0x00000030 */
15816 #define OPAMP_CSR_PGA_GAIN                  OPAMP_CSR_PGA_GAIN_Msk                    /*!< Operational amplifier Programmable amplifier gain value */
15817 #define OPAMP_CSR_PGA_GAIN_0                (0x1UL << OPAMP_CSR_PGA_GAIN_Pos)         /*!< 0x00000010 */
15818 #define OPAMP_CSR_PGA_GAIN_1                (0x2UL << OPAMP_CSR_PGA_GAIN_Pos)         /*!< 0x00000020 */
15819 #define OPAMP_CSR_VM_SEL_Pos                (8U)
15820 #define OPAMP_CSR_VM_SEL_Msk                (0x3UL << OPAMP_CSR_VM_SEL_Pos)           /*!< 0x00000300 */
15821 #define OPAMP_CSR_VM_SEL                    OPAMP_CSR_VM_SEL_Msk                      /*!< Inverting input selection */
15822 #define OPAMP_CSR_VM_SEL_0                  (0x1UL << OPAMP_CSR_VM_SEL_Pos)           /*!< 0x00000100 */
15823 #define OPAMP_CSR_VM_SEL_1                  (0x2UL << OPAMP_CSR_VM_SEL_Pos)           /*!< 0x00000200 */
15824 #define OPAMP_CSR_VP_SEL_Pos                (10U)
15825 #define OPAMP_CSR_VP_SEL_Msk                (0x1UL << OPAMP_CSR_VP_SEL_Pos)           /*!< 0x00000400 */
15826 #define OPAMP_CSR_VP_SEL                    OPAMP_CSR_VP_SEL_Msk                      /*!< Non inverted input selection */
15827 #define OPAMP_CSR_CALON_Pos                 (12U)
15828 #define OPAMP_CSR_CALON_Msk                 (0x1UL << OPAMP_CSR_CALON_Pos)            /*!< 0x00001000 */
15829 #define OPAMP_CSR_CALON                     OPAMP_CSR_CALON_Msk                       /*!< Calibration mode enable */
15830 #define OPAMP_CSR_CALSEL_Pos                (13U)
15831 #define OPAMP_CSR_CALSEL_Msk                (0x1UL << OPAMP_CSR_CALSEL_Pos)           /*!< 0x00002000 */
15832 #define OPAMP_CSR_CALSEL                    OPAMP_CSR_CALSEL_Msk                      /*!< Calibration selection */
15833 #define OPAMP_CSR_USERTRIM_Pos              (14U)
15834 #define OPAMP_CSR_USERTRIM_Msk              (0x1UL << OPAMP_CSR_USERTRIM_Pos)         /*!< 0x00004000 */
15835 #define OPAMP_CSR_USERTRIM                  OPAMP_CSR_USERTRIM_Msk                    /*!< User trimming enable */
15836 #define OPAMP_CSR_CALOUT_Pos                (15U)
15837 #define OPAMP_CSR_CALOUT_Msk                (0x1UL << OPAMP_CSR_CALOUT_Pos)           /*!< 0x00008000 */
15838 #define OPAMP_CSR_CALOUT                    OPAMP_CSR_CALOUT_Msk                      /*!< Operational amplifier calibration output */
15839 #define OPAMP_CSR_HSM_Pos                   (30U)
15840 #define OPAMP_CSR_HSM_Msk                   (0x1UL << OPAMP_CSR_HSM_Pos)              /*!< 0x40000000 */
15841 #define OPAMP_CSR_HSM                       OPAMP_CSR_HSM_Msk                         /*!< Operational amplifier high speed mode */
15842 #define OPAMP_CSR_OPARANGE_Pos              (31U)
15843 #define OPAMP_CSR_OPARANGE_Msk              (0x1UL << OPAMP_CSR_OPARANGE_Pos)         /*!< 0x80000000 */
15844 #define OPAMP_CSR_OPARANGE                  OPAMP_CSR_OPARANGE_Msk                    /*!< Operational amplifier range setting */
15845 
15846 /*******************  Bit definition for OPAMPx_OTR register  ******************/
15847 #define OPAMP_OTR_TRIMOFFSETN_Pos           (0U)
15848 #define OPAMP_OTR_TRIMOFFSETN_Msk           (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)     /*!< 0x0000001F */
15849 #define OPAMP_OTR_TRIMOFFSETN               OPAMP_OTR_TRIMOFFSETN_Msk                 /*!< Trim for NMOS differential pairs */
15850 #define OPAMP_OTR_TRIMOFFSETP_Pos           (8U)
15851 #define OPAMP_OTR_TRIMOFFSETP_Msk           (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)     /*!< 0x00001F00 */
15852 #define OPAMP_OTR_TRIMOFFSETP               OPAMP_OTR_TRIMOFFSETP_Msk                 /*!< Trim for PMOS differential pairs */
15853 
15854 /*******************  Bit definition for OPAMPx_LPOTR register  ****************/
15855 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos       (0U)
15856 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk       (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
15857 #define OPAMP_LPOTR_TRIMLPOFFSETN           OPAMP_LPOTR_TRIMLPOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
15858 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos       (8U)
15859 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk       (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
15860 #define OPAMP_LPOTR_TRIMLPOFFSETP           OPAMP_LPOTR_TRIMLPOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
15861 
15862 /******************************************************************************/
15863 /*                                                                            */
15864 /*                                 MDF/ADF                                    */
15865 /*                                                                            */
15866 /******************************************************************************/
15867 /*******************  Bit definition for MDF/ADF_GCR register  ********************/
15868 #define MDF_GCR_TRGO_Pos                    (0U)
15869 #define MDF_GCR_TRGO_Msk                    (0x1UL << MDF_GCR_TRGO_Pos)             /*!< 0x00000001 */
15870 #define MDF_GCR_TRGO                        MDF_GCR_TRGO_Msk                        /*!<Trigger output control */
15871 #define MDF_GCR_ILVNB_Pos                   (4U)
15872 #define MDF_GCR_ILVNB_Msk                   (0xFUL << MDF_GCR_ILVNB_Pos)            /*!< 0x000000F0 */
15873 #define MDF_GCR_ILVNB                       MDF_GCR_ILVNB_Msk                       /*!< Interleaved Number */
15874 
15875 /*******************  Bit definition for MDF/ADF_CKGCR register  ********************/
15876 #define MDF_CKGCR_CKDEN_Pos                 (0U)
15877 #define MDF_CKGCR_CKDEN_Msk                 (0x1UL << MDF_CKGCR_CKDEN_Pos)          /*!< 0x00000001 */
15878 #define MDF_CKGCR_CKDEN                     MDF_CKGCR_CKDEN_Msk                     /*!<CKGEN diveders enable */
15879 #define MDF_CKGCR_CCK0EN_Pos                (1U)
15880 #define MDF_CKGCR_CCK0EN_Msk                (0x1UL << MDF_CKGCR_CCK0EN_Pos)         /*!< 0x00000002 */
15881 #define MDF_CKGCR_CCK0EN                    MDF_CKGCR_CCK0EN_Msk                    /*!<CCK0 clock enable */
15882 #define MDF_CKGCR_CCK1EN_Pos                (2U)
15883 #define MDF_CKGCR_CCK1EN_Msk                (0x1UL << MDF_CKGCR_CCK1EN_Pos)         /*!< 0x00000004 */
15884 #define MDF_CKGCR_CCK1EN                    MDF_CKGCR_CCK1EN_Msk                    /*!<CCK1 clock enable */
15885 #define MDF_CKGCR_CKGMOD_Pos                (4U)
15886 #define MDF_CKGCR_CKGMOD_Msk                (0x1UL << MDF_CKGCR_CKGMOD_Pos)         /*!< 0x00000010 */
15887 #define MDF_CKGCR_CKGMOD                    MDF_CKGCR_CKGMOD_Msk                    /*!<Clock genartor mode */
15888 #define MDF_CKGCR_CCK0DIR_Pos               (5U)
15889 #define MDF_CKGCR_CCK0DIR_Msk               (0x1UL << MDF_CKGCR_CCK0DIR_Pos)        /*!< 0x00000020 */
15890 #define MDF_CKGCR_CCK0DIR                   MDF_CKGCR_CCK0DIR_Msk                   /*!<CCK0 clock direction */
15891 #define MDF_CKGCR_CCK1DIR_Pos               (6U)
15892 #define MDF_CKGCR_CCK1DIR_Msk               (0x1UL << MDF_CKGCR_CCK1DIR_Pos)        /*!< 0x00000040 */
15893 #define MDF_CKGCR_CCK1DIR                   MDF_CKGCR_CCK1DIR_Msk                   /*!<CCK1 clock direction */
15894 #define MDF_CKGCR_TRGSENS_Pos               (8U)
15895 #define MDF_CKGCR_TRGSENS_Msk               (0x1UL << MDF_CKGCR_TRGSENS_Pos)        /*!< 0x00000100 */
15896 #define MDF_CKGCR_TRGSENS                   MDF_CKGCR_TRGSENS_Msk                   /*!<CKGEN trigger sensitivity selection */
15897 #define MDF_CKGCR_TRGSRC_Pos                (12U)
15898 #define MDF_CKGCR_TRGSRC_Msk                (0xFUL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x0000F000 */
15899 #define MDF_CKGCR_TRGSRC                    MDF_CKGCR_TRGSRC_Msk                    /*!<Digital Filter trigger signal selection */
15900 #define MDF_CKGCR_TRGSRC_0                  (0x1UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00001000 */
15901 #define MDF_CKGCR_TRGSRC_1                  (0x2UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00002000 */
15902 #define MDF_CKGCR_TRGSRC_2                  (0x4UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00004000 */
15903 #define MDF_CKGCR_TRGSRC_3                  (0x8UL << MDF_CKGCR_TRGSRC_Pos)         /*!< 0x00008000 */
15904 #define MDF_CKGCR_CCKDIV_Pos                (16U)
15905 #define MDF_CKGCR_CCKDIV_Msk                (0xFUL << MDF_CKGCR_CCKDIV_Pos)         /*!< 0x000F0000 */
15906 #define MDF_CKGCR_CCKDIV                    MDF_CKGCR_CCKDIV_Msk                    /*!<Divider to control the MDF_CCK clock */
15907 #define MDF_CKGCR_PROCDIV_Pos               (24U)
15908 #define MDF_CKGCR_PROCDIV_Msk               (0x7FUL << MDF_CKGCR_PROCDIV_Pos)       /*!< 0x7F000000 */
15909 #define MDF_CKGCR_PROCDIV                   MDF_CKGCR_PROCDIV_Msk                   /*!<Divider to control the serial interface clock */
15910 #define MDF_CKGCR_CCKACTIVE_Pos             (31U)
15911 #define MDF_CKGCR_CCKACTIVE_Msk             (0x1UL << MDF_CKGCR_CCKACTIVE_Pos)      /*!< 0x80000000 */
15912 #define MDF_CKGCR_CCKACTIVE                 MDF_CKGCR_CCKACTIVE_Msk                 /*!<Clock generator active flag */
15913 
15914 /*******************  Bit definition for MDF/ADF_OR register  ********************/
15915 #define MDF_OR_OPTION_Pos                   (0U)
15916 #define MDF_OR_OPTION_Msk                   (0xFFFFFFFFUL << MDF_OR_OPTION_Pos)     /*!< 0xFFFFFFFF */
15917 #define MDF_OR_OPTION                       MDF_OR_OPTION_Msk                       /*!<Option Control Bits */
15918 
15919 /*******************  Bit definition for MDF/ADF_SITFxCR register  ********************/
15920 #define MDF_SITFCR_SITFEN_Pos               (0U)
15921 #define MDF_SITFCR_SITFEN_Msk               (0x1UL << MDF_SITFCR_SITFEN_Pos)        /*!< 0x00000001 */
15922 #define MDF_SITFCR_SITFEN                   MDF_SITFCR_SITFEN_Msk                   /*!<Serial interface enable */
15923 #define MDF_SITFCR_SCKSRC_Pos               (1U)
15924 #define MDF_SITFCR_SCKSRC_Msk               (0x3UL << MDF_SITFCR_SCKSRC_Pos)        /*!< 0x00000006 */
15925 #define MDF_SITFCR_SCKSRC                   MDF_SITFCR_SCKSRC_Msk                   /*!<Serial clock source */
15926 #define MDF_SITFCR_SCKSRC_0                 (0x1UL << MDF_SITFCR_SCKSRC_Pos)
15927 #define MDF_SITFCR_SCKSRC_1                 (0x2UL << MDF_SITFCR_SCKSRC_Pos)
15928 #define MDF_SITFCR_SITFMOD_Pos              (4U)
15929 #define MDF_SITFCR_SITFMOD_Msk              (0x3UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000030 */
15930 #define MDF_SITFCR_SITFMOD                  MDF_SITFCR_SITFMOD_Msk                  /*!<Serial interface type */
15931 #define MDF_SITFCR_SITFMOD_0                (0x1UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000010 */
15932 #define MDF_SITFCR_SITFMOD_1                (0x2UL << MDF_SITFCR_SITFMOD_Pos)       /*!< 0x00000020 */
15933 #define MDF_SITFCR_STH_Pos                  (8U)
15934 #define MDF_SITFCR_STH_Msk                  (0x1FUL << MDF_SITFCR_STH_Pos)          /*!< 0x00001F00 */
15935 #define MDF_SITFCR_STH                      MDF_SITFCR_STH_Msk                      /*!<Manchester Symbol threshold / SPI threshold */
15936 #define MDF_SITFCR_SITFACTIVE_Pos           (31U)
15937 #define MDF_SITFCR_SITFACTIVE_Msk           (0x1UL << MDF_SITFCR_SITFACTIVE_Pos)    /*!< 0x80000000 */
15938 #define MDF_SITFCR_SITFACTIVE               MDF_SITFCR_SITFACTIVE_Msk               /*!<Serial interface active flag */
15939 
15940 /*******************  Bit definition for MDF/ADF_BSMXxCR register  ********************/
15941 #define MDF_BSMXCR_BSSEL_Pos                (0U)
15942 #define MDF_BSMXCR_BSSEL_Msk                (0x1FUL << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x0000001F */
15943 #define MDF_BSMXCR_BSSEL                    MDF_BSMXCR_BSSEL_Msk                    /*!<Bit Streal selection */
15944 #define MDF_BSMXCR_BSSEL_0                  (0x1UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000001 */
15945 #define MDF_BSMXCR_BSSEL_1                  (0x2UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000002 */
15946 #define MDF_BSMXCR_BSSEL_2                  (0x4UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000004 */
15947 #define MDF_BSMXCR_BSSEL_3                  (0x8UL  << MDF_BSMXCR_BSSEL_Pos)        /*!< 0x00000008 */
15948 #define MDF_BSMXCR_BSSEL_4                  (0x10UL  << MDF_BSMXCR_BSSEL_Pos)       /*!< 0x00000010 */
15949 #define MDF_BSMXCR_BSMXACTIVATE_Pos         (31U)
15950 #define MDF_BSMXCR_BSMXACTIVATE_Msk         (0x1UL << MDF_BSMXCR_BSMXACTIVATE_Pos)  /*!< 0x80000000 */
15951 #define MDF_BSMXCR_BSMXACTIVATE             MDF_BSMXCR_BSMXACTIVATE_Msk             /*!<Bit Streal activation flag */
15952 
15953 /*******************  Bit definition for MDF/ADF_DFLTxCR register  ********************/
15954 #define MDF_DFLTCR_DFLTEN_Pos               (0U)
15955 #define MDF_DFLTCR_DFLTEN_Msk               (0x1UL << MDF_DFLTCR_DFLTEN_Pos)        /*!< 0x00000001 */
15956 #define MDF_DFLTCR_DFLTEN                   MDF_DFLTCR_DFLTEN_Msk                   /*!<Digital filter enable */
15957 #define MDF_DFLTCR_DMAEN_Pos                (1U)
15958 #define MDF_DFLTCR_DMAEN_Msk                (0x1UL << MDF_DFLTCR_DMAEN_Pos)         /*!< 0x00000002 */
15959 #define MDF_DFLTCR_DMAEN                    MDF_DFLTCR_DMAEN_Msk                    /*!<DMA request enable */
15960 #define MDF_DFLTCR_FTH_Pos                  (2U)
15961 #define MDF_DFLTCR_FTH_Msk                  (0x1UL << MDF_DFLTCR_FTH_Pos)           /*!< 0x00000004 */
15962 #define MDF_DFLTCR_FTH                      MDF_DFLTCR_FTH_Msk                      /*!<RXFIFO Threshold selection */
15963 #define MDF_DFLTCR_ACQMOD_Pos               (4U)
15964 #define MDF_DFLTCR_ACQMOD_Msk               (0x7UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000004 */
15965 #define MDF_DFLTCR_ACQMOD                   MDF_DFLTCR_ACQMOD_Msk                   /*!<Digital filter trigger mode */
15966 #define MDF_DFLTCR_ACQMOD_0                 (0x1UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000010 */
15967 #define MDF_DFLTCR_ACQMOD_1                 (0x2UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000020 */
15968 #define MDF_DFLTCR_ACQMOD_2                 (0x4UL << MDF_DFLTCR_ACQMOD_Pos)        /*!< 0x00000040 */
15969 #define MDF_DFLTCR_TRGSENS_Pos              (8U)
15970 #define MDF_DFLTCR_TRGSENS_Msk              (0x1UL << MDF_DFLTCR_TRGSENS_Pos)       /*!< 0x00000004 */
15971 #define MDF_DFLTCR_TRGSENS                  MDF_DFLTCR_TRGSENS_Msk                  /*!<Digital filter trigger sensitivity selection */
15972 #define MDF_DFLTCR_TRGSRC_Pos               (12U)
15973 #define MDF_DFLTCR_TRGSRC_Msk               (0xFUL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00000004 */
15974 #define MDF_DFLTCR_TRGSRC                   MDF_DFLTCR_TRGSRC_Msk                   /*!<Digital filter trigger signal selection */
15975 #define MDF_DFLTCR_TRGSRC_0                 (0x1UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00001000 */
15976 #define MDF_DFLTCR_TRGSRC_1                 (0x2UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00002000 */
15977 #define MDF_DFLTCR_TRGSRC_2                 (0x4UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00004000 */
15978 #define MDF_DFLTCR_TRGSRC_3                 (0x8UL << MDF_DFLTCR_TRGSRC_Pos)        /*!< 0x00008000 */
15979 #define MDF_DFLTCR_SNPSFMT_Pos              (16U)
15980 #define MDF_DFLTCR_SNPSFMT_Msk              (0x1UL << MDF_DFLTCR_SNPSFMT_Pos)       /*!< 0x00000004 */
15981 #define MDF_DFLTCR_SNPSFMT                  MDF_DFLTCR_SNPSFMT_Msk                  /*!<SnapShot Data format */
15982 #define MDF_DFLTCR_NBDIS_Pos                (20U)
15983 #define MDF_DFLTCR_NBDIS_Msk                (0xFFUL << MDF_DFLTCR_NBDIS_Pos)        /*!< 0x00000004 */
15984 #define MDF_DFLTCR_NBDIS                    MDF_DFLTCR_NBDIS_Msk                    /*!<Number of samples to be discard */
15985 #define MDF_DFLTCR_DFLTRUN_Pos              (30U)
15986 #define MDF_DFLTCR_DFLTRUN_Msk              (0x1UL << MDF_DFLTCR_DFLTRUN_Pos)       /*!< 0x00000004 */
15987 #define MDF_DFLTCR_DFLTRUN                  MDF_DFLTCR_DFLTRUN_Msk                  /*!<Digital filter run status flag */
15988 #define MDF_DFLTCR_DFLTACTIVE_Pos           (31U)
15989 #define MDF_DFLTCR_DFLTACTIVE_Msk           (0x1UL << MDF_DFLTCR_DFLTACTIVE_Pos)    /*!< 0x00000004 */
15990 #define MDF_DFLTCR_DFLTACTIVE               MDF_DFLTCR_DFLTACTIVE_Msk               /*!<Digital filter active flag */
15991 
15992 /*******************  Bit definition for MDF/ADF_DFLTxCICR register  ********************/
15993 #define MDF_DFLTCICR_DATSRC_Pos             (0U)
15994 #define MDF_DFLTCICR_DATSRC_Msk             (0x3UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000003 */
15995 #define MDF_DFLTCICR_DATSRC                 MDF_DFLTCICR_DATSRC_Msk                 /*!<Source Data for the digital filter */
15996 #define MDF_DFLTCICR_DATSRC_0               (0x1UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000001 */
15997 #define MDF_DFLTCICR_DATSRC_1               (0x2UL << MDF_DFLTCICR_DATSRC_Pos)      /*!< 0x00000002 */
15998 #define MDF_DFLTCICR_CICMOD_Pos             (4U)
15999 #define MDF_DFLTCICR_CICMOD_Msk             (0x7UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000070 */
16000 #define MDF_DFLTCICR_CICMOD                 MDF_DFLTCICR_CICMOD_Msk                 /*!<Select the CIC Mode*/
16001 #define MDF_DFLTCICR_CICMOD_0               (0x1UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000010 */
16002 #define MDF_DFLTCICR_CICMOD_1               (0x2UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000020 */
16003 #define MDF_DFLTCICR_CICMOD_2               (0x4UL << MDF_DFLTCICR_CICMOD_Pos)      /*!< 0x00000030 */
16004 #define MDF_DFLTCICR_MCICD_Pos              (8U)
16005 #define MDF_DFLTCICR_MCICD_Msk              (0x1FFUL << MDF_DFLTCICR_MCICD_Pos)     /*!< 0x0001FF00 */
16006 #define MDF_DFLTCICR_MCICD                  MDF_DFLTCICR_MCICD_Msk                  /*!<CIC decimation ratio selection*/
16007 #define MDF_DFLTCICR_SCALE_Pos              (20U)
16008 #define MDF_DFLTCICR_SCALE_Msk              (0x3FUL << MDF_DFLTCICR_SCALE_Pos)      /*!< 0x03F00000 */
16009 #define MDF_DFLTCICR_SCALE                  MDF_DFLTCICR_SCALE_Msk                  /*!<Scaling factor selection*/
16010 
16011 /*******************  Bit definition for MDF/ADF_DFLTxRSFR register  ********************/
16012 #define MDF_DFLTRSFR_RSFLTBYP_Pos           (0U)
16013 #define MDF_DFLTRSFR_RSFLTBYP_Msk           (0x1UL << MDF_DFLTRSFR_RSFLTBYP_Pos)    /*!< 0x00000001 */
16014 #define MDF_DFLTRSFR_RSFLTBYP               MDF_DFLTRSFR_RSFLTBYP_Msk               /*!<Reshape filter bypass*/
16015 #define MDF_DFLTRSFR_RSFLTD_Pos             (4U)
16016 #define MDF_DFLTRSFR_RSFLTD_Msk             (0x1UL << MDF_DFLTRSFR_RSFLTD_Pos)      /*!< 0x00000010 */
16017 #define MDF_DFLTRSFR_RSFLTD                 MDF_DFLTRSFR_RSFLTD_Msk                 /*!<Reshape filter decimation ratio*/
16018 #define MDF_DFLTRSFR_HPFBYP_Pos             (7U)
16019 #define MDF_DFLTRSFR_HPFBYP_Msk             (0x1UL << MDF_DFLTRSFR_HPFBYP_Pos)      /*!< 0x00000080 */
16020 #define MDF_DFLTRSFR_HPFBYP                 MDF_DFLTRSFR_HPFBYP_Msk                 /*!<High-pass filter bypass*/
16021 #define MDF_DFLTRSFR_HPFC_Pos               (8U)
16022 #define MDF_DFLTRSFR_HPFC_Msk               (0x3UL << MDF_DFLTRSFR_HPFC_Pos)        /*!< 0x00000080 */
16023 #define MDF_DFLTRSFR_HPFC                   MDF_DFLTRSFR_HPFC_Msk                   /*!<High-pass filter cut-off frequency*/
16024 #define MDF_DFLTRSFR_HPFC_0                 (0x1UL << MDF_DFLTRSFR_HPFC_Pos)
16025 #define MDF_DFLTRSFR_HPFC_1                 (0x2UL << MDF_DFLTRSFR_HPFC_Pos)
16026 
16027 /*******************  Bit definition for MDF/ADF_DFLTxINTR register  ********************/
16028 #define MDF_DFLTINTR_INTDIV_Pos             (0U)
16029 #define MDF_DFLTINTR_INTDIV_Msk             (0x3UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000003 */
16030 #define MDF_DFLTINTR_INTDIV                 MDF_DFLTINTR_INTDIV_Msk                 /*!<Integrator output dividion*/
16031 #define MDF_DFLTINTR_INTDIV_0               (0x1UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000001 */
16032 #define MDF_DFLTINTR_INTDIV_1               (0x2UL << MDF_DFLTINTR_INTDIV_Pos)      /*!< 0x00000002 */
16033 #define MDF_DFLTINTR_INTVAL_Pos             (4U)
16034 #define MDF_DFLTINTR_INTVAL_Msk             (0x7FUL << MDF_DFLTINTR_INTVAL_Pos)     /*!< 0x000007F0 */
16035 #define MDF_DFLTINTR_INTVAL                 MDF_DFLTINTR_INTVAL_Msk                 /*!<Integrator value selection*/
16036 
16037 /*******************  Bit definition for MDF/ADF_OLDxCR register  ********************/
16038 #define MDF_OLDCR_OLDEN_Pos                 (0U)
16039 #define MDF_OLDCR_OLDEN_Msk                 (0x1UL << MDF_OLDCR_OLDEN_Pos)          /*!< 0x00000001 */
16040 #define MDF_OLDCR_OLDEN                     MDF_OLDCR_OLDEN_Msk                     /*!<OLD enable*/
16041 #define MDF_OLDCR_THINB_Pos                 (1U)
16042 #define MDF_OLDCR_THINB_Msk                 (0x1UL << MDF_OLDCR_THINB_Pos)          /*!< 0x00000002 */
16043 #define MDF_OLDCR_THINB                     MDF_OLDCR_THINB_Msk                     /*!<OLD threshold in band*/
16044 #define MDF_OLDCR_BKOLD_Pos                 (4U)
16045 #define MDF_OLDCR_BKOLD_Msk                 (0xFUL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x000000F0 */
16046 #define MDF_OLDCR_BKOLD                     MDF_OLDCR_BKOLD_Msk                     /*!<Bteak signal assignment for OLD*/
16047 #define MDF_OLDCR_BKOLD_0                   (0x1UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000010 */
16048 #define MDF_OLDCR_BKOLD_1                   (0x2UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000020 */
16049 #define MDF_OLDCR_BKOLD_2                   (0x4UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000040 */
16050 #define MDF_OLDCR_BKOLD_3                   (0x8UL << MDF_OLDCR_BKOLD_Pos)          /*!< 0x00000080 */
16051 #define MDF_OLDCR_ACICN_Pos                 (12U)
16052 #define MDF_OLDCR_ACICN_Msk                 (0x3UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00003000 */
16053 #define MDF_OLDCR_ACICN                     MDF_OLDCR_ACICN_Msk                     /*!<OLD CIC order selection*/
16054 #define MDF_OLDCR_ACICN_0                   (0x1UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00001000 */
16055 #define MDF_OLDCR_ACICN_1                   (0x2UL << MDF_OLDCR_ACICN_Pos)          /*!< 0x00002000 */
16056 #define MDF_OLDCR_ACICD_Pos                 (17U)
16057 #define MDF_OLDCR_ACICD_Msk                 (0x1FUL << MDF_OLDCR_ACICD_Pos)         /*!< 0x003E0000 */
16058 #define MDF_OLDCR_ACICD                     MDF_OLDCR_ACICD_Msk                     /*!<OLD CIC decimation ratio selection*/
16059 #define MDF_OLDCR_OLDACTIVE_Pos             (31U)
16060 #define MDF_OLDCR_OLDACTIVE_Msk             (0x1UL << MDF_OLDCR_OLDACTIVE_Pos)      /*!< 0x80000000 */
16061 #define MDF_OLDCR_OLDACTIVE                 MDF_OLDCR_OLDACTIVE_Msk                 /*!<OLD active flag*/
16062 
16063 /*******************  Bit definition for MDF/ADF_OLDxTHLR register  ********************/
16064 #define MDF_OLDTHLR_OLDTHL_Pos              (0U)
16065 #define MDF_OLDTHLR_OLDTHL_Msk              (0x3FFFFFFUL << MDF_OLDTHLR_OLDTHL_Pos) /*!< 0x03FFFFFF */
16066 #define MDF_OLDTHLR_OLDTHL                  MDF_OLDTHLR_OLDTHL_Msk                  /*!<OLD Low threshold value*/
16067 
16068 /*******************  Bit definition for MDF/ADF_OLDxTHHR register  ********************/
16069 #define MDF_OLDTHHR_OLDTHH_Pos              (0U)
16070 #define MDF_OLDTHHR_OLDTHH_Msk              (0x3FFFFFFUL << MDF_OLDTHHR_OLDTHH_Pos) /*!< 0x03FFFFFF */
16071 #define MDF_OLDTHHR_OLDTHH                  MDF_OLDTHHR_OLDTHH_Msk                  /*!<OLD High threshold value*/
16072 
16073 /*******************  Bit definition for MDF/ADF_DLYxCR register  ********************/
16074 #define MDF_DLYCR_SKPDLY_Pos                (0U)
16075 #define MDF_DLYCR_SKPDLY_Msk                (0x7FUL << MDF_DLYCR_SKPDLY_Pos)        /*!< 0x0000007F */
16076 #define MDF_DLYCR_SKPDLY                    MDF_DLYCR_SKPDLY_Msk                    /*!<Delay to apply to a bitstream*/
16077 #define MDF_DLYCR_SKPBF_Pos                 (31U)
16078 #define MDF_DLYCR_SKPBF_Msk                 (0x1UL << MDF_DLYCR_SKPBF_Pos)          /*!< 0x80000000 */
16079 #define MDF_DLYCR_SKPBF                     MDF_DLYCR_SKPBF_Msk                     /*!<DSkip Busy Flag*/
16080 
16081 /*******************  Bit definition for MDF/ADF_SCDxCR register  ********************/
16082 #define MDF_SCDCR_SCDEN_Pos                 (0U)
16083 #define MDF_SCDCR_SCDEN_Msk                 (0x1UL << MDF_SCDCR_SCDEN_Pos)          /*!< 0x00000001 */
16084 #define MDF_SCDCR_SCDEN                     MDF_SCDCR_SCDEN_Msk                     /*!<Short circuit detector enable*/
16085 #define MDF_SCDCR_BKSCD_Pos                 (4U)
16086 #define MDF_SCDCR_BKSCD_Msk                 (0xFUL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x000000F0 */
16087 #define MDF_SCDCR_BKSCD                     MDF_SCDCR_BKSCD_Msk                     /*!<Break signal assignment to short circuit detector */
16088 #define MDF_SCDCR_BKSCD_0                   (0x1UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000010 */
16089 #define MDF_SCDCR_BKSCD_1                   (0x2UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000020 */
16090 #define MDF_SCDCR_BKSCD_2                   (0x4UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000040 */
16091 #define MDF_SCDCR_BKSCD_3                   (0x8UL << MDF_SCDCR_BKSCD_Pos)          /*!< 0x00000080 */
16092 #define MDF_SCDCR_SCDT_Pos                  (12U)
16093 #define MDF_SCDCR_SCDT_Msk                  (0xFFUL << MDF_SCDCR_SCDT_Pos)          /*!< 0x00000FF00 */
16094 #define MDF_SCDCR_SCDT                      MDF_SCDCR_SCDT_Msk                      /*!<Short circuit detector threshold*/
16095 #define MDF_SCDCR_SCDACTIVE_Pos             (31U)
16096 #define MDF_SCDCR_SCDACTIVE_Msk             (0x1UL << MDF_SCDCR_SCDACTIVE_Pos)      /*!< 0x80000000 */
16097 #define MDF_SCDCR_SCDACTIVE                 MDF_SCDCR_SCDACTIVE_Msk                 /*!<Short circuit detector active flag*/
16098 
16099 /*******************  Bit definition for MDF/ADF_DFLTIER register  ********************/
16100 #define MDF_DFLTIER_FTHIE_Pos               (0U)
16101 #define MDF_DFLTIER_FTHIE_Msk               (0x1UL << MDF_DFLTIER_FTHIE_Pos)        /*!< 0x00000001 */
16102 #define MDF_DFLTIER_FTHIE                   MDF_DFLTIER_FTHIE_Msk                   /*!<RXFIFO threshold interrupt enable*/
16103 #define MDF_DFLTIER_DOVRIE_Pos              (1U)
16104 #define MDF_DFLTIER_DOVRIE_Msk              (0x1UL << MDF_DFLTIER_DOVRIE_Pos)       /*!< 0x00000002 */
16105 #define MDF_DFLTIER_DOVRIE                  MDF_DFLTIER_DOVRIE_Msk                  /*!<Data overflow interrupt enable*/
16106 #define MDF_DFLTIER_SSDRIE_Pos              (2U)
16107 #define MDF_DFLTIER_SSDRIE_Msk              (0x1UL << MDF_DFLTIER_SSDRIE_Pos)       /*!< 0x00000004 */
16108 #define MDF_DFLTIER_SSDRIE                  MDF_DFLTIER_SSDRIE_Msk                  /*!<Snapshot data ready interrupt enable*/
16109 #define MDF_DFLTIER_OLDIE_Pos               (4U)
16110 #define MDF_DFLTIER_OLDIE_Msk               (0x1UL << MDF_DFLTIER_OLDIE_Pos)        /*!< 0x00000010 */
16111 #define MDF_DFLTIER_OLDIE                   MDF_DFLTIER_OLDIE_Msk                   /*!<OLD interrupt enable*/
16112 #define MDF_DFLTIER_SSOVRIE_Pos             (7U)
16113 #define MDF_DFLTIER_SSOVRIE_Msk             (0x1UL << MDF_DFLTIER_SSOVRIE_Pos)      /*!< 0x00000080 */
16114 #define MDF_DFLTIER_SSOVRIE                 MDF_DFLTIER_SSOVRIE_Msk                 /*!<Snapshot overrun interrupt enable*/
16115 #define MDF_DFLTIER_SCDIE_Pos               (8U)
16116 #define MDF_DFLTIER_SCDIE_Msk               (0x1UL << MDF_DFLTIER_SCDIE_Pos)        /*!< 0x00000100 */
16117 #define MDF_DFLTIER_SCDIE                   MDF_DFLTIER_SCDIE_Msk                   /*!<Short circuit dtector interrupt enable*/
16118 #define MDF_DFLTIER_SATIE_Pos               (9U)
16119 #define MDF_DFLTIER_SATIE_Msk               (0x1UL << MDF_DFLTIER_SATIE_Pos)        /*!< 0x00000200 */
16120 #define MDF_DFLTIER_SATIE                   MDF_DFLTIER_SATIE_Msk                   /*!<Saturation detection interrupt enable*/
16121 #define MDF_DFLTIER_CKABIE_Pos              (10U)
16122 #define MDF_DFLTIER_CKABIE_Msk              (0x1UL << MDF_DFLTIER_CKABIE_Pos)       /*!< 0x00000400 */
16123 #define MDF_DFLTIER_CKABIE                  MDF_DFLTIER_CKABIE_Msk                  /*!<Clock absence detection interrupt enable*/
16124 #define MDF_DFLTIER_RFOVRIE_Pos             (11U)
16125 #define MDF_DFLTIER_RFOVRIE_Msk             (0x1UL << MDF_DFLTIER_RFOVRIE_Pos)      /*!< 0x00000800 */
16126 #define MDF_DFLTIER_RFOVRIE                 MDF_DFLTIER_RFOVRIE_Msk                 /*!<reshape filter overrun interrupt enable*/
16127 #define MDF_DFLTIER_SDDETIE_Pos             (12U)
16128 #define MDF_DFLTIER_SDDETIE_Msk             (0x1UL << MDF_DFLTIER_SDDETIE_Pos)      /*!< 0x00001000 */
16129 #define MDF_DFLTIER_SDDETIE                 MDF_DFLTIER_SDDETIE_Msk                 /*!<SAD interrupt enable*/
16130 #define MDF_DFLTIER_SDLVLIE_Pos             (13U)
16131 #define MDF_DFLTIER_SDLVLIE_Msk             (0x1UL << MDF_DFLTIER_SDLVLIE_Pos)      /*!< 0x00002000 */
16132 #define MDF_DFLTIER_SDLVLIE                 MDF_DFLTIER_SDLVLIE_Msk                 /*!<Sound level value ready interrupt enable*/
16133 
16134 /*******************  Bit definition for MDF/ADF_DFLTISR register  ********************/
16135 #define MDF_DFLTISR_FTHF_Pos                (0U)
16136 #define MDF_DFLTISR_FTHF_Msk                (0x1UL << MDF_DFLTISR_FTHF_Pos)         /*!< 0x00000001 */
16137 #define MDF_DFLTISR_FTHF                    MDF_DFLTISR_FTHF_Msk                    /*!<RXFIFO threshold interrupt flag*/
16138 #define MDF_DFLTISR_DOVRF_Pos               (1U)
16139 #define MDF_DFLTISR_DOVRF_Msk               (0x1UL << MDF_DFLTISR_DOVRF_Pos)        /*!< 0x00000002 */
16140 #define MDF_DFLTISR_DOVRF                   MDF_DFLTISR_DOVRF_Msk                   /*!<Data overflow interrupt flag*/
16141 #define MDF_DFLTISR_SSDRF_Pos               (2U)
16142 #define MDF_DFLTISR_SSDRF_Msk               (0x1UL << MDF_DFLTISR_SSDRF_Pos)        /*!< 0x00000004 */
16143 #define MDF_DFLTISR_SSDRF                   MDF_DFLTISR_SSDRF_Msk                   /*!<Snapshot data ready interrupt flag*/
16144 #define MDF_DFLTISR_RXNEF_Pos               (3U)
16145 #define MDF_DFLTISR_RXNEF_Msk               (0x1UL << MDF_DFLTISR_RXNEF_Pos)        /*!< 0x00000008 */
16146 #define MDF_DFLTISR_RXNEF                   MDF_DFLTISR_RXNEF_Msk                   /*!<Snapshot data ready interrupt flag*/
16147 #define MDF_DFLTISR_OLDF_Pos                (4U)
16148 #define MDF_DFLTISR_OLDF_Msk                (0x1UL << MDF_DFLTISR_OLDF_Pos)         /*!< 0x00000010 */
16149 #define MDF_DFLTISR_OLDF                    MDF_DFLTISR_OLDF_Msk                    /*!<OLD interrupt flag*/
16150 #define MDF_DFLTISR_THLF_Pos                (5U)
16151 #define MDF_DFLTISR_THLF_Msk                (0x1UL << MDF_DFLTISR_THLF_Pos)         /*!< 0x00000010 */
16152 #define MDF_DFLTISR_THLF                    MDF_DFLTISR_THLF_Msk                    /*!<OLD interrupt flag*/
16153 #define MDF_DFLTISR_THHF_Pos                (6U)
16154 #define MDF_DFLTISR_THHF_Msk                (0x1UL << MDF_DFLTISR_THHF_Pos)         /*!< 0x00000010 */
16155 #define MDF_DFLTISR_THHF                    MDF_DFLTISR_THHF_Msk                    /*!<OLD interrupt flag*/
16156 #define MDF_DFLTISR_SSOVRF_Pos              (7U)
16157 #define MDF_DFLTISR_SSOVRF_Msk              (0x1UL << MDF_DFLTISR_SSOVRF_Pos)      /*!< 0x00000080 */
16158 #define MDF_DFLTISR_SSOVRF                  MDF_DFLTISR_SSOVRF_Msk                  /*!<Snapshot overrun interrupt flag*/
16159 #define MDF_DFLTISR_SCDF_Pos                (8U)
16160 #define MDF_DFLTISR_SCDF_Msk                (0x1UL << MDF_DFLTISR_SCDF_Pos)         /*!< 0x00000100 */
16161 #define MDF_DFLTISR_SCDF                    MDF_DFLTISR_SCDF_Msk                    /*!<Short circuit dtector interrupt flag*/
16162 #define MDF_DFLTISR_SATF_Pos                (9U)
16163 #define MDF_DFLTISR_SATF_Msk                (0x1UL << MDF_DFLTISR_SATF_Pos)         /*!< 0x00000200 */
16164 #define MDF_DFLTISR_SATF                    MDF_DFLTISR_SATF_Msk                    /*!<Saturation detection interrupt flag*/
16165 #define MDF_DFLTISR_CKABF_Pos               (10U)
16166 #define MDF_DFLTISR_CKABF_Msk               (0x1UL << MDF_DFLTISR_CKABF_Pos)        /*!< 0x00000400 */
16167 #define MDF_DFLTISR_CKABF                   MDF_DFLTISR_CKABF_Msk                   /*!<Clock absence detection interrupt flag*/
16168 #define MDF_DFLTISR_RFOVRF_Pos              (11U)
16169 #define MDF_DFLTISR_RFOVRF_Msk              (0x1UL << MDF_DFLTISR_RFOVRF_Pos)       /*!< 0x00000800 */
16170 #define MDF_DFLTISR_RFOVRF                  MDF_DFLTISR_RFOVRF_Msk                  /*!<reshape filter overrun interrupt flag*/
16171 #define MDF_DFLTISR_SDDETF_Pos              (12U)
16172 #define MDF_DFLTISR_SDDETF_Msk              (0x1UL << MDF_DFLTISR_SDDETF_Pos)        /*!< 0x00001000 */
16173 #define MDF_DFLTISR_SDDETF                  MDF_DFLTISR_SDDETF_Msk                  /*!<SAD interrupt flag*/
16174 #define MDF_DFLTISR_SDLVLF_Pos              (13U)
16175 #define MDF_DFLTISR_SDLVLF_Msk              (0x1UL << MDF_DFLTISR_SDLVLF_Pos)       /*!< 0x00002000 */
16176 #define MDF_DFLTISR_SDLVLF                  MDF_DFLTISR_SDLVLF_Msk                  /*!<Sound level value ready interrupt flag*/
16177 
16178 /*******************  Bit definition for MDF/ADF_OECCR register  ********************/
16179 #define MDF_OECCR_OFFSET_Pos                (0U)
16180 #define MDF_OECCR_OFFSET_Msk                (0x3FFFFFFUL << MDF_OECCR_OFFSET_Pos)   /*!< 0x03FFFFFF */
16181 #define MDF_OECCR_OFFSET                    MDF_OECCR_OFFSET_Msk                    /*!<Short circuit detector enable*/
16182 
16183 /*******************  Bit definition for MDF/ADF_SADCR register  ********************/
16184 #define MDF_SADCR_SADEN_Pos                 (0U)
16185 #define MDF_SADCR_SADEN_Msk                 (0x1UL << MDF_SADCR_SADEN_Pos)          /*!< 0x00000001 */
16186 #define MDF_SADCR_SADEN                     MDF_SADCR_SADEN_Msk                     /*!<SAD enable*/
16187 #define MDF_SADCR_DATCAP_Pos                (1U)
16188 #define MDF_SADCR_DATCAP_Msk                (0x3UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000003 */
16189 #define MDF_SADCR_DATCAP                    MDF_SADCR_DATCAP_Msk                    /*!<SAD data capture mode*/
16190 #define MDF_SADCR_DATCAP_0                  (0x1UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000002 */
16191 #define MDF_SADCR_DATCAP_1                  (0x2UL << MDF_SADCR_DATCAP_Pos)         /*!< 0x00000004 */
16192 #define MDF_SADCR_DETCFG_Pos                (3U)
16193 #define MDF_SADCR_DETCFG_Msk                (0x1UL << MDF_SADCR_DETCFG_Pos)         /*!< 0x00000008 */
16194 #define MDF_SADCR_DETCFG                    MDF_SADCR_DETCFG_Msk                    /*!<SAD trigger event configuration*/
16195 #define MDF_SADCR_SADST_Pos                 (4U)
16196 #define MDF_SADCR_SADST_Msk                 (0x3UL << MDF_SADCR_SADST_Pos)          /*!< 0x00000030 */
16197 #define MDF_SADCR_SADST                     MDF_SADCR_SADST_Msk                     /*!<SAD state*/
16198 #define MDF_SADCR_HYSTEN_Pos                (7U)
16199 #define MDF_SADCR_HYSTEN_Msk                (0x1UL << MDF_SADCR_HYSTEN_Pos)         /*!< 0x00000080 */
16200 #define MDF_SADCR_HYSTEN                    MDF_SADCR_HYSTEN_Msk                    /*!<Hysteresis enable*/
16201 #define MDF_SADCR_FRSIZE_Pos                (8U)
16202 #define MDF_SADCR_FRSIZE_Msk                (0x7UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000700 */
16203 #define MDF_SADCR_FRSIZE                    MDF_SADCR_FRSIZE_Msk                    /*!<Frame size*/
16204 #define MDF_SADCR_FRSIZE_0                  (0x1UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000100 */
16205 #define MDF_SADCR_FRSIZE_1                  (0x2UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000200 */
16206 #define MDF_SADCR_FRSIZE_2                  (0x4UL << MDF_SADCR_FRSIZE_Pos)         /*!< 0x00000300 */
16207 #define MDF_SADCR_SADMOD_Pos                (12U)
16208 #define MDF_SADCR_SADMOD_Msk                (0x3UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00003000 */
16209 #define MDF_SADCR_SADMOD                    MDF_SADCR_SADMOD_Msk                    /*!<SAD working mode*/
16210 #define MDF_SADCR_SADMOD_0                  (0x1UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00001000 */
16211 #define MDF_SADCR_SADMOD_1                  (0x2UL << MDF_SADCR_SADMOD_Pos)         /*!< 0x00002000 */
16212 #define MDF_SADCR_SADACTIVE_Pos             (31U)
16213 #define MDF_SADCR_SADACTIVE_Msk             (0x1UL << MDF_SADCR_SADACTIVE_Pos)      /*!< 0x80000000 */
16214 #define MDF_SADCR_SADACTIVE                 MDF_SADCR_SADACTIVE_Msk                 /*!<SAD active flag*/
16215 
16216 /*******************  Bit definition for MDF/ADF_SADCFGR register  ********************/
16217 #define MDF_SADCFGR_SNTHR_Pos               (0U)
16218 #define MDF_SADCFGR_SNTHR_Msk               (0xFUL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x0000000F */
16219 #define MDF_SADCFGR_SNTHR                   MDF_SADCFGR_SNTHR_Msk                   /*!<Signal to noise threshold*/
16220 #define MDF_SADCFGR_SNTHR_0                 (0x1UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000001 */
16221 #define MDF_SADCFGR_SNTHR_1                 (0x2UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000002 */
16222 #define MDF_SADCFGR_SNTHR_2                 (0x4UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000004 */
16223 #define MDF_SADCFGR_SNTHR_3                 (0x8UL << MDF_SADCFGR_SNTHR_Pos)        /*!< 0x00000008 */
16224 #define MDF_SADCFGR_ANSLP_Pos               (4U)
16225 #define MDF_SADCFGR_ANSLP_Msk               (0x7UL << MDF_SADCFGR_ANSLP_Pos)        /*!< 0x00000070 */
16226 #define MDF_SADCFGR_ANSLP                   MDF_SADCFGR_ANSLP_Msk                   /*!<Ambiant noise slope control*/
16227 #define MDF_SADCFGR_LFRNB_Pos               (8U)
16228 #define MDF_SADCFGR_LFRNB_Msk               (0x7UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000700 */
16229 #define MDF_SADCFGR_LFRNB                   MDF_SADCFGR_LFRNB_Msk                   /*!<Number of learning frames*/
16230 #define MDF_SADCFGR_LFRNB_0                 (0x1UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000100 */
16231 #define MDF_SADCFGR_LFRNB_1                 (0x2UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000200 */
16232 #define MDF_SADCFGR_LFRNB_2                 (0x4UL << MDF_SADCFGR_LFRNB_Pos)        /*!< 0x00000400 */
16233 #define MDF_SADCFGR_HGOVR_Pos               (12U)
16234 #define MDF_SADCFGR_HGOVR_Msk               (0x7UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00007000 */
16235 #define MDF_SADCFGR_HGOVR                   MDF_SADCFGR_HGOVR_Msk                   /*!<Hangover time window*/
16236 #define MDF_SADCFGR_HGOVR_0                 (0x1UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00001000 */
16237 #define MDF_SADCFGR_HGOVR_1                 (0x2UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00002000 */
16238 #define MDF_SADCFGR_HGOVR_2                 (0x4UL << MDF_SADCFGR_HGOVR_Pos)        /*!< 0x00004000 */
16239 #define MDF_SADCFGR_ANMIN_Pos               (16U)
16240 #define MDF_SADCFGR_ANMIN_Msk               (0x1FFFUL << MDF_SADCFGR_ANMIN_Pos)     /*!< 0x1FFF0000 */
16241 #define MDF_SADCFGR_ANMIN                   MDF_SADCFGR_ANMIN_Msk                   /*!<Hangover time window*/
16242 
16243 /*******************  Bit definition for MDF/ADF_SADSDLVR register  ********************/
16244 #define MDF_SADSDLVR_SDLVL_Pos              (0U)
16245 #define MDF_SADSDLVR_SDLVL_Msk              (0x7FFFUL << MDF_SADSDLVR_SDLVL_Pos)    /*!< 0x00007FFF */
16246 #define MDF_SADSDLVR_SDLVL                  MDF_SADSDLVR_SDLVL_Msk                  /*!<Short term sound level*/
16247 
16248 /*******************  Bit definition for MDF/ADF_SADANLVR register  ********************/
16249 #define MDF_SADANLVR_ANLVL_Pos              (0U)
16250 #define MDF_SADANLVR_ANLVL_Msk              (0x7FFFUL << MDF_SADANLVR_ANLVL_Pos)    /*!< 0x00007FFF */
16251 #define MDF_SADANLVR_ANLVL                  MDF_SADANLVR_ANLVL_Msk                  /*!<Ambiant noise level estimation*/
16252 
16253 /*******************  Bit definition for MDF/ADF_SNPSDR register  ********************/
16254 #define MDF_SNPSDR_MCICDC_Pos               (0U)
16255 #define MDF_SNPSDR_MCICDC_Msk               (0x1FFUL << MDF_SNPSDR_MCICDC_Pos)      /*!< 0x000001FF */
16256 #define MDF_SNPSDR_MCICDC                   MDF_SNPSDR_MCICDC_Msk                   /*!<MCIC decimation counter*/
16257 #define MDF_SNPSDR_EXTSDR_Pos               (9U)
16258 #define MDF_SNPSDR_EXTSDR_Msk               (0x7FUL << MDF_SNPSDR_EXTSDR_Pos)       /*!< 0x0000FE00 */
16259 #define MDF_SNPSDR_EXTSDR                   MDF_SNPSDR_EXTSDR_Msk                   /*!<Extended data size*/
16260 #define MDF_SNPSDR_SDR_Pos                  (16U)
16261 #define MDF_SNPSDR_SDR_Msk                  (0xFFFFUL << MDF_SNPSDR_SDR_Pos)        /*!< 0xFFFF0000 */
16262 #define MDF_SNPSDR_SDR                      MDF_SNPSDR_SDR_Msk                      /*!<Extended data size*/
16263 
16264 /*******************  Bit definition for MDF/ADF_DFLTDR register  ********************/
16265 #define MDF_DFLTDR_DR_Pos                   (8U)
16266 #define MDF_DFLTDR_DR_Msk                   (0xFFFFFFUL << MDF_DFLTDR_DR_Pos)       /*!< 0xFFFFFF00 */
16267 #define MDF_DFLTDR_DR                       MDF_DFLTDR_DR_Msk                       /*!<MCIC decimation counter*/
16268 
16269 /******************************************************************************/
16270 /*                                                                            */
16271 /*                                    TIM                                     */
16272 /*                                                                            */
16273 /******************************************************************************/
16274 /*******************  Bit definition for TIM_CR1 register  ********************/
16275 #define TIM_CR1_CEN_Pos                     (0U)
16276 #define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)              /*!< 0x00000001 */
16277 #define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                         /*!<Counter enable */
16278 #define TIM_CR1_UDIS_Pos                    (1U)
16279 #define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)             /*!< 0x00000002 */
16280 #define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                        /*!<Update disable */
16281 #define TIM_CR1_URS_Pos                     (2U)
16282 #define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)              /*!< 0x00000004 */
16283 #define TIM_CR1_URS                         TIM_CR1_URS_Msk                         /*!<Update request source */
16284 #define TIM_CR1_OPM_Pos                     (3U)
16285 #define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)              /*!< 0x00000008 */
16286 #define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                         /*!<One pulse mode */
16287 #define TIM_CR1_DIR_Pos                     (4U)
16288 #define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)              /*!< 0x00000010 */
16289 #define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                         /*!<Direction */
16290 #define TIM_CR1_CMS_Pos                     (5U)
16291 #define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)              /*!< 0x00000060 */
16292 #define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                         /*!<CMS[1:0] bits (Center-aligned mode selection) */
16293 #define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)              /*!< 0x00000020 */
16294 #define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)              /*!< 0x00000040 */
16295 #define TIM_CR1_ARPE_Pos                    (7U)
16296 #define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)             /*!< 0x00000080 */
16297 #define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                        /*!<Auto-reload preload enable */
16298 #define TIM_CR1_CKD_Pos                     (8U)
16299 #define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)              /*!< 0x00000300 */
16300 #define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                         /*!<CKD[1:0] bits (clock division) */
16301 #define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)              /*!< 0x00000100 */
16302 #define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)              /*!< 0x00000200 */
16303 #define TIM_CR1_UIFREMAP_Pos                (11U)
16304 #define TIM_CR1_UIFREMAP_Msk                (0x1UL << TIM_CR1_UIFREMAP_Pos)         /*!< 0x00000800 */
16305 #define TIM_CR1_UIFREMAP                    TIM_CR1_UIFREMAP_Msk                    /*!<Update interrupt flag remap */
16306 #define TIM_CR1_DITHEN_Pos                  (12U)
16307 #define TIM_CR1_DITHEN_Msk                  (0x1UL << TIM_CR1_DITHEN_Pos)           /*!< 0x00001000 */
16308 #define TIM_CR1_DITHEN                      TIM_CR1_DITHEN_Msk                      /*!<Dithering enable */
16309 
16310 /*******************  Bit definition for TIM_CR2 register  ********************/
16311 #define TIM_CR2_CCPC_Pos                    (0U)
16312 #define TIM_CR2_CCPC_Msk                    (0x1UL << TIM_CR2_CCPC_Pos)             /*!< 0x00000001 */
16313 #define TIM_CR2_CCPC                        TIM_CR2_CCPC_Msk                        /*!<Capture/Compare Preloaded Control */
16314 #define TIM_CR2_CCUS_Pos                    (2U)
16315 #define TIM_CR2_CCUS_Msk                    (0x1UL << TIM_CR2_CCUS_Pos)             /*!< 0x00000004 */
16316 #define TIM_CR2_CCUS                        TIM_CR2_CCUS_Msk                        /*!<Capture/Compare Control Update Selection */
16317 #define TIM_CR2_CCDS_Pos                    (3U)
16318 #define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)             /*!< 0x00000008 */
16319 #define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                        /*!<Capture/Compare DMA Selection */
16320 #define TIM_CR2_MMS_Pos                     (4U)
16321 #define TIM_CR2_MMS_Msk                     (0x200007UL << TIM_CR2_MMS_Pos)         /*!< 0x02000070 */
16322 #define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                         /*!<MMS[3:0] bits (Master Mode Selection) */
16323 #define TIM_CR2_MMS_0                       (0x000001UL << TIM_CR2_MMS_Pos)         /*!< 0x00000010 */
16324 #define TIM_CR2_MMS_1                       (0x000002UL << TIM_CR2_MMS_Pos)         /*!< 0x00000020 */
16325 #define TIM_CR2_MMS_2                       (0x000004UL << TIM_CR2_MMS_Pos)         /*!< 0x00000040 */
16326 #define TIM_CR2_MMS_3                       (0x200000UL << TIM_CR2_MMS_Pos)         /*!< 0x02000000 */
16327 #define TIM_CR2_TI1S_Pos                    (7U)
16328 #define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)             /*!< 0x00000080 */
16329 #define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                        /*!<TI1 Selection */
16330 #define TIM_CR2_OIS1_Pos                    (8U)
16331 #define TIM_CR2_OIS1_Msk                    (0x1UL << TIM_CR2_OIS1_Pos)             /*!< 0x00000100 */
16332 #define TIM_CR2_OIS1                        TIM_CR2_OIS1_Msk                        /*!<Output Idle state 1 (OC1 output) */
16333 #define TIM_CR2_OIS1N_Pos                   (9U)
16334 #define TIM_CR2_OIS1N_Msk                   (0x1UL << TIM_CR2_OIS1N_Pos)            /*!< 0x00000200 */
16335 #define TIM_CR2_OIS1N                       TIM_CR2_OIS1N_Msk                       /*!<Output Idle state 1 (OC1N output) */
16336 #define TIM_CR2_OIS2_Pos                    (10U)
16337 #define TIM_CR2_OIS2_Msk                    (0x1UL << TIM_CR2_OIS2_Pos)             /*!< 0x00000400 */
16338 #define TIM_CR2_OIS2                        TIM_CR2_OIS2_Msk                        /*!<Output Idle state 2 (OC2 output) */
16339 #define TIM_CR2_OIS2N_Pos                   (11U)
16340 #define TIM_CR2_OIS2N_Msk                   (0x1UL << TIM_CR2_OIS2N_Pos)            /*!< 0x00000800 */
16341 #define TIM_CR2_OIS2N                       TIM_CR2_OIS2N_Msk                       /*!<Output Idle state 2 (OC2N output) */
16342 #define TIM_CR2_OIS3_Pos                    (12U)
16343 #define TIM_CR2_OIS3_Msk                    (0x1UL << TIM_CR2_OIS3_Pos)             /*!< 0x00001000 */
16344 #define TIM_CR2_OIS3                        TIM_CR2_OIS3_Msk                        /*!<Output Idle state 3 (OC3 output) */
16345 #define TIM_CR2_OIS3N_Pos                   (13U)
16346 #define TIM_CR2_OIS3N_Msk                   (0x1UL << TIM_CR2_OIS3N_Pos)            /*!< 0x00002000 */
16347 #define TIM_CR2_OIS3N                       TIM_CR2_OIS3N_Msk                       /*!<Output Idle state 3 (OC3N output) */
16348 #define TIM_CR2_OIS4_Pos                    (14U)
16349 #define TIM_CR2_OIS4_Msk                    (0x1UL << TIM_CR2_OIS4_Pos)             /*!< 0x00004000 */
16350 #define TIM_CR2_OIS4                        TIM_CR2_OIS4_Msk                        /*!<Output Idle state 4 (OC4 output) */
16351 #define TIM_CR2_OIS4N_Pos                   (15U)
16352 #define TIM_CR2_OIS4N_Msk                   (0x1UL << TIM_CR2_OIS4N_Pos)            /*!< 0x00008000 */
16353 #define TIM_CR2_OIS4N                       TIM_CR2_OIS4N_Msk                       /*!<Output Idle state 4 (OC4N output) */
16354 #define TIM_CR2_OIS5_Pos                    (16U)
16355 #define TIM_CR2_OIS5_Msk                    (0x1UL << TIM_CR2_OIS5_Pos)             /*!< 0x00010000 */
16356 #define TIM_CR2_OIS5                        TIM_CR2_OIS5_Msk                        /*!<Output Idle state 5 (OC5 output) */
16357 #define TIM_CR2_OIS6_Pos                    (18U)
16358 #define TIM_CR2_OIS6_Msk                    (0x1UL << TIM_CR2_OIS6_Pos)             /*!< 0x00040000 */
16359 #define TIM_CR2_OIS6                        TIM_CR2_OIS6_Msk                        /*!<Output Idle state 6 (OC6 output) */
16360 #define TIM_CR2_MMS2_Pos                    (20U)
16361 #define TIM_CR2_MMS2_Msk                    (0xFUL << TIM_CR2_MMS2_Pos)             /*!< 0x00F00000 */
16362 #define TIM_CR2_MMS2                        TIM_CR2_MMS2_Msk                        /*!<MMS[2:0] bits (Master Mode Selection) */
16363 #define TIM_CR2_MMS2_0                      (0x1UL << TIM_CR2_MMS2_Pos)             /*!< 0x00100000 */
16364 #define TIM_CR2_MMS2_1                      (0x2UL << TIM_CR2_MMS2_Pos)             /*!< 0x00200000 */
16365 #define TIM_CR2_MMS2_2                      (0x4UL << TIM_CR2_MMS2_Pos)             /*!< 0x00400000 */
16366 #define TIM_CR2_MMS2_3                      (0x8UL << TIM_CR2_MMS2_Pos)             /*!< 0x00800000 */
16367 
16368 /*******************  Bit definition for TIM_SMCR register  *******************/
16369 #define TIM_SMCR_SMS_Pos                    (0U)
16370 #define TIM_SMCR_SMS_Msk                    (0x10007UL << TIM_SMCR_SMS_Pos)         /*!< 0x00010007 */
16371 #define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                        /*!<SMS[2:0] bits (Slave mode selection) */
16372 #define TIM_SMCR_SMS_0                      (0x00001UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
16373 #define TIM_SMCR_SMS_1                      (0x00002UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
16374 #define TIM_SMCR_SMS_2                      (0x00004UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
16375 #define TIM_SMCR_SMS_3                      (0x10000UL << TIM_SMCR_SMS_Pos)         /*!< 0x00010000 */
16376 #define TIM_SMCR_OCCS_Pos                   (3U)
16377 #define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)            /*!< 0x00000008 */
16378 #define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                       /*!< OCREF clear selection */
16379 #define TIM_SMCR_TS_Pos                     (4U)
16380 #define TIM_SMCR_TS_Msk                     (0x30007UL << TIM_SMCR_TS_Pos)          /*!< 0x00300070 */
16381 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                         /*!<TS[2:0] bits (Trigger selection) */
16382 #define TIM_SMCR_TS_0                       (0x00001UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
16383 #define TIM_SMCR_TS_1                       (0x00002UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
16384 #define TIM_SMCR_TS_2                       (0x00004UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
16385 #define TIM_SMCR_TS_3                       (0x10000UL << TIM_SMCR_TS_Pos)          /*!< 0x00100000 */
16386 #define TIM_SMCR_TS_4                       (0x20000UL << TIM_SMCR_TS_Pos)          /*!< 0x00200000 */
16387 #define TIM_SMCR_MSM_Pos                    (7U)
16388 #define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)             /*!< 0x00000080 */
16389 #define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                        /*!<Master/slave mode */
16390 #define TIM_SMCR_ETF_Pos                    (8U)
16391 #define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)             /*!< 0x00000F00 */
16392 #define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                        /*!<ETF[3:0] bits (External trigger filter) */
16393 #define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000100 */
16394 #define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000200 */
16395 #define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000400 */
16396 #define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000800 */
16397 #define TIM_SMCR_ETPS_Pos                   (12U)
16398 #define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00003000 */
16399 #define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                       /*!<ETPS[1:0] bits (External trigger prescaler) */
16400 #define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00001000 */
16401 #define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00002000 */
16402 #define TIM_SMCR_ECE_Pos                    (14U)
16403 #define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)             /*!< 0x00004000 */
16404 #define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                        /*!<External clock enable */
16405 #define TIM_SMCR_ETP_Pos                    (15U)
16406 #define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)             /*!< 0x00008000 */
16407 #define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                        /*!<External trigger polarity */
16408 #define TIM_SMCR_SMSPE_Pos                  (24U)
16409 #define TIM_SMCR_SMSPE_Msk                  (0x1UL << TIM_SMCR_SMSPE_Pos)           /*!< 0x02000000 */
16410 #define TIM_SMCR_SMSPE                      TIM_SMCR_SMSPE_Msk                      /*!<SMS preload enable */
16411 #define TIM_SMCR_SMSPS_Pos                  (25U)
16412 #define TIM_SMCR_SMSPS_Msk                  (0x1UL << TIM_SMCR_SMSPS_Pos)           /*!< 0x04000000 */
16413 #define TIM_SMCR_SMSPS                      TIM_SMCR_SMSPS_Msk                      /*!<SMS preload source */
16414 
16415 /*******************  Bit definition for TIM_DIER register  *******************/
16416 #define TIM_DIER_UIE_Pos                    (0U)
16417 #define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)             /*!< 0x00000001 */
16418 #define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                        /*!<Update interrupt enable */
16419 #define TIM_DIER_CC1IE_Pos                  (1U)
16420 #define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)           /*!< 0x00000002 */
16421 #define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                      /*!<Capture/Compare 1 interrupt enable */
16422 #define TIM_DIER_CC2IE_Pos                  (2U)
16423 #define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)           /*!< 0x00000004 */
16424 #define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                      /*!<Capture/Compare 2 interrupt enable */
16425 #define TIM_DIER_CC3IE_Pos                  (3U)
16426 #define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)           /*!< 0x00000008 */
16427 #define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                      /*!<Capture/Compare 3 interrupt enable */
16428 #define TIM_DIER_CC4IE_Pos                  (4U)
16429 #define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)           /*!< 0x00000010 */
16430 #define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                      /*!<Capture/Compare 4 interrupt enable */
16431 #define TIM_DIER_COMIE_Pos                  (5U)
16432 #define TIM_DIER_COMIE_Msk                  (0x1UL << TIM_DIER_COMIE_Pos)           /*!< 0x00000020 */
16433 #define TIM_DIER_COMIE                      TIM_DIER_COMIE_Msk                      /*!<COM interrupt enable */
16434 #define TIM_DIER_TIE_Pos                    (6U)
16435 #define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)             /*!< 0x00000040 */
16436 #define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                        /*!<Trigger interrupt enable */
16437 #define TIM_DIER_BIE_Pos                    (7U)
16438 #define TIM_DIER_BIE_Msk                    (0x1UL << TIM_DIER_BIE_Pos)             /*!< 0x00000080 */
16439 #define TIM_DIER_BIE                        TIM_DIER_BIE_Msk                        /*!<Break interrupt enable */
16440 #define TIM_DIER_UDE_Pos                    (8U)
16441 #define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)             /*!< 0x00000100 */
16442 #define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                        /*!<Update DMA request enable */
16443 #define TIM_DIER_CC1DE_Pos                  (9U)
16444 #define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)           /*!< 0x00000200 */
16445 #define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                      /*!<Capture/Compare 1 DMA request enable */
16446 #define TIM_DIER_CC2DE_Pos                  (10U)
16447 #define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)           /*!< 0x00000400 */
16448 #define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                      /*!<Capture/Compare 2 DMA request enable */
16449 #define TIM_DIER_CC3DE_Pos                  (11U)
16450 #define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)           /*!< 0x00000800 */
16451 #define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                      /*!<Capture/Compare 3 DMA request enable */
16452 #define TIM_DIER_CC4DE_Pos                  (12U)
16453 #define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)           /*!< 0x00001000 */
16454 #define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                      /*!<Capture/Compare 4 DMA request enable */
16455 #define TIM_DIER_COMDE_Pos                  (13U)
16456 #define TIM_DIER_COMDE_Msk                  (0x1UL << TIM_DIER_COMDE_Pos)           /*!< 0x00002000 */
16457 #define TIM_DIER_COMDE                      TIM_DIER_COMDE_Msk                      /*!<COM DMA request enable */
16458 #define TIM_DIER_TDE_Pos                    (14U)
16459 #define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)             /*!< 0x00004000 */
16460 #define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                        /*!<Trigger DMA request enable */
16461 #define TIM_DIER_IDXIE_Pos                  (20U)
16462 #define TIM_DIER_IDXIE_Msk                  (0x1UL << TIM_DIER_IDXIE_Pos)           /*!< 0x00100000 */
16463 #define TIM_DIER_IDXIE                      TIM_DIER_IDXIE_Msk                      /*!<Encoder index interrupt enable */
16464 #define TIM_DIER_DIRIE_Pos                  (21U)
16465 #define TIM_DIER_DIRIE_Msk                  (0x1UL << TIM_DIER_DIRIE_Pos)           /*!< 0x00200000 */
16466 #define TIM_DIER_DIRIE                      TIM_DIER_DIRIE_Msk                      /*!<Encoder direction change interrupt enable */
16467 #define TIM_DIER_IERRIE_Pos                 (22U)
16468 #define TIM_DIER_IERRIE_Msk                 (0x1UL << TIM_DIER_IERRIE_Pos)          /*!< 0x00400000 */
16469 #define TIM_DIER_IERRIE                     TIM_DIER_IERRIE_Msk                     /*!<Encoder index error enable */
16470 #define TIM_DIER_TERRIE_Pos                 (23U)
16471 #define TIM_DIER_TERRIE_Msk                 (0x1UL << TIM_DIER_TERRIE_Pos)          /*!< 0x00800000 */
16472 #define TIM_DIER_TERRIE                     TIM_DIER_TERRIE_Msk                     /*!<Encoder transition error enable */
16473 
16474 /********************  Bit definition for TIM_SR register  ********************/
16475 #define TIM_SR_UIF_Pos                      (0U)
16476 #define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)               /*!< 0x00000001 */
16477 #define TIM_SR_UIF                          TIM_SR_UIF_Msk                          /*!<Update interrupt Flag */
16478 #define TIM_SR_CC1IF_Pos                    (1U)
16479 #define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)             /*!< 0x00000002 */
16480 #define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                        /*!<Capture/Compare 1 interrupt Flag */
16481 #define TIM_SR_CC2IF_Pos                    (2U)
16482 #define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)             /*!< 0x00000004 */
16483 #define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                        /*!<Capture/Compare 2 interrupt Flag */
16484 #define TIM_SR_CC3IF_Pos                    (3U)
16485 #define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)             /*!< 0x00000008 */
16486 #define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                        /*!<Capture/Compare 3 interrupt Flag */
16487 #define TIM_SR_CC4IF_Pos                    (4U)
16488 #define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)             /*!< 0x00000010 */
16489 #define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                        /*!<Capture/Compare 4 interrupt Flag */
16490 #define TIM_SR_COMIF_Pos                    (5U)
16491 #define TIM_SR_COMIF_Msk                    (0x1UL << TIM_SR_COMIF_Pos)             /*!< 0x00000020 */
16492 #define TIM_SR_COMIF                        TIM_SR_COMIF_Msk                        /*!<COM interrupt Flag */
16493 #define TIM_SR_TIF_Pos                      (6U)
16494 #define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)               /*!< 0x00000040 */
16495 #define TIM_SR_TIF                          TIM_SR_TIF_Msk                          /*!<Trigger interrupt Flag */
16496 #define TIM_SR_BIF_Pos                      (7U)
16497 #define TIM_SR_BIF_Msk                      (0x1UL << TIM_SR_BIF_Pos)               /*!< 0x00000080 */
16498 #define TIM_SR_BIF                          TIM_SR_BIF_Msk                          /*!<Break interrupt Flag */
16499 #define TIM_SR_B2IF_Pos                     (8U)
16500 #define TIM_SR_B2IF_Msk                     (0x1UL << TIM_SR_B2IF_Pos)              /*!< 0x00000100 */
16501 #define TIM_SR_B2IF                         TIM_SR_B2IF_Msk                         /*!<Break 2 interrupt Flag */
16502 #define TIM_SR_CC1OF_Pos                    (9U)
16503 #define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)             /*!< 0x00000200 */
16504 #define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                        /*!<Capture/Compare 1 Overcapture Flag */
16505 #define TIM_SR_CC2OF_Pos                    (10U)
16506 #define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)             /*!< 0x00000400 */
16507 #define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                        /*!<Capture/Compare 2 Overcapture Flag */
16508 #define TIM_SR_CC3OF_Pos                    (11U)
16509 #define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)             /*!< 0x00000800 */
16510 #define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                        /*!<Capture/Compare 3 Overcapture Flag */
16511 #define TIM_SR_CC4OF_Pos                    (12U)
16512 #define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)             /*!< 0x00001000 */
16513 #define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                        /*!<Capture/Compare 4 Overcapture Flag */
16514 #define TIM_SR_SBIF_Pos                     (13U)
16515 #define TIM_SR_SBIF_Msk                     (0x1UL << TIM_SR_SBIF_Pos)              /*!< 0x00002000 */
16516 #define TIM_SR_SBIF                         TIM_SR_SBIF_Msk                         /*!<System Break interrupt Flag */
16517 #define TIM_SR_CC5IF_Pos                    (16U)
16518 #define TIM_SR_CC5IF_Msk                    (0x1UL << TIM_SR_CC5IF_Pos)             /*!< 0x00010000 */
16519 #define TIM_SR_CC5IF                        TIM_SR_CC5IF_Msk                        /*!<Capture/Compare 5 interrupt Flag */
16520 #define TIM_SR_CC6IF_Pos                    (17U)
16521 #define TIM_SR_CC6IF_Msk                    (0x1UL << TIM_SR_CC6IF_Pos)             /*!< 0x00020000 */
16522 #define TIM_SR_CC6IF                        TIM_SR_CC6IF_Msk                        /*!<Capture/Compare 6 interrupt Flag */
16523 #define TIM_SR_IDXF_Pos                     (20U)
16524 #define TIM_SR_IDXF_Msk                     (0x1UL << TIM_SR_IDXF_Pos)              /*!< 0x00100000 */
16525 #define TIM_SR_IDXF                         TIM_SR_IDXF_Msk                         /*!<Encoder index interrupt flag */
16526 #define TIM_SR_DIRF_Pos                     (21U)
16527 #define TIM_SR_DIRF_Msk                     (0x1UL << TIM_SR_DIRF_Pos)              /*!< 0x00200000 */
16528 #define TIM_SR_DIRF                         TIM_SR_DIRF_Msk                         /*!<Encoder direction change interrupt flag */
16529 #define TIM_SR_IERRF_Pos                    (22U)
16530 #define TIM_SR_IERRF_Msk                    (0x1UL << TIM_SR_IERRF_Pos)             /*!< 0x00400000 */
16531 #define TIM_SR_IERRF                        TIM_SR_IERRF_Msk                        /*!<Encoder index error flag */
16532 #define TIM_SR_TERRF_Pos                    (23U)
16533 #define TIM_SR_TERRF_Msk                    (0x1UL << TIM_SR_TERRF_Pos)             /*!< 0x00800000 */
16534 #define TIM_SR_TERRF                        TIM_SR_TERRF_Msk                        /*!<Encoder transition error flag */
16535 
16536 /*******************  Bit definition for TIM_EGR register  ********************/
16537 #define TIM_EGR_UG_Pos                      (0U)
16538 #define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)               /*!< 0x00000001 */
16539 #define TIM_EGR_UG                          TIM_EGR_UG_Msk                          /*!<Update Generation */
16540 #define TIM_EGR_CC1G_Pos                    (1U)
16541 #define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)             /*!< 0x00000002 */
16542 #define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                        /*!<Capture/Compare 1 Generation */
16543 #define TIM_EGR_CC2G_Pos                    (2U)
16544 #define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)             /*!< 0x00000004 */
16545 #define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                        /*!<Capture/Compare 2 Generation */
16546 #define TIM_EGR_CC3G_Pos                    (3U)
16547 #define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)             /*!< 0x00000008 */
16548 #define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                        /*!<Capture/Compare 3 Generation */
16549 #define TIM_EGR_CC4G_Pos                    (4U)
16550 #define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)             /*!< 0x00000010 */
16551 #define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                        /*!<Capture/Compare 4 Generation */
16552 #define TIM_EGR_COMG_Pos                    (5U)
16553 #define TIM_EGR_COMG_Msk                    (0x1UL << TIM_EGR_COMG_Pos)             /*!< 0x00000020 */
16554 #define TIM_EGR_COMG                        TIM_EGR_COMG_Msk                        /*!<Capture/Compare Control Update Generation */
16555 #define TIM_EGR_TG_Pos                      (6U)
16556 #define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)               /*!< 0x00000040 */
16557 #define TIM_EGR_TG                          TIM_EGR_TG_Msk                          /*!<Trigger Generation */
16558 #define TIM_EGR_BG_Pos                      (7U)
16559 #define TIM_EGR_BG_Msk                      (0x1UL << TIM_EGR_BG_Pos)               /*!< 0x00000080 */
16560 #define TIM_EGR_BG                          TIM_EGR_BG_Msk                          /*!<Break Generation */
16561 #define TIM_EGR_B2G_Pos                     (8U)
16562 #define TIM_EGR_B2G_Msk                     (0x1UL << TIM_EGR_B2G_Pos)              /*!< 0x00000100 */
16563 #define TIM_EGR_B2G                         TIM_EGR_B2G_Msk                         /*!<Break 2 Generation */
16564 
16565 /******************  Bit definition for TIM_CCMR1 register  *******************/
16566 #define TIM_CCMR1_CC1S_Pos                  (0U)
16567 #define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000003 */
16568 #define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                      /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
16569 #define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000001 */
16570 #define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000002 */
16571 #define TIM_CCMR1_OC1FE_Pos                 (2U)
16572 #define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)          /*!< 0x00000004 */
16573 #define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                     /*!<Output Compare 1 Fast enable */
16574 #define TIM_CCMR1_OC1PE_Pos                 (3U)
16575 #define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)          /*!< 0x00000008 */
16576 #define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                     /*!<Output Compare 1 Preload enable */
16577 #define TIM_CCMR1_OC1M_Pos                  (4U)
16578 #define TIM_CCMR1_OC1M_Msk                  (0x1007UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00010070 */
16579 #define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                      /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
16580 #define TIM_CCMR1_OC1M_0                    (0x0001UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000010 */
16581 #define TIM_CCMR1_OC1M_1                    (0x0002UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000020 */
16582 #define TIM_CCMR1_OC1M_2                    (0x0004UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000040 */
16583 #define TIM_CCMR1_OC1M_3                    (0x1000UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00010000 */
16584 #define TIM_CCMR1_OC1CE_Pos                 (7U)
16585 #define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)          /*!< 0x00000080 */
16586 #define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                     /*!<Output Compare 1 Clear Enable */
16587 #define TIM_CCMR1_CC2S_Pos                  (8U)
16588 #define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000300 */
16589 #define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                      /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
16590 #define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000100 */
16591 #define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000200 */
16592 #define TIM_CCMR1_OC2FE_Pos                 (10U)
16593 #define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)          /*!< 0x00000400 */
16594 #define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                     /*!<Output Compare 2 Fast enable */
16595 #define TIM_CCMR1_OC2PE_Pos                 (11U)
16596 #define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)          /*!< 0x00000800 */
16597 #define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                     /*!<Output Compare 2 Preload enable */
16598 #define TIM_CCMR1_OC2M_Pos                  (12U)
16599 #define TIM_CCMR1_OC2M_Msk                  (0x1007UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x01007000 */
16600 #define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                      /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
16601 #define TIM_CCMR1_OC2M_0                    (0x0001UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00001000 */
16602 #define TIM_CCMR1_OC2M_1                    (0x0002UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00002000 */
16603 #define TIM_CCMR1_OC2M_2                    (0x0004UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00004000 */
16604 #define TIM_CCMR1_OC2M_3                    (0x1000UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x01000000 */
16605 #define TIM_CCMR1_OC2CE_Pos                 (15U)
16606 #define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)          /*!< 0x00008000 */
16607 #define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                     /*!<Output Compare 2 Clear Enable */
16608 
16609 /*----------------------------------------------------------------------------*/
16610 #define TIM_CCMR1_IC1PSC_Pos                (2U)
16611 #define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x0000000C */
16612 #define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk                    /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
16613 #define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x00000004 */
16614 #define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x00000008 */
16615 #define TIM_CCMR1_IC1F_Pos                  (4U)
16616 #define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)           /*!< 0x000000F0 */
16617 #define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                      /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
16618 #define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000010 */
16619 #define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000020 */
16620 #define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000040 */
16621 #define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000080 */
16622 #define TIM_CCMR1_IC2PSC_Pos                (10U)
16623 #define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000C00 */
16624 #define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk                    /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
16625 #define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000400 */
16626 #define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000800 */
16627 #define TIM_CCMR1_IC2F_Pos                  (12U)
16628 #define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)           /*!< 0x0000F000 */
16629 #define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                      /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
16630 #define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00001000 */
16631 #define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00002000 */
16632 #define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00004000 */
16633 #define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00008000 */
16634 
16635 /******************  Bit definition for TIM_CCMR2 register  *******************/
16636 #define TIM_CCMR2_CC3S_Pos                  (0U)
16637 #define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000003 */
16638 #define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                      /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
16639 #define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000001 */
16640 #define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000002 */
16641 #define TIM_CCMR2_OC3FE_Pos                 (2U)
16642 #define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)          /*!< 0x00000004 */
16643 #define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                     /*!<Output Compare 3 Fast enable */
16644 #define TIM_CCMR2_OC3PE_Pos                 (3U)
16645 #define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)          /*!< 0x00000008 */
16646 #define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                     /*!<Output Compare 3 Preload enable */
16647 #define TIM_CCMR2_OC3M_Pos                  (4U)
16648 #define TIM_CCMR2_OC3M_Msk                  (0x1007UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00010070 */
16649 #define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                      /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
16650 #define TIM_CCMR2_OC3M_0                    (0x0001UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000010 */
16651 #define TIM_CCMR2_OC3M_1                    (0x0002UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000020 */
16652 #define TIM_CCMR2_OC3M_2                    (0x0004UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000040 */
16653 #define TIM_CCMR2_OC3M_3                    (0x1000UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00010000 */
16654 #define TIM_CCMR2_OC3CE_Pos                 (7U)
16655 #define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)          /*!< 0x00000080 */
16656 #define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                     /*!<Output Compare 3 Clear Enable */
16657 #define TIM_CCMR2_CC4S_Pos                  (8U)
16658 #define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000300 */
16659 #define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                      /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
16660 #define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000100 */
16661 #define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000200 */
16662 #define TIM_CCMR2_OC4FE_Pos                 (10U)
16663 #define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)          /*!< 0x00000400 */
16664 #define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                     /*!<Output Compare 4 Fast enable */
16665 #define TIM_CCMR2_OC4PE_Pos                 (11U)
16666 #define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)          /*!< 0x00000800 */
16667 #define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                     /*!<Output Compare 4 Preload enable */
16668 #define TIM_CCMR2_OC4M_Pos                  (12U)
16669 #define TIM_CCMR2_OC4M_Msk                  (0x1007UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x01007000 */
16670 #define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                      /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
16671 #define TIM_CCMR2_OC4M_0                    (0x0001UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00001000 */
16672 #define TIM_CCMR2_OC4M_1                    (0x0002UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00002000 */
16673 #define TIM_CCMR2_OC4M_2                    (0x0004UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00004000 */
16674 #define TIM_CCMR2_OC4M_3                    (0x1000UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x01000000 */
16675 #define TIM_CCMR2_OC4CE_Pos                 (15U)
16676 #define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)          /*!< 0x00008000 */
16677 #define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                     /*!<Output Compare 4 Clear Enable */
16678 
16679 /*----------------------------------------------------------------------------*/
16680 #define TIM_CCMR2_IC3PSC_Pos                (2U)
16681 #define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x0000000C */
16682 #define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk                    /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
16683 #define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x00000004 */
16684 #define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x00000008 */
16685 #define TIM_CCMR2_IC3F_Pos                  (4U)
16686 #define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)           /*!< 0x000000F0 */
16687 #define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                      /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
16688 #define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000010 */
16689 #define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000020 */
16690 #define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000040 */
16691 #define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000080 */
16692 #define TIM_CCMR2_IC4PSC_Pos                (10U)
16693 #define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000C00 */
16694 #define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk                    /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
16695 #define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000400 */
16696 #define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000800 */
16697 #define TIM_CCMR2_IC4F_Pos                  (12U)
16698 #define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)           /*!< 0x0000F000 */
16699 #define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                      /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
16700 #define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00001000 */
16701 #define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00002000 */
16702 #define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00004000 */
16703 #define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00008000 */
16704 
16705 /******************  Bit definition for TIM_CCMR3 register  *******************/
16706 #define TIM_CCMR3_OC5FE_Pos                 (2U)
16707 #define TIM_CCMR3_OC5FE_Msk                 (0x1UL << TIM_CCMR3_OC5FE_Pos)          /*!< 0x00000004 */
16708 #define TIM_CCMR3_OC5FE                     TIM_CCMR3_OC5FE_Msk                     /*!<Output Compare 5 Fast enable */
16709 #define TIM_CCMR3_OC5PE_Pos                 (3U)
16710 #define TIM_CCMR3_OC5PE_Msk                 (0x1UL << TIM_CCMR3_OC5PE_Pos)          /*!< 0x00000008 */
16711 #define TIM_CCMR3_OC5PE                     TIM_CCMR3_OC5PE_Msk                     /*!<Output Compare 5 Preload enable */
16712 #define TIM_CCMR3_OC5M_Pos                  (4U)
16713 #define TIM_CCMR3_OC5M_Msk                  (0x1007UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00010070 */
16714 #define TIM_CCMR3_OC5M                      TIM_CCMR3_OC5M_Msk                      /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
16715 #define TIM_CCMR3_OC5M_0                    (0x0001UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000010 */
16716 #define TIM_CCMR3_OC5M_1                    (0x0002UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000020 */
16717 #define TIM_CCMR3_OC5M_2                    (0x0004UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000040 */
16718 #define TIM_CCMR3_OC5M_3                    (0x1000UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00010000 */
16719 #define TIM_CCMR3_OC5CE_Pos                 (7U)
16720 #define TIM_CCMR3_OC5CE_Msk                 (0x1UL << TIM_CCMR3_OC5CE_Pos)          /*!< 0x00000080 */
16721 #define TIM_CCMR3_OC5CE                     TIM_CCMR3_OC5CE_Msk                     /*!<Output Compare 5 Clear Enable */
16722 #define TIM_CCMR3_OC6FE_Pos                 (10U)
16723 #define TIM_CCMR3_OC6FE_Msk                 (0x1UL << TIM_CCMR3_OC6FE_Pos)          /*!< 0x00000400 */
16724 #define TIM_CCMR3_OC6FE                     TIM_CCMR3_OC6FE_Msk                     /*!<Output Compare 6 Fast enable */
16725 #define TIM_CCMR3_OC6PE_Pos                 (11U)
16726 #define TIM_CCMR3_OC6PE_Msk                 (0x1UL << TIM_CCMR3_OC6PE_Pos)          /*!< 0x00000800 */
16727 #define TIM_CCMR3_OC6PE                     TIM_CCMR3_OC6PE_Msk                     /*!<Output Compare 6 Preload enable */
16728 #define TIM_CCMR3_OC6M_Pos                  (12U)
16729 #define TIM_CCMR3_OC6M_Msk                  (0x1007UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x01007000 */
16730 #define TIM_CCMR3_OC6M                      TIM_CCMR3_OC6M_Msk                      /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
16731 #define TIM_CCMR3_OC6M_0                    (0x0001UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00001000 */
16732 #define TIM_CCMR3_OC6M_1                    (0x0002UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00002000 */
16733 #define TIM_CCMR3_OC6M_2                    (0x0004UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00004000 */
16734 #define TIM_CCMR3_OC6M_3                    (0x1000UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x01000000 */
16735 #define TIM_CCMR3_OC6CE_Pos                 (15U)
16736 #define TIM_CCMR3_OC6CE_Msk                 (0x1UL << TIM_CCMR3_OC6CE_Pos)          /*!< 0x00008000 */
16737 #define TIM_CCMR3_OC6CE                     TIM_CCMR3_OC6CE_Msk                     /*!<Output Compare 6 Clear Enable */
16738 
16739 /*******************  Bit definition for TIM_CCER register  *******************/
16740 #define TIM_CCER_CC1E_Pos                   (0U)
16741 #define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)            /*!< 0x00000001 */
16742 #define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                       /*!<Capture/Compare 1 output enable */
16743 #define TIM_CCER_CC1P_Pos                   (1U)
16744 #define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)            /*!< 0x00000002 */
16745 #define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                       /*!<Capture/Compare 1 output Polarity */
16746 #define TIM_CCER_CC1NE_Pos                  (2U)
16747 #define TIM_CCER_CC1NE_Msk                  (0x1UL << TIM_CCER_CC1NE_Pos)           /*!< 0x00000004 */
16748 #define TIM_CCER_CC1NE                      TIM_CCER_CC1NE_Msk                      /*!<Capture/Compare 1 Complementary output enable */
16749 #define TIM_CCER_CC1NP_Pos                  (3U)
16750 #define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)           /*!< 0x00000008 */
16751 #define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                      /*!<Capture/Compare 1 Complementary output Polarity */
16752 #define TIM_CCER_CC2E_Pos                   (4U)
16753 #define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)            /*!< 0x00000010 */
16754 #define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                       /*!<Capture/Compare 2 output enable */
16755 #define TIM_CCER_CC2P_Pos                   (5U)
16756 #define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)            /*!< 0x00000020 */
16757 #define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                       /*!<Capture/Compare 2 output Polarity */
16758 #define TIM_CCER_CC2NE_Pos                  (6U)
16759 #define TIM_CCER_CC2NE_Msk                  (0x1UL << TIM_CCER_CC2NE_Pos)           /*!< 0x00000040 */
16760 #define TIM_CCER_CC2NE                      TIM_CCER_CC2NE_Msk                      /*!<Capture/Compare 2 Complementary output enable */
16761 #define TIM_CCER_CC2NP_Pos                  (7U)
16762 #define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)           /*!< 0x00000080 */
16763 #define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                      /*!<Capture/Compare 2 Complementary output Polarity */
16764 #define TIM_CCER_CC3E_Pos                   (8U)
16765 #define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)            /*!< 0x00000100 */
16766 #define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                       /*!<Capture/Compare 3 output enable */
16767 #define TIM_CCER_CC3P_Pos                   (9U)
16768 #define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)            /*!< 0x00000200 */
16769 #define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                       /*!<Capture/Compare 3 output Polarity */
16770 #define TIM_CCER_CC3NE_Pos                  (10U)
16771 #define TIM_CCER_CC3NE_Msk                  (0x1UL << TIM_CCER_CC3NE_Pos)           /*!< 0x00000400 */
16772 #define TIM_CCER_CC3NE                      TIM_CCER_CC3NE_Msk                      /*!<Capture/Compare 3 Complementary output enable */
16773 #define TIM_CCER_CC3NP_Pos                  (11U)
16774 #define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)           /*!< 0x00000800 */
16775 #define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                      /*!<Capture/Compare 3 Complementary output Polarity */
16776 #define TIM_CCER_CC4E_Pos                   (12U)
16777 #define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)            /*!< 0x00001000 */
16778 #define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                       /*!<Capture/Compare 4 output enable */
16779 #define TIM_CCER_CC4P_Pos                   (13U)
16780 #define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)            /*!< 0x00002000 */
16781 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                       /*!<Capture/Compare 4 output Polarity */
16782 #define TIM_CCER_CC4NE_Pos                  (14U)
16783 #define TIM_CCER_CC4NE_Msk                  (0x1UL << TIM_CCER_CC4NE_Pos)           /*!< 0x00004000 */
16784 #define TIM_CCER_CC4NE                      TIM_CCER_CC4NE_Msk                      /*!<Capture/Compare 4 Complementary output enable */
16785 #define TIM_CCER_CC4NP_Pos                  (15U)
16786 #define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)           /*!< 0x00008000 */
16787 #define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                      /*!<Capture/Compare 4 Complementary output Polarity */
16788 #define TIM_CCER_CC5E_Pos                   (16U)
16789 #define TIM_CCER_CC5E_Msk                   (0x1UL << TIM_CCER_CC5E_Pos)            /*!< 0x00010000 */
16790 #define TIM_CCER_CC5E                       TIM_CCER_CC5E_Msk                       /*!<Capture/Compare 5 output enable */
16791 #define TIM_CCER_CC5P_Pos                   (17U)
16792 #define TIM_CCER_CC5P_Msk                   (0x1UL << TIM_CCER_CC5P_Pos)            /*!< 0x00020000 */
16793 #define TIM_CCER_CC5P                       TIM_CCER_CC5P_Msk                       /*!<Capture/Compare 5 output Polarity */
16794 #define TIM_CCER_CC6E_Pos                   (20U)
16795 #define TIM_CCER_CC6E_Msk                   (0x1UL << TIM_CCER_CC6E_Pos)            /*!< 0x00100000 */
16796 #define TIM_CCER_CC6E                       TIM_CCER_CC6E_Msk                       /*!<Capture/Compare 6 output enable */
16797 #define TIM_CCER_CC6P_Pos                   (21U)
16798 #define TIM_CCER_CC6P_Msk                   (0x1UL << TIM_CCER_CC6P_Pos)            /*!< 0x00200000 */
16799 #define TIM_CCER_CC6P                       TIM_CCER_CC6P_Msk                       /*!<Capture/Compare 6 output Polarity */
16800 
16801 /*******************  Bit definition for TIM_CNT register  ********************/
16802 #define TIM_CNT_CNT_Pos                     (0U)
16803 #define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)       /*!< 0xFFFFFFFF */
16804 #define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                         /*!<Counter Value */
16805 #define TIM_CNT_UIFCPY_Pos                  (31U)
16806 #define TIM_CNT_UIFCPY_Msk                  (0x1UL << TIM_CNT_UIFCPY_Pos)           /*!< 0x80000000 */
16807 #define TIM_CNT_UIFCPY                      TIM_CNT_UIFCPY_Msk                      /*!<Update interrupt flag copy (if UIFREMAP=1) */
16808 
16809 /*******************  Bit definition for TIM_PSC register  ********************/
16810 #define TIM_PSC_PSC_Pos                     (0U)
16811 #define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)           /*!< 0x0000FFFF */
16812 #define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                         /*!<Prescaler Value */
16813 
16814 /*******************  Bit definition for TIM_ARR register  ********************/
16815 #define TIM_ARR_ARR_Pos                     (0U)
16816 #define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)       /*!< 0xFFFFFFFF */
16817 #define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                         /*!<Actual auto-reload Value */
16818 
16819 /*******************  Bit definition for TIM_RCR register  ********************/
16820 #define TIM_RCR_REP_Pos                     (0U)
16821 #define TIM_RCR_REP_Msk                     (0xFFFFUL << TIM_RCR_REP_Pos)           /*!< 0x0000FFFF */
16822 #define TIM_RCR_REP                         TIM_RCR_REP_Msk                         /*!<Repetition Counter Value */
16823 
16824 /*******************  Bit definition for TIM_CCR1 register  *******************/
16825 #define TIM_CCR1_CCR1_Pos                   (0U)
16826 #define TIM_CCR1_CCR1_Msk                   (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0xFFFFFFFF */
16827 #define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                       /*!<Capture/Compare 1 Value */
16828 
16829 /*******************  Bit definition for TIM_CCR2 register  *******************/
16830 #define TIM_CCR2_CCR2_Pos                   (0U)
16831 #define TIM_CCR2_CCR2_Msk                   (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0xFFFFFFFF */
16832 #define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                       /*!<Capture/Compare 2 Value */
16833 
16834 /*******************  Bit definition for TIM_CCR3 register  *******************/
16835 #define TIM_CCR3_CCR3_Pos                   (0U)
16836 #define TIM_CCR3_CCR3_Msk                   (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0xFFFFFFFF */
16837 #define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                       /*!<Capture/Compare 3 Value */
16838 
16839 /*******************  Bit definition for TIM_CCR4 register  *******************/
16840 #define TIM_CCR4_CCR4_Pos                   (0U)
16841 #define TIM_CCR4_CCR4_Msk                   (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0xFFFFFFFF */
16842 #define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                       /*!<Capture/Compare 4 Value */
16843 
16844 /*******************  Bit definition for TIM_CCR5 register  *******************/
16845 #define TIM_CCR5_CCR5_Pos                   (0U)
16846 #define TIM_CCR5_CCR5_Msk                   (0xFFFFFUL << TIM_CCR5_CCR5_Pos)        /*!< 0x000FFFFF */
16847 #define TIM_CCR5_CCR5                       TIM_CCR5_CCR5_Msk                       /*!<Capture/Compare 5 Value */
16848 #define TIM_CCR5_GC5C1_Pos                  (29U)
16849 #define TIM_CCR5_GC5C1_Msk                  (0x1UL << TIM_CCR5_GC5C1_Pos)           /*!< 0x20000000 */
16850 #define TIM_CCR5_GC5C1                      TIM_CCR5_GC5C1_Msk                      /*!<Group Channel 5 and Channel 1 */
16851 #define TIM_CCR5_GC5C2_Pos                  (30U)
16852 #define TIM_CCR5_GC5C2_Msk                  (0x1UL << TIM_CCR5_GC5C2_Pos)           /*!< 0x40000000 */
16853 #define TIM_CCR5_GC5C2                      TIM_CCR5_GC5C2_Msk                      /*!<Group Channel 5 and Channel 2 */
16854 #define TIM_CCR5_GC5C3_Pos                  (31U)
16855 #define TIM_CCR5_GC5C3_Msk                  (0x1UL << TIM_CCR5_GC5C3_Pos)           /*!< 0x80000000 */
16856 #define TIM_CCR5_GC5C3                      TIM_CCR5_GC5C3_Msk                      /*!<Group Channel 5 and Channel 3 */
16857 
16858 /*******************  Bit definition for TIM_CCR6 register  *******************/
16859 #define TIM_CCR6_CCR6_Pos                   (0U)
16860 #define TIM_CCR6_CCR6_Msk                   (0xFFFFFUL << TIM_CCR6_CCR6_Pos)        /*!< 0x000FFFFF */
16861 #define TIM_CCR6_CCR6                       TIM_CCR6_CCR6_Msk                       /*!<Capture/Compare 6 Value */
16862 
16863 /*******************  Bit definition for TIM_BDTR register  *******************/
16864 #define TIM_BDTR_DTG_Pos                    (0U)
16865 #define TIM_BDTR_DTG_Msk                    (0xFFUL << TIM_BDTR_DTG_Pos)            /*!< 0x000000FF */
16866 #define TIM_BDTR_DTG                        TIM_BDTR_DTG_Msk                        /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
16867 #define TIM_BDTR_DTG_0                      (0x01UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000001 */
16868 #define TIM_BDTR_DTG_1                      (0x02UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000002 */
16869 #define TIM_BDTR_DTG_2                      (0x04UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000004 */
16870 #define TIM_BDTR_DTG_3                      (0x08UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000008 */
16871 #define TIM_BDTR_DTG_4                      (0x10UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000010 */
16872 #define TIM_BDTR_DTG_5                      (0x20UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000020 */
16873 #define TIM_BDTR_DTG_6                      (0x40UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000040 */
16874 #define TIM_BDTR_DTG_7                      (0x80UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000080 */
16875 #define TIM_BDTR_LOCK_Pos                   (8U)
16876 #define TIM_BDTR_LOCK_Msk                   (0x3UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000300 */
16877 #define TIM_BDTR_LOCK                       TIM_BDTR_LOCK_Msk                       /*!<LOCK[1:0] bits (Lock Configuration) */
16878 #define TIM_BDTR_LOCK_0                     (0x1UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000100 */
16879 #define TIM_BDTR_LOCK_1                     (0x2UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000200 */
16880 #define TIM_BDTR_OSSI_Pos                   (10U)
16881 #define TIM_BDTR_OSSI_Msk                   (0x1UL << TIM_BDTR_OSSI_Pos)            /*!< 0x00000400 */
16882 #define TIM_BDTR_OSSI                       TIM_BDTR_OSSI_Msk                       /*!<Off-State Selection for Idle mode */
16883 #define TIM_BDTR_OSSR_Pos                   (11U)
16884 #define TIM_BDTR_OSSR_Msk                   (0x1UL << TIM_BDTR_OSSR_Pos)            /*!< 0x00000800 */
16885 #define TIM_BDTR_OSSR                       TIM_BDTR_OSSR_Msk                       /*!<Off-State Selection for Run mode */
16886 #define TIM_BDTR_BKE_Pos                    (12U)
16887 #define TIM_BDTR_BKE_Msk                    (0x1UL << TIM_BDTR_BKE_Pos)             /*!< 0x00001000 */
16888 #define TIM_BDTR_BKE                        TIM_BDTR_BKE_Msk                        /*!<Break enable for Break 1 */
16889 #define TIM_BDTR_BKP_Pos                    (13U)
16890 #define TIM_BDTR_BKP_Msk                    (0x1UL << TIM_BDTR_BKP_Pos)             /*!< 0x00002000 */
16891 #define TIM_BDTR_BKP                        TIM_BDTR_BKP_Msk                        /*!<Break Polarity for Break 1 */
16892 #define TIM_BDTR_AOE_Pos                    (14U)
16893 #define TIM_BDTR_AOE_Msk                    (0x1UL << TIM_BDTR_AOE_Pos)             /*!< 0x00004000 */
16894 #define TIM_BDTR_AOE                        TIM_BDTR_AOE_Msk                        /*!<Automatic Output enable */
16895 #define TIM_BDTR_MOE_Pos                    (15U)
16896 #define TIM_BDTR_MOE_Msk                    (0x1UL << TIM_BDTR_MOE_Pos)             /*!< 0x00008000 */
16897 #define TIM_BDTR_MOE                        TIM_BDTR_MOE_Msk                        /*!<Main Output enable */
16898 #define TIM_BDTR_BKF_Pos                    (16U)
16899 #define TIM_BDTR_BKF_Msk                    (0xFUL << TIM_BDTR_BKF_Pos)             /*!< 0x000F0000 */
16900 #define TIM_BDTR_BKF                        TIM_BDTR_BKF_Msk                        /*!<Break Filter for Break 1 */
16901 #define TIM_BDTR_BK2F_Pos                   (20U)
16902 #define TIM_BDTR_BK2F_Msk                   (0xFUL << TIM_BDTR_BK2F_Pos)            /*!< 0x00F00000 */
16903 #define TIM_BDTR_BK2F                       TIM_BDTR_BK2F_Msk                       /*!<Break Filter for Break 2 */
16904 #define TIM_BDTR_BK2E_Pos                   (24U)
16905 #define TIM_BDTR_BK2E_Msk                   (0x1UL << TIM_BDTR_BK2E_Pos)            /*!< 0x01000000 */
16906 #define TIM_BDTR_BK2E                       TIM_BDTR_BK2E_Msk                       /*!<Break enable for Break 2 */
16907 #define TIM_BDTR_BK2P_Pos                   (25U)
16908 #define TIM_BDTR_BK2P_Msk                   (0x1UL << TIM_BDTR_BK2P_Pos)            /*!< 0x02000000 */
16909 #define TIM_BDTR_BK2P                       TIM_BDTR_BK2P_Msk                       /*!<Break Polarity for Break 2 */
16910 #define TIM_BDTR_BKDSRM_Pos                 (26U)
16911 #define TIM_BDTR_BKDSRM_Msk                 (0x1UL << TIM_BDTR_BKDSRM_Pos)          /*!< 0x04000000 */
16912 #define TIM_BDTR_BKDSRM                     TIM_BDTR_BKDSRM_Msk                     /*!<Break disarming/re-arming */
16913 #define TIM_BDTR_BK2DSRM_Pos                (27U)
16914 #define TIM_BDTR_BK2DSRM_Msk                (0x1UL << TIM_BDTR_BK2DSRM_Pos)         /*!< 0x08000000 */
16915 #define TIM_BDTR_BK2DSRM                    TIM_BDTR_BK2DSRM_Msk                    /*!<Break2 disarming/re-arming */
16916 #define TIM_BDTR_BKBID_Pos                  (28U)
16917 #define TIM_BDTR_BKBID_Msk                  (0x1UL << TIM_BDTR_BKBID_Pos)           /*!< 0x10000000 */
16918 #define TIM_BDTR_BKBID                      TIM_BDTR_BKBID_Msk                      /*!<Break BIDirectional */
16919 #define TIM_BDTR_BK2BID_Pos                 (29U)
16920 #define TIM_BDTR_BK2BID_Msk                 (0x1UL << TIM_BDTR_BK2BID_Pos)          /*!< 0x20000000 */
16921 #define TIM_BDTR_BK2BID                     TIM_BDTR_BK2BID_Msk                     /*!<Break2 BIDirectional */
16922 
16923 /*******************  Bit definition for TIM_DCR register  ********************/
16924 #define TIM_DCR_DBA_Pos                     (0U)
16925 #define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)             /*!< 0x0000001F */
16926 #define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                         /*!<DBA[4:0] bits (DMA Base Address) */
16927 #define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)             /*!< 0x00000001 */
16928 #define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)             /*!< 0x00000002 */
16929 #define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)             /*!< 0x00000004 */
16930 #define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)             /*!< 0x00000008 */
16931 #define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)             /*!< 0x00000010 */
16932 #define TIM_DCR_DBL_Pos                     (8U)
16933 #define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)             /*!< 0x00001F00 */
16934 #define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                         /*!<DBL[4:0] bits (DMA Burst Length) */
16935 #define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)             /*!< 0x00000100 */
16936 #define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)             /*!< 0x00000200 */
16937 #define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)             /*!< 0x00000400 */
16938 #define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)             /*!< 0x00000800 */
16939 #define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)             /*!< 0x00001000 */
16940 #define TIM_DCR_DBSS_Pos                    (16U)
16941 #define TIM_DCR_DBSS_Msk                    (0xFUL << TIM_DCR_DBSS_Pos)             /*!< 0x00000F00 */
16942 #define TIM_DCR_DBSS                        TIM_DCR_DBSS_Msk                        /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
16943 #define TIM_DCR_DBSS_0                      (0x01UL << TIM_DCR_DBSS_Pos)            /*!< 0x00010000 */
16944 #define TIM_DCR_DBSS_1                      (0x02UL << TIM_DCR_DBSS_Pos)            /*!< 0x00020000 */
16945 #define TIM_DCR_DBSS_2                      (0x04UL << TIM_DCR_DBSS_Pos)            /*!< 0x00040000 */
16946 #define TIM_DCR_DBSS_3                      (0x08UL << TIM_DCR_DBSS_Pos)            /*!< 0x00080000 */
16947 
16948 /*******************  Bit definition for TIM1_AF1 register  *******************/
16949 #define TIM1_AF1_BKINE_Pos                  (0U)
16950 #define TIM1_AF1_BKINE_Msk                  (0x1UL << TIM1_AF1_BKINE_Pos)           /*!< 0x00000001 */
16951 #define TIM1_AF1_BKINE                      TIM1_AF1_BKINE_Msk                      /*!<BRK BKIN input enable */
16952 #define TIM1_AF1_BKCMP1E_Pos                (1U)
16953 #define TIM1_AF1_BKCMP1E_Msk                (0x1UL << TIM1_AF1_BKCMP1E_Pos)         /*!< 0x00000002 */
16954 #define TIM1_AF1_BKCMP1E                    TIM1_AF1_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
16955 #define TIM1_AF1_BKCMP2E_Pos                (2U)
16956 #define TIM1_AF1_BKCMP2E_Msk                (0x1UL << TIM1_AF1_BKCMP2E_Pos)         /*!< 0x00000004 */
16957 #define TIM1_AF1_BKCMP2E                    TIM1_AF1_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
16958 #define TIM1_AF1_BKDF1BK0E_Pos              (8U)
16959 #define TIM1_AF1_BKDF1BK0E_Msk              (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)       /*!< 0x00000100 */
16960 #define TIM1_AF1_BKDF1BK0E                  TIM1_AF1_BKDF1BK0E_Msk                  /*!<BRK mdf1_break[0](TIM1) or mdf1_break[2](TIM2) enable */
16961 #define TIM1_AF1_BKINP_Pos                  (9U)
16962 #define TIM1_AF1_BKINP_Msk                  (0x1UL << TIM1_AF1_BKINP_Pos)           /*!< 0x00000200 */
16963 #define TIM1_AF1_BKINP                      TIM1_AF1_BKINP_Msk                      /*!<BRK BKIN input polarity */
16964 #define TIM1_AF1_BKCMP1P_Pos                (10U)
16965 #define TIM1_AF1_BKCMP1P_Msk                (0x1UL << TIM1_AF1_BKCMP1P_Pos)         /*!< 0x00000400 */
16966 #define TIM1_AF1_BKCMP1P                    TIM1_AF1_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
16967 #define TIM1_AF1_BKCMP2P_Pos                (11U)
16968 #define TIM1_AF1_BKCMP2P_Msk                (0x1UL << TIM1_AF1_BKCMP2P_Pos)         /*!< 0x00000800 */
16969 #define TIM1_AF1_BKCMP2P                    TIM1_AF1_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
16970 #define TIM1_AF1_ETRSEL_Pos                 (14U)
16971 #define TIM1_AF1_ETRSEL_Msk                 (0xFUL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x0003C000 */
16972 #define TIM1_AF1_ETRSEL                     TIM1_AF1_ETRSEL_Msk                     /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
16973 #define TIM1_AF1_ETRSEL_0                   (0x1UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00004000 */
16974 #define TIM1_AF1_ETRSEL_1                   (0x2UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00008000 */
16975 #define TIM1_AF1_ETRSEL_2                   (0x4UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00010000 */
16976 #define TIM1_AF1_ETRSEL_3                   (0x8UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00020000 */
16977 
16978 /*******************  Bit definition for TIM1_AF2 register  *********************/
16979 #define TIM1_AF2_BK2INE_Pos                 (0U)
16980 #define TIM1_AF2_BK2INE_Msk                 (0x1UL << TIM1_AF2_BK2INE_Pos)          /*!< 0x00000001 */
16981 #define TIM1_AF2_BK2INE                     TIM1_AF2_BK2INE_Msk                     /*!<BRK2 BKIN input enable */
16982 #define TIM1_AF2_BK2CMP1E_Pos               (1U)
16983 #define TIM1_AF2_BK2CMP1E_Msk               (0x1UL << TIM1_AF2_BK2CMP1E_Pos)        /*!< 0x00000002 */
16984 #define TIM1_AF2_BK2CMP1E                   TIM1_AF2_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
16985 #define TIM1_AF2_BK2CMP2E_Pos               (2U)
16986 #define TIM1_AF2_BK2CMP2E_Msk               (0x1UL << TIM1_AF2_BK2CMP2E_Pos)        /*!< 0x00000004 */
16987 #define TIM1_AF2_BK2CMP2E                   TIM1_AF2_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
16988 #define TIM1_AF2_BK2DF1BK1E_Pos             (8U)
16989 #define TIM1_AF2_BK2DF1BK1E_Msk             (0x1UL << TIM1_AF2_BK2DF1BK1E_Pos)      /*!< 0x00000100 */
16990 #define TIM1_AF2_BK2DF1BK1E                 TIM1_AF2_BK2DF1BK1E_Msk                 /*!<BRK2 mdf1_break[1](TIM1) or mdf1_break[3](TIM8) enable */
16991 #define TIM1_AF2_BK2INP_Pos                 (9U)
16992 #define TIM1_AF2_BK2INP_Msk                 (0x1UL << TIM1_AF2_BK2INP_Pos)          /*!< 0x00000200 */
16993 #define TIM1_AF2_BK2INP                     TIM1_AF2_BK2INP_Msk                     /*!<BRK2 BKIN input polarity */
16994 #define TIM1_AF2_BK2CMP1P_Pos               (10U)
16995 #define TIM1_AF2_BK2CMP1P_Msk               (0x1UL << TIM1_AF2_BK2CMP1P_Pos)        /*!< 0x00000400 */
16996 #define TIM1_AF2_BK2CMP1P                   TIM1_AF2_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
16997 #define TIM1_AF2_BK2CMP2P_Pos               (11U)
16998 #define TIM1_AF2_BK2CMP2P_Msk               (0x1UL << TIM1_AF2_BK2CMP2P_Pos)        /*!< 0x00000800 */
16999 #define TIM1_AF2_BK2CMP2P                   TIM1_AF2_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
17000 #define TIM1_AF2_OCRSEL_Pos                 (16U)
17001 #define TIM1_AF2_OCRSEL_Msk                 (0x1UL << TIM1_AF2_OCRSEL_Pos)          /*!< 0x00010000 */
17002 #define TIM1_AF2_OCRSEL                     TIM1_AF2_OCRSEL_Msk                     /*!<OCREF_CLR source selection */
17003 #define TIM1_AF2_OCRSEL_0                   (0x1UL << TIM1_AF2_OCRSEL_Pos)          /*!< 0x00010000 */
17004 
17005 /*******************  Bit definition for TIM_OR register  *********************/
17006 #define TIM_OR1_HSE32EN_Pos                 (1U)
17007 #define TIM_OR1_HSE32EN_Msk                 (0x1UL << TIM_OR1_HSE32EN_Pos)           /*!< 0x00000002 */
17008 #define TIM_OR1_HSE32EN                     TIM_OR1_HSE32EN_Msk                      /*!< HSE/32 clock enable */
17009 
17010 /*******************  Bit definition for TIM_TISEL register  *********************/
17011 #define TIM_TISEL_TI1SEL_Pos                (0U)
17012 #define TIM_TISEL_TI1SEL_Msk                (0xFUL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x0000000F */
17013 #define TIM_TISEL_TI1SEL                    TIM_TISEL_TI1SEL_Msk                    /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
17014 #define TIM_TISEL_TI1SEL_0                  (0x1UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000001 */
17015 #define TIM_TISEL_TI1SEL_1                  (0x2UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000002 */
17016 #define TIM_TISEL_TI1SEL_2                  (0x4UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000004 */
17017 #define TIM_TISEL_TI1SEL_3                  (0x8UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000008 */
17018 #define TIM_TISEL_TI2SEL_Pos                (8U)
17019 #define TIM_TISEL_TI2SEL_Msk                (0xFUL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000F00 */
17020 #define TIM_TISEL_TI2SEL                    TIM_TISEL_TI2SEL_Msk                    /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
17021 #define TIM_TISEL_TI2SEL_0                  (0x1UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000100 */
17022 #define TIM_TISEL_TI2SEL_1                  (0x2UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000200 */
17023 #define TIM_TISEL_TI2SEL_2                  (0x4UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000400 */
17024 #define TIM_TISEL_TI2SEL_3                  (0x8UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000800 */
17025 #define TIM_TISEL_TI3SEL_Pos                (16U)
17026 #define TIM_TISEL_TI3SEL_Msk                (0xFUL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x000F0000 */
17027 #define TIM_TISEL_TI3SEL                    TIM_TISEL_TI3SEL_Msk                    /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
17028 #define TIM_TISEL_TI3SEL_0                  (0x1UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00010000 */
17029 #define TIM_TISEL_TI3SEL_1                  (0x2UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00020000 */
17030 #define TIM_TISEL_TI3SEL_2                  (0x4UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00040000 */
17031 #define TIM_TISEL_TI3SEL_3                  (0x8UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00080000 */
17032 #define TIM_TISEL_TI4SEL_Pos                (24U)
17033 #define TIM_TISEL_TI4SEL_Msk                (0xFUL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x0F000000 */
17034 #define TIM_TISEL_TI4SEL                    TIM_TISEL_TI4SEL_Msk                    /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
17035 #define TIM_TISEL_TI4SEL_0                  (0x1UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x01000000 */
17036 #define TIM_TISEL_TI4SEL_1                  (0x2UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x02000000 */
17037 #define TIM_TISEL_TI4SEL_2                  (0x4UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x04000000 */
17038 #define TIM_TISEL_TI4SEL_3                  (0x8UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x08000000 */
17039 
17040 /*******************  Bit definition for TIM_DTR2 register  *********************/
17041 #define TIM_DTR2_DTGF_Pos                   (0U)
17042 #define TIM_DTR2_DTGF_Msk                   (0xFFUL << TIM_DTR2_DTGF_Pos)           /*!< 0x0000000F */
17043 #define TIM_DTR2_DTGF                       TIM_DTR2_DTGF_Msk                       /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
17044 #define TIM_DTR2_DTGF_0                     (0x01UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000001 */
17045 #define TIM_DTR2_DTGF_1                     (0x02UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000002 */
17046 #define TIM_DTR2_DTGF_2                     (0x04UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000004 */
17047 #define TIM_DTR2_DTGF_3                     (0x08UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000008 */
17048 #define TIM_DTR2_DTGF_4                     (0x10UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000010 */
17049 #define TIM_DTR2_DTGF_5                     (0x20UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000020 */
17050 #define TIM_DTR2_DTGF_6                     (0x40UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000040 */
17051 #define TIM_DTR2_DTGF_7                     (0x80UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000080 */
17052 #define TIM_DTR2_DTAE_Pos                   (16U)
17053 #define TIM_DTR2_DTAE_Msk                   (0x1UL << TIM_DTR2_DTAE_Pos)            /*!< 0x00004000 */
17054 #define TIM_DTR2_DTAE                       TIM_DTR2_DTAE_Msk                       /*!<Deadtime asymmetric enable */
17055 #define TIM_DTR2_DTPE_Pos                   (17U)
17056 #define TIM_DTR2_DTPE_Msk                   (0x1UL << TIM_DTR2_DTPE_Pos)            /*!< 0x00008000 */
17057 #define TIM_DTR2_DTPE                       TIM_DTR2_DTPE_Msk                       /*!<Deadtime prelaod enable */
17058 
17059 /*******************  Bit definition for TIM_ECR register  *********************/
17060 #define TIM_ECR_IE_Pos                      (0U)
17061 #define TIM_ECR_IE_Msk                      (0x1UL << TIM_ECR_IE_Pos)               /*!< 0x00000001 */
17062 #define TIM_ECR_IE                          TIM_ECR_IE_Msk                          /*!<Index enable */
17063 #define TIM_ECR_IDIR_Pos                    (1U)
17064 #define TIM_ECR_IDIR_Msk                    (0x3UL << TIM_ECR_IDIR_Pos)             /*!< 0x00000006 */
17065 #define TIM_ECR_IDIR                        TIM_ECR_IDIR_Msk                        /*!<IDIR[1:0] bits (Index direction)*/
17066 #define TIM_ECR_IDIR_0                      (0x01UL << TIM_ECR_IDIR_Pos)            /*!< 0x00000001 */
17067 #define TIM_ECR_IDIR_1                      (0x02UL << TIM_ECR_IDIR_Pos)            /*!< 0x00000002 */
17068 #define TIM_ECR_IBLK_Pos                    (3U)
17069 #define TIM_ECR_IBLK_Msk                    (0x3UL << TIM_ECR_IBLK_Pos)             /*!< 0x00000018 */
17070 #define TIM_ECR_IBLK                        TIM_ECR_IBLK_Msk                        /*!<IBLK[1:0] bits (Index blanking)*/
17071 #define TIM_ECR_IBLK_0                      (0x01UL << TIM_ECR_IBLK_Pos)            /*!< 0x00000008 */
17072 #define TIM_ECR_IBLK_1                      (0x02UL << TIM_ECR_IBLK_Pos)            /*!< 0x00000010 */
17073 #define TIM_ECR_FIDX_Pos                    (5U)
17074 #define TIM_ECR_FIDX_Msk                    (0x1UL << TIM_ECR_FIDX_Pos)             /*!< 0x00000020 */
17075 #define TIM_ECR_FIDX                        TIM_ECR_FIDX_Msk                        /*!<First index enable */
17076 #define TIM_ECR_IPOS_Pos                    (6U)
17077 #define TIM_ECR_IPOS_Msk                    (0x3UL << TIM_ECR_IPOS_Pos)             /*!< 0x000000C0 */
17078 #define TIM_ECR_IPOS                        TIM_ECR_IPOS_Msk                        /*!<IPOS[1:0] bits (Index positioning)*/
17079 #define TIM_ECR_IPOS_0                      (0x01UL << TIM_ECR_IPOS_Pos)            /*!< 0x00000040 */
17080 #define TIM_ECR_IPOS_1                      (0x02UL << TIM_ECR_IPOS_Pos)            /*!< 0x00000080 */
17081 #define TIM_ECR_PW_Pos                      (16U)
17082 #define TIM_ECR_PW_Msk                      (0xFFUL << TIM_ECR_PW_Pos)              /*!< 0x00FF0000 */
17083 #define TIM_ECR_PW                          TIM_ECR_PW_Msk                          /*!<PW[7:0] bits (Pulse width)*/
17084 #define TIM_ECR_PW_0                        (0x01UL << TIM_ECR_PW_Pos)              /*!< 0x00010000 */
17085 #define TIM_ECR_PW_1                        (0x02UL << TIM_ECR_PW_Pos)              /*!< 0x00020000 */
17086 #define TIM_ECR_PW_2                        (0x04UL << TIM_ECR_PW_Pos)              /*!< 0x00040000 */
17087 #define TIM_ECR_PW_3                        (0x08UL << TIM_ECR_PW_Pos)              /*!< 0x00080000 */
17088 #define TIM_ECR_PW_4                        (0x10UL << TIM_ECR_PW_Pos)              /*!< 0x00100000 */
17089 #define TIM_ECR_PW_5                        (0x20UL << TIM_ECR_PW_Pos)              /*!< 0x00200000 */
17090 #define TIM_ECR_PW_6                        (0x40UL << TIM_ECR_PW_Pos)              /*!< 0x00400000 */
17091 #define TIM_ECR_PW_7                        (0x80UL << TIM_ECR_PW_Pos)              /*!< 0x00800000 */
17092 #define TIM_ECR_PWPRSC_Pos                  (24U)
17093 #define TIM_ECR_PWPRSC_Msk                  (0x7UL << TIM_ECR_PWPRSC_Pos)           /*!< 0x07000000 */
17094 #define TIM_ECR_PWPRSC                      TIM_ECR_PWPRSC_Msk                      /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
17095 #define TIM_ECR_PWPRSC_0                    (0x01UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x01000000 */
17096 #define TIM_ECR_PWPRSC_1                    (0x02UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x02000000 */
17097 #define TIM_ECR_PWPRSC_2                    (0x04UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x04000000 */
17098 
17099 /*******************  Bit definition for TIM_DMAR register  *******************/
17100 #define TIM_DMAR_DMAB_Pos                   (0U)
17101 #define TIM_DMAR_DMAB_Msk                   (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0xFFFFFFFF */
17102 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                       /*!<DMA register for burst accesses */
17103 
17104 /******************************************************************************/
17105 /*                                                                            */
17106 /*                         Low Power Timer (LPTIM)                            */
17107 /*                                                                            */
17108 /******************************************************************************/
17109 /******************  Bit definition for LPTIM_ISR register  *******************/
17110 #define LPTIM_ISR_CC1IF_Pos                 (0U)
17111 #define LPTIM_ISR_CC1IF_Msk                 (0x1UL << LPTIM_ISR_CC1IF_Pos)            /*!< 0x00000001 */
17112 #define LPTIM_ISR_CC1IF                     LPTIM_ISR_CC1IF_Msk                       /*!< Capture/Compare 1 interrupt flag */
17113 #define LPTIM_ISR_ARRM_Pos                  (1U)
17114 #define LPTIM_ISR_ARRM_Msk                  (0x1UL << LPTIM_ISR_ARRM_Pos)           /*!< 0x00000002 */
17115 #define LPTIM_ISR_ARRM                      LPTIM_ISR_ARRM_Msk                      /*!< Autoreload match */
17116 #define LPTIM_ISR_EXTTRIG_Pos               (2U)
17117 #define LPTIM_ISR_EXTTRIG_Msk               (0x1UL << LPTIM_ISR_EXTTRIG_Pos)        /*!< 0x00000004 */
17118 #define LPTIM_ISR_EXTTRIG                   LPTIM_ISR_EXTTRIG_Msk                   /*!< External trigger edge event */
17119 #define LPTIM_ISR_CMP1OK_Pos                (3U)
17120 #define LPTIM_ISR_CMP1OK_Msk                (0x1UL << LPTIM_ISR_CMP1OK_Pos)         /*!< 0x00000008 */
17121 #define LPTIM_ISR_CMP1OK                    LPTIM_ISR_CMP1OK_Msk                    /*!< Compare register 1 update OK */
17122 #define LPTIM_ISR_ARROK_Pos                 (4U)
17123 #define LPTIM_ISR_ARROK_Msk                 (0x1UL << LPTIM_ISR_ARROK_Pos)          /*!< 0x00000010 */
17124 #define LPTIM_ISR_ARROK                     LPTIM_ISR_ARROK_Msk                     /*!< Autoreload register update OK */
17125 #define LPTIM_ISR_UP_Pos                    (5U)
17126 #define LPTIM_ISR_UP_Msk                    (0x1UL << LPTIM_ISR_UP_Pos)             /*!< 0x00000020 */
17127 #define LPTIM_ISR_UP                        LPTIM_ISR_UP_Msk                        /*!< Counter direction change down to up */
17128 #define LPTIM_ISR_DOWN_Pos                  (6U)
17129 #define LPTIM_ISR_DOWN_Msk                  (0x1UL << LPTIM_ISR_DOWN_Pos)           /*!< 0x00000040 */
17130 #define LPTIM_ISR_DOWN                      LPTIM_ISR_DOWN_Msk                      /*!< Counter direction change up to down */
17131 #define LPTIM_ISR_UE_Pos                    (7U)
17132 #define LPTIM_ISR_UE_Msk                    (0x1UL << LPTIM_ISR_UE_Pos)             /*!< 0x00000080 */
17133 #define LPTIM_ISR_UE                        LPTIM_ISR_UE_Msk                        /*!< Update event */
17134 #define LPTIM_ISR_REPOK_Pos                 (8U)
17135 #define LPTIM_ISR_REPOK_Msk                 (0x1UL << LPTIM_ISR_REPOK_Pos)          /*!< 0x00000100 */
17136 #define LPTIM_ISR_REPOK                     LPTIM_ISR_REPOK_Msk                     /*!< Repetition register update OK */
17137 #define LPTIM_ISR_CC2IF_Pos                 (9U)
17138 #define LPTIM_ISR_CC2IF_Msk                 (0x1UL << LPTIM_ISR_CC2IF_Pos)          /*!< 0x00000200 */
17139 #define LPTIM_ISR_CC2IF                     LPTIM_ISR_CC2IF_Msk                     /*!< Capture/Compare 2 interrupt flag */
17140 #define LPTIM_ISR_CC1OF_Pos                 (12U)
17141 #define LPTIM_ISR_CC1OF_Msk                 (0x1UL << LPTIM_ISR_CC1OF_Pos)          /*!< 0x00001000 */
17142 #define LPTIM_ISR_CC1OF                     LPTIM_ISR_CC1OF_Msk                     /*!< Capture/Compare 1 over-capture flag */
17143 #define LPTIM_ISR_CC2OF_Pos                 (13U)
17144 #define LPTIM_ISR_CC2OF_Msk                 (0x1UL << LPTIM_ISR_CC2OF_Pos)          /*!< 0x00002000 */
17145 #define LPTIM_ISR_CC2OF                     LPTIM_ISR_CC2OF_Msk                     /*!< Capture/Compare 2 over-capture flag */
17146 #define LPTIM_ISR_CMP2OK_Pos                (19U)
17147 #define LPTIM_ISR_CMP2OK_Msk                (0x1UL << LPTIM_ISR_CMP2OK_Pos)         /*!< 0x00080000 */
17148 #define LPTIM_ISR_CMP2OK                    LPTIM_ISR_CMP2OK_Msk                    /*!< Compare register 2 update OK */
17149 #define LPTIM_ISR_DIEROK_Pos                (24U)
17150 #define LPTIM_ISR_DIEROK_Msk                (0x1UL << LPTIM_ISR_DIEROK_Pos)         /*!< 0x01000000 */
17151 #define LPTIM_ISR_DIEROK                    LPTIM_ISR_DIEROK_Msk                    /*!< DMA & interrupt enable update OK */
17152 
17153 /******************  Bit definition for LPTIM_ICR register  *******************/
17154 #define LPTIM_ICR_CC1CF_Pos                 (0U)
17155 #define LPTIM_ICR_CC1CF_Msk                 (0x1UL << LPTIM_ICR_CC1CF_Pos)          /*!< 0x00000001 */
17156 #define LPTIM_ICR_CC1CF                     LPTIM_ICR_CC1CF_Msk                     /*!< Capture/Compare 1 clear flag  */
17157 #define LPTIM_ICR_ARRMCF_Pos                (1U)
17158 #define LPTIM_ICR_ARRMCF_Msk                (0x1UL << LPTIM_ICR_ARRMCF_Pos)         /*!< 0x00000002 */
17159 #define LPTIM_ICR_ARRMCF                    LPTIM_ICR_ARRMCF_Msk                    /*!< Autoreload match clear flag */
17160 #define LPTIM_ICR_EXTTRIGCF_Pos             (2U)
17161 #define LPTIM_ICR_EXTTRIGCF_Msk             (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)      /*!< 0x00000004 */
17162 #define LPTIM_ICR_EXTTRIGCF                 LPTIM_ICR_EXTTRIGCF_Msk                 /*!< External trigger edge event clear flag */
17163 #define LPTIM_ICR_CMP1OKCF_Pos              (3U)
17164 #define LPTIM_ICR_CMP1OKCF_Msk              (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)       /*!< 0x00000008 */
17165 #define LPTIM_ICR_CMP1OKCF                  LPTIM_ICR_CMP1OKCF_Msk                  /*!< Compare register 1 update OK clear flag */
17166 #define LPTIM_ICR_ARROKCF_Pos               (4U)
17167 #define LPTIM_ICR_ARROKCF_Msk               (0x1UL << LPTIM_ICR_ARROKCF_Pos)        /*!< 0x00000010 */
17168 #define LPTIM_ICR_ARROKCF                   LPTIM_ICR_ARROKCF_Msk                   /*!< Autoreload register update OK clear flag */
17169 #define LPTIM_ICR_UPCF_Pos                  (5U)
17170 #define LPTIM_ICR_UPCF_Msk                  (0x1UL << LPTIM_ICR_UPCF_Pos)           /*!< 0x00000020 */
17171 #define LPTIM_ICR_UPCF                      LPTIM_ICR_UPCF_Msk                      /*!< Counter direction change down to up clear flag */
17172 #define LPTIM_ICR_DOWNCF_Pos                (6U)
17173 #define LPTIM_ICR_DOWNCF_Msk                (0x1UL << LPTIM_ICR_DOWNCF_Pos)         /*!< 0x00000040 */
17174 #define LPTIM_ICR_DOWNCF                    LPTIM_ICR_DOWNCF_Msk                    /*!< Counter direction change up to down clear flag */
17175 #define LPTIM_ICR_UECF_Pos                  (7U)
17176 #define LPTIM_ICR_UECF_Msk                  (0x1UL << LPTIM_ICR_UECF_Pos)           /*!< 0x00000080 */
17177 #define LPTIM_ICR_UECF                      LPTIM_ICR_UECF_Msk                      /*!< Update event clear flag */
17178 #define LPTIM_ICR_REPOKCF_Pos               (8U)
17179 #define LPTIM_ICR_REPOKCF_Msk               (0x1UL << LPTIM_ICR_REPOKCF_Pos)        /*!< 0x00000100 */
17180 #define LPTIM_ICR_REPOKCF                   LPTIM_ICR_REPOKCF_Msk                   /*!< Repetition register update OK clear flag */
17181 #define LPTIM_ICR_CC2CF_Pos                 (9U)
17182 #define LPTIM_ICR_CC2CF_Msk                 (0x1UL << LPTIM_ICR_CC2CF_Pos)          /*!< 0x00000200 */
17183 #define LPTIM_ICR_CC2CF                     LPTIM_ICR_CC2CF_Msk                     /*!< Capture/Compare 2 clear flag  */
17184 #define LPTIM_ICR_CC1OCF_Pos                (12U)
17185 #define LPTIM_ICR_CC1OCF_Msk                (0x1UL << LPTIM_ICR_CC1OCF_Pos)         /*!< 0x00001000 */
17186 #define LPTIM_ICR_CC1OCF                    LPTIM_ICR_CC1OCF_Msk                    /*!< Capture/Compare 1 over-capture clear flag */
17187 #define LPTIM_ICR_CC2OCF_Pos                (13U)
17188 #define LPTIM_ICR_CC2OCF_Msk                (0x1UL << LPTIM_ICR_CC2OCF_Pos)         /*!< 0x00002000 */
17189 #define LPTIM_ICR_CC2OCF                    LPTIM_ICR_CC2OCF_Msk                    /*!< Capture/Compare 2 over-capture clear flag */
17190 #define LPTIM_ICR_CMP2OKCF_Pos              (19U)
17191 #define LPTIM_ICR_CMP2OKCF_Msk              (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)       /*!< 0x00080000 */
17192 #define LPTIM_ICR_CMP2OKCF                  LPTIM_ICR_CMP2OKCF_Msk                  /*!< Compare register 2 update OK clear flag */
17193 #define LPTIM_ICR_DIEROKCF_Pos              (24U)
17194 #define LPTIM_ICR_DIEROKCF_Msk              (0x1UL << LPTIM_ICR_DIEROKCF_Pos)       /*!< 0x01000000 */
17195 #define LPTIM_ICR_DIEROKCF                  LPTIM_ICR_DIEROKCF_Msk                  /*!< Interrupt enable register update OK clear flag */
17196 /******************  Bit definition for LPTIM_DIER register *******************/
17197 #define LPTIM_DIER_CC1IE_Pos                (0U)
17198 #define LPTIM_DIER_CC1IE_Msk                (0x1UL << LPTIM_DIER_CC1IE_Pos)         /*!< 0x00000001 */
17199 #define LPTIM_DIER_CC1IE                    LPTIM_DIER_CC1IE_Msk                    /*!< Compare/Compare interrupt enable */
17200 #define LPTIM_DIER_ARRMIE_Pos               (1U)
17201 #define LPTIM_DIER_ARRMIE_Msk               (0x1UL << LPTIM_DIER_ARRMIE_Pos)        /*!< 0x00000002 */
17202 #define LPTIM_DIER_ARRMIE                   LPTIM_DIER_ARRMIE_Msk                   /*!< Autoreload match interrupt enable */
17203 #define LPTIM_DIER_EXTTRIGIE_Pos            (2U)
17204 #define LPTIM_DIER_EXTTRIGIE_Msk            (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)     /*!< 0x00000004 */
17205 #define LPTIM_DIER_EXTTRIGIE                LPTIM_DIER_EXTTRIGIE_Msk                /*!< External trigger edge event interrupt enable */
17206 #define LPTIM_DIER_CMP1OKIE_Pos             (3U)
17207 #define LPTIM_DIER_CMP1OKIE_Msk             (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)      /*!< 0x00000008 */
17208 #define LPTIM_DIER_CMP1OKIE                 LPTIM_DIER_CMP1OKIE_Msk                 /*!< Compare register 1 update OK interrupt enable */
17209 #define LPTIM_DIER_ARROKIE_Pos              (4U)
17210 #define LPTIM_DIER_ARROKIE_Msk              (0x1UL << LPTIM_DIER_ARROKIE_Pos)       /*!< 0x00000010 */
17211 #define LPTIM_DIER_ARROKIE                  LPTIM_DIER_ARROKIE_Msk                  /*!< Autoreload register update OK interrupt enable */
17212 #define LPTIM_DIER_UPIE_Pos                 (5U)
17213 #define LPTIM_DIER_UPIE_Msk                 (0x1UL << LPTIM_DIER_UPIE_Pos)          /*!< 0x00000020 */
17214 #define LPTIM_DIER_UPIE                     LPTIM_DIER_UPIE_Msk                     /*!< Counter direction change down to up interrupt enable */
17215 #define LPTIM_DIER_DOWNIE_Pos               (6U)
17216 #define LPTIM_DIER_DOWNIE_Msk               (0x1UL << LPTIM_DIER_DOWNIE_Pos)        /*!< 0x00000040 */
17217 #define LPTIM_DIER_DOWNIE                   LPTIM_DIER_DOWNIE_Msk                   /*!< Counter direction change up to down interrupt enable */
17218 #define LPTIM_DIER_UEIE_Pos                 (7U)
17219 #define LPTIM_DIER_UEIE_Msk                 (0x1UL << LPTIM_DIER_UEIE_Pos)          /*!< 0x00000080 */
17220 #define LPTIM_DIER_UEIE                     LPTIM_DIER_UEIE_Msk                     /*!< Update event interrupt enable */
17221 #define LPTIM_DIER_REPOKIE_Pos              (8U)
17222 #define LPTIM_DIER_REPOKIE_Msk              (0x1UL << LPTIM_DIER_REPOKIE_Pos)       /*!< 0x00000100 */
17223 #define LPTIM_DIER_REPOKIE                  LPTIM_DIER_REPOKIE_Msk                  /*!< Repetition register update OK interrupt enable */
17224 #define LPTIM_DIER_CC2IE_Pos                (9U)
17225 #define LPTIM_DIER_CC2IE_Msk                (0x1UL << LPTIM_DIER_CC2IE_Pos)         /*!< 0x00000200 */
17226 #define LPTIM_DIER_CC2IE                    LPTIM_DIER_CC2IE_Msk                    /*!< Capture/Compare 2 interrupt interrupt enable */
17227 #define LPTIM_DIER_CC1OIE_Pos               (12U)
17228 #define LPTIM_DIER_CC1OIE_Msk               (0x1UL << LPTIM_DIER_CC1OIE_Pos)        /*!< 0x00001000 */
17229 #define LPTIM_DIER_CC1OIE                   LPTIM_DIER_CC1OIE_Msk                   /*!< Capture/Compare 1 over-capture interrupt enable */
17230 #define LPTIM_DIER_CC2OIE_Pos               (13U)
17231 #define LPTIM_DIER_CC2OIE_Msk               (0x1UL << LPTIM_DIER_CC2OIE_Pos)        /*!< 0x00002000 */
17232 #define LPTIM_DIER_CC2OIE                   LPTIM_DIER_CC2OIE_Msk                   /*!< Capture/Compare 2 over-capture interrupt enable */
17233 #define LPTIM_DIER_CC1DE_Pos                (16U)
17234 #define LPTIM_DIER_CC1DE_Msk                (0x1UL << LPTIM_DIER_CC1DE_Pos)         /*!< 0x00010000 */
17235 #define LPTIM_DIER_CC1DE                    LPTIM_DIER_CC1DE_Msk                    /*!< Capture/Compare 1 DMA request enable */
17236 #define LPTIM_DIER_CMP2OKIE_Pos             (19U)
17237 #define LPTIM_DIER_CMP2OKIE_Msk             (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)      /*!< 0x00080000 */
17238 #define LPTIM_DIER_CMP2OKIE                 LPTIM_DIER_CMP2OKIE_Msk                 /*!< Compare register 2 update OK interrupt enable */
17239 #define LPTIM_DIER_UEDE_Pos                 (23U)
17240 #define LPTIM_DIER_UEDE_Msk                 (0x1UL << LPTIM_DIER_UEDE_Pos)          /*!< 0x00800000 */
17241 #define LPTIM_DIER_UEDE                     LPTIM_DIER_UEDE_Msk                     /*!< Update event DMA request enable */
17242 #define LPTIM_DIER_CC2DE_Pos                (25U)
17243 #define LPTIM_DIER_CC2DE_Msk                (0x1UL << LPTIM_DIER_CC2DE_Pos)         /*!< 0x02000000 */
17244 #define LPTIM_DIER_CC2DE                    LPTIM_DIER_CC2DE_Msk                    /*!< Capture/Compare 2 DMA request enable */
17245 
17246 /******************  Bit definition for LPTIM_CFGR register *******************/
17247 #define LPTIM_CFGR_CKSEL_Pos                (0U)
17248 #define LPTIM_CFGR_CKSEL_Msk                (0x1UL << LPTIM_CFGR_CKSEL_Pos)         /*!< 0x00000001 */
17249 #define LPTIM_CFGR_CKSEL                    LPTIM_CFGR_CKSEL_Msk                    /*!< Clock selector */
17250 #define LPTIM_CFGR_CKPOL_Pos                (1U)
17251 #define LPTIM_CFGR_CKPOL_Msk                (0x3UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000006 */
17252 #define LPTIM_CFGR_CKPOL                    LPTIM_CFGR_CKPOL_Msk                    /*!< CKPOL[1:0] bits (Clock polarity) */
17253 #define LPTIM_CFGR_CKPOL_0                  (0x1UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000002 */
17254 #define LPTIM_CFGR_CKPOL_1                  (0x2UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000004 */
17255 #define LPTIM_CFGR_CKFLT_Pos                (3U)
17256 #define LPTIM_CFGR_CKFLT_Msk                (0x3UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000018 */
17257 #define LPTIM_CFGR_CKFLT                    LPTIM_CFGR_CKFLT_Msk                    /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
17258 #define LPTIM_CFGR_CKFLT_0                  (0x1UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000008 */
17259 #define LPTIM_CFGR_CKFLT_1                  (0x2UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000010 */
17260 #define LPTIM_CFGR_TRGFLT_Pos               (6U)
17261 #define LPTIM_CFGR_TRGFLT_Msk               (0x3UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x000000C0 */
17262 #define LPTIM_CFGR_TRGFLT                   LPTIM_CFGR_TRGFLT_Msk                   /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
17263 #define LPTIM_CFGR_TRGFLT_0                 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000040 */
17264 #define LPTIM_CFGR_TRGFLT_1                 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000080 */
17265 #define LPTIM_CFGR_PRESC_Pos                (9U)
17266 #define LPTIM_CFGR_PRESC_Msk                (0x7UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000E00 */
17267 #define LPTIM_CFGR_PRESC                    LPTIM_CFGR_PRESC_Msk                    /*!< PRESC[2:0] bits (Clock prescaler) */
17268 #define LPTIM_CFGR_PRESC_0                  (0x1UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000200 */
17269 #define LPTIM_CFGR_PRESC_1                  (0x2UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000400 */
17270 #define LPTIM_CFGR_PRESC_2                  (0x4UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000800 */
17271 #define LPTIM_CFGR_TRIGSEL_Pos              (13U)
17272 #define LPTIM_CFGR_TRIGSEL_Msk              (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x0000E000 */
17273 #define LPTIM_CFGR_TRIGSEL                  LPTIM_CFGR_TRIGSEL_Msk                  /*!< TRIGSEL[2:0]] bits (Trigger selector) */
17274 #define LPTIM_CFGR_TRIGSEL_0                (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00002000 */
17275 #define LPTIM_CFGR_TRIGSEL_1                (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00004000 */
17276 #define LPTIM_CFGR_TRIGSEL_2                (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00008000 */
17277 #define LPTIM_CFGR_TRIGEN_Pos               (17U)
17278 #define LPTIM_CFGR_TRIGEN_Msk               (0x3UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00060000 */
17279 #define LPTIM_CFGR_TRIGEN                   LPTIM_CFGR_TRIGEN_Msk                   /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
17280 #define LPTIM_CFGR_TRIGEN_0                 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00020000 */
17281 #define LPTIM_CFGR_TRIGEN_1                 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00040000 */
17282 #define LPTIM_CFGR_TIMOUT_Pos               (19U)
17283 #define LPTIM_CFGR_TIMOUT_Msk               (0x1UL << LPTIM_CFGR_TIMOUT_Pos)        /*!< 0x00080000 */
17284 #define LPTIM_CFGR_TIMOUT                   LPTIM_CFGR_TIMOUT_Msk                   /*!< Timout enable */
17285 #define LPTIM_CFGR_WAVE_Pos                 (20U)
17286 #define LPTIM_CFGR_WAVE_Msk                 (0x1UL << LPTIM_CFGR_WAVE_Pos)          /*!< 0x00100000 */
17287 #define LPTIM_CFGR_WAVE                     LPTIM_CFGR_WAVE_Msk                     /*!< Waveform shape */
17288 #define LPTIM_CFGR_WAVPOL_Pos               (21U)
17289 #define LPTIM_CFGR_WAVPOL_Msk               (0x1UL << LPTIM_CFGR_WAVPOL_Pos)        /*!< 0x00200000 */
17290 #define LPTIM_CFGR_WAVPOL                   LPTIM_CFGR_WAVPOL_Msk                   /*!< Waveform shape */
17291 #define LPTIM_CFGR_PRELOAD_Pos              (22U)
17292 #define LPTIM_CFGR_PRELOAD_Msk              (0x1UL << LPTIM_CFGR_PRELOAD_Pos)       /*!< 0x00400000 */
17293 #define LPTIM_CFGR_PRELOAD                  LPTIM_CFGR_PRELOAD_Msk                  /*!< Reg update mode */
17294 #define LPTIM_CFGR_COUNTMODE_Pos            (23U)
17295 #define LPTIM_CFGR_COUNTMODE_Msk            (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)     /*!< 0x00800000 */
17296 #define LPTIM_CFGR_COUNTMODE                LPTIM_CFGR_COUNTMODE_Msk                /*!< Counter mode enable */
17297 #define LPTIM_CFGR_ENC_Pos                  (24U)
17298 #define LPTIM_CFGR_ENC_Msk                  (0x1UL << LPTIM_CFGR_ENC_Pos)           /*!< 0x01000000 */
17299 #define LPTIM_CFGR_ENC                      LPTIM_CFGR_ENC_Msk                      /*!< Encoder mode enable */
17300 
17301 /******************  Bit definition for LPTIM_CR register  ********************/
17302 #define LPTIM_CR_ENABLE_Pos                 (0U)
17303 #define LPTIM_CR_ENABLE_Msk                 (0x1UL << LPTIM_CR_ENABLE_Pos)          /*!< 0x00000001 */
17304 #define LPTIM_CR_ENABLE                     LPTIM_CR_ENABLE_Msk                     /*!< LPTIMer enable */
17305 #define LPTIM_CR_SNGSTRT_Pos                (1U)
17306 #define LPTIM_CR_SNGSTRT_Msk                (0x1UL << LPTIM_CR_SNGSTRT_Pos)         /*!< 0x00000002 */
17307 #define LPTIM_CR_SNGSTRT                    LPTIM_CR_SNGSTRT_Msk                    /*!< Timer start in single mode */
17308 #define LPTIM_CR_CNTSTRT_Pos                (2U)
17309 #define LPTIM_CR_CNTSTRT_Msk                (0x1UL << LPTIM_CR_CNTSTRT_Pos)         /*!< 0x00000004 */
17310 #define LPTIM_CR_CNTSTRT                    LPTIM_CR_CNTSTRT_Msk                    /*!< Timer start in continuous mode */
17311 #define LPTIM_CR_COUNTRST_Pos               (3U)
17312 #define LPTIM_CR_COUNTRST_Msk               (0x1UL << LPTIM_CR_COUNTRST_Pos)        /*!< 0x00000008 */
17313 #define LPTIM_CR_COUNTRST                   LPTIM_CR_COUNTRST_Msk                   /*!< Timer Counter reset in synchronous mode*/
17314 #define LPTIM_CR_RSTARE_Pos                 (4U)
17315 #define LPTIM_CR_RSTARE_Msk                 (0x1UL << LPTIM_CR_RSTARE_Pos)          /*!< 0x00000010 */
17316 #define LPTIM_CR_RSTARE                     LPTIM_CR_RSTARE_Msk                     /*!< Timer Counter reset after read enable (asynchronously)*/
17317 
17318 /******************  Bit definition for LPTIM_CCR1 register  ******************/
17319 #define LPTIM_CCR1_CCR1_Pos                 (0U)
17320 #define LPTIM_CCR1_CCR1_Msk                 (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)       /*!< 0x0000FFFF */
17321 #define LPTIM_CCR1_CCR1                     LPTIM_CCR1_CCR1_Msk                     /*!< Compare register 1 */
17322 
17323 /******************  Bit definition for LPTIM_ARR register  *******************/
17324 #define LPTIM_ARR_ARR_Pos                   (0U)
17325 #define LPTIM_ARR_ARR_Msk                   (0xFFFFUL << LPTIM_ARR_ARR_Pos)         /*!< 0x0000FFFF */
17326 #define LPTIM_ARR_ARR                       LPTIM_ARR_ARR_Msk                       /*!< Auto reload register */
17327 
17328 /******************  Bit definition for LPTIM_CNT register  *******************/
17329 #define LPTIM_CNT_CNT_Pos                   (0U)
17330 #define LPTIM_CNT_CNT_Msk                   (0xFFFFUL << LPTIM_CNT_CNT_Pos)         /*!< 0x0000FFFF */
17331 #define LPTIM_CNT_CNT                       LPTIM_CNT_CNT_Msk                       /*!< Counter register */
17332 
17333 /******************  Bit definition for LPTIM_CFGR2 register  *****************/
17334 #define LPTIM_CFGR2_IN1SEL_Pos              (0U)
17335 #define LPTIM_CFGR2_IN1SEL_Msk              (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000003 */
17336 #define LPTIM_CFGR2_IN1SEL                  LPTIM_CFGR2_IN1SEL_Msk                  /*!< IN1SEL[1:0] bits (Remap selection) */
17337 #define LPTIM_CFGR2_IN1SEL_0                (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000001 */
17338 #define LPTIM_CFGR2_IN1SEL_1                (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000002 */
17339 #define LPTIM_CFGR2_IN2SEL_Pos              (4U)
17340 #define LPTIM_CFGR2_IN2SEL_Msk              (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000030 */
17341 #define LPTIM_CFGR2_IN2SEL                  LPTIM_CFGR2_IN2SEL_Msk                  /*!< IN2SEL[5:4] bits (Remap selection) */
17342 #define LPTIM_CFGR2_IN2SEL_0                (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000010 */
17343 #define LPTIM_CFGR2_IN2SEL_1                (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000020 */
17344 #define LPTIM_CFGR2_IC1SEL_Pos              (16U)
17345 #define LPTIM_CFGR2_IC1SEL_Msk              (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00000003 */
17346 #define LPTIM_CFGR2_IC1SEL                  LPTIM_CFGR2_IC1SEL_Msk                  /*!< IC1SEL[17:16] bits */
17347 #define LPTIM_CFGR2_IC1SEL_0                (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00010000 */
17348 #define LPTIM_CFGR2_IC1SEL_1                (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00020000 */
17349 #define LPTIM_CFGR2_IC2SEL_Pos              (20U)
17350 #define LPTIM_CFGR2_IC2SEL_Msk              (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00000030 */
17351 #define LPTIM_CFGR2_IC2SEL                  LPTIM_CFGR2_IC2SEL_Msk                  /*!< IC2SEL[21:20] bits */
17352 #define LPTIM_CFGR2_IC2SEL_0                (0x1UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00100000 */
17353 #define LPTIM_CFGR2_IC2SEL_1                (0x2UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00200000 */
17354 
17355 /******************  Bit definition for LPTIM_RCR register  *******************/
17356 #define LPTIM_RCR_REP_Pos                   (0U)
17357 #define LPTIM_RCR_REP_Msk                   (0xFFUL << LPTIM_RCR_REP_Pos)           /*!< 0x000000FF */
17358 #define LPTIM_RCR_REP                       LPTIM_RCR_REP_Msk                       /*!< Repetition register value */
17359 
17360 /*****************  Bit definition for LPTIM_CCMR1 register  ******************/
17361 #define LPTIM_CCMR1_CC1SEL_Pos              (0U)
17362 #define LPTIM_CCMR1_CC1SEL_Msk              (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)       /*!< 0x00000001 */
17363 #define LPTIM_CCMR1_CC1SEL                  LPTIM_CCMR1_CC1SEL_Msk                  /*!< Capture/Compare 1 selection */
17364 #define LPTIM_CCMR1_CC1E_Pos                (1U)
17365 #define LPTIM_CCMR1_CC1E_Msk                (0x1UL << LPTIM_CCMR1_CC1E_Pos)         /*!< 0x00000002 */
17366 #define LPTIM_CCMR1_CC1E                    LPTIM_CCMR1_CC1E_Msk                    /*!< Capture/Compare 1 output enable */
17367 #define LPTIM_CCMR1_CC1P_Pos                (2U)
17368 #define LPTIM_CCMR1_CC1P_Msk                (0x3UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x0000000C */
17369 #define LPTIM_CCMR1_CC1P                    LPTIM_CCMR1_CC1P_Msk                    /*!< Capture/Compare 1 output polarity */
17370 #define LPTIM_CCMR1_CC1P_0                  (0x1UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000004 */
17371 #define LPTIM_CCMR1_CC1P_1                  (0x2UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000008 */
17372 #define LPTIM_CCMR1_IC1PSC_Pos              (8U)
17373 #define LPTIM_CCMR1_IC1PSC_Msk              (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000300 */
17374 #define LPTIM_CCMR1_IC1PSC                  LPTIM_CCMR1_IC1PSC_Msk                  /*!< Input capture 1 prescaler */
17375 #define LPTIM_CCMR1_IC1PSC_0                (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000100 */
17376 #define LPTIM_CCMR1_IC1PSC_1                (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000200 */
17377 #define LPTIM_CCMR1_IC1F_Pos                (12U)
17378 #define LPTIM_CCMR1_IC1F_Msk                (0x3UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00003000 */
17379 #define LPTIM_CCMR1_IC1F                    LPTIM_CCMR1_IC1F_Msk                    /*!< Input capture 1 filter */
17380 #define LPTIM_CCMR1_IC1F_0                  (0x1UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00001000 */
17381 #define LPTIM_CCMR1_IC1F_1                  (0x2UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00002000 */
17382 #define LPTIM_CCMR1_CC2SEL_Pos              (16U)
17383 #define LPTIM_CCMR1_CC2SEL_Msk              (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)       /*!< 0x00010000 */
17384 #define LPTIM_CCMR1_CC2SEL                  LPTIM_CCMR1_CC2SEL_Msk                  /*!< Capture/Compare 2 selection */
17385 #define LPTIM_CCMR1_CC2E_Pos                (17U)
17386 #define LPTIM_CCMR1_CC2E_Msk                (0x1UL << LPTIM_CCMR1_CC2E_Pos)         /*!< 0x00020000 */
17387 #define LPTIM_CCMR1_CC2E                    LPTIM_CCMR1_CC2E_Msk                    /*!< Capture/Compare 2 output enable */
17388 #define LPTIM_CCMR1_CC2P_Pos                (18U)
17389 #define LPTIM_CCMR1_CC2P_Msk                (0x3UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x000C0000 */
17390 #define LPTIM_CCMR1_CC2P                    LPTIM_CCMR1_CC2P_Msk                    /*!< Capture/Compare 2 output polarity */
17391 #define LPTIM_CCMR1_CC2P_0                  (0x1UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00040000 */
17392 #define LPTIM_CCMR1_CC2P_1                  (0x2UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00080000 */
17393 #define LPTIM_CCMR1_IC2PSC_Pos              (24U)
17394 #define LPTIM_CCMR1_IC2PSC_Msk              (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x03000000 */
17395 #define LPTIM_CCMR1_IC2PSC                  LPTIM_CCMR1_IC2PSC_Msk                  /*!< Input capture 2 prescaler */
17396 #define LPTIM_CCMR1_IC2PSC_0                (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x01000000 */
17397 #define LPTIM_CCMR1_IC2PSC_1                (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x02000000 */
17398 #define LPTIM_CCMR1_IC2F_Pos                (28U)
17399 #define LPTIM_CCMR1_IC2F_Msk                (0x3UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x30000000 */
17400 #define LPTIM_CCMR1_IC2F                    LPTIM_CCMR1_IC2F_Msk                    /*!< Input capture 2 filter */
17401 #define LPTIM_CCMR1_IC2F_0                  (0x1UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x10000000 */
17402 #define LPTIM_CCMR1_IC2F_1                  (0x2UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x20000000 */
17403 
17404 /******************  Bit definition for LPTIM_CCR2 register  ******************/
17405 #define LPTIM_CCR2_CCR2_Pos                 (0U)
17406 #define LPTIM_CCR2_CCR2_Msk                 (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)       /*!< 0x0000FFFF */
17407 #define LPTIM_CCR2_CCR2                     LPTIM_CCR2_CCR2_Msk                     /*!< Compare register 2 */
17408 
17409 /******************************************************************************/
17410 /*                                                                            */
17411 /*                Parallel Synchronous Slave Interface (PSSI )                */
17412 /*                                                                            */
17413 /******************************************************************************/
17414 /********************  Bit definition for PSSI_CR register  *******************/
17415 #define PSSI_CR_CKPOL_Pos                   (5U)
17416 #define PSSI_CR_CKPOL_Msk                   (0x1UL << PSSI_CR_CKPOL_Pos)            /*!< 0x00000020 */
17417 #define PSSI_CR_CKPOL                       PSSI_CR_CKPOL_Msk                       /*!< Parallel data clock polarity */
17418 #define PSSI_CR_DEPOL_Pos                   (6U)
17419 #define PSSI_CR_DEPOL_Msk                   (0x1UL << PSSI_CR_DEPOL_Pos)            /*!< 0x00000040 */
17420 #define PSSI_CR_DEPOL                       PSSI_CR_DEPOL_Msk                       /*!<  Data enable polarity */
17421 #define PSSI_CR_RDYPOL_Pos                  (8U)
17422 #define PSSI_CR_RDYPOL_Msk                  (0x1UL << PSSI_CR_RDYPOL_Pos)           /*!< 0x00000100 */
17423 #define PSSI_CR_RDYPOL                      PSSI_CR_RDYPOL_Msk                      /*!< Ready polarity */
17424 #define PSSI_CR_EDM_Pos                     (10U)
17425 #define PSSI_CR_EDM_Msk                     (0x3UL << PSSI_CR_EDM_Pos)              /*!< 0x00000C00 */
17426 #define PSSI_CR_EDM                         PSSI_CR_EDM_Msk                         /*!< Extended data mode */
17427 #define PSSI_CR_ENABLE_Pos                  (14U)
17428 #define PSSI_CR_ENABLE_Msk                  (0x1UL << PSSI_CR_ENABLE_Pos)           /*!< 0x00004000 */
17429 #define PSSI_CR_ENABLE                      PSSI_CR_ENABLE_Msk                      /*!< PSSI enable */
17430 #define PSSI_CR_DERDYCFG_Pos                (18U)
17431 #define PSSI_CR_DERDYCFG_Msk                (0x7UL << PSSI_CR_DERDYCFG_Pos)         /*!< 0x001C0000 */
17432 #define PSSI_CR_DERDYCFG                    PSSI_CR_DERDYCFG_Msk                    /*!< Data enable and ready configuration */
17433 #define PSSI_CR_DMAEN_Pos                   (30U)
17434 #define PSSI_CR_DMAEN_Msk                   (0x1UL << PSSI_CR_DMAEN_Pos)            /*!< 0x40000000 */
17435 #define PSSI_CR_DMAEN                       PSSI_CR_DMAEN_Msk                       /*!< DMA enable */
17436 #define PSSI_CR_OUTEN_Pos                   (31U)
17437 #define PSSI_CR_OUTEN_Msk                   (0x1UL << PSSI_CR_OUTEN_Pos)            /*!< 0x80000000 */
17438 #define PSSI_CR_OUTEN                       PSSI_CR_OUTEN_Msk                       /*!< Data direction selection */
17439 
17440 /********************  Bit definition for PSSI_SR register  *******************/
17441 #define PSSI_SR_RTT4B_Pos                   (2U)
17442 #define PSSI_SR_RTT4B_Msk                   (0x1UL << PSSI_SR_RTT4B_Pos)            /*!< 0x00000004 */
17443 #define PSSI_SR_RTT4B                       PSSI_SR_RTT4B_Msk                       /*!< Ready to transfer four bytes */
17444 #define PSSI_SR_RTT1B_Pos                   (3U)
17445 #define PSSI_SR_RTT1B_Msk                   (0x1UL << PSSI_SR_RTT1B_Pos)            /*!< 0x00000008 */
17446 #define PSSI_SR_RTT1B                       PSSI_SR_RTT1B_Msk                       /*!< Ready to transfer one byte */
17447 
17448 /********************  Bit definition for PSSI_RIS register  *******************/
17449 #define PSSI_RIS_OVR_RIS_Pos                (1U)
17450 #define PSSI_RIS_OVR_RIS_Msk                (0x1UL << PSSI_RIS_OVR_RIS_Pos)         /*!< 0x00000002 */
17451 #define PSSI_RIS_OVR_RIS                    PSSI_RIS_OVR_RIS_Msk                    /*!< Data buffer overrun/underrun raw interrupt status */
17452 
17453 /********************  Bit definition for PSSI_IER register  *******************/
17454 #define PSSI_IER_OVR_IE_Pos                 (1U)
17455 #define PSSI_IER_OVR_IE_Msk                 (0x1UL << PSSI_IER_OVR_IE_Pos)          /*!< 0x00000002 */
17456 #define PSSI_IER_OVR_IE                     PSSI_IER_OVR_IE_Msk                     /*!< Data buffer overrun/underrun interrupt enable */
17457 
17458 /********************  Bit definition for PSSI_MIS register  *******************/
17459 #define PSSI_MIS_OVR_MIS_Pos                (1U)
17460 #define PSSI_MIS_OVR_MIS_Msk                (0x1UL << PSSI_MIS_OVR_MIS_Pos)         /*!< 0x00000002 */
17461 #define PSSI_MIS_OVR_MIS                    PSSI_MIS_OVR_MIS_Msk                    /*!< Data buffer overrun/underrun masked interrupt status */
17462 
17463 /********************  Bit definition for PSSI_ICR register  *******************/
17464 #define PSSI_ICR_OVR_ISC_Pos                (1U)
17465 #define PSSI_ICR_OVR_ISC_Msk                (0x1UL << PSSI_ICR_OVR_ISC_Pos)         /*!< 0x00000002 */
17466 #define PSSI_ICR_OVR_ISC                    PSSI_ICR_OVR_ISC_Msk                    /*!< Data buffer overrun/underrun interrupt status clear */
17467 
17468 /********************  Bit definition for PSSI_DR register  *******************/
17469 #define PSSI_DR_DR_Pos                      (0U)
17470 #define PSSI_DR_DR_Msk                      (0xFFFFFFFFUL << PSSI_DR_DR_Pos)        /*!< 0xFFFFFFF */
17471 #define PSSI_DR_DR                          PSSI_DR_DR_Msk                          /*!< Data register  */
17472 
17473 /******************************************************************************/
17474 /*                                                                            */
17475 /*                           SDMMC Interface                                  */
17476 /*                                                                            */
17477 /******************************************************************************/
17478 /******************  Bit definition for SDMMC_POWER register  ******************/
17479 #define SDMMC_POWER_PWRCTRL_Pos             (0U)
17480 #define SDMMC_POWER_PWRCTRL_Msk             (0x3UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
17481 #define SDMMC_POWER_PWRCTRL                 SDMMC_POWER_PWRCTRL_Msk                 /*!<PWRCTRL[1:0] bits (Power supply control bits) */
17482 #define SDMMC_POWER_PWRCTRL_0               (0x1UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
17483 #define SDMMC_POWER_PWRCTRL_1               (0x2UL << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
17484 #define SDMMC_POWER_VSWITCH_Pos             (2U)
17485 #define SDMMC_POWER_VSWITCH_Msk             (0x1UL << SDMMC_POWER_VSWITCH_Pos)      /*!< 0x00000004 */
17486 #define SDMMC_POWER_VSWITCH                 SDMMC_POWER_VSWITCH_Msk                 /*!<Voltage switch sequence start */
17487 #define SDMMC_POWER_VSWITCHEN_Pos           (3U)
17488 #define SDMMC_POWER_VSWITCHEN_Msk           (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)    /*!< 0x00000008 */
17489 #define SDMMC_POWER_VSWITCHEN               SDMMC_POWER_VSWITCHEN_Msk               /*!<Voltage switch procedure enable */
17490 #define SDMMC_POWER_DIRPOL_Pos              (4U)
17491 #define SDMMC_POWER_DIRPOL_Msk              (0x1UL << SDMMC_POWER_DIRPOL_Pos)       /*!< 0x00000010 */
17492 #define SDMMC_POWER_DIRPOL                  SDMMC_POWER_DIRPOL_Msk                  /*!<Data and Command direction signals polarity selection */
17493 
17494 /******************  Bit definition for SDMMC_CLKCR register  ******************/
17495 #define SDMMC_CLKCR_CLKDIV_Pos              (0U)
17496 #define SDMMC_CLKCR_CLKDIV_Msk              (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)     /*!< 0x000003FF */
17497 #define SDMMC_CLKCR_CLKDIV                  SDMMC_CLKCR_CLKDIV_Msk                  /*!<Clock divide factor             */
17498 #define SDMMC_CLKCR_PWRSAV_Pos              (12U)
17499 #define SDMMC_CLKCR_PWRSAV_Msk              (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00001000 */
17500 #define SDMMC_CLKCR_PWRSAV                  SDMMC_CLKCR_PWRSAV_Msk                  /*!<Power saving configuration bit  */
17501 #define SDMMC_CLKCR_WIDBUS_Pos              (14U)
17502 #define SDMMC_CLKCR_WIDBUS_Msk              (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x0000C000 */
17503 #define SDMMC_CLKCR_WIDBUS                  SDMMC_CLKCR_WIDBUS_Msk                  /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
17504 #define SDMMC_CLKCR_WIDBUS_0                (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00004000 */
17505 #define SDMMC_CLKCR_WIDBUS_1                (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00008000 */
17506 #define SDMMC_CLKCR_NEGEDGE_Pos             (16U)
17507 #define SDMMC_CLKCR_NEGEDGE_Msk             (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00010000 */
17508 #define SDMMC_CLKCR_NEGEDGE                 SDMMC_CLKCR_NEGEDGE_Msk                 /*!<SDMMC_CK dephasing selection bit */
17509 #define SDMMC_CLKCR_HWFC_EN_Pos             (17U)
17510 #define SDMMC_CLKCR_HWFC_EN_Msk             (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00020000 */
17511 #define SDMMC_CLKCR_HWFC_EN                 SDMMC_CLKCR_HWFC_EN_Msk                 /*!<HW Flow Control enable           */
17512 #define SDMMC_CLKCR_DDR_Pos                 (18U)
17513 #define SDMMC_CLKCR_DDR_Msk                 (0x1UL << SDMMC_CLKCR_DDR_Pos)          /*!< 0x00040000 */
17514 #define SDMMC_CLKCR_DDR                     SDMMC_CLKCR_DDR_Msk                     /*!<Data rate signaling selection    */
17515 #define SDMMC_CLKCR_BUSSPEED_Pos            (19U)
17516 #define SDMMC_CLKCR_BUSSPEED_Msk            (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)     /*!< 0x00080000 */
17517 #define SDMMC_CLKCR_BUSSPEED                SDMMC_CLKCR_BUSSPEED_Msk                /*!<Bus speed mode selection         */
17518 #define SDMMC_CLKCR_SELCLKRX_Pos            (20U)
17519 #define SDMMC_CLKCR_SELCLKRX_Msk            (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00300000 */
17520 #define SDMMC_CLKCR_SELCLKRX                SDMMC_CLKCR_SELCLKRX_Msk                /*!<SELCLKRX[1:0] bits (Receive clock selection) */
17521 #define SDMMC_CLKCR_SELCLKRX_0              (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00100000 */
17522 #define SDMMC_CLKCR_SELCLKRX_1              (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)     /*!< 0x00200000 */
17523 
17524 /*******************  Bit definition for SDMMC_ARG register  *******************/
17525 #define SDMMC_ARG_CMDARG_Pos                (0U)
17526 #define SDMMC_ARG_CMDARG_Msk                (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
17527 #define SDMMC_ARG_CMDARG                    SDMMC_ARG_CMDARG_Msk                    /*!<Command argument */
17528 
17529 /*******************  Bit definition for SDMMC_CMD register  *******************/
17530 #define SDMMC_CMD_CMDINDEX_Pos              (0U)
17531 #define SDMMC_CMD_CMDINDEX_Msk              (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
17532 #define SDMMC_CMD_CMDINDEX                  SDMMC_CMD_CMDINDEX_Msk                  /*!<Command Index                               */
17533 #define SDMMC_CMD_CMDTRANS_Pos              (6U)
17534 #define SDMMC_CMD_CMDTRANS_Msk              (0x1UL << SDMMC_CMD_CMDTRANS_Pos)       /*!< 0x00000040 */
17535 #define SDMMC_CMD_CMDTRANS                  SDMMC_CMD_CMDTRANS_Msk                  /*!<CPSM Treats command as a Data Transfer      */
17536 #define SDMMC_CMD_CMDSTOP_Pos               (7U)
17537 #define SDMMC_CMD_CMDSTOP_Msk               (0x1UL << SDMMC_CMD_CMDSTOP_Pos)        /*!< 0x00000080 */
17538 #define SDMMC_CMD_CMDSTOP                   SDMMC_CMD_CMDSTOP_Msk                   /*!<CPSM Treats command as a Stop               */
17539 #define SDMMC_CMD_WAITRESP_Pos              (8U)
17540 #define SDMMC_CMD_WAITRESP_Msk              (0x3UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000300 */
17541 #define SDMMC_CMD_WAITRESP                  SDMMC_CMD_WAITRESP_Msk                  /*!<WAITRESP[1:0] bits (Wait for response bits) */
17542 #define SDMMC_CMD_WAITRESP_0                (0x1UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000100 */
17543 #define SDMMC_CMD_WAITRESP_1                (0x2UL << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000200 */
17544 #define SDMMC_CMD_WAITINT_Pos               (10U)
17545 #define SDMMC_CMD_WAITINT_Msk               (0x1UL << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000400 */
17546 #define SDMMC_CMD_WAITINT                   SDMMC_CMD_WAITINT_Msk                   /*!<CPSM Waits for Interrupt Request                               */
17547 #define SDMMC_CMD_WAITPEND_Pos              (11U)
17548 #define SDMMC_CMD_WAITPEND_Msk              (0x1UL << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000800 */
17549 #define SDMMC_CMD_WAITPEND                  SDMMC_CMD_WAITPEND_Msk                  /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
17550 #define SDMMC_CMD_CPSMEN_Pos                (12U)
17551 #define SDMMC_CMD_CPSMEN_Msk                (0x1UL << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00001000 */
17552 #define SDMMC_CMD_CPSMEN                    SDMMC_CMD_CPSMEN_Msk                    /*!<Command path state machine (CPSM) Enable bit                   */
17553 #define SDMMC_CMD_DTHOLD_Pos                (13U)
17554 #define SDMMC_CMD_DTHOLD_Msk                (0x1UL << SDMMC_CMD_DTHOLD_Pos)         /*!< 0x00002000 */
17555 #define SDMMC_CMD_DTHOLD                    SDMMC_CMD_DTHOLD_Msk                    /*!<Hold new data block transmission and reception in the DPSM     */
17556 #define SDMMC_CMD_BOOTMODE_Pos              (14U)
17557 #define SDMMC_CMD_BOOTMODE_Msk              (0x1UL << SDMMC_CMD_BOOTMODE_Pos)       /*!< 0x00004000 */
17558 #define SDMMC_CMD_BOOTMODE                  SDMMC_CMD_BOOTMODE_Msk                  /*!<Boot mode                                                      */
17559 #define SDMMC_CMD_BOOTEN_Pos                (15U)
17560 #define SDMMC_CMD_BOOTEN_Msk                (0x1UL << SDMMC_CMD_BOOTEN_Pos)         /*!< 0x00008000 */
17561 #define SDMMC_CMD_BOOTEN                    SDMMC_CMD_BOOTEN_Msk                    /*!<Enable Boot mode procedure                                     */
17562 #define SDMMC_CMD_CMDSUSPEND_Pos            (16U)
17563 #define SDMMC_CMD_CMDSUSPEND_Msk            (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)     /*!< 0x00010000 */
17564 #define SDMMC_CMD_CMDSUSPEND                SDMMC_CMD_CMDSUSPEND_Msk                /*!<CPSM Treats command as a Suspend or Resume command             */
17565 
17566 /*****************  Bit definition for SDMMC_RESPCMD register  *****************/
17567 #define SDMMC_RESPCMD_RESPCMD_Pos           (0U)
17568 #define SDMMC_RESPCMD_RESPCMD_Msk           (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
17569 #define SDMMC_RESPCMD_RESPCMD               SDMMC_RESPCMD_RESPCMD_Msk               /*!<Response command index */
17570 
17571 /******************  Bit definition for SDMMC_RESP1 register  ******************/
17572 #define SDMMC_RESP1_CARDSTATUS1_Pos         (0U)
17573 #define SDMMC_RESP1_CARDSTATUS1_Msk         (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
17574 #define SDMMC_RESP1_CARDSTATUS1             SDMMC_RESP1_CARDSTATUS1_Msk             /*!<Card Status */
17575 
17576 /******************  Bit definition for SDMMC_RESP2 register  ******************/
17577 #define SDMMC_RESP2_CARDSTATUS2_Pos         (0U)
17578 #define SDMMC_RESP2_CARDSTATUS2_Msk         (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
17579 #define SDMMC_RESP2_CARDSTATUS2             SDMMC_RESP2_CARDSTATUS2_Msk             /*!<Card Status */
17580 
17581 /******************  Bit definition for SDMMC_RESP3 register  ******************/
17582 #define SDMMC_RESP3_CARDSTATUS3_Pos         (0U)
17583 #define SDMMC_RESP3_CARDSTATUS3_Msk         (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
17584 #define SDMMC_RESP3_CARDSTATUS3             SDMMC_RESP3_CARDSTATUS3_Msk             /*!<Card Status */
17585 
17586 /******************  Bit definition for SDMMC_RESP4 register  ******************/
17587 #define SDMMC_RESP4_CARDSTATUS4_Pos         (0U)
17588 #define SDMMC_RESP4_CARDSTATUS4_Msk         (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
17589 #define SDMMC_RESP4_CARDSTATUS4             SDMMC_RESP4_CARDSTATUS4_Msk             /*!<Card Status */
17590 
17591 /******************  Bit definition for SDMMC_DTIMER register  *****************/
17592 #define SDMMC_DTIMER_DATATIME_Pos           (0U)
17593 #define SDMMC_DTIMER_DATATIME_Msk           (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
17594 #define SDMMC_DTIMER_DATATIME               SDMMC_DTIMER_DATATIME_Msk               /*!<Data timeout period. */
17595 
17596 /******************  Bit definition for SDMMC_DLEN register  *******************/
17597 #define SDMMC_DLEN_DATALENGTH_Pos           (0U)
17598 #define SDMMC_DLEN_DATALENGTH_Msk           (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
17599 #define SDMMC_DLEN_DATALENGTH               SDMMC_DLEN_DATALENGTH_Msk               /*!<Data length value    */
17600 
17601 /******************  Bit definition for SDMMC_DCTRL register  ******************/
17602 #define SDMMC_DCTRL_DTEN_Pos                (0U)
17603 #define SDMMC_DCTRL_DTEN_Msk                (0x1UL << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
17604 #define SDMMC_DCTRL_DTEN                    SDMMC_DCTRL_DTEN_Msk                    /*!<Data transfer enabled bit                */
17605 #define SDMMC_DCTRL_DTDIR_Pos               (1U)
17606 #define SDMMC_DCTRL_DTDIR_Msk               (0x1UL << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
17607 #define SDMMC_DCTRL_DTDIR                   SDMMC_DCTRL_DTDIR_Msk                   /*!<Data transfer direction selection        */
17608 #define SDMMC_DCTRL_DTMODE_Pos              (2U)
17609 #define SDMMC_DCTRL_DTMODE_Msk              (0x3UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x0000000C */
17610 #define SDMMC_DCTRL_DTMODE                  SDMMC_DCTRL_DTMODE_Msk                  /*!<DTMODE[1:0] Data transfer mode selection */
17611 #define SDMMC_DCTRL_DTMODE_0                (0x1UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
17612 #define SDMMC_DCTRL_DTMODE_1                (0x2UL << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000008 */
17613 #define SDMMC_DCTRL_DBLOCKSIZE_Pos          (4U)
17614 #define SDMMC_DCTRL_DBLOCKSIZE_Msk          (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
17615 #define SDMMC_DCTRL_DBLOCKSIZE              SDMMC_DCTRL_DBLOCKSIZE_Msk              /*!<DBLOCKSIZE[3:0] bits (Data block size) */
17616 #define SDMMC_DCTRL_DBLOCKSIZE_0            (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
17617 #define SDMMC_DCTRL_DBLOCKSIZE_1            (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
17618 #define SDMMC_DCTRL_DBLOCKSIZE_2            (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
17619 #define SDMMC_DCTRL_DBLOCKSIZE_3            (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
17620 #define SDMMC_DCTRL_RWSTART_Pos             (8U)
17621 #define SDMMC_DCTRL_RWSTART_Msk             (0x1UL << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
17622 #define SDMMC_DCTRL_RWSTART                 SDMMC_DCTRL_RWSTART_Msk                 /*!<Read wait start                                 */
17623 #define SDMMC_DCTRL_RWSTOP_Pos              (9U)
17624 #define SDMMC_DCTRL_RWSTOP_Msk              (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
17625 #define SDMMC_DCTRL_RWSTOP                  SDMMC_DCTRL_RWSTOP_Msk                  /*!<Read wait stop                                  */
17626 #define SDMMC_DCTRL_RWMOD_Pos               (10U)
17627 #define SDMMC_DCTRL_RWMOD_Msk               (0x1UL << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
17628 #define SDMMC_DCTRL_RWMOD                   SDMMC_DCTRL_RWMOD_Msk                   /*!<Read wait mode                                  */
17629 #define SDMMC_DCTRL_SDIOEN_Pos              (11U)
17630 #define SDMMC_DCTRL_SDIOEN_Msk              (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
17631 #define SDMMC_DCTRL_SDIOEN                  SDMMC_DCTRL_SDIOEN_Msk                  /*!<SD I/O enable functions                         */
17632 #define SDMMC_DCTRL_BOOTACKEN_Pos           (12U)
17633 #define SDMMC_DCTRL_BOOTACKEN_Msk           (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)    /*!< 0x00001000 */
17634 #define SDMMC_DCTRL_BOOTACKEN               SDMMC_DCTRL_BOOTACKEN_Msk               /*!<Enable the reception of the Boot Acknowledgment */
17635 #define SDMMC_DCTRL_FIFORST_Pos             (13U)
17636 #define SDMMC_DCTRL_FIFORST_Msk             (0x1UL << SDMMC_DCTRL_FIFORST_Pos)      /*!< 0x00002000 */
17637 #define SDMMC_DCTRL_FIFORST                 SDMMC_DCTRL_FIFORST_Msk                 /*!<FIFO reset                                      */
17638 
17639 /******************  Bit definition for SDMMC_DCOUNT register  *****************/
17640 #define SDMMC_DCOUNT_DATACOUNT_Pos          (0U)
17641 #define SDMMC_DCOUNT_DATACOUNT_Msk          (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
17642 #define SDMMC_DCOUNT_DATACOUNT              SDMMC_DCOUNT_DATACOUNT_Msk              /*!<Data count value */
17643 
17644 /******************  Bit definition for SDMMC_STA register  ********************/
17645 #define SDMMC_STA_CCRCFAIL_Pos              (0U)
17646 #define SDMMC_STA_CCRCFAIL_Msk              (0x1UL << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
17647 #define SDMMC_STA_CCRCFAIL                  SDMMC_STA_CCRCFAIL_Msk                  /*!<Command response received (CRC check failed)  */
17648 #define SDMMC_STA_DCRCFAIL_Pos              (1U)
17649 #define SDMMC_STA_DCRCFAIL_Msk              (0x1UL << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
17650 #define SDMMC_STA_DCRCFAIL                  SDMMC_STA_DCRCFAIL_Msk                  /*!<Data block sent/received (CRC check failed)   */
17651 #define SDMMC_STA_CTIMEOUT_Pos              (2U)
17652 #define SDMMC_STA_CTIMEOUT_Msk              (0x1UL << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
17653 #define SDMMC_STA_CTIMEOUT                  SDMMC_STA_CTIMEOUT_Msk                  /*!<Command response timeout                      */
17654 #define SDMMC_STA_DTIMEOUT_Pos              (3U)
17655 #define SDMMC_STA_DTIMEOUT_Msk              (0x1UL << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
17656 #define SDMMC_STA_DTIMEOUT                  SDMMC_STA_DTIMEOUT_Msk                  /*!<Data timeout                                  */
17657 #define SDMMC_STA_TXUNDERR_Pos              (4U)
17658 #define SDMMC_STA_TXUNDERR_Msk              (0x1UL << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
17659 #define SDMMC_STA_TXUNDERR                  SDMMC_STA_TXUNDERR_Msk                  /*!<Transmit FIFO underrun error                  */
17660 #define SDMMC_STA_RXOVERR_Pos               (5U)
17661 #define SDMMC_STA_RXOVERR_Msk               (0x1UL << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
17662 #define SDMMC_STA_RXOVERR                   SDMMC_STA_RXOVERR_Msk                   /*!<Received FIFO overrun error                   */
17663 #define SDMMC_STA_CMDREND_Pos               (6U)
17664 #define SDMMC_STA_CMDREND_Msk               (0x1UL << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
17665 #define SDMMC_STA_CMDREND                   SDMMC_STA_CMDREND_Msk                   /*!<Command response received (CRC check passed)  */
17666 #define SDMMC_STA_CMDSENT_Pos               (7U)
17667 #define SDMMC_STA_CMDSENT_Msk               (0x1UL << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
17668 #define SDMMC_STA_CMDSENT                   SDMMC_STA_CMDSENT_Msk                   /*!<Command sent (no response required)           */
17669 #define SDMMC_STA_DATAEND_Pos               (8U)
17670 #define SDMMC_STA_DATAEND_Msk               (0x1UL << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
17671 #define SDMMC_STA_DATAEND                   SDMMC_STA_DATAEND_Msk                   /*!<Data end (data counter, SDIDCOUNT, is zero)   */
17672 #define SDMMC_STA_DHOLD_Pos                 (9U)
17673 #define SDMMC_STA_DHOLD_Msk                 (0x1UL << SDMMC_STA_DHOLD_Pos)          /*!< 0x00000200 */
17674 #define SDMMC_STA_DHOLD                     SDMMC_STA_DHOLD_Msk                     /*!<Data transfer Hold                                                      */
17675 #define SDMMC_STA_DBCKEND_Pos               (10U)
17676 #define SDMMC_STA_DBCKEND_Msk               (0x1UL << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
17677 #define SDMMC_STA_DBCKEND                   SDMMC_STA_DBCKEND_Msk                   /*!<Data block sent/received (CRC check passed)   */
17678 #define SDMMC_STA_DABORT_Pos                (11U)
17679 #define SDMMC_STA_DABORT_Msk                (0x1UL << SDMMC_STA_DABORT_Pos)         /*!< 0x00000800 */
17680 #define SDMMC_STA_DABORT                    SDMMC_STA_DABORT_Msk                    /*!<Data transfer aborted by CMD12                                          */
17681 #define SDMMC_STA_DPSMACT_Pos               (12U)
17682 #define SDMMC_STA_DPSMACT_Msk               (0x1UL << SDMMC_STA_DPSMACT_Pos)        /*!< 0x00001000 */
17683 #define SDMMC_STA_DPSMACT                   SDMMC_STA_DPSMACT_Msk                   /*!<Data path state machine active                                       */
17684 #define SDMMC_STA_CPSMACT_Pos               (13U)
17685 #define SDMMC_STA_CPSMACT_Msk               (0x1UL << SDMMC_STA_CPSMACT_Pos)        /*!< 0x00002000 */
17686 #define SDMMC_STA_CPSMACT                   SDMMC_STA_CPSMACT_Msk                   /*!<Command path state machine active                                          */
17687 #define SDMMC_STA_TXFIFOHE_Pos              (14U)
17688 #define SDMMC_STA_TXFIFOHE_Msk              (0x1UL << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
17689 #define SDMMC_STA_TXFIFOHE                  SDMMC_STA_TXFIFOHE_Msk                  /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
17690 #define SDMMC_STA_RXFIFOHF_Pos              (15U)
17691 #define SDMMC_STA_RXFIFOHF_Msk              (0x1UL << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
17692 #define SDMMC_STA_RXFIFOHF                  SDMMC_STA_RXFIFOHF_Msk                  /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
17693 #define SDMMC_STA_TXFIFOF_Pos               (16U)
17694 #define SDMMC_STA_TXFIFOF_Msk               (0x1UL << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
17695 #define SDMMC_STA_TXFIFOF                   SDMMC_STA_TXFIFOF_Msk                   /*!<Transmit FIFO full                            */
17696 #define SDMMC_STA_RXFIFOF_Pos               (17U)
17697 #define SDMMC_STA_RXFIFOF_Msk               (0x1UL << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
17698 #define SDMMC_STA_RXFIFOF                   SDMMC_STA_RXFIFOF_Msk                   /*!<Receive FIFO full                             */
17699 #define SDMMC_STA_TXFIFOE_Pos               (18U)
17700 #define SDMMC_STA_TXFIFOE_Msk               (0x1UL << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
17701 #define SDMMC_STA_TXFIFOE                   SDMMC_STA_TXFIFOE_Msk                   /*!<Transmit FIFO empty                           */
17702 #define SDMMC_STA_RXFIFOE_Pos               (19U)
17703 #define SDMMC_STA_RXFIFOE_Msk               (0x1UL << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
17704 #define SDMMC_STA_RXFIFOE                   SDMMC_STA_RXFIFOE_Msk                   /*!<Receive FIFO empty                            */
17705 #define SDMMC_STA_BUSYD0_Pos                (20U)
17706 #define SDMMC_STA_BUSYD0_Msk                (0x1UL << SDMMC_STA_BUSYD0_Pos)         /*!< 0x00100000 */
17707 #define SDMMC_STA_BUSYD0                    SDMMC_STA_BUSYD0_Msk                    /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
17708 #define SDMMC_STA_BUSYD0END_Pos             (21U)
17709 #define SDMMC_STA_BUSYD0END_Msk             (0x1UL << SDMMC_STA_BUSYD0END_Pos)      /*!< 0x00200000 */
17710 #define SDMMC_STA_BUSYD0END                 SDMMC_STA_BUSYD0END_Msk                 /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
17711 #define SDMMC_STA_SDIOIT_Pos                (22U)
17712 #define SDMMC_STA_SDIOIT_Msk                (0x1UL << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
17713 #define SDMMC_STA_SDIOIT                    SDMMC_STA_SDIOIT_Msk                    /*!<SDIO interrupt received                                                 */
17714 #define SDMMC_STA_ACKFAIL_Pos               (23U)
17715 #define SDMMC_STA_ACKFAIL_Msk               (0x1UL << SDMMC_STA_ACKFAIL_Pos)        /*!< 0x00800000 */
17716 #define SDMMC_STA_ACKFAIL                   SDMMC_STA_ACKFAIL_Msk                   /*!<Boot Acknowledgment received (BootAck check fail)                       */
17717 #define SDMMC_STA_ACKTIMEOUT_Pos            (24U)
17718 #define SDMMC_STA_ACKTIMEOUT_Msk            (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)     /*!< 0x01000000 */
17719 #define SDMMC_STA_ACKTIMEOUT                SDMMC_STA_ACKTIMEOUT_Msk                /*!<Boot Acknowledgment timeout                                             */
17720 #define SDMMC_STA_VSWEND_Pos                (25U)
17721 #define SDMMC_STA_VSWEND_Msk                (0x1UL << SDMMC_STA_VSWEND_Pos)         /*!< 0x02000000 */
17722 #define SDMMC_STA_VSWEND                    SDMMC_STA_VSWEND_Msk                    /*!<Voltage switch critical timing section completion                       */
17723 #define SDMMC_STA_CKSTOP_Pos                (26U)
17724 #define SDMMC_STA_CKSTOP_Msk                (0x1UL << SDMMC_STA_CKSTOP_Pos)         /*!< 0x04000000 */
17725 #define SDMMC_STA_CKSTOP                    SDMMC_STA_CKSTOP_Msk                    /*!<SDMMC_CK stopped in Voltage switch procedure                            */
17726 #define SDMMC_STA_IDMATE_Pos                (27U)
17727 #define SDMMC_STA_IDMATE_Msk                (0x1UL << SDMMC_STA_IDMATE_Pos)         /*!< 0x08000000 */
17728 #define SDMMC_STA_IDMATE                    SDMMC_STA_IDMATE_Msk                    /*!<IDMA transfer error                                                     */
17729 #define SDMMC_STA_IDMABTC_Pos               (28U)
17730 #define SDMMC_STA_IDMABTC_Msk               (0x1UL << SDMMC_STA_IDMABTC_Pos)        /*!< 0x10000000 */
17731 #define SDMMC_STA_IDMABTC                   SDMMC_STA_IDMABTC_Msk                   /*!<IDMA buffer transfer complete                                           */
17732 
17733 /*******************  Bit definition for SDMMC_ICR register  *******************/
17734 #define SDMMC_ICR_CCRCFAILC_Pos             (0U)
17735 #define SDMMC_ICR_CCRCFAILC_Msk             (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
17736 #define SDMMC_ICR_CCRCFAILC                 SDMMC_ICR_CCRCFAILC_Msk                 /*!<CCRCFAIL flag clear bit */
17737 #define SDMMC_ICR_DCRCFAILC_Pos             (1U)
17738 #define SDMMC_ICR_DCRCFAILC_Msk             (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
17739 #define SDMMC_ICR_DCRCFAILC                 SDMMC_ICR_DCRCFAILC_Msk                 /*!<DCRCFAIL flag clear bit */
17740 #define SDMMC_ICR_CTIMEOUTC_Pos             (2U)
17741 #define SDMMC_ICR_CTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
17742 #define SDMMC_ICR_CTIMEOUTC                 SDMMC_ICR_CTIMEOUTC_Msk                 /*!<CTIMEOUT flag clear bit */
17743 #define SDMMC_ICR_DTIMEOUTC_Pos             (3U)
17744 #define SDMMC_ICR_DTIMEOUTC_Msk             (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
17745 #define SDMMC_ICR_DTIMEOUTC                 SDMMC_ICR_DTIMEOUTC_Msk                 /*!<DTIMEOUT flag clear bit */
17746 #define SDMMC_ICR_TXUNDERRC_Pos             (4U)
17747 #define SDMMC_ICR_TXUNDERRC_Msk             (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
17748 #define SDMMC_ICR_TXUNDERRC                 SDMMC_ICR_TXUNDERRC_Msk                 /*!<TXUNDERR flag clear bit */
17749 #define SDMMC_ICR_RXOVERRC_Pos              (5U)
17750 #define SDMMC_ICR_RXOVERRC_Msk              (0x1UL << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
17751 #define SDMMC_ICR_RXOVERRC                  SDMMC_ICR_RXOVERRC_Msk                  /*!<RXOVERR flag clear bit  */
17752 #define SDMMC_ICR_CMDRENDC_Pos              (6U)
17753 #define SDMMC_ICR_CMDRENDC_Msk              (0x1UL << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
17754 #define SDMMC_ICR_CMDRENDC                  SDMMC_ICR_CMDRENDC_Msk                  /*!<CMDREND flag clear bit  */
17755 #define SDMMC_ICR_CMDSENTC_Pos              (7U)
17756 #define SDMMC_ICR_CMDSENTC_Msk              (0x1UL << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
17757 #define SDMMC_ICR_CMDSENTC                  SDMMC_ICR_CMDSENTC_Msk                  /*!<CMDSENT flag clear bit  */
17758 #define SDMMC_ICR_DATAENDC_Pos              (8U)
17759 #define SDMMC_ICR_DATAENDC_Msk              (0x1UL << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
17760 #define SDMMC_ICR_DATAENDC                  SDMMC_ICR_DATAENDC_Msk                  /*!<DATAEND flag clear bit  */
17761 #define SDMMC_ICR_DHOLDC_Pos                (9U)
17762 #define SDMMC_ICR_DHOLDC_Msk                (0x1UL << SDMMC_ICR_DHOLDC_Pos)         /*!< 0x00000200 */
17763 #define SDMMC_ICR_DHOLDC                    SDMMC_ICR_DHOLDC_Msk                    /*!<DHOLD flag clear bit       */
17764 #define SDMMC_ICR_DBCKENDC_Pos              (10U)
17765 #define SDMMC_ICR_DBCKENDC_Msk              (0x1UL << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
17766 #define SDMMC_ICR_DBCKENDC                  SDMMC_ICR_DBCKENDC_Msk                  /*!<DBCKEND flag clear bit  */
17767 #define SDMMC_ICR_DABORTC_Pos               (11U)
17768 #define SDMMC_ICR_DABORTC_Msk               (0x1UL << SDMMC_ICR_DABORTC_Pos)        /*!< 0x00000800 */
17769 #define SDMMC_ICR_DABORTC                   SDMMC_ICR_DABORTC_Msk                   /*!<DABORTC flag clear bit     */
17770 #define SDMMC_ICR_BUSYD0ENDC_Pos            (21U)
17771 #define SDMMC_ICR_BUSYD0ENDC_Msk            (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)     /*!< 0x00200000 */
17772 #define SDMMC_ICR_BUSYD0ENDC                SDMMC_ICR_BUSYD0ENDC_Msk                /*!<BUSYD0ENDC flag clear bit  */
17773 #define SDMMC_ICR_SDIOITC_Pos               (22U)
17774 #define SDMMC_ICR_SDIOITC_Msk               (0x1UL << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
17775 #define SDMMC_ICR_SDIOITC                   SDMMC_ICR_SDIOITC_Msk                   /*!<SDIOIT flag clear bit      */
17776 #define SDMMC_ICR_ACKFAILC_Pos              (23U)
17777 #define SDMMC_ICR_ACKFAILC_Msk              (0x1UL << SDMMC_ICR_ACKFAILC_Pos)       /*!< 0x00800000 */
17778 #define SDMMC_ICR_ACKFAILC                  SDMMC_ICR_ACKFAILC_Msk                  /*!<ACKFAILC flag clear bit    */
17779 #define SDMMC_ICR_ACKTIMEOUTC_Pos           (24U)
17780 #define SDMMC_ICR_ACKTIMEOUTC_Msk           (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)    /*!< 0x01000000 */
17781 #define SDMMC_ICR_ACKTIMEOUTC               SDMMC_ICR_ACKTIMEOUTC_Msk               /*!<ACKTIMEOUTC flag clear bit */
17782 #define SDMMC_ICR_VSWENDC_Pos               (25U)
17783 #define SDMMC_ICR_VSWENDC_Msk               (0x1UL << SDMMC_ICR_VSWENDC_Pos)        /*!< 0x02000000 */
17784 #define SDMMC_ICR_VSWENDC                   SDMMC_ICR_VSWENDC_Msk                   /*!<VSWENDC flag clear bit     */
17785 #define SDMMC_ICR_CKSTOPC_Pos               (26U)
17786 #define SDMMC_ICR_CKSTOPC_Msk               (0x1UL << SDMMC_ICR_CKSTOPC_Pos)        /*!< 0x04000000 */
17787 #define SDMMC_ICR_CKSTOPC                   SDMMC_ICR_CKSTOPC_Msk                   /*!<CKSTOPC flag clear bit     */
17788 #define SDMMC_ICR_IDMATEC_Pos               (27U)
17789 #define SDMMC_ICR_IDMATEC_Msk               (0x1UL << SDMMC_ICR_IDMATEC_Pos)        /*!< 0x08000000 */
17790 #define SDMMC_ICR_IDMATEC                   SDMMC_ICR_IDMATEC_Msk                   /*!<IDMATEC flag clear bit     */
17791 #define SDMMC_ICR_IDMABTCC_Pos              (28U)
17792 #define SDMMC_ICR_IDMABTCC_Msk              (0x1UL << SDMMC_ICR_IDMABTCC_Pos)       /*!< 0x10000000 */
17793 #define SDMMC_ICR_IDMABTCC                  SDMMC_ICR_IDMABTCC_Msk                  /*!<IDMABTCC flag clear bit    */
17794 
17795 /******************  Bit definition for SDMMC_MASK register  *******************/
17796 #define SDMMC_MASK_CCRCFAILIE_Pos           (0U)
17797 #define SDMMC_MASK_CCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
17798 #define SDMMC_MASK_CCRCFAILIE               SDMMC_MASK_CCRCFAILIE_Msk               /*!<Command CRC Fail Interrupt Enable          */
17799 #define SDMMC_MASK_DCRCFAILIE_Pos           (1U)
17800 #define SDMMC_MASK_DCRCFAILIE_Msk           (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
17801 #define SDMMC_MASK_DCRCFAILIE               SDMMC_MASK_DCRCFAILIE_Msk               /*!<Data CRC Fail Interrupt Enable             */
17802 #define SDMMC_MASK_CTIMEOUTIE_Pos           (2U)
17803 #define SDMMC_MASK_CTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
17804 #define SDMMC_MASK_CTIMEOUTIE               SDMMC_MASK_CTIMEOUTIE_Msk               /*!<Command TimeOut Interrupt Enable           */
17805 #define SDMMC_MASK_DTIMEOUTIE_Pos           (3U)
17806 #define SDMMC_MASK_DTIMEOUTIE_Msk           (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
17807 #define SDMMC_MASK_DTIMEOUTIE               SDMMC_MASK_DTIMEOUTIE_Msk               /*!<Data TimeOut Interrupt Enable              */
17808 #define SDMMC_MASK_TXUNDERRIE_Pos           (4U)
17809 #define SDMMC_MASK_TXUNDERRIE_Msk           (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
17810 #define SDMMC_MASK_TXUNDERRIE               SDMMC_MASK_TXUNDERRIE_Msk               /*!<Tx FIFO UnderRun Error Interrupt Enable    */
17811 #define SDMMC_MASK_RXOVERRIE_Pos            (5U)
17812 #define SDMMC_MASK_RXOVERRIE_Msk            (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
17813 #define SDMMC_MASK_RXOVERRIE                SDMMC_MASK_RXOVERRIE_Msk                /*!<Rx FIFO OverRun Error Interrupt Enable     */
17814 #define SDMMC_MASK_CMDRENDIE_Pos            (6U)
17815 #define SDMMC_MASK_CMDRENDIE_Msk            (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
17816 #define SDMMC_MASK_CMDRENDIE                SDMMC_MASK_CMDRENDIE_Msk                /*!<Command Response Received Interrupt Enable */
17817 #define SDMMC_MASK_CMDSENTIE_Pos            (7U)
17818 #define SDMMC_MASK_CMDSENTIE_Msk            (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
17819 #define SDMMC_MASK_CMDSENTIE                SDMMC_MASK_CMDSENTIE_Msk                /*!<Command Sent Interrupt Enable              */
17820 #define SDMMC_MASK_DATAENDIE_Pos            (8U)
17821 #define SDMMC_MASK_DATAENDIE_Msk            (0x1UL << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
17822 #define SDMMC_MASK_DATAENDIE                SDMMC_MASK_DATAENDIE_Msk                /*!<Data End Interrupt Enable                  */
17823 #define SDMMC_MASK_DHOLDIE_Pos              (9U)
17824 #define SDMMC_MASK_DHOLDIE_Msk              (0x1UL << SDMMC_MASK_DHOLDIE_Pos)       /*!< 0x00000200 */
17825 #define SDMMC_MASK_DHOLDIE                  SDMMC_MASK_DHOLDIE_Msk                  /*!<Data Hold Interrupt Enable                 */
17826 #define SDMMC_MASK_DBCKENDIE_Pos            (10U)
17827 #define SDMMC_MASK_DBCKENDIE_Msk            (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
17828 #define SDMMC_MASK_DBCKENDIE                SDMMC_MASK_DBCKENDIE_Msk                /*!<Data Block End Interrupt Enable            */
17829 #define SDMMC_MASK_DABORTIE_Pos             (11U)
17830 #define SDMMC_MASK_DABORTIE_Msk             (0x1UL << SDMMC_MASK_DABORTIE_Pos)      /*!< 0x00000800 */
17831 #define SDMMC_MASK_DABORTIE                 SDMMC_MASK_DABORTIE_Msk                 /*!<Data transfer aborted interrupt enable     */
17832 #define SDMMC_MASK_TXFIFOHEIE_Pos           (14U)
17833 #define SDMMC_MASK_TXFIFOHEIE_Msk           (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
17834 #define SDMMC_MASK_TXFIFOHEIE               SDMMC_MASK_TXFIFOHEIE_Msk               /*!<Tx FIFO Half Empty interrupt Enable        */
17835 #define SDMMC_MASK_RXFIFOHFIE_Pos           (15U)
17836 #define SDMMC_MASK_RXFIFOHFIE_Msk           (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
17837 #define SDMMC_MASK_RXFIFOHFIE               SDMMC_MASK_RXFIFOHFIE_Msk               /*!<Rx FIFO Half Full interrupt Enable         */
17838 #define SDMMC_MASK_RXFIFOFIE_Pos            (17U)
17839 #define SDMMC_MASK_RXFIFOFIE_Msk            (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
17840 #define SDMMC_MASK_RXFIFOFIE                SDMMC_MASK_RXFIFOFIE_Msk                /*!<Rx FIFO Full interrupt Enable              */
17841 #define SDMMC_MASK_TXFIFOEIE_Pos            (18U)
17842 #define SDMMC_MASK_TXFIFOEIE_Msk            (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
17843 #define SDMMC_MASK_TXFIFOEIE                SDMMC_MASK_TXFIFOEIE_Msk                /*!<Tx FIFO Empty interrupt Enable             */
17844 #define SDMMC_MASK_BUSYD0ENDIE_Pos          (21U)
17845 #define SDMMC_MASK_BUSYD0ENDIE_Msk          (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)   /*!< 0x00200000 */
17846 #define SDMMC_MASK_BUSYD0ENDIE              SDMMC_MASK_BUSYD0ENDIE_Msk              /*!<BUSYD0ENDIE interrupt Enable */
17847 #define SDMMC_MASK_SDIOITIE_Pos             (22U)
17848 #define SDMMC_MASK_SDIOITIE_Msk             (0x1UL << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
17849 #define SDMMC_MASK_SDIOITIE                 SDMMC_MASK_SDIOITIE_Msk                 /*!<SDMMC Mode Interrupt Received interrupt Enable */
17850 #define SDMMC_MASK_ACKFAILIE_Pos            (23U)
17851 #define SDMMC_MASK_ACKFAILIE_Msk            (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)     /*!< 0x00800000 */
17852 #define SDMMC_MASK_ACKFAILIE                SDMMC_MASK_ACKFAILIE_Msk                /*!<Acknowledgment Fail Interrupt Enable */
17853 #define SDMMC_MASK_ACKTIMEOUTIE_Pos         (24U)
17854 #define SDMMC_MASK_ACKTIMEOUTIE_Msk         (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)  /*!< 0x01000000 */
17855 #define SDMMC_MASK_ACKTIMEOUTIE             SDMMC_MASK_ACKTIMEOUTIE_Msk             /*!<Acknowledgment timeout Interrupt Enable */
17856 #define SDMMC_MASK_VSWENDIE_Pos             (25U)
17857 #define SDMMC_MASK_VSWENDIE_Msk             (0x1UL << SDMMC_MASK_VSWENDIE_Pos)      /*!< 0x02000000 */
17858 #define SDMMC_MASK_VSWENDIE                 SDMMC_MASK_VSWENDIE_Msk                 /*!<Voltage switch critical timing section completion Interrupt Enable */
17859 #define SDMMC_MASK_CKSTOPIE_Pos             (26U)
17860 #define SDMMC_MASK_CKSTOPIE_Msk             (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)      /*!< 0x04000000 */
17861 #define SDMMC_MASK_CKSTOPIE                 SDMMC_MASK_CKSTOPIE_Msk                 /*!<Voltage Switch clock stopped Interrupt Enable */
17862 #define SDMMC_MASK_IDMABTCIE_Pos            (28U)
17863 #define SDMMC_MASK_IDMABTCIE_Msk            (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)     /*!< 0x10000000 */
17864 #define SDMMC_MASK_IDMABTCIE                SDMMC_MASK_IDMABTCIE_Msk                /*!<IDMA buffer transfer complete Interrupt Enable */
17865 
17866 /*****************  Bit definition for SDMMC_ACKTIME register  *****************/
17867 #define SDMMC_ACKTIME_ACKTIME_Pos           (0U)
17868 #define SDMMC_ACKTIME_ACKTIME_Msk           (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
17869 #define SDMMC_ACKTIME_ACKTIME               SDMMC_ACKTIME_ACKTIME_Msk               /*!<Boot acknowledgment timeout period */
17870 
17871 /******************  Bit definition for SDMMC_FIFO register  *******************/
17872 #define SDMMC_FIFO_FIFODATA_Pos             (0U)
17873 #define SDMMC_FIFO_FIFODATA_Msk             (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
17874 #define SDMMC_FIFO_FIFODATA                 SDMMC_FIFO_FIFODATA_Msk                 /*!<Receive and transmit FIFO data */
17875 
17876 /******************  Bit definition for SDMMC_IDMACTRL register ****************/
17877 #define SDMMC_IDMA_IDMAEN_Pos               (0U)
17878 #define SDMMC_IDMA_IDMAEN_Msk               (0x1UL << SDMMC_IDMA_IDMAEN_Pos)        /*!< 0x00000001 */
17879 #define SDMMC_IDMA_IDMAEN                   SDMMC_IDMA_IDMAEN_Msk                   /*!< Enable the internal DMA of the SDMMC peripheral */
17880 #define SDMMC_IDMA_IDMABMODE_Pos            (1U)
17881 #define SDMMC_IDMA_IDMABMODE_Msk            (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)     /*!< 0x00000002 */
17882 #define SDMMC_IDMA_IDMABMODE                SDMMC_IDMA_IDMABMODE_Msk                /*!< Enable Linked List mode for IDMA */
17883 
17884 /*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
17885 #define SDMMC_IDMABSIZE_IDMABNDT_Pos        (5U)
17886 #define SDMMC_IDMABSIZE_IDMABNDT_Msk        (0xFFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x0000FFE0 */
17887 #define SDMMC_IDMABSIZE_IDMABNDT            SDMMC_IDMABSIZE_IDMABNDT_Msk            /*!< Number of transfers per buffer */
17888 
17889 /*****************  Bit definition for SDMMC_IDMABASER register  ***************/
17890 #define SDMMC_IDMABASER_IDMABASER           ((uint32_t)0xFFFFFFFF)                  /*!< Memory base address register */
17891 
17892 /*****************  Bit definition for SDMMC_IDMALAR) register  ***************/
17893 #define SDMMC_IDMALAR_IDMALA_Pos            (0U)
17894 #define SDMMC_IDMALAR_IDMALA_Msk            (0x3FFFUL << SDMMC_IDMALAR_IDMALA_Pos)  /*!< 0x00003FFF */
17895 #define SDMMC_IDMALAR_IDMALA                SDMMC_IDMALAR_IDMALA_Msk                /*!< Linked list item address offset */
17896 #define SDMMC_IDMALAR_ABR_Pos               (29U)
17897 #define SDMMC_IDMALAR_ABR_Msk               (0x1UL << SDMMC_IDMALAR_ABR_Pos)        /*!< 0x20000000 */
17898 #define SDMMC_IDMALAR_ABR                   SDMMC_IDMALAR_ABR_Msk                   /*!< Acknowledge linked list buffer ready */
17899 #define SDMMC_IDMALAR_ULS_Pos               (30U)
17900 #define SDMMC_IDMALAR_ULS_Msk               (0x1UL << SDMMC_IDMALAR_ULS_Pos)        /*!< 0x40000000 */
17901 #define SDMMC_IDMALAR_ULS                   SDMMC_IDMALAR_ULS_Msk                   /*!< Update Size from linked list */
17902 #define SDMMC_IDMALAR_ULA_Pos               (31U)
17903 #define SDMMC_IDMALAR_ULA_Msk               (0x1UL << SDMMC_IDMALAR_ULA_Pos)        /*!< 0x80000000 */
17904 #define SDMMC_IDMALAR_ULA                   SDMMC_IDMALAR_ULA_Msk                   /*!< Update Address from linked list */
17905 
17906 /*****************  Bit definition for SDMMC_IDMABAR) register  ***************/
17907 #define SDMMC_IDMABAR_IDMABAR               ((uint32_t)0xFFFFFFFF)                  /*!< linked list memory base register */
17908 
17909 /******************************************************************************/
17910 /*                                                                            */
17911 /*                          XSPI  (HSPI/OCTOSPI)                              */
17912 /*                                                                            */
17913 /******************************************************************************/
17914 /************  Bit definition for XSPI_CR register  **************************/
17915 #define XSPI_CR_EN_Pos                   (0U)
17916 #define XSPI_CR_EN_Msk                   (0x1UL << XSPI_CR_EN_Pos)                        /*!< 0x00000001 */
17917 #define XSPI_CR_EN                       XSPI_CR_EN_Msk                                   /*!< Enable */
17918 #define XSPI_CR_ABORT_Pos                (1U)
17919 #define XSPI_CR_ABORT_Msk                (0x1UL << XSPI_CR_ABORT_Pos)                     /*!< 0x00000002 */
17920 #define XSPI_CR_ABORT                    XSPI_CR_ABORT_Msk                                /*!< Abort request */
17921 #define XSPI_CR_DMAEN_Pos                (2U)
17922 #define XSPI_CR_DMAEN_Msk                (0x1UL << XSPI_CR_DMAEN_Pos)                     /*!< 0x00000004 */
17923 #define XSPI_CR_DMAEN                    XSPI_CR_DMAEN_Msk                                /*!< DMA Enable */
17924 #define XSPI_CR_TCEN_Pos                 (3U)
17925 #define XSPI_CR_TCEN_Msk                 (0x1UL << XSPI_CR_TCEN_Pos)                      /*!< 0x00000008 */
17926 #define XSPI_CR_TCEN                     XSPI_CR_TCEN_Msk                                 /*!< Timeout Counter Enable */
17927 #define XSPI_CR_DMM_Pos                  (6U)
17928 #define XSPI_CR_DMM_Msk                  (0x1UL << XSPI_CR_DMM_Pos)                       /*!< 0x00000040 */
17929 #define XSPI_CR_DMM                      XSPI_CR_DMM_Msk                                  /*!< Dual Memory Mode */
17930 #define XSPI_OCTOSPI_CR_MSEL_Pos         (7U)
17931 #define XSPI_OCTOSPI_CR_MSEL_Msk         (0x1UL << XSPI_OCTOSPI_CR_MSEL_Pos)              /*!< 0x00000080 */
17932 #define XSPI_OCTOSPI_CR_MSEL             XSPI_OCTOSPI_CR_MSEL_Msk                         /*!< Memory Select */
17933 #define XSPI_CR_FTHRES_Pos               (8U)
17934 #define XSPI_CR_FTHRES_Msk               (0x3FUL << XSPI_CR_FTHRES_Pos)                   /*!< 0x00003F00 */
17935 #define XSPI_CR_FTHRES                   XSPI_CR_FTHRES_Msk                               /*!< FIFO Threshold Level */
17936 #define XSPI_CR_TEIE_Pos                 (16U)
17937 #define XSPI_CR_TEIE_Msk                 (0x1UL << XSPI_CR_TEIE_Pos)                      /*!< 0x00010000 */
17938 #define XSPI_CR_TEIE                     XSPI_CR_TEIE_Msk                                 /*!< Transfer Error Interrupt Enable */
17939 #define XSPI_CR_TCIE_Pos                 (17U)
17940 #define XSPI_CR_TCIE_Msk                 (0x1UL << XSPI_CR_TCIE_Pos)                      /*!< 0x00020000 */
17941 #define XSPI_CR_TCIE                     XSPI_CR_TCIE_Msk                                 /*!< Transfer Complete Interrupt Enable */
17942 #define XSPI_CR_FTIE_Pos                 (18U)
17943 #define XSPI_CR_FTIE_Msk                 (0x1UL << XSPI_CR_FTIE_Pos)                      /*!< 0x00040000 */
17944 #define XSPI_CR_FTIE                     XSPI_CR_FTIE_Msk                                 /*!< FIFO Threshold Interrupt Enable */
17945 #define XSPI_CR_SMIE_Pos                 (19U)
17946 #define XSPI_CR_SMIE_Msk                 (0x1UL << XSPI_CR_SMIE_Pos)                      /*!< 0x00080000 */
17947 #define XSPI_CR_SMIE                     XSPI_CR_SMIE_Msk                                 /*!< Status Match Interrupt Enable */
17948 #define XSPI_CR_TOIE_Pos                 (20U)
17949 #define XSPI_CR_TOIE_Msk                 (0x1UL << XSPI_CR_TOIE_Pos)                      /*!< 0x00100000 */
17950 #define XSPI_CR_TOIE                     XSPI_CR_TOIE_Msk                                 /*!< TimeOut Interrupt Enable */
17951 #define XSPI_CR_APMS_Pos                 (22U)
17952 #define XSPI_CR_APMS_Msk                 (0x1UL << XSPI_CR_APMS_Pos)                      /*!< 0x00400000 */
17953 #define XSPI_CR_APMS                     XSPI_CR_APMS_Msk                                 /*!< Automatic Poll Mode Stop */
17954 #define XSPI_CR_PMM_Pos                  (23U)
17955 #define XSPI_CR_PMM_Msk                  (0x1UL << XSPI_CR_PMM_Pos)                       /*!< 0x00800000 */
17956 #define XSPI_CR_PMM                      XSPI_CR_PMM_Msk                                  /*!< Polling Match Mode */
17957 #define XSPI_CR_FMODE_Pos                (28U)
17958 #define XSPI_CR_FMODE_Msk                (0x3UL << XSPI_CR_FMODE_Pos)                     /*!< 0x30000000 */
17959 #define XSPI_CR_FMODE                    XSPI_CR_FMODE_Msk                                /*!< Functional Mode */
17960 #define XSPI_CR_FMODE_0                  (0x1UL << XSPI_CR_FMODE_Pos)                     /*!< 0x10000000 */
17961 #define XSPI_CR_FMODE_1                  (0x2UL << XSPI_CR_FMODE_Pos)                     /*!< 0x20000000 */
17962 #define XSPI_HSPI_CR_MSEL_Pos            (30U)
17963 #define XSPI_HSPI_CR_MSEL_Msk            (0x3UL << XSPI_HSPI_CR_MSEL_Pos)                 /*!< 0xC0000000 */
17964 #define XSPI_HSPI_CR_MSEL                XSPI_HSPI_CR_MSEL_Msk                            /*!< Memory Select only for HSPI, Invalid for OCTOSPI */
17965 #define XSPI_HSPI_CR_MSEL_0              (0x1UL << XSPI_HSPI_CR_MSEL_Pos)                 /*!< 0x40000000 */
17966 #define XSPI_HSPI_CR_MSEL_1              (0x2UL << XSPI_HSPI_CR_MSEL_Pos)                 /*!< 0x80000000 */
17967 
17968 /*************  Bit definition for XSPI_DCR1 register  ***********************/
17969 #define XSPI_DCR1_CKMODE_Pos             (0U)
17970 #define XSPI_DCR1_CKMODE_Msk             (0x1UL << XSPI_DCR1_CKMODE_Pos)                  /*!< 0x00000001 */
17971 #define XSPI_DCR1_CKMODE                 XSPI_DCR1_CKMODE_Msk                             /*!< Mode 0 / Mode 3 */
17972 #define XSPI_DCR1_FRCK_Pos               (1U)
17973 #define XSPI_DCR1_FRCK_Msk               (0x1UL << XSPI_DCR1_FRCK_Pos)                    /*!< 0x00000002 */
17974 #define XSPI_DCR1_FRCK                   XSPI_DCR1_FRCK_Msk                               /*!< Free Running Clock */
17975 #define XSPI_OCTOSPI_DCR1_DLYBYP_Pos     (3U)
17976 #define XSPI_OCTOSPI_DCR1_DLYBYP_Msk     (0x1UL << XSPI_OCTOSPI_DCR1_DLYBYP_Pos)          /*!< 0x00000008 */
17977 #define XSPI_OCTOSPI_DCR1_DLYBYP         XSPI_OCTOSPI_DCR1_DLYBYP_Msk                     /*!< Delay Block Bypass only for OCTOSPI */
17978 #define XSPI_DCR1_CSHT_Pos               (8U)
17979 #define XSPI_DCR1_CSHT_Msk               (0x3FUL << XSPI_DCR1_CSHT_Pos)                   /*!< 0x00003F00 */
17980 #define XSPI_DCR1_CSHT                   XSPI_DCR1_CSHT_Msk                               /*!< Chip Select High Time */
17981 #define XSPI_DCR1_DEVSIZE_Pos            (16U)
17982 #define XSPI_DCR1_DEVSIZE_Msk            (0x1FUL << XSPI_DCR1_DEVSIZE_Pos)                /*!< 0x001F0000 */
17983 #define XSPI_DCR1_DEVSIZE                XSPI_DCR1_DEVSIZE_Msk                            /*!< Device Size */
17984 #define XSPI_DCR1_MTYP_Pos               (24U)
17985 #define XSPI_DCR1_MTYP_Msk               (0x7UL << XSPI_DCR1_MTYP_Pos)                    /*!< 0x07000000 */
17986 #define XSPI_DCR1_MTYP                   XSPI_DCR1_MTYP_Msk                               /*!< Memory Type */
17987 #define XSPI_DCR1_MTYP_0                 (0x1UL << XSPI_DCR1_MTYP_Pos)                    /*!< 0x01000000 */
17988 #define XSPI_DCR1_MTYP_1                 (0x2UL << XSPI_DCR1_MTYP_Pos)                    /*!< 0x02000000 */
17989 #define XSPI_DCR1_MTYP_2                 (0x4UL << XSPI_DCR1_MTYP_Pos)                    /*!< 0x04000000 */
17990 
17991 /**************** Bit definition for XSPI_DCR2 register  *********************/
17992 #define XSPI_DCR2_PRESCALER_Pos          (0U)
17993 #define XSPI_DCR2_PRESCALER_Msk          (0xFFUL << XSPI_DCR2_PRESCALER_Pos)              /*!< 0x000000FF */
17994 #define XSPI_DCR2_PRESCALER              XSPI_DCR2_PRESCALER_Msk                          /*!< Clock prescaler */
17995 #define XSPI_DCR2_WRAPSIZE_Pos           (16U)
17996 #define XSPI_DCR2_WRAPSIZE_Msk           (0x7UL << XSPI_DCR2_WRAPSIZE_Pos)                /*!< 0x00070000 */
17997 #define XSPI_DCR2_WRAPSIZE               XSPI_DCR2_WRAPSIZE_Msk                           /*!< Wrap Size */
17998 #define XSPI_DCR2_WRAPSIZE_0             (0x1UL << XSPI_DCR2_WRAPSIZE_Pos)                /*!< 0x00010000 */
17999 #define XSPI_DCR2_WRAPSIZE_1             (0x2UL << XSPI_DCR2_WRAPSIZE_Pos)                /*!< 0x00020000 */
18000 #define XSPI_DCR2_WRAPSIZE_2             (0x4UL << XSPI_DCR2_WRAPSIZE_Pos)                /*!< 0x00040000 */
18001 
18002 /****************  Bit definition for XSPI_DCR3 register  ********************/
18003 #define XSPI_OCTOSPI_DCR3_MAXTRAN_Pos    (0U)
18004 #define XSPI_OCTOSPI_DCR3_MAXTRAN_Msk    (0xFFUL << XSPI_OCTOSPI_DCR3_MAXTRAN_Pos)        /*!< 0x000000FF */
18005 #define XSPI_OCTOSPI_DCR3_MAXTRAN        XSPI_OCTOSPI_DCR3_MAXTRAN_Msk                    /*!< Maximum transfer only for OCTOSPI */
18006 #define XSPI_DCR3_CSBOUND_Pos            (16U)
18007 #define XSPI_DCR3_CSBOUND_Msk            (0x1FUL << XSPI_DCR3_CSBOUND_Pos)                /*!< 0x001F0000 */
18008 #define XSPI_DCR3_CSBOUND                XSPI_DCR3_CSBOUND_Msk                            /*!< Maximum transfer */
18009 /****************  Bit definition for XSPI_DCR4 register  ********************/
18010 #define XSPI_DCR4_REFRESH_Pos            (0U)
18011 #define XSPI_DCR4_REFRESH_Msk            (0xFFFFFFFFUL << XSPI_DCR4_REFRESH_Pos)          /*!< 0xFFFFFFFF */
18012 #define XSPI_DCR4_REFRESH                XSPI_DCR4_REFRESH_Msk                            /*!< Refresh rate */
18013 
18014 /*****************  Bit definition for XSPI_SR  register  ********************/
18015 #define XSPI_SR_TEF_Pos                  (0U)
18016 #define XSPI_SR_TEF_Msk                  (0x1UL << XSPI_SR_TEF_Pos)                       /*!< 0x00000001 */
18017 #define XSPI_SR_TEF                      XSPI_SR_TEF_Msk                                  /*!< Transfer Error Flag */
18018 #define XSPI_SR_TCF_Pos                  (1U)
18019 #define XSPI_SR_TCF_Msk                  (0x1UL << XSPI_SR_TCF_Pos)                       /*!< 0x00000002 */
18020 #define XSPI_SR_TCF                      XSPI_SR_TCF_Msk                                  /*!< Transfer Complete Flag */
18021 #define XSPI_SR_FTF_Pos                  (2U)
18022 #define XSPI_SR_FTF_Msk                  (0x1UL << XSPI_SR_FTF_Pos)                       /*!< 0x00000004 */
18023 #define XSPI_SR_FTF                      XSPI_SR_FTF_Msk                                  /*!< FIFO Threshold Flag */
18024 #define XSPI_SR_SMF_Pos                  (3U)
18025 #define XSPI_SR_SMF_Msk                  (0x1UL << XSPI_SR_SMF_Pos)                       /*!< 0x00000008 */
18026 #define XSPI_SR_SMF                      XSPI_SR_SMF_Msk                                  /*!< Status Match Flag */
18027 #define XSPI_SR_TOF_Pos                  (4U)
18028 #define XSPI_SR_TOF_Msk                  (0x1UL << XSPI_SR_TOF_Pos)                       /*!< 0x00000010 */
18029 #define XSPI_SR_TOF                      XSPI_SR_TOF_Msk                                  /*!< Timeout Flag */
18030 #define XSPI_SR_BUSY_Pos                 (5U)
18031 #define XSPI_SR_BUSY_Msk                 (0x1UL << XSPI_SR_BUSY_Pos)                      /*!< 0x00000020 */
18032 #define XSPI_SR_BUSY                     XSPI_SR_BUSY_Msk                                 /*!< Busy */
18033 #define XSPI_SR_FLEVEL_Pos               (8U)
18034 #define XSPI_SR_FLEVEL_Msk               (0x7FUL << XSPI_SR_FLEVEL_Pos)                   /*!< 0x00007F00 */
18035 #define XSPI_SR_FLEVEL                   XSPI_SR_FLEVEL_Msk                               /*!< FIFO Level */
18036 
18037 /****************  Bit definition for XSPI_FCR register  *********************/
18038 #define XSPI_FCR_CTEF_Pos                (0U)
18039 #define XSPI_FCR_CTEF_Msk                (0x1UL << XSPI_FCR_CTEF_Pos)                     /*!< 0x00000001 */
18040 #define XSPI_FCR_CTEF                    XSPI_FCR_CTEF_Msk                                /*!< Clear Transfer Error Flag */
18041 #define XSPI_FCR_CTCF_Pos                (1U)
18042 #define XSPI_FCR_CTCF_Msk                (0x1UL << XSPI_FCR_CTCF_Pos)                     /*!< 0x00000002 */
18043 #define XSPI_FCR_CTCF                    XSPI_FCR_CTCF_Msk                                /*!< Clear Transfer Complete Flag */
18044 #define XSPI_FCR_CSMF_Pos                (3U)
18045 #define XSPI_FCR_CSMF_Msk                (0x1UL << XSPI_FCR_CSMF_Pos)                     /*!< 0x00000008 */
18046 #define XSPI_FCR_CSMF                    XSPI_FCR_CSMF_Msk                                /*!< Clear Status Match Flag */
18047 #define XSPI_FCR_CTOF_Pos                (4U)
18048 #define XSPI_FCR_CTOF_Msk                (0x1UL << XSPI_FCR_CTOF_Pos)                     /*!< 0x00000010 */
18049 #define XSPI_FCR_CTOF                    XSPI_FCR_CTOF_Msk                                /*!< Clear Timeout Flag */
18050 
18051 /****************  Bit definition for XSPI_DLR register  *********************/
18052 #define XSPI_DLR_DL_Pos                  (0U)
18053 #define XSPI_DLR_DL_Msk                  (0xFFFFFFFFUL << XSPI_DLR_DL_Pos)                /*!< 0xFFFFFFFF */
18054 #define XSPI_DLR_DL                      XSPI_DLR_DL_Msk                                  /*!< Data Length */
18055 
18056 /*****************  Bit definition for XSPI_AR register  *********************/
18057 #define XSPI_AR_ADDRESS_Pos              (0U)
18058 #define XSPI_AR_ADDRESS_Msk              (0xFFFFFFFFUL << XSPI_AR_ADDRESS_Pos)            /*!< 0xFFFFFFFF */
18059 #define XSPI_AR_ADDRESS                  XSPI_AR_ADDRESS_Msk                              /*!< Address */
18060 
18061 /*****************  Bit definition for XSPI_DR register  *********************/
18062 #define XSPI_DR_DATA_Pos                 (0U)
18063 #define XSPI_DR_DATA_Msk                 (0xFFFFFFFFUL << XSPI_DR_DATA_Pos)               /*!< 0xFFFFFFFF */
18064 #define XSPI_DR_DATA                     XSPI_DR_DATA_Msk                                 /*!< Data */
18065 
18066 /***************  Bit definition for XSPI_PSMKR register  ********************/
18067 #define XSPI_PSMKR_MASK_Pos              (0U)
18068 #define XSPI_PSMKR_MASK_Msk              (0xFFFFFFFFUL << XSPI_PSMKR_MASK_Pos)            /*!< 0xFFFFFFFF */
18069 #define XSPI_PSMKR_MASK                  XSPI_PSMKR_MASK_Msk                              /*!< Status mask */
18070 
18071 /***************  Bit definition for XSPI_PSMAR register  ********************/
18072 #define XSPI_PSMAR_MATCH_Pos             (0U)
18073 #define XSPI_PSMAR_MATCH_Msk             (0xFFFFFFFFUL << XSPI_PSMAR_MATCH_Pos)           /*!< 0xFFFFFFFF */
18074 #define XSPI_PSMAR_MATCH                 XSPI_PSMAR_MATCH_Msk                             /*!< Status match */
18075 
18076 /****************  Bit definition for XSPI_PIR register  *********************/
18077 #define XSPI_PIR_INTERVAL_Pos            (0U)
18078 #define XSPI_PIR_INTERVAL_Msk            (0xFFFFUL << XSPI_PIR_INTERVAL_Pos)              /*!< 0x0000FFFF */
18079 #define XSPI_PIR_INTERVAL                XSPI_PIR_INTERVAL_Msk                            /*!< Polling Interval */
18080 
18081 /****************  Bit definition for XSPI_CCR register  *********************/
18082 #define XSPI_CCR_IMODE_Pos               (0U)
18083 #define XSPI_CCR_IMODE_Msk               (0x7UL << XSPI_CCR_IMODE_Pos)                    /*!< 0x00000007 */
18084 #define XSPI_CCR_IMODE                   XSPI_CCR_IMODE_Msk                               /*!< Instruction Mode */
18085 #define XSPI_CCR_IMODE_0                 (0x1UL << XSPI_CCR_IMODE_Pos)                    /*!< 0x00000001 */
18086 #define XSPI_CCR_IMODE_1                 (0x2UL << XSPI_CCR_IMODE_Pos)                    /*!< 0x00000002 */
18087 #define XSPI_CCR_IMODE_2                 (0x4UL << XSPI_CCR_IMODE_Pos)                    /*!< 0x00000004 */
18088 #define XSPI_CCR_IDTR_Pos                (3U)
18089 #define XSPI_CCR_IDTR_Msk                (0x1UL << XSPI_CCR_IDTR_Pos)                     /*!< 0x00000008 */
18090 #define XSPI_CCR_IDTR                    XSPI_CCR_IDTR_Msk                                /*!< Instruction Double Transfer Rate */
18091 #define XSPI_CCR_ISIZE_Pos               (4U)
18092 #define XSPI_CCR_ISIZE_Msk               (0x3UL << XSPI_CCR_ISIZE_Pos)                    /*!< 0x00000030 */
18093 #define XSPI_CCR_ISIZE                   XSPI_CCR_ISIZE_Msk                               /*!< Instruction Size */
18094 #define XSPI_CCR_ISIZE_0                 (0x1UL << XSPI_CCR_ISIZE_Pos)                    /*!< 0x00000010 */
18095 #define XSPI_CCR_ISIZE_1                 (0x2UL << XSPI_CCR_ISIZE_Pos)                    /*!< 0x00000020 */
18096 #define XSPI_CCR_ADMODE_Pos              (8U)
18097 #define XSPI_CCR_ADMODE_Msk              (0x7UL << XSPI_CCR_ADMODE_Pos)                   /*!< 0x00000700 */
18098 #define XSPI_CCR_ADMODE                  XSPI_CCR_ADMODE_Msk                              /*!< Address Mode */
18099 #define XSPI_CCR_ADMODE_0                (0x1UL << XSPI_CCR_ADMODE_Pos)                   /*!< 0x00000100 */
18100 #define XSPI_CCR_ADMODE_1                (0x2UL << XSPI_CCR_ADMODE_Pos)                   /*!< 0x00000200 */
18101 #define XSPI_CCR_ADMODE_2                (0x4UL << XSPI_CCR_ADMODE_Pos)                   /*!< 0x00000400 */
18102 #define XSPI_CCR_ADDTR_Pos               (11U)
18103 #define XSPI_CCR_ADDTR_Msk               (0x1UL << XSPI_CCR_ADDTR_Pos)                    /*!< 0x00000800 */
18104 #define XSPI_CCR_ADDTR                   XSPI_CCR_ADDTR_Msk                               /*!< Address Double Transfer Rate */
18105 #define XSPI_CCR_ADSIZE_Pos              (12U)
18106 #define XSPI_CCR_ADSIZE_Msk              (0x3UL << XSPI_CCR_ADSIZE_Pos)                   /*!< 0x00003000 */
18107 #define XSPI_CCR_ADSIZE                  XSPI_CCR_ADSIZE_Msk                              /*!< Address Size */
18108 #define XSPI_CCR_ADSIZE_0                (0x1UL << XSPI_CCR_ADSIZE_Pos)                   /*!< 0x00001000 */
18109 #define XSPI_CCR_ADSIZE_1                (0x2UL << XSPI_CCR_ADSIZE_Pos)                   /*!< 0x00002000 */
18110 #define XSPI_CCR_ABMODE_Pos              (16U)
18111 #define XSPI_CCR_ABMODE_Msk              (0x7UL << XSPI_CCR_ABMODE_Pos)                   /*!< 0x00070000 */
18112 #define XSPI_CCR_ABMODE                  XSPI_CCR_ABMODE_Msk                              /*!< Alternate Bytes Mode */
18113 #define XSPI_CCR_ABMODE_0                (0x1UL << XSPI_CCR_ABMODE_Pos)                   /*!< 0x00010000 */
18114 #define XSPI_CCR_ABMODE_1                (0x2UL << XSPI_CCR_ABMODE_Pos)                   /*!< 0x00020000 */
18115 #define XSPI_CCR_ABMODE_2                (0x4UL << XSPI_CCR_ABMODE_Pos)                   /*!< 0x00040000 */
18116 #define XSPI_CCR_ABDTR_Pos               (19U)
18117 #define XSPI_CCR_ABDTR_Msk               (0x1UL << XSPI_CCR_ABDTR_Pos)                    /*!< 0x00080000 */
18118 #define XSPI_CCR_ABDTR                   XSPI_CCR_ABDTR_Msk                               /*!< Alternate Bytes Double Transfer Rate */
18119 #define XSPI_CCR_ABSIZE_Pos              (20U)
18120 #define XSPI_CCR_ABSIZE_Msk              (0x3UL << XSPI_CCR_ABSIZE_Pos)                   /*!< 0x00300000 */
18121 #define XSPI_CCR_ABSIZE                  XSPI_CCR_ABSIZE_Msk                              /*!< Alternate Bytes Size */
18122 #define XSPI_CCR_ABSIZE_0                (0x1UL << XSPI_CCR_ABSIZE_Pos)                   /*!< 0x00100000 */
18123 #define XSPI_CCR_ABSIZE_1                (0x2UL << XSPI_CCR_ABSIZE_Pos)                   /*!< 0x00200000 */
18124 #define XSPI_CCR_DMODE_Pos               (24U)
18125 #define XSPI_CCR_DMODE_Msk               (0x7UL << XSPI_CCR_DMODE_Pos)                    /*!< 0x07000000 */
18126 #define XSPI_CCR_DMODE                   XSPI_CCR_DMODE_Msk                               /*!< Data Mode */
18127 #define XSPI_CCR_DMODE_0                 (0x1UL << XSPI_CCR_DMODE_Pos)                    /*!< 0x01000000 */
18128 #define XSPI_CCR_DMODE_1                 (0x2UL << XSPI_CCR_DMODE_Pos)                    /*!< 0x02000000 */
18129 #define XSPI_CCR_DMODE_2                 (0x4UL << XSPI_CCR_DMODE_Pos)                    /*!< 0x04000000 */
18130 #define XSPI_CCR_DDTR_Pos                (27U)
18131 #define XSPI_CCR_DDTR_Msk                (0x1UL << XSPI_CCR_DDTR_Pos)                     /*!< 0x08000000 */
18132 #define XSPI_CCR_DDTR                    XSPI_CCR_DDTR_Msk                                /*!< Data Double Transfer Rate */
18133 #define XSPI_CCR_DQSE_Pos                (29U)
18134 #define XSPI_CCR_DQSE_Msk                (0x1UL << XSPI_CCR_DQSE_Pos)                     /*!< 0x20000000 */
18135 #define XSPI_CCR_DQSE                    XSPI_CCR_DQSE_Msk                                /*!< DQS Enable */
18136 #define XSPI_CCR_SIOO_Pos                (31U)
18137 #define XSPI_CCR_SIOO_Msk                (0x1UL << XSPI_CCR_SIOO_Pos)                     /*!< 0x80000000 */
18138 #define XSPI_CCR_SIOO                    XSPI_CCR_SIOO_Msk                                /*!< Send Instruction Only Once Mode */
18139 
18140 /****************  Bit definition for XSPI_TCR register  *********************/
18141 #define XSPI_TCR_DCYC_Pos                (0U)
18142 #define XSPI_TCR_DCYC_Msk                (0x1FUL << XSPI_TCR_DCYC_Pos)                    /*!< 0x0000001F */
18143 #define XSPI_TCR_DCYC                    XSPI_TCR_DCYC_Msk                                /*!< Number of Dummy Cycles */
18144 #define XSPI_TCR_DHQC_Pos                (28U)
18145 #define XSPI_TCR_DHQC_Msk                (0x1UL << XSPI_TCR_DHQC_Pos)                     /*!< 0x10000000 */
18146 #define XSPI_TCR_DHQC                    XSPI_TCR_DHQC_Msk                                /*!< Delay Hold Quarter Cycle */
18147 #define XSPI_TCR_SSHIFT_Pos              (30U)
18148 #define XSPI_TCR_SSHIFT_Msk              (0x1UL << XSPI_TCR_SSHIFT_Pos)                   /*!< 0x40000000 */
18149 #define XSPI_TCR_SSHIFT                  XSPI_TCR_SSHIFT_Msk                              /*!< Sample Shift */
18150 
18151 /*****************  Bit definition for XSPI_IR register  *********************/
18152 #define XSPI_IR_INSTRUCTION_Pos          (0U)
18153 #define XSPI_IR_INSTRUCTION_Msk          (0xFFFFFFFFUL << XSPI_IR_INSTRUCTION_Pos)        /*!< 0xFFFFFFFF */
18154 #define XSPI_IR_INSTRUCTION              XSPI_IR_INSTRUCTION_Msk                          /*!< Instruction */
18155 
18156 /****************  Bit definition for XSPI_ABR register  *********************/
18157 #define XSPI_ABR_ALTERNATE_Pos           (0U)
18158 #define XSPI_ABR_ALTERNATE_Msk           (0xFFFFFFFFUL << XSPI_ABR_ALTERNATE_Pos)         /*!< 0xFFFFFFFF */
18159 #define XSPI_ABR_ALTERNATE               XSPI_ABR_ALTERNATE_Msk                           /*!< Alternate Bytes */
18160 
18161 /****************  Bit definition for XSPI_LPTR register  ********************/
18162 #define XSPI_LPTR_TIMEOUT_Pos            (0U)
18163 #define XSPI_LPTR_TIMEOUT_Msk            (0xFFFFUL << XSPI_LPTR_TIMEOUT_Pos)              /*!< 0x0000FFFF */
18164 #define XSPI_LPTR_TIMEOUT                XSPI_LPTR_TIMEOUT_Msk                            /*!< Timeout period */
18165 
18166 /****************  Bit definition for XSPI_WPCCR register  *******************/
18167 #define XSPI_WPCCR_IMODE_Pos             (0U)
18168 #define XSPI_WPCCR_IMODE_Msk             (0x7UL << XSPI_WPCCR_IMODE_Pos)                  /*!< 0x00000007 */
18169 #define XSPI_WPCCR_IMODE                 XSPI_WPCCR_IMODE_Msk                             /*!< Instruction Mode */
18170 #define XSPI_WPCCR_IMODE_0               (0x1UL << XSPI_WPCCR_IMODE_Pos)                  /*!< 0x00000001 */
18171 #define XSPI_WPCCR_IMODE_1               (0x2UL << XSPI_WPCCR_IMODE_Pos)                  /*!< 0x00000002 */
18172 #define XSPI_WPCCR_IMODE_2               (0x4UL << XSPI_WPCCR_IMODE_Pos)                  /*!< 0x00000004 */
18173 #define XSPI_WPCCR_IDTR_Pos              (3U)
18174 #define XSPI_WPCCR_IDTR_Msk              (0x1UL << XSPI_WPCCR_IDTR_Pos)                   /*!< 0x00000008 */
18175 #define XSPI_WPCCR_IDTR                  XSPI_WPCCR_IDTR_Msk                              /*!< Instruction Double Transfer Rate */
18176 #define XSPI_WPCCR_ISIZE_Pos             (4U)
18177 #define XSPI_WPCCR_ISIZE_Msk             (0x3UL << XSPI_WPCCR_ISIZE_Pos)                  /*!< 0x00000030 */
18178 #define XSPI_WPCCR_ISIZE                 XSPI_WPCCR_ISIZE_Msk                             /*!< Instruction Size */
18179 #define XSPI_WPCCR_ISIZE_0               (0x1UL << XSPI_WPCCR_ISIZE_Pos)                  /*!< 0x00000010 */
18180 #define XSPI_WPCCR_ISIZE_1               (0x2UL << XSPI_WPCCR_ISIZE_Pos)                  /*!< 0x00000020 */
18181 #define XSPI_WPCCR_ADMODE_Pos            (8U)
18182 #define XSPI_WPCCR_ADMODE_Msk            (0x7UL << XSPI_WPCCR_ADMODE_Pos)                 /*!< 0x00000700 */
18183 #define XSPI_WPCCR_ADMODE                XSPI_WPCCR_ADMODE_Msk                            /*!< Address Mode */
18184 #define XSPI_WPCCR_ADMODE_0              (0x1UL << XSPI_WPCCR_ADMODE_Pos)                 /*!< 0x00000100 */
18185 #define XSPI_WPCCR_ADMODE_1              (0x2UL << XSPI_WPCCR_ADMODE_Pos)                 /*!< 0x00000200 */
18186 #define XSPI_WPCCR_ADMODE_2              (0x4UL << XSPI_WPCCR_ADMODE_Pos)                 /*!< 0x00000400 */
18187 #define XSPI_WPCCR_ADDTR_Pos             (11U)
18188 #define XSPI_WPCCR_ADDTR_Msk             (0x1UL << XSPI_WPCCR_ADDTR_Pos)                  /*!< 0x00000800 */
18189 #define XSPI_WPCCR_ADDTR                 XSPI_WPCCR_ADDTR_Msk                             /*!< Address Double Transfer Rate */
18190 #define XSPI_WPCCR_ADSIZE_Pos            (12U)
18191 #define XSPI_WPCCR_ADSIZE_Msk            (0x3UL << XSPI_WPCCR_ADSIZE_Pos)                 /*!< 0x00003000 */
18192 #define XSPI_WPCCR_ADSIZE                XSPI_WPCCR_ADSIZE_Msk                            /*!< Address Size */
18193 #define XSPI_WPCCR_ADSIZE_0              (0x1UL << XSPI_WPCCR_ADSIZE_Pos)                 /*!< 0x00001000 */
18194 #define XSPI_WPCCR_ADSIZE_1              (0x2UL << XSPI_WPCCR_ADSIZE_Pos)                 /*!< 0x00002000 */
18195 #define XSPI_WPCCR_ABMODE_Pos            (16U)
18196 #define XSPI_WPCCR_ABMODE_Msk            (0x7UL << XSPI_WPCCR_ABMODE_Pos)                 /*!< 0x00070000 */
18197 #define XSPI_WPCCR_ABMODE                XSPI_WPCCR_ABMODE_Msk                            /*!< Alternate Bytes Mode */
18198 #define XSPI_WPCCR_ABMODE_0              (0x1UL << XSPI_WPCCR_ABMODE_Pos)                 /*!< 0x00010000 */
18199 #define XSPI_WPCCR_ABMODE_1              (0x2UL << XSPI_WPCCR_ABMODE_Pos)                 /*!< 0x00020000 */
18200 #define XSPI_WPCCR_ABMODE_2              (0x4UL << XSPI_WPCCR_ABMODE_Pos)                 /*!< 0x00040000 */
18201 #define XSPI_WPCCR_ABDTR_Pos             (19U)
18202 #define XSPI_WPCCR_ABDTR_Msk             (0x1UL << XSPI_WPCCR_ABDTR_Pos)                  /*!< 0x00080000 */
18203 #define XSPI_WPCCR_ABDTR                 XSPI_WPCCR_ABDTR_Msk                             /*!< Alternate Bytes Double Transfer Rate */
18204 #define XSPI_WPCCR_ABSIZE_Pos            (20U)
18205 #define XSPI_WPCCR_ABSIZE_Msk            (0x3UL << XSPI_WPCCR_ABSIZE_Pos)                 /*!< 0x00300000 */
18206 #define XSPI_WPCCR_ABSIZE                XSPI_WPCCR_ABSIZE_Msk                            /*!< Alternate Bytes Size */
18207 #define XSPI_WPCCR_ABSIZE_0              (0x1UL << XSPI_WPCCR_ABSIZE_Pos)                 /*!< 0x00100000 */
18208 #define XSPI_WPCCR_ABSIZE_1              (0x2UL << XSPI_WPCCR_ABSIZE_Pos)                 /*!< 0x00200000 */
18209 #define XSPI_WPCCR_DMODE_Pos             (24U)
18210 #define XSPI_WPCCR_DMODE_Msk             (0x7UL << XSPI_WPCCR_DMODE_Pos)                  /*!< 0x07000000 */
18211 #define XSPI_WPCCR_DMODE                 XSPI_WPCCR_DMODE_Msk                             /*!< Data Mode */
18212 #define XSPI_WPCCR_DMODE_0               (0x1UL << XSPI_WPCCR_DMODE_Pos)                  /*!< 0x01000000 */
18213 #define XSPI_WPCCR_DMODE_1               (0x2UL << XSPI_WPCCR_DMODE_Pos)                  /*!< 0x02000000 */
18214 #define XSPI_WPCCR_DMODE_2               (0x4UL << XSPI_WPCCR_DMODE_Pos)                  /*!< 0x04000000 */
18215 #define XSPI_WPCCR_DDTR_Pos              (27U)
18216 #define XSPI_WPCCR_DDTR_Msk              (0x1UL << XSPI_WPCCR_DDTR_Pos)                   /*!< 0x08000000 */
18217 #define XSPI_WPCCR_DDTR                  XSPI_WPCCR_DDTR_Msk                              /*!< Data Double Transfer Rate */
18218 #define XSPI_WPCCR_DQSE_Pos              (29U)
18219 #define XSPI_WPCCR_DQSE_Msk              (0x1UL << XSPI_WPCCR_DQSE_Pos)                   /*!< 0x20000000 */
18220 #define XSPI_WPCCR_DQSE                  XSPI_WPCCR_DQSE_Msk                              /*!< DQS Enable */
18221 
18222 /****************  Bit definition for XSPI_WPTCR register  *******************/
18223 #define XSPI_WPTCR_DCYC_Pos              (0U)
18224 #define XSPI_WPTCR_DCYC_Msk              (0x1FUL << XSPI_WPTCR_DCYC_Pos)                  /*!< 0x0000001F */
18225 #define XSPI_WPTCR_DCYC                  XSPI_WPTCR_DCYC_Msk                              /*!< Number of Dummy Cycles */
18226 #define XSPI_WPTCR_DHQC_Pos              (28U)
18227 #define XSPI_WPTCR_DHQC_Msk              (0x1UL << XSPI_WPTCR_DHQC_Pos)                   /*!< 0x10000000 */
18228 #define XSPI_WPTCR_DHQC                  XSPI_WPTCR_DHQC_Msk                              /*!< Delay Hold Quarter Cycle */
18229 #define XSPI_WPTCR_SSHIFT_Pos            (30U)
18230 #define XSPI_WPTCR_SSHIFT_Msk            (0x1UL << XSPI_WPTCR_SSHIFT_Pos)                 /*!< 0x40000000 */
18231 #define XSPI_WPTCR_SSHIFT                XSPI_WPTCR_SSHIFT_Msk                            /*!< Sample Shift */
18232 
18233 /*****************  Bit definition for XSPI_WPIR register  *******************/
18234 #define XSPI_WPIR_INSTRUCTION_Pos        (0U)
18235 #define XSPI_WPIR_INSTRUCTION_Msk        (0xFFFFFFFFUL << XSPI_WPIR_INSTRUCTION_Pos)      /*!< 0xFFFFFFFF */
18236 #define XSPI_WPIR_INSTRUCTION            XSPI_WPIR_INSTRUCTION_Msk                        /*!< Instruction */
18237 
18238 /****************  Bit definition for XSPI_WPABR register  *******************/
18239 #define XSPI_WPABR_ALTERNATE_Pos         (0U)
18240 #define XSPI_WPABR_ALTERNATE_Msk         (0xFFFFFFFFUL << XSPI_WPABR_ALTERNATE_Pos)       /*!< 0xFFFFFFFF */
18241 #define XSPI_WPABR_ALTERNATE             XSPI_WPABR_ALTERNATE_Msk                         /*!< Alternate Bytes */
18242 
18243 /****************  Bit definition for XSPI_WCCRregister  *********************/
18244 #define XSPI_WCCR_IMODE_Pos              (0U)
18245 #define XSPI_WCCR_IMODE_Msk              (0x7UL << XSPI_WCCR_IMODE_Pos)                   /*!< 0x00000007 */
18246 #define XSPI_WCCR_IMODE                  XSPI_WCCR_IMODE_Msk                              /*!< Instruction Mode */
18247 #define XSPI_WCCR_IMODE_0                (0x1UL << XSPI_WCCR_IMODE_Pos)                   /*!< 0x00000001 */
18248 #define XSPI_WCCR_IMODE_1                (0x2UL << XSPI_WCCR_IMODE_Pos)                   /*!< 0x00000002 */
18249 #define XSPI_WCCR_IMODE_2                (0x4UL << XSPI_WCCR_IMODE_Pos)                   /*!< 0x00000004 */
18250 #define XSPI_WCCR_IDTR_Pos               (3U)
18251 #define XSPI_WCCR_IDTR_Msk               (0x1UL << XSPI_WCCR_IDTR_Pos)                    /*!< 0x00000008 */
18252 #define XSPI_WCCR_IDTR                   XSPI_WCCR_IDTR_Msk                               /*!< Instruction Double Transfer Rate */
18253 #define XSPI_WCCR_ISIZE_Pos              (4U)
18254 #define XSPI_WCCR_ISIZE_Msk              (0x3UL << XSPI_WCCR_ISIZE_Pos)                   /*!< 0x00000030 */
18255 #define XSPI_WCCR_ISIZE                  XSPI_WCCR_ISIZE_Msk                              /*!< Instruction Size */
18256 #define XSPI_WCCR_ISIZE_0                (0x1UL << XSPI_WCCR_ISIZE_Pos)                   /*!< 0x00000010 */
18257 #define XSPI_WCCR_ISIZE_1                (0x2UL << XSPI_WCCR_ISIZE_Pos)                   /*!< 0x00000020 */
18258 #define XSPI_WCCR_ADMODE_Pos             (8U)
18259 #define XSPI_WCCR_ADMODE_Msk             (0x7UL << XSPI_WCCR_ADMODE_Pos)                  /*!< 0x00000700 */
18260 #define XSPI_WCCR_ADMODE                 XSPI_WCCR_ADMODE_Msk                             /*!< Address Mode */
18261 #define XSPI_WCCR_ADMODE_0               (0x1UL << XSPI_WCCR_ADMODE_Pos)                  /*!< 0x00000100 */
18262 #define XSPI_WCCR_ADMODE_1               (0x2UL << XSPI_WCCR_ADMODE_Pos)                  /*!< 0x00000200 */
18263 #define XSPI_WCCR_ADMODE_2               (0x4UL << XSPI_WCCR_ADMODE_Pos)                  /*!< 0x00000400 */
18264 #define XSPI_WCCR_ADDTR_Pos              (11U)
18265 #define XSPI_WCCR_ADDTR_Msk              (0x1UL << XSPI_WCCR_ADDTR_Pos)                   /*!< 0x00000800 */
18266 #define XSPI_WCCR_ADDTR                  XSPI_WCCR_ADDTR_Msk                              /*!< Address Double Transfer Rate */
18267 #define XSPI_WCCR_ADSIZE_Pos             (12U)
18268 #define XSPI_WCCR_ADSIZE_Msk             (0x3UL << XSPI_WCCR_ADSIZE_Pos)                  /*!< 0x00003000 */
18269 #define XSPI_WCCR_ADSIZE                 XSPI_WCCR_ADSIZE_Msk                             /*!< Address Size */
18270 #define XSPI_WCCR_ADSIZE_0               (0x1UL << XSPI_WCCR_ADSIZE_Pos)                  /*!< 0x00001000 */
18271 #define XSPI_WCCR_ADSIZE_1               (0x2UL << XSPI_WCCR_ADSIZE_Pos)                  /*!< 0x00002000 */
18272 #define XSPI_WCCR_ABMODE_Pos             (16U)
18273 #define XSPI_WCCR_ABMODE_Msk             (0x7UL << XSPI_WCCR_ABMODE_Pos)                  /*!< 0x00070000 */
18274 #define XSPI_WCCR_ABMODE                 XSPI_WCCR_ABMODE_Msk                             /*!< Alternate Bytes Mode */
18275 #define XSPI_WCCR_ABMODE_0               (0x1UL << XSPI_WCCR_ABMODE_Pos)                  /*!< 0x00010000 */
18276 #define XSPI_WCCR_ABMODE_1               (0x2UL << XSPI_WCCR_ABMODE_Pos)                  /*!< 0x00020000 */
18277 #define XSPI_WCCR_ABMODE_2               (0x4UL << XSPI_WCCR_ABMODE_Pos)                  /*!< 0x00040000 */
18278 #define XSPI_WCCR_ABDTR_Pos              (19U)
18279 #define XSPI_WCCR_ABDTR_Msk              (0x1UL << XSPI_WCCR_ABDTR_Pos)                   /*!< 0x00080000 */
18280 #define XSPI_WCCR_ABDTR                  XSPI_WCCR_ABDTR_Msk                              /*!< Alternate Bytes Double Transfer Rate */
18281 #define XSPI_WCCR_ABSIZE_Pos             (20U)
18282 #define XSPI_WCCR_ABSIZE_Msk             (0x3UL << XSPI_WCCR_ABSIZE_Pos)                  /*!< 0x00300000 */
18283 #define XSPI_WCCR_ABSIZE                 XSPI_WCCR_ABSIZE_Msk                             /*!< Alternate Bytes Size */
18284 #define XSPI_WCCR_ABSIZE_0               (0x1UL << XSPI_WCCR_ABSIZE_Pos)                  /*!< 0x00100000 */
18285 #define XSPI_WCCR_ABSIZE_1               (0x2UL << XSPI_WCCR_ABSIZE_Pos)                  /*!< 0x00200000 */
18286 #define XSPI_WCCR_DMODE_Pos              (24U)
18287 #define XSPI_WCCR_DMODE_Msk              (0x7UL << XSPI_WCCR_DMODE_Pos)                   /*!< 0x07000000 */
18288 #define XSPI_WCCR_DMODE                  XSPI_WCCR_DMODE_Msk                              /*!< Data Mode */
18289 #define XSPI_WCCR_DMODE_0                (0x1UL << XSPI_WCCR_DMODE_Pos)                   /*!< 0x01000000 */
18290 #define XSPI_WCCR_DMODE_1                (0x2UL << XSPI_WCCR_DMODE_Pos)                   /*!< 0x02000000 */
18291 #define XSPI_WCCR_DMODE_2                (0x4UL << XSPI_WCCR_DMODE_Pos)                   /*!< 0x04000000 */
18292 #define XSPI_WCCR_DDTR_Pos               (27U)
18293 #define XSPI_WCCR_DDTR_Msk               (0x1UL << XSPI_WCCR_DDTR_Pos)                    /*!< 0x08000000 */
18294 #define XSPI_WCCR_DDTR                   XSPI_WCCR_DDTR_Msk                               /*!< Data Double Transfer Rate */
18295 #define XSPI_WCCR_DQSE_Pos               (29U)
18296 #define XSPI_WCCR_DQSE_Msk               (0x1UL << XSPI_WCCR_DQSE_Pos)                    /*!< 0x20000000 */
18297 #define XSPI_WCCR_DQSE                   XSPI_WCCR_DQSE_Msk                               /*!< DQS Enable */
18298 
18299 /****************  Bit definition for XSPI_WTCR register  ********************/
18300 #define XSPI_WTCR_DCYC_Pos               (0U)
18301 #define XSPI_WTCR_DCYC_Msk               (0x1FUL << XSPI_WTCR_DCYC_Pos)                   /*!< 0x0000001F */
18302 #define XSPI_WTCR_DCYC                   XSPI_WTCR_DCYC_Msk                               /*!< Number of Dummy Cycles */
18303 
18304 /****************  Bit definition for XSPI_WIR register  *********************/
18305 #define XSPI_WIR_INSTRUCTION_Pos         (0U)
18306 #define XSPI_WIR_INSTRUCTION_Msk         (0xFFFFFFFFUL << XSPI_WIR_INSTRUCTION_Pos)       /*!< 0xFFFFFFFF */
18307 #define XSPI_WIR_INSTRUCTION             XSPI_WIR_INSTRUCTION_Msk                         /*!< Instruction */
18308 
18309 /****************  Bit definition for XSPI_WABR register  ********************/
18310 #define XSPI_WABR_ALTERNATE_Pos          (0U)
18311 #define XSPI_WABR_ALTERNATE_Msk          (0xFFFFFFFFUL << XSPI_WABR_ALTERNATE_Pos)        /*!< 0xFFFFFFFF */
18312 #define XSPI_WABR_ALTERNATE              XSPI_WABR_ALTERNATE_Msk                          /*!< Alternate Bytes */
18313 
18314 /****************  Bit definition for XSPI_HLCR register  ********************/
18315 #define XSPI_HLCR_LM_Pos                 (0U)
18316 #define XSPI_HLCR_LM_Msk                 (0x1UL << XSPI_HLCR_LM_Pos)                      /*!< 0x00000001 */
18317 #define XSPI_HLCR_LM                     XSPI_HLCR_LM_Msk                                 /*!< Latency Mode */
18318 #define XSPI_HLCR_WZL_Pos                (1U)
18319 #define XSPI_HLCR_WZL_Msk                (0x1UL << XSPI_HLCR_WZL_Pos)                     /*!< 0x00000002 */
18320 #define XSPI_HLCR_WZL                    XSPI_HLCR_WZL_Msk                                /*!< Write Zero Latency */
18321 #define XSPI_HLCR_TACC_Pos               (8U)
18322 #define XSPI_HLCR_TACC_Msk               (0xFFUL << XSPI_HLCR_TACC_Pos)                   /*!< 0x0000FF00 */
18323 #define XSPI_HLCR_TACC                   XSPI_HLCR_TACC_Msk                               /*!< Access Time */
18324 #define XSPI_HLCR_TRWR_Pos               (16U)
18325 #define XSPI_HLCR_TRWR_Msk               (0xFFUL << XSPI_HLCR_TRWR_Pos)                   /*!< 0x00FF0000 */
18326 #define XSPI_HLCR_TRWR                   XSPI_HLCR_TRWR_Msk                               /*!< Read Write Recovery Time */
18327 /****************  Bit definition for XSPI_CALFCR register  ******************/
18328 #define XSPI_HSPI_CALFCR_FINE_Pos         (0U)
18329 #define XSPI_HSPI_CALFCR_FINE_Msk         (0x7FUL << XSPI_HSPI_CALFCR_FINE_Pos)           /*!< 0x0000007F */
18330 #define XSPI_HSPI_CALFCR_FINE             XSPI_HSPI_CALFCR_FINE_Msk                       /*!< Fine Calibration only for HSPI, Invalid for OCTOSPI */
18331 #define XSPI_HSPI_CALFCR_COARSE_Pos       (16U)
18332 #define XSPI_HSPI_CALFCR_COARSE_Msk       (0x1FUL << XSPI_HSPI_CALFCR_COARSE_Pos)         /*!< 0x001F0000 */
18333 #define XSPI_HSPI_CALFCR_COARSE           XSPI_HSPI_CALFCR_COARSE_Msk                     /*!< Coarse Calibration only for HSPI, Invalid for OCTOSPI */
18334 #define XSPI_HSPI_CALFCR_CALMAX_Pos       (31U)
18335 #define XSPI_HSPI_CALFCR_CALMAX_Msk       (0x1UL << XSPI_HSPI_CALFCR_CALMAX_Pos)          /*!< 0x80000000 */
18336 #define XSPI_HSPI_CALFCR_CALMAX           XSPI_HSPI_CALFCR_CALMAX_Msk                     /*!< Max Value only for HSPI, Invalid for OCTOSPI */
18337 
18338 /****************  Bit definition for XSPI_CALMR register  *******************/
18339 #define XSPI_HSPI_CALMR_FINE_Pos          (0U)
18340 #define XSPI_HSPI_CALMR_FINE_Msk          (0x7FUL << XSPI_HSPI_CALMR_FINE_Pos)            /*!< 0x0000007F */
18341 #define XSPI_HSPI_CALMR_FINE              XSPI_HSPI_CALMR_FINE_Msk                        /*!< Fine Calibration only for HSPI, Invalid for OCTOSPI */
18342 #define XSPI_HSPI_CALMR_COARSE_Pos        (16U)
18343 #define XSPI_HSPI_CALMR_COARSE_Msk        (0x1FUL << XSPI_HSPI_CALMR_COARSE_Pos)          /*!< 0x001F0000 */
18344 #define XSPI_HSPI_CALMR_COARSE            XSPI_HSPI_CALMR_COARSE_Msk                      /*!< Coarse Calibration only for HSPI, Invalid for OCTOSPI */
18345 
18346 /****************  Bit definition for XSPI_CALSOR register  ******************/
18347 #define XSPI_HSPI_CALSOR_FINE_Pos         (0U)
18348 #define XSPI_HSPI_CALSOR_FINE_Msk         (0x7FUL << XSPI_HSPI_CALSOR_FINE_Pos)           /*!< 0x0000007F */
18349 #define XSPI_HSPI_CALSOR_FINE             XSPI_HSPI_CALSOR_FINE_Msk                       /*!< Fine Calibration only for HSPI, Invalid for OCTOSPI */
18350 #define XSPI_HSPI_CALSOR_COARSE_Pos       (16U)
18351 #define XSPI_HSPI_CALSOR_COARSE_Msk       (0x1FUL << XSPI_HSPI_CALSOR_COARSE_Pos)         /*!< 0x001F0000 */
18352 #define XSPI_HSPI_CALSOR_COARSE           XSPI_HSPI_CALSOR_COARSE_Msk                     /*!< Coarse Calibration only for HSPI, Invalid for OCTOSPI */
18353 
18354 /****************  Bit definition for XSPI_CALSIR register  ******************/
18355 #define XSPI_HSPI_CALSIR_FINE_Pos        (0U)
18356 #define XSPI_HSPI_CALSIR_FINE_Msk        (0x7FUL << XSPI_HSPI_CALSIR_FINE_Pos)            /*!< 0x0000007F */
18357 #define XSPI_HSPI_CALSIR_FINE            XSPI_HSPI_CALSIR_FINE_Msk                        /*!< Fine Calibration only for HSPI, Invalid for OCTOSPI */
18358 #define XSPI_HSPI_CALSIR_COARSE_Pos      (16U)
18359 #define XSPI_HSPI_CALSIR_COARSE_Msk      (0x1FUL << XSPI_HSPI_CALSIR_COARSE_Pos)          /*!< 0x001F0000 */
18360 #define XSPI_HSPI_CALSIR_COARSE          XSPI_HSPI_CALSIR_COARSE_Msk                      /*!< Coarse Calibration only for HSPI, Invalid for OCTOSPI */
18361 
18362 /******************************************************************************/
18363 /*                                                                            */
18364 /*                                    OCTOSPI                                 */
18365 /*                                                                            */
18366 /******************************************************************************/
18367 /*****************  Bit definition for OCTOSPI_CR register  *******************/
18368 #define OCTOSPI_CR_EN_Pos                   XSPI_CR_EN_Pos
18369 #define OCTOSPI_CR_EN_Msk                   XSPI_CR_EN_Msk                                /*!< 0x00000001 */
18370 #define OCTOSPI_CR_EN                       XSPI_CR_EN                                    /*!< Enable */
18371 #define OCTOSPI_CR_ABORT_Pos                XSPI_CR_ABORT_Pos
18372 #define OCTOSPI_CR_ABORT_Msk                XSPI_CR_ABORT_Msk                             /*!< 0x00000002 */
18373 #define OCTOSPI_CR_ABORT                    XSPI_CR_ABORT                                 /*!< Abort request */
18374 #define OCTOSPI_CR_DMAEN_Pos                XSPI_CR_DMAEN_Pos
18375 #define OCTOSPI_CR_DMAEN_Msk                XSPI_CR_DMAEN_Msk                             /*!< 0x00000004 */
18376 #define OCTOSPI_CR_DMAEN                    XSPI_CR_DMAEN                                 /*!< DMA Enable */
18377 #define OCTOSPI_CR_TCEN_Pos                 XSPI_CR_TCEN_Pos
18378 #define OCTOSPI_CR_TCEN_Msk                 XSPI_CR_TCEN_Msk                              /*!< 0x00000008 */
18379 #define OCTOSPI_CR_TCEN                     XSPI_CR_TCEN                                  /*!< Timeout Counter Enable */
18380 #define OCTOSPI_CR_DMM_Pos                  XSPI_CR_DMM_Pos
18381 #define OCTOSPI_CR_DMM_Msk                  XSPI_CR_DMM_Msk                               /*!< 0x00000040 */
18382 #define OCTOSPI_CR_DMM                      XSPI_CR_DMM                                   /*!< Dual Memory Mode */
18383 #define OCTOSPI_CR_MSEL_Pos                 XSPI_OCTOSPI_CR_MSEL_Pos
18384 #define OCTOSPI_CR_MSEL_Msk                 XSPI_OCTOSPI_CR_MSEL_Msk                      /*!< 0x00000080 */
18385 #define OCTOSPI_CR_MSEL                     XSPI_OCTOSPI_CR_MSEL                          /*!< Memory Select */
18386 #define OCTOSPI_CR_FTHRES_Pos               XSPI_CR_FTHRES_Pos
18387 #define OCTOSPI_CR_FTHRES_Msk               (0x1FUL << OCTOSPI_CR_FTHRES_Pos)             /*!< 0x00001F00 */
18388 #define OCTOSPI_CR_FTHRES                   XSPI_CR_FTHRES                                /*!< FIFO Threshold Level */
18389 #define OCTOSPI_CR_TEIE_Pos                 XSPI_CR_TEIE_Pos
18390 #define OCTOSPI_CR_TEIE_Msk                 XSPI_CR_TEIE_Msk                              /*!< 0x00010000 */
18391 #define OCTOSPI_CR_TEIE                     XSPI_CR_TEIE                                  /*!< Transfer Error Interrupt Enable */
18392 #define OCTOSPI_CR_TCIE_Pos                 XSPI_CR_TCIE_Pos
18393 #define OCTOSPI_CR_TCIE_Msk                 XSPI_CR_TCIE_Msk                              /*!< 0x00020000 */
18394 #define OCTOSPI_CR_TCIE                     XSPI_CR_TCIE                                  /*!< Transfer Complete Interrupt Enable */
18395 #define OCTOSPI_CR_FTIE_Pos                 XSPI_CR_FTIE_Pos
18396 #define OCTOSPI_CR_FTIE_Msk                 XSPI_CR_FTIE_Msk)                             /*!< 0x00040000 */
18397 #define OCTOSPI_CR_FTIE                     XSPI_CR_FTIE                                  /*!< FIFO Threshold Interrupt Enable */
18398 #define OCTOSPI_CR_SMIE_Pos                 XSPI_CR_SMIE_Pos
18399 #define OCTOSPI_CR_SMIE_Msk                 XSPI_CR_SMIE_Msk                              /*!< 0x00080000 */
18400 #define OCTOSPI_CR_SMIE                     XSPI_CR_SMIE                                  /*!< Status Match Interrupt Enable */
18401 #define OCTOSPI_CR_TOIE_Pos                 XSPI_CR_TOIE_Pos
18402 #define OCTOSPI_CR_TOIE_Msk                 XSPI_CR_TOIE_Msk                              /*!< 0x00100000 */
18403 #define OCTOSPI_CR_TOIE                     XSPI_CR_TOIE                                  /*!< TimeOut Interrupt Enable */
18404 #define OCTOSPI_CR_APMS_Pos                 XSPI_CR_APMS_Pos
18405 #define OCTOSPI_CR_APMS_Msk                 XSPI_CR_APMS_Msk                              /*!< 0x00400000 */
18406 #define OCTOSPI_CR_APMS                     XSPI_CR_APMS                                  /*!< Automatic Poll Mode Stop */
18407 #define OCTOSPI_CR_PMM_Pos                  XSPI_CR_PMM_Pos
18408 #define OCTOSPI_CR_PMM_Msk                  XSPI_CR_PMM_Msk                               /*!< 0x00800000 */
18409 #define OCTOSPI_CR_PMM                      XSPI_CR_PMM                                   /*!< Polling Match Mode */
18410 #define OCTOSPI_CR_FMODE_Pos                XSPI_CR_FMODE_Pos
18411 #define OCTOSPI_CR_FMODE_Msk                XSPI_CR_FMODE_Msk                             /*!< 0x30000000 */
18412 #define OCTOSPI_CR_FMODE                    XSPI_CR_FMODE                                 /*!< Functional Mode */
18413 #define OCTOSPI_CR_FMODE_0                  XSPI_CR_FMODE_0                               /*!< 0x10000000 */
18414 #define OCTOSPI_CR_FMODE_1                  XSPI_CR_FMODE_1                               /*!< 0x20000000 */
18415 
18416 /* Legacy Bit definition for OCTOSPI_CR register */
18417 #define OCTOSPI_CR_DQM                      XSPI_CR_DMM                                   /*!< Legacy Dual Memory Mode */
18418 #define OCTOSPI_CR_FSEL                     XSPI_OCTOSPI_CR_MSEL                          /*!< Legacy Memory Select */
18419 
18420 /****************  Bit definition for OCTOSPI_DCR1 register  ******************/
18421 #define OCTOSPI_DCR1_CKMODE_Pos             XSPI_DCR1_CKMODE_Pos
18422 #define OCTOSPI_DCR1_CKMODE_Msk             XSPI_DCR1_CKMODE_Msk                          /*!< 0x00000001 */
18423 #define OCTOSPI_DCR1_CKMODE                 XSPI_DCR1_CKMODE                              /*!< Mode 0 / Mode 3 */
18424 #define OCTOSPI_DCR1_FRCK_Pos               XSPI_DCR1_FRCK_Pos
18425 #define OCTOSPI_DCR1_FRCK_Msk               XSPI_DCR1_FRCK_Msk                            /*!< 0x00000002 */
18426 #define OCTOSPI_DCR1_FRCK                   XSPI_DCR1_FRCK                                /*!< Free Running Clock */
18427 #define OCTOSPI_DCR1_DLYBYP_Pos             XSPI_OCTOSPI_DCR1_DLYBYP_Pos
18428 #define OCTOSPI_DCR1_DLYBYP_Msk             XSPI_OCTOSPI_DCR1_DLYBYP_Msk                  /*!< 0x00000008 */
18429 #define OCTOSPI_DCR1_DLYBYP                 XSPI_OCTOSPI_DCR1_DLYBYP                      /*!< Delay Block Bypass */
18430 #define OCTOSPI_DCR1_CSHT_Pos               XSPI_DCR1_CSHT_Pos
18431 #define OCTOSPI_DCR1_CSHT_Msk               XSPI_DCR1_CSHT_Msk                            /*!< 0x00003F00 */
18432 #define OCTOSPI_DCR1_CSHT                   XSPI_DCR1_CSHT                                /*!< Chip Select High Time */
18433 #define OCTOSPI_DCR1_DEVSIZE_Pos            XSPI_DCR1_DEVSIZE_Pos
18434 #define OCTOSPI_DCR1_DEVSIZE_Msk            XSPI_DCR1_DEVSIZE_Msk                         /*!< 0x001F0000 */
18435 #define OCTOSPI_DCR1_DEVSIZE                XSPI_DCR1_DEVSIZE                             /*!< Device Size */
18436 #define OCTOSPI_DCR1_MTYP_Pos               XSPI_DCR1_MTYP_Pos
18437 #define OCTOSPI_DCR1_MTYP_Msk               XSPI_DCR1_MTYP_Msk                            /*!< 0x07000000 */
18438 #define OCTOSPI_DCR1_MTYP                   XSPI_DCR1_MTYP                                /*!< Memory Type */
18439 #define OCTOSPI_DCR1_MTYP_0                 XSPI_DCR1_MTYP_0                              /*!< 0x01000000 */
18440 #define OCTOSPI_DCR1_MTYP_1                 XSPI_DCR1_MTYP_1                              /*!< 0x02000000 */
18441 #define OCTOSPI_DCR1_MTYP_2                 XSPI_DCR1_MTYP_2                              /*!< 0x04000000 */
18442 
18443 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
18444 #define OCTOSPI_DCR2_PRESCALER_Pos          XSPI_DCR2_PRESCALER_Pos
18445 #define OCTOSPI_DCR2_PRESCALER_Msk          XSPI_DCR2_PRESCALER_Msk                       /*!< 0x000000FF */
18446 #define OCTOSPI_DCR2_PRESCALER              XSPI_DCR2_PRESCALER                           /*!< Clock prescaler */
18447 #define OCTOSPI_DCR2_WRAPSIZE_Pos           XSPI_DCR2_WRAPSIZE_Pos
18448 #define OCTOSPI_DCR2_WRAPSIZE_Msk           XSPI_DCR2_WRAPSIZE_Msk                        /*!< 0x00070000 */
18449 #define OCTOSPI_DCR2_WRAPSIZE               XSPI_DCR2_WRAPSIZE                            /*!< Wrap Size */
18450 #define OCTOSPI_DCR2_WRAPSIZE_0             XSPI_DCR2_WRAPSIZE_0                          /*!< 0x00010000 */
18451 #define OCTOSPI_DCR2_WRAPSIZE_1             XSPI_DCR2_WRAPSIZE_1                          /*!< 0x00020000 */
18452 #define OCTOSPI_DCR2_WRAPSIZE_2             XSPI_DCR2_WRAPSIZE_2                          /*!< 0x00040000 */
18453 
18454 /****************  Bit definition for OCTOSPI_DCR3 register  ******************/
18455 #define OCTOSPI_DCR3_MAXTRAN_Pos            XSPI_OCTOSPI_DCR3_MAXTRAN_Pos
18456 #define OCTOSPI_DCR3_MAXTRAN_Msk            XSPI_OCTOSPI_DCR3_MAXTRAN_Msk                 /*!< 0x000000FF */
18457 #define OCTOSPI_DCR3_MAXTRAN                XSPI_OCTOSPI_DCR3_MAXTRAN                     /*!< Maximum transfer */
18458 #define OCTOSPI_DCR3_CSBOUND_Pos            XSPI_DCR3_CSBOUND_Pos
18459 #define OCTOSPI_DCR3_CSBOUND_Msk            XSPI_DCR3_CSBOUND_Msk                         /*!< 0x001F0000 */
18460 #define OCTOSPI_DCR3_CSBOUND                XSPI_DCR3_CSBOUND                             /*!< Maximum transfer */
18461 
18462 /****************  Bit definition for OCTOSPI_DCR4 register  ******************/
18463 #define OCTOSPI_DCR4_REFRESH_Pos            XSPI_DCR4_REFRESH_Pos
18464 #define OCTOSPI_DCR4_REFRESH_Msk            XSPI_DCR4_REFRESH_Msk                         /*!< 0xFFFFFFFF */
18465 #define OCTOSPI_DCR4_REFRESH                XSPI_DCR4_REFRESH                             /*!< Refresh rate */
18466 
18467 /*****************  Bit definition for OCTOSPI_SR register  *******************/
18468 #define OCTOSPI_SR_TEF_Pos                  XSPI_SR_TEF_Pos
18469 #define OCTOSPI_SR_TEF_Msk                  XSPI_SR_TEF_Msk                               /*!< 0x00000001 */
18470 #define OCTOSPI_SR_TEF                      XSPI_SR_TEF                                   /*!< Transfer Error Flag */
18471 #define OCTOSPI_SR_TCF_Pos                  XSPI_SR_TCF_Pos
18472 #define OCTOSPI_SR_TCF_Msk                  XSPI_SR_TCF_Msk                               /*!< 0x00000002 */
18473 #define OCTOSPI_SR_TCF                      XSPI_SR_TCF                                   /*!< Transfer Complete Flag */
18474 #define OCTOSPI_SR_FTF_Pos                  XSPI_SR_FTF_Pos
18475 #define OCTOSPI_SR_FTF_Msk                  XSPI_SR_FTF_Msk                               /*!< 0x00000004 */
18476 #define OCTOSPI_SR_FTF                      XSPI_SR_FTF                                   /*!< FIFO Threshold Flag */
18477 #define OCTOSPI_SR_SMF_Pos                  XSPI_SR_SMF_Pos
18478 #define OCTOSPI_SR_SMF_Msk                  XSPI_SR_SMF_Msk                               /*!< 0x00000008 */
18479 #define OCTOSPI_SR_SMF                      XSPI_SR_SMF                                   /*!< Status Match Flag */
18480 #define OCTOSPI_SR_TOF_Pos                  XSPI_SR_TOF_Pos
18481 #define OCTOSPI_SR_TOF_Msk                  XSPI_SR_TOF_Msk                               /*!< 0x00000010 */
18482 #define OCTOSPI_SR_TOF                      XSPI_SR_TOF                                   /*!< Timeout Flag */
18483 #define OCTOSPI_SR_BUSY_Pos                 XSPI_SR_BUSY_Pos
18484 #define OCTOSPI_SR_BUSY_Msk                 XSPI_SR_BUSY_Msk                              /*!< 0x00000020 */
18485 #define OCTOSPI_SR_BUSY                     XSPI_SR_BUSY                                  /*!< Busy */
18486 #define OCTOSPI_SR_FLEVEL_Pos               XSPI_SR_FLEVEL_Pos
18487 #define OCTOSPI_SR_FLEVEL_Msk               (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)             /*!< 0x00003F00 */
18488 #define OCTOSPI_SR_FLEVEL                   XSPI_SR_FLEVEL                                /*!< FIFO Level */
18489 
18490 /****************  Bit definition for OCTOSPI_FCR register  *******************/
18491 #define OCTOSPI_FCR_CTEF_Pos                XSPI_FCR_CTEF_Pos
18492 #define OCTOSPI_FCR_CTEF_Msk                XSPI_FCR_CTEF_Msk                             /*!< 0x00000001 */
18493 #define OCTOSPI_FCR_CTEF                    XSPI_FCR_CTEF                                 /*!< Clear Transfer Error Flag */
18494 #define OCTOSPI_FCR_CTCF_Pos                XSPI_FCR_CTCF_Pos
18495 #define OCTOSPI_FCR_CTCF_Msk                XSPI_FCR_CTCF_Msk                             /*!< 0x00000002 */
18496 #define OCTOSPI_FCR_CTCF                    XSPI_FCR_CTCF                                 /*!< Clear Transfer Complete Flag */
18497 #define OCTOSPI_FCR_CSMF_Pos                XSPI_FCR_CSMF_Pos
18498 #define OCTOSPI_FCR_CSMF_Msk                XSPI_FCR_CSMF_Msk                             /*!< 0x00000008 */
18499 #define OCTOSPI_FCR_CSMF                    XSPI_FCR_CSMF                                 /*!< Clear Status Match Flag */
18500 #define OCTOSPI_FCR_CTOF_Pos                XSPI_FCR_CTOF_Pos
18501 #define OCTOSPI_FCR_CTOF_Msk                XSPI_FCR_CTOF_Msk                             /*!< 0x00000010 */
18502 #define OCTOSPI_FCR_CTOF                    XSPI_FCR_CTOF                                 /*!< Clear Timeout Flag */
18503 
18504 /****************  Bit definition for OCTOSPI_DLR register  *******************/
18505 #define OCTOSPI_DLR_DL_Pos                  XSPI_DLR_DL_Pos
18506 #define OCTOSPI_DLR_DL_Msk                  XSPI_DLR_DL_Msk                               /*!< 0xFFFFFFFF */
18507 #define OCTOSPI_DLR_DL                      XSPI_DLR_DL                                   /*!< Data Length */
18508 
18509 /*****************  Bit definition for OCTOSPI_AR register  *******************/
18510 #define OCTOSPI_AR_ADDRESS_Pos              XSPI_AR_ADDRESS_Pos
18511 #define OCTOSPI_AR_ADDRESS_Msk              XSPI_AR_ADDRESS_Msk                           /*!< 0xFFFFFFFF */
18512 #define OCTOSPI_AR_ADDRESS                  XSPI_AR_ADDRESS                               /*!< Address */
18513 
18514 /*****************  Bit definition for OCTOSPI_DR register  *******************/
18515 #define OCTOSPI_DR_DATA_Pos                 XSPI_DR_DATA_Pos
18516 #define OCTOSPI_DR_DATA_Msk                 XSPI_DR_DATA_Msk                              /*!< 0xFFFFFFFF */
18517 #define OCTOSPI_DR_DATA                     XSPI_DR_DATA                                  /*!< Data */
18518 
18519 /***************  Bit definition for OCTOSPI_PSMKR register  ******************/
18520 #define OCTOSPI_PSMKR_MASK_Pos              XSPI_PSMKR_MASK_Pos
18521 #define OCTOSPI_PSMKR_MASK_Msk              XSPI_PSMKR_MASK_Msk                           /*!< 0xFFFFFFFF */
18522 #define OCTOSPI_PSMKR_MASK                  XSPI_PSMKR_MASK                               /*!< Status mask */
18523 
18524 /***************  Bit definition for OCTOSPI_PSMAR register  ******************/
18525 #define OCTOSPI_PSMAR_MATCH_Pos             XSPI_PSMAR_MATCH_Pos
18526 #define OCTOSPI_PSMAR_MATCH_Msk             XSPI_PSMAR_MATCH_Msk                          /*!< 0xFFFFFFFF */
18527 #define OCTOSPI_PSMAR_MATCH                 XSPI_PSMAR_MATCH                              /*!< Status match */
18528 
18529 /****************  Bit definition for OCTOSPI_PIR register  *******************/
18530 #define OCTOSPI_PIR_INTERVAL_Pos            XSPI_PIR_INTERVAL_Pos
18531 #define OCTOSPI_PIR_INTERVAL_Msk            XSPI_PIR_INTERVAL_Msk                         /*!< 0x0000FFFF */
18532 #define OCTOSPI_PIR_INTERVAL                XSPI_PIR_INTERVAL                             /*!< Polling Interval */
18533 
18534 /****************  Bit definition for OCTOSPI_CCR register  *******************/
18535 #define OCTOSPI_CCR_IMODE_Pos               XSPI_CCR_IMODE_Pos
18536 #define OCTOSPI_CCR_IMODE_Msk               XSPI_CCR_IMODE_Msk                            /*!< 0x00000007 */
18537 #define OCTOSPI_CCR_IMODE                   XSPI_CCR_IMODE                                /*!< Instruction Mode */
18538 #define OCTOSPI_CCR_IMODE_0                 XSPI_CCR_IMODE_0                              /*!< 0x00000001 */
18539 #define OCTOSPI_CCR_IMODE_1                 XSPI_CCR_IMODE_1                              /*!< 0x00000002 */
18540 #define OCTOSPI_CCR_IMODE_2                 XSPI_CCR_IMODE_2                              /*!< 0x00000004 */
18541 #define OCTOSPI_CCR_IDTR_Pos                XSPI_CCR_IDTR_Pos
18542 #define OCTOSPI_CCR_IDTR_Msk                XSPI_CCR_IDTR_Msk                             /*!< 0x00000008 */
18543 #define OCTOSPI_CCR_IDTR                    XSPI_CCR_IDTR                                 /*!< Instruction Double Transfer Rate */
18544 #define OCTOSPI_CCR_ISIZE_Pos               XSPI_CCR_ISIZE_Pos
18545 #define OCTOSPI_CCR_ISIZE_Msk               XSPI_CCR_ISIZE_Msk                            /*!< 0x00000030 */
18546 #define OCTOSPI_CCR_ISIZE                   XSPI_CCR_ISIZE                                /*!< Instruction Size */
18547 #define OCTOSPI_CCR_ISIZE_0                 XSPI_CCR_ISIZE_0                              /*!< 0x00000010 */
18548 #define OCTOSPI_CCR_ISIZE_1                 XSPI_CCR_ISIZE_1                              /*!< 0x00000020 */
18549 #define OCTOSPI_CCR_ADMODE_Pos              XSPI_CCR_ADMODE_Pos
18550 #define OCTOSPI_CCR_ADMODE_Msk              XSPI_CCR_ADMODE_Msk                           /*!< 0x00000700 */
18551 #define OCTOSPI_CCR_ADMODE                  XSPI_CCR_ADMODE                               /*!< Address Mode */
18552 #define OCTOSPI_CCR_ADMODE_0                XSPI_CCR_ADMODE_0                             /*!< 0x00000100 */
18553 #define OCTOSPI_CCR_ADMODE_1                XSPI_CCR_ADMODE_1                             /*!< 0x00000200 */
18554 #define OCTOSPI_CCR_ADMODE_2                XSPI_CCR_ADMODE_2                             /*!< 0x00000400 */
18555 #define OCTOSPI_CCR_ADDTR_Pos               XSPI_CCR_ADDTR_Pos
18556 #define OCTOSPI_CCR_ADDTR_Msk               XSPI_CCR_ADDTR_Msk                            /*!< 0x00000800 */
18557 #define OCTOSPI_CCR_ADDTR                   XSPI_CCR_ADDTR                                /*!< Address Double Transfer Rate */
18558 #define OCTOSPI_CCR_ADSIZE_Pos              XSPI_CCR_ADSIZE_Pos
18559 #define OCTOSPI_CCR_ADSIZE_Msk              XSPI_CCR_ADSIZE_Msk                           /*!< 0x00003000 */
18560 #define OCTOSPI_CCR_ADSIZE                  XSPI_CCR_ADSIZE                               /*!< Address Size */
18561 #define OCTOSPI_CCR_ADSIZE_0                XSPI_CCR_ADSIZE_0                             /*!< 0x00001000 */
18562 #define OCTOSPI_CCR_ADSIZE_1                XSPI_CCR_ADSIZE_1                             /*!< 0x00002000 */
18563 #define OCTOSPI_CCR_ABMODE_Pos              XSPI_CCR_ABMODE_Pos
18564 #define OCTOSPI_CCR_ABMODE_Msk              XSPI_CCR_ABMODE_Msk                           /*!< 0x00070000 */
18565 #define OCTOSPI_CCR_ABMODE                  XSPI_CCR_ABMODE                               /*!< Alternate Bytes Mode */
18566 #define OCTOSPI_CCR_ABMODE_0                XSPI_CCR_ABMODE_0                             /*!< 0x00010000 */
18567 #define OCTOSPI_CCR_ABMODE_1                XSPI_CCR_ABMODE_1                             /*!< 0x00020000 */
18568 #define OCTOSPI_CCR_ABMODE_2                XSPI_CCR_ABMODE_2                             /*!< 0x00040000 */
18569 #define OCTOSPI_CCR_ABDTR_Pos               XSPI_CCR_ABDTR_Pos
18570 #define OCTOSPI_CCR_ABDTR_Msk               XSPI_CCR_ABDTR_Msk                            /*!< 0x00080000 */
18571 #define OCTOSPI_CCR_ABDTR                   XSPI_CCR_ABDTR                                /*!< Alternate Bytes Double Transfer Rate */
18572 #define OCTOSPI_CCR_ABSIZE_Pos              XSPI_CCR_ABSIZE_Pos
18573 #define OCTOSPI_CCR_ABSIZE_Msk              XSPI_CCR_ABSIZE_Msk                           /*!< 0x00300000 */
18574 #define OCTOSPI_CCR_ABSIZE                  XSPI_CCR_ABSIZE                               /*!< Alternate Bytes Size */
18575 #define OCTOSPI_CCR_ABSIZE_0                XSPI_CCR_ABSIZE_0                             /*!< 0x00100000 */
18576 #define OCTOSPI_CCR_ABSIZE_1                XSPI_CCR_ABSIZE_1                             /*!< 0x00200000 */
18577 #define OCTOSPI_CCR_DMODE_Pos               XSPI_CCR_DMODE_Pos
18578 #define OCTOSPI_CCR_DMODE_Msk               XSPI_CCR_DMODE_Msk                            /*!< 0x07000000 */
18579 #define OCTOSPI_CCR_DMODE                   XSPI_CCR_DMODE                                /*!< Data Mode */
18580 #define OCTOSPI_CCR_DMODE_0                 XSPI_CCR_DMODE_0                              /*!< 0x01000000 */
18581 #define OCTOSPI_CCR_DMODE_1                 XSPI_CCR_DMODE_1                              /*!< 0x02000000 */
18582 #define OCTOSPI_CCR_DMODE_2                 XSPI_CCR_DMODE_2                              /*!< 0x04000000 */
18583 #define OCTOSPI_CCR_DDTR_Pos                XSPI_CCR_DDTR_Pos
18584 #define OCTOSPI_CCR_DDTR_Msk                XSPI_CCR_DDTR_Msk                             /*!< 0x08000000 */
18585 #define OCTOSPI_CCR_DDTR                    XSPI_CCR_DDTR                                 /*!< Data Double Transfer Rate */
18586 #define OCTOSPI_CCR_DQSE_Pos                XSPI_CCR_DQSE_Pos
18587 #define OCTOSPI_CCR_DQSE_Msk                XSPI_CCR_DQSE_Msk                             /*!< 0x20000000 */
18588 #define OCTOSPI_CCR_DQSE                    XSPI_CCR_DQSE                                 /*!< DQS Enable */
18589 #define OCTOSPI_CCR_SIOO_Pos                XSPI_CCR_SIOO_Pos
18590 #define OCTOSPI_CCR_SIOO_Msk                XSPI_CCR_SIOO_Msk                             /*!< 0x80000000 */
18591 #define OCTOSPI_CCR_SIOO                    XSPI_CCR_SIOO                                 /*!< Send Instruction Only Once Mode */
18592 
18593 /****************  Bit definition for OCTOSPI_TCR register  *******************/
18594 #define OCTOSPI_TCR_DCYC_Pos                XSPI_TCR_DCYC_Pos
18595 #define OCTOSPI_TCR_DCYC_Msk                XSPI_TCR_DCYC_Msk                             /*!< 0x0000001F */
18596 #define OCTOSPI_TCR_DCYC                    XSPI_TCR_DCYC                                 /*!< Number of Dummy Cycles */
18597 #define OCTOSPI_TCR_DHQC_Pos                XSPI_TCR_DHQC_Pos
18598 #define OCTOSPI_TCR_DHQC_Msk                XSPI_TCR_DHQC_Msk                             /*!< 0x10000000 */
18599 #define OCTOSPI_TCR_DHQC                    XSPI_TCR_DHQC                                 /*!< Delay Hold Quarter Cycle */
18600 #define OCTOSPI_TCR_SSHIFT_Pos              XSPI_TCR_SSHIFT_Pos
18601 #define OCTOSPI_TCR_SSHIFT_Msk              XSPI_TCR_SSHIFT_Msk                           /*!< 0x40000000 */
18602 #define OCTOSPI_TCR_SSHIFT                  XSPI_TCR_SSHIFT                               /*!< Sample Shift */
18603 
18604 /*****************  Bit definition for OCTOSPI_IR register  *******************/
18605 #define OCTOSPI_IR_INSTRUCTION_Pos          XSPI_IR_INSTRUCTION_Pos
18606 #define OCTOSPI_IR_INSTRUCTION_Msk          XSPI_IR_INSTRUCTION_Msk                       /*!< 0xFFFFFFFF */
18607 #define OCTOSPI_IR_INSTRUCTION              XSPI_IR_INSTRUCTION                           /*!< Instruction */
18608 
18609 /****************  Bit definition for OCTOSPI_ABR register  *******************/
18610 #define OCTOSPI_ABR_ALTERNATE_Pos           XSPI_ABR_ALTERNATE_Pos
18611 #define OCTOSPI_ABR_ALTERNATE_Msk           XSPI_ABR_ALTERNATE_Msk                        /*!< 0xFFFFFFFF */
18612 #define OCTOSPI_ABR_ALTERNATE               XSPI_ABR_ALTERNATE                            /*!< Alternate Bytes */
18613 
18614 /****************  Bit definition for OCTOSPI_LPTR register  ******************/
18615 #define OCTOSPI_LPTR_TIMEOUT_Pos            XSPI_LPTR_TIMEOUT_Pos
18616 #define OCTOSPI_LPTR_TIMEOUT_Msk            XSPI_LPTR_TIMEOUT_Msk                         /*!< 0x0000FFFF */
18617 #define OCTOSPI_LPTR_TIMEOUT                XSPI_LPTR_TIMEOUT                             /*!< Timeout period */
18618 
18619 /****************  Bit definition for OCTOSPI_WPCCR register  *******************/
18620 #define OCTOSPI_WPCCR_IMODE_Pos             XSPI_WPCCR_IMODE_Pos
18621 #define OCTOSPI_WPCCR_IMODE_Msk             XSPI_WPCCR_IMODE_Msk                          /*!< 0x00000007 */
18622 #define OCTOSPI_WPCCR_IMODE                 XSPI_WPCCR_IMODE                              /*!< Instruction Mode */
18623 #define OCTOSPI_WPCCR_IMODE_0               XSPI_WPCCR_IMODE_0                            /*!< 0x00000001 */
18624 #define OCTOSPI_WPCCR_IMODE_1               XSPI_WPCCR_IMODE_1                            /*!< 0x00000002 */
18625 #define OCTOSPI_WPCCR_IMODE_2               XSPI_WPCCR_IMODE_2                            /*!< 0x00000004 */
18626 #define OCTOSPI_WPCCR_IDTR_Pos              XSPI_WPCCR_IDTR_Pos
18627 #define OCTOSPI_WPCCR_IDTR_Msk              XSPI_WPCCR_IDTR_Msk                           /*!< 0x00000008 */
18628 #define OCTOSPI_WPCCR_IDTR                  XSPI_WPCCR_IDTR                               /*!< Instruction Double Transfer Rate */
18629 #define OCTOSPI_WPCCR_ISIZE_Pos             XSPI_WPCCR_ISIZE_Pos
18630 #define OCTOSPI_WPCCR_ISIZE_Msk             XSPI_WPCCR_ISIZE_Msk                          /*!< 0x00000030 */
18631 #define OCTOSPI_WPCCR_ISIZE                 XSPI_WPCCR_ISIZE                              /*!< Instruction Size */
18632 #define OCTOSPI_WPCCR_ISIZE_0               XSPI_WPCCR_ISIZE_0                            /*!< 0x00000010 */
18633 #define OCTOSPI_WPCCR_ISIZE_1               XSPI_WPCCR_ISIZE_1                            /*!< 0x00000020 */
18634 #define OCTOSPI_WPCCR_ADMODE_Pos            XSPI_WPCCR_ADMODE_Pos
18635 #define OCTOSPI_WPCCR_ADMODE_Msk            XSPI_WPCCR_ADMODE_Msk                         /*!< 0x00000700 */
18636 #define OCTOSPI_WPCCR_ADMODE                XSPI_WPCCR_ADMODE                             /*!< Address Mode */
18637 #define OCTOSPI_WPCCR_ADMODE_0              XSPI_WPCCR_ADMODE_0                           /*!< 0x00000100 */
18638 #define OCTOSPI_WPCCR_ADMODE_1              XSPI_WPCCR_ADMODE_1                           /*!< 0x00000200 */
18639 #define OCTOSPI_WPCCR_ADMODE_2              XSPI_WPCCR_ADMODE_2                           /*!< 0x00000400 */
18640 #define OCTOSPI_WPCCR_ADDTR_Pos             XSPI_WPCCR_ADDTR_Pos
18641 #define OCTOSPI_WPCCR_ADDTR_Msk             XSPI_WPCCR_ADDTR_Msk                          /*!< 0x00000800 */
18642 #define OCTOSPI_WPCCR_ADDTR                 XSPI_WPCCR_ADDTR                              /*!< Address Double Transfer Rate */
18643 #define OCTOSPI_WPCCR_ADSIZE_Pos            XSPI_WPCCR_ADSIZE_Pos
18644 #define OCTOSPI_WPCCR_ADSIZE_Msk            XSPI_WPCCR_ADSIZE_Msk                         /*!< 0x00003000 */
18645 #define OCTOSPI_WPCCR_ADSIZE                XSPI_WPCCR_ADSIZE                             /*!< Address Size */
18646 #define OCTOSPI_WPCCR_ADSIZE_0              XSPI_WPCCR_ADSIZE_0                           /*!< 0x00001000 */
18647 #define OCTOSPI_WPCCR_ADSIZE_1              XSPI_WPCCR_ADSIZE_1                           /*!< 0x00002000 */
18648 #define OCTOSPI_WPCCR_ABMODE_Pos            XSPI_WPCCR_ABMODE_Pos
18649 #define OCTOSPI_WPCCR_ABMODE_Msk            XSPI_WPCCR_ABMODE_Msk                         /*!< 0x00070000 */
18650 #define OCTOSPI_WPCCR_ABMODE                XSPI_WPCCR_ABMODE                             /*!< Alternate Bytes Mode */
18651 #define OCTOSPI_WPCCR_ABMODE_0              XSPI_WPCCR_ABMODE_0                           /*!< 0x00010000 */
18652 #define OCTOSPI_WPCCR_ABMODE_1              XSPI_WPCCR_ABMODE_1                           /*!< 0x00020000 */
18653 #define OCTOSPI_WPCCR_ABMODE_2              XSPI_WPCCR_ABMODE_2                           /*!< 0x00040000 */
18654 #define OCTOSPI_WPCCR_ABDTR_Pos             XSPI_WPCCR_ABDTR_Pos
18655 #define OCTOSPI_WPCCR_ABDTR_Msk             XSPI_WPCCR_ABDTR_Msk                          /*!< 0x00080000 */
18656 #define OCTOSPI_WPCCR_ABDTR                 XSPI_WPCCR_ABDTR                              /*!< Alternate Bytes Double Transfer Rate */
18657 #define OCTOSPI_WPCCR_ABSIZE_Pos            XSPI_WPCCR_ABSIZE_Pos
18658 #define OCTOSPI_WPCCR_ABSIZE_Msk            XSPI_WPCCR_ABSIZE_Msk                         /*!< 0x00300000 */
18659 #define OCTOSPI_WPCCR_ABSIZE                XSPI_WPCCR_ABSIZE                             /*!< Alternate Bytes Size */
18660 #define OCTOSPI_WPCCR_ABSIZE_0              XSPI_WPCCR_ABSIZE_0                           /*!< 0x00100000 */
18661 #define OCTOSPI_WPCCR_ABSIZE_1              XSPI_WPCCR_ABSIZE_1                           /*!< 0x00200000 */
18662 #define OCTOSPI_WPCCR_DMODE_Pos             XSPI_WPCCR_DMODE_Pos
18663 #define OCTOSPI_WPCCR_DMODE_Msk             XSPI_WPCCR_DMODE_Msk                          /*!< 0x07000000 */
18664 #define OCTOSPI_WPCCR_DMODE                 XSPI_WPCCR_DMODE                              /*!< Data Mode */
18665 #define OCTOSPI_WPCCR_DMODE_0               XSPI_WPCCR_DMODE_0                            /*!< 0x01000000 */
18666 #define OCTOSPI_WPCCR_DMODE_1               XSPI_WPCCR_DMODE_1                            /*!< 0x02000000 */
18667 #define OCTOSPI_WPCCR_DMODE_2               XSPI_WPCCR_DMODE_2                            /*!< 0x04000000 */
18668 #define OCTOSPI_WPCCR_DDTR_Pos              XSPI_WPCCR_DDTR_Pos
18669 #define OCTOSPI_WPCCR_DDTR_Msk              XSPI_WPCCR_DDTR_Msk                           /*!< 0x08000000 */
18670 #define OCTOSPI_WPCCR_DDTR                  XSPI_WPCCR_DDTR                               /*!< Data Double Transfer Rate */
18671 #define OCTOSPI_WPCCR_DQSE_Pos              XSPI_WPCCR_DQSE_Pos
18672 #define OCTOSPI_WPCCR_DQSE_Msk              XSPI_WPCCR_DQSE_Msk                           /*!< 0x20000000 */
18673 #define OCTOSPI_WPCCR_DQSE                  XSPI_WPCCR_DQSE                               /*!< DQS Enable */
18674 
18675 /****************  Bit definition for OCTOSPI_WPTCR register  *******************/
18676 #define OCTOSPI_WPTCR_DCYC_Pos              XSPI_WPTCR_DCYC_Pos
18677 #define OCTOSPI_WPTCR_DCYC_Msk              XSPI_WPTCR_DCYC_Msk                           /*!< 0x0000001F */
18678 #define OCTOSPI_WPTCR_DCYC                  XSPI_WPTCR_DCYC                               /*!< Number of Dummy Cycles */
18679 #define OCTOSPI_WPTCR_DHQC_Pos              XSPI_WPTCR_DHQC_Pos
18680 #define OCTOSPI_WPTCR_DHQC_Msk              XSPI_WPTCR_DHQC_Msk                           /*!< 0x10000000 */
18681 #define OCTOSPI_WPTCR_DHQC                  XSPI_WPTCR_DHQC                               /*!< Delay Hold Quarter Cycle */
18682 #define OCTOSPI_WPTCR_SSHIFT_Pos            XSPI_WPTCR_SSHIFT_Pos
18683 #define OCTOSPI_WPTCR_SSHIFT_Msk            XSPI_WPTCR_SSHIFT_Msk                         /*!< 0x40000000 */
18684 #define OCTOSPI_WPTCR_SSHIFT                XSPI_WPTCR_SSHIFT                             /*!< Sample Shift */
18685 
18686 /*****************  Bit definition for OCTOSPI_WPIR register  *******************/
18687 #define OCTOSPI_WPIR_INSTRUCTION_Pos        XSPI_WPIR_INSTRUCTION_Pos
18688 #define OCTOSPI_WPIR_INSTRUCTION_Msk        XSPI_WPIR_INSTRUCTION_Msk                     /*!< 0xFFFFFFFF */
18689 #define OCTOSPI_WPIR_INSTRUCTION            XSPI_WPIR_INSTRUCTION                         /*!< Instruction */
18690 
18691 /****************  Bit definition for OCTOSPI_WPABR register  *******************/
18692 #define OCTOSPI_WPABR_ALTERNATE_Pos         XSPI_WPABR_ALTERNATE_Pos
18693 #define OCTOSPI_WPABR_ALTERNATE_Msk         XSPI_WPABR_ALTERNATE_Msk                      /*!< 0xFFFFFFFF */
18694 #define OCTOSPI_WPABR_ALTERNATE             XSPI_WPABR_ALTERNATE                          /*!< Alternate Bytes */
18695 
18696 /****************  Bit definition for OCTOSPI_WCCR register  ******************/
18697 #define OCTOSPI_WCCR_IMODE_Pos              XSPI_WCCR_IMODE_Pos
18698 #define OCTOSPI_WCCR_IMODE_Msk              XSPI_WCCR_IMODE_Msk                           /*!< 0x00000007 */
18699 #define OCTOSPI_WCCR_IMODE                  XSPI_WCCR_IMODE                               /*!< Instruction Mode */
18700 #define OCTOSPI_WCCR_IMODE_0                XSPI_WCCR_IMODE_0                             /*!< 0x00000001 */
18701 #define OCTOSPI_WCCR_IMODE_1                XSPI_WCCR_IMODE_1                             /*!< 0x00000002 */
18702 #define OCTOSPI_WCCR_IMODE_2                XSPI_WCCR_IMODE_2                             /*!< 0x00000004 */
18703 #define OCTOSPI_WCCR_IDTR_Pos               XSPI_WCCR_IDTR_Pos
18704 #define OCTOSPI_WCCR_IDTR_Msk               XSPI_WCCR_IDTR_Msk                            /*!< 0x00000008 */
18705 #define OCTOSPI_WCCR_IDTR                   XSPI_WCCR_IDTR                                /*!< Instruction Double Transfer Rate */
18706 #define OCTOSPI_WCCR_ISIZE_Pos              XSPI_WCCR_ISIZE_Pos
18707 #define OCTOSPI_WCCR_ISIZE_Msk              XSPI_WCCR_ISIZE_Msk                           /*!< 0x00000030 */
18708 #define OCTOSPI_WCCR_ISIZE                  XSPI_WCCR_ISIZE                               /*!< Instruction Size */
18709 #define OCTOSPI_WCCR_ISIZE_0                XSPI_WCCR_ISIZE_0                             /*!< 0x00000010 */
18710 #define OCTOSPI_WCCR_ISIZE_1                XSPI_WCCR_ISIZE_1                             /*!< 0x00000020 */
18711 #define OCTOSPI_WCCR_ADMODE_Pos             XSPI_WCCR_ADMODE_Pos
18712 #define OCTOSPI_WCCR_ADMODE_Msk             XSPI_WCCR_ADMODE_Msk                          /*!< 0x00000700 */
18713 #define OCTOSPI_WCCR_ADMODE                 XSPI_WCCR_ADMODE                              /*!< Address Mode */
18714 #define OCTOSPI_WCCR_ADMODE_0               XSPI_WCCR_ADMODE_0                            /*!< 0x00000100 */
18715 #define OCTOSPI_WCCR_ADMODE_1               XSPI_WCCR_ADMODE_1                            /*!< 0x00000200 */
18716 #define OCTOSPI_WCCR_ADMODE_2               XSPI_WCCR_ADMODE_2                            /*!< 0x00000400 */
18717 #define OCTOSPI_WCCR_ADDTR_Pos              XSPI_WCCR_ADDTR_Pos
18718 #define OCTOSPI_WCCR_ADDTR_Msk              XSPI_WCCR_ADDTR_Msk                           /*!< 0x00000800 */
18719 #define OCTOSPI_WCCR_ADDTR                  XSPI_WCCR_ADDTR                               /*!< Address Double Transfer Rate */
18720 #define OCTOSPI_WCCR_ADSIZE_Pos             XSPI_WCCR_ADSIZE_Pos
18721 #define OCTOSPI_WCCR_ADSIZE_Msk             XSPI_WCCR_ADSIZE_Msk                          /*!< 0x00003000 */
18722 #define OCTOSPI_WCCR_ADSIZE                 XSPI_WCCR_ADSIZE                              /*!< Address Size */
18723 #define OCTOSPI_WCCR_ADSIZE_0               XSPI_WCCR_ADSIZE_0                            /*!< 0x00001000 */
18724 #define OCTOSPI_WCCR_ADSIZE_1               XSPI_WCCR_ADSIZE_1                            /*!< 0x00002000 */
18725 #define OCTOSPI_WCCR_ABMODE_Pos             XSPI_WCCR_ABMODE_Pos
18726 #define OCTOSPI_WCCR_ABMODE_Msk             XSPI_WCCR_ABMODE_Msk                          /*!< 0x00070000 */
18727 #define OCTOSPI_WCCR_ABMODE                 XSPI_WCCR_ABMODE                              /*!< Alternate Bytes Mode */
18728 #define OCTOSPI_WCCR_ABMODE_0               XSPI_WCCR_ABMODE_0                            /*!< 0x00010000 */
18729 #define OCTOSPI_WCCR_ABMODE_1               XSPI_WCCR_ABMODE_1                            /*!< 0x00020000 */
18730 #define OCTOSPI_WCCR_ABMODE_2               XSPI_WCCR_ABMODE_2                            /*!< 0x00040000 */
18731 #define OCTOSPI_WCCR_ABDTR_Pos              XSPI_WCCR_ABDTR_Pos
18732 #define OCTOSPI_WCCR_ABDTR_Msk              XSPI_WCCR_ABDTR_Msk                           /*!< 0x00080000 */
18733 #define OCTOSPI_WCCR_ABDTR                  XSPI_WCCR_ABDTR                               /*!< Alternate Bytes Double Transfer Rate */
18734 #define OCTOSPI_WCCR_ABSIZE_Pos             XSPI_WCCR_ABSIZE_Pos
18735 #define OCTOSPI_WCCR_ABSIZE_Msk             XSPI_WCCR_ABSIZE_Msk                          /*!< 0x00300000 */
18736 #define OCTOSPI_WCCR_ABSIZE                 XSPI_WCCR_ABSIZE                              /*!< Alternate Bytes Size */
18737 #define OCTOSPI_WCCR_ABSIZE_0               XSPI_WCCR_ABSIZE_0                            /*!< 0x00100000 */
18738 #define OCTOSPI_WCCR_ABSIZE_1               XSPI_WCCR_ABSIZE_1                            /*!< 0x00200000 */
18739 #define OCTOSPI_WCCR_DMODE_Pos              XSPI_WCCR_DMODE_Pos
18740 #define OCTOSPI_WCCR_DMODE_Msk              XSPI_WCCR_DMODE_Msk                           /*!< 0x07000000 */
18741 #define OCTOSPI_WCCR_DMODE                  XSPI_WCCR_DMODE                               /*!< Data Mode */
18742 #define OCTOSPI_WCCR_DMODE_0                XSPI_WCCR_DMODE_0                             /*!< 0x01000000 */
18743 #define OCTOSPI_WCCR_DMODE_1                XSPI_WCCR_DMODE_1                             /*!< 0x02000000 */
18744 #define OCTOSPI_WCCR_DMODE_2                XSPI_WCCR_DMODE_2                             /*!< 0x04000000 */
18745 #define OCTOSPI_WCCR_DDTR_Pos               XSPI_WCCR_DDTR_Pos
18746 #define OCTOSPI_WCCR_DDTR_Msk               XSPI_WCCR_DDTR_Msk                            /*!< 0x08000000 */
18747 #define OCTOSPI_WCCR_DDTR                   XSPI_WCCR_DDTR                                /*!< Data Double Transfer Rate */
18748 #define OCTOSPI_WCCR_DQSE_Pos               XSPI_WCCR_DQSE_Pos
18749 #define OCTOSPI_WCCR_DQSE_Msk               XSPI_WCCR_DQSE_Msk                            /*!< 0x20000000 */
18750 #define OCTOSPI_WCCR_DQSE                   XSPI_WCCR_DQSE                                /*!< DQS Enable */
18751 
18752 /****************  Bit definition for OCTOSPI_WTCR register  ******************/
18753 #define OCTOSPI_WTCR_DCYC_Pos               XSPI_WTCR_DCYC_Pos
18754 #define OCTOSPI_WTCR_DCYC_Msk               XSPI_WTCR_DCYC_Msk                            /*!< 0x0000001F */
18755 #define OCTOSPI_WTCR_DCYC                   XSPI_WTCR_DCYC                                /*!< Number of Dummy Cycles */
18756 
18757 /****************  Bit definition for OCTOSPI_WIR register  *******************/
18758 #define OCTOSPI_WIR_INSTRUCTION_Pos         XSPI_WIR_INSTRUCTION_Pos
18759 #define OCTOSPI_WIR_INSTRUCTION_Msk         XSPI_WIR_INSTRUCTION_Msk                      /*!< 0xFFFFFFFF */
18760 #define OCTOSPI_WIR_INSTRUCTION             XSPI_WIR_INSTRUCTION                          /*!< Instruction */
18761 
18762 /****************  Bit definition for OCTOSPI_WABR register  ******************/
18763 #define OCTOSPI_WABR_ALTERNATE_Pos          XSPI_WABR_ALTERNATE_Pos
18764 #define OCTOSPI_WABR_ALTERNATE_Msk          XSPI_WABR_ALTERNATE_Msk                       /*!< 0xFFFFFFFF */
18765 #define OCTOSPI_WABR_ALTERNATE              XSPI_WABR_ALTERNATE                           /*!< Alternate Bytes */
18766 
18767 /****************  Bit definition for OCTOSPI_HLCR register  ******************/
18768 #define OCTOSPI_HLCR_LM_Pos                 XSPI_HLCR_LM_Pos
18769 #define OCTOSPI_HLCR_LM_Msk                 XSPI_HLCR_LM_Msk                              /*!< 0x00000001 */
18770 #define OCTOSPI_HLCR_LM                     XSPI_HLCR_LM                                  /*!< Latency Mode */
18771 #define OCTOSPI_HLCR_WZL_Pos                XSPI_HLCR_WZL_Pos
18772 #define OCTOSPI_HLCR_WZL_Msk                XSPI_HLCR_WZL_Msk                             /*!< 0x00000002 */
18773 #define OCTOSPI_HLCR_WZL                    XSPI_HLCR_WZL                                 /*!< Write Zero Latency */
18774 #define OCTOSPI_HLCR_TACC_Pos               XSPI_HLCR_TACC_Pos
18775 #define OCTOSPI_HLCR_TACC_Msk               XSPI_HLCR_TACC_Msk                            /*!< 0x0000FF00 */
18776 #define OCTOSPI_HLCR_TACC                   XSPI_HLCR_TACC                                /*!< Access Time */
18777 #define OCTOSPI_HLCR_TRWR_Pos               XSPI_HLCR_TRWR_Pos
18778 #define OCTOSPI_HLCR_TRWR_Msk               XSPI_HLCR_TRWR_Msk                            /*!< 0x00FF0000 */
18779 #define OCTOSPI_HLCR_TRWR                   XSPI_HLCR_TRWR                                /*!< Read Write Recovery Time */
18780 
18781 /******************************************************************************/
18782 /*                                                                            */
18783 /*                            Hexadeca-SPI (HSPI)                             */
18784 /*                                                                            */
18785 /******************************************************************************/
18786 /************* Bit definition for HSPI_CR register  ***************************/
18787 #define HSPI_CR_EN_Pos                   XSPI_CR_EN_Pos
18788 #define HSPI_CR_EN_Msk                   XSPI_CR_EN_Msk                                   /*!< 0x00000001 */
18789 #define HSPI_CR_EN                       XSPI_CR_EN                                       /*!< Enable */
18790 #define HSPI_CR_ABORT_Pos                XSPI_CR_ABORT_Pos
18791 #define HSPI_CR_ABORT_Msk                XSPI_CR_ABORT_Msk                                /*!< 0x00000002 */
18792 #define HSPI_CR_ABORT                    XSPI_CR_ABORT                                    /*!< Abort request */
18793 #define HSPI_CR_DMAEN_Pos                XSPI_CR_DMAEN_Pos
18794 #define HSPI_CR_DMAEN_Msk                XSPI_CR_DMAEN_Msk                                /*!< 0x00000004 */
18795 #define HSPI_CR_DMAEN                    XSPI_CR_DMAEN                                    /*!< DMA Enable */
18796 #define HSPI_CR_TCEN_Pos                 XSPI_CR_TCEN_Pos
18797 #define HSPI_CR_TCEN_Msk                 XSPI_CR_TCEN_Msk                                 /*!< 0x00000008 */
18798 #define HSPI_CR_TCEN                     XSPI_CR_TCEN                                     /*!< Timeout Counter Enable */
18799 #define HSPI_CR_DMM_Pos                  XSPI_CR_DMM_Pos
18800 #define HSPI_CR_DMM_Msk                  XSPI_CR_DMM_Msk                                  /*!< 0x00000040 */
18801 #define HSPI_CR_DMM                      XSPI_CR_DMM                                      /*!< Dual Memory Mode */
18802 #define HSPI_CR_FTHRES_Pos               XSPI_CR_FTHRES_Pos
18803 #define HSPI_CR_FTHRES_Msk               XSPI_CR_FTHRES_Msk                               /*!< 0x00003F00 */
18804 #define HSPI_CR_FTHRES                   XSPI_CR_FTHRES                                   /*!< FIFO Threshold Level*/
18805 #define HSPI_CR_TEIE_Pos                 XSPI_CR_TEIE_Pos
18806 #define HSPI_CR_TEIE_Msk                 XSPI_CR_TEIE_Msk                                 /*!< 0x00010000 */
18807 #define HSPI_CR_TEIE                     XSPI_CR_TEIE                                     /*!< Transfer Error Interrupt Enable */
18808 #define HSPI_CR_TCIE_Pos                 XSPI_CR_TCIE_Pos
18809 #define HSPI_CR_TCIE_Msk                 XSPI_CR_TCIE_Msk                                 /*!< 0x00020000 */
18810 #define HSPI_CR_TCIE                     XSPI_CR_TCIE                                     /*!< Transfer Complete Interrupt Enable */
18811 #define HSPI_CR_FTIE_Pos                 XSPI_CR_FTIE_Pos
18812 #define HSPI_CR_FTIE_Msk                 XSPI_CR_FTIE_Msk                                 /*!< 0x00040000 */
18813 #define HSPI_CR_FTIE                     XSPI_CR_FTIE                                     /*!< FIFO Threshold Interrupt Enable */
18814 #define HSPI_CR_SMIE_Pos                 XSPI_CR_SMIE_Pos
18815 #define HSPI_CR_SMIE_Msk                 XSPI_CR_SMIE_Msk                                 /*!< 0x00080000 */
18816 #define HSPI_CR_SMIE                     XSPI_CR_SMIE                                     /*!< Status Match Interrupt Enable */
18817 #define HSPI_CR_TOIE_Pos                 XSPI_CR_TOIE_Pos
18818 #define HSPI_CR_TOIE_Msk                 XSPI_CR_TOIE_Msk                                 /*!< 0x00100000 */
18819 #define HSPI_CR_TOIE                     XSPI_CR_TOIE                                     /*!< TimeOut Interrupt Enable */
18820 #define HSPI_CR_APMS_Pos                 XSPI_CR_APMS_Pos
18821 #define HSPI_CR_APMS_Msk                 XSPI_CR_APMS_Msk                                 /*!< 0x00400000 */
18822 #define HSPI_CR_APMS                     XSPI_CR_APMS                                     /*!< Automatic Poll Mode Stop */
18823 #define HSPI_CR_PMM_Pos                  XSPI_CR_PMM_Pos
18824 #define HSPI_CR_PMM_Msk                  XSPI_CR_PMM_Msk                                  /*!< 0x00800000 */
18825 #define HSPI_CR_PMM                      XSPI_CR_PMM                                      /*!< Polling Match Mode */
18826 #define HSPI_CR_FMODE_Pos                XSPI_CR_FMODE_Pos
18827 #define HSPI_CR_FMODE_Msk                XSPI_CR_FMODE_Msk                                /*!< 0x30000000 */
18828 #define HSPI_CR_FMODE                    XSPI_CR_FMODE                                    /*!< Functional Mode */
18829 #define HSPI_CR_FMODE_0                  XSPI_CR_FMODE_0                                  /*!< 0x10000000 */
18830 #define HSPI_CR_FMODE_1                  XSPI_CR_FMODE_1                                  /*!< 0x20000000 */
18831 #define HSPI_CR_MSEL_Pos                 XSPI_HSPI_CR_MSEL_Pos
18832 #define HSPI_CR_MSEL_Msk                 XSPI_HSPI_CR_MSEL_Msk                            /*!< 0xC0000000 */
18833 #define HSPI_CR_MSEL                     XSPI_HSPI_CR_MSEL                                /*!< Memory Select */
18834 #define HSPI_CR_MSEL_0                   XSPI_HSPI_CR_MSEL_0                              /*!< 0x40000000 */
18835 #define HSPI_CR_MSEL_1                   XSPI_HSPI_CR_MSEL_1                              /*!< 0x80000000 */
18836 
18837 /************* Bit definition for HSPI_DCR1 register  *************************/
18838 #define HSPI_DCR1_CKMODE_Pos             XSPI_DCR1_CKMODE_Pos
18839 #define HSPI_DCR1_CKMODE_Msk             XSPI_DCR1_CKMODE_Msk                             /*!< 0x00000001 */
18840 #define HSPI_DCR1_CKMODE                 XSPI_DCR1_CKMODE                                 /*!< Mode 0 / Mode 3 */
18841 #define HSPI_DCR1_FRCK_Pos               XSPI_DCR1_FRCK_Pos
18842 #define HSPI_DCR1_FRCK_Msk               XSPI_DCR1_FRCK_Msk                               /*!< 0x00000002 */
18843 #define HSPI_DCR1_FRCK                   XSPI_DCR1_FRCK                                   /*!< Free Running Clock */
18844 #define HSPI_DCR1_CSHT_Pos               XSPI_DCR1_CSHT_Pos
18845 #define HSPI_DCR1_CSHT_Msk               XSPI_DCR1_CSHT_Msk                               /*!< 0x00003F00 */
18846 #define HSPI_DCR1_CSHT                   XSPI_DCR1_CSHT                                   /*!< Chip Select High Time */
18847 #define HSPI_DCR1_DEVSIZE_Pos            XSPI_DCR1_DEVSIZE_Pos
18848 #define HSPI_DCR1_DEVSIZE_Msk            XSPI_DCR1_DEVSIZE_Msk                            /*!< 0x001F0000 */
18849 #define HSPI_DCR1_DEVSIZE                XSPI_DCR1_DEVSIZE                                /*!< Device Size */
18850 #define HSPI_DCR1_MTYP_Pos               XSPI_DCR1_MTYP_Pos
18851 #define HSPI_DCR1_MTYP_Msk               XSPI_DCR1_MTYP_Msk                               /*!< 0x07000000 */
18852 #define HSPI_DCR1_MTYP                   XSPI_DCR1_MTYP                                   /*!< Memory Type */
18853 #define HSPI_DCR1_MTYP_0                 XSPI_DCR1_MTYP_0                                 /*!< 0x01000000 */
18854 #define HSPI_DCR1_MTYP_1                 XSPI_DCR1_MTYP_1                                 /*!< 0x02000000 */
18855 #define HSPI_DCR1_MTYP_2                 XSPI_DCR1_MTYP_2                                 /*!< 0x04000000 */
18856 
18857 /************* Bit definition for HSPI_DCR2 register  *************************/
18858 #define HSPI_DCR2_PRESCALER_Pos          XSPI_DCR2_PRESCALER_Pos
18859 #define HSPI_DCR2_PRESCALER_Msk          XSPI_DCR2_PRESCALER_Msk                          /*!< 0x000000FF */
18860 #define HSPI_DCR2_PRESCALER              XSPI_DCR2_PRESCALER                              /*!< Clock prescaler */
18861 #define HSPI_DCR2_WRAPSIZE_Pos           XSPI_DCR2_WRAPSIZE_Pos
18862 #define HSPI_DCR2_WRAPSIZE_Msk           XSPI_DCR2_WRAPSIZE_Msk                           /*!< 0x00070000 */
18863 #define HSPI_DCR2_WRAPSIZE               XSPI_DCR2_WRAPSIZE                               /*!< Wrap Size */
18864 #define HSPI_DCR2_WRAPSIZE_0             XSPI_DCR2_WRAPSIZE_0                             /*!< 0x00010000 */
18865 #define HSPI_DCR2_WRAPSIZE_1             XSPI_DCR2_WRAPSIZE_1                             /*!< 0x00020000 */
18866 #define HSPI_DCR2_WRAPSIZE_2             XSPI_DCR2_WRAPSIZE_2                             /*!< 0x00040000 */
18867 
18868 /************* Bit definition for HSPI_DCR3 register  *************************/
18869 #define HSPI_DCR3_CSBOUND_Pos            XSPI_DCR3_CSBOUND_Pos
18870 #define HSPI_DCR3_CSBOUND_Msk            XSPI_DCR3_CSBOUND_Msk                            /*!< 0x001F0000 */
18871 #define HSPI_DCR3_CSBOUND                XSPI_DCR3_CSBOUND                                /*!< Maximum transfer */
18872 
18873 /************* Bit definition for HSPI_DCR4 register  *************************/
18874 #define HSPI_DCR4_REFRESH_Pos            XSPI_DCR4_REFRESH_Pos
18875 #define HSPI_DCR4_REFRESH_Msk            XSPI_DCR4_REFRESH_Msk                            /*!< 0xFFFFFFFF */
18876 #define HSPI_DCR4_REFRESH                XSPI_DCR4_REFRESH                                /*!< Refresh rate */
18877 
18878 /************* Bit definition for HSPI_SR register  ***************************/
18879 #define HSPI_SR_TEF_Pos                  XSPI_SR_TEF_Pos
18880 #define HSPI_SR_TEF_Msk                  XSPI_SR_TEF_Msk                                  /*!< 0x00000001 */
18881 #define HSPI_SR_TEF                      XSPI_SR_TEF                                      /*!< Transfer Error Flag */
18882 #define HSPI_SR_TCF_Pos                  XSPI_SR_TCF_Pos
18883 #define HSPI_SR_TCF_Msk                  XSPI_SR_TCF_Msk                                  /*!< 0x00000002 */
18884 #define HSPI_SR_TCF                      XSPI_SR_TCF                                      /*!< Transfer Complete Flag */
18885 #define HSPI_SR_FTF_Pos                  XSPI_SR_FTF_Pos
18886 #define HSPI_SR_FTF_Msk                  XSPI_SR_FTF_Msk                                  /*!< 0x00000004 */
18887 #define HSPI_SR_FTF                      XSPI_SR_FTF                                      /*!< FIFO Threshold Flag */
18888 #define HSPI_SR_SMF_Pos                  XSPI_SR_SMF_Pos
18889 #define HSPI_SR_SMF_Msk                  XSPI_SR_SMF_Msk                                  /*!< 0x00000008 */
18890 #define HSPI_SR_SMF                      XSPI_SR_SMF                                      /*!< Status Match Flag */
18891 #define HSPI_SR_TOF_Pos                  XSPI_SR_TOF_Pos
18892 #define HSPI_SR_TOF_Msk                  XSPI_SR_TOF_Msk                                  /*!< 0x00000010 */
18893 #define HSPI_SR_TOF                      XSPI_SR_TOF                                      /*!< Timeout Flag */
18894 #define HSPI_SR_BUSY_Pos                 XSPI_SR_BUSY_Pos
18895 #define HSPI_SR_BUSY_Msk                 XSPI_SR_BUSY_Msk                                 /*!< 0x00000020 */
18896 #define HSPI_SR_BUSY                     XSPI_SR_BUSY                                     /*!< Busy */
18897 #define HSPI_SR_FLEVEL_Pos               XSPI_SR_FLEVEL_Pos
18898 #define HSPI_SR_FLEVEL_Msk               XSPI_SR_FLEVEL_Msk                               /*!< 0x00007F00 */
18899 #define HSPI_SR_FLEVEL                   XSPI_SR_FLEVEL                                   /*!< FIFO Level */
18900 
18901 /************* Bit definition for HSPI_FCR register  *************************/
18902 #define HSPI_FCR_CTEF_Pos                XSPI_FCR_CTEF_Pos
18903 #define HSPI_FCR_CTEF_Msk                XSPI_FCR_CTEF_Msk                                /*!< 0x00000001 */
18904 #define HSPI_FCR_CTEF                    XSPI_FCR_CTEF                                    /*!< Clear Transfer Error Flag */
18905 #define HSPI_FCR_CTCF_Pos                XSPI_FCR_CTCF_Pos
18906 #define HSPI_FCR_CTCF_Msk                XSPI_FCR_CTCF_Msk                                /*!< 0x00000002 */
18907 #define HSPI_FCR_CTCF                    XSPI_FCR_CTCF                                    /*!< Clear Transfer Complete Flag */
18908 #define HSPI_FCR_CSMF_Pos                XSPI_FCR_CSMF_Pos
18909 #define HSPI_FCR_CSMF_Msk                XSPI_FCR_CSMF_Msk                                /*!< 0x00000008 */
18910 #define HSPI_FCR_CSMF                    XSPI_FCR_CSMF                                    /*!< Clear Status Match Flag */
18911 #define HSPI_FCR_CTOF_Pos                XSPI_FCR_CTOF_Pos
18912 #define HSPI_FCR_CTOF_Msk                XSPI_FCR_CTOF_Msk                                /*!< 0x00000010 */
18913 #define HSPI_FCR_CTOF                    XSPI_FCR_CTOF                                    /*!< Clear Timeout Flag */
18914 
18915 /************* Bit definition for HSPI_DLR register  *************************/
18916 #define HSPI_DLR_DL_Pos                  XSPI_DLR_DL_Pos
18917 #define HSPI_DLR_DL_Msk                  XSPI_DLR_DL_Msk                                  /*!< 0xFFFFFFFF */
18918 #define HSPI_DLR_DL                      XSPI_DLR_DL                                      /*!< Data Length */
18919 
18920 /************* Bit definition for HSPI_AR register  *************************/
18921 #define HSPI_AR_ADDRESS_Pos              XSPI_AR_ADDRESS_Pos
18922 #define HSPI_AR_ADDRESS_Msk              XSPI_AR_ADDRESS_Msk                              /*!< 0xFFFFFFFF */
18923 #define HSPI_AR_ADDRESS                  XSPI_AR_ADDRESS                                  /*!< Address */
18924 
18925 /************* Bit definition for HSPI_DR register  *************************/
18926 #define HSPI_DR_DATA_Pos                 XSPI_DR_DATA_Pos
18927 #define HSPI_DR_DATA_Msk                 XSPI_DR_DATA_Msk                                 /*!< 0xFFFFFFFF */
18928 #define HSPI_DR_DATA                     XSPI_DR_DATA                                     /*!< Data */
18929 
18930 /************ Bit definition for HSPI_PSMKR register  ***********************/
18931 #define HSPI_PSMKR_MASK_Pos              XSPI_PSMKR_MASK_Pos
18932 #define HSPI_PSMKR_MASK_Msk              XSPI_PSMKR_MASK_Msk                              /*!< 0xFFFFFFFF */
18933 #define HSPI_PSMKR_MASK                  XSPI_PSMKR_MASK                                  /*!< Status mask */
18934 
18935 /************ Bit definition for HSPI_PSMAR register  ***********************/
18936 #define HSPI_PSMAR_MATCH_Pos             XSPI_PSMAR_MATCH_Pos
18937 #define HSPI_PSMAR_MATCH_Msk             XSPI_PSMAR_MATCH_Msk                             /*!< 0xFFFFFFFF */
18938 #define HSPI_PSMAR_MATCH                 XSPI_PSMAR_MATCH                                 /*!< Status match */
18939 
18940 /************* Bit definition for HSPI_PIR register  ************************/
18941 #define HSPI_PIR_INTERVAL_Pos            XSPI_PIR_INTERVAL_Pos
18942 #define HSPI_PIR_INTERVAL_Msk            XSPI_PIR_INTERVAL_Msk                            /*!< 0x0000FFFF */
18943 #define HSPI_PIR_INTERVAL                XSPI_PIR_INTERVAL                                /*!< Polling Interval */
18944 
18945 /************* Bit definition for HSPI_CCR register  ************************/
18946 #define HSPI_CCR_IMODE_Pos               XSPI_CCR_IMODE_Pos
18947 #define HSPI_CCR_IMODE_Msk               XSPI_CCR_IMODE_Msk                               /*!< 0x00000007 */
18948 #define HSPI_CCR_IMODE                   XSPI_CCR_IMODE                                   /*!< Instruction Mode */
18949 #define HSPI_CCR_IMODE_0                 XSPI_CCR_IMODE_0                                 /*!< 0x00000001 */
18950 #define HSPI_CCR_IMODE_1                 XSPI_CCR_IMODE_1                                 /*!< 0x00000002 */
18951 #define HSPI_CCR_IMODE_2                 XSPI_CCR_IMODE_2                                 /*!< 0x00000004 */
18952 #define HSPI_CCR_IDTR_Pos                XSPI_CCR_IDTR_Pos
18953 #define HSPI_CCR_IDTR_Msk                XSPI_CCR_IDTR_Msk                                /*!< 0x00000008 */
18954 #define HSPI_CCR_IDTR                    XSPI_CCR_IDTR                                    /*!< Instruction Double Transfer Rate */
18955 #define HSPI_CCR_ISIZE_Pos               XSPI_CCR_ISIZE_Pos
18956 #define HSPI_CCR_ISIZE_Msk               XSPI_CCR_ISIZE_Msk                               /*!< 0x00000030 */
18957 #define HSPI_CCR_ISIZE                   XSPI_CCR_ISIZE                                   /*!< Instruction Size */
18958 #define HSPI_CCR_ISIZE_0                 XSPI_CCR_ISIZE_0                                 /*!< 0x00000010 */
18959 #define HSPI_CCR_ISIZE_1                 XSPI_CCR_ISIZE_1                                 /*!< 0x00000020 */
18960 #define HSPI_CCR_ADMODE_Pos              XSPI_CCR_ADMODE_Pos
18961 #define HSPI_CCR_ADMODE_Msk              XSPI_CCR_ADMODE_Msk                              /*!< 0x00000700 */
18962 #define HSPI_CCR_ADMODE                  XSPI_CCR_ADMODE                                  /*!< Address Mode */
18963 #define HSPI_CCR_ADMODE_0                XSPI_CCR_ADMODE_0                                /*!< 0x00000100 */
18964 #define HSPI_CCR_ADMODE_1                XSPI_CCR_ADMODE_1                                /*!< 0x00000200 */
18965 #define HSPI_CCR_ADMODE_2                XSPI_CCR_ADMODE_2                                /*!< 0x00000400 */
18966 #define HSPI_CCR_ADDTR_Pos               XSPI_CCR_ADDTR_Pos
18967 #define HSPI_CCR_ADDTR_Msk               XSPI_CCR_ADDTR_Msk                               /*!< 0x00000800 */
18968 #define HSPI_CCR_ADDTR                   XSPI_CCR_ADDTR                                   /*!< Address Double Transfer Rate */
18969 #define HSPI_CCR_ADSIZE_Pos              XSPI_CCR_ADSIZE_Pos
18970 #define HSPI_CCR_ADSIZE_Msk              XSPI_CCR_ADSIZE_Msk                              /*!< 0x00003000 */
18971 #define HSPI_CCR_ADSIZE                  XSPI_CCR_ADSIZE                                  /*!< Address Size */
18972 #define HSPI_CCR_ADSIZE_0                XSPI_CCR_ADSIZE_0                                /*!< 0x00001000 */
18973 #define HSPI_CCR_ADSIZE_1                XSPI_CCR_ADSIZE_1                                /*!< 0x00002000 */
18974 #define HSPI_CCR_ABMODE_Pos              XSPI_CCR_ABMODE_Pos
18975 #define HSPI_CCR_ABMODE_Msk              XSPI_CCR_ABMODE_Msk                              /*!< 0x00070000 */
18976 #define HSPI_CCR_ABMODE                  XSPI_CCR_ABMODE                                  /*!< Alternate Bytes Mode */
18977 #define HSPI_CCR_ABMODE_0                XSPI_CCR_ABMODE_0                                /*!< 0x00010000 */
18978 #define HSPI_CCR_ABMODE_1                XSPI_CCR_ABMODE_1                                /*!< 0x00020000 */
18979 #define HSPI_CCR_ABMODE_2                XSPI_CCR_ABMODE_2                                /*!< 0x00040000 */
18980 #define HSPI_CCR_ABDTR_Pos               XSPI_CCR_ABDTR_Pos
18981 #define HSPI_CCR_ABDTR_Msk               XSPI_CCR_ABDTR_Msk                               /*!< 0x00080000 */
18982 #define HSPI_CCR_ABDTR                   XSPI_CCR_ABDTR                                   /*!< Alternate Bytes Double Transfer Rate */
18983 #define HSPI_CCR_ABSIZE_Pos              XSPI_CCR_ABSIZE_Pos
18984 #define HSPI_CCR_ABSIZE_Msk              XSPI_CCR_ABSIZE_Msk                              /*!< 0x00300000 */
18985 #define HSPI_CCR_ABSIZE                  XSPI_CCR_ABSIZE                                  /*!< Alternate Bytes Size */
18986 #define HSPI_CCR_ABSIZE_0                XSPI_CCR_ABSIZE_0                                /*!< 0x00100000 */
18987 #define HSPI_CCR_ABSIZE_1                XSPI_CCR_ABSIZE_1                                /*!< 0x00200000 */
18988 #define HSPI_CCR_DMODE_Pos               XSPI_CCR_DMODE_Pos
18989 #define HSPI_CCR_DMODE_Msk               XSPI_CCR_DMODE_Msk                               /*!< 0x07000000 */
18990 #define HSPI_CCR_DMODE                   XSPI_CCR_DMODE                                   /*!< Data Mode */
18991 #define HSPI_CCR_DMODE_0                 XSPI_CCR_DMODE_0                                 /*!< 0x01000000 */
18992 #define HSPI_CCR_DMODE_1                 XSPI_CCR_DMODE_1                                 /*!< 0x02000000 */
18993 #define HSPI_CCR_DMODE_2                 XSPI_CCR_DMODE_2                                 /*!< 0x04000000 */
18994 #define HSPI_CCR_DDTR_Pos                XSPI_CCR_DDTR_Pos
18995 #define HSPI_CCR_DDTR_Msk                XSPI_CCR_DDTR_Msk                                /*!< 0x08000000 */
18996 #define HSPI_CCR_DDTR                    XSPI_CCR_DDTR                                    /*!< Data Double Transfer Rate */
18997 #define HSPI_CCR_DQSE_Pos                XSPI_CCR_DQSE_Pos
18998 #define HSPI_CCR_DQSE_Msk                XSPI_CCR_DQSE_Msk                                /*!< 0x20000000 */
18999 #define HSPI_CCR_DQSE                    XSPI_CCR_DQSE                                    /*!< DQS Enable */
19000 #define HSPI_CCR_SIOO_Pos                XSPI_CCR_SIOO_Pos
19001 #define HSPI_CCR_SIOO_Msk                XSPI_CCR_SIOO_Msk                                /*!< 0x80000000 */
19002 #define HSPI_CCR_SIOO                    XSPI_CCR_SIOO                                    /*!< Send Instruction Only Once Mode */
19003 
19004 /************* Bit definition for HSPI_TCR register  *************************/
19005 #define HSPI_TCR_DCYC_Pos                XSPI_TCR_DCYC_Pos
19006 #define HSPI_TCR_DCYC_Msk                XSPI_TCR_DCYC_Msk                                /*!< 0x0000001F */
19007 #define HSPI_TCR_DCYC                    XSPI_TCR_DCYC                                    /*!< Number of Dummy Cycles */
19008 #define HSPI_TCR_DHQC_Pos                XSPI_TCR_DHQC_Pos
19009 #define HSPI_TCR_DHQC_Msk                XSPI_TCR_DHQC_Msk                                /*!< 0x10000000 */
19010 #define HSPI_TCR_DHQC                    XSPI_TCR_DHQC                                    /*!< Delay Hold Quarter Cycle */
19011 #define HSPI_TCR_SSHIFT_Pos              XSPI_TCR_SSHIFT_Pos
19012 #define HSPI_TCR_SSHIFT_Msk              XSPI_TCR_SSHIFT_Msk                              /*!< 0x40000000 */
19013 #define HSPI_TCR_SSHIFT                  XSPI_TCR_SSHIFT                                  /*!< Sample Shift */
19014 
19015 /************* Bit definition for HSPI_IR register  **************************/
19016 #define HSPI_IR_INSTRUCTION_Pos          XSPI_IR_INSTRUCTION_Pos
19017 #define HSPI_IR_INSTRUCTION_Msk          XSPI_IR_INSTRUCTION_Msk                          /*!< 0xFFFFFFFF */
19018 #define HSPI_IR_INSTRUCTION              XSPI_IR_INSTRUCTION                              /*!< Instruction */
19019 
19020 /************* Bit definition for HSPI_ABR register  *************************/
19021 #define HSPI_ABR_ALTERNATE_Pos           XSPI_ABR_ALTERNATE_Pos
19022 #define HSPI_ABR_ALTERNATE_Msk           XSPI_ABR_ALTERNATE_Msk                           /*!< 0xFFFFFFFF */
19023 #define HSPI_ABR_ALTERNATE               XSPI_ABR_ALTERNATE                               /*!< Alternate Bytes */
19024 
19025 /************* Bit definition for HSPI_LPTR register  ************************/
19026 #define HSPI_LPTR_TIMEOUT_Pos            XSPI_LPTR_TIMEOUT_Pos
19027 #define HSPI_LPTR_TIMEOUT_Msk            XSPI_LPTR_TIMEOUT_Msk                            /*!< 0x0000FFFF */
19028 #define HSPI_LPTR_TIMEOUT                XSPI_LPTR_TIMEOUT                                /*!< Timeout period */
19029 
19030 /************ Bit definition for HSPI_WPCCR register  ************************/
19031 #define HSPI_WPCCR_IMODE_Pos             XSPI_WPCCR_IMODE_Pos
19032 #define HSPI_WPCCR_IMODE_Msk             XSPI_WPCCR_IMODE_Msk                             /*!< 0x00000007 */
19033 #define HSPI_WPCCR_IMODE                 XSPI_WPCCR_IMODE                                 /*!< Instruction Mode */
19034 #define HSPI_WPCCR_IMODE_0               XSPI_WPCCR_IMODE_0                               /*!< 0x00000001 */
19035 #define HSPI_WPCCR_IMODE_1               XSPI_WPCCR_IMODE_1                               /*!< 0x00000002 */
19036 #define HSPI_WPCCR_IMODE_2               XSPI_WPCCR_IMODE_2                               /*!< 0x00000004 */
19037 #define HSPI_WPCCR_IDTR_Pos              XSPI_WPCCR_IDTR_Pos
19038 #define HSPI_WPCCR_IDTR_Msk              XSPI_WPCCR_IDTR_Msk                              /*!< 0x00000008 */
19039 #define HSPI_WPCCR_IDTR                  XSPI_WPCCR_IDTR                                  /*!< Instruction Double Transfer Rate */
19040 #define HSPI_WPCCR_ISIZE_Pos             XSPI_WPCCR_ISIZE_Pos
19041 #define HSPI_WPCCR_ISIZE_Msk             XSPI_WPCCR_ISIZE_Msk                             /*!< 0x00000030 */
19042 #define HSPI_WPCCR_ISIZE                 XSPI_WPCCR_ISIZE                                 /*!< Instruction Size */
19043 #define HSPI_WPCCR_ISIZE_0               XSPI_WPCCR_ISIZE_0                               /*!< 0x00000010 */
19044 #define HSPI_WPCCR_ISIZE_1               XSPI_WPCCR_ISIZE_1                               /*!< 0x00000020 */
19045 #define HSPI_WPCCR_ADMODE_Pos            XSPI_WPCCR_ADMODE_Pos
19046 #define HSPI_WPCCR_ADMODE_Msk            XSPI_WPCCR_ADMODE_Msk                            /*!< 0x00000700 */
19047 #define HSPI_WPCCR_ADMODE                XSPI_WPCCR_ADMODE                                /*!< Address Mode */
19048 #define HSPI_WPCCR_ADMODE_0              XSPI_WPCCR_ADMODE_0                              /*!< 0x00000100 */
19049 #define HSPI_WPCCR_ADMODE_1              XSPI_WPCCR_ADMODE_1                              /*!< 0x00000200 */
19050 #define HSPI_WPCCR_ADMODE_2              XSPI_WPCCR_ADMODE_2                              /*!< 0x00000400 */
19051 #define HSPI_WPCCR_ADDTR_Pos             XSPI_WPCCR_ADDTR_Pos
19052 #define HSPI_WPCCR_ADDTR_Msk             XSPI_WPCCR_ADDTR_Msk                             /*!< 0x00000800 */
19053 #define HSPI_WPCCR_ADDTR                 XSPI_WPCCR_ADDTR                                 /*!< Address Double Transfer Rate */
19054 #define HSPI_WPCCR_ADSIZE_Pos            XSPI_WPCCR_ADSIZE_Pos
19055 #define HSPI_WPCCR_ADSIZE_Msk            XSPI_WPCCR_ADSIZE_Msk                            /*!< 0x00003000 */
19056 #define HSPI_WPCCR_ADSIZE                XSPI_WPCCR_ADSIZE                                /*!< Address Size */
19057 #define HSPI_WPCCR_ADSIZE_0              XSPI_WPCCR_ADSIZE_0                              /*!< 0x00001000 */
19058 #define HSPI_WPCCR_ADSIZE_1              XSPI_WPCCR_ADSIZE_1                              /*!< 0x00002000 */
19059 #define HSPI_WPCCR_ABMODE_Pos            XSPI_WPCCR_ABMODE_Pos
19060 #define HSPI_WPCCR_ABMODE_Msk            XSPI_WPCCR_ABMODE_Msk                            /*!< 0x00070000 */
19061 #define HSPI_WPCCR_ABMODE                XSPI_WPCCR_ABMODE                                /*!< Alternate Bytes Mode */
19062 #define HSPI_WPCCR_ABMODE_0              XSPI_WPCCR_ABMODE_0                              /*!< 0x00010000 */
19063 #define HSPI_WPCCR_ABMODE_1              XSPI_WPCCR_ABMODE_1                              /*!< 0x00020000 */
19064 #define HSPI_WPCCR_ABMODE_2              XSPI_WPCCR_ABMODE_2                              /*!< 0x00040000 */
19065 #define HSPI_WPCCR_ABDTR_Pos             XSPI_WPCCR_ABDTR_Pos
19066 #define HSPI_WPCCR_ABDTR_Msk             XSPI_WPCCR_ABDTR_Msk                             /*!< 0x00080000 */
19067 #define HSPI_WPCCR_ABDTR                 XSPI_WPCCR_ABDTR                                 /*!< Alternate Bytes Double Transfer Rate */
19068 #define HSPI_WPCCR_ABSIZE_Pos            XSPI_WPCCR_ABSIZE_Pos
19069 #define HSPI_WPCCR_ABSIZE_Msk            XSPI_WPCCR_ABSIZE_Msk                            /*!< 0x00300000 */
19070 #define HSPI_WPCCR_ABSIZE                XSPI_WPCCR_ABSIZE                                /*!< Alternate Bytes Size */
19071 #define HSPI_WPCCR_ABSIZE_0              XSPI_WPCCR_ABSIZE_0                              /*!< 0x00100000 */
19072 #define HSPI_WPCCR_ABSIZE_1              XSPI_WPCCR_ABSIZE_1                              /*!< 0x00200000 */
19073 #define HSPI_WPCCR_DMODE_Pos             XSPI_WPCCR_DMODE_Pos
19074 #define HSPI_WPCCR_DMODE_Msk             XSPI_WPCCR_DMODE_Msk                             /*!< 0x07000000 */
19075 #define HSPI_WPCCR_DMODE                 XSPI_WPCCR_DMODE                                 /*!< Data Mode */
19076 #define HSPI_WPCCR_DMODE_0               XSPI_WPCCR_DMODE_0                               /*!< 0x01000000 */
19077 #define HSPI_WPCCR_DMODE_1               XSPI_WPCCR_DMODE_1                               /*!< 0x02000000 */
19078 #define HSPI_WPCCR_DMODE_2               XSPI_WPCCR_DMODE_2                               /*!< 0x04000000 */
19079 #define HSPI_WPCCR_DDTR_Pos              XSPI_WPCCR_DDTR_Pos
19080 #define HSPI_WPCCR_DDTR_Msk              XSPI_WPCCR_DDTR_Msk                              /*!< 0x08000000 */
19081 #define HSPI_WPCCR_DDTR                  XSPI_WPCCR_DDTR                                  /*!< Data Double Transfer Rate */
19082 #define HSPI_WPCCR_DQSE_Pos              XSPI_WPCCR_DQSE_Pos
19083 #define HSPI_WPCCR_DQSE_Msk              XSPI_WPCCR_DQSE_Msk                              /*!< 0x20000000 */
19084 #define HSPI_WPCCR_DQSE                  XSPI_WPCCR_DQSE                                  /*!< DQS Enable */
19085 
19086 /************ Bit definition for HSPI_WPTCR register  ************************/
19087 #define HSPI_WPTCR_DCYC_Pos              XSPI_WPTCR_DCYC_Pos
19088 #define HSPI_WPTCR_DCYC_Msk              XSPI_WPTCR_DCYC_Msk                              /*!< 0x0000001F */
19089 #define HSPI_WPTCR_DCYC                  XSPI_WPTCR_DCYC                                  /*!< Number of Dummy Cycles */
19090 #define HSPI_WPTCR_DHQC_Pos              XSPI_WPTCR_DHQC_Pos
19091 #define HSPI_WPTCR_DHQC_Msk              XSPI_WPTCR_DHQC_Msk                              /*!< 0x10000000 */
19092 #define HSPI_WPTCR_DHQC                  XSPI_WPTCR_DHQC                                  /*!< Delay Hold Quarter Cycle */
19093 #define HSPI_WPTCR_SSHIFT_Pos            XSPI_WPTCR_SSHIFT_Pos
19094 #define HSPI_WPTCR_SSHIFT_Msk            XSPI_WPTCR_SSHIFT_Msk                            /*!< 0x40000000 */
19095 #define HSPI_WPTCR_SSHIFT                XSPI_WPTCR_SSHIFT                                /*!< Sample Shift */
19096 
19097 /************* Bit definition for HSPI_WPIR register  *************************/
19098 #define HSPI_WPIR_INSTRUCTION_Pos        XSPI_WPIR_INSTRUCTION_Pos
19099 #define HSPI_WPIR_INSTRUCTION_Msk        XSPI_WPIR_INSTRUCTION_Msk                        /*!< 0xFFFFFFFF */
19100 #define HSPI_WPIR_INSTRUCTION            XSPI_WPIR_INSTRUCTION                            /*!< Instruction */
19101 
19102 /************* Bit definition for HSPI_WPABR register  *************************/
19103 #define HSPI_WPABR_ALTERNATE_Pos         XSPI_WPABR_ALTERNATE_Pos
19104 #define HSPI_WPABR_ALTERNATE_Msk         XSPI_WPABR_ALTERNATE_Msk                         /*!< 0xFFFFFFFF */
19105 #define HSPI_WPABR_ALTERNATE             XSPI_WPABR_ALTERNATE                             /*!< Alternate Bytes */
19106 
19107 /************* Bit definition for HSPI_WCCR register  **************************/
19108 #define HSPI_WCCR_IMODE_Pos              XSPI_WCCR_IMODE_Pos
19109 #define HSPI_WCCR_IMODE_Msk              XSPI_WCCR_IMODE_Msk                              /*!< 0x00000007 */
19110 #define HSPI_WCCR_IMODE                  XSPI_WCCR_IMODE                                  /*!< Instruction Mode */
19111 #define HSPI_WCCR_IMODE_0                XSPI_WCCR_IMODE_0                                /*!< 0x00000001 */
19112 #define HSPI_WCCR_IMODE_1                XSPI_WCCR_IMODE_1                                /*!< 0x00000002 */
19113 #define HSPI_WCCR_IMODE_2                XSPI_WCCR_IMODE_2                                /*!< 0x00000004 */
19114 #define HSPI_WCCR_IDTR_Pos               XSPI_WCCR_IDTR_Pos
19115 #define HSPI_WCCR_IDTR_Msk               XSPI_WCCR_IDTR_Msk                               /*!< 0x00000008 */
19116 #define HSPI_WCCR_IDTR                   XSPI_WCCR_IDTR                                   /*!< Instruction Double Transfer Rate */
19117 #define HSPI_WCCR_ISIZE_Pos              XSPI_WCCR_ISIZE_Pos
19118 #define HSPI_WCCR_ISIZE_Msk              XSPI_WCCR_ISIZE_Msk                              /*!< 0x00000030 */
19119 #define HSPI_WCCR_ISIZE                  XSPI_WCCR_ISIZE                                  /*!< Instruction Size */
19120 #define HSPI_WCCR_ISIZE_0                XSPI_WCCR_ISIZE_0                                /*!< 0x00000010 */
19121 #define HSPI_WCCR_ISIZE_1                XSPI_WCCR_ISIZE_1                                /*!< 0x00000020 */
19122 #define HSPI_WCCR_ADMODE_Pos             XSPI_WCCR_ADMODE_Pos
19123 #define HSPI_WCCR_ADMODE_Msk             XSPI_WCCR_ADMODE_Msk                             /*!< 0x00000700 */
19124 #define HSPI_WCCR_ADMODE                 XSPI_WCCR_ADMODE                                 /*!< Address Mode */
19125 #define HSPI_WCCR_ADMODE_0               XSPI_WCCR_ADMODE_0                               /*!< 0x00000100 */
19126 #define HSPI_WCCR_ADMODE_1               XSPI_WCCR_ADMODE_1                               /*!< 0x00000200 */
19127 #define HSPI_WCCR_ADMODE_2               XSPI_WCCR_ADMODE_2                               /*!< 0x00000400 */
19128 #define HSPI_WCCR_ADDTR_Pos              XSPI_WCCR_ADDTR_Pos
19129 #define HSPI_WCCR_ADDTR_Msk              XSPI_WCCR_ADDTR_Msk                              /*!< 0x00000800 */
19130 #define HSPI_WCCR_ADDTR                  XSPI_WCCR_ADDTR                                  /*!< Address Double Transfer Rate */
19131 #define HSPI_WCCR_ADSIZE_Pos             XSPI_WCCR_ADSIZE_Pos
19132 #define HSPI_WCCR_ADSIZE_Msk             XSPI_WCCR_ADSIZE_Msk                             /*!< 0x00003000 */
19133 #define HSPI_WCCR_ADSIZE                 XSPI_WCCR_ADSIZE                                 /*!< Address Size */
19134 #define HSPI_WCCR_ADSIZE_0               XSPI_WCCR_ADSIZE_0                               /*!< 0x00001000 */
19135 #define HSPI_WCCR_ADSIZE_1               XSPI_WCCR_ADSIZE_1                               /*!< 0x00002000 */
19136 #define HSPI_WCCR_ABMODE_Pos             XSPI_WCCR_ABMODE_Pos
19137 #define HSPI_WCCR_ABMODE_Msk             XSPI_WCCR_ABMODE_Msk                             /*!< 0x00070000 */
19138 #define HSPI_WCCR_ABMODE                 XSPI_WCCR_ABMODE                                 /*!< Alternate Bytes Mode */
19139 #define HSPI_WCCR_ABMODE_0               XSPI_WCCR_ABMODE_0                               /*!< 0x00010000 */
19140 #define HSPI_WCCR_ABMODE_1               XSPI_WCCR_ABMODE_1                               /*!< 0x00020000 */
19141 #define HSPI_WCCR_ABMODE_2               XSPI_WCCR_ABMODE_2                               /*!< 0x00040000 */
19142 #define HSPI_WCCR_ABDTR_Pos              XSPI_WCCR_ABDTR_Pos
19143 #define HSPI_WCCR_ABDTR_Msk              XSPI_WCCR_ABDTR_Msk                              /*!< 0x00080000 */
19144 #define HSPI_WCCR_ABDTR                  XSPI_WCCR_ABDTR                                  /*!< Alternate Bytes Double Transfer Rate */
19145 #define HSPI_WCCR_ABSIZE_Pos             XSPI_WCCR_ABSIZE_Pos
19146 #define HSPI_WCCR_ABSIZE_Msk             XSPI_WCCR_ABSIZE_Msk                             /*!< 0x00300000 */
19147 #define HSPI_WCCR_ABSIZE                 XSPI_WCCR_ABSIZE                                 /*!< Alternate Bytes Size */
19148 #define HSPI_WCCR_ABSIZE_0               XSPI_WCCR_ABSIZE_0                               /*!< 0x00100000 */
19149 #define HSPI_WCCR_ABSIZE_1               XSPI_WCCR_ABSIZE_1                               /*!< 0x00200000 */
19150 #define HSPI_WCCR_DMODE_Pos              XSPI_WCCR_DMODE_Pos
19151 #define HSPI_WCCR_DMODE_Msk              XSPI_WCCR_DMODE_Msk                              /*!< 0x07000000 */
19152 #define HSPI_WCCR_DMODE                  XSPI_WCCR_DMODE                                  /*!< Data Mode */
19153 #define HSPI_WCCR_DMODE_0                XSPI_WCCR_DMODE_0                                /*!< 0x01000000 */
19154 #define HSPI_WCCR_DMODE_1                XSPI_WCCR_DMODE_1                                /*!< 0x02000000 */
19155 #define HSPI_WCCR_DMODE_2                XSPI_WCCR_DMODE_2                                /*!< 0x04000000 */
19156 #define HSPI_WCCR_DDTR_Pos               XSPI_WCCR_DDTR_Pos
19157 #define HSPI_WCCR_DDTR_Msk               XSPI_WCCR_DDTR_Msk                               /*!< 0x08000000 */
19158 #define HSPI_WCCR_DDTR                   XSPI_WCCR_DDTR                                   /*!< Data Double Transfer Rate */
19159 #define HSPI_WCCR_DQSE_Pos               XSPI_WCCR_DQSE_Pos
19160 #define HSPI_WCCR_DQSE_Msk               XSPI_WCCR_DQSE_Msk                               /*!< 0x20000000 */
19161 #define HSPI_WCCR_DQSE                   XSPI_WCCR_DQSE                                   /*!< DQS Enable */
19162 
19163 /************* Bit definition for HSPI_WTCR register  *************************/
19164 #define HSPI_WTCR_DCYC_Pos               XSPI_WTCR_DCYC_Pos
19165 #define HSPI_WTCR_DCYC_Msk               XSPI_WTCR_DCYC_Msk                               /*!< 0x0000001F */
19166 #define HSPI_WTCR_DCYC                   XSPI_WTCR_DCYC                                   /*!< Number of Dummy Cycles */
19167 
19168 /************* Bit definition for HSPI_WIR register  **************************/
19169 #define HSPI_WIR_INSTRUCTION_Pos         XSPI_WIR_INSTRUCTION_Pos
19170 #define HSPI_WIR_INSTRUCTION_Msk         XSPI_WIR_INSTRUCTION_Msk                         /*!< 0xFFFFFFFF */
19171 #define HSPI_WIR_INSTRUCTION             XSPI_WIR_INSTRUCTION                             /*!< Instruction */
19172 
19173 /************* Bit definition for HSPI_WABR register  *************************/
19174 #define HSPI_WABR_ALTERNATE_Pos          XSPI_WABR_ALTERNATE_Pos
19175 #define HSPI_WABR_ALTERNATE_Msk          XSPI_WABR_ALTERNATE_Msk                          /*!< 0xFFFFFFFF */
19176 #define HSPI_WABR_ALTERNATE              XSPI_WABR_ALTERNATE                              /*!< Alternate Bytes */
19177 
19178 /************* Bit definition for HSPI_HLCR register  *************************/
19179 #define HSPI_HLCR_LM_Pos                 XSPI_HLCR_LM_Pos
19180 #define HSPI_HLCR_LM_Msk                 XSPI_HLCR_LM_Msk                                 /*!< 0x00000001 */
19181 #define HSPI_HLCR_LM                     XSPI_HLCR_LM                                     /*!< Latency Mode */
19182 #define HSPI_HLCR_WZL_Pos                XSPI_HLCR_WZL_Pos
19183 #define HSPI_HLCR_WZL_Msk                XSPI_HLCR_WZL_Msk                                /*!< 0x00000002 */
19184 #define HSPI_HLCR_WZL                    XSPI_HLCR_WZL                                    /*!< Write Zero Latency */
19185 #define HSPI_HLCR_TACC_Pos               XSPI_HLCR_TACC_Pos
19186 #define HSPI_HLCR_TACC_Msk               XSPI_HLCR_TACC_Msk                               /*!< 0x0000FF00 */
19187 #define HSPI_HLCR_TACC                   XSPI_HLCR_TACC                                   /*!< Access Time */
19188 #define HSPI_HLCR_TRWR_Pos               XSPI_HLCR_TRWR_Pos
19189 #define HSPI_HLCR_TRWR_Msk               XSPI_HLCR_TRWR_Msk                               /*!< 0x00FF0000 */
19190 #define HSPI_HLCR_TRWR                   XSPI_HLCR_TRWR                                   /*!< Read Write Recovery Time */
19191 
19192 /************* Bit definition for HSPI_CALFCR register  ***********************/
19193 #define HSPI_CALFCR_FINE_Pos             XSPI_HSPI_CALFCR_FINE_Pos
19194 #define HSPI_CALFCR_FINE_Msk             XSPI_HSPI_CALFCR_FINE_Msk                        /*!< 0x0000007F */
19195 #define HSPI_CALFCR_FINE                 XSPI_HSPI_CALFCR_FINE                            /*!< Fine Calibration */
19196 #define HSPI_CALFCR_COARSE_Pos           XSPI_HSPI_CALFCR_COARSE_Pos
19197 #define HSPI_CALFCR_COARSE_Msk           XSPI_HSPI_CALFCR_COARSE_Msk                      /*!< 0x001F0000 */
19198 #define HSPI_CALFCR_COARSE               XSPI_HSPI_CALFCR_COARSE                          /*!< Coarse Calibration */
19199 #define HSPI_CALFCR_CALMAX_Pos           XSPI_HSPI_CALFCR_CALMAX_Pos
19200 #define HSPI_CALFCR_CALMAX_Msk           XSPI_HSPI_CALFCR_CALMAX_Msk                      /*!< 0x80000000 */
19201 #define HSPI_CALFCR_CALMAX               XSPI_HSPI_CALFCR_CALMAX                          /*!< Max Value */
19202 
19203 /************* Bit definition for HSPI_CALMR register  ***********************/
19204 #define HSPI_CALMR_FINE_Pos              XSPI_HSPI_CALMR_FINE_Pos
19205 #define HSPI_CALMR_FINE_Msk              XSPI_HSPI_CALMR_FINE_Msk                         /*!< 0x0000007F */
19206 #define HSPI_CALMR_FINE                  XSPI_HSPI_CALMR_FINE                             /*!< Fine Calibration */
19207 #define HSPI_CALMR_COARSE_Pos            XSPI_HSPI_CALMR_COARSE_Pos
19208 #define HSPI_CALMR_COARSE_Msk            XSPI_HSPI_CALMR_COARSE_Msk                       /*!< 0x001F0000 */
19209 #define HSPI_CALMR_COARSE                XSPI_HSPI_CALMR_COARSE                           /*!< Coarse Calibration */
19210 
19211 /************* Bit definition for HSPI_CALSOR register  ***********************/
19212 #define HSPI_CALSOR_FINE_Pos             XSPI_HSPI_CALSOR_FINE_Pos
19213 #define HSPI_CALSOR_FINE_Msk             XSPI_HSPI_CALSOR_FINE_Msk                        /*!< 0x0000007F */
19214 #define HSPI_CALSOR_FINE                 XSPI_HSPI_CALSOR_FINE                            /*!< Fine Calibration */
19215 #define HSPI_CALSOR_COARSE_Pos           XSPI_HSPI_CALSOR_COARSE_Pos
19216 #define HSPI_CALSOR_COARSE_Msk           XSPI_HSPI_CALSOR_COARSE_Msk                      /*!< 0x001F0000 */
19217 #define HSPI_CALSOR_COARSE               XSPI_HSPI_CALSOR_COARSE                          /*!< Coarse Calibration */
19218 
19219 /************* Bit definition for HSPI_CALSIR register  ***********************/
19220 #define HSPI_CALSIR_FINE_Pos             XSPI_HSPI_CALSIR_FINE_Pos
19221 #define HSPI_CALSIR_FINE_Msk             XSPI_HSPI_CALSIR_FINE_Msk                        /*!< 0x0000007F */
19222 #define HSPI_CALSIR_FINE                 XSPI_HSPI_CALSIR_FINE                            /*!< Fine Calibration */
19223 #define HSPI_CALSIR_COARSE_Pos           XSPI_HSPI_CALSIR_COARSE_Pos
19224 #define HSPI_CALSIR_COARSE_Msk           XSPI_HSPI_CALSIR_COARSE_Msk                      /*!< 0x001F0000 */
19225 #define HSPI_CALSIR_COARSE               XSPI_HSPI_CALSIR_COARSE                          /*!< Coarse Calibration */
19226 
19227 /******************************************************************************/
19228 /*                                                                            */
19229 /*                                  XSPIM (OCTOSPIM)                                  */
19230 /*                                                                            */
19231 /******************************************************************************/
19232 /***************  Bit definition for XSPIM_CR register  ********************/
19233 #define XSPIM_CR_MUXEN_Pos               (0U)
19234 #define XSPIM_CR_MUXEN_Msk               (0x1UL << XSPIM_CR_MUXEN_Pos)                    /*!< 0x00000001 */
19235 #define XSPIM_CR_MUXEN                   XSPIM_CR_MUXEN_Msk                               /*!< Multiplexed Mode Enable */
19236 #define XSPIM_CR_REQ2ACK_TIME_Pos        (16U)
19237 #define XSPIM_CR_REQ2ACK_TIME_Msk        (0xFFUL << XSPIM_CR_REQ2ACK_TIME_Pos)            /*!< 0x00FF0000 */
19238 #define XSPIM_CR_REQ2ACK_TIME            XSPIM_CR_REQ2ACK_TIME_Msk                        /*!< REQ to ACK Time */
19239 
19240 /***************  Bit definition for XSPIM_PCR register  *****************/
19241 #define XSPIM_PCR_CLKEN_Pos              (0U)
19242 #define XSPIM_PCR_CLKEN_Msk              (0x1UL << XSPIM_PCR_CLKEN_Pos)                   /*!< 0x00000001 */
19243 #define XSPIM_PCR_CLKEN                  XSPIM_PCR_CLKEN_Msk                              /*!< CLK/CLKn Enable for Port n */
19244 #define XSPIM_PCR_CLKSRC_Pos             (1U)
19245 #define XSPIM_PCR_CLKSRC_Msk             (0x1UL << XSPIM_PCR_CLKSRC_Pos)                  /*!< 0x00000002 */
19246 #define XSPIM_PCR_CLKSRC                 XSPIM_PCR_CLKSRC_Msk                             /*!< CLK/CLKn Source for Port n*/
19247 #define XSPIM_PCR_DQSEN_Pos              (4U)
19248 #define XSPIM_PCR_DQSEN_Msk              (0x1UL << XSPIM_PCR_DQSEN_Pos)                   /*!< 0x00000010 */
19249 #define XSPIM_PCR_DQSEN                  XSPIM_PCR_DQSEN_Msk                              /*!< DQS Enable for Port n */
19250 #define XSPIM_PCR_DQSSRC_Pos             (5U)
19251 #define XSPIM_PCR_DQSSRC_Msk             (0x1UL << XSPIM_PCR_DQSSRC_Pos)                  /*!< 0x00000020 */
19252 #define XSPIM_PCR_DQSSRC                 XSPIM_PCR_DQSSRC_Msk                             /*!< DQS Source for Port n */
19253 #define XSPIM_PCR_NCSEN_Pos              (8U)
19254 #define XSPIM_PCR_NCSEN_Msk              (0x1UL << XSPIM_PCR_NCSEN_Pos)                   /*!< 0x00000100U */
19255 #define XSPIM_PCR_NCSEN                  XSPIM_PCR_NCSEN_Msk                              /*!< nCS Enable for Port n*/
19256 #define XSPIM_PCR_NCSSRC_Pos             (9U)
19257 #define XSPIM_PCR_NCSSRC_Msk             (0x1UL << XSPIM_PCR_NCSSRC_Pos)                  /*!< 0x00000200U */
19258 #define XSPIM_PCR_NCSSRC                 XSPIM_PCR_NCSSRC_Msk                             /*!< nCS Source for Port n */
19259 #define XSPIM_PCR_IOLEN_Pos              (16U)
19260 #define XSPIM_PCR_IOLEN_Msk              (0x1UL << XSPIM_PCR_IOLEN_Pos)                   /*!< 0x00010000U */
19261 #define XSPIM_PCR_IOLEN                  XSPIM_PCR_IOLEN_Msk                              /*!< IO[3:0] Enable for Port n */
19262 #define XSPIM_PCR_IOLSRC_Pos             (17U)
19263 #define XSPIM_PCR_IOLSRC_Msk             (0x3UL << XSPIM_PCR_IOLSRC_Pos)                  /*!< 0x00060000U */
19264 #define XSPIM_PCR_IOLSRC                 XSPIM_PCR_IOLSRC_Msk                             /*!< IO[3:0] Source for Port n */
19265 #define XSPIM_PCR_IOLSRC_0               (0x1UL << XSPIM_PCR_IOLSRC_Pos)                  /*!< 0x00020000 */
19266 #define XSPIM_PCR_IOLSRC_1               (0x2UL << XSPIM_PCR_IOLSRC_Pos)                  /*!< 0x00040000 */
19267 #define XSPIM_PCR_IOHEN_Pos              (24U)
19268 #define XSPIM_PCR_IOHEN_Msk              (0x1UL << XSPIM_PCR_IOHEN_Pos)                   /*!< 0x01000000U */
19269 #define XSPIM_PCR_IOHEN                  XSPIM_PCR_IOHEN_Msk                              /*!< IO[7:4] Enable for Port n */
19270 #define XSPIM_PCR_IOHSRC_Pos             (25U)
19271 #define XSPIM_PCR_IOHSRC_Msk             (0x3UL << XSPIM_PCR_IOHSRC_Pos)                  /*!< 0x06000000U */
19272 #define XSPIM_PCR_IOHSRC                 XSPIM_PCR_IOHSRC_Msk                             /*!< IO[7:4] Source for Port n */
19273 #define XSPIM_PCR_IOHSRC_0               (0x1UL << XSPIM_PCR_IOHSRC_Pos)                  /*!< 0x02000000U */
19274 #define XSPIM_PCR_IOHSRC_1               (0x2UL << XSPIM_PCR_IOHSRC_Pos)                  /*!< 0x04000000U */
19275 
19276 /******************************************************************************/
19277 /*                                                                            */
19278 /*                                  OCTOSPIM                                  */
19279 /*                                                                            */
19280 /******************************************************************************/
19281 /***************  Bit definition for OCTOSPIM_CR register  ********************/
19282 #define OCTOSPIM_CR_MUXEN_Pos               XSPIM_CR_MUXEN_Pos
19283 #define OCTOSPIM_CR_MUXEN_Msk               XSPIM_CR_MUXEN_Msk                            /*!< 0x00000001 */
19284 #define OCTOSPIM_CR_MUXEN                   XSPIM_CR_MUXEN                                /*!< Multiplexed Mode Enable */
19285 #define OCTOSPIM_CR_REQ2ACK_TIME_Pos        XSPIM_CR_REQ2ACK_TIME_Pos
19286 #define OCTOSPIM_CR_REQ2ACK_TIME_Msk        XSPIM_CR_REQ2ACK_TIME_Msk                     /*!< 0x00FF0000 */
19287 #define OCTOSPIM_CR_REQ2ACK_TIME            XSPIM_CR_REQ2ACK_TIME                         /*!< REQ to ACK Time */
19288 
19289 /***************  Bit definition for OCTOSPIM_PCR register  *****************/
19290 #define OCTOSPIM_PCR_CLKEN_Pos              XSPIM_PCR_CLKEN_Pos
19291 #define OCTOSPIM_PCR_CLKEN_Msk              XSPIM_PCR_CLKEN_Msk                           /*!< 0x00000001 */
19292 #define OCTOSPIM_PCR_CLKEN                  XSPIM_PCR_CLKEN                               /*!< CLK/CLKn Enable for Port n */
19293 #define OCTOSPIM_PCR_CLKSRC_Pos             XSPIM_PCR_CLKSRC_Pos
19294 #define OCTOSPIM_PCR_CLKSRC_Msk             XSPIM_PCR_CLKSRC_Msk                          /*!< 0x00000002 */
19295 #define OCTOSPIM_PCR_CLKSRC                 XSPIM_PCR_CLKSRC                              /*!< CLK/CLKn Source for Port n*/
19296 #define OCTOSPIM_PCR_DQSEN_Pos              XSPIM_PCR_DQSEN_Pos
19297 #define OCTOSPIM_PCR_DQSEN_Msk              XSPIM_PCR_DQSEN_Msk                           /*!< 0x00000010 */
19298 #define OCTOSPIM_PCR_DQSEN                  XSPIM_PCR_DQSEN                               /*!< DQS Enable for Port n */
19299 #define OCTOSPIM_PCR_DQSSRC_Pos             XSPIM_PCR_DQSSRC_Pos
19300 #define OCTOSPIM_PCR_DQSSRC_Msk             XSPIM_PCR_DQSSRC_Msk                          /*!< 0x00000020 */
19301 #define OCTOSPIM_PCR_DQSSRC                 XSPIM_PCR_DQSSRC                              /*!< DQS Source for Port n */
19302 #define OCTOSPIM_PCR_NCSEN_Pos              XSPIM_PCR_NCSEN_Pos
19303 #define OCTOSPIM_PCR_NCSEN_Msk              XSPIM_PCR_NCSEN_Msk                           /*!< 0x00000100U */
19304 #define OCTOSPIM_PCR_NCSEN                  XSPIM_PCR_NCSEN                               /*!< nCS Enable for Port n*/
19305 #define OCTOSPIM_PCR_NCSSRC_Pos             XSPIM_PCR_NCSSRC_Pos
19306 #define OCTOSPIM_PCR_NCSSRC_Msk             XSPIM_PCR_NCSSRC_Msk                          /*!< 0x00000200U */
19307 #define OCTOSPIM_PCR_NCSSRC                 XSPIM_PCR_NCSSRC                              /*!< nCS Source for Port n */
19308 #define OCTOSPIM_PCR_IOLEN_Pos              XSPIM_PCR_IOLEN_Pos
19309 #define OCTOSPIM_PCR_IOLEN_Msk              XSPIM_PCR_IOLEN_Msk                           /*!< 0x00010000U */
19310 #define OCTOSPIM_PCR_IOLEN                  XSPIM_PCR_IOLEN                               /*!< IO[3:0] Enable for Port n */
19311 #define OCTOSPIM_PCR_IOLSRC_Pos             XSPIM_PCR_IOLSRC_Pos
19312 #define OCTOSPIM_PCR_IOLSRC_Msk             XSPIM_PCR_IOLSRC_Msk                          /*!< 0x00060000U */
19313 #define OCTOSPIM_PCR_IOLSRC                 XSPIM_PCR_IOLSRC                              /*!< IO[3:0] Source for Port n */
19314 #define OCTOSPIM_PCR_IOLSRC_0               XSPIM_PCR_IOLSRC_0                            /*!< 0x00020000 */
19315 #define OCTOSPIM_PCR_IOLSRC_1               XSPIM_PCR_IOLSRC_1                            /*!< 0x00040000 */
19316 #define OCTOSPIM_PCR_IOHEN_Pos              XSPIM_PCR_IOHEN_Pos
19317 #define OCTOSPIM_PCR_IOHEN_Msk              XSPIM_PCR_IOHEN_Msk                           /*!< 0x01000000U */
19318 #define OCTOSPIM_PCR_IOHEN                  XSPIM_PCR_IOHEN                               /*!< IO[7:4] Enable for Port n */
19319 #define OCTOSPIM_PCR_IOHSRC_Pos             XSPIM_PCR_IOHSRC_Pos
19320 #define OCTOSPIM_PCR_IOHSRC_Msk             XSPIM_PCR_IOHSRC_Msk                          /*!< 0x06000000U */
19321 #define OCTOSPIM_PCR_IOHSRC                 XSPIM_PCR_IOHSRC                              /*!< IO[7:4] Source for Port n */
19322 #define OCTOSPIM_PCR_IOHSRC_0               XSPIM_PCR_IOHSRC_0                            /*!< 0x02000000U */
19323 #define OCTOSPIM_PCR_IOHSRC_1               XSPIM_PCR_IOHSRC_1                            /*!< 0x04000000U */
19324 
19325 /******************************************************************************/
19326 /*                                                                            */
19327 /*                        Delay Block Interface (DLYB)                        */
19328 /*                                                                            */
19329 /******************************************************************************/
19330 /*******************  Bit definition for DLYB_CR register  ********************/
19331 #define DLYB_CR_DEN_Pos                     (0U)
19332 #define DLYB_CR_DEN_Msk                     (0x1UL << DLYB_CR_DEN_Pos)              /*!< 0x00000001 */
19333 #define DLYB_CR_DEN                         DLYB_CR_DEN_Msk                         /*!<Delay Block enable */
19334 #define DLYB_CR_SEN_Pos                     (1U)
19335 #define DLYB_CR_SEN_Msk                     (0x1UL << DLYB_CR_SEN_Pos)              /*!< 0x00000002 */
19336 #define DLYB_CR_SEN                         DLYB_CR_SEN_Msk                         /*!<Sampler length enable */
19337 
19338 /*******************  Bit definition for DLYB_CFGR register  ********************/
19339 #define DLYB_CFGR_SEL_Pos                   (0U)
19340 #define DLYB_CFGR_SEL_Msk                   (0xFUL << DLYB_CFGR_SEL_Pos)            /*!< 0x0000000F */
19341 #define DLYB_CFGR_SEL                       DLYB_CFGR_SEL_Msk                       /*!<Select the phase for the Output clock[3:0] */
19342 #define DLYB_CFGR_SEL_0                     (0x1UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000001 */
19343 #define DLYB_CFGR_SEL_1                     (0x2UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000002 */
19344 #define DLYB_CFGR_SEL_2                     (0x3UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000003 */
19345 #define DLYB_CFGR_SEL_3                     (0x8UL << DLYB_CFGR_SEL_Pos)            /*!< 0x00000008 */
19346 
19347 #define DLYB_CFGR_UNIT_Pos                  (8U)
19348 #define DLYB_CFGR_UNIT_Msk                  (0x7FUL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00007F00 */
19349 #define DLYB_CFGR_UNIT                      DLYB_CFGR_UNIT_Msk                      /*!<Delay Defines the delay of a Unit delay cell[6:0] */
19350 #define DLYB_CFGR_UNIT_0                    (0x01UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000100 */
19351 #define DLYB_CFGR_UNIT_1                    (0x02UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000200 */
19352 #define DLYB_CFGR_UNIT_2                    (0x04UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000400 */
19353 #define DLYB_CFGR_UNIT_3                    (0x08UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00000800 */
19354 #define DLYB_CFGR_UNIT_4                    (0x10UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00001000 */
19355 #define DLYB_CFGR_UNIT_5                    (0x20UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00002000 */
19356 #define DLYB_CFGR_UNIT_6                    (0x40UL << DLYB_CFGR_UNIT_Pos)          /*!< 0x00004000 */
19357 
19358 #define DLYB_CFGR_LNG_Pos                   (16U)
19359 #define DLYB_CFGR_LNG_Msk                   (0xFFFUL << DLYB_CFGR_LNG_Pos)          /*!< 0x0FFF0000 */
19360 #define DLYB_CFGR_LNG                       DLYB_CFGR_LNG_Msk                       /*!<Delay line length value[11:0] */
19361 #define DLYB_CFGR_LNG_0                     (0x001UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00010000 */
19362 #define DLYB_CFGR_LNG_1                     (0x002UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00020000 */
19363 #define DLYB_CFGR_LNG_2                     (0x004UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00040000 */
19364 #define DLYB_CFGR_LNG_3                     (0x008UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00080000 */
19365 #define DLYB_CFGR_LNG_4                     (0x010UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00100000 */
19366 #define DLYB_CFGR_LNG_5                     (0x020UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00200000 */
19367 #define DLYB_CFGR_LNG_6                     (0x040UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00400000 */
19368 #define DLYB_CFGR_LNG_7                     (0x080UL << DLYB_CFGR_LNG_Pos)          /*!< 0x00800000 */
19369 #define DLYB_CFGR_LNG_8                     (0x100UL << DLYB_CFGR_LNG_Pos)          /*!< 0x01000000 */
19370 #define DLYB_CFGR_LNG_9                     (0x200UL << DLYB_CFGR_LNG_Pos)          /*!< 0x02000000 */
19371 #define DLYB_CFGR_LNG_10                    (0x400UL << DLYB_CFGR_LNG_Pos)          /*!< 0x04000000 */
19372 #define DLYB_CFGR_LNG_11                    (0x800UL << DLYB_CFGR_LNG_Pos)          /*!< 0x08000000 */
19373 
19374 #define DLYB_CFGR_LNGF_Pos                  (31U)
19375 #define DLYB_CFGR_LNGF_Msk                  (0x1UL << DLYB_CFGR_LNGF_Pos)            /*!< 0x80000000 */
19376 #define DLYB_CFGR_LNGF                      DLYB_CFGR_LNGF_Msk                       /*!<Length valid flag */
19377 
19378 /******************************************************************************/
19379 /*                                                                            */
19380 /*                              On The Fly Decryption                         */
19381 /*                                                                            */
19382 /******************************************************************************/
19383 /******************  Bit definition for OTFDEC_CR register  ******************/
19384 #define OTFDEC_CR_ENC_Pos                   (0U)
19385 #define OTFDEC_CR_ENC_Msk                   (0x1UL << OTFDEC_CR_ENC_Pos)            /*!< 0x00000001 */
19386 #define OTFDEC_CR_ENC                       OTFDEC_CR_ENC_Msk                       /*!< Encryption mode bit */
19387 
19388 /******************  Bit definition for OTFDEC_PRIVCFGR register  ************/
19389 #define OTFDEC_PRIVCFGR_PRIV_Pos            (0U)
19390 #define OTFDEC_PRIVCFGR_PRIV_Msk            (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos)     /*!< 0x00000001 */
19391 #define OTFDEC_PRIVCFGR_PRIV                OTFDEC_PRIVCFGR_PRIV_Msk                /*!< Privileged access protection */
19392 
19393 /******************  Bit definition for OTFDEC_REG_CONFIGR register  *********/
19394 #define OTFDEC_REG_CONFIGR_REG_EN_Pos       (0U)
19395 #define OTFDEC_REG_CONFIGR_REG_EN_Msk       (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos) /*!< 0x00000001 */
19396 #define OTFDEC_REG_CONFIGR_REG_EN           OTFDEC_REG_CONFIGR_REG_EN_Msk           /*!< Region on-the-fly decryption enable */
19397 #define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos   (1U)
19398 #define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk   (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos) /*!< 0x00000002 */
19399 #define OTFDEC_REG_CONFIGR_CONFIGLOCK       OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk       /*!< Region config lock */
19400 #define OTFDEC_REG_CONFIGR_KEYLOCK_Pos      (2U)
19401 #define OTFDEC_REG_CONFIGR_KEYLOCK_Msk      (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos) /*!< 0x00000004 */
19402 #define OTFDEC_REG_CONFIGR_KEYLOCK          OTFDEC_REG_CONFIGR_KEYLOCK_Msk          /*!< Region key lock */
19403 #define OTFDEC_REG_CONFIGR_MODE_Pos         (4U)
19404 #define OTFDEC_REG_CONFIGR_MODE_Msk         (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos)  /*!< 0x00000030 */
19405 #define OTFDEC_REG_CONFIGR_MODE             OTFDEC_REG_CONFIGR_MODE_Msk             /*!< Region operating mode */
19406 #define OTFDEC_REG_CONFIGR_MODE_0           (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos)  /*!< 0x00000010 */
19407 #define OTFDEC_REG_CONFIGR_MODE_1           (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos)  /*!< 0x00000020 */
19408 #define OTFDEC_REG_CONFIGR_KEYCRC_Pos       (8U)
19409 #define OTFDEC_REG_CONFIGR_KEYCRC_Msk       (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos) /*!< 0x0000FF00 */
19410 #define OTFDEC_REG_CONFIGR_KEYCRC           OTFDEC_REG_CONFIGR_KEYCRC_Msk           /*!< Region key 8-bit CRC */
19411 #define OTFDEC_REG_CONFIGR_VERSION_Pos      (16U)
19412 #define OTFDEC_REG_CONFIGR_VERSION_Msk      (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos) /*!< 0xFFFF0000 */
19413 #define OTFDEC_REG_CONFIGR_VERSION          OTFDEC_REG_CONFIGR_VERSION_Msk          /*!< Region firmware version */
19414 
19415 /******************  Bit definition for OTFDEC_REG_START_ADDR register  ******/
19416 #define OTFDEC_REG_START_ADDR_Pos           (0U)
19417 #define OTFDEC_REG_START_ADDR_Msk           (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos) /*!< 0xFFFFFFFF */
19418 #define OTFDEC_REG_START_ADDR               OTFDEC_REG_START_ADDR_Msk               /*!< Region AHB start address */
19419 
19420 /******************  Bit definition for OTFDEC_REG_END_ADDR register  ********/
19421 #define OTFDEC_REG_END_ADDR_Pos             (0U)
19422 #define OTFDEC_REG_END_ADDR_Msk             (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos) /*!< 0xFFFFFFFF */
19423 #define OTFDEC_REG_END_ADDR                 OTFDEC_REG_END_ADDR_Msk                 /*!< Region AHB end address */
19424 
19425 /******************  Bit definition for OTFDEC_REG_NONCER0 register  *********/
19426 #define OTFDEC_REG_NONCER0_Pos              (0U)
19427 #define OTFDEC_REG_NONCER0_Msk              (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos) /*!< 0xFFFFFFFF */
19428 #define OTFDEC_REG_NONCER0                  OTFDEC_REG_NONCER0_Msk                  /*!< Region Nonce Register (LSB nonce[31:0]) */
19429 
19430 /******************  Bit definition for OTFDEC_REG_NONCER1 register  *********/
19431 #define OTFDEC_REG_NONCER1_Pos              (0U)
19432 #define OTFDEC_REG_NONCER1_Msk              (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos) /*!< 0xFFFFFFFF */
19433 #define OTFDEC_REG_NONCER1                  OTFDEC_REG_NONCER1_Msk                  /*!< Region Nonce Register (MSB nonce[63:32]) */
19434 
19435 /******************  Bit definition for OTFDEC_REG_KEYR0 register  ***********/
19436 #define OTFDEC_REG_KEYR0_Pos                (0U)
19437 #define OTFDEC_REG_KEYR0_Msk                (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos)  /*!< 0xFFFFFFFF */
19438 #define OTFDEC_REG_KEYR0                    OTFDEC_REG_KEYR0_Msk                    /*!< Region Key Register (LSB key[31:0]) */
19439 
19440 /******************  Bit definition for OTFDEC_REG_KEYR1 register  ***********/
19441 #define OTFDEC_REG_KEYR1_Pos                (0U)
19442 #define OTFDEC_REG_KEYR1_Msk                (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos)  /*!< 0xFFFFFFFF */
19443 #define OTFDEC_REG_KEYR1                    OTFDEC_REG_KEYR1_Msk                    /*!< Region Key Register (key[63:32]) */
19444 
19445 /******************  Bit definition for OTFDEC_REG_KEYR2 register  ***********/
19446 #define OTFDEC_REG_KEYR2_Pos                (0U)
19447 #define OTFDEC_REG_KEYR2_Msk                (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos)  /*!< 0xFFFFFFFF */
19448 #define OTFDEC_REG_KEYR2                    OTFDEC_REG_KEYR2_Msk                    /*!< Region Key Register (key[95:64]) */
19449 
19450 /******************  Bit definition for OTFDEC_REG_KEYR3 register  ***********/
19451 #define OTFDEC_REG_KEYR3_Pos                (0U)
19452 #define OTFDEC_REG_KEYR3_Msk                (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos)  /*!< 0xFFFFFFFF */
19453 #define OTFDEC_REG_KEYR3                    OTFDEC_REG_KEYR3_Msk                    /*!< Region Key Register (key[127:96]) */
19454 
19455 /******************  Bit definition for OTFDEC_ISR register  *****************/
19456 #define OTFDEC_ISR_SEIF_Pos                 (0U)
19457 #define OTFDEC_ISR_SEIF_Msk                 (0x1UL << OTFDEC_ISR_SEIF_Pos)          /*!< 0x00000001 */
19458 #define OTFDEC_ISR_SEIF                     OTFDEC_ISR_SEIF_Msk                     /*!< Security Error Interrupt Flag status bit before enable (mask) */
19459 #define OTFDEC_ISR_XONEIF_Pos               (1U)
19460 #define OTFDEC_ISR_XONEIF_Msk               (0x1UL << OTFDEC_ISR_XONEIF_Pos)        /*!< 0x00000002 */
19461 #define OTFDEC_ISR_XONEIF                   OTFDEC_ISR_XONEIF_Msk                   /*!< Execute-only Error Interrupt Flag status bit before enable (mask) */
19462 #define OTFDEC_ISR_KEIF_Pos                 (2U)
19463 #define OTFDEC_ISR_KEIF_Msk                 (0x1UL << OTFDEC_ISR_KEIF_Pos)          /*!< 0x00000004 */
19464 #define OTFDEC_ISR_KEIF                     OTFDEC_ISR_KEIF_Msk                     /*!< Key Error Interrupt Flag status bit before enable (mask) */
19465 
19466 /******************  Bit definition  for OTFDEC_ICR register  *****************/
19467 #define OTFDEC_ICR_SEIF_Pos                 (0U)
19468 #define OTFDEC_ICR_SEIF_Msk                 (0x1UL << OTFDEC_ICR_SEIF_Pos)          /*!< 0x00000001 */
19469 #define OTFDEC_ICR_SEIF                     OTFDEC_ICR_SEIF_Msk                     /*!< Security Error Interrupt Flag clear bit */
19470 #define OTFDEC_ICR_XONEIF_Pos               (1U)
19471 #define OTFDEC_ICR_XONEIF_Msk               (0x1UL << OTFDEC_ICR_XONEIF_Pos)        /*!< 0x00000002 */
19472 #define OTFDEC_ICR_XONEIF                   OTFDEC_ICR_XONEIF_Msk                   /*!< Execute-only Error Interrupt Flag clear bit */
19473 #define OTFDEC_ICR_KEIF_Pos                 (2U)
19474 #define OTFDEC_ICR_KEIF_Msk                 (0x1UL << OTFDEC_ICR_KEIF_Pos)          /*!< 0x00000004 */
19475 #define OTFDEC_ICR_KEIF                     OTFDEC_ICR_KEIF_Msk                     /*!< Key Error Interrupt Flag clear bit */
19476 
19477 /******************  Bit definition for OTFDEC_IER register  *****************/
19478 #define OTFDEC_IER_SEIE_Pos                 (0U)
19479 #define OTFDEC_IER_SEIE_Msk                 (0x1UL << OTFDEC_IER_SEIE_Pos)          /*!< 0x00000001 */
19480 #define OTFDEC_IER_SEIE                     OTFDEC_IER_SEIE_Msk                     /*!< Security Error Interrupt Enable bit */
19481 #define OTFDEC_IER_XONEIE_Pos               (1U)
19482 #define OTFDEC_IER_XONEIE_Msk               (0x1UL << OTFDEC_IER_XONEIE_Pos)        /*!< 0x00000002 */
19483 #define OTFDEC_IER_XONEIE                   OTFDEC_IER_XONEIE_Msk                   /*!< Execute-only Error Interrupt Enable bit */
19484 #define OTFDEC_IER_KEIE_Pos                 (2U)
19485 #define OTFDEC_IER_KEIE_Msk                 (0x1UL << OTFDEC_IER_KEIE_Pos)          /*!< 0x00000004 */
19486 #define OTFDEC_IER_KEIE                     OTFDEC_IER_KEIE_Msk
19487 
19488 /******************************************************************************/
19489 /*                                                                            */
19490 /*                             Power Control                                  */
19491 /*                                                                            */
19492 /******************************************************************************/
19493 /********************  Bit definition for PWR_CR1 register  *******************/
19494 #define PWR_CR1_LPMS_Pos                    (0U)
19495 #define PWR_CR1_LPMS_Msk                    (0x7UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000007 */
19496 #define PWR_CR1_LPMS                        PWR_CR1_LPMS_Msk                        /*!< LPMS[2:0] Low-power mode selection field     */
19497 #define PWR_CR1_LPMS_0                      (0x1UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000001 */
19498 #define PWR_CR1_LPMS_1                      (0x2UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000002 */
19499 #define PWR_CR1_LPMS_2                      (0x4UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000004 */
19500 #define PWR_CR1_RRSB1_Pos                   (5U)
19501 #define PWR_CR1_RRSB1_Msk                   (0x1UL << PWR_CR1_RRSB1_Pos)            /*!< 0x00000020 */
19502 #define PWR_CR1_RRSB1                       PWR_CR1_RRSB1_Msk                       /*!< SRAM2 page 2 Retention in Standby            */
19503 #define PWR_CR1_RRSB2_Pos                   (6U)
19504 #define PWR_CR1_RRSB2_Msk                   (0x1UL << PWR_CR1_RRSB2_Pos)            /*!< 0x00000040 */
19505 #define PWR_CR1_RRSB2                       PWR_CR1_RRSB2_Msk                       /*!< SRAM2 page 1 Retention in Standby            */
19506 #define PWR_CR1_ULPMEN_Pos                  (7U)
19507 #define PWR_CR1_ULPMEN_Msk                  (0x1UL << PWR_CR1_ULPMEN_Pos)           /*!< 0x00000080 */
19508 #define PWR_CR1_ULPMEN                      PWR_CR1_ULPMEN_Msk                      /*!< BOR ultra-low power mode in Standby/Shutdown */
19509 #define PWR_CR1_SRAM1PD_Pos                 (8U)
19510 #define PWR_CR1_SRAM1PD_Msk                 (0x1UL << PWR_CR1_SRAM1PD_Pos)          /*!< 0x00000100 */
19511 #define PWR_CR1_SRAM1PD                     PWR_CR1_SRAM1PD_Msk                     /*!< SRAM1 power-down in Run mode                 */
19512 #define PWR_CR1_SRAM2PD_Pos                 (9U)
19513 #define PWR_CR1_SRAM2PD_Msk                 (0x1UL << PWR_CR1_SRAM2PD_Pos)          /*!< 0x00000200 */
19514 #define PWR_CR1_SRAM2PD                     PWR_CR1_SRAM2PD_Msk                     /*!< SRAM2 power-down in Run mode                 */
19515 #define PWR_CR1_SRAM3PD_Pos                 (10U)
19516 #define PWR_CR1_SRAM3PD_Msk                 (0x1UL << PWR_CR1_SRAM3PD_Pos)          /*!< 0x00000400 */
19517 #define PWR_CR1_SRAM3PD                     PWR_CR1_SRAM3PD_Msk                     /*!< SRAM3 power-down in Run mode                 */
19518 #define PWR_CR1_SRAM4PD_Pos                 (11U)
19519 #define PWR_CR1_SRAM4PD_Msk                 (0x1UL << PWR_CR1_SRAM4PD_Pos)          /*!< 0x00000800 */
19520 #define PWR_CR1_SRAM4PD                     PWR_CR1_SRAM4PD_Msk                     /*!< SRAM4 power-down in Run mode                 */
19521 #define PWR_CR1_SRAM5PD_Pos                 (12U)
19522 #define PWR_CR1_SRAM5PD_Msk                 (0x1UL << PWR_CR1_SRAM5PD_Pos)           /*!< 0x0001000 */
19523 #define PWR_CR1_SRAM5PD                     PWR_CR1_SRAM5PD_Msk                      /*!< SRAM5 power down                            */
19524 #define PWR_CR1_SRAM6PD_Pos                 (13U)
19525 #define PWR_CR1_SRAM6PD_Msk                 (0x1UL << PWR_CR1_SRAM6PD_Pos)           /*!< 0x0002000 */
19526 #define PWR_CR1_SRAM6PD                     PWR_CR1_SRAM6PD_Msk                      /*!< SRAM6 power down                            */
19527 #define PWR_CR1_FORCE_USBPWR_Pos            (15U)
19528 #define PWR_CR1_FORCE_USBPWR_Msk            (0x1UL << PWR_CR1_FORCE_USBPWR_Pos)      /*!< 0x0008000 */
19529 #define PWR_CR1_FORCE_USBPWR                PWR_CR1_FORCE_USBPWR_Msk                 /*!< Force USB PWR                               */
19530 
19531 /********************  Bit definition for PWR_CR2 register  *******************/
19532 #define PWR_CR2_SRAM1PDS1_Pos               (0U)
19533 #define PWR_CR2_SRAM1PDS1_Msk               (0x1UL << PWR_CR2_SRAM1PDS1_Pos)        /*!< 0x00000001 */
19534 #define PWR_CR2_SRAM1PDS1                   PWR_CR2_SRAM1PDS1_Msk                   /*!< SRAM1 page 1 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
19535 #define PWR_CR2_SRAM1PDS2_Pos               (1U)
19536 #define PWR_CR2_SRAM1PDS2_Msk               (0x1UL << PWR_CR2_SRAM1PDS2_Pos)        /*!< 0x00000002 */
19537 #define PWR_CR2_SRAM1PDS2                   PWR_CR2_SRAM1PDS2_Msk                   /*!< SRAM1 page 2 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
19538 #define PWR_CR2_SRAM1PDS3_Pos               (2U)
19539 #define PWR_CR2_SRAM1PDS3_Msk               (0x1UL << PWR_CR2_SRAM1PDS3_Pos)        /*!< 0x00000004 */
19540 #define PWR_CR2_SRAM1PDS3                   PWR_CR2_SRAM1PDS3_Msk                   /*!< SRAM1 page 3 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
19541 #define PWR_CR2_SRAM2PDS1_Pos               (4U)
19542 #define PWR_CR2_SRAM2PDS1_Msk               (0x1UL << PWR_CR2_SRAM2PDS1_Pos)        /*!< 0x00000010 */
19543 #define PWR_CR2_SRAM2PDS1                   PWR_CR2_SRAM2PDS1_Msk                   /*!< SRAM2 page 1 (8 KB) power-down in Stop modes (Stop 0, 1, 2, 3)            */
19544 #define PWR_CR2_SRAM2PDS2_Pos               (5U)
19545 #define PWR_CR2_SRAM2PDS2_Msk               (0x1UL << PWR_CR2_SRAM2PDS2_Pos)        /*!< 0x00000020 */
19546 #define PWR_CR2_SRAM2PDS2                   PWR_CR2_SRAM2PDS2_Msk                   /*!< SRAM2 page 2 (56 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
19547 #define PWR_CR2_SRAM4PDS_Pos                (6U)
19548 #define PWR_CR2_SRAM4PDS_Msk                (0x1UL << PWR_CR2_SRAM4PDS_Pos)         /*!< 0x00000040 */
19549 #define PWR_CR2_SRAM4PDS                    PWR_CR2_SRAM4PDS_Msk                    /*!< SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3)                          */
19550 #define PWR_CR2_DC2RAMPDS_Pos               (7U)
19551 #define PWR_CR2_DC2RAMPDS_Msk               (0x1UL << PWR_CR2_DC2RAMPDS_Pos)        /*!< 0x00000080 */
19552 #define PWR_CR2_DC2RAMPDS                   PWR_CR2_DC2RAMPDS_Msk                   /*!< DCACHE2 SRAM power-down in Stop modes (Stop 0, 1, 2, 3)                   */
19553 #define PWR_CR2_ICRAMPDS_Pos                (8U)
19554 #define PWR_CR2_ICRAMPDS_Msk                (0x1UL << PWR_CR2_ICRAMPDS_Pos)         /*!< 0x00000100 */
19555 #define PWR_CR2_ICRAMPDS                    PWR_CR2_ICRAMPDS_Msk                    /*!< ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3)                    */
19556 #define PWR_CR2_DC1RAMPDS_Pos               (9U)
19557 #define PWR_CR2_DC1RAMPDS_Msk               (0x1UL << PWR_CR2_DC1RAMPDS_Pos)        /*!< 0x00000200 */
19558 #define PWR_CR2_DC1RAMPDS                   PWR_CR2_DC1RAMPDS_Msk                   /*!< DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3)                   */
19559 #define PWR_CR2_DMA2DRAMPDS_Pos             (10U)
19560 #define PWR_CR2_DMA2DRAMPDS_Msk             (0x1UL << PWR_CR2_DMA2DRAMPDS_Pos)      /*!< 0x00000400 */
19561 #define PWR_CR2_DMA2DRAMPDS                 PWR_CR2_DMA2DRAMPDS_Msk                 /*!< DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3)                     */
19562 #define PWR_CR2_PRAMPDS_Pos                 (11U)
19563 #define PWR_CR2_PRAMPDS_Msk                 (0x1UL << PWR_CR2_PRAMPDS_Pos)          /*!< 0x00000800 */
19564 #define PWR_CR2_PRAMPDS                     PWR_CR2_PRAMPDS_Msk                     /*!< FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3) */
19565 #define PWR_CR2_PKARAMPDS_Pos               (12U)
19566 #define PWR_CR2_PKARAMPDS_Msk               (0x1UL << PWR_CR2_PKARAMPDS_Pos)        /*!< 0x00001000 */
19567 #define PWR_CR2_PKARAMPDS                   PWR_CR2_PKARAMPDS_Msk                   /*!< PKA32 SRAM power-down in Stop modes (Stop 0, 1, 2, 3)                     */
19568 #define PWR_CR2_SRAM4FWU_Pos                (13U)
19569 #define PWR_CR2_SRAM4FWU_Msk                (0x1UL << PWR_CR2_SRAM4FWU_Pos)         /*!< 0x00002000 */
19570 #define PWR_CR2_SRAM4FWU                    PWR_CR2_SRAM4FWU_Msk                    /*!< SRAM4 fast wakeup from Stop modes (Stop 0, 1, 2)                          */
19571 #define PWR_CR2_FLASHFWU_Pos                (14U)
19572 #define PWR_CR2_FLASHFWU_Msk                (0x1UL << PWR_CR2_FLASHFWU_Pos)         /*!< 0x00004000 */
19573 #define PWR_CR2_FLASHFWU                    PWR_CR2_FLASHFWU_Msk                    /*!< Flash memory fast wakeup from Stop modes (Stop 0, 1)                      */
19574 #define PWR_CR2_SRAM3PDS1_Pos               (16U)
19575 #define PWR_CR2_SRAM3PDS1_Msk               (0x1UL << PWR_CR2_SRAM3PDS1_Pos)        /*!< 0x00010000 */
19576 #define PWR_CR2_SRAM3PDS1                   PWR_CR2_SRAM3PDS1_Msk                   /*!< SRAM3 page 1 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
19577 #define PWR_CR2_SRAM3PDS2_Pos               (17U)
19578 #define PWR_CR2_SRAM3PDS2_Msk               (0x1UL << PWR_CR2_SRAM3PDS2_Pos)        /*!< 0x00020000 */
19579 #define PWR_CR2_SRAM3PDS2                   PWR_CR2_SRAM3PDS2_Msk                   /*!< SRAM3 page 2 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
19580 #define PWR_CR2_SRAM3PDS3_Pos               (18U)
19581 #define PWR_CR2_SRAM3PDS3_Msk               (0x1UL << PWR_CR2_SRAM3PDS3_Pos)        /*!< 0x00040000 */
19582 #define PWR_CR2_SRAM3PDS3                   PWR_CR2_SRAM3PDS3_Msk                   /*!< SRAM3 page 3 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
19583 #define PWR_CR2_SRAM3PDS4_Pos               (19U)
19584 #define PWR_CR2_SRAM3PDS4_Msk               (0x1UL << PWR_CR2_SRAM3PDS4_Pos)        /*!< 0x00080000 */
19585 #define PWR_CR2_SRAM3PDS4                   PWR_CR2_SRAM3PDS4_Msk                   /*!< SRAM3 page 4 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
19586 #define PWR_CR2_SRAM3PDS5_Pos               (20U)
19587 #define PWR_CR2_SRAM3PDS5_Msk               (0x1UL << PWR_CR2_SRAM3PDS5_Pos)        /*!< 0x00100000 */
19588 #define PWR_CR2_SRAM3PDS5                   PWR_CR2_SRAM3PDS5_Msk                   /*!< SRAM3 page 5 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
19589 #define PWR_CR2_SRAM3PDS6_Pos               (21U)
19590 #define PWR_CR2_SRAM3PDS6_Msk               (0x1UL << PWR_CR2_SRAM3PDS6_Pos)        /*!< 0x00200000 */
19591 #define PWR_CR2_SRAM3PDS6                   PWR_CR2_SRAM3PDS6_Msk                   /*!< SRAM3 page 6 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
19592 #define PWR_CR2_SRAM3PDS7_Pos               (22U)
19593 #define PWR_CR2_SRAM3PDS7_Msk               (0x1UL << PWR_CR2_SRAM3PDS7_Pos)        /*!< 0x00400000 */
19594 #define PWR_CR2_SRAM3PDS7                   PWR_CR2_SRAM3PDS7_Msk                   /*!< SRAM3 page 7 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
19595 #define PWR_CR2_SRAM3PDS8_Pos               (23U)
19596 #define PWR_CR2_SRAM3PDS8_Msk               (0x1UL << PWR_CR2_SRAM3PDS8_Pos)        /*!< 0x00800000 */
19597 #define PWR_CR2_SRAM3PDS8                   PWR_CR2_SRAM3PDS8_Msk                   /*!< SRAM3 page 8 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)           */
19598 #define PWR_CR2_GPRAMPDS_Pos                (24U)
19599 #define PWR_CR2_GPRAMPDS_Msk                (0x1UL << PWR_CR2_GPRAMPDS_Pos)         /*!< 0x01000000 */
19600 #define PWR_CR2_GPRAMPDS                    PWR_CR2_GPRAMPDS_Msk                    /*!< Graphic peripherals (LTDC, GFXMMU) SRAM power-down in Stop modes (Stop 0, 1, 2, 3) */
19601 #define PWR_CR2_DSIRAMPDS_Pos               (25U)
19602 #define PWR_CR2_DSIRAMPDS_Msk               (0x1UL << PWR_CR2_DSIRAMPDS_Pos)        /*!< 0x02000000 */
19603 #define PWR_CR2_DSIRAMPDS                   PWR_CR2_DSIRAMPDS_Msk                   /*!< DSI SRAM power-down in Stop modes (Stop 0, 1)                                      */
19604 #define PWR_CR2_JPEGRAMPDS_Pos              (26U)
19605 #define PWR_CR2_JPEGRAMPDS_Msk              (0x1UL << PWR_CR2_JPEGRAMPDS_Pos)       /*!< 0x04000000 */
19606 #define PWR_CR2_JPEGRAMPDS                  PWR_CR2_JPEGRAMPDS_Msk                  /*!< JPEG SRAM power-down in Stop modes (Stop 0, 1)                             */
19607 #define PWR_CR2_SRDRUN_Pos                  (31U)
19608 #define PWR_CR2_SRDRUN_Msk                  (0x1UL << PWR_CR2_SRDRUN_Pos)           /*!< 0x80000000 */
19609 #define PWR_CR2_SRDRUN                      PWR_CR2_SRDRUN_Msk                      /*!< SmartRun domain in Run mode */
19610 
19611 /********************  Bit definition for PWR_CR3 register  *******************/
19612 #define PWR_CR3_REGSEL_Pos                  (1U)
19613 #define PWR_CR3_REGSEL_Msk                  (0x1UL << PWR_CR3_REGSEL_Pos)           /*!< 0x00000002 */
19614 #define PWR_CR3_REGSEL                      PWR_CR3_REGSEL_Msk                      /*!< Regulator selection */
19615 #define PWR_CR3_FSTEN_Pos                   (2U)
19616 #define PWR_CR3_FSTEN_Msk                   (0x1UL << PWR_CR3_FSTEN_Pos)            /*!< 0x00000004 */
19617 #define PWR_CR3_FSTEN                       PWR_CR3_FSTEN_Msk                       /*!< Fast soft start     */
19618 
19619 /*******************  Bit definition for PWR_VOSR register  *******************/
19620 #define PWR_VOSR_USBBOOSTRDY_Pos            (13U)
19621 #define PWR_VOSR_USBBOOSTRDY_Msk            (0x1UL << PWR_VOSR_USBBOOSTRDY_Pos)     /*!< 0x00002000 */
19622 #define PWR_VOSR_USBBOOSTRDY                PWR_VOSR_USBBOOSTRDY_Msk                /*!< USB EPOD booster ready                               */
19623 #define PWR_VOSR_BOOSTRDY_Pos               (14U)
19624 #define PWR_VOSR_BOOSTRDY_Msk               (0x1UL << PWR_VOSR_BOOSTRDY_Pos)        /*!< 0x00004000 */
19625 #define PWR_VOSR_BOOSTRDY                   PWR_VOSR_BOOSTRDY_Msk                   /*!< EPOD booster ready                                   */
19626 #define PWR_VOSR_VOSRDY_Pos                 (15U)
19627 #define PWR_VOSR_VOSRDY_Msk                 (0x1UL << PWR_VOSR_VOSRDY_Pos)          /*!< 0x00008000 */
19628 #define PWR_VOSR_VOSRDY                     PWR_VOSR_VOSRDY_Msk                     /*!< Ready bit for VCORE voltage scaling output selection */
19629 #define PWR_VOSR_VOS_Pos                    (16U)
19630 #define PWR_VOSR_VOS_Msk                    (0x3UL << PWR_VOSR_VOS_Pos)             /*!< 0x00030000 */
19631 #define PWR_VOSR_VOS                        PWR_VOSR_VOS_Msk                        /*!< VOS[1:0] Voltage scaling range selection field       */
19632 #define PWR_VOSR_VOS_0                      (0x1UL << PWR_VOSR_VOS_Pos)             /*!< 0x00010000 */
19633 #define PWR_VOSR_VOS_1                      (0x2UL << PWR_VOSR_VOS_Pos)             /*!< 0x00020000 */
19634 #define PWR_VOSR_BOOSTEN_Pos                (18U)
19635 #define PWR_VOSR_BOOSTEN_Msk                (0x1UL << PWR_VOSR_BOOSTEN_Pos)         /*!< 0x00040000 */
19636 #define PWR_VOSR_BOOSTEN                    PWR_VOSR_BOOSTEN_Msk                    /*!< EPOD booster enable                                  */
19637 #define PWR_VOSR_USBPWREN_Pos               (19U)
19638 #define PWR_VOSR_USBPWREN_Msk               (0x1UL << PWR_VOSR_USBPWREN_Pos)       /*!< 0x00080000 */
19639 #define PWR_VOSR_USBPWREN                   PWR_VOSR_USBPWREN_Msk                  /*!< USB Power enable                                     */
19640 #define PWR_VOSR_USBBOOSTEN_Pos             (20U)
19641 #define PWR_VOSR_USBBOOSTEN_Msk             (0x1UL << PWR_VOSR_USBBOOSTEN_Pos)     /*!< 0x00100000 */
19642 #define PWR_VOSR_USBBOOSTEN                 PWR_VOSR_USBBOOSTEN_Msk                /*!< USB EPOD booster enable                              */
19643 #define PWR_VOSR_VDD11USBDIS_Pos            (21U)
19644 #define PWR_VOSR_VDD11USBDIS_Msk            (0x1UL << PWR_VOSR_VDD11USBDIS_Pos)    /*!< 0x00200000 */
19645 #define PWR_VOSR_VDD11USBDIS                PWR_VOSR_VDD11USBDIS_Msk               /*!< OTG_HS VDD11USB disable                              */
19646 
19647 /*******************  Bit definition for PWR_SVMCR register  ******************/
19648 #define PWR_SVMCR_PVDE_Pos                  (4U)
19649 #define PWR_SVMCR_PVDE_Msk                  (0x1UL << PWR_SVMCR_PVDE_Pos)           /*!< 0x00000010 */
19650 #define PWR_SVMCR_PVDE                      PWR_SVMCR_PVDE_Msk                      /*!< Programmable voltage detector enable                            */
19651 #define PWR_SVMCR_PVDLS_Pos                 (5U)
19652 #define PWR_SVMCR_PVDLS_Msk                 (0x7UL << PWR_SVMCR_PVDLS_Pos)          /*!< 0x000000E0 */
19653 #define PWR_SVMCR_PVDLS                     PWR_SVMCR_PVDLS_Msk                     /*!< PVDLS[2:0] Programmable voltage detector level selection field  */
19654 #define PWR_SVMCR_PVDLS_0                   (0x1UL << PWR_SVMCR_PVDLS_Pos)          /*!< 0x00000020 */
19655 #define PWR_SVMCR_PVDLS_1                   (0x2UL << PWR_SVMCR_PVDLS_Pos)          /*!< 0x00000040 */
19656 #define PWR_SVMCR_PVDLS_2                   (0x4UL << PWR_SVMCR_PVDLS_Pos)          /*!< 0x00000080 */
19657 #define PWR_SVMCR_UVMEN_Pos                 (24U)
19658 #define PWR_SVMCR_UVMEN_Msk                 (0x1UL << PWR_SVMCR_UVMEN_Pos)          /*!< 0x01000000 */
19659 #define PWR_SVMCR_UVMEN                     PWR_SVMCR_UVMEN_Msk                     /*!< VDDUSB Independent USB supply voltage monitor enable            */
19660 #define PWR_SVMCR_IO2VMEN_Pos               (25U)
19661 #define PWR_SVMCR_IO2VMEN_Msk               (0x1UL << PWR_SVMCR_IO2VMEN_Pos)        /*!< 0x02000000 */
19662 #define PWR_SVMCR_IO2VMEN                   PWR_SVMCR_IO2VMEN_Msk                   /*!< VDDIO2 Independent I/Os voltage monitor enable                  */
19663 #define PWR_SVMCR_AVM1EN_Pos                (26U)
19664 #define PWR_SVMCR_AVM1EN_Msk                (0x1UL << PWR_SVMCR_AVM1EN_Pos)         /*!< 0x04000000 */
19665 #define PWR_SVMCR_AVM1EN                    PWR_SVMCR_AVM1EN_Msk                    /*!< VDDA Independent analog supply voltage monitor 1 enable         */
19666 #define PWR_SVMCR_AVM2EN_Pos                (27U)
19667 #define PWR_SVMCR_AVM2EN_Msk                (0x1UL << PWR_SVMCR_AVM2EN_Pos)         /*!< 0x08000000 */
19668 #define PWR_SVMCR_AVM2EN                    PWR_SVMCR_AVM2EN_Msk                    /*!< VDDA Independent analog supply voltage monitor 2 enable         */
19669 #define PWR_SVMCR_USV_Pos                   (28U)
19670 #define PWR_SVMCR_USV_Msk                   (0x1UL << PWR_SVMCR_USV_Pos)            /*!< 0x10000000 */
19671 #define PWR_SVMCR_USV                       PWR_SVMCR_USV_Msk                       /*!< VDDUSB Independent USB supply valid                             */
19672 #define PWR_SVMCR_IO2SV_Pos                 (29U)
19673 #define PWR_SVMCR_IO2SV_Msk                 (0x1UL << PWR_SVMCR_IO2SV_Pos)          /*!< 0x20000000 */
19674 #define PWR_SVMCR_IO2SV                     PWR_SVMCR_IO2SV_Msk                     /*!< VDDIO2 Independent I/Os supply valid                            */
19675 #define PWR_SVMCR_ASV_Pos                   (30U)
19676 #define PWR_SVMCR_ASV_Msk                   (0x1UL << PWR_SVMCR_ASV_Pos)            /*!< 0x40000000 */
19677 #define PWR_SVMCR_ASV                       PWR_SVMCR_ASV_Msk                       /*!< VDDA Independent analog supply valid                            */
19678 
19679 /*******************  Bit definition for PWR_WUCR1 register  ******************/
19680 #define PWR_WUCR1_WUPEN1_Pos                (0U)
19681 #define PWR_WUCR1_WUPEN1_Msk                (0x1UL << PWR_WUCR1_WUPEN1_Pos)         /*!< 0x00000001 */
19682 #define PWR_WUCR1_WUPEN1                    PWR_WUCR1_WUPEN1_Msk                    /*!< Wakeup pin WKUP1 enable */
19683 #define PWR_WUCR1_WUPEN2_Pos                (1U)
19684 #define PWR_WUCR1_WUPEN2_Msk                (0x1UL << PWR_WUCR1_WUPEN2_Pos)         /*!< 0x00000002 */
19685 #define PWR_WUCR1_WUPEN2                    PWR_WUCR1_WUPEN2_Msk                    /*!< Wakeup pin WKUP2 enable */
19686 #define PWR_WUCR1_WUPEN3_Pos                (2U)
19687 #define PWR_WUCR1_WUPEN3_Msk                (0x1UL << PWR_WUCR1_WUPEN3_Pos)         /*!< 0x00000004 */
19688 #define PWR_WUCR1_WUPEN3                    PWR_WUCR1_WUPEN3_Msk                    /*!< Wakeup pin WKUP3 enable */
19689 #define PWR_WUCR1_WUPEN4_Pos                (3U)
19690 #define PWR_WUCR1_WUPEN4_Msk                (0x1UL << PWR_WUCR1_WUPEN4_Pos)         /*!< 0x00000008 */
19691 #define PWR_WUCR1_WUPEN4                    PWR_WUCR1_WUPEN4_Msk                    /*!< Wakeup pin WKUP4 enable */
19692 #define PWR_WUCR1_WUPEN5_Pos                (4U)
19693 #define PWR_WUCR1_WUPEN5_Msk                (0x1UL << PWR_WUCR1_WUPEN5_Pos)         /*!< 0x00000010 */
19694 #define PWR_WUCR1_WUPEN5                    PWR_WUCR1_WUPEN5_Msk                    /*!< Wakeup pin WKUP5 enable */
19695 #define PWR_WUCR1_WUPEN6_Pos                (5U)
19696 #define PWR_WUCR1_WUPEN6_Msk                (0x1UL << PWR_WUCR1_WUPEN6_Pos)         /*!< 0x00000020 */
19697 #define PWR_WUCR1_WUPEN6                    PWR_WUCR1_WUPEN6_Msk                    /*!< Wakeup pin WKUP6 enable */
19698 #define PWR_WUCR1_WUPEN7_Pos                (6U)
19699 #define PWR_WUCR1_WUPEN7_Msk                (0x1UL << PWR_WUCR1_WUPEN7_Pos)         /*!< 0x00000040 */
19700 #define PWR_WUCR1_WUPEN7                    PWR_WUCR1_WUPEN7_Msk                    /*!< Wakeup pin WKUP7 enable */
19701 #define PWR_WUCR1_WUPEN8_Pos                (7U)
19702 #define PWR_WUCR1_WUPEN8_Msk                (0x1UL << PWR_WUCR1_WUPEN8_Pos)         /*!< 0x00000080 */
19703 #define PWR_WUCR1_WUPEN8                    PWR_WUCR1_WUPEN8_Msk                    /*!< Wakeup pin WKUP8 enable */
19704 
19705 /*******************  Bit definition for PWR_WUCR2 register  ******************/
19706 #define PWR_WUCR2_WUPP1_Pos                 (0U)
19707 #define PWR_WUCR2_WUPP1_Msk                 (0x1UL << PWR_WUCR2_WUPP1_Pos)          /*!< 0x00000001 */
19708 #define PWR_WUCR2_WUPP1                     PWR_WUCR2_WUPP1_Msk                     /*!< Wakeup pin WKUP1 polarity */
19709 #define PWR_WUCR2_WUPP2_Pos                 (1U)
19710 #define PWR_WUCR2_WUPP2_Msk                 (0x1UL << PWR_WUCR2_WUPP2_Pos)          /*!< 0x00000002 */
19711 #define PWR_WUCR2_WUPP2                     PWR_WUCR2_WUPP2_Msk                     /*!< Wakeup pin WKUP2 polarity */
19712 #define PWR_WUCR2_WUPP3_Pos                 (2U)
19713 #define PWR_WUCR2_WUPP3_Msk                 (0x1UL << PWR_WUCR2_WUPP3_Pos)          /*!< 0x00000004 */
19714 #define PWR_WUCR2_WUPP3                     PWR_WUCR2_WUPP3_Msk                     /*!< Wakeup pin WKUP3 polarity */
19715 #define PWR_WUCR2_WUPP4_Pos                 (3U)
19716 #define PWR_WUCR2_WUPP4_Msk                 (0x1UL << PWR_WUCR2_WUPP4_Pos)          /*!< 0x00000008 */
19717 #define PWR_WUCR2_WUPP4                     PWR_WUCR2_WUPP4_Msk                     /*!< Wakeup pin WKUP4 polarity */
19718 #define PWR_WUCR2_WUPP5_Pos                 (4U)
19719 #define PWR_WUCR2_WUPP5_Msk                 (0x1UL << PWR_WUCR2_WUPP5_Pos)          /*!< 0x00000010 */
19720 #define PWR_WUCR2_WUPP5                     PWR_WUCR2_WUPP5_Msk                     /*!< Wakeup pin WKUP5 polarity */
19721 #define PWR_WUCR2_WUPP6_Pos                 (5U)
19722 #define PWR_WUCR2_WUPP6_Msk                 (0x1UL << PWR_WUCR2_WUPP6_Pos)          /*!< 0x00000020 */
19723 #define PWR_WUCR2_WUPP6                     PWR_WUCR2_WUPP6_Msk                     /*!< Wakeup pin WKUP6 polarity */
19724 #define PWR_WUCR2_WUPP7_Pos                 (6U)
19725 #define PWR_WUCR2_WUPP7_Msk                 (0x1UL << PWR_WUCR2_WUPP7_Pos)          /*!< 0x00000040 */
19726 #define PWR_WUCR2_WUPP7                     PWR_WUCR2_WUPP7_Msk                     /*!< Wakeup pin WKUP7 polarity */
19727 #define PWR_WUCR2_WUPP8_Pos                 (7U)
19728 #define PWR_WUCR2_WUPP8_Msk                 (0x1UL << PWR_WUCR2_WUPP8_Pos)          /*!< 0x00000080 */
19729 #define PWR_WUCR2_WUPP8                     PWR_WUCR2_WUPP8_Msk                     /*!< Wakeup pin WKUP8 polarity */
19730 
19731 /*******************  Bit definition for PWR_WUCR3 register  ******************/
19732 #define PWR_WUCR3_WUSEL1_Pos                (0U)
19733 #define PWR_WUCR3_WUSEL1_Msk                (0x3UL << PWR_WUCR3_WUSEL1_Pos)         /*!< 0x00000003 */
19734 #define PWR_WUCR3_WUSEL1                    PWR_WUCR3_WUSEL1_Msk                    /*!< Wakeup pin WKUP1 selection field */
19735 #define PWR_WUCR3_WUSEL1_0                  (0x1UL << PWR_WUCR3_WUSEL1_Pos)         /*!< 0x00000001 */
19736 #define PWR_WUCR3_WUSEL1_1                  (0x2UL << PWR_WUCR3_WUSEL1_Pos)         /*!< 0x00000002 */
19737 #define PWR_WUCR3_WUSEL2_Pos                (2U)
19738 #define PWR_WUCR3_WUSEL2_Msk                (0x3UL << PWR_WUCR3_WUSEL2_Pos)         /*!< 0x0000000C */
19739 #define PWR_WUCR3_WUSEL2                    PWR_WUCR3_WUSEL2_Msk                    /*!< Wakeup pin WKUP2 selection field */
19740 #define PWR_WUCR3_WUSEL2_0                  (0x1UL << PWR_WUCR3_WUSEL2_Pos)         /*!< 0x00000004 */
19741 #define PWR_WUCR3_WUSEL2_1                  (0x2UL << PWR_WUCR3_WUSEL2_Pos)         /*!< 0x00000008 */
19742 #define PWR_WUCR3_WUSEL3_Pos                (4U)
19743 #define PWR_WUCR3_WUSEL3_Msk                (0x3UL << PWR_WUCR3_WUSEL3_Pos)         /*!< 0x00000030 */
19744 #define PWR_WUCR3_WUSEL3                    PWR_WUCR3_WUSEL3_Msk                    /*!< Wakeup pin WKUP3 selection field */
19745 #define PWR_WUCR3_WUSEL3_0                  (0x1UL << PWR_WUCR3_WUSEL3_Pos)         /*!< 0x00000010 */
19746 #define PWR_WUCR3_WUSEL3_1                  (0x2UL << PWR_WUCR3_WUSEL3_Pos)         /*!< 0x00000020 */
19747 #define PWR_WUCR3_WUSEL4_Pos                (6U)
19748 #define PWR_WUCR3_WUSEL4_Msk                (0x3UL << PWR_WUCR3_WUSEL4_Pos)         /*!< 0x000000C0 */
19749 #define PWR_WUCR3_WUSEL4                    PWR_WUCR3_WUSEL4_Msk                    /*!< Wakeup pin WKUP4 selection field */
19750 #define PWR_WUCR3_WUSEL4_0                  (0x1UL << PWR_WUCR3_WUSEL4_Pos)         /*!< 0x00000040 */
19751 #define PWR_WUCR3_WUSEL4_1                  (0x2UL << PWR_WUCR3_WUSEL4_Pos)         /*!< 0x00000080 */
19752 #define PWR_WUCR3_WUSEL5_Pos                (8U)
19753 #define PWR_WUCR3_WUSEL5_Msk                (0x3UL << PWR_WUCR3_WUSEL5_Pos)         /*!< 0x00000300 */
19754 #define PWR_WUCR3_WUSEL5                    PWR_WUCR3_WUSEL5_Msk                    /*!< Wakeup pin WKUP5 selection field */
19755 #define PWR_WUCR3_WUSEL5_0                  (0x1UL << PWR_WUCR3_WUSEL5_Pos)         /*!< 0x00000100 */
19756 #define PWR_WUCR3_WUSEL5_1                  (0x2UL << PWR_WUCR3_WUSEL5_Pos)         /*!< 0x00000200 */
19757 #define PWR_WUCR3_WUSEL6_Pos                (10U)
19758 #define PWR_WUCR3_WUSEL6_Msk                (0x3UL << PWR_WUCR3_WUSEL6_Pos)         /*!< 0x00000C00 */
19759 #define PWR_WUCR3_WUSEL6                    PWR_WUCR3_WUSEL6_Msk                    /*!< Wakeup pin WKUP6 selection field */
19760 #define PWR_WUCR3_WUSEL6_0                  (0x1UL << PWR_WUCR3_WUSEL6_Pos)         /*!< 0x00000400 */
19761 #define PWR_WUCR3_WUSEL6_1                  (0x2UL << PWR_WUCR3_WUSEL6_Pos)         /*!< 0x00000800 */
19762 #define PWR_WUCR3_WUSEL7_Pos                (12U)
19763 #define PWR_WUCR3_WUSEL7_Msk                (0x3UL << PWR_WUCR3_WUSEL7_Pos)         /*!< 0x00003000 */
19764 #define PWR_WUCR3_WUSEL7                    PWR_WUCR3_WUSEL7_Msk                    /*!< Wakeup pin WKUP7 selection field */
19765 #define PWR_WUCR3_WUSEL7_0                  (0x1UL << PWR_WUCR3_WUSEL7_Pos)         /*!< 0x00001000 */
19766 #define PWR_WUCR3_WUSEL7_1                  (0x2UL << PWR_WUCR3_WUSEL7_Pos)         /*!< 0x00002000 */
19767 #define PWR_WUCR3_WUSEL8_Pos                (14U)
19768 #define PWR_WUCR3_WUSEL8_Msk                (0x3UL << PWR_WUCR3_WUSEL8_Pos)         /*!< 0x0000C000 */
19769 #define PWR_WUCR3_WUSEL8                    PWR_WUCR3_WUSEL8_Msk                    /*!< Wakeup pin WKUP8 selection field */
19770 #define PWR_WUCR3_WUSEL8_0                  (0x1UL << PWR_WUCR3_WUSEL8_Pos)         /*!< 0x00004000 */
19771 #define PWR_WUCR3_WUSEL8_1                  (0x2UL << PWR_WUCR3_WUSEL8_Pos)         /*!< 0x00008000 */
19772 
19773 /*******************  Bit definition for PWR_BDCR1 register  ******************/
19774 #define PWR_BDCR1_BREN_Pos                  (0U)
19775 #define PWR_BDCR1_BREN_Msk                  (0x1UL << PWR_BDCR1_BREN_Pos)           /*!< 0x00000001 */
19776 #define PWR_BDCR1_BREN                      PWR_BDCR1_BREN_Msk                      /*!< Backup regulator enable                                 */
19777 #define PWR_BDCR1_MONEN_Pos                 (4U)
19778 #define PWR_BDCR1_MONEN_Msk                 (0x1UL << PWR_BDCR1_MONEN_Pos)          /*!< 0x00000010 */
19779 #define PWR_BDCR1_MONEN                     PWR_BDCR1_MONEN_Msk                     /*!< Backup Domain voltage and temperature monitoring enable */
19780 
19781 /*******************  Bit definition for PWR_BDCR2 register  ******************/
19782 #define PWR_BDCR2_VBE_Pos                   (0U)
19783 #define PWR_BDCR2_VBE_Msk                   (0x1UL << PWR_BDCR2_VBE_Pos)            /*!< 0x00000001 */
19784 #define PWR_BDCR2_VBE                       PWR_BDCR2_VBE_Msk                       /*!< VBAT charging enable             */
19785 #define PWR_BDCR2_VBRS_Pos                  (1U)
19786 #define PWR_BDCR2_VBRS_Msk                  (0x1UL << PWR_BDCR2_VBRS_Pos)           /*!< 0x00000002 */
19787 #define PWR_BDCR2_VBRS                      PWR_BDCR2_VBRS_Msk                      /*!< VBAT charging resistor selection */
19788 
19789 /********************  Bit definition for PWR_DBPR register  ******************/
19790 #define PWR_DBPR_DBP_Pos                    (0U)
19791 #define PWR_DBPR_DBP_Msk                    (0x1UL << PWR_DBPR_DBP_Pos)             /*!< 0x00000001 */
19792 #define PWR_DBPR_DBP                        PWR_DBPR_DBP_Msk                        /*!< Disable backup domain write protection */
19793 
19794 /********************  Bit definition for PWR_UCPDR register  *****************/
19795 #define PWR_UCPDR_UCPD_DBDIS_Pos            (0U)
19796 #define PWR_UCPDR_UCPD_DBDIS_Msk            (0x1UL << PWR_UCPDR_UCPD_DBDIS_Pos)     /*!< 0x00000001 */
19797 #define PWR_UCPDR_UCPD_DBDIS                PWR_UCPDR_UCPD_DBDIS_Msk                /*!< USB Type-C and Power Delivery Dead Battery disable */
19798 #define PWR_UCPDR_UCPD_STDBY_Pos            (1U)
19799 #define PWR_UCPDR_UCPD_STDBY_Msk            (0x1UL << PWR_UCPDR_UCPD_STDBY_Pos)     /*!< 0x00000002 */
19800 #define PWR_UCPDR_UCPD_STDBY                PWR_UCPDR_UCPD_STDBY_Msk                /*!< USB Type-C and Power Delivery Standby mode         */
19801 
19802 /*******************  Bit definition for PWR_SECCFGR register  ****************/
19803 #define PWR_SECCFGR_WUP1SEC_Pos             (0U)
19804 #define PWR_SECCFGR_WUP1SEC_Msk             (0x1UL << PWR_SECCFGR_WUP1SEC_Pos)      /*!< 0x00000001 */
19805 #define PWR_SECCFGR_WUP1SEC                 PWR_SECCFGR_WUP1SEC_Msk                 /*!< WUP1 secure protection                             */
19806 #define PWR_SECCFGR_WUP2SEC_Pos             (1U)
19807 #define PWR_SECCFGR_WUP2SEC_Msk             (0x1UL << PWR_SECCFGR_WUP2SEC_Pos)      /*!< 0x00000002 */
19808 #define PWR_SECCFGR_WUP2SEC                 PWR_SECCFGR_WUP2SEC_Msk                 /*!< WUP2 secure protection                             */
19809 #define PWR_SECCFGR_WUP3SEC_Pos             (2U)
19810 #define PWR_SECCFGR_WUP3SEC_Msk             (0x1UL << PWR_SECCFGR_WUP3SEC_Pos)      /*!< 0x00000004 */
19811 #define PWR_SECCFGR_WUP3SEC                 PWR_SECCFGR_WUP3SEC_Msk                 /*!< WUP3 secure protection                             */
19812 #define PWR_SECCFGR_WUP4SEC_Pos             (3U)
19813 #define PWR_SECCFGR_WUP4SEC_Msk             (0x1UL << PWR_SECCFGR_WUP4SEC_Pos)      /*!< 0x00000008 */
19814 #define PWR_SECCFGR_WUP4SEC                 PWR_SECCFGR_WUP4SEC_Msk                 /*!< WUP4 secure protection                             */
19815 #define PWR_SECCFGR_WUP5SEC_Pos             (4U)
19816 #define PWR_SECCFGR_WUP5SEC_Msk             (0x1UL << PWR_SECCFGR_WUP5SEC_Pos)      /*!< 0x00000010 */
19817 #define PWR_SECCFGR_WUP5SEC                 PWR_SECCFGR_WUP5SEC_Msk                 /*!< WUP5 secure protection                             */
19818 #define PWR_SECCFGR_WUP6SEC_Pos             (5U)
19819 #define PWR_SECCFGR_WUP6SEC_Msk             (0x1UL << PWR_SECCFGR_WUP6SEC_Pos)      /*!< 0x00000020 */
19820 #define PWR_SECCFGR_WUP6SEC                 PWR_SECCFGR_WUP6SEC_Msk                 /*!< WUP6 secure protection                             */
19821 #define PWR_SECCFGR_WUP7SEC_Pos             (6U)
19822 #define PWR_SECCFGR_WUP7SEC_Msk             (0x1UL << PWR_SECCFGR_WUP7SEC_Pos)      /*!< 0x00000040 */
19823 #define PWR_SECCFGR_WUP7SEC                 PWR_SECCFGR_WUP7SEC_Msk                 /*!< WUP7 secure protection                             */
19824 #define PWR_SECCFGR_WUP8SEC_Pos             (7U)
19825 #define PWR_SECCFGR_WUP8SEC_Msk             (0x1UL << PWR_SECCFGR_WUP8SEC_Pos)      /*!< 0x00000080 */
19826 #define PWR_SECCFGR_WUP8SEC                 PWR_SECCFGR_WUP8SEC_Msk                 /*!< WUP8 secure protection                             */
19827 #define PWR_SECCFGR_LPMSEC_Pos              (12U)
19828 #define PWR_SECCFGR_LPMSEC_Msk              (0x1UL << PWR_SECCFGR_LPMSEC_Pos)       /*!< 0x00001000 */
19829 #define PWR_SECCFGR_LPMSEC                  PWR_SECCFGR_LPMSEC_Msk                  /*!< Low-power modes secure protection                  */
19830 #define PWR_SECCFGR_VDMSEC_Pos              (13U)
19831 #define PWR_SECCFGR_VDMSEC_Msk              (0x1UL << PWR_SECCFGR_VDMSEC_Pos)       /*!< 0x00002000 */
19832 #define PWR_SECCFGR_VDMSEC                  PWR_SECCFGR_VDMSEC_Msk                  /*!< Voltage detection and monitoring secure protection */
19833 #define PWR_SECCFGR_VBSEC_Pos               (14U)
19834 #define PWR_SECCFGR_VBSEC_Msk               (0x1UL << PWR_SECCFGR_VBSEC_Pos)        /*!< 0x00004000 */
19835 #define PWR_SECCFGR_VBSEC                   PWR_SECCFGR_VBSEC_Msk                   /*!< Backup domain secure protection                    */
19836 #define PWR_SECCFGR_APCSEC_Pos              (15U)
19837 #define PWR_SECCFGR_APCSEC_Msk              (0x1UL << PWR_SECCFGR_APCSEC_Pos)       /*!< 0x00008000 */
19838 #define PWR_SECCFGR_APCSEC                  PWR_SECCFGR_APCSEC_Msk                  /*!< Pull-up/pull-down secure protection                */
19839 
19840 /*******************  Bit definition for PWR_PRIVCFGR register  ***************/
19841 #define PWR_PRIVCFGR_SPRIV_Pos              (0U)
19842 #define PWR_PRIVCFGR_SPRIV_Msk              (0x1UL << PWR_PRIVCFGR_SPRIV_Pos)       /*!< 0x00000001 */
19843 #define PWR_PRIVCFGR_SPRIV                  PWR_PRIVCFGR_SPRIV_Msk                  /*!< RCC secure functions privilege configuration     */
19844 #define PWR_PRIVCFGR_NSPRIV_Pos             (1U)
19845 #define PWR_PRIVCFGR_NSPRIV_Msk             (0x1UL << PWR_PRIVCFGR_NSPRIV_Pos)      /*!< 0x00000002 */
19846 #define PWR_PRIVCFGR_NSPRIV                 PWR_PRIVCFGR_NSPRIV_Msk                 /*!< RCC non-secure functions privilege configuration */
19847 
19848 /**********************  Bit definition for PWR_SR register  ******************/
19849 #define PWR_SR_CSSF_Pos                     (0U)
19850 #define PWR_SR_CSSF_Msk                     (0x1UL << PWR_SR_CSSF_Pos)              /*!< 0x00000001 */
19851 #define PWR_SR_CSSF                         PWR_SR_CSSF_Msk                         /*!< Clear Stop and Standby/Shutdown flags */
19852 #define PWR_SR_STOPF_Pos                    (1U)
19853 #define PWR_SR_STOPF_Msk                    (0x1UL << PWR_SR_STOPF_Pos)             /*!< 0x00000002 */
19854 #define PWR_SR_STOPF                        PWR_SR_STOPF_Msk                        /*!< Stop flag                             */
19855 #define PWR_SR_SBF_Pos                      (2U)
19856 #define PWR_SR_SBF_Msk                      (0x1UL << PWR_SR_SBF_Pos)               /*!< 0x00000004 */
19857 #define PWR_SR_SBF                          PWR_SR_SBF_Msk                          /*!< Standby/Shutdown flag                 */
19858 
19859 /********************  Bit definition for PWR_SVMSR register  *****************/
19860 #define PWR_SVMSR_REGS_Pos                  (1U)
19861 #define PWR_SVMSR_REGS_Msk                  (0x1UL << PWR_SVMSR_REGS_Pos)           /*!< 0x00000002 */
19862 #define PWR_SVMSR_REGS                      PWR_SVMSR_REGS_Msk                      /*!< Regulator status                                  */
19863 #define PWR_SVMSR_PVDO_Pos                  (4U)
19864 #define PWR_SVMSR_PVDO_Msk                  (0x1UL << PWR_SVMSR_PVDO_Pos)           /*!< 0x00000010 */
19865 #define PWR_SVMSR_PVDO                      PWR_SVMSR_PVDO_Msk                      /*!< VDD voltage detector output                       */
19866 #define PWR_SVMSR_ACTVOSRDY_Pos             (15U)
19867 #define PWR_SVMSR_ACTVOSRDY_Msk             (0x1UL << PWR_SVMSR_ACTVOSRDY_Pos)      /*!< 0x00008000 */
19868 #define PWR_SVMSR_ACTVOSRDY                 PWR_SVMSR_ACTVOSRDY_Msk                 /*!< Voltage level ready for currently used VOS        */
19869 #define PWR_SVMSR_ACTVOS_Pos                (16U)
19870 #define PWR_SVMSR_ACTVOS_Msk                (0x3UL << PWR_SVMSR_ACTVOS_Pos)         /*!< 0x00030000 */
19871 #define PWR_SVMSR_ACTVOS                    PWR_SVMSR_ACTVOS_Msk                    /*!< Voltage Output Scaling currently applied to VCORE */
19872 #define PWR_SVMSR_ACTVOS_0                  (0x1UL << PWR_SVMSR_ACTVOS_Pos)         /*!< 0x00010000 */
19873 #define PWR_SVMSR_ACTVOS_1                  (0x2UL << PWR_SVMSR_ACTVOS_Pos)         /*!< 0x00020000 */
19874 #define PWR_SVMSR_VDDUSBRDY_Pos             (24U)
19875 #define PWR_SVMSR_VDDUSBRDY_Msk             (0x1UL << PWR_SVMSR_VDDUSBRDY_Pos)      /*!< 0x01000000 */
19876 #define PWR_SVMSR_VDDUSBRDY                 PWR_SVMSR_VDDUSBRDY_Msk                 /*!< VDDUSB ready                                      */
19877 #define PWR_SVMSR_VDDIO2RDY_Pos             (25U)
19878 #define PWR_SVMSR_VDDIO2RDY_Msk             (0x1UL << PWR_SVMSR_VDDIO2RDY_Pos)      /*!< 0x02000000 */
19879 #define PWR_SVMSR_VDDIO2RDY                 PWR_SVMSR_VDDIO2RDY_Msk                 /*!< VDDIO2 ready                                      */
19880 #define PWR_SVMSR_VDDA1RDY_Pos              (26U)
19881 #define PWR_SVMSR_VDDA1RDY_Msk              (0x1UL << PWR_SVMSR_VDDA1RDY_Pos)       /*!< 0x04000000 */
19882 #define PWR_SVMSR_VDDA1RDY                  PWR_SVMSR_VDDA1RDY_Msk                  /*!< VDDA ready versus 1.6V voltage monitor            */
19883 #define PWR_SVMSR_VDDA2RDY_Pos              (27U)
19884 #define PWR_SVMSR_VDDA2RDY_Msk              (0x1UL << PWR_SVMSR_VDDA2RDY_Pos)       /*!< 0x08000000 */
19885 #define PWR_SVMSR_VDDA2RDY                  PWR_SVMSR_VDDA2RDY_Msk                  /*!< VDDA ready versus 1.8V voltage monitor            */
19886 
19887 /*********************  Bit definition for PWR_BDSR register  *****************/
19888 #define PWR_BDSR_VBATH_Pos                  (1U)
19889 #define PWR_BDSR_VBATH_Msk                  (0x1UL << PWR_BDSR_VBATH_Pos)           /*!< 0x00000002 */
19890 #define PWR_BDSR_VBATH                      PWR_BDSR_VBATH_Msk                      /*!< VBAT level monitoring versus high threshold        */
19891 #define PWR_BDSR_TEMPL_Pos                  (2U)
19892 #define PWR_BDSR_TEMPL_Msk                  (0x1UL << PWR_BDSR_TEMPL_Pos)           /*!< 0x00000004 */
19893 #define PWR_BDSR_TEMPL                      PWR_BDSR_TEMPL_Msk                      /*!< Temperature level monitoring versus low threshold  */
19894 #define PWR_BDSR_TEMPH_Pos                  (3U)
19895 #define PWR_BDSR_TEMPH_Msk                  (0x1UL << PWR_BDSR_TEMPH_Pos)           /*!< 0x00000008 */
19896 #define PWR_BDSR_TEMPH                      PWR_BDSR_TEMPH_Msk                      /*!< Temperature level monitoring versus high threshold */
19897 
19898 /*********************  Bit definition for PWR_WUSR register  *****************/
19899 #define PWR_WUSR_WUF1_Pos                   (0U)
19900 #define PWR_WUSR_WUF1_Msk                   (0x1UL << PWR_WUSR_WUF1_Pos)            /*!< 0x00000001 */
19901 #define PWR_WUSR_WUF1                       PWR_WUSR_WUF1_Msk                       /*!< Wakeup flag 1   */
19902 #define PWR_WUSR_WUF2_Pos                   (1U)
19903 #define PWR_WUSR_WUF2_Msk                   (0x1UL << PWR_WUSR_WUF2_Pos)            /*!< 0x00000002 */
19904 #define PWR_WUSR_WUF2                       PWR_WUSR_WUF2_Msk                       /*!< Wakeup flag 2   */
19905 #define PWR_WUSR_WUF3_Pos                   (2U)
19906 #define PWR_WUSR_WUF3_Msk                   (0x1UL << PWR_WUSR_WUF3_Pos)            /*!< 0x00000004 */
19907 #define PWR_WUSR_WUF3                       PWR_WUSR_WUF3_Msk                       /*!< Wakeup flag 3   */
19908 #define PWR_WUSR_WUF4_Pos                   (3U)
19909 #define PWR_WUSR_WUF4_Msk                   (0x1UL << PWR_WUSR_WUF4_Pos)            /*!< 0x00000008 */
19910 #define PWR_WUSR_WUF4                       PWR_WUSR_WUF4_Msk                       /*!< Wakeup flag 4   */
19911 #define PWR_WUSR_WUF5_Pos                   (4U)
19912 #define PWR_WUSR_WUF5_Msk                   (0x1UL << PWR_WUSR_WUF5_Pos)            /*!< 0x00000010 */
19913 #define PWR_WUSR_WUF5                       PWR_WUSR_WUF5_Msk                       /*!< Wakeup flag 5   */
19914 #define PWR_WUSR_WUF6_Pos                   (5U)
19915 #define PWR_WUSR_WUF6_Msk                   (0x1UL << PWR_WUSR_WUF6_Pos)            /*!< 0x00000020 */
19916 #define PWR_WUSR_WUF6                       PWR_WUSR_WUF6_Msk                       /*!< Wakeup flag 6   */
19917 #define PWR_WUSR_WUF7_Pos                   (6U)
19918 #define PWR_WUSR_WUF7_Msk                   (0x1UL << PWR_WUSR_WUF7_Pos)            /*!< 0x00000040 */
19919 #define PWR_WUSR_WUF7                       PWR_WUSR_WUF7_Msk                       /*!< Wakeup flag 7   */
19920 #define PWR_WUSR_WUF8_Pos                   (7U)
19921 #define PWR_WUSR_WUF8_Msk                   (0x1UL << PWR_WUSR_WUF8_Pos)            /*!< 0x00000080 */
19922 #define PWR_WUSR_WUF8                       PWR_WUSR_WUF8_Msk                       /*!< Wakeup flag 8   */
19923 #define PWR_WUSR_WUF_Pos                    (0U)
19924 #define PWR_WUSR_WUF_Msk                    (0xFFUL << PWR_WUSR_WUF_Pos)            /*!< 0x000000FF */
19925 #define PWR_WUSR_WUF                        PWR_WUSR_WUF_Msk                        /*!< all Wakeup flag */
19926 
19927 /*********************  Bit definition for PWR_WUSCR register  ****************/
19928 #define PWR_WUSCR_CWUF1_Pos                 (0U)
19929 #define PWR_WUSCR_CWUF1_Msk                 (0x1UL << PWR_WUSCR_CWUF1_Pos)          /*!< 0x00000001*/
19930 #define PWR_WUSCR_CWUF1                     PWR_WUSCR_CWUF1_Msk                     /*!< Wakeup clear flag 1   */
19931 #define PWR_WUSCR_CWUF2_Pos                 (1U)
19932 #define PWR_WUSCR_CWUF2_Msk                 (0x1UL << PWR_WUSCR_CWUF2_Pos)          /*!< 0x00000002 */
19933 #define PWR_WUSCR_CWUF2                     PWR_WUSCR_CWUF2_Msk                     /*!< Wakeup clear flag 2   */
19934 #define PWR_WUSCR_CWUF3_Pos                 (2U)
19935 #define PWR_WUSCR_CWUF3_Msk                 (0x1UL << PWR_WUSCR_CWUF3_Pos)          /*!< 0x00000004 */
19936 #define PWR_WUSCR_CWUF3                     PWR_WUSCR_CWUF3_Msk                     /*!< Wakeup clear flag 3   */
19937 #define PWR_WUSCR_CWUF4_Pos                 (3U)
19938 #define PWR_WUSCR_CWUF4_Msk                 (0x1UL << PWR_WUSCR_CWUF4_Pos)          /*!< 0x00000008 */
19939 #define PWR_WUSCR_CWUF4                     PWR_WUSCR_CWUF4_Msk                     /*!< Wakeup clear flag 4   */
19940 #define PWR_WUSCR_CWUF5_Pos                 (4U)
19941 #define PWR_WUSCR_CWUF5_Msk                 (0x1UL << PWR_WUSCR_CWUF5_Pos)          /*!< 0x00000010 */
19942 #define PWR_WUSCR_CWUF5                     PWR_WUSCR_CWUF5_Msk                     /*!< Wakeup clear flag 5   */
19943 #define PWR_WUSCR_CWUF6_Pos                 (5U)
19944 #define PWR_WUSCR_CWUF6_Msk                 (0x1UL << PWR_WUSCR_CWUF6_Pos)          /*!< 0x00000020 */
19945 #define PWR_WUSCR_CWUF6                     PWR_WUSCR_CWUF6_Msk                     /*!< Wakeup clear flag 6   */
19946 #define PWR_WUSCR_CWUF7_Pos                 (6U)
19947 #define PWR_WUSCR_CWUF7_Msk                 (0x1UL << PWR_WUSCR_CWUF7_Pos)          /*!< 0x00000040 */
19948 #define PWR_WUSCR_CWUF7                     PWR_WUSCR_CWUF7_Msk                     /*!< Wakeup clear flag 7   */
19949 #define PWR_WUSCR_CWUF8_Pos                 (7U)
19950 #define PWR_WUSCR_CWUF8_Msk                 (0x1UL << PWR_WUSCR_CWUF8_Pos)          /*!< 0x00000080 */
19951 #define PWR_WUSCR_CWUF8                     PWR_WUSCR_CWUF8_Msk                     /*!< Wakeup clear flag 8   */
19952 #define PWR_WUSCR_CWUF_Pos                  (0U)
19953 #define PWR_WUSCR_CWUF_Msk                  (0xFFUL << PWR_WUSCR_CWUF_Pos)          /*!< 0x000000FF */
19954 #define PWR_WUSCR_CWUF                      PWR_WUSCR_CWUF_Msk                      /*!< all Wakeup clear flag */
19955 
19956 /*********************  Bit definition for PWR_APCR register  *****************/
19957 #define PWR_APCR_APC_Pos                    (0U)
19958 #define PWR_APCR_APC_Msk                    (0x1UL << PWR_APCR_APC_Pos)             /*!< 0x00000001 */
19959 #define PWR_APCR_APC                        PWR_APCR_APC_Msk                        /*!< Apply pull-up and pull-down configuration */
19960 
19961 /********************  Bit definition for PWR_PUCRA register  *****************/
19962 #define PWR_PUCRA_PU0_Pos                   (0U)
19963 #define PWR_PUCRA_PU0_Msk                   (0x1UL << PWR_PUCRA_PU0_Pos)            /*!< 0x00000001 */
19964 #define PWR_PUCRA_PU0                       PWR_PUCRA_PU0_Msk                       /*!< Apply pull-up for PA0  */
19965 #define PWR_PUCRA_PU1_Pos                   (1U)
19966 #define PWR_PUCRA_PU1_Msk                   (0x1UL << PWR_PUCRA_PU1_Pos)            /*!< 0x00000002 */
19967 #define PWR_PUCRA_PU1                       PWR_PUCRA_PU1_Msk                       /*!< Apply pull-up for PA1  */
19968 #define PWR_PUCRA_PU2_Pos                   (2U)
19969 #define PWR_PUCRA_PU2_Msk                   (0x1UL << PWR_PUCRA_PU2_Pos)            /*!< 0x00000004 */
19970 #define PWR_PUCRA_PU2                       PWR_PUCRA_PU2_Msk                       /*!< Apply pull-up for PA2  */
19971 #define PWR_PUCRA_PU3_Pos                   (3U)
19972 #define PWR_PUCRA_PU3_Msk                   (0x1UL << PWR_PUCRA_PU3_Pos)            /*!< 0x00000008 */
19973 #define PWR_PUCRA_PU3                       PWR_PUCRA_PU3_Msk                       /*!< Apply pull-up for PA3  */
19974 #define PWR_PUCRA_PU4_Pos                   (4U)
19975 #define PWR_PUCRA_PU4_Msk                   (0x1UL << PWR_PUCRA_PU4_Pos)            /*!< 0x00000010 */
19976 #define PWR_PUCRA_PU4                       PWR_PUCRA_PU4_Msk                       /*!< Apply pull-up for PA4  */
19977 #define PWR_PUCRA_PU5_Pos                   (5U)
19978 #define PWR_PUCRA_PU5_Msk                   (0x1UL << PWR_PUCRA_PU5_Pos)            /*!< 0x00000020 */
19979 #define PWR_PUCRA_PU5                       PWR_PUCRA_PU5_Msk                       /*!< Apply pull-up for PA5  */
19980 #define PWR_PUCRA_PU6_Pos                   (6U)
19981 #define PWR_PUCRA_PU6_Msk                   (0x1UL << PWR_PUCRA_PU6_Pos)            /*!< 0x00000040 */
19982 #define PWR_PUCRA_PU6                       PWR_PUCRA_PU6_Msk                       /*!< Apply pull-up for PA6  */
19983 #define PWR_PUCRA_PU7_Pos                   (7U)
19984 #define PWR_PUCRA_PU7_Msk                   (0x1UL << PWR_PUCRA_PU7_Pos)            /*!< 0x00000080 */
19985 #define PWR_PUCRA_PU7                       PWR_PUCRA_PU7_Msk                       /*!< Apply pull-up for PA7  */
19986 #define PWR_PUCRA_PU8_Pos                   (8U)
19987 #define PWR_PUCRA_PU8_Msk                   (0x1UL << PWR_PUCRA_PU8_Pos)            /*!< 0x00000100 */
19988 #define PWR_PUCRA_PU8                       PWR_PUCRA_PU8_Msk                       /*!< Apply pull-up for PA8  */
19989 #define PWR_PUCRA_PU9_Pos                   (9U)
19990 #define PWR_PUCRA_PU9_Msk                   (0x1UL << PWR_PUCRA_PU9_Pos)            /*!< 0x00000200 */
19991 #define PWR_PUCRA_PU9                       PWR_PUCRA_PU9_Msk                       /*!< Apply pull-up for PA9  */
19992 #define PWR_PUCRA_PU10_Pos                  (10U)
19993 #define PWR_PUCRA_PU10_Msk                  (0x1UL << PWR_PUCRA_PU10_Pos)           /*!< 0x00000400 */
19994 #define PWR_PUCRA_PU10                      PWR_PUCRA_PU10_Msk                      /*!< Apply pull-up for PA10 */
19995 #define PWR_PUCRA_PU11_Pos                  (11U)
19996 #define PWR_PUCRA_PU11_Msk                  (0x1UL << PWR_PUCRA_PU11_Pos)           /*!< 0x00000800 */
19997 #define PWR_PUCRA_PU11                      PWR_PUCRA_PU11_Msk                      /*!< Apply pull-up for PA11 */
19998 #define PWR_PUCRA_PU12_Pos                  (12U)
19999 #define PWR_PUCRA_PU12_Msk                  (0x1UL << PWR_PUCRA_PU12_Pos)           /*!< 0x00001000 */
20000 #define PWR_PUCRA_PU12                      PWR_PUCRA_PU12_Msk                      /*!< Apply pull-up for PA12 */
20001 #define PWR_PUCRA_PU13_Pos                  (13U)
20002 #define PWR_PUCRA_PU13_Msk                  (0x1UL << PWR_PUCRA_PU13_Pos)           /*!< 0x00002000 */
20003 #define PWR_PUCRA_PU13                      PWR_PUCRA_PU13_Msk                      /*!< Apply pull-up for PA13 */
20004 #define PWR_PUCRA_PU15_Pos                  (15U)
20005 #define PWR_PUCRA_PU15_Msk                  (0x1UL << PWR_PUCRA_PU15_Pos)           /*!< 0x00008000 */
20006 #define PWR_PUCRA_PU15                      PWR_PUCRA_PU15_Msk                      /*!< Apply pull-up for PA15 */
20007 
20008 /********************  Bit definition for PWR_PDCRA register  *****************/
20009 #define PWR_PDCRA_PD0_Pos                   (0U)
20010 #define PWR_PDCRA_PD0_Msk                   (0x1UL << PWR_PDCRA_PD0_Pos)            /*!< 0x00000001 */
20011 #define PWR_PDCRA_PD0                       PWR_PDCRA_PD0_Msk                       /*!< Apply pull-down for PA0  */
20012 #define PWR_PDCRA_PD1_Pos                   (1U)
20013 #define PWR_PDCRA_PD1_Msk                   (0x1UL << PWR_PDCRA_PD1_Pos)            /*!< 0x00000002 */
20014 #define PWR_PDCRA_PD1                       PWR_PDCRA_PD1_Msk                       /*!< Apply pull-down for PA1  */
20015 #define PWR_PDCRA_PD2_Pos                   (2U)
20016 #define PWR_PDCRA_PD2_Msk                   (0x1UL << PWR_PDCRA_PD2_Pos)            /*!< 0x00000004 */
20017 #define PWR_PDCRA_PD2                       PWR_PDCRA_PD2_Msk                       /*!< Apply pull-down for PA2  */
20018 #define PWR_PDCRA_PD3_Pos                   (3U)
20019 #define PWR_PDCRA_PD3_Msk                   (0x1UL << PWR_PDCRA_PD3_Pos)            /*!< 0x00000008 */
20020 #define PWR_PDCRA_PD3                       PWR_PDCRA_PD3_Msk                       /*!< Apply pull-down for PA3  */
20021 #define PWR_PDCRA_PD4_Pos                   (4U)
20022 #define PWR_PDCRA_PD4_Msk                   (0x1UL << PWR_PDCRA_PD4_Pos)            /*!< 0x00000010 */
20023 #define PWR_PDCRA_PD4                       PWR_PDCRA_PD4_Msk                       /*!< Apply pull-down for PA4  */
20024 #define PWR_PDCRA_PD5_Pos                   (5U)
20025 #define PWR_PDCRA_PD5_Msk                   (0x1UL << PWR_PDCRA_PD5_Pos)            /*!< 0x00000020 */
20026 #define PWR_PDCRA_PD5                       PWR_PDCRA_PD5_Msk                       /*!< Apply pull-down for PA5  */
20027 #define PWR_PDCRA_PD6_Pos                   (6U)
20028 #define PWR_PDCRA_PD6_Msk                   (0x1UL << PWR_PDCRA_PD6_Pos)            /*!< 0x00000040 */
20029 #define PWR_PDCRA_PD6                       PWR_PDCRA_PD6_Msk                       /*!< Apply pull-down for PA6  */
20030 #define PWR_PDCRA_PD7_Pos                   (7U)
20031 #define PWR_PDCRA_PD7_Msk                   (0x1UL << PWR_PDCRA_PD7_Pos)            /*!< 0x00000080 */
20032 #define PWR_PDCRA_PD7                       PWR_PDCRA_PD7_Msk                       /*!< Apply pull-down for PA7  */
20033 #define PWR_PDCRA_PD8_Pos                   (8U)
20034 #define PWR_PDCRA_PD8_Msk                   (0x1UL << PWR_PDCRA_PD8_Pos)            /*!< 0x00000100 */
20035 #define PWR_PDCRA_PD8                       PWR_PDCRA_PD8_Msk                       /*!< Apply pull-down for PA8  */
20036 #define PWR_PDCRA_PD9_Pos                   (9U)
20037 #define PWR_PDCRA_PD9_Msk                   (0x1UL << PWR_PDCRA_PD9_Pos)            /*!< 0x00000200 */
20038 #define PWR_PDCRA_PD9                       PWR_PDCRA_PD9_Msk                       /*!< Apply pull-down for PA9  */
20039 #define PWR_PDCRA_PD10_Pos                  (10U)
20040 #define PWR_PDCRA_PD10_Msk                  (0x1UL << PWR_PDCRA_PD10_Pos)           /*!< 0x00000400 */
20041 #define PWR_PDCRA_PD10                      PWR_PDCRA_PD10_Msk                      /*!< Apply pull-down for PA10 */
20042 #define PWR_PDCRA_PD11_Pos                  (11U)
20043 #define PWR_PDCRA_PD11_Msk                  (0x1UL << PWR_PDCRA_PD11_Pos)           /*!< 0x00000800 */
20044 #define PWR_PDCRA_PD11                      PWR_PDCRA_PD11_Msk                      /*!< Apply pull-down for PA11 */
20045 #define PWR_PDCRA_PD12_Pos                  (12U)
20046 #define PWR_PDCRA_PD12_Msk                  (0x1UL << PWR_PDCRA_PD12_Pos)           /*!< 0x00001000 */
20047 #define PWR_PDCRA_PD12                      PWR_PDCRA_PD12_Msk                      /*!< Apply pull-down for PA12 */
20048 #define PWR_PDCRA_PD14_Pos                  (14U)
20049 #define PWR_PDCRA_PD14_Msk                  (0x1UL << PWR_PDCRA_PD14_Pos)           /*!< 0x00004000 */
20050 #define PWR_PDCRA_PD14                      PWR_PDCRA_PD14_Msk                      /*!< Apply pull-down for PA14 */
20051 
20052 /********************  Bit definition for PWR_PUCRB register  *****************/
20053 #define PWR_PUCRB_PU0_Pos                   (0U)
20054 #define PWR_PUCRB_PU0_Msk                   (0x1UL << PWR_PUCRB_PU0_Pos)            /*!< 0x00000001 */
20055 #define PWR_PUCRB_PU0                       PWR_PUCRB_PU0_Msk                       /*!< Apply pull-up for PB0  */
20056 #define PWR_PUCRB_PU1_Pos                   (1U)
20057 #define PWR_PUCRB_PU1_Msk                   (0x1UL << PWR_PUCRB_PU1_Pos)            /*!< 0x00000002 */
20058 #define PWR_PUCRB_PU1                       PWR_PUCRB_PU1_Msk                       /*!< Apply pull-up for PB1  */
20059 #define PWR_PUCRB_PU2_Pos                   (2U)
20060 #define PWR_PUCRB_PU2_Msk                   (0x1UL << PWR_PUCRB_PU2_Pos)            /*!< 0x00000004 */
20061 #define PWR_PUCRB_PU2                       PWR_PUCRB_PU2_Msk                       /*!< Apply pull-up for PB2  */
20062 #define PWR_PUCRB_PU3_Pos                   (3U)
20063 #define PWR_PUCRB_PU3_Msk                   (0x1UL << PWR_PUCRB_PU3_Pos)            /*!< 0x00000008 */
20064 #define PWR_PUCRB_PU3                       PWR_PUCRB_PU3_Msk                       /*!< Apply pull-up for PB3  */
20065 #define PWR_PUCRB_PU4_Pos                   (4U)
20066 #define PWR_PUCRB_PU4_Msk                   (0x1UL << PWR_PUCRB_PU4_Pos)            /*!< 0x00000010 */
20067 #define PWR_PUCRB_PU4                       PWR_PUCRB_PU4_Msk                       /*!< Apply pull-up for PB4  */
20068 #define PWR_PUCRB_PU5_Pos                   (5U)
20069 #define PWR_PUCRB_PU5_Msk                   (0x1UL << PWR_PUCRB_PU5_Pos)            /*!< 0x00000020 */
20070 #define PWR_PUCRB_PU5                       PWR_PUCRB_PU5_Msk                       /*!< Apply pull-up for PB5  */
20071 #define PWR_PUCRB_PU6_Pos                   (6U)
20072 #define PWR_PUCRB_PU6_Msk                   (0x1UL << PWR_PUCRB_PU6_Pos)            /*!< 0x00000040 */
20073 #define PWR_PUCRB_PU6                       PWR_PUCRB_PU6_Msk                       /*!< Apply pull-up for PB6  */
20074 #define PWR_PUCRB_PU7_Pos                   (7U)
20075 #define PWR_PUCRB_PU7_Msk                   (0x1UL << PWR_PUCRB_PU7_Pos)            /*!< 0x00000080 */
20076 #define PWR_PUCRB_PU7                       PWR_PUCRB_PU7_Msk                       /*!< Apply pull-up for PB7  */
20077 #define PWR_PUCRB_PU8_Pos                   (8U)
20078 #define PWR_PUCRB_PU8_Msk                   (0x1UL << PWR_PUCRB_PU8_Pos)            /*!< 0x00000100 */
20079 #define PWR_PUCRB_PU8                       PWR_PUCRB_PU8_Msk                       /*!< Apply pull-up for PB8  */
20080 #define PWR_PUCRB_PU9_Pos                   (9U)
20081 #define PWR_PUCRB_PU9_Msk                   (0x1UL << PWR_PUCRB_PU9_Pos)            /*!< 0x00000200 */
20082 #define PWR_PUCRB_PU9                       PWR_PUCRB_PU9_Msk                       /*!< Apply pull-up for PB9  */
20083 #define PWR_PUCRB_PU10_Pos                  (10U)
20084 #define PWR_PUCRB_PU10_Msk                  (0x1UL << PWR_PUCRB_PU10_Pos)           /*!< 0x00000400 */
20085 #define PWR_PUCRB_PU10                      PWR_PUCRB_PU10_Msk                      /*!< Apply pull-up for PB10 */
20086 #define PWR_PUCRB_PU11_Pos                  (11U)
20087 #define PWR_PUCRB_PU11_Msk                  (0x1UL << PWR_PUCRB_PU11_Pos)           /*!< 0x00000800 */
20088 #define PWR_PUCRB_PU11                      PWR_PUCRB_PU11_Msk                      /*!< Apply pull-up for PB11 */
20089 #define PWR_PUCRB_PU12_Pos                  (12U)
20090 #define PWR_PUCRB_PU12_Msk                  (0x1UL << PWR_PUCRB_PU12_Pos)           /*!< 0x00001000 */
20091 #define PWR_PUCRB_PU12                      PWR_PUCRB_PU12_Msk                      /*!< Apply pull-up for PB12 */
20092 #define PWR_PUCRB_PU13_Pos                  (13U)
20093 #define PWR_PUCRB_PU13_Msk                  (0x1UL << PWR_PUCRB_PU13_Pos)           /*!< 0x00002000 */
20094 #define PWR_PUCRB_PU13                      PWR_PUCRB_PU13_Msk                      /*!< Apply pull-up for PB13 */
20095 #define PWR_PUCRB_PU14_Pos                  (14U)
20096 #define PWR_PUCRB_PU14_Msk                  (0x1UL << PWR_PUCRB_PU14_Pos)           /*!< 0x00004000 */
20097 #define PWR_PUCRB_PU14                      PWR_PUCRB_PU14_Msk                      /*!< Apply pull-up for PB14 */
20098 #define PWR_PUCRB_PU15_Pos                  (15U)
20099 #define PWR_PUCRB_PU15_Msk                  (0x1UL << PWR_PUCRB_PU15_Pos)           /*!< 0x00008000 */
20100 #define PWR_PUCRB_PU15                      PWR_PUCRB_PU15_Msk                      /*!< Apply pull-up for PB15 */
20101 
20102 /********************  Bit definition for PWR_PDCRB register  *****************/
20103 #define PWR_PDCRB_PD0_Pos                   (0U)
20104 #define PWR_PDCRB_PD0_Msk                   (0x1UL << PWR_PDCRB_PD0_Pos)            /*!< 0x00000001 */
20105 #define PWR_PDCRB_PD0                       PWR_PDCRB_PD0_Msk                       /*!< Apply pull-down for PB0  */
20106 #define PWR_PDCRB_PD1_Pos                   (1U)
20107 #define PWR_PDCRB_PD1_Msk                   (0x1UL << PWR_PDCRB_PD1_Pos)            /*!< 0x00000002 */
20108 #define PWR_PDCRB_PD1                       PWR_PDCRB_PD1_Msk                       /*!< Apply pull-down for PB1  */
20109 #define PWR_PDCRB_PD2_Pos                   (2U)
20110 #define PWR_PDCRB_PD2_Msk                   (0x1UL << PWR_PDCRB_PD2_Pos)            /*!< 0x00000004 */
20111 #define PWR_PDCRB_PD2                       PWR_PDCRB_PD2_Msk                       /*!< Apply pull-down for PB2  */
20112 #define PWR_PDCRB_PD3_Pos                   (3U)
20113 #define PWR_PDCRB_PD3_Msk                   (0x1UL << PWR_PDCRB_PD3_Pos)            /*!< 0x00000008 */
20114 #define PWR_PDCRB_PD3                       PWR_PDCRB_PD3_Msk                       /*!< Apply pull-down for PB3  */
20115 #define PWR_PDCRB_PD5_Pos                   (5U)
20116 #define PWR_PDCRB_PD5_Msk                   (0x1UL << PWR_PDCRB_PD5_Pos)            /*!< 0x00000020 */
20117 #define PWR_PDCRB_PD5                       PWR_PDCRB_PD5_Msk                       /*!< Apply pull-down for PB5  */
20118 #define PWR_PDCRB_PD6_Pos                   (6U)
20119 #define PWR_PDCRB_PD6_Msk                   (0x1UL << PWR_PDCRB_PD6_Pos)            /*!< 0x00000040 */
20120 #define PWR_PDCRB_PD6                       PWR_PDCRB_PD6_Msk                       /*!< Apply pull-down for PB6  */
20121 #define PWR_PDCRB_PD7_Pos                   (7U)
20122 #define PWR_PDCRB_PD7_Msk                   (0x1UL << PWR_PDCRB_PD7_Pos)            /*!< 0x00000080 */
20123 #define PWR_PDCRB_PD7                       PWR_PDCRB_PD7_Msk                       /*!< Apply pull-down for PB7  */
20124 #define PWR_PDCRB_PD8_Pos                   (8U)
20125 #define PWR_PDCRB_PD8_Msk                   (0x1UL << PWR_PDCRB_PD8_Pos)            /*!< 0x00000100 */
20126 #define PWR_PDCRB_PD8                       PWR_PDCRB_PD8_Msk                       /*!< Apply pull-down for PB8  */
20127 #define PWR_PDCRB_PD9_Pos                   (9U)
20128 #define PWR_PDCRB_PD9_Msk                   (0x1UL << PWR_PDCRB_PD9_Pos)            /*!< 0x00000200 */
20129 #define PWR_PDCRB_PD9                       PWR_PDCRB_PD9_Msk                       /*!< Apply pull-down for PB9  */
20130 #define PWR_PDCRB_PD10_Pos                  (10U)
20131 #define PWR_PDCRB_PD10_Msk                  (0x1UL << PWR_PDCRB_PD10_Pos)           /*!< 0x00000400 */
20132 #define PWR_PDCRB_PD10                      PWR_PDCRB_PD10_Msk                      /*!< Apply pull-down for PB10 */
20133 #define PWR_PDCRB_PD11_Pos                  (11U)
20134 #define PWR_PDCRB_PD11_Msk                  (0x1UL << PWR_PDCRB_PD11_Pos)           /*!< 0x00000800 */
20135 #define PWR_PDCRB_PD11                      PWR_PDCRB_PD11_Msk                      /*!< Apply pull-down for PB11 */
20136 #define PWR_PDCRB_PD12_Pos                  (12U)
20137 #define PWR_PDCRB_PD12_Msk                  (0x1UL << PWR_PDCRB_PD12_Pos)           /*!< 0x00001000 */
20138 #define PWR_PDCRB_PD12                      PWR_PDCRB_PD12_Msk                      /*!< Apply pull-down for PB12 */
20139 #define PWR_PDCRB_PD13_Pos                  (13U)
20140 #define PWR_PDCRB_PD13_Msk                  (0x1UL << PWR_PDCRB_PD13_Pos)           /*!< 0x00002000 */
20141 #define PWR_PDCRB_PD13                      PWR_PDCRB_PD13_Msk                      /*!< Apply pull-down for PB13 */
20142 #define PWR_PDCRB_PD14_Pos                  (14U)
20143 #define PWR_PDCRB_PD14_Msk                  (0x1UL << PWR_PDCRB_PD14_Pos)           /*!< 0x00004000 */
20144 #define PWR_PDCRB_PD14                      PWR_PDCRB_PD14_Msk                      /*!< Apply pull-down for PB14 */
20145 #define PWR_PDCRB_PD15_Pos                  (15U)
20146 #define PWR_PDCRB_PD15_Msk                  (0x1UL << PWR_PDCRB_PD15_Pos)           /*!< 0x00008000 */
20147 #define PWR_PDCRB_PD15                      PWR_PDCRB_PD15_Msk                      /*!< Apply pull-down for PB15 */
20148 
20149 /********************  Bit definition for PWR_PUCRC register  *****************/
20150 #define PWR_PUCRC_PU0_Pos                   (0U)
20151 #define PWR_PUCRC_PU0_Msk                   (0x1UL << PWR_PUCRC_PU0_Pos)            /*!< 0x00000001 */
20152 #define PWR_PUCRC_PU0                       PWR_PUCRC_PU0_Msk                       /*!< Apply pull-up for PC0  */
20153 #define PWR_PUCRC_PU1_Pos                   (1U)
20154 #define PWR_PUCRC_PU1_Msk                   (0x1UL << PWR_PUCRC_PU1_Pos)            /*!< 0x00000002 */
20155 #define PWR_PUCRC_PU1                       PWR_PUCRC_PU1_Msk                       /*!< Apply pull-up for PC1  */
20156 #define PWR_PUCRC_PU2_Pos                   (2U)
20157 #define PWR_PUCRC_PU2_Msk                   (0x1UL << PWR_PUCRC_PU2_Pos)            /*!< 0x00000004 */
20158 #define PWR_PUCRC_PU2                       PWR_PUCRC_PU2_Msk                       /*!< Apply pull-up for PC2  */
20159 #define PWR_PUCRC_PU3_Pos                   (3U)
20160 #define PWR_PUCRC_PU3_Msk                   (0x1UL << PWR_PUCRC_PU3_Pos)            /*!< 0x00000008 */
20161 #define PWR_PUCRC_PU3                       PWR_PUCRC_PU3_Msk                       /*!< Apply pull-up for PC3  */
20162 #define PWR_PUCRC_PU4_Pos                   (4U)
20163 #define PWR_PUCRC_PU4_Msk                   (0x1UL << PWR_PUCRC_PU4_Pos)            /*!< 0x00000010 */
20164 #define PWR_PUCRC_PU4                       PWR_PUCRC_PU4_Msk                       /*!< Apply pull-up for PC4  */
20165 #define PWR_PUCRC_PU5_Pos                   (5U)
20166 #define PWR_PUCRC_PU5_Msk                   (0x1UL << PWR_PUCRC_PU5_Pos)            /*!< 0x00000020 */
20167 #define PWR_PUCRC_PU5                       PWR_PUCRC_PU5_Msk                       /*!< Apply pull-up for PC5  */
20168 #define PWR_PUCRC_PU6_Pos                   (6U)
20169 #define PWR_PUCRC_PU6_Msk                   (0x1UL << PWR_PUCRC_PU6_Pos)            /*!< 0x00000040 */
20170 #define PWR_PUCRC_PU6                       PWR_PUCRC_PU6_Msk                       /*!< Apply pull-up for PC6  */
20171 #define PWR_PUCRC_PU7_Pos                   (7U)
20172 #define PWR_PUCRC_PU7_Msk                   (0x1UL << PWR_PUCRC_PU7_Pos)            /*!< 0x00000080 */
20173 #define PWR_PUCRC_PU7                       PWR_PUCRC_PU7_Msk                       /*!< Apply pull-up for PC7  */
20174 #define PWR_PUCRC_PU8_Pos                   (8U)
20175 #define PWR_PUCRC_PU8_Msk                   (0x1UL << PWR_PUCRC_PU8_Pos)            /*!< 0x00000100 */
20176 #define PWR_PUCRC_PU8                       PWR_PUCRC_PU8_Msk                       /*!< Apply pull-up for PC8  */
20177 #define PWR_PUCRC_PU9_Pos                   (9U)
20178 #define PWR_PUCRC_PU9_Msk                   (0x1UL << PWR_PUCRC_PU9_Pos)            /*!< 0x00000200 */
20179 #define PWR_PUCRC_PU9                       PWR_PUCRC_PU9_Msk                       /*!< Apply pull-up for PC9  */
20180 #define PWR_PUCRC_PU10_Pos                  (10U)
20181 #define PWR_PUCRC_PU10_Msk                  (0x1UL << PWR_PUCRC_PU10_Pos)           /*!< 0x00000400 */
20182 #define PWR_PUCRC_PU10                      PWR_PUCRC_PU10_Msk                      /*!< Apply pull-up for PC10 */
20183 #define PWR_PUCRC_PU11_Pos                  (11U)
20184 #define PWR_PUCRC_PU11_Msk                  (0x1UL << PWR_PUCRC_PU11_Pos)           /*!< 0x00000800 */
20185 #define PWR_PUCRC_PU11                      PWR_PUCRC_PU11_Msk                      /*!< Apply pull-up for PC11 */
20186 #define PWR_PUCRC_PU12_Pos                  (12U)
20187 #define PWR_PUCRC_PU12_Msk                  (0x1UL << PWR_PUCRC_PU12_Pos)           /*!< 0x00001000 */
20188 #define PWR_PUCRC_PU12                      PWR_PUCRC_PU12_Msk                      /*!< Apply pull-up for PC12 */
20189 #define PWR_PUCRC_PU13_Pos                  (13U)
20190 #define PWR_PUCRC_PU13_Msk                  (0x1UL << PWR_PUCRC_PU13_Pos)           /*!< 0x00002000 */
20191 #define PWR_PUCRC_PU13                      PWR_PUCRC_PU13_Msk                      /*!< Apply pull-up for PC13 */
20192 #define PWR_PUCRC_PU14_Pos                  (14U)
20193 #define PWR_PUCRC_PU14_Msk                  (0x1UL << PWR_PUCRC_PU14_Pos)           /*!< 0x00004000 */
20194 #define PWR_PUCRC_PU14                      PWR_PUCRC_PU14_Msk                      /*!< Apply pull-up for PC14 */
20195 #define PWR_PUCRC_PU15_Pos                  (15U)
20196 #define PWR_PUCRC_PU15_Msk                  (0x1UL << PWR_PUCRC_PU15_Pos)           /*!< 0x00008000 */
20197 #define PWR_PUCRC_PU15                      PWR_PUCRC_PU15_Msk                      /*!< Apply pull-up for PC15 */
20198 
20199 /********************  Bit definition for PWR_PDCRC register  *****************/
20200 #define PWR_PDCRC_PD0_Pos                   (0U)
20201 #define PWR_PDCRC_PD0_Msk                   (0x1UL << PWR_PDCRC_PD0_Pos)            /*!< 0x00000001 */
20202 #define PWR_PDCRC_PD0                       PWR_PDCRC_PD0_Msk                       /*!< Apply pull-down for PC0  */
20203 #define PWR_PDCRC_PD1_Pos                   (1U)
20204 #define PWR_PDCRC_PD1_Msk                   (0x1UL << PWR_PDCRC_PD1_Pos)            /*!< 0x00000002 */
20205 #define PWR_PDCRC_PD1                       PWR_PDCRC_PD1_Msk                       /*!< Apply pull-down for PC1  */
20206 #define PWR_PDCRC_PD2_Pos                   (2U)
20207 #define PWR_PDCRC_PD2_Msk                   (0x1UL << PWR_PDCRC_PD2_Pos)            /*!< 0x00000004 */
20208 #define PWR_PDCRC_PD2                       PWR_PDCRC_PD2_Msk                       /*!< Apply pull-down for PC2  */
20209 #define PWR_PDCRC_PD3_Pos                   (3U)
20210 #define PWR_PDCRC_PD3_Msk                   (0x1UL << PWR_PDCRC_PD3_Pos)            /*!< 0x00000008 */
20211 #define PWR_PDCRC_PD3                       PWR_PDCRC_PD3_Msk                       /*!< Apply pull-down for PC3  */
20212 #define PWR_PDCRC_PD4_Pos                   (4U)
20213 #define PWR_PDCRC_PD4_Msk                   (0x1UL << PWR_PDCRC_PD4_Pos)            /*!< 0x00000010 */
20214 #define PWR_PDCRC_PD4                       PWR_PDCRC_PD4_Msk                       /*!< Apply pull-down for PC4  */
20215 #define PWR_PDCRC_PD5_Pos                   (5U)
20216 #define PWR_PDCRC_PD5_Msk                   (0x1UL << PWR_PDCRC_PD5_Pos)            /*!< 0x00000020 */
20217 #define PWR_PDCRC_PD5                       PWR_PDCRC_PD5_Msk                       /*!< Apply pull-down for PC5  */
20218 #define PWR_PDCRC_PD6_Pos                   (6U)
20219 #define PWR_PDCRC_PD6_Msk                   (0x1UL << PWR_PDCRC_PD6_Pos)            /*!< 0x00000040 */
20220 #define PWR_PDCRC_PD6                       PWR_PDCRC_PD6_Msk                       /*!< Apply pull-down for PC6  */
20221 #define PWR_PDCRC_PD7_Pos                   (7U)
20222 #define PWR_PDCRC_PD7_Msk                   (0x1UL << PWR_PDCRC_PD7_Pos)            /*!< 0x00000080 */
20223 #define PWR_PDCRC_PD7                       PWR_PDCRC_PD7_Msk                       /*!< Apply pull-down for PC7  */
20224 #define PWR_PDCRC_PD8_Pos                   (8U)
20225 #define PWR_PDCRC_PD8_Msk                   (0x1UL << PWR_PDCRC_PD8_Pos)            /*!< 0x00000100 */
20226 #define PWR_PDCRC_PD8                       PWR_PDCRC_PD8_Msk                       /*!< Apply pull-down for PC8  */
20227 #define PWR_PDCRC_PD9_Pos                   (9U)
20228 #define PWR_PDCRC_PD9_Msk                   (0x1UL << PWR_PDCRC_PD9_Pos)            /*!< 0x00000200 */
20229 #define PWR_PDCRC_PD9                       PWR_PDCRC_PD9_Msk                       /*!< Apply pull-down for PC9  */
20230 #define PWR_PDCRC_PD10_Pos                  (10U)
20231 #define PWR_PDCRC_PD10_Msk                  (0x1UL << PWR_PDCRC_PD10_Pos)           /*!< 0x00000400 */
20232 #define PWR_PDCRC_PD10                      PWR_PDCRC_PD10_Msk                      /*!< Apply pull-down for PC10 */
20233 #define PWR_PDCRC_PD11_Pos                  (11U)
20234 #define PWR_PDCRC_PD11_Msk                  (0x1UL << PWR_PDCRC_PD11_Pos)           /*!< 0x00000800 */
20235 #define PWR_PDCRC_PD11                      PWR_PDCRC_PD11_Msk                      /*!< Apply pull-down for PC11 */
20236 #define PWR_PDCRC_PD12_Pos                  (12U)
20237 #define PWR_PDCRC_PD12_Msk                  (0x1UL << PWR_PDCRC_PD12_Pos)           /*!< 0x00001000 */
20238 #define PWR_PDCRC_PD12                      PWR_PDCRC_PD12_Msk                      /*!< Apply pull-down for PC12 */
20239 #define PWR_PDCRC_PD13_Pos                  (13U)
20240 #define PWR_PDCRC_PD13_Msk                  (0x1UL << PWR_PDCRC_PD13_Pos)           /*!< 0x00002000 */
20241 #define PWR_PDCRC_PD13                      PWR_PDCRC_PD13_Msk                      /*!< Apply pull-down for PC13 */
20242 #define PWR_PDCRC_PD14_Pos                  (14U)
20243 #define PWR_PDCRC_PD14_Msk                  (0x1UL << PWR_PDCRC_PD14_Pos)           /*!< 0x00004000 */
20244 #define PWR_PDCRC_PD14                      PWR_PDCRC_PD14_Msk                      /*!< Apply pull-down for PC14 */
20245 #define PWR_PDCRC_PD15_Pos                  (15U)
20246 #define PWR_PDCRC_PD15_Msk                  (0x1UL << PWR_PDCRC_PD15_Pos)           /*!< 0x00008000 */
20247 #define PWR_PDCRC_PD15                      PWR_PDCRC_PD15_Msk                      /*!< Apply pull-down for PC15 */
20248 
20249 /********************  Bit definition for PWR_PUCRD register  *****************/
20250 #define PWR_PUCRD_PU0_Pos                   (0U)
20251 #define PWR_PUCRD_PU0_Msk                   (0x1UL << PWR_PUCRD_PU0_Pos)            /*!< 0x00000001 */
20252 #define PWR_PUCRD_PU0                       PWR_PUCRD_PU0_Msk                       /*!< Apply pull-up for PD0  */
20253 #define PWR_PUCRD_PU1_Pos                   (1U)
20254 #define PWR_PUCRD_PU1_Msk                   (0x1UL << PWR_PUCRD_PU1_Pos)            /*!< 0x00000002 */
20255 #define PWR_PUCRD_PU1                       PWR_PUCRD_PU1_Msk                       /*!< Apply pull-up for PD1  */
20256 #define PWR_PUCRD_PU2_Pos                   (2U)
20257 #define PWR_PUCRD_PU2_Msk                   (0x1UL << PWR_PUCRD_PU2_Pos)            /*!< 0x00000004 */
20258 #define PWR_PUCRD_PU2                       PWR_PUCRD_PU2_Msk                       /*!< Apply pull-up for PD2  */
20259 #define PWR_PUCRD_PU3_Pos                   (3U)
20260 #define PWR_PUCRD_PU3_Msk                   (0x1UL << PWR_PUCRD_PU3_Pos)            /*!< 0x00000008 */
20261 #define PWR_PUCRD_PU3                       PWR_PUCRD_PU3_Msk                       /*!< Apply pull-up for PD3  */
20262 #define PWR_PUCRD_PU4_Pos                   (4U)
20263 #define PWR_PUCRD_PU4_Msk                   (0x1UL << PWR_PUCRD_PU4_Pos)            /*!< 0x00000010 */
20264 #define PWR_PUCRD_PU4                       PWR_PUCRD_PU4_Msk                       /*!< Apply pull-up for PD4  */
20265 #define PWR_PUCRD_PU5_Pos                   (5U)
20266 #define PWR_PUCRD_PU5_Msk                   (0x1UL << PWR_PUCRD_PU5_Pos)            /*!< 0x00000020 */
20267 #define PWR_PUCRD_PU5                       PWR_PUCRD_PU5_Msk                       /*!< Apply pull-up for PD5  */
20268 #define PWR_PUCRD_PU6_Pos                   (6U)
20269 #define PWR_PUCRD_PU6_Msk                   (0x1UL << PWR_PUCRD_PU6_Pos)            /*!< 0x00000040 */
20270 #define PWR_PUCRD_PU6                       PWR_PUCRD_PU6_Msk                       /*!< Apply pull-up for PD6  */
20271 #define PWR_PUCRD_PU7_Pos                   (7U)
20272 #define PWR_PUCRD_PU7_Msk                   (0x1UL << PWR_PUCRD_PU7_Pos)            /*!< 0x00000080 */
20273 #define PWR_PUCRD_PU7                       PWR_PUCRD_PU7_Msk                       /*!< Apply pull-up for PD7  */
20274 #define PWR_PUCRD_PU8_Pos                   (8U)
20275 #define PWR_PUCRD_PU8_Msk                   (0x1UL << PWR_PUCRD_PU8_Pos)            /*!< 0x00000100 */
20276 #define PWR_PUCRD_PU8                       PWR_PUCRD_PU8_Msk                       /*!< Apply pull-up for PD8  */
20277 #define PWR_PUCRD_PU9_Pos                   (9U)
20278 #define PWR_PUCRD_PU9_Msk                   (0x1UL << PWR_PUCRD_PU9_Pos)            /*!< 0x00000200 */
20279 #define PWR_PUCRD_PU9                       PWR_PUCRD_PU9_Msk                       /*!< Apply pull-up for PD9  */
20280 #define PWR_PUCRD_PU10_Pos                  (10U)
20281 #define PWR_PUCRD_PU10_Msk                  (0x1UL << PWR_PUCRD_PU10_Pos)           /*!< 0x00000400 */
20282 #define PWR_PUCRD_PU10                      PWR_PUCRD_PU10_Msk                      /*!< Apply pull-up for PD10 */
20283 #define PWR_PUCRD_PU11_Pos                  (11U)
20284 #define PWR_PUCRD_PU11_Msk                  (0x1UL << PWR_PUCRD_PU11_Pos)           /*!< 0x00000800 */
20285 #define PWR_PUCRD_PU11                      PWR_PUCRD_PU11_Msk                      /*!< Apply pull-up for PD11 */
20286 #define PWR_PUCRD_PU12_Pos                  (12U)
20287 #define PWR_PUCRD_PU12_Msk                  (0x1UL << PWR_PUCRD_PU12_Pos)           /*!< 0x00001000 */
20288 #define PWR_PUCRD_PU12                      PWR_PUCRD_PU12_Msk                      /*!< Apply pull-up for PD12 */
20289 #define PWR_PUCRD_PU13_Pos                  (13U)
20290 #define PWR_PUCRD_PU13_Msk                  (0x1UL << PWR_PUCRD_PU13_Pos)           /*!< 0x00002000 */
20291 #define PWR_PUCRD_PU13                      PWR_PUCRD_PU13_Msk                      /*!< Apply pull-up for PD13 */
20292 #define PWR_PUCRD_PU14_Pos                  (14U)
20293 #define PWR_PUCRD_PU14_Msk                  (0x1UL << PWR_PUCRD_PU14_Pos)           /*!< 0x00004000 */
20294 #define PWR_PUCRD_PU14                      PWR_PUCRD_PU14_Msk                      /*!< Apply pull-up for PD14 */
20295 #define PWR_PUCRD_PU15_Pos                  (15U)
20296 #define PWR_PUCRD_PU15_Msk                  (0x1UL << PWR_PUCRD_PU15_Pos)           /*!< 0x00008000 */
20297 #define PWR_PUCRD_PU15                      PWR_PUCRD_PU15_Msk                      /*!< Apply pull-up for PD15 */
20298 
20299 /********************  Bit definition for PWR_PDCRD register  *****************/
20300 #define PWR_PDCRD_PD0_Pos                   (0U)
20301 #define PWR_PDCRD_PD0_Msk                   (0x1UL << PWR_PDCRD_PD0_Pos)            /*!< 0x00000001 */
20302 #define PWR_PDCRD_PD0                       PWR_PDCRD_PD0_Msk                       /*!< Apply pull-down for PD0  */
20303 #define PWR_PDCRD_PD1_Pos                   (1U)
20304 #define PWR_PDCRD_PD1_Msk                   (0x1UL << PWR_PDCRD_PD1_Pos)            /*!< 0x00000002 */
20305 #define PWR_PDCRD_PD1                       PWR_PDCRD_PD1_Msk                       /*!< Apply pull-down for PD1  */
20306 #define PWR_PDCRD_PD2_Pos                   (2U)
20307 #define PWR_PDCRD_PD2_Msk                   (0x1UL << PWR_PDCRD_PD2_Pos)            /*!< 0x00000004 */
20308 #define PWR_PDCRD_PD2                       PWR_PDCRD_PD2_Msk                       /*!< Apply pull-down for PD2  */
20309 #define PWR_PDCRD_PD3_Pos                   (3U)
20310 #define PWR_PDCRD_PD3_Msk                   (0x1UL << PWR_PDCRD_PD3_Pos)            /*!< 0x00000008 */
20311 #define PWR_PDCRD_PD3                       PWR_PDCRD_PD3_Msk                       /*!< Apply pull-down for PD3  */
20312 #define PWR_PDCRD_PD4_Pos                   (4U)
20313 #define PWR_PDCRD_PD4_Msk                   (0x1UL << PWR_PDCRD_PD4_Pos)            /*!< 0x00000010 */
20314 #define PWR_PDCRD_PD4                       PWR_PDCRD_PD4_Msk                       /*!< Apply pull-down for PD4  */
20315 #define PWR_PDCRD_PD5_Pos                   (5U)
20316 #define PWR_PDCRD_PD5_Msk                   (0x1UL << PWR_PDCRD_PD5_Pos)            /*!< 0x00000020 */
20317 #define PWR_PDCRD_PD5                       PWR_PDCRD_PD5_Msk                       /*!< Apply pull-down for PD5  */
20318 #define PWR_PDCRD_PD6_Pos                   (6U)
20319 #define PWR_PDCRD_PD6_Msk                   (0x1UL << PWR_PDCRD_PD6_Pos)            /*!< 0x00000040 */
20320 #define PWR_PDCRD_PD6                       PWR_PDCRD_PD6_Msk                       /*!< Apply pull-down for PD6  */
20321 #define PWR_PDCRD_PD7_Pos                   (7U)
20322 #define PWR_PDCRD_PD7_Msk                   (0x1UL << PWR_PDCRD_PD7_Pos)            /*!< 0x00000080 */
20323 #define PWR_PDCRD_PD7                       PWR_PDCRD_PD7_Msk                       /*!< Apply pull-down for PD7  */
20324 #define PWR_PDCRD_PD8_Pos                   (8U)
20325 #define PWR_PDCRD_PD8_Msk                   (0x1UL << PWR_PDCRD_PD8_Pos)            /*!< 0x00000100 */
20326 #define PWR_PDCRD_PD8                       PWR_PDCRD_PD8_Msk                       /*!< Apply pull-down for PD8  */
20327 #define PWR_PDCRD_PD9_Pos                   (9U)
20328 #define PWR_PDCRD_PD9_Msk                   (0x1UL << PWR_PDCRD_PD9_Pos)            /*!< 0x00000200 */
20329 #define PWR_PDCRD_PD9                       PWR_PDCRD_PD9_Msk                       /*!< Apply pull-down for PD9  */
20330 #define PWR_PDCRD_PD10_Pos                  (10U)
20331 #define PWR_PDCRD_PD10_Msk                  (0x1UL << PWR_PDCRD_PD10_Pos)           /*!< 0x00000400 */
20332 #define PWR_PDCRD_PD10                      PWR_PDCRD_PD10_Msk                      /*!< Apply pull-down for PD10 */
20333 #define PWR_PDCRD_PD11_Pos                  (11U)
20334 #define PWR_PDCRD_PD11_Msk                  (0x1UL << PWR_PDCRD_PD11_Pos)           /*!< 0x00000800 */
20335 #define PWR_PDCRD_PD11                      PWR_PDCRD_PD11_Msk                      /*!< Apply pull-down for PD11 */
20336 #define PWR_PDCRD_PD12_Pos                  (12U)
20337 #define PWR_PDCRD_PD12_Msk                  (0x1UL << PWR_PDCRD_PD12_Pos)           /*!< 0x00001000 */
20338 #define PWR_PDCRD_PD12                      PWR_PDCRD_PD12_Msk                      /*!< Apply pull-down for PD12 */
20339 #define PWR_PDCRD_PD13_Pos                  (13U)
20340 #define PWR_PDCRD_PD13_Msk                  (0x1UL << PWR_PDCRD_PD13_Pos)           /*!< 0x00002000 */
20341 #define PWR_PDCRD_PD13                      PWR_PDCRD_PD13_Msk                      /*!< Apply pull-down for PD13 */
20342 #define PWR_PDCRD_PD14_Pos                  (14U)
20343 #define PWR_PDCRD_PD14_Msk                  (0x1UL << PWR_PDCRD_PD14_Pos)           /*!< 0x00004000 */
20344 #define PWR_PDCRD_PD14                      PWR_PDCRD_PD14_Msk                      /*!< Apply pull-down for PD14 */
20345 #define PWR_PDCRD_PD15_Pos                  (15U)
20346 #define PWR_PDCRD_PD15_Msk                  (0x1UL << PWR_PDCRD_PD15_Pos)           /*!< 0x00008000 */
20347 #define PWR_PDCRD_PD15                      PWR_PDCRD_PD15_Msk                      /*!< Apply pull-down for PD15 */
20348 
20349 /********************  Bit definition for PWR_PUCRE register  *****************/
20350 #define PWR_PUCRE_PU0_Pos                   (0U)
20351 #define PWR_PUCRE_PU0_Msk                   (0x1UL << PWR_PUCRE_PU0_Pos)            /*!< 0x00000001 */
20352 #define PWR_PUCRE_PU0                       PWR_PUCRE_PU0_Msk                       /*!< Apply pull-up for PE0  */
20353 #define PWR_PUCRE_PU1_Pos                   (1U)
20354 #define PWR_PUCRE_PU1_Msk                   (0x1UL << PWR_PUCRE_PU1_Pos)            /*!< 0x00000002 */
20355 #define PWR_PUCRE_PU1                       PWR_PUCRE_PU1_Msk                       /*!< Apply pull-up for PE1  */
20356 #define PWR_PUCRE_PU2_Pos                   (2U)
20357 #define PWR_PUCRE_PU2_Msk                   (0x1UL << PWR_PUCRE_PU2_Pos)            /*!< 0x00000004 */
20358 #define PWR_PUCRE_PU2                       PWR_PUCRE_PU2_Msk                       /*!< Apply pull-up for PE2  */
20359 #define PWR_PUCRE_PU3_Pos                   (3U)
20360 #define PWR_PUCRE_PU3_Msk                   (0x1UL << PWR_PUCRE_PU3_Pos)            /*!< 0x00000008 */
20361 #define PWR_PUCRE_PU3                       PWR_PUCRE_PU3_Msk                       /*!< Apply pull-up for PE3  */
20362 #define PWR_PUCRE_PU4_Pos                   (4U)
20363 #define PWR_PUCRE_PU4_Msk                   (0x1UL << PWR_PUCRE_PU4_Pos)            /*!< 0x00000010 */
20364 #define PWR_PUCRE_PU4                       PWR_PUCRE_PU4_Msk                       /*!< Apply pull-up for PE4  */
20365 #define PWR_PUCRE_PU5_Pos                   (5U)
20366 #define PWR_PUCRE_PU5_Msk                   (0x1UL << PWR_PUCRE_PU5_Pos)            /*!< 0x00000020 */
20367 #define PWR_PUCRE_PU5                       PWR_PUCRE_PU5_Msk                       /*!< Apply pull-up for PE5  */
20368 #define PWR_PUCRE_PU6_Pos                   (6U)
20369 #define PWR_PUCRE_PU6_Msk                   (0x1UL << PWR_PUCRE_PU6_Pos)            /*!< 0x00000040 */
20370 #define PWR_PUCRE_PU6                       PWR_PUCRE_PU6_Msk                       /*!< Apply pull-up for PE6  */
20371 #define PWR_PUCRE_PU7_Pos                   (7U)
20372 #define PWR_PUCRE_PU7_Msk                   (0x1UL << PWR_PUCRE_PU7_Pos)            /*!< 0x00000080 */
20373 #define PWR_PUCRE_PU7                       PWR_PUCRE_PU7_Msk                       /*!< Apply pull-up for PE7  */
20374 #define PWR_PUCRE_PU8_Pos                   (8U)
20375 #define PWR_PUCRE_PU8_Msk                   (0x1UL << PWR_PUCRE_PU8_Pos)            /*!< 0x00000100 */
20376 #define PWR_PUCRE_PU8                       PWR_PUCRE_PU8_Msk                       /*!< Apply pull-up for PE8  */
20377 #define PWR_PUCRE_PU9_Pos                   (9U)
20378 #define PWR_PUCRE_PU9_Msk                   (0x1UL << PWR_PUCRE_PU9_Pos)            /*!< 0x00000200 */
20379 #define PWR_PUCRE_PU9                       PWR_PUCRE_PU9_Msk                       /*!< Apply pull-up for PE9  */
20380 #define PWR_PUCRE_PU10_Pos                  (10U)
20381 #define PWR_PUCRE_PU10_Msk                  (0x1UL << PWR_PUCRE_PU10_Pos)           /*!< 0x00000400 */
20382 #define PWR_PUCRE_PU10                      PWR_PUCRE_PU10_Msk                      /*!< Apply pull-up for PE10 */
20383 #define PWR_PUCRE_PU11_Pos                  (11U)
20384 #define PWR_PUCRE_PU11_Msk                  (0x1UL << PWR_PUCRE_PU11_Pos)           /*!< 0x00000800 */
20385 #define PWR_PUCRE_PU11                      PWR_PUCRE_PU11_Msk                      /*!< Apply pull-up for PE11 */
20386 #define PWR_PUCRE_PU12_Pos                  (12U)
20387 #define PWR_PUCRE_PU12_Msk                  (0x1UL << PWR_PUCRE_PU12_Pos)           /*!< 0x00001000 */
20388 #define PWR_PUCRE_PU12                      PWR_PUCRE_PU12_Msk                      /*!< Apply pull-up for PE12 */
20389 #define PWR_PUCRE_PU13_Pos                  (13U)
20390 #define PWR_PUCRE_PU13_Msk                  (0x1UL << PWR_PUCRE_PU13_Pos)           /*!< 0x00002000 */
20391 #define PWR_PUCRE_PU13                      PWR_PUCRE_PU13_Msk                      /*!< Apply pull-up for PE13 */
20392 #define PWR_PUCRE_PU14_Pos                  (14U)
20393 #define PWR_PUCRE_PU14_Msk                  (0x1UL << PWR_PUCRE_PU14_Pos)           /*!< 0x00004000 */
20394 #define PWR_PUCRE_PU14                      PWR_PUCRE_PU14_Msk                      /*!< Apply pull-up for PE14 */
20395 #define PWR_PUCRE_PU15_Pos                  (15U)
20396 #define PWR_PUCRE_PU15_Msk                  (0x1UL << PWR_PUCRE_PU15_Pos)           /*!< 0x00008000 */
20397 #define PWR_PUCRE_PU15                      PWR_PUCRE_PU15_Msk                      /*!< Apply pull-up for PE15 */
20398 
20399 /********************  Bit definition for PWR_PDCRE register  *****************/
20400 #define PWR_PDCRE_PD0_Pos                   (0U)
20401 #define PWR_PDCRE_PD0_Msk                   (0x1UL << PWR_PDCRE_PD0_Pos)            /*!< 0x00000001 */
20402 #define PWR_PDCRE_PD0                       PWR_PDCRE_PD0_Msk                       /*!< Apply pull-down for PE0  */
20403 #define PWR_PDCRE_PD1_Pos                   (1U)
20404 #define PWR_PDCRE_PD1_Msk                   (0x1UL << PWR_PDCRE_PD1_Pos)            /*!< 0x00000002 */
20405 #define PWR_PDCRE_PD1                       PWR_PDCRE_PD1_Msk                       /*!< Apply pull-down for PE1  */
20406 #define PWR_PDCRE_PD2_Pos                   (2U)
20407 #define PWR_PDCRE_PD2_Msk                   (0x1UL << PWR_PDCRE_PD2_Pos)            /*!< 0x00000004 */
20408 #define PWR_PDCRE_PD2                       PWR_PDCRE_PD2_Msk                       /*!< Apply pull-down for PE2  */
20409 #define PWR_PDCRE_PD3_Pos                   (3U)
20410 #define PWR_PDCRE_PD3_Msk                   (0x1UL << PWR_PDCRE_PD3_Pos)            /*!< 0x00000008 */
20411 #define PWR_PDCRE_PD3                       PWR_PDCRE_PD3_Msk                       /*!< Apply pull-down for PE3  */
20412 #define PWR_PDCRE_PD4_Pos                   (4U)
20413 #define PWR_PDCRE_PD4_Msk                   (0x1UL << PWR_PDCRE_PD4_Pos)            /*!< 0x00000010 */
20414 #define PWR_PDCRE_PD4                       PWR_PDCRE_PD4_Msk                       /*!< Apply pull-down for PE4  */
20415 #define PWR_PDCRE_PD5_Pos                   (5U)
20416 #define PWR_PDCRE_PD5_Msk                   (0x1UL << PWR_PDCRE_PD5_Pos)            /*!< 0x00000020 */
20417 #define PWR_PDCRE_PD5                       PWR_PDCRE_PD5_Msk                       /*!< Apply pull-down for PE5  */
20418 #define PWR_PDCRE_PD6_Pos                   (6U)
20419 #define PWR_PDCRE_PD6_Msk                   (0x1UL << PWR_PDCRE_PD6_Pos)            /*!< 0x00000040 */
20420 #define PWR_PDCRE_PD6                       PWR_PDCRE_PD6_Msk                       /*!< Apply pull-down for PE6  */
20421 #define PWR_PDCRE_PD7_Pos                   (7U)
20422 #define PWR_PDCRE_PD7_Msk                   (0x1UL << PWR_PDCRE_PD7_Pos)            /*!< 0x00000080 */
20423 #define PWR_PDCRE_PD7                       PWR_PDCRE_PD7_Msk                       /*!< Apply pull-down for PE7  */
20424 #define PWR_PDCRE_PD8_Pos                   (8U)
20425 #define PWR_PDCRE_PD8_Msk                   (0x1UL << PWR_PDCRE_PD8_Pos)            /*!< 0x00000100 */
20426 #define PWR_PDCRE_PD8                       PWR_PDCRE_PD8_Msk                       /*!< Apply pull-down for PE8  */
20427 #define PWR_PDCRE_PD9_Pos                   (9U)
20428 #define PWR_PDCRE_PD9_Msk                   (0x1UL << PWR_PDCRE_PD9_Pos)            /*!< 0x00000200 */
20429 #define PWR_PDCRE_PD9                       PWR_PDCRE_PD9_Msk                       /*!< Apply pull-down for PE9  */
20430 #define PWR_PDCRE_PD10_Pos                  (10U)
20431 #define PWR_PDCRE_PD10_Msk                  (0x1UL << PWR_PDCRE_PD10_Pos)           /*!< 0x00000400 */
20432 #define PWR_PDCRE_PD10                      PWR_PDCRE_PD10_Msk                      /*!< Apply pull-down for PE10 */
20433 #define PWR_PDCRE_PD11_Pos                  (11U)
20434 #define PWR_PDCRE_PD11_Msk                  (0x1UL << PWR_PDCRE_PD11_Pos)           /*!< 0x00000800 */
20435 #define PWR_PDCRE_PD11                      PWR_PDCRE_PD11_Msk                      /*!< Apply pull-down for PE11 */
20436 #define PWR_PDCRE_PD12_Pos                  (12U)
20437 #define PWR_PDCRE_PD12_Msk                  (0x1UL << PWR_PDCRE_PD12_Pos)           /*!< 0x00001000 */
20438 #define PWR_PDCRE_PD12                      PWR_PDCRE_PD12_Msk                      /*!< Apply pull-down for PE12 */
20439 #define PWR_PDCRE_PD13_Pos                  (13U)
20440 #define PWR_PDCRE_PD13_Msk                  (0x1UL << PWR_PDCRE_PD13_Pos)           /*!< 0x00002000 */
20441 #define PWR_PDCRE_PD13                      PWR_PDCRE_PD13_Msk                      /*!< Apply pull-down for PE13 */
20442 #define PWR_PDCRE_PD14_Pos                  (14U)
20443 #define PWR_PDCRE_PD14_Msk                  (0x1UL << PWR_PDCRE_PD14_Pos)           /*!< 0x00004000 */
20444 #define PWR_PDCRE_PD14                      PWR_PDCRE_PD14_Msk                      /*!< Apply pull-down for PE14 */
20445 #define PWR_PDCRE_PD15_Pos                  (15U)
20446 #define PWR_PDCRE_PD15_Msk                  (0x1UL << PWR_PDCRE_PD15_Pos)           /*!< 0x00008000 */
20447 #define PWR_PDCRE_PD15                      PWR_PDCRE_PD15_Msk                      /*!< Apply pull-down for PE15 */
20448 
20449 /********************  Bit definition for PWR_PUCRF register  *****************/
20450 #define PWR_PUCRF_PU0_Pos                   (0U)
20451 #define PWR_PUCRF_PU0_Msk                   (0x1UL << PWR_PUCRF_PU0_Pos)            /*!< 0x00000001 */
20452 #define PWR_PUCRF_PU0                       PWR_PUCRF_PU0_Msk                       /*!< Apply pull-up for PF0  */
20453 #define PWR_PUCRF_PU1_Pos                   (1U)
20454 #define PWR_PUCRF_PU1_Msk                   (0x1UL << PWR_PUCRF_PU1_Pos)            /*!< 0x00000002 */
20455 #define PWR_PUCRF_PU1                       PWR_PUCRF_PU1_Msk                       /*!< Apply pull-up for PF1  */
20456 #define PWR_PUCRF_PU2_Pos                   (2U)
20457 #define PWR_PUCRF_PU2_Msk                   (0x1UL << PWR_PUCRF_PU2_Pos)            /*!< 0x00000004 */
20458 #define PWR_PUCRF_PU2                       PWR_PUCRF_PU2_Msk                       /*!< Apply pull-up for PF2  */
20459 #define PWR_PUCRF_PU3_Pos                   (3U)
20460 #define PWR_PUCRF_PU3_Msk                   (0x1UL << PWR_PUCRF_PU3_Pos)            /*!< 0x00000008 */
20461 #define PWR_PUCRF_PU3                       PWR_PUCRF_PU3_Msk                       /*!< Apply pull-up for PF3  */
20462 #define PWR_PUCRF_PU4_Pos                   (4U)
20463 #define PWR_PUCRF_PU4_Msk                   (0x1UL << PWR_PUCRF_PU4_Pos)            /*!< 0x00000010 */
20464 #define PWR_PUCRF_PU4                       PWR_PUCRF_PU4_Msk                       /*!< Apply pull-up for PF4  */
20465 #define PWR_PUCRF_PU5_Pos                   (5U)
20466 #define PWR_PUCRF_PU5_Msk                   (0x1UL << PWR_PUCRF_PU5_Pos)            /*!< 0x00000020 */
20467 #define PWR_PUCRF_PU5                       PWR_PUCRF_PU5_Msk                       /*!< Apply pull-up for PF5  */
20468 #define PWR_PUCRF_PU6_Pos                   (6U)
20469 #define PWR_PUCRF_PU6_Msk                   (0x1UL << PWR_PUCRF_PU6_Pos)            /*!< 0x00000040 */
20470 #define PWR_PUCRF_PU6                       PWR_PUCRF_PU6_Msk                       /*!< Apply pull-up for PF6  */
20471 #define PWR_PUCRF_PU7_Pos                   (7U)
20472 #define PWR_PUCRF_PU7_Msk                   (0x1UL << PWR_PUCRF_PU7_Pos)            /*!< 0x00000080 */
20473 #define PWR_PUCRF_PU7                       PWR_PUCRF_PU7_Msk                       /*!< Apply pull-up for PF7  */
20474 #define PWR_PUCRF_PU8_Pos                   (8U)
20475 #define PWR_PUCRF_PU8_Msk                   (0x1UL << PWR_PUCRF_PU8_Pos)            /*!< 0x00000100 */
20476 #define PWR_PUCRF_PU8                       PWR_PUCRF_PU8_Msk                       /*!< Apply pull-up for PF8  */
20477 #define PWR_PUCRF_PU9_Pos                   (9U)
20478 #define PWR_PUCRF_PU9_Msk                   (0x1UL << PWR_PUCRF_PU9_Pos)            /*!< 0x00000200 */
20479 #define PWR_PUCRF_PU9                       PWR_PUCRF_PU9_Msk                       /*!< Apply pull-up for PF9  */
20480 #define PWR_PUCRF_PU10_Pos                  (10U)
20481 #define PWR_PUCRF_PU10_Msk                  (0x1UL << PWR_PUCRF_PU10_Pos)           /*!< 0x00000400 */
20482 #define PWR_PUCRF_PU10                      PWR_PUCRF_PU10_Msk                      /*!< Apply pull-up for PF10 */
20483 #define PWR_PUCRF_PU11_Pos                  (11U)
20484 #define PWR_PUCRF_PU11_Msk                  (0x1UL << PWR_PUCRF_PU11_Pos)           /*!< 0x00000800 */
20485 #define PWR_PUCRF_PU11                      PWR_PUCRF_PU11_Msk                      /*!< Apply pull-up for PF11 */
20486 #define PWR_PUCRF_PU12_Pos                  (12U)
20487 #define PWR_PUCRF_PU12_Msk                  (0x1UL << PWR_PUCRF_PU12_Pos)           /*!< 0x00001000 */
20488 #define PWR_PUCRF_PU12                      PWR_PUCRF_PU12_Msk                      /*!< Apply pull-up for PF12 */
20489 #define PWR_PUCRF_PU13_Pos                  (13U)
20490 #define PWR_PUCRF_PU13_Msk                  (0x1UL << PWR_PUCRF_PU13_Pos)           /*!< 0x00002000 */
20491 #define PWR_PUCRF_PU13                      PWR_PUCRF_PU13_Msk                      /*!< Apply pull-up for PF13 */
20492 #define PWR_PUCRF_PU14_Pos                  (14U)
20493 #define PWR_PUCRF_PU14_Msk                  (0x1UL << PWR_PUCRF_PU14_Pos)           /*!< 0x00004000 */
20494 #define PWR_PUCRF_PU14                      PWR_PUCRF_PU14_Msk                      /*!< Apply pull-up for PF14 */
20495 #define PWR_PUCRF_PU15_Pos                  (15U)
20496 #define PWR_PUCRF_PU15_Msk                  (0x1UL << PWR_PUCRF_PU15_Pos)           /*!< 0x00008000 */
20497 #define PWR_PUCRF_PU15                      PWR_PUCRF_PU15_Msk                      /*!< Apply pull-up for PF15 */
20498 
20499 /********************  Bit definition for PWR_PDCRF register  *****************/
20500 #define PWR_PDCRF_PD0_Pos                   (0U)
20501 #define PWR_PDCRF_PD0_Msk                   (0x1UL << PWR_PDCRF_PD0_Pos)            /*!< 0x00000001 */
20502 #define PWR_PDCRF_PD0                       PWR_PDCRF_PD0_Msk                       /*!< Apply pull-down for PF0  */
20503 #define PWR_PDCRF_PD1_Pos                   (1U)
20504 #define PWR_PDCRF_PD1_Msk                   (0x1UL << PWR_PDCRF_PD1_Pos)            /*!< 0x00000002 */
20505 #define PWR_PDCRF_PD1                       PWR_PDCRF_PD1_Msk                       /*!< Apply pull-down for PF1  */
20506 #define PWR_PDCRF_PD2_Pos                   (2U)
20507 #define PWR_PDCRF_PD2_Msk                   (0x1UL << PWR_PDCRF_PD2_Pos)            /*!< 0x00000004 */
20508 #define PWR_PDCRF_PD2                       PWR_PDCRF_PD2_Msk                       /*!< Apply pull-down for PF2  */
20509 #define PWR_PDCRF_PD3_Pos                   (3U)
20510 #define PWR_PDCRF_PD3_Msk                   (0x1UL << PWR_PDCRF_PD3_Pos)            /*!< 0x00000008 */
20511 #define PWR_PDCRF_PD3                       PWR_PDCRF_PD3_Msk                       /*!< Apply pull-down for PF3  */
20512 #define PWR_PDCRF_PD4_Pos                   (4U)
20513 #define PWR_PDCRF_PD4_Msk                   (0x1UL << PWR_PDCRF_PD4_Pos)            /*!< 0x00000010 */
20514 #define PWR_PDCRF_PD4                       PWR_PDCRF_PD4_Msk                       /*!< Apply pull-down for PF4  */
20515 #define PWR_PDCRF_PD5_Pos                   (5U)
20516 #define PWR_PDCRF_PD5_Msk                   (0x1UL << PWR_PDCRF_PD5_Pos)            /*!< 0x00000020 */
20517 #define PWR_PDCRF_PD5                       PWR_PDCRF_PD5_Msk                       /*!< Apply pull-down for PF5  */
20518 #define PWR_PDCRF_PD6_Pos                   (6U)
20519 #define PWR_PDCRF_PD6_Msk                   (0x1UL << PWR_PDCRF_PD6_Pos)            /*!< 0x00000040 */
20520 #define PWR_PDCRF_PD6                       PWR_PDCRF_PD6_Msk                       /*!< Apply pull-down for PF6  */
20521 #define PWR_PDCRF_PD7_Pos                   (7U)
20522 #define PWR_PDCRF_PD7_Msk                   (0x1UL << PWR_PDCRF_PD7_Pos)            /*!< 0x00000080 */
20523 #define PWR_PDCRF_PD7                       PWR_PDCRF_PD7_Msk                       /*!< Apply pull-down for PF7  */
20524 #define PWR_PDCRF_PD8_Pos                   (8U)
20525 #define PWR_PDCRF_PD8_Msk                   (0x1UL << PWR_PDCRF_PD8_Pos)            /*!< 0x00000100 */
20526 #define PWR_PDCRF_PD8                       PWR_PDCRF_PD8_Msk                       /*!< Apply pull-down for PF8  */
20527 #define PWR_PDCRF_PD9_Pos                   (9U)
20528 #define PWR_PDCRF_PD9_Msk                   (0x1UL << PWR_PDCRF_PD9_Pos)            /*!< 0x00000200 */
20529 #define PWR_PDCRF_PD9                       PWR_PDCRF_PD9_Msk                       /*!< Apply pull-down for PF9  */
20530 #define PWR_PDCRF_PD10_Pos                  (10U)
20531 #define PWR_PDCRF_PD10_Msk                  (0x1UL << PWR_PDCRF_PD10_Pos)           /*!< 0x00000400 */
20532 #define PWR_PDCRF_PD10                      PWR_PDCRF_PD10_Msk                      /*!< Apply pull-down for PF10 */
20533 #define PWR_PDCRF_PD11_Pos                  (11U)
20534 #define PWR_PDCRF_PD11_Msk                  (0x1UL << PWR_PDCRF_PD11_Pos)           /*!< 0x00000800 */
20535 #define PWR_PDCRF_PD11                      PWR_PDCRF_PD11_Msk                      /*!< Apply pull-down for PF11 */
20536 #define PWR_PDCRF_PD12_Pos                  (12U)
20537 #define PWR_PDCRF_PD12_Msk                  (0x1UL << PWR_PDCRF_PD12_Pos)           /*!< 0x00001000 */
20538 #define PWR_PDCRF_PD12                      PWR_PDCRF_PD12_Msk                      /*!< Apply pull-down for PF12 */
20539 #define PWR_PDCRF_PD13_Pos                  (13U)
20540 #define PWR_PDCRF_PD13_Msk                  (0x1UL << PWR_PDCRF_PD13_Pos)           /*!< 0x00002000 */
20541 #define PWR_PDCRF_PD13                      PWR_PDCRF_PD13_Msk                      /*!< Apply pull-down for PF13 */
20542 #define PWR_PDCRF_PD14_Pos                  (14U)
20543 #define PWR_PDCRF_PD14_Msk                  (0x1UL << PWR_PDCRF_PD14_Pos)           /*!< 0x00004000 */
20544 #define PWR_PDCRF_PD14                      PWR_PDCRF_PD14_Msk                      /*!< Apply pull-down for PF14 */
20545 #define PWR_PDCRF_PD15_Pos                  (15U)
20546 #define PWR_PDCRF_PD15_Msk                  (0x1UL << PWR_PDCRF_PD15_Pos)           /*!< 0x00008000 */
20547 #define PWR_PDCRF_PD15                      PWR_PDCRF_PD15_Msk                      /*!< Apply pull-down for PF15 */
20548 
20549 /********************  Bit definition for PWR_PUCRG register  *****************/
20550 #define PWR_PUCRG_PU0_Pos                   (0U)
20551 #define PWR_PUCRG_PU0_Msk                   (0x1UL << PWR_PUCRG_PU0_Pos)            /*!< 0x00000001 */
20552 #define PWR_PUCRG_PU0                       PWR_PUCRG_PU0_Msk                       /*!< Apply pull-up for PG0  */
20553 #define PWR_PUCRG_PU1_Pos                   (1U)
20554 #define PWR_PUCRG_PU1_Msk                   (0x1UL << PWR_PUCRG_PU1_Pos)            /*!< 0x00000002 */
20555 #define PWR_PUCRG_PU1                       PWR_PUCRG_PU1_Msk                       /*!< Apply pull-up for PG1  */
20556 #define PWR_PUCRG_PU2_Pos                   (2U)
20557 #define PWR_PUCRG_PU2_Msk                   (0x1UL << PWR_PUCRG_PU2_Pos)            /*!< 0x00000004 */
20558 #define PWR_PUCRG_PU2                       PWR_PUCRG_PU2_Msk                       /*!< Apply pull-up for PG2  */
20559 #define PWR_PUCRG_PU3_Pos                   (3U)
20560 #define PWR_PUCRG_PU3_Msk                   (0x1UL << PWR_PUCRG_PU3_Pos)            /*!< 0x00000008 */
20561 #define PWR_PUCRG_PU3                       PWR_PUCRG_PU3_Msk                       /*!< Apply pull-up for PG3  */
20562 #define PWR_PUCRG_PU4_Pos                   (4U)
20563 #define PWR_PUCRG_PU4_Msk                   (0x1UL << PWR_PUCRG_PU4_Pos)            /*!< 0x00000010 */
20564 #define PWR_PUCRG_PU4                       PWR_PUCRG_PU4_Msk                       /*!< Apply pull-up for PG4  */
20565 #define PWR_PUCRG_PU5_Pos                   (5U)
20566 #define PWR_PUCRG_PU5_Msk                   (0x1UL << PWR_PUCRG_PU5_Pos)            /*!< 0x00000020 */
20567 #define PWR_PUCRG_PU5                       PWR_PUCRG_PU5_Msk                       /*!< Apply pull-up for PG5  */
20568 #define PWR_PUCRG_PU6_Pos                   (6U)
20569 #define PWR_PUCRG_PU6_Msk                   (0x1UL << PWR_PUCRG_PU6_Pos)            /*!< 0x00000040 */
20570 #define PWR_PUCRG_PU6                       PWR_PUCRG_PU6_Msk                       /*!< Apply pull-up for PG6  */
20571 #define PWR_PUCRG_PU7_Pos                   (7U)
20572 #define PWR_PUCRG_PU7_Msk                   (0x1UL << PWR_PUCRG_PU7_Pos)            /*!< 0x00000080 */
20573 #define PWR_PUCRG_PU7                       PWR_PUCRG_PU7_Msk                       /*!< Apply pull-up for PG7  */
20574 #define PWR_PUCRG_PU8_Pos                   (8U)
20575 #define PWR_PUCRG_PU8_Msk                   (0x1UL << PWR_PUCRG_PU8_Pos)            /*!< 0x00000100 */
20576 #define PWR_PUCRG_PU8                       PWR_PUCRG_PU8_Msk                       /*!< Apply pull-up for PG8  */
20577 #define PWR_PUCRG_PU9_Pos                   (9U)
20578 #define PWR_PUCRG_PU9_Msk                   (0x1UL << PWR_PUCRG_PU9_Pos)            /*!< 0x00000200 */
20579 #define PWR_PUCRG_PU9                       PWR_PUCRG_PU9_Msk                       /*!< Apply pull-up for PG9  */
20580 #define PWR_PUCRG_PU10_Pos                  (10U)
20581 #define PWR_PUCRG_PU10_Msk                  (0x1UL << PWR_PUCRG_PU10_Pos)           /*!< 0x00000400 */
20582 #define PWR_PUCRG_PU10                      PWR_PUCRG_PU10_Msk                      /*!< Apply pull-up for PG10 */
20583 #define PWR_PUCRG_PU11_Pos                  (11U)
20584 #define PWR_PUCRG_PU11_Msk                  (0x1UL << PWR_PUCRG_PU11_Pos)           /*!< 0x00000800 */
20585 #define PWR_PUCRG_PU11                      PWR_PUCRG_PU11_Msk                      /*!< Apply pull-up for PG11 */
20586 #define PWR_PUCRG_PU12_Pos                  (12U)
20587 #define PWR_PUCRG_PU12_Msk                  (0x1UL << PWR_PUCRG_PU12_Pos)           /*!< 0x00001000 */
20588 #define PWR_PUCRG_PU12                      PWR_PUCRG_PU12_Msk                      /*!< Apply pull-up for PG12 */
20589 #define PWR_PUCRG_PU13_Pos                  (13U)
20590 #define PWR_PUCRG_PU13_Msk                  (0x1UL << PWR_PUCRG_PU13_Pos)           /*!< 0x00002000 */
20591 #define PWR_PUCRG_PU13                      PWR_PUCRG_PU13_Msk                      /*!< Apply pull-up for PG13 */
20592 #define PWR_PUCRG_PU14_Pos                  (14U)
20593 #define PWR_PUCRG_PU14_Msk                  (0x1UL << PWR_PUCRG_PU14_Pos)           /*!< 0x00004000 */
20594 #define PWR_PUCRG_PU14                      PWR_PUCRG_PU14_Msk                      /*!< Apply pull-up for PG14 */
20595 #define PWR_PUCRG_PU15_Pos                  (15U)
20596 #define PWR_PUCRG_PU15_Msk                  (0x1UL << PWR_PUCRG_PU15_Pos)           /*!< 0x00008000 */
20597 #define PWR_PUCRG_PU15                      PWR_PUCRG_PU15_Msk                      /*!< Apply pull-up for PG15 */
20598 
20599 /********************  Bit definition for PWR_PDCRG register  *****************/
20600 #define PWR_PDCRG_PD0_Pos                   (0U)
20601 #define PWR_PDCRG_PD0_Msk                   (0x1UL << PWR_PDCRG_PD0_Pos)            /*!< 0x00000001 */
20602 #define PWR_PDCRG_PD0                       PWR_PDCRG_PD0_Msk                       /*!< Apply pull-down for PG0  */
20603 #define PWR_PDCRG_PD1_Pos                   (1U)
20604 #define PWR_PDCRG_PD1_Msk                   (0x1UL << PWR_PDCRG_PD1_Pos)            /*!< 0x00000002 */
20605 #define PWR_PDCRG_PD1                       PWR_PDCRG_PD1_Msk                       /*!< Apply pull-down for PG1  */
20606 #define PWR_PDCRG_PD2_Pos                   (2U)
20607 #define PWR_PDCRG_PD2_Msk                   (0x1UL << PWR_PDCRG_PD2_Pos)            /*!< 0x00000004 */
20608 #define PWR_PDCRG_PD2                       PWR_PDCRG_PD2_Msk                       /*!< Apply pull-down for PG2  */
20609 #define PWR_PDCRG_PD3_Pos                   (3U)
20610 #define PWR_PDCRG_PD3_Msk                   (0x1UL << PWR_PDCRG_PD3_Pos)            /*!< 0x00000008 */
20611 #define PWR_PDCRG_PD3                       PWR_PDCRG_PD3_Msk                       /*!< Apply pull-down for PG3  */
20612 #define PWR_PDCRG_PD4_Pos                   (4U)
20613 #define PWR_PDCRG_PD4_Msk                   (0x1UL << PWR_PDCRG_PD4_Pos)            /*!< 0x00000010 */
20614 #define PWR_PDCRG_PD4                       PWR_PDCRG_PD4_Msk                       /*!< Apply pull-down for PG4  */
20615 #define PWR_PDCRG_PD5_Pos                   (5U)
20616 #define PWR_PDCRG_PD5_Msk                   (0x1UL << PWR_PDCRG_PD5_Pos)            /*!< 0x00000020 */
20617 #define PWR_PDCRG_PD5                       PWR_PDCRG_PD5_Msk                       /*!< Apply pull-down for PG5  */
20618 #define PWR_PDCRG_PD6_Pos                   (6U)
20619 #define PWR_PDCRG_PD6_Msk                   (0x1UL << PWR_PDCRG_PD6_Pos)            /*!< 0x00000040 */
20620 #define PWR_PDCRG_PD6                       PWR_PDCRG_PD6_Msk                       /*!< Apply pull-down for PG6  */
20621 #define PWR_PDCRG_PD7_Pos                   (7U)
20622 #define PWR_PDCRG_PD7_Msk                   (0x1UL << PWR_PDCRG_PD7_Pos)            /*!< 0x00000080 */
20623 #define PWR_PDCRG_PD7                       PWR_PDCRG_PD7_Msk                       /*!< Apply pull-down for PG7  */
20624 #define PWR_PDCRG_PD8_Pos                   (8U)
20625 #define PWR_PDCRG_PD8_Msk                   (0x1UL << PWR_PDCRG_PD8_Pos)            /*!< 0x00000100 */
20626 #define PWR_PDCRG_PD8                       PWR_PDCRG_PD8_Msk                       /*!< Apply pull-down for PG8  */
20627 #define PWR_PDCRG_PD9_Pos                   (9U)
20628 #define PWR_PDCRG_PD9_Msk                   (0x1UL << PWR_PDCRG_PD9_Pos)            /*!< 0x00000200 */
20629 #define PWR_PDCRG_PD9                       PWR_PDCRG_PD9_Msk                       /*!< Apply pull-down for PG9  */
20630 #define PWR_PDCRG_PD10_Pos                  (10U)
20631 #define PWR_PDCRG_PD10_Msk                  (0x1UL << PWR_PDCRG_PD10_Pos)           /*!< 0x00000400 */
20632 #define PWR_PDCRG_PD10                      PWR_PDCRG_PD10_Msk                      /*!< Apply pull-down for PG10 */
20633 #define PWR_PDCRG_PD11_Pos                  (11U)
20634 #define PWR_PDCRG_PD11_Msk                  (0x1UL << PWR_PDCRG_PD11_Pos)           /*!< 0x00000800 */
20635 #define PWR_PDCRG_PD11                      PWR_PDCRG_PD11_Msk                      /*!< Apply pull-down for PG11 */
20636 #define PWR_PDCRG_PD12_Pos                  (12U)
20637 #define PWR_PDCRG_PD12_Msk                  (0x1UL << PWR_PDCRG_PD12_Pos)           /*!< 0x00001000 */
20638 #define PWR_PDCRG_PD12                      PWR_PDCRG_PD12_Msk                      /*!< Apply pull-down for PG12 */
20639 #define PWR_PDCRG_PD13_Pos                  (13U)
20640 #define PWR_PDCRG_PD13_Msk                  (0x1UL << PWR_PDCRG_PD13_Pos)           /*!< 0x00002000 */
20641 #define PWR_PDCRG_PD13                      PWR_PDCRG_PD13_Msk                      /*!< Apply pull-down for PG13 */
20642 #define PWR_PDCRG_PD14_Pos                  (14U)
20643 #define PWR_PDCRG_PD14_Msk                  (0x1UL << PWR_PDCRG_PD14_Pos)           /*!< 0x00004000 */
20644 #define PWR_PDCRG_PD14                      PWR_PDCRG_PD14_Msk                      /*!< Apply pull-down for PG14 */
20645 #define PWR_PDCRG_PD15_Pos                  (15U)
20646 #define PWR_PDCRG_PD15_Msk                  (0x1UL << PWR_PDCRG_PD15_Pos)           /*!< 0x00008000 */
20647 #define PWR_PDCRG_PD15                      PWR_PDCRG_PD15_Msk                      /*!< Apply pull-down for PG15 */
20648 
20649 /********************  Bit definition for PWR_PUCRH register  *****************/
20650 #define PWR_PUCRH_PU0_Pos                   (0U)
20651 #define PWR_PUCRH_PU0_Msk                   (0x1UL << PWR_PUCRH_PU0_Pos)            /*!< 0x00000001 */
20652 #define PWR_PUCRH_PU0                       PWR_PUCRH_PU0_Msk                       /*!< Apply pull-up for PH0  */
20653 #define PWR_PUCRH_PU1_Pos                   (1U)
20654 #define PWR_PUCRH_PU1_Msk                   (0x1UL << PWR_PUCRH_PU1_Pos)            /*!< 0x00000002 */
20655 #define PWR_PUCRH_PU1                       PWR_PUCRH_PU1_Msk                       /*!< Apply pull-up for PH1  */
20656 #define PWR_PUCRH_PU2_Pos                   (2U)
20657 #define PWR_PUCRH_PU2_Msk                   (0x1UL << PWR_PUCRH_PU2_Pos)            /*!< 0x00000004 */
20658 #define PWR_PUCRH_PU2                       PWR_PUCRH_PU2_Msk                       /*!< Apply pull-up for PH2  */
20659 #define PWR_PUCRH_PU3_Pos                   (3U)
20660 #define PWR_PUCRH_PU3_Msk                   (0x1UL << PWR_PUCRH_PU3_Pos)            /*!< 0x00000008 */
20661 #define PWR_PUCRH_PU3                       PWR_PUCRH_PU3_Msk                       /*!< Apply pull-up for PH3  */
20662 #define PWR_PUCRH_PU4_Pos                   (4U)
20663 #define PWR_PUCRH_PU4_Msk                   (0x1UL << PWR_PUCRH_PU4_Pos)            /*!< 0x00000010 */
20664 #define PWR_PUCRH_PU4                       PWR_PUCRH_PU4_Msk                       /*!< Apply pull-up for PH4  */
20665 #define PWR_PUCRH_PU5_Pos                   (5U)
20666 #define PWR_PUCRH_PU5_Msk                   (0x1UL << PWR_PUCRH_PU5_Pos)            /*!< 0x00000020 */
20667 #define PWR_PUCRH_PU5                       PWR_PUCRH_PU5_Msk                       /*!< Apply pull-up for PH5  */
20668 #define PWR_PUCRH_PU6_Pos                   (6U)
20669 #define PWR_PUCRH_PU6_Msk                   (0x1UL << PWR_PUCRH_PU6_Pos)            /*!< 0x00000040 */
20670 #define PWR_PUCRH_PU6                       PWR_PUCRH_PU6_Msk                       /*!< Apply pull-up for PH6  */
20671 #define PWR_PUCRH_PU7_Pos                   (7U)
20672 #define PWR_PUCRH_PU7_Msk                   (0x1UL << PWR_PUCRH_PU7_Pos)            /*!< 0x00000080 */
20673 #define PWR_PUCRH_PU7                       PWR_PUCRH_PU7_Msk                       /*!< Apply pull-up for PH7  */
20674 #define PWR_PUCRH_PU8_Pos                   (8U)
20675 #define PWR_PUCRH_PU8_Msk                   (0x1UL << PWR_PUCRH_PU8_Pos)            /*!< 0x00000100 */
20676 #define PWR_PUCRH_PU8                       PWR_PUCRH_PU8_Msk                       /*!< Apply pull-up for PH8  */
20677 #define PWR_PUCRH_PU9_Pos                   (9U)
20678 #define PWR_PUCRH_PU9_Msk                   (0x1UL << PWR_PUCRH_PU9_Pos)            /*!< 0x00000200 */
20679 #define PWR_PUCRH_PU9                       PWR_PUCRH_PU9_Msk                       /*!< Apply pull-up for PH9  */
20680 #define PWR_PUCRH_PU10_Pos                  (10U)
20681 #define PWR_PUCRH_PU10_Msk                  (0x1UL << PWR_PUCRH_PU10_Pos)           /*!< 0x00000400 */
20682 #define PWR_PUCRH_PU10                      PWR_PUCRH_PU10_Msk                      /*!< Apply pull-up for PH10 */
20683 #define PWR_PUCRH_PU11_Pos                  (11U)
20684 #define PWR_PUCRH_PU11_Msk                  (0x1UL << PWR_PUCRH_PU11_Pos)           /*!< 0x00000800 */
20685 #define PWR_PUCRH_PU11                      PWR_PUCRH_PU11_Msk                      /*!< Apply pull-up for PH11 */
20686 #define PWR_PUCRH_PU12_Pos                  (12U)
20687 #define PWR_PUCRH_PU12_Msk                  (0x1UL << PWR_PUCRH_PU12_Pos)           /*!< 0x00001000 */
20688 #define PWR_PUCRH_PU12                      PWR_PUCRH_PU12_Msk                      /*!< Apply pull-up for PH12 */
20689 #define PWR_PUCRH_PU13_Pos                  (13U)
20690 #define PWR_PUCRH_PU13_Msk                  (0x1UL << PWR_PUCRH_PU13_Pos)           /*!< 0x00002000 */
20691 #define PWR_PUCRH_PU13                      PWR_PUCRH_PU13_Msk                      /*!< Apply pull-up for PH13 */
20692 #define PWR_PUCRH_PU14_Pos                  (14U)
20693 #define PWR_PUCRH_PU14_Msk                  (0x1UL << PWR_PUCRH_PU14_Pos)           /*!< 0x00004000 */
20694 #define PWR_PUCRH_PU14                      PWR_PUCRH_PU14_Msk                      /*!< Apply pull-up for PH14 */
20695 #define PWR_PUCRH_PU15_Pos                  (15U)
20696 #define PWR_PUCRH_PU15_Msk                  (0x1UL << PWR_PUCRH_PU15_Pos)           /*!< 0x00008000 */
20697 #define PWR_PUCRH_PU15                      PWR_PUCRH_PU15_Msk                      /*!< Apply pull-up for PH15 */
20698 
20699 /********************  Bit definition for PWR_PDCRH register  *****************/
20700 #define PWR_PDCRH_PD0_Pos                   (0U)
20701 #define PWR_PDCRH_PD0_Msk                   (0x1UL << PWR_PDCRH_PD0_Pos)            /*!< 0x00000001 */
20702 #define PWR_PDCRH_PD0                       PWR_PDCRH_PD0_Msk                       /*!< Apply pull-down for PH0  */
20703 #define PWR_PDCRH_PD1_Pos                   (1U)
20704 #define PWR_PDCRH_PD1_Msk                   (0x1UL << PWR_PDCRH_PD1_Pos)            /*!< 0x00000002 */
20705 #define PWR_PDCRH_PD1                       PWR_PDCRH_PD1_Msk                       /*!< Apply pull-down for PH1  */
20706 #define PWR_PDCRH_PD2_Pos                   (2U)
20707 #define PWR_PDCRH_PD2_Msk                   (0x1UL << PWR_PDCRH_PD2_Pos)            /*!< 0x00000004 */
20708 #define PWR_PDCRH_PD2                       PWR_PDCRH_PD2_Msk                       /*!< Apply pull-down for PH2  */
20709 #define PWR_PDCRH_PD3_Pos                   (3U)
20710 #define PWR_PDCRH_PD3_Msk                   (0x1UL << PWR_PDCRH_PD3_Pos)            /*!< 0x00000008 */
20711 #define PWR_PDCRH_PD3                       PWR_PDCRH_PD3_Msk                       /*!< Apply pull-down for PH3  */
20712 #define PWR_PDCRH_PD4_Pos                   (4U)
20713 #define PWR_PDCRH_PD4_Msk                   (0x1UL << PWR_PDCRH_PD4_Pos)            /*!< 0x00000010 */
20714 #define PWR_PDCRH_PD4                       PWR_PDCRH_PD4_Msk                       /*!< Apply pull-down for PH4  */
20715 #define PWR_PDCRH_PD5_Pos                   (5U)
20716 #define PWR_PDCRH_PD5_Msk                   (0x1UL << PWR_PDCRH_PD5_Pos)            /*!< 0x00000020 */
20717 #define PWR_PDCRH_PD5                       PWR_PDCRH_PD5_Msk                       /*!< Apply pull-down for PH5  */
20718 #define PWR_PDCRH_PD6_Pos                   (6U)
20719 #define PWR_PDCRH_PD6_Msk                   (0x1UL << PWR_PDCRH_PD6_Pos)            /*!< 0x00000040 */
20720 #define PWR_PDCRH_PD6                       PWR_PDCRH_PD6_Msk                       /*!< Apply pull-down for PH6  */
20721 #define PWR_PDCRH_PD7_Pos                   (7U)
20722 #define PWR_PDCRH_PD7_Msk                   (0x1UL << PWR_PDCRH_PD7_Pos)            /*!< 0x00000080 */
20723 #define PWR_PDCRH_PD7                       PWR_PDCRH_PD7_Msk                       /*!< Apply pull-down for PH7  */
20724 #define PWR_PDCRH_PD8_Pos                   (8U)
20725 #define PWR_PDCRH_PD8_Msk                   (0x1UL << PWR_PDCRH_PD8_Pos)            /*!< 0x00000100 */
20726 #define PWR_PDCRH_PD8                       PWR_PDCRH_PD8_Msk                       /*!< Apply pull-down for PH8  */
20727 #define PWR_PDCRH_PD9_Pos                   (9U)
20728 #define PWR_PDCRH_PD9_Msk                   (0x1UL << PWR_PDCRH_PD9_Pos)            /*!< 0x00000200 */
20729 #define PWR_PDCRH_PD9                       PWR_PDCRH_PD9_Msk                       /*!< Apply pull-down for PH9  */
20730 #define PWR_PDCRH_PD10_Pos                  (10U)
20731 #define PWR_PDCRH_PD10_Msk                  (0x1UL << PWR_PDCRH_PD10_Pos)           /*!< 0x00000400 */
20732 #define PWR_PDCRH_PD10                      PWR_PDCRH_PD10_Msk                      /*!< Apply pull-down for PH10 */
20733 #define PWR_PDCRH_PD11_Pos                  (11U)
20734 #define PWR_PDCRH_PD11_Msk                  (0x1UL << PWR_PDCRH_PD11_Pos)           /*!< 0x00000800 */
20735 #define PWR_PDCRH_PD11                      PWR_PDCRH_PD11_Msk                      /*!< Apply pull-down for PH11 */
20736 #define PWR_PDCRH_PD12_Pos                  (12U)
20737 #define PWR_PDCRH_PD12_Msk                  (0x1UL << PWR_PDCRH_PD12_Pos)           /*!< 0x00001000 */
20738 #define PWR_PDCRH_PD12                      PWR_PDCRH_PD12_Msk                      /*!< Apply pull-down for PH12 */
20739 #define PWR_PDCRH_PD13_Pos                  (13U)
20740 #define PWR_PDCRH_PD13_Msk                  (0x1UL << PWR_PDCRH_PD13_Pos)           /*!< 0x00002000 */
20741 #define PWR_PDCRH_PD13                      PWR_PDCRH_PD13_Msk                      /*!< Apply pull-down for PH13 */
20742 #define PWR_PDCRH_PD14_Pos                  (14U)
20743 #define PWR_PDCRH_PD14_Msk                  (0x1UL << PWR_PDCRH_PD14_Pos)           /*!< 0x00004000 */
20744 #define PWR_PDCRH_PD14                      PWR_PDCRH_PD14_Msk                      /*!< Apply pull-down for PH14 */
20745 #define PWR_PDCRH_PD15_Pos                  (15U)
20746 #define PWR_PDCRH_PD15_Msk                  (0x1UL << PWR_PDCRH_PD15_Pos)           /*!< 0x00008000 */
20747 #define PWR_PDCRH_PD15                      PWR_PDCRH_PD15_Msk                      /*!< Apply pull-down for PH15 */
20748 
20749 /********************  Bit definition for PWR_PUCRI register  *****************/
20750 #define PWR_PUCRI_PU0_Pos                   (0U)
20751 #define PWR_PUCRI_PU0_Msk                   (0x1UL << PWR_PUCRI_PU0_Pos)            /*!< 0x00000001 */
20752 #define PWR_PUCRI_PU0                       PWR_PUCRI_PU0_Msk                       /*!< Apply pull-up for PI0  */
20753 #define PWR_PUCRI_PU1_Pos                   (1U)
20754 #define PWR_PUCRI_PU1_Msk                   (0x1UL << PWR_PUCRI_PU1_Pos)            /*!< 0x00000002 */
20755 #define PWR_PUCRI_PU1                       PWR_PUCRI_PU1_Msk                       /*!< Apply pull-up for PI1  */
20756 #define PWR_PUCRI_PU2_Pos                   (2U)
20757 #define PWR_PUCRI_PU2_Msk                   (0x1UL << PWR_PUCRI_PU2_Pos)            /*!< 0x00000004 */
20758 #define PWR_PUCRI_PU2                       PWR_PUCRI_PU2_Msk                       /*!< Apply pull-up for PI2  */
20759 #define PWR_PUCRI_PU3_Pos                   (3U)
20760 #define PWR_PUCRI_PU3_Msk                   (0x1UL << PWR_PUCRI_PU3_Pos)            /*!< 0x00000008 */
20761 #define PWR_PUCRI_PU3                       PWR_PUCRI_PU3_Msk                       /*!< Apply pull-up for PI3  */
20762 #define PWR_PUCRI_PU4_Pos                   (4U)
20763 #define PWR_PUCRI_PU4_Msk                   (0x1UL << PWR_PUCRI_PU4_Pos)            /*!< 0x00000010 */
20764 #define PWR_PUCRI_PU4                       PWR_PUCRI_PU4_Msk                       /*!< Apply pull-up for PI4  */
20765 #define PWR_PUCRI_PU5_Pos                   (5U)
20766 #define PWR_PUCRI_PU5_Msk                   (0x1UL << PWR_PUCRI_PU5_Pos)            /*!< 0x00000020 */
20767 #define PWR_PUCRI_PU5                       PWR_PUCRI_PU5_Msk                       /*!< Apply pull-up for PI5  */
20768 #define PWR_PUCRI_PU6_Pos                   (6U)
20769 #define PWR_PUCRI_PU6_Msk                   (0x1UL << PWR_PUCRI_PU6_Pos)            /*!< 0x00000040 */
20770 #define PWR_PUCRI_PU6                       PWR_PUCRI_PU6_Msk                       /*!< Apply pull-up for PI6  */
20771 #define PWR_PUCRI_PU7_Pos                   (7U)
20772 #define PWR_PUCRI_PU7_Msk                   (0x1UL << PWR_PUCRI_PU7_Pos)            /*!< 0x00000080 */
20773 #define PWR_PUCRI_PU7                       PWR_PUCRI_PU7_Msk                       /*!< Apply pull-up for PI7  */
20774 #define PWR_PUCRI_PU8_Pos                   (8U)
20775 #define PWR_PUCRI_PU8_Msk                   (0x1UL << PWR_PUCRI_PU8_Pos)            /*!< 0x00000100 */
20776 #define PWR_PUCRI_PU8                       PWR_PUCRI_PU8_Msk                       /*!< Apply pull-up for PI8  */
20777 #define PWR_PUCRI_PU9_Pos                   (9U)
20778 #define PWR_PUCRI_PU9_Msk                   (0x1UL << PWR_PUCRI_PU9_Pos)            /*!< 0x00000200 */
20779 #define PWR_PUCRI_PU9                       PWR_PUCRI_PU9_Msk                       /*!< Apply pull-up for PI9  */
20780 #define PWR_PUCRI_PU10_Pos                  (10U)
20781 #define PWR_PUCRI_PU10_Msk                  (0x1UL << PWR_PUCRI_PU10_Pos)           /*!< 0x00000400 */
20782 #define PWR_PUCRI_PU10                      PWR_PUCRI_PU10_Msk                      /*!< Apply pull-up for PI10 */
20783 #define PWR_PUCRI_PU11_Pos                  (11U)
20784 #define PWR_PUCRI_PU11_Msk                  (0x1UL << PWR_PUCRI_PU11_Pos)           /*!< 0x00000800 */
20785 #define PWR_PUCRI_PU11                      PWR_PUCRI_PU11_Msk                      /*!< Apply pull-up for PI11 */
20786 #define PWR_PUCRI_PU12_Pos                  (12U)
20787 #define PWR_PUCRI_PU12_Msk                  (0x1UL << PWR_PUCRI_PU12_Pos)           /*!< 0x00001000 */
20788 #define PWR_PUCRI_PU12                      PWR_PUCRI_PU12_Msk                      /*!< Apply pull-up for PI12 */
20789 #define PWR_PUCRI_PU13_Pos                  (13U)
20790 #define PWR_PUCRI_PU13_Msk                  (0x1UL << PWR_PUCRI_PU13_Pos)           /*!< 0x00002000 */
20791 #define PWR_PUCRI_PU13                      PWR_PUCRI_PU13_Msk                      /*!< Apply pull-up for PI13 */
20792 #define PWR_PUCRI_PU14_Pos                  (14U)
20793 #define PWR_PUCRI_PU14_Msk                  (0x1UL << PWR_PUCRI_PU14_Pos)           /*!< 0x00004000 */
20794 #define PWR_PUCRI_PU14                      PWR_PUCRI_PU14_Msk                      /*!< Apply pull-up for PI14 */
20795 #define PWR_PUCRI_PU15_Pos                  (15U)
20796 #define PWR_PUCRI_PU15_Msk                  (0x1UL << PWR_PUCRI_PU15_Pos)           /*!< 0x00008000 */
20797 #define PWR_PUCRI_PU15                      PWR_PUCRI_PU15_Msk                      /*!< Apply pull-up for PI15 */
20798 
20799 /********************  Bit definition for PWR_PDCRI register  *****************/
20800 #define PWR_PDCRI_PD0_Pos                   (0U)
20801 #define PWR_PDCRI_PD0_Msk                   (0x1UL << PWR_PDCRI_PD0_Pos)            /*!< 0x00000001 */
20802 #define PWR_PDCRI_PD0                       PWR_PDCRI_PD0_Msk                       /*!< Apply pull-down for PI0  */
20803 #define PWR_PDCRI_PD1_Pos                   (1U)
20804 #define PWR_PDCRI_PD1_Msk                   (0x1UL << PWR_PDCRI_PD1_Pos)            /*!< 0x00000002 */
20805 #define PWR_PDCRI_PD1                       PWR_PDCRI_PD1_Msk                       /*!< Apply pull-down for PI1  */
20806 #define PWR_PDCRI_PD2_Pos                   (2U)
20807 #define PWR_PDCRI_PD2_Msk                   (0x1UL << PWR_PDCRI_PD2_Pos)            /*!< 0x00000004 */
20808 #define PWR_PDCRI_PD2                       PWR_PDCRI_PD2_Msk                       /*!< Apply pull-down for PI2  */
20809 #define PWR_PDCRI_PD3_Pos                   (3U)
20810 #define PWR_PDCRI_PD3_Msk                   (0x1UL << PWR_PDCRI_PD3_Pos)            /*!< 0x00000008 */
20811 #define PWR_PDCRI_PD3                       PWR_PDCRI_PD3_Msk                       /*!< Apply pull-down for PI3  */
20812 #define PWR_PDCRI_PD4_Pos                   (4U)
20813 #define PWR_PDCRI_PD4_Msk                   (0x1UL << PWR_PDCRI_PD4_Pos)            /*!< 0x00000010 */
20814 #define PWR_PDCRI_PD4                       PWR_PDCRI_PD4_Msk                       /*!< Apply pull-down for PI4  */
20815 #define PWR_PDCRI_PD5_Pos                   (5U)
20816 #define PWR_PDCRI_PD5_Msk                   (0x1UL << PWR_PDCRI_PD5_Pos)            /*!< 0x00000020 */
20817 #define PWR_PDCRI_PD5                       PWR_PDCRI_PD5_Msk                       /*!< Apply pull-down for PI5  */
20818 #define PWR_PDCRI_PD6_Pos                   (6U)
20819 #define PWR_PDCRI_PD6_Msk                   (0x1UL << PWR_PDCRI_PD6_Pos)            /*!< 0x00000040 */
20820 #define PWR_PDCRI_PD6                       PWR_PDCRI_PD6_Msk                       /*!< Apply pull-down for PI6  */
20821 #define PWR_PDCRI_PD7_Pos                   (7U)
20822 #define PWR_PDCRI_PD7_Msk                   (0x1UL << PWR_PDCRI_PD7_Pos)            /*!< 0x00000080 */
20823 #define PWR_PDCRI_PD7                       PWR_PDCRI_PD7_Msk                       /*!< Apply pull-down for PI7  */
20824 #define PWR_PDCRI_PD8_Pos                   (8U)
20825 #define PWR_PDCRI_PD8_Msk                   (0x1UL << PWR_PDCRI_PD8_Pos)            /*!< 0x00000100 */
20826 #define PWR_PDCRI_PD8                       PWR_PDCRI_PD8_Msk                       /*!< Apply pull-down for PI8  */
20827 #define PWR_PDCRI_PD9_Pos                   (9U)
20828 #define PWR_PDCRI_PD9_Msk                   (0x1UL << PWR_PDCRI_PD9_Pos)            /*!< 0x00000200 */
20829 #define PWR_PDCRI_PD9                       PWR_PDCRI_PD9_Msk                       /*!< Apply pull-down for PI9  */
20830 #define PWR_PDCRI_PD10_Pos                  (10U)
20831 #define PWR_PDCRI_PD10_Msk                  (0x1UL << PWR_PDCRI_PD10_Pos)           /*!< 0x00000400 */
20832 #define PWR_PDCRI_PD10                      PWR_PDCRI_PD10_Msk                      /*!< Apply pull-down for PI10 */
20833 #define PWR_PDCRI_PD11_Pos                  (11U)
20834 #define PWR_PDCRI_PD11_Msk                  (0x1UL << PWR_PDCRI_PD11_Pos)           /*!< 0x00000800 */
20835 #define PWR_PDCRI_PD11                      PWR_PDCRI_PD11_Msk                      /*!< Apply pull-down for PI11 */
20836 #define PWR_PDCRI_PD12_Pos                  (12U)
20837 #define PWR_PDCRI_PD12_Msk                  (0x1UL << PWR_PDCRI_PD12_Pos)           /*!< 0x00001000 */
20838 #define PWR_PDCRI_PD12                      PWR_PDCRI_PD12_Msk                      /*!< Apply pull-down for PI12 */
20839 #define PWR_PDCRI_PD13_Pos                  (13U)
20840 #define PWR_PDCRI_PD13_Msk                  (0x1UL << PWR_PDCRI_PD13_Pos)           /*!< 0x00002000 */
20841 #define PWR_PDCRI_PD13                      PWR_PDCRI_PD13_Msk                      /*!< Apply pull-down for PI13 */
20842 #define PWR_PDCRI_PD14_Pos                  (14U)
20843 #define PWR_PDCRI_PD14_Msk                  (0x1UL << PWR_PDCRI_PD14_Pos)           /*!< 0x00004000 */
20844 #define PWR_PDCRI_PD14                      PWR_PDCRI_PD14_Msk                      /*!< Apply pull-down for PI14 */
20845 #define PWR_PDCRI_PD15_Pos                  (15U)
20846 #define PWR_PDCRI_PD15_Msk                  (0x1UL << PWR_PDCRI_PD15_Pos)           /*!< 0x00008000 */
20847 #define PWR_PDCRI_PD15                      PWR_PDCRI_PD15_Msk                      /*!< Apply pull-down for PI15 */
20848 /********************  Bit definition for PWR_PUCRJ register  *****************/
20849 #define PWR_PUCRJ_PU0_Pos                   (0U)
20850 #define PWR_PUCRJ_PU0_Msk                   (0x1UL << PWR_PUCRJ_PU0_Pos)            /*!< 0x00000001 */
20851 #define PWR_PUCRJ_PU0                       PWR_PUCRJ_PU0_Msk                       /*!< Apply pull-up for PJ0  */
20852 #define PWR_PUCRJ_PU1_Pos                   (1U)
20853 #define PWR_PUCRJ_PU1_Msk                   (0x1UL << PWR_PUCRJ_PU1_Pos)            /*!< 0x00000002 */
20854 #define PWR_PUCRJ_PU1                       PWR_PUCRJ_PU1_Msk                       /*!< Apply pull-up for PJ1  */
20855 #define PWR_PUCRJ_PU2_Pos                   (2U)
20856 #define PWR_PUCRJ_PU2_Msk                   (0x1UL << PWR_PUCRJ_PU2_Pos)            /*!< 0x00000004 */
20857 #define PWR_PUCRJ_PU2                       PWR_PUCRJ_PU2_Msk                       /*!< Apply pull-up for PJ2  */
20858 #define PWR_PUCRJ_PU3_Pos                   (3U)
20859 #define PWR_PUCRJ_PU3_Msk                   (0x1UL << PWR_PUCRJ_PU3_Pos)            /*!< 0x00000008 */
20860 #define PWR_PUCRJ_PU3                       PWR_PUCRJ_PU3_Msk                       /*!< Apply pull-up for PJ3  */
20861 #define PWR_PUCRJ_PU4_Pos                   (4U)
20862 #define PWR_PUCRJ_PU4_Msk                   (0x1UL << PWR_PUCRJ_PU4_Pos)            /*!< 0x00000010 */
20863 #define PWR_PUCRJ_PU4                       PWR_PUCRJ_PU4_Msk                       /*!< Apply pull-up for PJ4  */
20864 #define PWR_PUCRJ_PU5_Pos                   (5U)
20865 #define PWR_PUCRJ_PU5_Msk                   (0x1UL << PWR_PUCRJ_PU5_Pos)            /*!< 0x00000020 */
20866 #define PWR_PUCRJ_PU5                       PWR_PUCRJ_PU5_Msk                       /*!< Apply pull-up for PJ5  */
20867 #define PWR_PUCRJ_PU6_Pos                   (6U)
20868 #define PWR_PUCRJ_PU6_Msk                   (0x1UL << PWR_PUCRJ_PU6_Pos)            /*!< 0x00000040 */
20869 #define PWR_PUCRJ_PU6                       PWR_PUCRJ_PU6_Msk                       /*!< Apply pull-up for PJ6  */
20870 #define PWR_PUCRJ_PU7_Pos                   (7U)
20871 #define PWR_PUCRJ_PU7_Msk                   (0x1UL << PWR_PUCRJ_PU7_Pos)            /*!< 0x00000080 */
20872 #define PWR_PUCRJ_PU7                       PWR_PUCRJ_PU7_Msk                       /*!< Apply pull-up for PJ7  */
20873 #define PWR_PUCRJ_PU8_Pos                   (8U)
20874 #define PWR_PUCRJ_PU8_Msk                   (0x1UL << PWR_PUCRJ_PU8_Pos)            /*!< 0x00000100 */
20875 #define PWR_PUCRJ_PU8                       PWR_PUCRJ_PU8_Msk                       /*!< Apply pull-up for PJ8  */
20876 #define PWR_PUCRJ_PU9_Pos                   (9U)
20877 #define PWR_PUCRJ_PU9_Msk                   (0x1UL << PWR_PUCRJ_PU9_Pos)            /*!< 0x00000200 */
20878 #define PWR_PUCRJ_PU9                       PWR_PUCRJ_PU9_Msk                       /*!< Apply pull-up for PJ9  */
20879 #define PWR_PUCRJ_PU10_Pos                  (10U)
20880 #define PWR_PUCRJ_PU10_Msk                  (0x1UL << PWR_PUCRJ_PU10_Pos)           /*!< 0x00000400 */
20881 #define PWR_PUCRJ_PU10                      PWR_PUCRJ_PU10_Msk                      /*!< Apply pull-up for PJ10 */
20882 #define PWR_PUCRJ_PU11_Pos                  (11U)
20883 #define PWR_PUCRJ_PU11_Msk                  (0x1UL << PWR_PUCRJ_PU11_Pos)           /*!< 0x00000800 */
20884 #define PWR_PUCRJ_PU11                      PWR_PUCRJ_PU11_Msk                      /*!< Apply pull-up for PJ11 */
20885 
20886 /********************  Bit definition for PWR_PDCRJ register  *****************/
20887 #define PWR_PDCRJ_PD0_Pos                   (0U)
20888 #define PWR_PDCRJ_PD0_Msk                   (0x1UL << PWR_PDCRJ_PD0_Pos)            /*!< 0x00000001 */
20889 #define PWR_PDCRJ_PD0                       PWR_PDCRJ_PD0_Msk                       /*!< Apply pull-down for PJ0  */
20890 #define PWR_PDCRJ_PD1_Pos                   (1U)
20891 #define PWR_PDCRJ_PD1_Msk                   (0x1UL << PWR_PDCRJ_PD1_Pos)            /*!< 0x00000002 */
20892 #define PWR_PDCRJ_PD1                       PWR_PDCRJ_PD1_Msk                       /*!< Apply pull-down for PJ1  */
20893 #define PWR_PDCRJ_PD2_Pos                   (2U)
20894 #define PWR_PDCRJ_PD2_Msk                   (0x1UL << PWR_PDCRJ_PD2_Pos)            /*!< 0x00000004 */
20895 #define PWR_PDCRJ_PD2                       PWR_PDCRJ_PD2_Msk                       /*!< Apply pull-down for PJ2  */
20896 #define PWR_PDCRJ_PD3_Pos                   (3U)
20897 #define PWR_PDCRJ_PD3_Msk                   (0x1UL << PWR_PDCRJ_PD3_Pos)            /*!< 0x00000008 */
20898 #define PWR_PDCRJ_PD3                       PWR_PDCRJ_PD3_Msk                       /*!< Apply pull-down for PJ3  */
20899 #define PWR_PDCRJ_PD4_Pos                   (4U)
20900 #define PWR_PDCRJ_PD4_Msk                   (0x1UL << PWR_PDCRJ_PD4_Pos)            /*!< 0x00000010 */
20901 #define PWR_PDCRJ_PD4                       PWR_PDCRJ_PD4_Msk                       /*!< Apply pull-down for PJ4  */
20902 #define PWR_PDCRJ_PD5_Pos                   (5U)
20903 #define PWR_PDCRJ_PD5_Msk                   (0x1UL << PWR_PDCRJ_PD5_Pos)            /*!< 0x00000020 */
20904 #define PWR_PDCRJ_PD5                       PWR_PDCRJ_PD5_Msk                       /*!< Apply pull-down for PJ5  */
20905 #define PWR_PDCRJ_PD6_Pos                   (6U)
20906 #define PWR_PDCRJ_PD6_Msk                   (0x1UL << PWR_PDCRJ_PD6_Pos)            /*!< 0x00000040 */
20907 #define PWR_PDCRJ_PD6                       PWR_PDCRJ_PD6_Msk                       /*!< Apply pull-down for PJ6  */
20908 #define PWR_PDCRJ_PD7_Pos                   (7U)
20909 #define PWR_PDCRJ_PD7_Msk                   (0x1UL << PWR_PDCRJ_PD7_Pos)            /*!< 0x00000080 */
20910 #define PWR_PDCRJ_PD7                       PWR_PDCRJ_PD7_Msk                       /*!< Apply pull-down for PJ7  */
20911 #define PWR_PDCRJ_PD8_Pos                   (8U)
20912 #define PWR_PDCRJ_PD8_Msk                   (0x1UL << PWR_PDCRJ_PD8_Pos)            /*!< 0x00000100 */
20913 #define PWR_PDCRJ_PD8                       PWR_PDCRJ_PD8_Msk                       /*!< Apply pull-down for PJ8  */
20914 #define PWR_PDCRJ_PD9_Pos                   (9U)
20915 #define PWR_PDCRJ_PD9_Msk                   (0x1UL << PWR_PDCRJ_PD9_Pos)            /*!< 0x00000200 */
20916 #define PWR_PDCRJ_PD9                       PWR_PDCRJ_PD9_Msk                       /*!< Apply pull-down for PJ9  */
20917 #define PWR_PDCRJ_PD10_Pos                  (10U)
20918 #define PWR_PDCRJ_PD10_Msk                  (0x1UL << PWR_PDCRJ_PD10_Pos)           /*!< 0x00000400 */
20919 #define PWR_PDCRJ_PD10                      PWR_PDCRJ_PD10_Msk                      /*!< Apply pull-down for PJ10 */
20920 #define PWR_PDCRJ_PD11_Pos                  (11U)
20921 #define PWR_PDCRJ_PD11_Msk                  (0x1UL << PWR_PDCRJ_PD11_Pos)           /*!< 0x00000800 */
20922 #define PWR_PDCRJ_PD11                      PWR_PDCRJ_PD11_Msk                      /*!< Apply pull-down for PJ11 */
20923 
20924 /********************  Bit definition for PWR_CR4 register  *******************/
20925 #define PWR_CR4_SRAM1PDS4_Pos               (0U)
20926 #define PWR_CR4_SRAM1PDS4_Msk               (0x1UL << PWR_CR4_SRAM1PDS4_Pos)        /*!< 0x00000001 */
20927 #define PWR_CR4_SRAM1PDS4                   PWR_CR4_SRAM1PDS4_Msk                   /*!< SRAM1 page 4 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20928 #define PWR_CR4_SRAM1PDS5_Pos               (1U)
20929 #define PWR_CR4_SRAM1PDS5_Msk               (0x1UL << PWR_CR4_SRAM1PDS5_Pos)        /*!< 0x00000002 */
20930 #define PWR_CR4_SRAM1PDS5                   PWR_CR4_SRAM1PDS5_Msk                   /*!< SRAM1 page 5 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20931 #define PWR_CR4_SRAM1PDS6_Pos               (2U)
20932 #define PWR_CR4_SRAM1PDS6_Msk               (0x1UL << PWR_CR4_SRAM1PDS6_Pos)        /*!< 0x00000004 */
20933 #define PWR_CR4_SRAM1PDS6                   PWR_CR4_SRAM1PDS6_Msk                   /*!< SRAM1 page 6 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20934 #define PWR_CR4_SRAM1PDS7_Pos               (3U)
20935 #define PWR_CR4_SRAM1PDS7_Msk               (0x1UL << PWR_CR4_SRAM1PDS7_Pos)        /*!< 0x00000008 */
20936 #define PWR_CR4_SRAM1PDS7                   PWR_CR4_SRAM1PDS7_Msk                   /*!< SRAM1 page 7 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20937 #define PWR_CR4_SRAM1PDS8_Pos               (4U)
20938 #define PWR_CR4_SRAM1PDS8_Msk               (0x1UL << PWR_CR4_SRAM1PDS8_Pos)        /*!< 0x00000010 */
20939 #define PWR_CR4_SRAM1PDS8                   PWR_CR4_SRAM1PDS8_Msk                   /*!< SRAM1 page 8 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20940 #define PWR_CR4_SRAM1PDS9_Pos               (5U)
20941 #define PWR_CR4_SRAM1PDS9_Msk               (0x1UL << PWR_CR4_SRAM1PDS9_Pos)        /*!< 0x00000020 */
20942 #define PWR_CR4_SRAM1PDS9                   PWR_CR4_SRAM1PDS9_Msk                   /*!< SRAM1 page 9 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20943 #define PWR_CR4_SRAM1PDS10_Pos              (6U)
20944 #define PWR_CR4_SRAM1PDS10_Msk              (0x1UL << PWR_CR4_SRAM1PDS10_Pos)       /*!< 0x00000040 */
20945 #define PWR_CR4_SRAM1PDS10                  PWR_CR4_SRAM1PDS10_Msk                  /*!< SRAM1 page 10 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
20946 #define PWR_CR4_SRAM1PDS11_Pos              (7U)
20947 #define PWR_CR4_SRAM1PDS11_Msk              (0x1UL << PWR_CR4_SRAM1PDS11_Pos)       /*!< 0x00000080 */
20948 #define PWR_CR4_SRAM1PDS11                  PWR_CR4_SRAM1PDS11_Msk                  /*!< SRAM1 page 11 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
20949 #define PWR_CR4_SRAM1PDS12_Pos              (8U)
20950 #define PWR_CR4_SRAM1PDS12_Msk              (0x1UL << PWR_CR4_SRAM1PDS12_Pos)       /*!< 0x00000100 */
20951 #define PWR_CR4_SRAM1PDS12                  PWR_CR4_SRAM1PDS12_Msk                  /*!< SRAM1 page 12 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
20952 #define PWR_CR4_SRAM3PDS9_Pos               (10U)
20953 #define PWR_CR4_SRAM3PDS9_Msk               (0x1UL << PWR_CR4_SRAM3PDS9_Pos)        /*!< 0x00000400 */
20954 #define PWR_CR4_SRAM3PDS9                   PWR_CR4_SRAM3PDS9_Msk                   /*!< SRAM3 page 9 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20955 #define PWR_CR4_SRAM3PDS10_Pos              (11U)
20956 #define PWR_CR4_SRAM3PDS10_Msk              (0x1UL << PWR_CR4_SRAM3PDS10_Pos)       /*!< 0x00000800 */
20957 #define PWR_CR4_SRAM3PDS10                  PWR_CR4_SRAM3PDS10_Msk                  /*!< SRAM3 page 10 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
20958 #define PWR_CR4_SRAM3PDS11_Pos              (12U)
20959 #define PWR_CR4_SRAM3PDS11_Msk              (0x1UL << PWR_CR4_SRAM3PDS11_Pos)       /*!< 0x00001000 */
20960 #define PWR_CR4_SRAM3PDS11                  PWR_CR4_SRAM3PDS11_Msk                  /*!< SRAM3 page 11 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
20961 #define PWR_CR4_SRAM3PDS12_Pos              (13U)
20962 #define PWR_CR4_SRAM3PDS12_Msk              (0x1UL << PWR_CR4_SRAM3PDS12_Pos)       /*!< 0x00002000 */
20963 #define PWR_CR4_SRAM3PDS12                  PWR_CR4_SRAM3PDS12_Msk                  /*!< SRAM3 page 12 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
20964 #define PWR_CR4_SRAM3PDS13_Pos              (14U)
20965 #define PWR_CR4_SRAM3PDS13_Msk              (0x1UL << PWR_CR4_SRAM3PDS13_Pos)       /*!< 0x00004000 */
20966 #define PWR_CR4_SRAM3PDS13                  PWR_CR4_SRAM3PDS13_Msk                  /*!< SRAM3 page 13 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
20967 #define PWR_CR4_SRAM5PDS1_Pos               (16U)
20968 #define PWR_CR4_SRAM5PDS1_Msk               (0x1UL << PWR_CR4_SRAM5PDS1_Pos)        /*!< 0x00010000 */
20969 #define PWR_CR4_SRAM5PDS1                   PWR_CR4_SRAM5PDS1_Msk                   /*!< SRAM5 page 1 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20970 #define PWR_CR4_SRAM5PDS2_Pos               (17U)
20971 #define PWR_CR4_SRAM5PDS2_Msk               (0x1UL << PWR_CR4_SRAM5PDS2_Pos)        /*!< 0x00020000 */
20972 #define PWR_CR4_SRAM5PDS2                   PWR_CR4_SRAM5PDS2_Msk                   /*!< SRAM5 page 2 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20973 #define PWR_CR4_SRAM5PDS3_Pos               (18U)
20974 #define PWR_CR4_SRAM5PDS3_Msk               (0x1UL << PWR_CR4_SRAM5PDS3_Pos)        /*!< 0x00040000 */
20975 #define PWR_CR4_SRAM5PDS3                   PWR_CR4_SRAM5PDS3_Msk                   /*!< SRAM5 page 3 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20976 #define PWR_CR4_SRAM5PDS4_Pos               (19U)
20977 #define PWR_CR4_SRAM5PDS4_Msk               (0x1UL << PWR_CR4_SRAM5PDS4_Pos)        /*!< 0x00080000 */
20978 #define PWR_CR4_SRAM5PDS4                   PWR_CR4_SRAM5PDS4_Msk                   /*!< SRAM5 page 4 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20979 #define PWR_CR4_SRAM5PDS5_Pos               (20U)
20980 #define PWR_CR4_SRAM5PDS5_Msk               (0x1UL << PWR_CR4_SRAM5PDS5_Pos)        /*!< 0x00100000 */
20981 #define PWR_CR4_SRAM5PDS5                   PWR_CR4_SRAM5PDS5_Msk                   /*!< SRAM5 page 5 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20982 #define PWR_CR4_SRAM5PDS6_Pos               (21U)
20983 #define PWR_CR4_SRAM5PDS6_Msk               (0x1UL << PWR_CR4_SRAM5PDS6_Pos)        /*!< 0x00200000 */
20984 #define PWR_CR4_SRAM5PDS6                   PWR_CR4_SRAM5PDS6_Msk                   /*!< SRAM5 page 6 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20985 #define PWR_CR4_SRAM5PDS7_Pos               (22U)
20986 #define PWR_CR4_SRAM5PDS7_Msk               (0x1UL << PWR_CR4_SRAM5PDS7_Pos)        /*!< 0x00400000 */
20987 #define PWR_CR4_SRAM5PDS7                   PWR_CR4_SRAM5PDS7_Msk                   /*!< SRAM5 page 7 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20988 #define PWR_CR4_SRAM5PDS8_Pos               (23U)
20989 #define PWR_CR4_SRAM5PDS8_Msk               (0x1UL << PWR_CR4_SRAM5PDS8_Pos)        /*!< 0x00800000 */
20990 #define PWR_CR4_SRAM5PDS8                   PWR_CR4_SRAM5PDS8_Msk                   /*!< SRAM5 page 8 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20991 #define PWR_CR4_SRAM5PDS9_Pos               (24U)
20992 #define PWR_CR4_SRAM5PDS9_Msk               (0x1UL << PWR_CR4_SRAM5PDS9_Pos)        /*!< 0x01000000 */
20993 #define PWR_CR4_SRAM5PDS9                   PWR_CR4_SRAM5PDS9_Msk                   /*!< SRAM5 page 9 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3)  */
20994 #define PWR_CR4_SRAM5PDS10_Pos              (25U)
20995 #define PWR_CR4_SRAM5PDS10_Msk              (0x1UL << PWR_CR4_SRAM5PDS10_Pos)       /*!< 0x02000000 */
20996 #define PWR_CR4_SRAM5PDS10                  PWR_CR4_SRAM5PDS10_Msk                  /*!< SRAM5 page 10 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
20997 #define PWR_CR4_SRAM5PDS11_Pos              (26U)
20998 #define PWR_CR4_SRAM5PDS11_Msk              (0x1UL << PWR_CR4_SRAM5PDS11_Pos)       /*!< 0x04000000 */
20999 #define PWR_CR4_SRAM5PDS11                  PWR_CR4_SRAM5PDS11_Msk                  /*!< SRAM5 page 11 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
21000 #define PWR_CR4_SRAM5PDS12_Pos              (27U)
21001 #define PWR_CR4_SRAM5PDS12_Msk              (0x1UL << PWR_CR4_SRAM5PDS12_Pos)       /*!< 0x08000000 */
21002 #define PWR_CR4_SRAM5PDS12                  PWR_CR4_SRAM5PDS12_Msk                  /*!< SRAM5 page 12 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
21003 #define PWR_CR4_SRAM5PDS13_Pos              (28U)
21004 #define PWR_CR4_SRAM5PDS13_Msk              (0x1UL << PWR_CR4_SRAM5PDS13_Pos)       /*!< 0x10000000 */
21005 #define PWR_CR4_SRAM5PDS13                  PWR_CR4_SRAM5PDS13_Msk                  /*!< SRAM5 page 13 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
21006 /********************  Bit definition for PWR_CR5 register  *******************/
21007 #define PWR_CR5_SRAM6PDS1_Pos               (0U)
21008 #define PWR_CR5_SRAM6PDS1_Msk               (0x1UL << PWR_CR5_SRAM6PDS1_Pos)       /*!< 0x00000001 */
21009 #define PWR_CR5_SRAM6PDS1                   PWR_CR5_SRAM6PDS1_Msk                  /*!< SRAM6 page 1 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
21010 #define PWR_CR5_SRAM6PDS2_Pos               (1U)
21011 #define PWR_CR5_SRAM6PDS2_Msk               (0x1UL << PWR_CR5_SRAM6PDS2_Pos)       /*!< 0x00000002 */
21012 #define PWR_CR5_SRAM6PDS2                   PWR_CR5_SRAM6PDS2_Msk                  /*!< SRAM6 page 2 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
21013 #define PWR_CR5_SRAM6PDS3_Pos               (2U)
21014 #define PWR_CR5_SRAM6PDS3_Msk               (0x1UL << PWR_CR5_SRAM6PDS3_Pos)       /*!< 0x00000004 */
21015 #define PWR_CR5_SRAM6PDS3                   PWR_CR5_SRAM6PDS3_Msk                  /*!< SRAM6 page 3 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
21016 #define PWR_CR5_SRAM6PDS4_Pos               (3U)
21017 #define PWR_CR5_SRAM6PDS4_Msk               (0x1UL << PWR_CR5_SRAM6PDS4_Pos)       /*!< 0x00000008 */
21018 #define PWR_CR5_SRAM6PDS4                   PWR_CR5_SRAM6PDS4_Msk                  /*!< SRAM6 page 4 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
21019 #define PWR_CR5_SRAM6PDS5_Pos               (4U)
21020 #define PWR_CR5_SRAM6PDS5_Msk               (0x1UL << PWR_CR5_SRAM6PDS5_Pos)       /*!< 0x00000010 */
21021 #define PWR_CR5_SRAM6PDS5                   PWR_CR5_SRAM6PDS5_Msk                  /*!< SRAM6 page 5 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
21022 #define PWR_CR5_SRAM6PDS6_Pos               (5U)
21023 #define PWR_CR5_SRAM6PDS6_Msk               (0x1UL << PWR_CR5_SRAM6PDS6_Pos)       /*!< 0x00000020 */
21024 #define PWR_CR5_SRAM6PDS6                   PWR_CR5_SRAM6PDS6_Msk                  /*!< SRAM6 page 6 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
21025 #define PWR_CR5_SRAM6PDS7_Pos               (6U)
21026 #define PWR_CR5_SRAM6PDS7_Msk               (0x1UL << PWR_CR5_SRAM6PDS7_Pos)       /*!< 0x00000040 */
21027 #define PWR_CR5_SRAM6PDS7                   PWR_CR5_SRAM6PDS7_Msk                  /*!< SRAM6 page 7 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
21028 #define PWR_CR5_SRAM6PDS8_Pos               (7U)
21029 #define PWR_CR5_SRAM6PDS8_Msk               (0x1UL << PWR_CR5_SRAM6PDS8_Pos)       /*!< 0x00000080 */
21030 #define PWR_CR5_SRAM6PDS8                   PWR_CR5_SRAM6PDS8_Msk                  /*!< SRAM6 page 8 (64 KB) power-down in Stop modes (Stop 0, 1, 2, 3) */
21031 
21032 /******************************************************************************/
21033 /*                                                                            */
21034 /*                      SRAMs configuration controller                        */
21035 /*                                                                            */
21036 /******************************************************************************/
21037 /*******************  Bit definition for RAMCFG_CR register  ******************/
21038 #define RAMCFG_CR_ECCE_Pos                  (0U)
21039 #define RAMCFG_CR_ECCE_Msk                  (0x1UL << RAMCFG_CR_ECCE_Pos)           /*!< 0x00000001 */
21040 #define RAMCFG_CR_ECCE                      RAMCFG_CR_ECCE_Msk                      /*!< ECC Enable */
21041 #define RAMCFG_CR_ALE_Pos                   (4U)
21042 #define RAMCFG_CR_ALE_Msk                   (0x1UL << RAMCFG_CR_ALE_Pos)            /*!< 0x00000010 */
21043 #define RAMCFG_CR_ALE                       RAMCFG_CR_ALE_Msk                       /*!< Address Latching Enable */
21044 #define RAMCFG_CR_SRAMER_Pos                (8U)
21045 #define RAMCFG_CR_SRAMER_Msk                (0x1UL << RAMCFG_CR_SRAMER_Pos)         /*!< 0x00000100 */
21046 #define RAMCFG_CR_SRAMER                    RAMCFG_CR_SRAMER_Msk                    /*!< Start Erase */
21047 #define RAMCFG_CR_WSC_Pos                   (16U)
21048 #define RAMCFG_CR_WSC_Msk                   (0x7UL << RAMCFG_CR_WSC_Pos)            /*!< 0x00070000 */
21049 #define RAMCFG_CR_WSC                       RAMCFG_CR_WSC_Msk                       /*!< WSC[18:16] Wait State Configuration field */
21050 #define RAMCFG_CR_WSC_0                     (0x1UL << RAMCFG_CR_WSC_Pos)            /*!< 0x00010000 */
21051 #define RAMCFG_CR_WSC_1                     (0x2UL << RAMCFG_CR_WSC_Pos)            /*!< 0x00020000 */
21052 #define RAMCFG_CR_WSC_2                     (0x4UL << RAMCFG_CR_WSC_Pos)            /*!< 0x00040000 */
21053 
21054 /*******************  Bit definition for RAMCFG_IER register  *****************/
21055 #define RAMCFG_IER_SEIE_Pos                 (0U)
21056 #define RAMCFG_IER_SEIE_Msk                 (0x1UL << RAMCFG_IER_SEIE_Pos)          /*!< 0x00000001 */
21057 #define RAMCFG_IER_SEIE                     RAMCFG_IER_SEIE_Msk                     /*!< Single Error Interrupt Enable */
21058 #define RAMCFG_IER_DEIE_Pos                 (1U)
21059 #define RAMCFG_IER_DEIE_Msk                 (0x1UL << RAMCFG_IER_DEIE_Pos)          /*!< 0x00000002 */
21060 #define RAMCFG_IER_DEIE                     RAMCFG_IER_DEIE_Msk                     /*!< Double Error Interrupt Enable */
21061 #define RAMCFG_IER_ECCNMI_Pos               (3U)
21062 #define RAMCFG_IER_ECCNMI_Msk               (0x1UL << RAMCFG_IER_ECCNMI_Pos)        /*!< 0x00000008 */
21063 #define RAMCFG_IER_ECCNMI                   RAMCFG_IER_ECCNMI_Msk                   /*!< NMI redirection interrupt */
21064 
21065 /*******************  Bit definition for RAMCFG_ISR register  *****************/
21066 #define RAMCFG_ISR_SEDC_Pos                 (0U)
21067 #define RAMCFG_ISR_SEDC_Msk                 (0x1UL << RAMCFG_ISR_SEDC_Pos)          /*!< 0x00000001 */
21068 #define RAMCFG_ISR_SEDC                     RAMCFG_ISR_SEDC_Msk                     /*!< Single Error Detected and Corrected flag */
21069 #define RAMCFG_ISR_DED_Pos                  (1U)
21070 #define RAMCFG_ISR_DED_Msk                  (0x1UL << RAMCFG_ISR_DED_Pos)           /*!< 0x00000002 */
21071 #define RAMCFG_ISR_DED                      RAMCFG_ISR_DED_Msk                      /*!< Double Error Detected flag */
21072 #define RAMCFG_ISR_SRAMBUSY_Pos             (8U)
21073 #define RAMCFG_ISR_SRAMBUSY_Msk             (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos)      /*!< 0x00000100 */
21074 #define RAMCFG_ISR_SRAMBUSY                 RAMCFG_ISR_SRAMBUSY_Msk                 /*!< SRAM busy flag */
21075 
21076 /*******************  Bit definition for RAMCFG_SEAR register  ****************/
21077 #define RAMCFG_SEAR_ESEA_Pos                (0U)
21078 #define RAMCFG_SEAR_ESEA_Msk                (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos)  /*!< 0xFFFFFFFF */
21079 #define RAMCFG_SEAR_ESEA                    RAMCFG_SEAR_ESEA_Msk                    /*!< ECC Single Error Address */
21080 
21081 /*******************  Bit definition for RAMCFG_DEAR register  ****************/
21082 #define RAMCFG_DEAR_EDEA_Pos                (0U)
21083 #define RAMCFG_DEAR_EDEA_Msk                (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos)  /*!< 0xFFFFFFFF */
21084 #define RAMCFG_DEAR_EDEA                    RAMCFG_DEAR_EDEA_Msk                    /*!< ECC Double Error Address */
21085 
21086 /*******************  Bit definition for RAMCFG_ICR register  *****************/
21087 #define RAMCFG_ICR_CSEDC_Pos                (0U)
21088 #define RAMCFG_ICR_CSEDC_Msk                (0x1UL << RAMCFG_ICR_CSEDC_Pos)         /*!< 0x00000001 */
21089 #define RAMCFG_ICR_CSEDC                    RAMCFG_ICR_CSEDC_Msk                    /*!< Clear ECC Single Error Detected and Corrected Flag */
21090 #define RAMCFG_ICR_CDED_Pos                 (1U)
21091 #define RAMCFG_ICR_CDED_Msk                 (0x1UL << RAMCFG_ICR_CDED_Pos)          /*!< 0x00000002 */
21092 #define RAMCFG_ICR_CDED                     RAMCFG_ICR_CDED_Msk                     /*!< Clear ECC Double Error Detected Flag*/
21093 
21094 /******************  Bit definition for RAMCFG_WPR1 register  *****************/
21095 #define RAMCFG_WPR1_P0WP_Pos                (0U)
21096 #define RAMCFG_WPR1_P0WP_Msk                (0x1UL << RAMCFG_WPR1_P0WP_Pos)         /*!< 0x00000001 */
21097 #define RAMCFG_WPR1_P0WP                    RAMCFG_WPR1_P0WP_Msk                    /*!< Write Protection Page 00 */
21098 #define RAMCFG_WPR1_P1WP_Pos                (1U)
21099 #define RAMCFG_WPR1_P1WP_Msk                (0x1UL << RAMCFG_WPR1_P1WP_Pos)         /*!< 0x00000002 */
21100 #define RAMCFG_WPR1_P1WP                    RAMCFG_WPR1_P1WP_Msk                    /*!< Write Protection Page 01 */
21101 #define RAMCFG_WPR1_P2WP_Pos                (2U)
21102 #define RAMCFG_WPR1_P2WP_Msk                (0x1UL << RAMCFG_WPR1_P2WP_Pos)         /*!< 0x00000004 */
21103 #define RAMCFG_WPR1_P2WP                    RAMCFG_WPR1_P2WP_Msk                    /*!< Write Protection Page 02 */
21104 #define RAMCFG_WPR1_P3WP_Pos                (3U)
21105 #define RAMCFG_WPR1_P3WP_Msk                (0x1UL << RAMCFG_WPR1_P3WP_Pos)         /*!< 0x00000008 */
21106 #define RAMCFG_WPR1_P3WP                    RAMCFG_WPR1_P3WP_Msk                    /*!< Write Protection Page 03 */
21107 #define RAMCFG_WPR1_P4WP_Pos                (4U)
21108 #define RAMCFG_WPR1_P4WP_Msk                (0x1UL << RAMCFG_WPR1_P4WP_Pos)         /*!< 0x00000010 */
21109 #define RAMCFG_WPR1_P4WP                    RAMCFG_WPR1_P4WP_Msk                    /*!< Write Protection Page 04 */
21110 #define RAMCFG_WPR1_P5WP_Pos                (5U)
21111 #define RAMCFG_WPR1_P5WP_Msk                (0x1UL << RAMCFG_WPR1_P5WP_Pos)         /*!< 0x00000020 */
21112 #define RAMCFG_WPR1_P5WP                    RAMCFG_WPR1_P5WP_Msk                    /*!< Write Protection Page 05 */
21113 #define RAMCFG_WPR1_P6WP_Pos                (6U)
21114 #define RAMCFG_WPR1_P6WP_Msk                (0x1UL << RAMCFG_WPR1_P6WP_Pos)         /*!< 0x00000040 */
21115 #define RAMCFG_WPR1_P6WP                    RAMCFG_WPR1_P6WP_Msk                    /*!< Write Protection Page 06 */
21116 #define RAMCFG_WPR1_P7WP_Pos                (7U)
21117 #define RAMCFG_WPR1_P7WP_Msk                (0x1UL << RAMCFG_WPR1_P7WP_Pos)         /*!< 0x00000080 */
21118 #define RAMCFG_WPR1_P7WP                    RAMCFG_WPR1_P7WP_Msk                    /*!< Write Protection Page 07 */
21119 #define RAMCFG_WPR1_P8WP_Pos                (8U)
21120 #define RAMCFG_WPR1_P8WP_Msk                (0x1UL << RAMCFG_WPR1_P8WP_Pos)         /*!< 0x00000100 */
21121 #define RAMCFG_WPR1_P8WP                    RAMCFG_WPR1_P8WP_Msk                    /*!< Write Protection Page 08 */
21122 #define RAMCFG_WPR1_P9WP_Pos                (9U)
21123 #define RAMCFG_WPR1_P9WP_Msk                (0x1UL << RAMCFG_WPR1_P9WP_Pos)         /*!< 0x00000200 */
21124 #define RAMCFG_WPR1_P9WP                    RAMCFG_WPR1_P9WP_Msk                    /*!< Write Protection Page 09 */
21125 #define RAMCFG_WPR1_P10WP_Pos               (10U)
21126 #define RAMCFG_WPR1_P10WP_Msk               (0x1UL << RAMCFG_WPR1_P10WP_Pos)        /*!< 0x00000400 */
21127 #define RAMCFG_WPR1_P10WP                   RAMCFG_WPR1_P10WP_Msk                   /*!< Write Protection Page 10 */
21128 #define RAMCFG_WPR1_P11WP_Pos               (11U)
21129 #define RAMCFG_WPR1_P11WP_Msk               (0x1UL << RAMCFG_WPR1_P11WP_Pos)        /*!< 0x00000800 */
21130 #define RAMCFG_WPR1_P11WP                   RAMCFG_WPR1_P11WP_Msk                   /*!< Write Protection Page 11 */
21131 #define RAMCFG_WPR1_P12WP_Pos               (12U)
21132 #define RAMCFG_WPR1_P12WP_Msk               (0x1UL << RAMCFG_WPR1_P12WP_Pos)        /*!< 0x00001000 */
21133 #define RAMCFG_WPR1_P12WP                   RAMCFG_WPR1_P12WP_Msk                   /*!< Write Protection Page 12 */
21134 #define RAMCFG_WPR1_P13WP_Pos               (13U)
21135 #define RAMCFG_WPR1_P13WP_Msk               (0x1UL << RAMCFG_WPR1_P13WP_Pos)        /*!< 0x00002000 */
21136 #define RAMCFG_WPR1_P13WP                   RAMCFG_WPR1_P13WP_Msk                   /*!< Write Protection Page 13 */
21137 #define RAMCFG_WPR1_P14WP_Pos               (14U)
21138 #define RAMCFG_WPR1_P14WP_Msk               (0x1UL << RAMCFG_WPR1_P14WP_Pos)        /*!< 0x00004000 */
21139 #define RAMCFG_WPR1_P14WP                   RAMCFG_WPR1_P14WP_Msk                   /*!< Write Protection Page 14 */
21140 #define RAMCFG_WPR1_P15WP_Pos               (15U)
21141 #define RAMCFG_WPR1_P15WP_Msk               (0x1UL << RAMCFG_WPR1_P15WP_Pos)        /*!< 0x00008000 */
21142 #define RAMCFG_WPR1_P15WP                   RAMCFG_WPR1_P15WP_Msk                   /*!< Write Protection Page 15 */
21143 #define RAMCFG_WPR1_P16WP_Pos               (16U)
21144 #define RAMCFG_WPR1_P16WP_Msk               (0x1UL << RAMCFG_WPR1_P16WP_Pos)        /*!< 0x00010000 */
21145 #define RAMCFG_WPR1_P16WP                   RAMCFG_WPR1_P16WP_Msk                   /*!< Write Protection Page 16 */
21146 #define RAMCFG_WPR1_P17WP_Pos               (17U)
21147 #define RAMCFG_WPR1_P17WP_Msk               (0x1UL << RAMCFG_WPR1_P17WP_Pos)        /*!< 0x00020000 */
21148 #define RAMCFG_WPR1_P17WP                   RAMCFG_WPR1_P17WP_Msk                   /*!< Write Protection Page 17 */
21149 #define RAMCFG_WPR1_P18WP_Pos               (18U)
21150 #define RAMCFG_WPR1_P18WP_Msk               (0x1UL << RAMCFG_WPR1_P18WP_Pos)        /*!< 0x00040000 */
21151 #define RAMCFG_WPR1_P18WP                   RAMCFG_WPR1_P18WP_Msk                   /*!< Write Protection Page 18 */
21152 #define RAMCFG_WPR1_P19WP_Pos               (19U)
21153 #define RAMCFG_WPR1_P19WP_Msk               (0x1UL << RAMCFG_WPR1_P19WP_Pos)        /*!< 0x00080000 */
21154 #define RAMCFG_WPR1_P19WP                   RAMCFG_WPR1_P19WP_Msk                   /*!< Write Protection Page 19 */
21155 #define RAMCFG_WPR1_P20WP_Pos               (20U)
21156 #define RAMCFG_WPR1_P20WP_Msk               (0x1UL << RAMCFG_WPR1_P20WP_Pos)        /*!< 0x00100000 */
21157 #define RAMCFG_WPR1_P20WP                   RAMCFG_WPR1_P20WP_Msk                   /*!< Write Protection Page 20 */
21158 #define RAMCFG_WPR1_P21WP_Pos               (21U)
21159 #define RAMCFG_WPR1_P21WP_Msk               (0x1UL << RAMCFG_WPR1_P21WP_Pos)        /*!< 0x00200000 */
21160 #define RAMCFG_WPR1_P21WP                   RAMCFG_WPR1_P21WP_Msk                   /*!< Write Protection Page 21 */
21161 #define RAMCFG_WPR1_P22WP_Pos               (22U)
21162 #define RAMCFG_WPR1_P22WP_Msk               (0x1UL << RAMCFG_WPR1_P22WP_Pos)        /*!< 0x00400000 */
21163 #define RAMCFG_WPR1_P22WP                   RAMCFG_WPR1_P22WP_Msk                   /*!< Write Protection Page 22 */
21164 #define RAMCFG_WPR1_P23WP_Pos               (23U)
21165 #define RAMCFG_WPR1_P23WP_Msk               (0x1UL << RAMCFG_WPR1_P23WP_Pos)        /*!< 0x00800000 */
21166 #define RAMCFG_WPR1_P23WP                   RAMCFG_WPR1_P23WP_Msk                   /*!< Write Protection Page 23 */
21167 #define RAMCFG_WPR1_P24WP_Pos               (24U)
21168 #define RAMCFG_WPR1_P24WP_Msk               (0x1UL << RAMCFG_WPR1_P24WP_Pos)        /*!< 0x01000000 */
21169 #define RAMCFG_WPR1_P24WP                   RAMCFG_WPR1_P24WP_Msk                   /*!< Write Protection Page 24 */
21170 #define RAMCFG_WPR1_P25WP_Pos               (25U)
21171 #define RAMCFG_WPR1_P25WP_Msk               (0x1UL << RAMCFG_WPR1_P25WP_Pos)        /*!< 0x02000000 */
21172 #define RAMCFG_WPR1_P25WP                   RAMCFG_WPR1_P25WP_Msk                   /*!< Write Protection Page 25 */
21173 #define RAMCFG_WPR1_P26WP_Pos               (26U)
21174 #define RAMCFG_WPR1_P26WP_Msk               (0x1UL << RAMCFG_WPR1_P26WP_Pos)        /*!< 0x04000000 */
21175 #define RAMCFG_WPR1_P26WP                   RAMCFG_WPR1_P26WP_Msk                   /*!< Write Protection Page 26 */
21176 #define RAMCFG_WPR1_P27WP_Pos               (27U)
21177 #define RAMCFG_WPR1_P27WP_Msk               (0x1UL << RAMCFG_WPR1_P27WP_Pos)        /*!< 0x08000000 */
21178 #define RAMCFG_WPR1_P27WP                   RAMCFG_WPR1_P27WP_Msk                   /*!< Write Protection Page 27 */
21179 #define RAMCFG_WPR1_P28WP_Pos               (28U)
21180 #define RAMCFG_WPR1_P28WP_Msk               (0x1UL << RAMCFG_WPR1_P28WP_Pos)        /*!< 0x10000000 */
21181 #define RAMCFG_WPR1_P28WP                   RAMCFG_WPR1_P28WP_Msk                   /*!< Write Protection Page 28 */
21182 #define RAMCFG_WPR1_P29WP_Pos               (29U)
21183 #define RAMCFG_WPR1_P29WP_Msk               (0x1UL << RAMCFG_WPR1_P29WP_Pos)        /*!< 0x20000000 */
21184 #define RAMCFG_WPR1_P29WP                   RAMCFG_WPR1_P29WP_Msk                   /*!< Write Protection Page 29 */
21185 #define RAMCFG_WPR1_P30WP_Pos               (30U)
21186 #define RAMCFG_WPR1_P30WP_Msk               (0x1UL << RAMCFG_WPR1_P30WP_Pos)        /*!< 0x40000000 */
21187 #define RAMCFG_WPR1_P30WP                   RAMCFG_WPR1_P30WP_Msk                   /*!< Write Protection Page 30 */
21188 #define RAMCFG_WPR1_P31WP_Pos               (31U)
21189 #define RAMCFG_WPR1_P31WP_Msk               (0x1UL << RAMCFG_WPR1_P31WP_Pos)        /*!< 0x80000000 */
21190 #define RAMCFG_WPR1_P31WP                   RAMCFG_WPR1_P31WP_Msk                   /*!< Write Protection Page 31 */
21191 
21192 /******************  Bit definition for RAMCFG_WPR2 register  ****************/
21193 #define RAMCFG_WPR2_P32WP_Pos               (0U)
21194 #define RAMCFG_WPR2_P32WP_Msk               (0x1UL << RAMCFG_WPR2_P32WP_Pos)        /*!< 0x00000001 */
21195 #define RAMCFG_WPR2_P32WP                   RAMCFG_WPR2_P32WP_Msk                   /*!< Write Protection Page 32 */
21196 #define RAMCFG_WPR2_P33WP_Pos               (1U)
21197 #define RAMCFG_WPR2_P33WP_Msk               (0x1UL << RAMCFG_WPR2_P33WP_Pos)        /*!< 0x00000002 */
21198 #define RAMCFG_WPR2_P33WP                   RAMCFG_WPR2_P33WP_Msk                   /*!< Write Protection Page 33 */
21199 #define RAMCFG_WPR2_P34WP_Pos               (2U)
21200 #define RAMCFG_WPR2_P34WP_Msk               (0x1UL << RAMCFG_WPR2_P34WP_Pos)        /*!< 0x00000004 */
21201 #define RAMCFG_WPR2_P34WP                   RAMCFG_WPR2_P34WP_Msk                   /*!< Write Protection Page 34 */
21202 #define RAMCFG_WPR2_P35WP_Pos               (3U)
21203 #define RAMCFG_WPR2_P35WP_Msk               (0x1UL << RAMCFG_WPR2_P35WP_Pos)        /*!< 0x00000008 */
21204 #define RAMCFG_WPR2_P35WP                   RAMCFG_WPR2_P35WP_Msk                   /*!< Write Protection Page 35 */
21205 #define RAMCFG_WPR2_P36WP_Pos               (4U)
21206 #define RAMCFG_WPR2_P36WP_Msk               (0x1UL << RAMCFG_WPR2_P36WP_Pos)        /*!< 0x00000010 */
21207 #define RAMCFG_WPR2_P36WP                   RAMCFG_WPR2_P36WP_Msk                   /*!< Write Protection Page 36 */
21208 #define RAMCFG_WPR2_P37WP_Pos               (5U)
21209 #define RAMCFG_WPR2_P37WP_Msk               (0x1UL << RAMCFG_WPR2_P37WP_Pos)        /*!< 0x00000020 */
21210 #define RAMCFG_WPR2_P37WP                   RAMCFG_WPR2_P37WP_Msk                   /*!< Write Protection Page 37 */
21211 #define RAMCFG_WPR2_P38WP_Pos               (6U)
21212 #define RAMCFG_WPR2_P38WP_Msk               (0x1UL << RAMCFG_WPR2_P38WP_Pos)        /*!< 0x00000040 */
21213 #define RAMCFG_WPR2_P38WP                   RAMCFG_WPR2_P38WP_Msk                   /*!< Write Protection Page 38 */
21214 #define RAMCFG_WPR2_P39WP_Pos               (7U)
21215 #define RAMCFG_WPR2_P39WP_Msk               (0x1UL << RAMCFG_WPR2_P39WP_Pos)        /*!< 0x00000080 */
21216 #define RAMCFG_WPR2_P39WP                   RAMCFG_WPR2_P39WP_Msk                   /*!< Write Protection Page 39 */
21217 #define RAMCFG_WPR2_P40WP_Pos               (8U)
21218 #define RAMCFG_WPR2_P40WP_Msk               (0x1UL << RAMCFG_WPR2_P40WP_Pos)        /*!< 0x00000100 */
21219 #define RAMCFG_WPR2_P40WP                   RAMCFG_WPR2_P40WP_Msk                   /*!< Write Protection Page 40 */
21220 #define RAMCFG_WPR2_P41WP_Pos               (9U)
21221 #define RAMCFG_WPR2_P41WP_Msk               (0x1UL << RAMCFG_WPR2_P41WP_Pos)        /*!< 0x00000200 */
21222 #define RAMCFG_WPR2_P41WP                   RAMCFG_WPR2_P41WP_Msk                   /*!< Write Protection Page 41 */
21223 #define RAMCFG_WPR2_P42WP_Pos               (10U)
21224 #define RAMCFG_WPR2_P42WP_Msk               (0x1UL << RAMCFG_WPR2_P42WP_Pos)        /*!< 0x00000400 */
21225 #define RAMCFG_WPR2_P42WP                   RAMCFG_WPR2_P42WP_Msk                   /*!< Write Protection Page 42 */
21226 #define RAMCFG_WPR2_P43WP_Pos               (11U)
21227 #define RAMCFG_WPR2_P43WP_Msk               (0x1UL << RAMCFG_WPR2_P43WP_Pos)        /*!< 0x00000800 */
21228 #define RAMCFG_WPR2_P43WP                   RAMCFG_WPR2_P43WP_Msk                   /*!< Write Protection Page 43 */
21229 #define RAMCFG_WPR2_P44WP_Pos               (12U)
21230 #define RAMCFG_WPR2_P44WP_Msk               (0x1UL << RAMCFG_WPR2_P44WP_Pos)        /*!< 0x00001000 */
21231 #define RAMCFG_WPR2_P44WP                   RAMCFG_WPR2_P44WP_Msk                   /*!< Write Protection Page 44 */
21232 #define RAMCFG_WPR2_P45WP_Pos               (13U)
21233 #define RAMCFG_WPR2_P45WP_Msk               (0x1UL << RAMCFG_WPR2_P45WP_Pos)        /*!< 0x00002000 */
21234 #define RAMCFG_WPR2_P45WP                   RAMCFG_WPR2_P45WP_Msk                   /*!< Write Protection Page 45 */
21235 #define RAMCFG_WPR2_P46WP_Pos               (14U)
21236 #define RAMCFG_WPR2_P46WP_Msk               (0x1UL << RAMCFG_WPR2_P46WP_Pos)        /*!< 0x00004000 */
21237 #define RAMCFG_WPR2_P46WP                   RAMCFG_WPR2_P46WP_Msk                   /*!< Write Protection Page 46 */
21238 #define RAMCFG_WPR2_P47WP_Pos               (15U)
21239 #define RAMCFG_WPR2_P47WP_Msk               (0x1UL << RAMCFG_WPR2_P47WP_Pos)        /*!< 0x00008000 */
21240 #define RAMCFG_WPR2_P47WP                   RAMCFG_WPR2_P47WP_Msk                   /*!< Write Protection Page 47 */
21241 #define RAMCFG_WPR2_P48WP_Pos               (16U)
21242 #define RAMCFG_WPR2_P48WP_Msk               (0x1UL << RAMCFG_WPR2_P48WP_Pos)        /*!< 0x00010000 */
21243 #define RAMCFG_WPR2_P48WP                   RAMCFG_WPR2_P48WP_Msk                   /*!< Write Protection Page 48 */
21244 #define RAMCFG_WPR2_P49WP_Pos               (17U)
21245 #define RAMCFG_WPR2_P49WP_Msk               (0x1UL << RAMCFG_WPR2_P49WP_Pos)        /*!< 0x00020000 */
21246 #define RAMCFG_WPR2_P49WP                   RAMCFG_WPR2_P49WP_Msk                   /*!< Write Protection Page 49 */
21247 #define RAMCFG_WPR2_P50WP_Pos               (18U)
21248 #define RAMCFG_WPR2_P50WP_Msk               (0x1UL << RAMCFG_WPR2_P50WP_Pos)        /*!< 0x00040000 */
21249 #define RAMCFG_WPR2_P50WP                   RAMCFG_WPR2_P50WP_Msk                   /*!< Write Protection Page 50 */
21250 #define RAMCFG_WPR2_P51WP_Pos               (19U)
21251 #define RAMCFG_WPR2_P51WP_Msk               (0x1UL << RAMCFG_WPR2_P51WP_Pos)        /*!< 0x00080000 */
21252 #define RAMCFG_WPR2_P51WP                   RAMCFG_WPR2_P51WP_Msk                   /*!< Write Protection Page 51 */
21253 #define RAMCFG_WPR2_P52WP_Pos               (20U)
21254 #define RAMCFG_WPR2_P52WP_Msk               (0x1UL << RAMCFG_WPR2_P52WP_Pos)        /*!< 0x00100000 */
21255 #define RAMCFG_WPR2_P52WP                   RAMCFG_WPR2_P52WP_Msk                   /*!< Write Protection Page 52 */
21256 #define RAMCFG_WPR2_P53WP_Pos               (21U)
21257 #define RAMCFG_WPR2_P53WP_Msk               (0x1UL << RAMCFG_WPR2_P53WP_Pos)        /*!< 0x00200000 */
21258 #define RAMCFG_WPR2_P53WP                   RAMCFG_WPR2_P53WP_Msk                   /*!< Write Protection Page 53 */
21259 #define RAMCFG_WPR2_P54WP_Pos               (22U)
21260 #define RAMCFG_WPR2_P54WP_Msk               (0x1UL << RAMCFG_WPR2_P54WP_Pos)        /*!< 0x00400000 */
21261 #define RAMCFG_WPR2_P54WP                   RAMCFG_WPR2_P54WP_Msk                   /*!< Write Protection Page 54 */
21262 #define RAMCFG_WPR2_P55WP_Pos               (23U)
21263 #define RAMCFG_WPR2_P55WP_Msk               (0x1UL << RAMCFG_WPR2_P55WP_Pos)        /*!< 0x00800000 */
21264 #define RAMCFG_WPR2_P55WP                   RAMCFG_WPR2_P55WP_Msk                   /*!< Write Protection Page 55 */
21265 #define RAMCFG_WPR2_P56WP_Pos               (24U)
21266 #define RAMCFG_WPR2_P56WP_Msk               (0x1UL << RAMCFG_WPR2_P56WP_Pos)        /*!< 0x01000000 */
21267 #define RAMCFG_WPR2_P56WP                   RAMCFG_WPR2_P56WP_Msk                   /*!< Write Protection Page 56 */
21268 #define RAMCFG_WPR2_P57WP_Pos               (25U)
21269 #define RAMCFG_WPR2_P57WP_Msk               (0x1UL << RAMCFG_WPR2_P57WP_Pos)        /*!< 0x02000000 */
21270 #define RAMCFG_WPR2_P57WP                   RAMCFG_WPR2_P57WP_Msk                   /*!< Write Protection Page 57 */
21271 #define RAMCFG_WPR2_P58WP_Pos               (26U)
21272 #define RAMCFG_WPR2_P58WP_Msk               (0x1UL << RAMCFG_WPR2_P58WP_Pos)        /*!< 0x04000000 */
21273 #define RAMCFG_WPR2_P58WP                   RAMCFG_WPR2_P58WP_Msk                   /*!< Write Protection Page 58 */
21274 #define RAMCFG_WPR2_P59WP_Pos               (27U)
21275 #define RAMCFG_WPR2_P59WP_Msk               (0x1UL << RAMCFG_WPR2_P59WP_Pos)        /*!< 0x08000000 */
21276 #define RAMCFG_WPR2_P59WP                   RAMCFG_WPR2_P59WP_Msk                   /*!< Write Protection Page 59 */
21277 #define RAMCFG_WPR2_P60WP_Pos               (28U)
21278 #define RAMCFG_WPR2_P60WP_Msk               (0x1UL << RAMCFG_WPR2_P60WP_Pos)        /*!< 0x10000000 */
21279 #define RAMCFG_WPR2_P60WP                   RAMCFG_WPR2_P60WP_Msk                   /*!< Write Protection Page 60 */
21280 #define RAMCFG_WPR2_P61WP_Pos               (29U)
21281 #define RAMCFG_WPR2_P61WP_Msk               (0x1UL << RAMCFG_WPR2_P61WP_Pos)        /*!< 0x20000000 */
21282 #define RAMCFG_WPR2_P61WP                   RAMCFG_WPR2_P61WP_Msk                   /*!< Write Protection Page 61 */
21283 #define RAMCFG_WPR2_P62WP_Pos               (30U)
21284 #define RAMCFG_WPR2_P62WP_Msk               (0x1UL << RAMCFG_WPR2_P62WP_Pos)        /*!< 0x40000000 */
21285 #define RAMCFG_WPR2_P62WP                   RAMCFG_WPR2_P62WP_Msk                   /*!< Write Protection Page 62 */
21286 #define RAMCFG_WPR2_P63WP_Pos               (31U)
21287 #define RAMCFG_WPR2_P63WP_Msk               (0x1UL << RAMCFG_WPR2_P63WP_Pos)        /*!< 0x80000000 */
21288 #define RAMCFG_WPR2_P63WP                   RAMCFG_WPR2_P63WP_Msk                   /*!< Write Protection Page 63 */
21289 
21290 /*****************  Bit definition for RAMCFG_ECCKEYR register  ***************/
21291 #define RAMCFG_ECCKEYR_ECCKEY_Pos           (0U)
21292 #define RAMCFG_ECCKEYR_ECCKEY_Msk           (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos)   /*!< 0x000000FF */
21293 #define RAMCFG_ECCKEYR_ECCKEY               RAMCFG_ECCKEYR_ECCKEY_Msk               /*!< ECC Write Protection Key */
21294 
21295 /*****************  Bit definition for RAMCFG_ERKEYR register  ****************/
21296 #define RAMCFG_ERKEYR_ERASEKEY_Pos          (0U)
21297 #define RAMCFG_ERKEYR_ERASEKEY_Msk          (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos)  /*!< 0x000000FF */
21298 #define RAMCFG_ERKEYR_ERASEKEY              RAMCFG_ERKEYR_ERASEKEY_Msk              /*!< Erase Write Protection Key */
21299 
21300 /******************************************************************************/
21301 /*                                                                            */
21302 /*                         Reset and Clock Control                            */
21303 /*                                                                            */
21304 /******************************************************************************/
21305 /********************  Bit definition for RCC_CR register  ********************/
21306 #define RCC_CR_MSISON_Pos                   (0U)
21307 #define RCC_CR_MSISON_Msk                   (0x1UL << RCC_CR_MSISON_Pos)            /*!< 0x00000001 */
21308 #define RCC_CR_MSISON                       RCC_CR_MSISON_Msk                       /*!< Internal Multi Speed Oscillator (MSIS) Clock Enable */
21309 #define RCC_CR_MSIKERON_Pos                 (1U)
21310 #define RCC_CR_MSIKERON_Msk                 (0x1UL << RCC_CR_MSIKERON_Pos)          /*!< 0x00000002 */
21311 #define RCC_CR_MSIKERON                     RCC_CR_MSIKERON_Msk                     /*!< MSI Enable for Some IPs Kernels */
21312 #define RCC_CR_MSISRDY_Pos                  (2U)
21313 #define RCC_CR_MSISRDY_Msk                  (0x1UL << RCC_CR_MSISRDY_Pos)           /*!< 0x00000004 */
21314 #define RCC_CR_MSISRDY                      RCC_CR_MSISRDY_Msk                      /*!< Internal Multi Speed Oscillator (MSIS) Clock Ready Flag */
21315 #define RCC_CR_MSIPLLEN_Pos                 (3U)
21316 #define RCC_CR_MSIPLLEN_Msk                 (0x1UL << RCC_CR_MSIPLLEN_Pos)          /*!< 0x00000008 */
21317 #define RCC_CR_MSIPLLEN                     RCC_CR_MSIPLLEN_Msk                     /*!< Internal Multi Speed Oscillator (MSI) PLL Mode Enable */
21318 #define RCC_CR_MSIKON_Pos                   (4U)
21319 #define RCC_CR_MSIKON_Msk                   (0x1UL << RCC_CR_MSIKON_Pos)            /*!< 0x00000010 */
21320 #define RCC_CR_MSIKON                       RCC_CR_MSIKON_Msk                       /*!< Internal Multi Speed Oscillator Kernel (MSIK) Enable */
21321 #define RCC_CR_MSIKRDY_Pos                  (5U)
21322 #define RCC_CR_MSIKRDY_Msk                  (0x1UL << RCC_CR_MSIKRDY_Pos)           /*!< 0x00000020 */
21323 #define RCC_CR_MSIKRDY                      RCC_CR_MSIKRDY_Msk                      /*!< Internal Multi Speed Oscillator Kernel (MSIK) Ready Flag */
21324 #define RCC_CR_MSIPLLSEL_Pos                (6U)
21325 #define RCC_CR_MSIPLLSEL_Msk                (0x1UL << RCC_CR_MSIPLLSEL_Pos)         /*!< 0x00000040 */
21326 #define RCC_CR_MSIPLLSEL                    RCC_CR_MSIPLLSEL_Msk                    /*!< Internal Multi Speed Oscillator (MSI) PLL Mode Selection */
21327 #define RCC_CR_MSIPLLFAST_Pos               (7U)
21328 #define RCC_CR_MSIPLLFAST_Msk               (0x1UL << RCC_CR_MSIPLLFAST_Pos)        /*!< 0x00000080 */
21329 #define RCC_CR_MSIPLLFAST                   RCC_CR_MSIPLLFAST_Msk                   /*!< Internal Multi Speed Oscillator (MSI) PLL Fast Mode Selection */
21330 #define RCC_CR_HSION_Pos                    (8U)
21331 #define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)             /*!< 0x00000100 */
21332 #define RCC_CR_HSION                        RCC_CR_HSION_Msk                        /*!< Internal High Speed Oscillator (HSI16) Clock Enable */
21333 #define RCC_CR_HSIKERON_Pos                 (9U)
21334 #define RCC_CR_HSIKERON_Msk                 (0x1UL << RCC_CR_HSIKERON_Pos)          /*!< 0x00000200 */
21335 #define RCC_CR_HSIKERON                     RCC_CR_HSIKERON_Msk                     /*!< Internal High Speed Oscillator (HSI16) Clock Enable for some IPs Kernel */
21336 #define RCC_CR_HSIRDY_Pos                   (10U)
21337 #define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)            /*!< 0x00000400 */
21338 #define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                       /*!< Internal High Speed Oscillator (HSI16) Clock Ready Flag */
21339 #define RCC_CR_HSI48ON_Pos                  (12U)
21340 #define RCC_CR_HSI48ON_Msk                  (0x1UL << RCC_CR_HSI48ON_Pos)           /*!< 0x000001000 */
21341 #define RCC_CR_HSI48ON                      RCC_CR_HSI48ON_Msk                      /*!< Internal High Speed Oscillator (HSI48) Clock Enable */
21342 #define RCC_CR_HSI48RDY_Pos                 (13U)
21343 #define RCC_CR_HSI48RDY_Msk                 (0x1UL << RCC_CR_HSI48RDY_Pos)          /*!< 0x000002000 */
21344 #define RCC_CR_HSI48RDY                     RCC_CR_HSI48RDY_Msk                     /*!< Internal High Speed Oscillator (HSI48) Clock Ready Flag */
21345 #define RCC_CR_SHSION_Pos                   (14U)
21346 #define RCC_CR_SHSION_Msk                   (0x1UL << RCC_CR_SHSION_Pos)            /*!< 0x000004000 */
21347 #define RCC_CR_SHSION                       RCC_CR_SHSION_Msk                       /*!< Internal High Speed Secure (SHSI) Clock Enable */
21348 #define RCC_CR_SHSIRDY_Pos                  (15U)
21349 #define RCC_CR_SHSIRDY_Msk                  (0x1UL << RCC_CR_SHSIRDY_Pos)           /*!< 0x000008000 */
21350 #define RCC_CR_SHSIRDY                      RCC_CR_SHSIRDY_Msk                      /*!< Internal High Speed Secure (SHSI) Clock Ready Flag */
21351 #define RCC_CR_HSEON_Pos                    (16U)
21352 #define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)             /*!< 0x00010000 */
21353 #define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                        /*!< External High Speed Oscillator (HSE) Clock Enable */
21354 #define RCC_CR_HSERDY_Pos                   (17U)
21355 #define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)            /*!< 0x00020000 */
21356 #define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                       /*!< External High Speed Oscillator (HSE) Clock Ready */
21357 #define RCC_CR_HSEBYP_Pos                   (18U)
21358 #define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)            /*!< 0x00040000 */
21359 #define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                       /*!< External High Speed Oscillator (HSE) Clock Bypass */
21360 #define RCC_CR_CSSON_Pos                    (19U)
21361 #define RCC_CR_CSSON_Msk                    (0x1UL << RCC_CR_CSSON_Pos)             /*!< 0x00080000 */
21362 #define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                        /*!< HSE Clock Security System Enable */
21363 #define RCC_CR_HSEEXT_Pos                   (20U)
21364 #define RCC_CR_HSEEXT_Msk                   (0x1UL << RCC_CR_HSEEXT_Pos)            /*!< 0x00100000 */
21365 #define RCC_CR_HSEEXT                       RCC_CR_HSEEXT_Msk                       /*!< External High Speed clock type in Bypass Mode */
21366 #define RCC_CR_PLL1ON_Pos                   (24U)
21367 #define RCC_CR_PLL1ON_Msk                   (0x1UL << RCC_CR_PLL1ON_Pos)            /*!< 0x01000000 */
21368 #define RCC_CR_PLL1ON                       RCC_CR_PLL1ON_Msk                       /*!< System PLL 1 Clock Enable */
21369 #define RCC_CR_PLL1RDY_Pos                  (25U)
21370 #define RCC_CR_PLL1RDY_Msk                  (0x1UL << RCC_CR_PLL1RDY_Pos)           /*!< 0x02000000 */
21371 #define RCC_CR_PLL1RDY                      RCC_CR_PLL1RDY_Msk                      /*!< System PLL 1 Clock Ready Flag */
21372 #define RCC_CR_PLL2ON_Pos                   (26U)
21373 #define RCC_CR_PLL2ON_Msk                   (0x1UL << RCC_CR_PLL2ON_Pos)            /*!< 0x04000000 */
21374 #define RCC_CR_PLL2ON                       RCC_CR_PLL2ON_Msk                       /*!< System PLL 2 Enable */
21375 #define RCC_CR_PLL2RDY_Pos                  (27U)
21376 #define RCC_CR_PLL2RDY_Msk                  (0x1UL << RCC_CR_PLL2RDY_Pos)           /*!< 0x08000000 */
21377 #define RCC_CR_PLL2RDY                      RCC_CR_PLL2RDY_Msk                      /*!< System PLL 2 Ready Flag */
21378 #define RCC_CR_PLL3ON_Pos                   (28U)
21379 #define RCC_CR_PLL3ON_Msk                   (0x1UL << RCC_CR_PLL3ON_Pos)            /*!< 0x10000000 */
21380 #define RCC_CR_PLL3ON                       RCC_CR_PLL3ON_Msk                       /*!< System PLL 3 Enable */
21381 #define RCC_CR_PLL3RDY_Pos                  (29U)
21382 #define RCC_CR_PLL3RDY_Msk                  (0x1UL << RCC_CR_PLL3RDY_Pos)           /*!< 0x20000000 */
21383 #define RCC_CR_PLL3RDY                      RCC_CR_PLL3RDY_Msk                      /*!< System PLL 3 Ready Flag */
21384 
21385 /********************  Bit definition for RCC_ICSCR1 register  ***************/
21386 /*!< MSICAL configuration */
21387 #define RCC_ICSCR1_MSICAL3_Pos              (0U)
21388 #define RCC_ICSCR1_MSICAL3_Msk              (0x1FUL << RCC_ICSCR1_MSICAL3_Pos)      /*!< 0x0000001F */
21389 #define RCC_ICSCR1_MSICAL3                  RCC_ICSCR1_MSICAL3_Msk                  /*!< MSICAL[4:0] bits: MSIRC3 Clock Calibration for MSI Ranges 12 to 15 */
21390 #define RCC_ICSCR1_MSICAL3_0                (0x01UL << RCC_ICSCR1_MSICAL3_Pos)      /*!< 0x00000001 */
21391 #define RCC_ICSCR1_MSICAL3_1                (0x02UL << RCC_ICSCR1_MSICAL3_Pos)      /*!< 0x00000002 */
21392 #define RCC_ICSCR1_MSICAL3_2                (0x04UL << RCC_ICSCR1_MSICAL3_Pos)      /*!< 0x00000004 */
21393 #define RCC_ICSCR1_MSICAL3_3                (0x08UL << RCC_ICSCR1_MSICAL3_Pos)      /*!< 0x00000008 */
21394 #define RCC_ICSCR1_MSICAL3_4                (0x10UL << RCC_ICSCR1_MSICAL3_Pos)      /*!< 0x00000010 */
21395 #define RCC_ICSCR1_MSICAL2_Pos              (5U)
21396 #define RCC_ICSCR1_MSICAL2_Msk              (0x1FUL << RCC_ICSCR1_MSICAL2_Pos)      /*!< 0x000003E0 */
21397 #define RCC_ICSCR1_MSICAL2                  RCC_ICSCR1_MSICAL2_Msk                  /*!< MSICAL[4:0] bits: MSIRC2 Clock Calibration for MSI Ranges 8 to 11*/
21398 #define RCC_ICSCR1_MSICAL2_0                (0x01UL << RCC_ICSCR1_MSICAL2_Pos)      /*!< 0x00000020 */
21399 #define RCC_ICSCR1_MSICAL2_1                (0x02UL << RCC_ICSCR1_MSICAL2_Pos)      /*!< 0x00000040 */
21400 #define RCC_ICSCR1_MSICAL2_2                (0x04UL << RCC_ICSCR1_MSICAL2_Pos)      /*!< 0x00000080 */
21401 #define RCC_ICSCR1_MSICAL2_3                (0x08UL << RCC_ICSCR1_MSICAL2_Pos)      /*!< 0x000000C0 */
21402 #define RCC_ICSCR1_MSICAL2_4                (0x10UL << RCC_ICSCR1_MSICAL2_Pos)      /*!< 0x00000100 */
21403 #define RCC_ICSCR1_MSICAL1_Pos              (10U)
21404 #define RCC_ICSCR1_MSICAL1_Msk              (0x1FUL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x00007C00 */
21405 #define RCC_ICSCR1_MSICAL1                  RCC_ICSCR1_MSICAL1_Msk                  /*!< MSICAL[4:0] bits: MSIRC1 Clock Calibration for MSI Ranges 4 to 7 */
21406 #define RCC_ICSCR1_MSICAL1_0                (0x01UL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x00000200 */
21407 #define RCC_ICSCR1_MSICAL1_1                (0x02UL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x00000400 */
21408 #define RCC_ICSCR1_MSICAL1_2                (0x04UL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x00000800 */
21409 #define RCC_ICSCR1_MSICAL1_3                (0x08UL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x00000C00 */
21410 #define RCC_ICSCR1_MSICAL1_4                (0x10UL << RCC_ICSCR1_MSICAL1_Pos)      /*!< 0x00001000 */
21411 #define RCC_ICSCR1_MSICAL0_Pos              (15U)
21412 #define RCC_ICSCR1_MSICAL0_Msk              (0x1FUL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x000F8000 */
21413 #define RCC_ICSCR1_MSICAL0                  RCC_ICSCR1_MSICAL0_Msk                  /*!< MSICAL[4:0] bits: MSIRC0 Clock Calibration for MSI Ranges 0 to 3 */
21414 #define RCC_ICSCR1_MSICAL0_0                (0x01UL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x00002000 */
21415 #define RCC_ICSCR1_MSICAL0_1                (0x02UL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x00004000 */
21416 #define RCC_ICSCR1_MSICAL0_2                (0x04UL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x00008000 */
21417 #define RCC_ICSCR1_MSICAL0_3                (0x08UL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x0000C000 */
21418 #define RCC_ICSCR1_MSICAL0_4                (0x10UL << RCC_ICSCR1_MSICAL0_Pos)      /*!< 0x00010000 */
21419 #define RCC_ICSCR1_MSIBIAS_Pos              (22U)
21420 #define RCC_ICSCR1_MSIBIAS_Msk              (0x1UL << RCC_ICSCR1_MSIBIAS_Pos)       /*!< 0x00400000 */
21421 #define RCC_ICSCR1_MSIBIAS                  RCC_ICSCR1_MSIBIAS_Msk                  /*!< Internal Multi Speed oscillator (MSI) BIAS mode selection */
21422 #define RCC_ICSCR1_MSIRGSEL_Pos             (23U)
21423 #define RCC_ICSCR1_MSIRGSEL_Msk             (0x1UL << RCC_ICSCR1_MSIRGSEL_Pos)      /*!< 0x00000008 */
21424 #define RCC_ICSCR1_MSIRGSEL                 RCC_ICSCR1_MSIRGSEL_Msk                 /*!< Internal Multi Speed oscillator (MSI) range selection */
21425 
21426 /*!< MSIKRANGE configuration : 16 frequency ranges available */
21427 #define RCC_ICSCR1_MSIKRANGE_Pos            (24U)
21428 #define RCC_ICSCR1_MSIKRANGE_Msk            (0xFUL << RCC_ICSCR1_MSIKRANGE_Pos)     /*!< 0x0F000000 */
21429 #define RCC_ICSCR1_MSIKRANGE                RCC_ICSCR1_MSIKRANGE_Msk                /*!< Internal Multi Speed oscillator Kernel (MSIK) clock Ranges */
21430 #define RCC_ICSCR1_MSIKRANGE_0              (0x1UL << RCC_ICSCR1_MSIKRANGE_Pos)     /*!< 0x01000000 */
21431 #define RCC_ICSCR1_MSIKRANGE_1              (0x2UL << RCC_ICSCR1_MSIKRANGE_Pos)     /*!< 0x02000000 */
21432 #define RCC_ICSCR1_MSIKRANGE_2              (0x4UL << RCC_ICSCR1_MSIKRANGE_Pos)     /*!< 0x04000000 */
21433 #define RCC_ICSCR1_MSIKRANGE_3              (0x8UL << RCC_ICSCR1_MSIKRANGE_Pos)     /*!< 0x08000000 */
21434 
21435 /*!< MSIRANGE configuration : 16 frequency ranges available */
21436 #define RCC_ICSCR1_MSISRANGE_Pos            (28U)
21437 #define RCC_ICSCR1_MSISRANGE_Msk            (0xFUL << RCC_ICSCR1_MSISRANGE_Pos)     /*!< 0xF0000000 */
21438 #define RCC_ICSCR1_MSISRANGE                RCC_ICSCR1_MSISRANGE_Msk                /*!< Internal Multi Speed oscillator (MSI) clock Ranges */
21439 #define RCC_ICSCR1_MSISRANGE_0              (0x1UL << RCC_ICSCR1_MSISRANGE_Pos)     /*!< 0x10000000 */
21440 #define RCC_ICSCR1_MSISRANGE_1              (0x2UL << RCC_ICSCR1_MSISRANGE_Pos)     /*!< 0x20000000 */
21441 #define RCC_ICSCR1_MSISRANGE_2              (0x4UL << RCC_ICSCR1_MSISRANGE_Pos)     /*!< 0x40000000 */
21442 #define RCC_ICSCR1_MSISRANGE_3              (0x8UL << RCC_ICSCR1_MSISRANGE_Pos)     /*!< 0x80000000 */
21443 
21444 /********************  Bit definition for RCC_ICSCR2 register  ***************/
21445 /*!< MSITRIM configuration */
21446 #define RCC_ICSCR2_MSITRIM3_Pos             (0U)
21447 #define RCC_ICSCR2_MSITRIM3_Msk             (0x1FUL << RCC_ICSCR2_MSITRIM3_Pos)     /*!< 0x0000001F */
21448 #define RCC_ICSCR2_MSITRIM3                 RCC_ICSCR2_MSITRIM3_Msk                 /*!< MSITRIM[4:0] bits: MSI Clock Trimming for Ranges 12 to 15 */
21449 #define RCC_ICSCR2_MSITRIM3_0               (0x01UL << RCC_ICSCR2_MSITRIM3_Pos)     /*!< 0x00000001 */
21450 #define RCC_ICSCR2_MSITRIM3_1               (0x02UL << RCC_ICSCR2_MSITRIM3_Pos)     /*!< 0x00000002 */
21451 #define RCC_ICSCR2_MSITRIM3_2               (0x04UL << RCC_ICSCR2_MSITRIM3_Pos)     /*!< 0x00000004 */
21452 #define RCC_ICSCR2_MSITRIM3_3               (0x08UL << RCC_ICSCR2_MSITRIM3_Pos)     /*!< 0x00000008 */
21453 #define RCC_ICSCR2_MSITRIM3_4               (0x10UL << RCC_ICSCR2_MSITRIM3_Pos)     /*!< 0x00000010 */
21454 #define RCC_ICSCR2_MSITRIM2_Pos             (5U)
21455 #define RCC_ICSCR2_MSITRIM2_Msk             (0x1FUL << RCC_ICSCR2_MSITRIM2_Pos)     /*!< 0x000003E0 */
21456 #define RCC_ICSCR2_MSITRIM2                 RCC_ICSCR2_MSITRIM2_Msk                 /*!< MSITRIM[4:0] bits: MSI Clock Trimming for Ranges 8 to 11 */
21457 #define RCC_ICSCR2_MSITRIM2_0               (0x01UL << RCC_ICSCR2_MSITRIM2_Pos)     /*!< 0x00000020 */
21458 #define RCC_ICSCR2_MSITRIM2_1               (0x02UL << RCC_ICSCR2_MSITRIM2_Pos)     /*!< 0x00000040 */
21459 #define RCC_ICSCR2_MSITRIM2_2               (0x04UL << RCC_ICSCR2_MSITRIM2_Pos)     /*!< 0x00000080 */
21460 #define RCC_ICSCR2_MSITRIM2_3               (0x08UL << RCC_ICSCR2_MSITRIM2_Pos)     /*!< 0x000000C0 */
21461 #define RCC_ICSCR2_MSITRIM2_4               (0x10UL << RCC_ICSCR2_MSITRIM2_Pos)     /*!< 0x00000100 */
21462 #define RCC_ICSCR2_MSITRIM1_Pos             (10U)
21463 #define RCC_ICSCR2_MSITRIM1_Msk             (0x1FUL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x00007C00 */
21464 #define RCC_ICSCR2_MSITRIM1                 RCC_ICSCR2_MSITRIM1_Msk                 /*!< MSITRIM[4:0] bits: MSI Clock Trimming for Ranges 4 to 7 */
21465 #define RCC_ICSCR2_MSITRIM1_0               (0x01UL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x00000200 */
21466 #define RCC_ICSCR2_MSITRIM1_1               (0x02UL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x00000400 */
21467 #define RCC_ICSCR2_MSITRIM1_2               (0x04UL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x00000800 */
21468 #define RCC_ICSCR2_MSITRIM1_3               (0x08UL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x00000C00 */
21469 #define RCC_ICSCR2_MSITRIM1_4               (0x10UL << RCC_ICSCR2_MSITRIM1_Pos)     /*!< 0x00001000 */
21470 #define RCC_ICSCR2_MSITRIM0_Pos             (15U)
21471 #define RCC_ICSCR2_MSITRIM0_Msk             (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x000F8000 */
21472 #define RCC_ICSCR2_MSITRIM0                 RCC_ICSCR2_MSITRIM0_Msk                 /*!< MSITRIM[4:0] bits: MSI Clock Trimming for Ranges 0 to 3 */
21473 #define RCC_ICSCR2_MSITRIM0_0               (0x01UL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x00002000 */
21474 #define RCC_ICSCR2_MSITRIM0_1               (0x02UL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x00004000 */
21475 #define RCC_ICSCR2_MSITRIM0_2               (0x04UL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x00008000 */
21476 #define RCC_ICSCR2_MSITRIM0_3               (0x08UL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x0000C000 */
21477 #define RCC_ICSCR2_MSITRIM0_4               (0x10UL << RCC_ICSCR2_MSITRIM0_Pos)     /*!< 0x00010000 */
21478 
21479 /********************  Bit definition for RCC_ICSCR3 register  ***************/
21480 /*!< HSICAL configuration */
21481 #define RCC_ICSCR3_HSICAL_Pos               (0U)
21482 #define RCC_ICSCR3_HSICAL_Msk               (0xFFFUL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000FFF */
21483 #define RCC_ICSCR3_HSICAL                   RCC_ICSCR3_HSICAL_Msk                   /*!< HSICAL[11:0] bits: HSI Clock Calibration */
21484 #define RCC_ICSCR3_HSICAL_0                 (0x001UL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000001 */
21485 #define RCC_ICSCR3_HSICAL_1                 (0x002UL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000002 */
21486 #define RCC_ICSCR3_HSICAL_2                 (0x004UL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000004 */
21487 #define RCC_ICSCR3_HSICAL_3                 (0x008UL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000008 */
21488 #define RCC_ICSCR3_HSICAL_4                 (0x010UL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000010 */
21489 #define RCC_ICSCR3_HSICAL_5                 (0x020UL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000020 */
21490 #define RCC_ICSCR3_HSICAL_6                 (0x040UL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000040 */
21491 #define RCC_ICSCR3_HSICAL_7                 (0x080UL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000040 */
21492 #define RCC_ICSCR3_HSICAL_8                 (0x100UL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000080 */
21493 #define RCC_ICSCR3_HSICAL_9                 (0x200UL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000100 */
21494 #define RCC_ICSCR3_HSICAL_10                (0x400UL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000200 */
21495 #define RCC_ICSCR3_HSICAL_11                (0x800UL << RCC_ICSCR3_HSICAL_Pos)      /*!< 0x00000400 */
21496 
21497 /*!< HSITRIM configuration */
21498 #define RCC_ICSCR3_HSITRIM_Pos              (16U)
21499 #define RCC_ICSCR3_HSITRIM_Msk              (0x1FUL << RCC_ICSCR3_HSITRIM_Pos)      /*!< 0x7F000000 */
21500 #define RCC_ICSCR3_HSITRIM                  RCC_ICSCR3_HSITRIM_Msk                  /*!< HSITRIM[4:0] bits: HSI Clock Trimming */
21501 #define RCC_ICSCR3_HSITRIM_0                (0x01UL << RCC_ICSCR3_HSITRIM_Pos)      /*!< 0x00010000 */
21502 #define RCC_ICSCR3_HSITRIM_1                (0x02UL << RCC_ICSCR3_HSITRIM_Pos)      /*!< 0x00020000 */
21503 #define RCC_ICSCR3_HSITRIM_2                (0x04UL << RCC_ICSCR3_HSITRIM_Pos)      /*!< 0x00040000 */
21504 #define RCC_ICSCR3_HSITRIM_3                (0x08UL << RCC_ICSCR3_HSITRIM_Pos)      /*!< 0x00080000 */
21505 #define RCC_ICSCR3_HSITRIM_4                (0x10UL << RCC_ICSCR3_HSITRIM_Pos)      /*!< 0x00100000 */
21506 
21507 /********************  Bit definition for RCC_CRRCR register  *****************/
21508 /*!< HSI48CAL configuration */
21509 #define RCC_CRRCR_HSI48CAL_Pos              (0U)
21510 #define RCC_CRRCR_HSI48CAL_Msk              (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x000001FF */
21511 #define RCC_CRRCR_HSI48CAL                  RCC_CRRCR_HSI48CAL_Msk                  /*!< HSI48CAL[4:0] bits: HSI48 Clock Calibration */
21512 #define RCC_CRRCR_HSI48CAL_0                (0x001UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000001 */
21513 #define RCC_CRRCR_HSI48CAL_1                (0x002UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000002 */
21514 #define RCC_CRRCR_HSI48CAL_2                (0x004UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000004 */
21515 #define RCC_CRRCR_HSI48CAL_3                (0x008UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000008 */
21516 #define RCC_CRRCR_HSI48CAL_4                (0x010UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000010 */
21517 #define RCC_CRRCR_HSI48CAL_5                (0x020UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000020 */
21518 #define RCC_CRRCR_HSI48CAL_6                (0x040UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000040 */
21519 #define RCC_CRRCR_HSI48CAL_7                (0x080UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000080 */
21520 #define RCC_CRRCR_HSI48CAL_8                (0x100UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000100 */
21521 
21522 /********************  Bit definition for RCC_CFGR register  ******************/
21523 /*!< SW configuration */
21524 #define RCC_CFGR1_SW_Pos                    (0U)
21525 #define RCC_CFGR1_SW_Msk                    (0x3UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000003 */
21526 #define RCC_CFGR1_SW                        RCC_CFGR1_SW_Msk                        /*!< SW[1:0] bits (System clock Switch) */
21527 #define RCC_CFGR1_SW_0                      (0x1UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000001 */
21528 #define RCC_CFGR1_SW_1                      (0x2UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000002 */
21529 /*!< SWS configuration */
21530 #define RCC_CFGR1_SWS_Pos                   (2U)
21531 #define RCC_CFGR1_SWS_Msk                   (0x3UL << RCC_CFGR1_SWS_Pos)            /*!< 0x0000000C */
21532 #define RCC_CFGR1_SWS                       RCC_CFGR1_SWS_Msk                       /*!< SWS[1:0] bits (System Clock Switch Status) */
21533 #define RCC_CFGR1_SWS_0                     (0x1UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000004 */
21534 #define RCC_CFGR1_SWS_1                     (0x2UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000008 */
21535 #define RCC_CFGR1_STOPWUCK_Pos              (4U)
21536 #define RCC_CFGR1_STOPWUCK_Msk              (0x1UL << RCC_CFGR1_STOPWUCK_Pos)       /*!< 0x00008000 */
21537 #define RCC_CFGR1_STOPWUCK                  RCC_CFGR1_STOPWUCK_Msk                  /*!< Wake Up from stop and CSS backup clock selection */
21538 #define RCC_CFGR1_STOPKERWUCK_Pos           (5U)
21539 #define RCC_CFGR1_STOPKERWUCK_Msk           (0x1UL << RCC_CFGR1_STOPKERWUCK_Pos)    /*!< 0x00008000 */
21540 #define RCC_CFGR1_STOPKERWUCK               RCC_CFGR1_STOPKERWUCK_Msk               /*!< Kernel Clock Selection after a Wake Up from STOP */
21541 /*!< MCOSEL configuration */
21542 #define RCC_CFGR1_MCOSEL_Pos                (24U)
21543 #define RCC_CFGR1_MCOSEL_Msk                (0xFUL << RCC_CFGR1_MCOSEL_Pos)         /*!< 0x0F000000 */
21544 #define RCC_CFGR1_MCOSEL                    RCC_CFGR1_MCOSEL_Msk                    /*!< MCOSEL [3:0] bits (Microcontroller Clock Output (MCO) Selection) */
21545 #define RCC_CFGR1_MCOSEL_0                  (0x1UL << RCC_CFGR1_MCOSEL_Pos)         /*!< 0x01000000 */
21546 #define RCC_CFGR1_MCOSEL_1                  (0x2UL << RCC_CFGR1_MCOSEL_Pos)         /*!< 0x02000000 */
21547 #define RCC_CFGR1_MCOSEL_2                  (0x4UL << RCC_CFGR1_MCOSEL_Pos)         /*!< 0x04000000 */
21548 #define RCC_CFGR1_MCOSEL_3                  (0x8UL << RCC_CFGR1_MCOSEL_Pos)         /*!< 0x08000000 */
21549 #define RCC_CFGR1_MCOPRE_Pos                (28U)
21550 #define RCC_CFGR1_MCOPRE_Msk                (0x7UL << RCC_CFGR1_MCOPRE_Pos)         /*!< 0x70000000 */
21551 #define RCC_CFGR1_MCOPRE                    RCC_CFGR1_MCOPRE_Msk                    /*!< MCOPRE [2:0] bits (Microcontroller Clock Output (MCO) Prescaler) */
21552 #define RCC_CFGR1_MCOPRE_0                  (0x1UL << RCC_CFGR1_MCOPRE_Pos)         /*!< 0x10000000 */
21553 #define RCC_CFGR1_MCOPRE_1                  (0x2UL << RCC_CFGR1_MCOPRE_Pos)         /*!< 0x20000000 */
21554 #define RCC_CFGR1_MCOPRE_2                  (0x4UL << RCC_CFGR1_MCOPRE_Pos)         /*!< 0x40000000 */
21555 
21556 /********************  Bit definition for RCC_CFGR2 register  ******************/
21557 /*!< CDHPRE configuration */
21558 #define RCC_CFGR2_HPRE_Pos                  (0U)
21559 #define RCC_CFGR2_HPRE_Msk                  (0xFUL << RCC_CFGR2_HPRE_Pos)           /*!< 0x0000000F */
21560 #define RCC_CFGR2_HPRE                      RCC_CFGR2_HPRE_Msk                      /*!< HPRE[3:0] bits (AHB prescaler) */
21561 #define RCC_CFGR2_HPRE_0                    (0x1UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000001 */
21562 #define RCC_CFGR2_HPRE_1                    (0x2UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000002 */
21563 #define RCC_CFGR2_HPRE_2                    (0x4UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000004 */
21564 #define RCC_CFGR2_HPRE_3                    (0x8UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000008 */
21565 /*!< PPRE1 configuration */
21566 #define RCC_CFGR2_PPRE1_Pos                 (4U)
21567 #define RCC_CFGR2_PPRE1_Msk                 (0x7UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000070 */
21568 #define RCC_CFGR2_PPRE1                     RCC_CFGR2_PPRE1_Msk                     /*!< PPRE1[2:0] bits (APB1 prescaler) */
21569 #define RCC_CFGR2_PPRE1_0                   (0x1UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000010 */
21570 #define RCC_CFGR2_PPRE1_1                   (0x2UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000020 */
21571 #define RCC_CFGR2_PPRE1_2                   (0x4UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000040 */
21572 /*!< PPRE2 configuration */
21573 #define RCC_CFGR2_PPRE2_Pos                 (8U)
21574 #define RCC_CFGR2_PPRE2_Msk                 (0x7UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000F00 */
21575 #define RCC_CFGR2_PPRE2                     RCC_CFGR2_PPRE2_Msk                     /*!< PPRE2[2:0] bits (APB2 prescaler) */
21576 #define RCC_CFGR2_PPRE2_0                   (0x1UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000100 */
21577 #define RCC_CFGR2_PPRE2_1                   (0x2UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000200 */
21578 #define RCC_CFGR2_PPRE2_2                   (0x4UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000400 */
21579 /*!< PPRE_DPHY configuration */
21580 #define RCC_CFGR2_PPRE_DPHY_Pos             (12U)
21581 #define RCC_CFGR2_PPRE_DPHY_Msk             (0x7UL << RCC_CFGR2_PPRE_DPHY_Pos)      /*!< 0x00007000 */
21582 #define RCC_CFGR2_PPRE_DPHY                 RCC_CFGR2_PPRE_DPHY_Msk                 /*!< PPRE_DPHY[2:0] bits (DPHY prescaler) */
21583 #define RCC_CFGR2_PPRE_DPHY_0               (0x1UL << RCC_CFGR2_PPRE_DPHY_Pos)      /*!< 0x00001000 */
21584 #define RCC_CFGR2_PPRE_DPHY_1               (0x2UL << RCC_CFGR2_PPRE_DPHY_Pos)      /*!< 0x00002000 */
21585 #define RCC_CFGR2_PPRE_DPHY_2               (0x4UL << RCC_CFGR2_PPRE_DPHY_Pos)      /*!< 0x00004000 */
21586 #define RCC_CFGR2_AHB1DIS_Pos               (16U)
21587 #define RCC_CFGR2_AHB1DIS_Msk               (0x1UL << RCC_CFGR2_AHB1DIS_Pos)        /*!< 0x00010000 */
21588 #define RCC_CFGR2_AHB1DIS                   RCC_CFGR2_AHB1DIS_Msk                   /*!< AHB1 clock disable */
21589 #define RCC_CFGR2_AHB2DIS1_Pos              (17U)
21590 #define RCC_CFGR2_AHB2DIS1_Msk              (0x1UL << RCC_CFGR2_AHB2DIS1_Pos)       /*!< 0x00020000 */
21591 #define RCC_CFGR2_AHB2DIS1                  RCC_CFGR2_AHB2DIS1_Msk                  /*!< AHB2 clock disable */
21592 #define RCC_CFGR2_AHB2DIS2_Pos              (18U)
21593 #define RCC_CFGR2_AHB2DIS2_Msk              (0x1UL << RCC_CFGR2_AHB2DIS2_Pos)       /*!< 0x00040000 */
21594 #define RCC_CFGR2_AHB2DIS2                  RCC_CFGR2_AHB2DIS2_Msk                  /*!< AHB2 clock disable */
21595 #define RCC_CFGR2_APB1DIS_Pos               (19U)
21596 #define RCC_CFGR2_APB1DIS_Msk               (0x1UL << RCC_CFGR2_APB1DIS_Pos)        /*!< 0x00080000 */
21597 #define RCC_CFGR2_APB1DIS                   RCC_CFGR2_APB1DIS_Msk                   /*!< APB1 clock disable */
21598 #define RCC_CFGR2_APB2DIS_Pos               (20U)
21599 #define RCC_CFGR2_APB2DIS_Msk               (0x1UL << RCC_CFGR2_APB2DIS_Pos)        /*!< 0x00100000 */
21600 #define RCC_CFGR2_APB2DIS                   RCC_CFGR2_APB2DIS_Msk                   /*!< APB2 clock disable */
21601 
21602 /********************  Bit definition for RCC_CFGR3 register  ******************/
21603 /*!< PPRE3 configuration */
21604 #define RCC_CFGR3_PPRE3_Pos                 (4U)
21605 #define RCC_CFGR3_PPRE3_Msk                 (0x7UL << RCC_CFGR3_PPRE3_Pos)          /*!< 0x00000070 */
21606 #define RCC_CFGR3_PPRE3                     RCC_CFGR3_PPRE3_Msk                     /*!< PPRE31[2:0] bits (APB3 prescaler) */
21607 #define RCC_CFGR3_PPRE3_0                   (0x1UL << RCC_CFGR3_PPRE3_Pos)          /*!< 0x00000010 */
21608 #define RCC_CFGR3_PPRE3_1                   (0x2UL << RCC_CFGR3_PPRE3_Pos)          /*!< 0x00000020 */
21609 #define RCC_CFGR3_PPRE3_2                   (0x4UL << RCC_CFGR3_PPRE3_Pos)          /*!< 0x00000040 */
21610 
21611 #define RCC_CFGR3_AHB3DIS_Pos               (16U)
21612 #define RCC_CFGR3_AHB3DIS_Msk               (0x1UL << RCC_CFGR3_AHB3DIS_Pos)        /*!< 0x00010000 */
21613 #define RCC_CFGR3_AHB3DIS                   RCC_CFGR3_AHB3DIS_Msk                   /*!< AHB3 clock disable */
21614 
21615 #define RCC_CFGR3_APB3DIS_Pos               (17U)
21616 #define RCC_CFGR3_APB3DIS_Msk               (0x1UL << RCC_CFGR3_APB3DIS_Pos)        /*!< 0x00020000 */
21617 #define RCC_CFGR3_APB3DIS                   RCC_CFGR3_APB3DIS_Msk                   /*!< APB3 clock disable */
21618 
21619 /********************  Bit definition for RCC_PLL1CFGR register  ***************/
21620 #define RCC_PLL1CFGR_PLL1SRC_Pos            (0U)
21621 #define RCC_PLL1CFGR_PLL1SRC_Msk            (0x3UL << RCC_PLL1CFGR_PLL1SRC_Pos)     /*!< 0x00000003 */
21622 #define RCC_PLL1CFGR_PLL1SRC                RCC_PLL1CFGR_PLL1SRC_Msk                /*!< PLL1SRC[1:0] bits (PLL1 Entry Clock Source) */
21623 #define RCC_PLL1CFGR_PLL1SRC_0              (0x1UL << RCC_PLL1CFGR_PLL1SRC_Pos)     /*!< 0x00000001 */
21624 #define RCC_PLL1CFGR_PLL1SRC_1              (0x2UL << RCC_PLL1CFGR_PLL1SRC_Pos)     /*!< 0x00000002 */
21625 #define RCC_PLL1CFGR_PLL1RGE_Pos            (2U)
21626 #define RCC_PLL1CFGR_PLL1RGE_Msk            (0x3UL << RCC_PLL1CFGR_PLL1RGE_Pos)     /*!< 0x0000000C */
21627 #define RCC_PLL1CFGR_PLL1RGE                RCC_PLL1CFGR_PLL1RGE_Msk                /*!< PLL1RGE[1:0] bits (PLL1 Input Frequency Range) */
21628 #define RCC_PLL1CFGR_PLL1RGE_0              (0x1UL << RCC_PLL1CFGR_PLL1RGE_Pos)     /*!< 0x00000004 */
21629 #define RCC_PLL1CFGR_PLL1RGE_1              (0x2UL << RCC_PLL1CFGR_PLL1RGE_Pos)     /*!< 0x00000008 */
21630 #define RCC_PLL1CFGR_PLL1FRACEN_Pos         (4U)
21631 #define RCC_PLL1CFGR_PLL1FRACEN_Msk         (0x1UL << RCC_PLL1CFGR_PLL1FRACEN_Pos)  /*!< 0x00000010 */
21632 #define RCC_PLL1CFGR_PLL1FRACEN             RCC_PLL1CFGR_PLL1FRACEN_Msk             /*!< PLL1 Fractional Latch Enable */
21633 #define RCC_PLL1CFGR_PLL1M_Pos              (8U)
21634 #define RCC_PLL1CFGR_PLL1M_Msk              (0xFUL << RCC_PLL1CFGR_PLL1M_Pos)       /*!< 0x000003F0 */
21635 #define RCC_PLL1CFGR_PLL1M                  RCC_PLL1CFGR_PLL1M_Msk                  /*!< PLL1M[3:0]: bits (Prescaler for PLL1) */
21636 #define RCC_PLL1CFGR_PLL1M_0                (0x01UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000100 */
21637 #define RCC_PLL1CFGR_PLL1M_1                (0x02UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000200 */
21638 #define RCC_PLL1CFGR_PLL1M_2                (0x04UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000400 */
21639 #define RCC_PLL1CFGR_PLL1M_3                (0x08UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000800 */
21640 #define RCC_PLL1CFGR_PLL1MBOOST_Pos         (12U)
21641 #define RCC_PLL1CFGR_PLL1MBOOST_Msk         (0xFUL << RCC_PLL1CFGR_PLL1MBOOST_Pos)  /*!< 0x000003F0 */
21642 #define RCC_PLL1CFGR_PLL1MBOOST             RCC_PLL1CFGR_PLL1MBOOST_Msk             /*!< PLL1MBOOST[3:0]: bits (Prescaler for EPOD booster input clock) */
21643 #define RCC_PLL1CFGR_PLL1MBOOST_0           (0x01UL << RCC_PLL1CFGR_PLL1MBOOST_Pos) /*!< 0x00001000 */
21644 #define RCC_PLL1CFGR_PLL1MBOOST_1           (0x02UL << RCC_PLL1CFGR_PLL1MBOOST_Pos) /*!< 0x00002000 */
21645 #define RCC_PLL1CFGR_PLL1MBOOST_2           (0x04UL << RCC_PLL1CFGR_PLL1MBOOST_Pos) /*!< 0x00004000 */
21646 #define RCC_PLL1CFGR_PLL1MBOOST_3           (0x08UL << RCC_PLL1CFGR_PLL1MBOOST_Pos) /*!< 0x00008000 */
21647 #define RCC_PLL1CFGR_PLL1PEN_Pos            (16U)
21648 #define RCC_PLL1CFGR_PLL1PEN_Msk            (0x1UL << RCC_PLL1CFGR_PLL1PEN_Pos)     /*!< 0x00010000 */
21649 #define RCC_PLL1CFGR_PLL1PEN                RCC_PLL1CFGR_PLL1PEN_Msk                /*!< PLL1 DIVP Divider Output Enable */
21650 #define RCC_PLL1CFGR_PLL1QEN_Pos            (17U)
21651 #define RCC_PLL1CFGR_PLL1QEN_Msk            (0x1UL << RCC_PLL1CFGR_PLL1QEN_Pos)     /*!< 0x00020000 */
21652 #define RCC_PLL1CFGR_PLL1QEN                RCC_PLL1CFGR_PLL1QEN_Msk                /*!< PLL1 DIVQ Divider Output Enable */
21653 #define RCC_PLL1CFGR_PLL1REN_Pos            (18U)
21654 #define RCC_PLL1CFGR_PLL1REN_Msk            (0x1UL << RCC_PLL1CFGR_PLL1REN_Pos)     /*!< 0x00040000 */
21655 #define RCC_PLL1CFGR_PLL1REN                RCC_PLL1CFGR_PLL1REN_Msk                /*!< PLL1 DIVR Divider Output Enable */
21656 
21657 /********************  Bit definition for RCC_PLL2CFGR register  ***************/
21658 #define RCC_PLL2CFGR_PLL2SRC_Pos            (0U)
21659 #define RCC_PLL2CFGR_PLL2SRC_Msk            (0x3UL << RCC_PLL2CFGR_PLL2SRC_Pos)     /*!< 0x00000003 */
21660 #define RCC_PLL2CFGR_PLL2SRC                RCC_PLL2CFGR_PLL2SRC_Msk                /*!< PLL2SRC[1:0] bits (PLL2 Entry Clock Source) */
21661 #define RCC_PLL2CFGR_PLL2SRC_0              (0x1UL << RCC_PLL2CFGR_PLL2SRC_Pos)     /*!< 0x00000001 */
21662 #define RCC_PLL2CFGR_PLL2SRC_1              (0x2UL << RCC_PLL2CFGR_PLL2SRC_Pos)     /*!< 0x00000002 */
21663 #define RCC_PLL2CFGR_PLL2RGE_Pos            (2U)
21664 #define RCC_PLL2CFGR_PLL2RGE_Msk            (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos)     /*!< 0x0000000C */
21665 #define RCC_PLL2CFGR_PLL2RGE                RCC_PLL2CFGR_PLL2RGE_Msk                /*!< PLL2RGE[1:0] bits (PLL2 Input Frequency Range) */
21666 #define RCC_PLL2CFGR_PLL2RGE_0              (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos)     /*!< 0x00000004 */
21667 #define RCC_PLL2CFGR_PLL2RGE_1              (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos)     /*!< 0x00000008 */
21668 #define RCC_PLL2CFGR_PLL2FRACEN_Pos         (4U)
21669 #define RCC_PLL2CFGR_PLL2FRACEN_Msk         (0x1UL << RCC_PLL2CFGR_PLL2FRACEN_Pos)  /*!< 0x00000010 */
21670 #define RCC_PLL2CFGR_PLL2FRACEN             RCC_PLL2CFGR_PLL2FRACEN_Msk             /*!< PLL2 Fractional Latch Enable */
21671 #define RCC_PLL2CFGR_PLL2M_Pos              (8U)
21672 #define RCC_PLL2CFGR_PLL2M_Msk              (0xFUL << RCC_PLL2CFGR_PLL2M_Pos)       /*!< 0x000003F0 */
21673 #define RCC_PLL2CFGR_PLL2M                  RCC_PLL2CFGR_PLL2M_Msk                  /*!< PLL2M[3:0]: bits (Prescaler for PLL2) */
21674 #define RCC_PLL2CFGR_PLL2M_0                (0x01UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000100 */
21675 #define RCC_PLL2CFGR_PLL2M_1                (0x02UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000200 */
21676 #define RCC_PLL2CFGR_PLL2M_2                (0x04UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000400 */
21677 #define RCC_PLL2CFGR_PLL2M_3                (0x08UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000800 */
21678 #define RCC_PLL2CFGR_PLL2PEN_Pos            (16U)
21679 #define RCC_PLL2CFGR_PLL2PEN_Msk            (0x1UL << RCC_PLL2CFGR_PLL2PEN_Pos)     /*!< 0x00010000 */
21680 #define RCC_PLL2CFGR_PLL2PEN                RCC_PLL2CFGR_PLL2PEN_Msk                /*!< PLL2 DIVP Divider Output Enable */
21681 #define RCC_PLL2CFGR_PLL2QEN_Pos            (17U)
21682 #define RCC_PLL2CFGR_PLL2QEN_Msk            (0x1UL << RCC_PLL2CFGR_PLL2QEN_Pos)     /*!< 0x00020000 */
21683 #define RCC_PLL2CFGR_PLL2QEN                RCC_PLL2CFGR_PLL2QEN_Msk                /*!< PLL2 DIVQ Divider Output Enable */
21684 #define RCC_PLL2CFGR_PLL2REN_Pos            (18U)
21685 #define RCC_PLL2CFGR_PLL2REN_Msk            (0x1UL << RCC_PLL2CFGR_PLL2REN_Pos)     /*!< 0x00040000 */
21686 #define RCC_PLL2CFGR_PLL2REN                RCC_PLL2CFGR_PLL2REN_Msk                /*!< PLL2 DIVR Divider Output Enable */
21687 
21688 /********************  Bit definition for RCC_PLL3CFGR register  ***************/
21689 #define RCC_PLL3CFGR_PLL3SRC_Pos            (0U)
21690 #define RCC_PLL3CFGR_PLL3SRC_Msk            (0x3UL << RCC_PLL3CFGR_PLL3SRC_Pos)     /*!< 0x00000003 */
21691 #define RCC_PLL3CFGR_PLL3SRC                RCC_PLL3CFGR_PLL3SRC_Msk                /*!< PLL3SRC[1:0] bits (PLL3 Entry Clock Source) */
21692 #define RCC_PLL3CFGR_PLL3SRC_0              (0x1UL << RCC_PLL3CFGR_PLL3SRC_Pos)     /*!< 0x00000001 */
21693 #define RCC_PLL3CFGR_PLL3SRC_1              (0x2UL << RCC_PLL3CFGR_PLL3SRC_Pos)     /*!< 0x00000002 */
21694 #define RCC_PLL3CFGR_PLL3RGE_Pos            (2U)
21695 #define RCC_PLL3CFGR_PLL3RGE_Msk            (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos)     /*!< 0x0000000C */
21696 #define RCC_PLL3CFGR_PLL3RGE                RCC_PLL3CFGR_PLL3RGE_Msk                /*!< PLL3RGE[1:0] bits (PLL3 Input Frequency Range) */
21697 #define RCC_PLL3CFGR_PLL3RGE_0              (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos)     /*!< 0x00000004 */
21698 #define RCC_PLL3CFGR_PLL3RGE_1              (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos)     /*!< 0x00000008 */
21699 #define RCC_PLL3CFGR_PLL3FRACEN_Pos         (4U)
21700 #define RCC_PLL3CFGR_PLL3FRACEN_Msk         (0x1UL << RCC_PLL3CFGR_PLL3FRACEN_Pos)  /*!< 0x00000010 */
21701 #define RCC_PLL3CFGR_PLL3FRACEN             RCC_PLL3CFGR_PLL3FRACEN_Msk             /*!< PLL3 Fractional Latch Enable */
21702 #define RCC_PLL3CFGR_PLL3M_Pos              (8U)
21703 #define RCC_PLL3CFGR_PLL3M_Msk              (0xFUL << RCC_PLL3CFGR_PLL3M_Pos)       /*!< 0x000003F0 */
21704 #define RCC_PLL3CFGR_PLL3M                  RCC_PLL3CFGR_PLL3M_Msk                  /*!< PLL3M[3:0]: bits (Prescaler for PLL3) */
21705 #define RCC_PLL3CFGR_PLL3M_0                (0x01UL << RCC_PLL3CFGR_PLL3M_Pos)      /*!< 0x00000100 */
21706 #define RCC_PLL3CFGR_PLL3M_1                (0x02UL << RCC_PLL3CFGR_PLL3M_Pos)      /*!< 0x00000200 */
21707 #define RCC_PLL3CFGR_PLL3M_2                (0x04UL << RCC_PLL3CFGR_PLL3M_Pos)      /*!< 0x00000400 */
21708 #define RCC_PLL3CFGR_PLL3M_3                (0x08UL << RCC_PLL3CFGR_PLL3M_Pos)      /*!< 0x00000800 */
21709 #define RCC_PLL3CFGR_PLL3PEN_Pos            (16U)
21710 #define RCC_PLL3CFGR_PLL3PEN_Msk            (0x1UL << RCC_PLL3CFGR_PLL3PEN_Pos)     /*!< 0x00010000 */
21711 #define RCC_PLL3CFGR_PLL3PEN                RCC_PLL3CFGR_PLL3PEN_Msk                /*!< PLL3 DIVP Divider Output Enable */
21712 #define RCC_PLL3CFGR_PLL3QEN_Pos            (17U)
21713 #define RCC_PLL3CFGR_PLL3QEN_Msk            (0x1UL << RCC_PLL3CFGR_PLL3QEN_Pos)     /*!< 0x00020000 */
21714 #define RCC_PLL3CFGR_PLL3QEN                RCC_PLL3CFGR_PLL3QEN_Msk                /*!< PLL3 DIVQ Divider Output Enable */
21715 #define RCC_PLL3CFGR_PLL3REN_Pos            (18U)
21716 #define RCC_PLL3CFGR_PLL3REN_Msk            (0x1UL << RCC_PLL3CFGR_PLL3REN_Pos)     /*!< 0x00040000 */
21717 #define RCC_PLL3CFGR_PLL3REN                RCC_PLL3CFGR_PLL3REN_Msk                /*!< PLL3 DIVR Divider Output Enable */
21718 
21719 /********************  Bit definition for RCC_PLL1DIVR register  ***************/
21720 #define RCC_PLL1DIVR_PLL1N_Pos              (0U)
21721 #define RCC_PLL1DIVR_PLL1N_Msk              (0x1FFUL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x000001FF */
21722 #define RCC_PLL1DIVR_PLL1N                  RCC_PLL1DIVR_PLL1N_Msk                  /*!< PLL1N[8:0]: bits (Multiplication Factor For PLL1 VCO) */
21723 #define RCC_PLL1DIVR_PLL1N_0                (0x001UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000001 */
21724 #define RCC_PLL1DIVR_PLL1N_1                (0x002UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000002 */
21725 #define RCC_PLL1DIVR_PLL1N_2                (0x004UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000004 */
21726 #define RCC_PLL1DIVR_PLL1N_3                (0x008UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000008 */
21727 #define RCC_PLL1DIVR_PLL1N_4                (0x010UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000010 */
21728 #define RCC_PLL1DIVR_PLL1N_5                (0x020UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000020 */
21729 #define RCC_PLL1DIVR_PLL1N_6                (0x040UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000040 */
21730 #define RCC_PLL1DIVR_PLL1N_7                (0x080UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000080 */
21731 #define RCC_PLL1DIVR_PLL1N_8                (0x100UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000100 */
21732 #define RCC_PLL1DIVR_PLL1P_Pos              (9U)
21733 #define RCC_PLL1DIVR_PLL1P_Msk              (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos)      /*!< 0x0000FE00 */
21734 #define RCC_PLL1DIVR_PLL1P                  RCC_PLL1DIVR_PLL1P_Msk                  /*!< PLL1P[6:0]: bits (PLL1 DIVP Division Factor) */
21735 #define RCC_PLL1DIVR_PLL1P_0                (0x001UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00000200 */
21736 #define RCC_PLL1DIVR_PLL1P_1                (0x002UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00000400 */
21737 #define RCC_PLL1DIVR_PLL1P_2                (0x004UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00000800 */
21738 #define RCC_PLL1DIVR_PLL1P_3                (0x008UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00001000 */
21739 #define RCC_PLL1DIVR_PLL1P_4                (0x010UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00002000 */
21740 #define RCC_PLL1DIVR_PLL1P_5                (0x020UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00004000 */
21741 #define RCC_PLL1DIVR_PLL1P_6                (0x040UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00008000 */
21742 #define RCC_PLL1DIVR_PLL1Q_Pos              (16U)
21743 #define RCC_PLL1DIVR_PLL1Q_Msk              (0x7FUL << RCC_PLL1DIVR_PLL1Q_Pos)      /*!< 0x007F0000 */
21744 #define RCC_PLL1DIVR_PLL1Q                  RCC_PLL1DIVR_PLL1Q_Msk                  /*!< PLL1Q[6:0]: bits (PLL1 DIVQ Division Factor) */
21745 #define RCC_PLL1DIVR_PLL1Q_0                (0x001UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00010000 */
21746 #define RCC_PLL1DIVR_PLL1Q_1                (0x002UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00020000 */
21747 #define RCC_PLL1DIVR_PLL1Q_2                (0x004UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00040000 */
21748 #define RCC_PLL1DIVR_PLL1Q_3                (0x008UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00080000 */
21749 #define RCC_PLL1DIVR_PLL1Q_4                (0x010UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00100000 */
21750 #define RCC_PLL1DIVR_PLL1Q_5                (0x020UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00200020 */
21751 #define RCC_PLL1DIVR_PLL1Q_6                (0x040UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00400000 */
21752 #define RCC_PLL1DIVR_PLL1R_Pos              (24U)
21753 #define RCC_PLL1DIVR_PLL1R_Msk              (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos)      /*!< 0x7F000000 */
21754 #define RCC_PLL1DIVR_PLL1R                  RCC_PLL1DIVR_PLL1R_Msk                  /*!< PLL1R[6:0]: bits (PLL1 DIVR Division Factor) */
21755 #define RCC_PLL1DIVR_PLL1R_0                (0x001UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x01000000 */
21756 #define RCC_PLL1DIVR_PLL1R_1                (0x002UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x02000000 */
21757 #define RCC_PLL1DIVR_PLL1R_2                (0x004UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x04000000 */
21758 #define RCC_PLL1DIVR_PLL1R_3                (0x008UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x08000000 */
21759 #define RCC_PLL1DIVR_PLL1R_4                (0x010UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x10000000 */
21760 #define RCC_PLL1DIVR_PLL1R_5                (0x020UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x20000000 */
21761 #define RCC_PLL1DIVR_PLL1R_6                (0x040UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x40000000 */
21762 
21763 /********************  Bit definition for RCC_PLL1FRACR register  ***************/
21764 #define RCC_PLL1FRACR_PLL1FRACN_Pos         (3U)
21765 #define RCC_PLL1FRACR_PLL1FRACN_Msk         (0x1FFFUL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x0000FFF8 */
21766 #define RCC_PLL1FRACR_PLL1FRACN             RCC_PLL1FRACR_PLL1FRACN_Msk               /*!< PLL1FRACN[12:0]: bits (Fractional Part of the Multiplication Factor for PLL1 VCO) */
21767 #define RCC_PLL1FRACR_PLL1FRACN_0           (0x0001UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000008 */
21768 #define RCC_PLL1FRACR_PLL1FRACN_1           (0x0002UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000010 */
21769 #define RCC_PLL1FRACR_PLL1FRACN_2           (0x0004UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000020 */
21770 #define RCC_PLL1FRACR_PLL1FRACN_3           (0x0008UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000040 */
21771 #define RCC_PLL1FRACR_PLL1FRACN_4           (0x0010UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000080 */
21772 #define RCC_PLL1FRACR_PLL1FRACN_5           (0x0020UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000100 */
21773 #define RCC_PLL1FRACR_PLL1FRACN_6           (0x0040UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000200 */
21774 #define RCC_PLL1FRACR_PLL1FRACN_7           (0x0080UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000400 */
21775 #define RCC_PLL1FRACR_PLL1FRACN_8           (0x0100UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000800 */
21776 #define RCC_PLL1FRACR_PLL1FRACN_9           (0x0200UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00001000 */
21777 #define RCC_PLL1FRACR_PLL1FRACN_10          (0x0400UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00002000 */
21778 #define RCC_PLL1FRACR_PLL1FRACN_11          (0x0800UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00004000 */
21779 #define RCC_PLL1FRACR_PLL1FRACN_12          (0x1000UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00008000 */
21780 
21781 /********************  Bit definition for RCC_PLL2DIVR register  ***************/
21782 #define RCC_PLL2DIVR_PLL2N_Pos              (0U)
21783 #define RCC_PLL2DIVR_PLL2N_Msk              (0x1FFUL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x000001FF */
21784 #define RCC_PLL2DIVR_PLL2N                  RCC_PLL2DIVR_PLL2N_Msk                  /*!< PLL2N[8:0]: bits (Multiplication Factor for PLL2 VCO) */
21785 #define RCC_PLL2DIVR_PLL2N_0                (0x001UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000001 */
21786 #define RCC_PLL2DIVR_PLL2N_1                (0x002UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000002 */
21787 #define RCC_PLL2DIVR_PLL2N_2                (0x004UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000004 */
21788 #define RCC_PLL2DIVR_PLL2N_3                (0x008UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000008 */
21789 #define RCC_PLL2DIVR_PLL2N_4                (0x010UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000010 */
21790 #define RCC_PLL2DIVR_PLL2N_5                (0x020UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000020 */
21791 #define RCC_PLL2DIVR_PLL2N_6                (0x040UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000040 */
21792 #define RCC_PLL2DIVR_PLL2N_7                (0x080UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000080 */
21793 #define RCC_PLL2DIVR_PLL2N_8                (0x100UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000100 */
21794 #define RCC_PLL2DIVR_PLL2P_Pos              (9U)
21795 #define RCC_PLL2DIVR_PLL2P_Msk              (0x7FUL << RCC_PLL2DIVR_PLL2P_Pos)      /*!< 0x0000FE00 */
21796 #define RCC_PLL2DIVR_PLL2P                  RCC_PLL2DIVR_PLL2P_Msk                  /*!< PLL2P[6:0]: bits (PLL2 DIVP Division Factor) */
21797 #define RCC_PLL2DIVR_PLL2P_0                (0x001UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00000200 */
21798 #define RCC_PLL2DIVR_PLL2P_1                (0x002UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00000400 */
21799 #define RCC_PLL2DIVR_PLL2P_2                (0x004UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00000800 */
21800 #define RCC_PLL2DIVR_PLL2P_3                (0x008UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00001000 */
21801 #define RCC_PLL2DIVR_PLL2P_4                (0x010UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00002000 */
21802 #define RCC_PLL2DIVR_PLL2P_5                (0x020UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00004000 */
21803 #define RCC_PLL2DIVR_PLL2P_6                (0x040UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00008000 */
21804 #define RCC_PLL2DIVR_PLL2Q_Pos              (16U)
21805 #define RCC_PLL2DIVR_PLL2Q_Msk              (0x7FUL << RCC_PLL2DIVR_PLL2Q_Pos)      /*!< 0x007F0000 */
21806 #define RCC_PLL2DIVR_PLL2Q                  RCC_PLL2DIVR_PLL2Q_Msk                  /*!< PLL2Q[6:0]: bits (PLL2 DIVQ Division Factor) */
21807 #define RCC_PLL2DIVR_PLL2Q_0                (0x001UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00010000 */
21808 #define RCC_PLL2DIVR_PLL2Q_1                (0x002UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00020000 */
21809 #define RCC_PLL2DIVR_PLL2Q_2                (0x004UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00040000 */
21810 #define RCC_PLL2DIVR_PLL2Q_3                (0x008UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00080000 */
21811 #define RCC_PLL2DIVR_PLL2Q_4                (0x010UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00100000 */
21812 #define RCC_PLL2DIVR_PLL2Q_5                (0x020UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00200020 */
21813 #define RCC_PLL2DIVR_PLL2Q_6                (0x040UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00400000 */
21814 #define RCC_PLL2DIVR_PLL2R_Pos              (24U)
21815 #define RCC_PLL2DIVR_PLL2R_Msk              (0x7FUL << RCC_PLL2DIVR_PLL2R_Pos)      /*!< 0x7F000000 */
21816 #define RCC_PLL2DIVR_PLL2R                  RCC_PLL2DIVR_PLL2R_Msk                  /*!< PLL2R[6:0]: bits (PLL2 DIVR Division Factor) */
21817 #define RCC_PLL2DIVR_PLL2R_0                (0x001UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x01000000 */
21818 #define RCC_PLL2DIVR_PLL2R_1                (0x002UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x02000000 */
21819 #define RCC_PLL2DIVR_PLL2R_2                (0x004UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x04000000 */
21820 #define RCC_PLL2DIVR_PLL2R_3                (0x008UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x08000000 */
21821 #define RCC_PLL2DIVR_PLL2R_4                (0x010UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x10000000 */
21822 #define RCC_PLL2DIVR_PLL2R_5                (0x020UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x20000000 */
21823 #define RCC_PLL2DIVR_PLL2R_6                (0x040UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x40000000 */
21824 
21825 /********************  Bit definition for RCC_PLL2FRACR register  ***************/
21826 #define RCC_PLL2FRACR_PLL2FRACN_Pos         (3U)
21827 #define RCC_PLL2FRACR_PLL2FRACN_Msk         (0x1FFFUL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x0000FFF8 */
21828 #define RCC_PLL2FRACR_PLL2FRACN             RCC_PLL2FRACR_PLL2FRACN_Msk               /*!< PLL2FRACN[12:0]: bits (Fractional Part of the Multiplication Factor for PLL2 VCO) */
21829 #define RCC_PLL2FRACR_PLL2FRACN_0           (0x0001UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000008 */
21830 #define RCC_PLL2FRACR_PLL2FRACN_1           (0x0002UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000010 */
21831 #define RCC_PLL2FRACR_PLL2FRACN_2           (0x0004UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000020 */
21832 #define RCC_PLL2FRACR_PLL2FRACN_3           (0x0008UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000040 */
21833 #define RCC_PLL2FRACR_PLL2FRACN_4           (0x0010UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000080 */
21834 #define RCC_PLL2FRACR_PLL2FRACN_5           (0x0020UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000100 */
21835 #define RCC_PLL2FRACR_PLL2FRACN_6           (0x0040UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000200 */
21836 #define RCC_PLL2FRACR_PLL2FRACN_7           (0x0080UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000400 */
21837 #define RCC_PLL2FRACR_PLL2FRACN_8           (0x0100UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000800 */
21838 #define RCC_PLL2FRACR_PLL2FRACN_9           (0x0200UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00001000 */
21839 #define RCC_PLL2FRACR_PLL2FRACN_10          (0x0400UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00002000 */
21840 #define RCC_PLL2FRACR_PLL2FRACN_11          (0x0800UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00004000 */
21841 #define RCC_PLL2FRACR_PLL2FRACN_12          (0x1000UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00008000 */
21842 
21843 /********************  Bit definition for RCC_PLL3DIVR register  ***************/
21844 #define RCC_PLL3DIVR_PLL3N_Pos              (0U)
21845 #define RCC_PLL3DIVR_PLL3N_Msk              (0x1FFUL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x000001FF */
21846 #define RCC_PLL3DIVR_PLL3N                  RCC_PLL3DIVR_PLL3N_Msk                  /*!< PLL3N[8:0]: bits (Multiplication Factor for PLL3 VCO) */
21847 #define RCC_PLL3DIVR_PLL3N_0                (0x001UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000001 */
21848 #define RCC_PLL3DIVR_PLL3N_1                (0x002UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000002 */
21849 #define RCC_PLL3DIVR_PLL3N_2                (0x004UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000004 */
21850 #define RCC_PLL3DIVR_PLL3N_3                (0x008UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000008 */
21851 #define RCC_PLL3DIVR_PLL3N_4                (0x010UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000010 */
21852 #define RCC_PLL3DIVR_PLL3N_5                (0x020UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000020 */
21853 #define RCC_PLL3DIVR_PLL3N_6                (0x040UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000040 */
21854 #define RCC_PLL3DIVR_PLL3N_7                (0x080UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000080 */
21855 #define RCC_PLL3DIVR_PLL3N_8                (0x100UL << RCC_PLL3DIVR_PLL3N_Pos)     /*!< 0x00000100 */
21856 #define RCC_PLL3DIVR_PLL3P_Pos              (9U)
21857 #define RCC_PLL3DIVR_PLL3P_Msk              (0x7FUL << RCC_PLL3DIVR_PLL3P_Pos)      /*!< 0x0000FE00 */
21858 #define RCC_PLL3DIVR_PLL3P                  RCC_PLL3DIVR_PLL3P_Msk                  /*!< PLL3P[6:0]: bits (PLL2 DIVP Division Factor) */
21859 #define RCC_PLL3DIVR_PLL3P_0                (0x001UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00000200 */
21860 #define RCC_PLL3DIVR_PLL3P_1                (0x002UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00000400 */
21861 #define RCC_PLL3DIVR_PLL3P_2                (0x004UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00000800 */
21862 #define RCC_PLL3DIVR_PLL3P_3                (0x008UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00001000 */
21863 #define RCC_PLL3DIVR_PLL3P_4                (0x010UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00002000 */
21864 #define RCC_PLL3DIVR_PLL3P_5                (0x020UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00004000 */
21865 #define RCC_PLL3DIVR_PLL3P_6                (0x040UL << RCC_PLL3DIVR_PLL3P_Pos)     /*!< 0x00008000 */
21866 #define RCC_PLL3DIVR_PLL3Q_Pos              (16U)
21867 #define RCC_PLL3DIVR_PLL3Q_Msk              (0x7FUL << RCC_PLL3DIVR_PLL3Q_Pos)      /*!< 0x007F0000 */
21868 #define RCC_PLL3DIVR_PLL3Q                  RCC_PLL3DIVR_PLL3Q_Msk                  /*!< PLL3Q[6:0]: bits (PLL3 DIVQ Division Factor) */
21869 #define RCC_PLL3DIVR_PLL3Q_0                (0x001UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00010000 */
21870 #define RCC_PLL3DIVR_PLL3Q_1                (0x002UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00020000 */
21871 #define RCC_PLL3DIVR_PLL3Q_2                (0x004UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00040000 */
21872 #define RCC_PLL3DIVR_PLL3Q_3                (0x008UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00080000 */
21873 #define RCC_PLL3DIVR_PLL3Q_4                (0x010UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00100000 */
21874 #define RCC_PLL3DIVR_PLL3Q_5                (0x020UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00200020 */
21875 #define RCC_PLL3DIVR_PLL3Q_6                (0x040UL << RCC_PLL3DIVR_PLL3Q_Pos)     /*!< 0x00400000 */
21876 #define RCC_PLL3DIVR_PLL3R_Pos              (24U)
21877 #define RCC_PLL3DIVR_PLL3R_Msk              (0x7FUL << RCC_PLL3DIVR_PLL3R_Pos)      /*!< 0x7F000000 */
21878 #define RCC_PLL3DIVR_PLL3R                  RCC_PLL3DIVR_PLL3R_Msk                  /*!< PLL3R[6:0]: bits (PLL3 DIVR Division Factor) */
21879 #define RCC_PLL3DIVR_PLL3R_0                (0x001UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x01000000 */
21880 #define RCC_PLL3DIVR_PLL3R_1                (0x002UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x02000000 */
21881 #define RCC_PLL3DIVR_PLL3R_2                (0x004UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x04000000 */
21882 #define RCC_PLL3DIVR_PLL3R_3                (0x008UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x08000000 */
21883 #define RCC_PLL3DIVR_PLL3R_4                (0x010UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x10000000 */
21884 #define RCC_PLL3DIVR_PLL3R_5                (0x020UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x20000000 */
21885 #define RCC_PLL3DIVR_PLL3R_6                (0x040UL << RCC_PLL3DIVR_PLL3R_Pos)     /*!< 0x40000000 */
21886 
21887 /********************  Bit definition for RCC_PLL3FRACR register  ***************/
21888 #define RCC_PLL3FRACR_PLL3FRACN_Pos         (3U)
21889 #define RCC_PLL3FRACR_PLL3FRACN_Msk         (0x1FFFUL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x0000FFF8 */
21890 #define RCC_PLL3FRACR_PLL3FRACN             RCC_PLL3FRACR_PLL3FRACN_Msk               /*!< PLL3FRACN[12:0]: bits (Fractional Part of the Multiplication Factor for PLL3 VCO) */
21891 #define RCC_PLL3FRACR_PLL3FRACN_0           (0x0001UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000008 */
21892 #define RCC_PLL3FRACR_PLL3FRACN_1           (0x0002UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000010 */
21893 #define RCC_PLL3FRACR_PLL3FRACN_2           (0x0004UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000020 */
21894 #define RCC_PLL3FRACR_PLL3FRACN_3           (0x0008UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000040 */
21895 #define RCC_PLL3FRACR_PLL3FRACN_4           (0x0010UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000080 */
21896 #define RCC_PLL3FRACR_PLL3FRACN_5           (0x0020UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000100 */
21897 #define RCC_PLL3FRACR_PLL3FRACN_6           (0x0040UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000200 */
21898 #define RCC_PLL3FRACR_PLL3FRACN_7           (0x0080UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000400 */
21899 #define RCC_PLL3FRACR_PLL3FRACN_8           (0x0100UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00000800 */
21900 #define RCC_PLL3FRACR_PLL3FRACN_9           (0x0200UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00001000 */
21901 #define RCC_PLL3FRACR_PLL3FRACN_10          (0x0400UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00002000 */
21902 #define RCC_PLL3FRACR_PLL3FRACN_11          (0x0800UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00004000 */
21903 #define RCC_PLL3FRACR_PLL3FRACN_12          (0x1000UL << RCC_PLL3FRACR_PLL3FRACN_Pos) /*!< 0x00008000 */
21904 
21905 /********************  Bit definition for RCC_CIER register  ******************/
21906 #define RCC_CIER_LSIRDYIE_Pos               (0U)
21907 #define RCC_CIER_LSIRDYIE_Msk               (0x1UL << RCC_CIER_LSIRDYIE_Pos)        /*!< 0x00000001 */
21908 #define RCC_CIER_LSIRDYIE                   RCC_CIER_LSIRDYIE_Msk                   /*!< LSI Ready Interrupt Enable */
21909 #define RCC_CIER_LSERDYIE_Pos               (1U)
21910 #define RCC_CIER_LSERDYIE_Msk               (0x1UL << RCC_CIER_LSERDYIE_Pos)        /*!< 0x00000002 */
21911 #define RCC_CIER_LSERDYIE                   RCC_CIER_LSERDYIE_Msk                   /*!< LSE Ready Interrupt Enable */
21912 #define RCC_CIER_MSISRDYIE_Pos              (2U)
21913 #define RCC_CIER_MSISRDYIE_Msk              (0x1UL << RCC_CIER_MSISRDYIE_Pos)       /*!< 0x00000004 */
21914 #define RCC_CIER_MSISRDYIE                  RCC_CIER_MSISRDYIE_Msk                  /*!< MSIS Ready Interrupt Enable */
21915 #define RCC_CIER_HSIRDYIE_Pos               (3U)
21916 #define RCC_CIER_HSIRDYIE_Msk               (0x1UL << RCC_CIER_HSIRDYIE_Pos)        /*!< 0x00000008 */
21917 #define RCC_CIER_HSIRDYIE                   RCC_CIER_HSIRDYIE_Msk                   /*!< HSI16 Ready Interrupt Enable */
21918 #define RCC_CIER_HSERDYIE_Pos               (4U)
21919 #define RCC_CIER_HSERDYIE_Msk               (0x1UL << RCC_CIER_HSERDYIE_Pos)        /*!< 0x00000010 */
21920 #define RCC_CIER_HSERDYIE                   RCC_CIER_HSERDYIE_Msk                   /*!< HSE Ready Interrupt Enable */
21921 #define RCC_CIER_HSI48RDYIE_Pos             (5U)
21922 #define RCC_CIER_HSI48RDYIE_Msk             (0x1UL << RCC_CIER_HSI48RDYIE_Pos)      /*!< 0x00000020 */
21923 #define RCC_CIER_HSI48RDYIE                 RCC_CIER_HSI48RDYIE_Msk                 /*!< HSI48 Ready Interrupt Enable */
21924 #define RCC_CIER_PLL1RDYIE_Pos              (6U)
21925 #define RCC_CIER_PLL1RDYIE_Msk              (0x1UL << RCC_CIER_PLL1RDYIE_Pos)       /*!< 0x00000040 */
21926 #define RCC_CIER_PLL1RDYIE                  RCC_CIER_PLL1RDYIE_Msk                  /*!< PLL Ready Interrupt Enable */
21927 #define RCC_CIER_PLL2RDYIE_Pos              (7U)
21928 #define RCC_CIER_PLL2RDYIE_Msk              (0x1UL << RCC_CIER_PLL2RDYIE_Pos)       /*!< 0x00000080 */
21929 #define RCC_CIER_PLL2RDYIE                  RCC_CIER_PLL2RDYIE_Msk                  /*!< PLL2 Ready Interrupt Enable */
21930 #define RCC_CIER_PLL3RDYIE_Pos              (8U)
21931 #define RCC_CIER_PLL3RDYIE_Msk              (0x1UL << RCC_CIER_PLL3RDYIE_Pos)       /*!< 0x00000100 */
21932 #define RCC_CIER_PLL3RDYIE                  RCC_CIER_PLL3RDYIE_Msk                  /*!< PLL3 Ready Interrupt Enable */
21933 #define RCC_CIER_MSIKRDYIE_Pos              (11U)
21934 #define RCC_CIER_MSIKRDYIE_Msk              (0x1UL << RCC_CIER_MSIKRDYIE_Pos)       /*!< 0x00000080 */
21935 #define RCC_CIER_MSIKRDYIE                  RCC_CIER_MSIKRDYIE_Msk                  /*!< MSIK Ready Interrupt Enable */
21936 #define RCC_CIER_SHSIRDYIE_Pos              (12U)
21937 #define RCC_CIER_SHSIRDYIE_Msk              (0x1UL << RCC_CIER_SHSIRDYIE_Pos)       /*!< 0x00000100 */
21938 #define RCC_CIER_SHSIRDYIE                  RCC_CIER_SHSIRDYIE_Msk                  /*!< SHSI Ready Interrupt Enable */
21939 
21940 /********************  Bit definition for RCC_CIFR register  ****************/
21941 #define RCC_CIFR_LSIRDYF_Pos                (0U)
21942 #define RCC_CIFR_LSIRDYF_Msk                (0x1UL << RCC_CIFR_LSIRDYF_Pos)         /*!< 0x00000001 */
21943 #define RCC_CIFR_LSIRDYF                    RCC_CIFR_LSIRDYF_Msk                    /*!< LSI Ready Interrupt Flag */
21944 #define RCC_CIFR_LSERDYF_Pos                (1U)
21945 #define RCC_CIFR_LSERDYF_Msk                (0x1UL << RCC_CIFR_LSERDYF_Pos)         /*!< 0x00000002 */
21946 #define RCC_CIFR_LSERDYF                    RCC_CIFR_LSERDYF_Msk                    /*!< LSE Ready Interrupt Flag */
21947 #define RCC_CIFR_MSISRDYF_Pos               (2U)
21948 #define RCC_CIFR_MSISRDYF_Msk               (0x1UL << RCC_CIFR_MSISRDYF_Pos)        /*!< 0x00000004 */
21949 #define RCC_CIFR_MSISRDYF                   RCC_CIFR_MSISRDYF_Msk                   /*!< MSIS Ready Interrupt Flag */
21950 #define RCC_CIFR_HSIRDYF_Pos                (3U)
21951 #define RCC_CIFR_HSIRDYF_Msk                (0x1UL << RCC_CIFR_HSIRDYF_Pos)         /*!< 0x00000008 */
21952 #define RCC_CIFR_HSIRDYF                    RCC_CIFR_HSIRDYF_Msk                    /*!< HSI16 Ready Interrupt Flag */
21953 #define RCC_CIFR_HSERDYF_Pos                (4U)
21954 #define RCC_CIFR_HSERDYF_Msk                (0x1UL << RCC_CIFR_HSERDYF_Pos)         /*!< 0x00000010 */
21955 #define RCC_CIFR_HSERDYF                    RCC_CIFR_HSERDYF_Msk                    /*!< HSE Ready Interrupt Flag */
21956 #define RCC_CIFR_HSI48RDYF_Pos              (5U)
21957 #define RCC_CIFR_HSI48RDYF_Msk              (0x1UL << RCC_CIFR_HSI48RDYF_Pos)       /*!< 0x00000020 */
21958 #define RCC_CIFR_HSI48RDYF                  RCC_CIFR_HSI48RDYF_Msk                  /*!< HSI48 Ready Interrupt Flag */
21959 #define RCC_CIFR_PLL1RDYF_Pos               (6U)
21960 #define RCC_CIFR_PLL1RDYF_Msk               (0x1UL << RCC_CIFR_PLL1RDYF_Pos)        /*!< 0x00000040 */
21961 #define RCC_CIFR_PLL1RDYF                   RCC_CIFR_PLL1RDYF_Msk                   /*!< PLL1 Ready Interrupt Flag */
21962 #define RCC_CIFR_PLL2RDYF_Pos               (7U)
21963 #define RCC_CIFR_PLL2RDYF_Msk               (0x1UL << RCC_CIFR_PLL2RDYF_Pos)        /*!< 0x00000080 */
21964 #define RCC_CIFR_PLL2RDYF                   RCC_CIFR_PLL2RDYF_Msk                   /*!< PLL2 Ready Interrupt Flag */
21965 #define RCC_CIFR_PLL3RDYF_Pos               (8U)
21966 #define RCC_CIFR_PLL3RDYF_Msk               (0x1UL << RCC_CIFR_PLL3RDYF_Pos)        /*!< 0x00000100 */
21967 #define RCC_CIFR_PLL3RDYF                   RCC_CIFR_PLL3RDYF_Msk                   /*!< PLL3 Ready Interrupt Flag */
21968 #define RCC_CIFR_CSSF_Pos                   (10U)
21969 #define RCC_CIFR_CSSF_Msk                   (0x1UL << RCC_CIFR_CSSF_Pos)            /*!< 0x00000400 */
21970 #define RCC_CIFR_CSSF                       RCC_CIFR_CSSF_Msk                       /*!< Clock Security System Interrupt Flag */
21971 #define RCC_CIFR_MSIKRDYF_Pos               (11U)
21972 #define RCC_CIFR_MSIKRDYF_Msk               (0x1UL << RCC_CIFR_MSIKRDYF_Pos)        /*!< 0x00000080 */
21973 #define RCC_CIFR_MSIKRDYF                   RCC_CIFR_MSIKRDYF_Msk                   /*!< MSIK Ready Interrupt Flag */
21974 #define RCC_CIFR_SHSIRDYF_Pos               (12U)
21975 #define RCC_CIFR_SHSIRDYF_Msk               (0x1UL << RCC_CIFR_SHSIRDYF_Pos)        /*!< 0x00000100 */
21976 #define RCC_CIFR_SHSIRDYF                   RCC_CIFR_SHSIRDYF_Msk                   /*!< SHSI Ready Interrupt Flag */
21977 
21978 /********************  Bit definition for RCC_CICR register  ****************/
21979 #define RCC_CICR_LSIRDYC_Pos                (0U)
21980 #define RCC_CICR_LSIRDYC_Msk                (0x1UL << RCC_CICR_LSIRDYC_Pos)         /*!< 0x00000001 */
21981 #define RCC_CICR_LSIRDYC                    RCC_CICR_LSIRDYC_Msk                    /*!< LSI Ready Interrupt Clear */
21982 #define RCC_CICR_LSERDYC_Pos                (1U)
21983 #define RCC_CICR_LSERDYC_Msk                (0x1UL << RCC_CICR_LSERDYC_Pos)         /*!< 0x00000002 */
21984 #define RCC_CICR_LSERDYC                    RCC_CICR_LSERDYC_Msk                    /*!< LSE Ready Interrupt Clear */
21985 #define RCC_CICR_MSISRDYC_Pos               (2U)
21986 #define RCC_CICR_MSISRDYC_Msk               (0x1UL << RCC_CICR_MSISRDYC_Pos)        /*!< 0x00000004 */
21987 #define RCC_CICR_MSISRDYC                   RCC_CICR_MSISRDYC_Msk                   /*!< MSIS Ready Interrupt Clear */
21988 #define RCC_CICR_HSIRDYC_Pos                (3U)
21989 #define RCC_CICR_HSIRDYC_Msk                (0x1UL << RCC_CICR_HSIRDYC_Pos)         /*!< 0x00000008 */
21990 #define RCC_CICR_HSIRDYC                    RCC_CICR_HSIRDYC_Msk                    /*!< HSI16 Ready Interrupt Clear */
21991 #define RCC_CICR_HSERDYC_Pos                (4U)
21992 #define RCC_CICR_HSERDYC_Msk                (0x1UL << RCC_CICR_HSERDYC_Pos)         /*!< 0x00000010 */
21993 #define RCC_CICR_HSERDYC                    RCC_CICR_HSERDYC_Msk                    /*!< HSE Ready Interrupt Clear */
21994 #define RCC_CICR_HSI48RDYC_Pos              (5U)
21995 #define RCC_CICR_HSI48RDYC_Msk              (0x1UL << RCC_CICR_HSI48RDYC_Pos)       /*!< 0x00000020 */
21996 #define RCC_CICR_HSI48RDYC                  RCC_CICR_HSI48RDYC_Msk                  /*!< HSI48 Ready Interrupt Clear */
21997 #define RCC_CICR_PLL1RDYC_Pos               (6U)
21998 #define RCC_CICR_PLL1RDYC_Msk               (0x1UL << RCC_CICR_PLL1RDYC_Pos)        /*!< 0x00000040 */
21999 #define RCC_CICR_PLL1RDYC                   RCC_CICR_PLL1RDYC_Msk                   /*!< PLL1 Ready Interrupt Clear */
22000 #define RCC_CICR_PLL2RDYC_Pos               (7U)
22001 #define RCC_CICR_PLL2RDYC_Msk               (0x1UL << RCC_CICR_PLL2RDYC_Pos)        /*!< 0x00000080 */
22002 #define RCC_CICR_PLL2RDYC                   RCC_CICR_PLL2RDYC_Msk                   /*!< PLL2 Ready Interrupt Clear */
22003 #define RCC_CICR_PLL3RDYC_Pos               (8U)
22004 #define RCC_CICR_PLL3RDYC_Msk               (0x1UL << RCC_CICR_PLL3RDYC_Pos)        /*!< 0x00000100 */
22005 #define RCC_CICR_PLL3RDYC                   RCC_CICR_PLL3RDYC_Msk                   /*!< PLL3 Ready Interrupt Clear */
22006 #define RCC_CICR_CSSC_Pos                   (10U)
22007 #define RCC_CICR_CSSC_Msk                   (0x1UL << RCC_CICR_CSSC_Pos)            /*!< 0x00000400 */
22008 #define RCC_CICR_CSSC                       RCC_CICR_CSSC_Msk                       /*!< Clock Security System Interrupt Clear */
22009 #define RCC_CICR_MSIKRDYC_Pos               (11U)
22010 #define RCC_CICR_MSIKRDYC_Msk               (0x1UL << RCC_CICR_MSIKRDYC_Pos)        /*!< 0x00000080 */
22011 #define RCC_CICR_MSIKRDYC                   RCC_CICR_MSIKRDYC_Msk                   /*!< MSIK Ready Interrupt Clear */
22012 #define RCC_CICR_SHSIRDYC_Pos               (12U)
22013 #define RCC_CICR_SHSIRDYC_Msk               (0x1UL << RCC_CICR_SHSIRDYC_Pos)        /*!< 0x00000100 */
22014 #define RCC_CICR_SHSIRDYC                   RCC_CICR_SHSIRDYC_Msk                   /*!< SHSI Ready Interrupt Clear */
22015 
22016 /********************  Bit definition for RCC_AHB1RSTR register  **************/
22017 #define RCC_AHB1RSTR_GPDMA1RST_Pos          (0U)
22018 #define RCC_AHB1RSTR_GPDMA1RST_Msk          (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos)   /*!< 0x00000001 */
22019 #define RCC_AHB1RSTR_GPDMA1RST              RCC_AHB1RSTR_GPDMA1RST_Msk              /*!< GPDMA1 Reset */
22020 #define RCC_AHB1RSTR_CORDICRST_Pos          (1U)
22021 #define RCC_AHB1RSTR_CORDICRST_Msk          (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)   /*!< 0x00000002 */
22022 #define RCC_AHB1RSTR_CORDICRST              RCC_AHB1RSTR_CORDICRST_Msk              /*!< CORDIC Reset */
22023 #define RCC_AHB1RSTR_FMACRST_Pos            (2U)
22024 #define RCC_AHB1RSTR_FMACRST_Msk            (0x1UL << RCC_AHB1RSTR_FMACRST_Pos)     /*!< 0x00000004 */
22025 #define RCC_AHB1RSTR_FMACRST                RCC_AHB1RSTR_FMACRST_Msk                /*!< FMAC Reset */
22026 #define RCC_AHB1RSTR_MDF1RST_Pos            (3U)
22027 #define RCC_AHB1RSTR_MDF1RST_Msk            (0x1UL << RCC_AHB1RSTR_MDF1RST_Pos)     /*!< 0x00000008 */
22028 #define RCC_AHB1RSTR_MDF1RST                RCC_AHB1RSTR_MDF1RST_Msk                /*!< MDF1 Reset */
22029 #define RCC_AHB1RSTR_CRCRST_Pos             (12U)
22030 #define RCC_AHB1RSTR_CRCRST_Msk             (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)      /*!< 0x00001000 */
22031 #define RCC_AHB1RSTR_CRCRST                 RCC_AHB1RSTR_CRCRST_Msk                 /*!< CRC Reset */
22032 #define RCC_AHB1RSTR_JPEGRST_Pos            (15U)
22033 #define RCC_AHB1RSTR_JPEGRST_Msk            (0x1UL << RCC_AHB1RSTR_JPEGRST_Pos)     /*!< 0x00008000 */
22034 #define RCC_AHB1RSTR_JPEGRST                RCC_AHB1RSTR_JPEGRST_Msk                /*!< JPEG Reset */
22035 #define RCC_AHB1RSTR_TSCRST_Pos             (16U)
22036 #define RCC_AHB1RSTR_TSCRST_Msk             (0x1UL << RCC_AHB1RSTR_TSCRST_Pos)      /*!< 0x00010000 */
22037 #define RCC_AHB1RSTR_TSCRST                 RCC_AHB1RSTR_TSCRST_Msk                 /*!< TSC Reset */
22038 #define RCC_AHB1RSTR_RAMCFGRST_Pos          (17U)
22039 #define RCC_AHB1RSTR_RAMCFGRST_Msk          (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos)   /*!< 0x00020000 */
22040 #define RCC_AHB1RSTR_RAMCFGRST              RCC_AHB1RSTR_RAMCFGRST_Msk              /*!< RAMCFG Reset */
22041 #define RCC_AHB1RSTR_DMA2DRST_Pos           (18U)
22042 #define RCC_AHB1RSTR_DMA2DRST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos)    /*!< 0x00040000 */
22043 #define RCC_AHB1RSTR_DMA2DRST               RCC_AHB1RSTR_DMA2DRST_Msk               /*!< DMA2D Reset */
22044 #define RCC_AHB1RSTR_GFXMMURST_Pos          (19U)
22045 #define RCC_AHB1RSTR_GFXMMURST_Msk          (0x1UL << RCC_AHB1RSTR_GFXMMURST_Pos)   /*!< 0x00080000 */
22046 #define RCC_AHB1RSTR_GFXMMURST              RCC_AHB1RSTR_GFXMMURST_Msk
22047 #define RCC_AHB1RSTR_GPU2DRST_Pos           (20U)
22048 #define RCC_AHB1RSTR_GPU2DRST_Msk           (0x1UL << RCC_AHB1RSTR_GPU2DRST_Pos)    /*!< 0x00100000 */
22049 #define RCC_AHB1RSTR_GPU2DRST               RCC_AHB1RSTR_GPU2DRST_Msk
22050 
22051 /********************  Bit definition for RCC_AHB2RSTR1 register  **************/
22052 #define RCC_AHB2RSTR1_GPIOARST_Pos          (0U)
22053 #define RCC_AHB2RSTR1_GPIOARST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOARST_Pos)    /*!< 0x00000001 */
22054 #define RCC_AHB2RSTR1_GPIOARST              RCC_AHB2RSTR1_GPIOARST_Msk               /*!< IO port A Reset */
22055 #define RCC_AHB2RSTR1_GPIOBRST_Pos          (1U)
22056 #define RCC_AHB2RSTR1_GPIOBRST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOBRST_Pos)    /*!< 0x00000002 */
22057 #define RCC_AHB2RSTR1_GPIOBRST              RCC_AHB2RSTR1_GPIOBRST_Msk               /*!< IO port B Reset */
22058 #define RCC_AHB2RSTR1_GPIOCRST_Pos          (2U)
22059 #define RCC_AHB2RSTR1_GPIOCRST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOCRST_Pos)    /*!< 0x00000004 */
22060 #define RCC_AHB2RSTR1_GPIOCRST              RCC_AHB2RSTR1_GPIOCRST_Msk               /*!< IO port C Reset */
22061 #define RCC_AHB2RSTR1_GPIODRST_Pos          (3U)
22062 #define RCC_AHB2RSTR1_GPIODRST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIODRST_Pos)    /*!< 0x00000008 */
22063 #define RCC_AHB2RSTR1_GPIODRST              RCC_AHB2RSTR1_GPIODRST_Msk               /*!< IO port D Reset */
22064 #define RCC_AHB2RSTR1_GPIOERST_Pos          (4U)
22065 #define RCC_AHB2RSTR1_GPIOERST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOERST_Pos)    /*!< 0x00000010 */
22066 #define RCC_AHB2RSTR1_GPIOERST              RCC_AHB2RSTR1_GPIOERST_Msk               /*!< IO port E Reset */
22067 #define RCC_AHB2RSTR1_GPIOFRST_Pos          (5U)
22068 #define RCC_AHB2RSTR1_GPIOFRST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOFRST_Pos)    /*!< 0x00000020 */
22069 #define RCC_AHB2RSTR1_GPIOFRST              RCC_AHB2RSTR1_GPIOFRST_Msk               /*!< IO port F Reset */
22070 #define RCC_AHB2RSTR1_GPIOGRST_Pos          (6U)
22071 #define RCC_AHB2RSTR1_GPIOGRST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOGRST_Pos)    /*!< 0x00000040 */
22072 #define RCC_AHB2RSTR1_GPIOGRST              RCC_AHB2RSTR1_GPIOGRST_Msk               /*!< IO port G Reset */
22073 #define RCC_AHB2RSTR1_GPIOHRST_Pos          (7U)
22074 #define RCC_AHB2RSTR1_GPIOHRST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOHRST_Pos)    /*!< 0x00000080 */
22075 #define RCC_AHB2RSTR1_GPIOHRST              RCC_AHB2RSTR1_GPIOHRST_Msk               /*!< IO port H Reset */
22076 #define RCC_AHB2RSTR1_GPIOIRST_Pos          (8U)
22077 #define RCC_AHB2RSTR1_GPIOIRST_Msk          (0x1UL << RCC_AHB2RSTR1_GPIOIRST_Pos)    /*!< 0x00000100 */
22078 #define RCC_AHB2RSTR1_GPIOIRST              RCC_AHB2RSTR1_GPIOIRST_Msk               /*!< IO port I Reset */
22079 #define RCC_AHB2RSTR1_GPIOJRST_Pos           (9U)
22080 #define RCC_AHB2RSTR1_GPIOJRST_Msk           (0x1UL << RCC_AHB2RSTR1_GPIOJRST_Pos)    /*!< 0x00000200 */
22081 #define RCC_AHB2RSTR1_GPIOJRST               RCC_AHB2RSTR1_GPIOJRST_Msk
22082 #define RCC_AHB2RSTR1_ADC12RST_Pos           (10U)
22083 #define RCC_AHB2RSTR1_ADC12RST_Msk           (0x1UL << RCC_AHB2RSTR1_ADC12RST_Pos)     /*!< 0x00000400 */
22084 #define RCC_AHB2RSTR1_ADC12RST               RCC_AHB2RSTR1_ADC12RST_Msk                /*!< ADC1 Reset */
22085 #define RCC_AHB2RSTR1_DCMI_PSSIRST_Pos      (12U)
22086 #define RCC_AHB2RSTR1_DCMI_PSSIRST_Msk      (0x1UL << RCC_AHB2RSTR1_DCMI_PSSIRST_Pos) /*!< 0x00001000 */
22087 #define RCC_AHB2RSTR1_DCMI_PSSIRST          RCC_AHB2RSTR1_DCMI_PSSIRST_Msk            /*!< DCMI and PSSI Reset */
22088 #define RCC_AHB2RSTR1_OTGRST_Pos            (14U)
22089 #define RCC_AHB2RSTR1_OTGRST_Msk            (0x1UL << RCC_AHB2RSTR1_OTGRST_Pos)    /*!< 0x00004000 */
22090 #define RCC_AHB2RSTR1_OTGRST                RCC_AHB2RSTR1_OTGRST_Msk               /*!< OTG Reset */
22091 #define RCC_AHB2RSTR1_AESRST_Pos            (16U)
22092 #define RCC_AHB2RSTR1_AESRST_Msk            (0x1UL << RCC_AHB2RSTR1_AESRST_Pos)      /*!< 0x00010000 */
22093 #define RCC_AHB2RSTR1_AESRST                RCC_AHB2RSTR1_AESRST_Msk                 /*!< AES Hardware Accelerator Reset */
22094 #define RCC_AHB2RSTR1_HASHRST_Pos           (17U)
22095 #define RCC_AHB2RSTR1_HASHRST_Msk           (0x1UL << RCC_AHB2RSTR1_HASHRST_Pos)     /*!< 0x00020000 */
22096 #define RCC_AHB2RSTR1_HASHRST               RCC_AHB2RSTR1_HASHRST_Msk                /*!< Hash Reset */
22097 #define RCC_AHB2RSTR1_RNGRST_Pos            (18U)
22098 #define RCC_AHB2RSTR1_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR1_RNGRST_Pos)      /*!< 0x00040000 */
22099 #define RCC_AHB2RSTR1_RNGRST                RCC_AHB2RSTR1_RNGRST_Msk                 /*!< Random Number Generator Reset */
22100 #define RCC_AHB2RSTR1_PKARST_Pos            (19U)
22101 #define RCC_AHB2RSTR1_PKARST_Msk            (0x1UL << RCC_AHB2RSTR1_PKARST_Pos)      /*!< 0x00080000 */
22102 #define RCC_AHB2RSTR1_PKARST                RCC_AHB2RSTR1_PKARST_Msk                 /*!< PKA reset */
22103 #define RCC_AHB2RSTR1_SAESRST_Pos           (20U)
22104 #define RCC_AHB2RSTR1_SAESRST_Msk           (0x1UL << RCC_AHB2RSTR1_SAESRST_Pos)     /*!< 0x00080000 */
22105 #define RCC_AHB2RSTR1_SAESRST               RCC_AHB2RSTR1_SAESRST_Msk                /*!< SAES Hardware Accelerator Reset */
22106 #define RCC_AHB2RSTR1_OCTOSPIMRST_Pos       (21U)
22107 #define RCC_AHB2RSTR1_OCTOSPIMRST_Msk       (0x1UL << RCC_AHB2RSTR1_OCTOSPIMRST_Pos) /*!< 0x00200000 */
22108 #define RCC_AHB2RSTR1_OCTOSPIMRST           RCC_AHB2RSTR1_OCTOSPIMRST_Msk            /*!< OCTOSPIM Reset */
22109 #define RCC_AHB2RSTR1_OTFDEC1RST_Pos        (23U)
22110 #define RCC_AHB2RSTR1_OTFDEC1RST_Msk        (0x1UL << RCC_AHB2RSTR1_OTFDEC1RST_Pos)  /*!< 0x00800000 */
22111 #define RCC_AHB2RSTR1_OTFDEC1RST            RCC_AHB2RSTR1_OTFDEC1RST_Msk             /*!< OTFDEC1 Reset */
22112 #define RCC_AHB2RSTR1_OTFDEC2RST_Pos        (24U)
22113 #define RCC_AHB2RSTR1_OTFDEC2RST_Msk        (0x1UL << RCC_AHB2RSTR1_OTFDEC2RST_Pos)  /*!< 0x01000000 */
22114 #define RCC_AHB2RSTR1_OTFDEC2RST            RCC_AHB2RSTR1_OTFDEC2RST_Msk             /*!< OTFDEC2 Reset */
22115 #define RCC_AHB2RSTR1_SDMMC1RST_Pos         (27U)
22116 #define RCC_AHB2RSTR1_SDMMC1RST_Msk         (0x1UL << RCC_AHB2RSTR1_SDMMC1RST_Pos)   /*!< 0x08000000 */
22117 #define RCC_AHB2RSTR1_SDMMC1RST             RCC_AHB2RSTR1_SDMMC1RST_Msk              /*!< SDMMC1 Reset */
22118 #define RCC_AHB2RSTR1_SDMMC2RST_Pos         (28U)
22119 #define RCC_AHB2RSTR1_SDMMC2RST_Msk         (0x1UL << RCC_AHB2RSTR1_SDMMC2RST_Pos)   /*!< 0x08000000 */
22120 #define RCC_AHB2RSTR1_SDMMC2RST             RCC_AHB2RSTR1_SDMMC2RST_Msk              /*!< SDMMC2 Reset */
22121 
22122 /********************  Bit definition for RCC_AHB2RSTR2 register  **************/
22123 #define RCC_AHB2RSTR2_FSMCRST_Pos           (0U)
22124 #define RCC_AHB2RSTR2_FSMCRST_Msk           (0x1UL << RCC_AHB2RSTR2_FSMCRST_Pos)     /*!< 0x00000001 */
22125 #define RCC_AHB2RSTR2_FSMCRST               RCC_AHB2RSTR2_FSMCRST_Msk                /*!< Flexible Memory Controller Reset */
22126 #define RCC_AHB2RSTR2_OCTOSPI1RST_Pos       (4U)
22127 #define RCC_AHB2RSTR2_OCTOSPI1RST_Msk       (0x1UL << RCC_AHB2RSTR2_OCTOSPI1RST_Pos) /*!< 0x00000010 */
22128 #define RCC_AHB2RSTR2_OCTOSPI1RST           RCC_AHB2RSTR2_OCTOSPI1RST_Msk            /*!< OCTOSPI1 Reset */
22129 #define RCC_AHB2RSTR2_OCTOSPI2RST_Pos       (8U)
22130 #define RCC_AHB2RSTR2_OCTOSPI2RST_Msk       (0x1UL << RCC_AHB2RSTR2_OCTOSPI2RST_Pos) /*!< 0x00000100 */
22131 #define RCC_AHB2RSTR2_OCTOSPI2RST           RCC_AHB2RSTR2_OCTOSPI2RST_Msk            /*!< OCTOSPI2 Reset */
22132 #define RCC_AHB2RSTR2_HSPI1RST_Pos           (12U)
22133 #define RCC_AHB2RSTR2_HSPI1RST_Msk           (0x1UL << RCC_AHB2RSTR2_HSPI1RST_Pos)    /*!< 0x00001000 */
22134 #define RCC_AHB2RSTR2_HSPI1RST               RCC_AHB2RSTR2_HSPI1RST_Msk
22135 
22136 /********************  Bit definition for RCC_AHB3RSTR register  **************/
22137 #define RCC_AHB3RSTR_LPGPIO1RST_Pos         (0U)
22138 #define RCC_AHB3RSTR_LPGPIO1RST_Msk         (0x1UL << RCC_AHB3RSTR_LPGPIO1RST_Pos)  /*!< 0x00000001 */
22139 #define RCC_AHB3RSTR_LPGPIO1RST             RCC_AHB3RSTR_LPGPIO1RST_Msk             /*!< LPGPIO1 Reset */
22140 #define RCC_AHB3RSTR_ADC4RST_Pos            (5U)
22141 #define RCC_AHB3RSTR_ADC4RST_Msk            (0x1UL << RCC_AHB3RSTR_ADC4RST_Pos)     /*!< 0x00000040 */
22142 #define RCC_AHB3RSTR_ADC4RST                RCC_AHB3RSTR_ADC4RST_Msk                /*!< ADC4 Reset */
22143 #define RCC_AHB3RSTR_DAC1RST_Pos            (6U)
22144 #define RCC_AHB3RSTR_DAC1RST_Msk            (0x1UL << RCC_AHB3RSTR_DAC1RST_Pos)     /*!< 0x00000040 */
22145 #define RCC_AHB3RSTR_DAC1RST                RCC_AHB3RSTR_DAC1RST_Msk                /*!< DAC1 Reset */
22146 #define RCC_AHB3RSTR_LPDMA1RST_Pos          (9U)
22147 #define RCC_AHB3RSTR_LPDMA1RST_Msk          (0x1UL << RCC_AHB3RSTR_LPDMA1RST_Pos)   /*!< 0x000000080 */
22148 #define RCC_AHB3RSTR_LPDMA1RST              RCC_AHB3RSTR_LPDMA1RST_Msk              /*!< LPDMA1 Reset */
22149 #define RCC_AHB3RSTR_ADF1RST_Pos            (10U)
22150 #define RCC_AHB3RSTR_ADF1RST_Msk            (0x1UL << RCC_AHB3RSTR_ADF1RST_Pos)     /*!< 0x000000400 */
22151 #define RCC_AHB3RSTR_ADF1RST                RCC_AHB3RSTR_ADF1RST_Msk                /*!< ADF1 Reset */
22152 
22153 /********************  Bit definition for RCC_APB1RSTR1 register  **************/
22154 #define RCC_APB1RSTR1_TIM2RST_Pos           (0U)
22155 #define RCC_APB1RSTR1_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)    /*!< 0x00000001 */
22156 #define RCC_APB1RSTR1_TIM2RST               RCC_APB1RSTR1_TIM2RST_Msk               /*!< TIM2 Reset */
22157 #define RCC_APB1RSTR1_TIM3RST_Pos           (1U)
22158 #define RCC_APB1RSTR1_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)    /*!< 0x00000002 */
22159 #define RCC_APB1RSTR1_TIM3RST               RCC_APB1RSTR1_TIM3RST_Msk               /*!< TIM3 Reset */
22160 #define RCC_APB1RSTR1_TIM4RST_Pos           (2U)
22161 #define RCC_APB1RSTR1_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)    /*!< 0x00000004 */
22162 #define RCC_APB1RSTR1_TIM4RST               RCC_APB1RSTR1_TIM4RST_Msk               /*!< TIM4 Reset */
22163 #define RCC_APB1RSTR1_TIM5RST_Pos           (3U)
22164 #define RCC_APB1RSTR1_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)    /*!< 0x00000008 */
22165 #define RCC_APB1RSTR1_TIM5RST               RCC_APB1RSTR1_TIM5RST_Msk               /*!< TIM5 Reset */
22166 #define RCC_APB1RSTR1_TIM6RST_Pos           (4U)
22167 #define RCC_APB1RSTR1_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)    /*!< 0x00000010 */
22168 #define RCC_APB1RSTR1_TIM6RST               RCC_APB1RSTR1_TIM6RST_Msk               /*!< TIM6 Reset */
22169 #define RCC_APB1RSTR1_TIM7RST_Pos           (5U)
22170 #define RCC_APB1RSTR1_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)    /*!< 0x00000020 */
22171 #define RCC_APB1RSTR1_TIM7RST               RCC_APB1RSTR1_TIM7RST_Msk               /*!< TIM7 Reset */
22172 #define RCC_APB1RSTR1_SPI2RST_Pos           (14U)
22173 #define RCC_APB1RSTR1_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)    /*!< 0x00004000 */
22174 #define RCC_APB1RSTR1_SPI2RST               RCC_APB1RSTR1_SPI2RST_Msk               /*!< SPI2 Reset */
22175 #define RCC_APB1RSTR1_USART2RST_Pos         (17U)
22176 #define RCC_APB1RSTR1_USART2RST_Msk         (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)  /*!< 0x00020000 */
22177 #define RCC_APB1RSTR1_USART2RST             RCC_APB1RSTR1_USART2RST_Msk             /*!< USART2 Reset */
22178 #define RCC_APB1RSTR1_USART3RST_Pos         (18U)
22179 #define RCC_APB1RSTR1_USART3RST_Msk         (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)  /*!< 0x00040000 */
22180 #define RCC_APB1RSTR1_USART3RST             RCC_APB1RSTR1_USART3RST_Msk             /*!< USART3 Reset */
22181 #define RCC_APB1RSTR1_UART4RST_Pos          (19U)
22182 #define RCC_APB1RSTR1_UART4RST_Msk          (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)   /*!< 0x00080000 */
22183 #define RCC_APB1RSTR1_UART4RST              RCC_APB1RSTR1_UART4RST_Msk              /*!< UART4 Reset */
22184 #define RCC_APB1RSTR1_UART5RST_Pos          (20U)
22185 #define RCC_APB1RSTR1_UART5RST_Msk          (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)   /*!< 0x00100000 */
22186 #define RCC_APB1RSTR1_UART5RST              RCC_APB1RSTR1_UART5RST_Msk              /*!< UART5 Reset */
22187 #define RCC_APB1RSTR1_I2C1RST_Pos           (21U)
22188 #define RCC_APB1RSTR1_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)    /*!< 0x00200000 */
22189 #define RCC_APB1RSTR1_I2C1RST               RCC_APB1RSTR1_I2C1RST_Msk               /*!< I2C1 Reset */
22190 #define RCC_APB1RSTR1_I2C2RST_Pos           (22U)
22191 #define RCC_APB1RSTR1_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)    /*!< 0x00400000 */
22192 #define RCC_APB1RSTR1_I2C2RST               RCC_APB1RSTR1_I2C2RST_Msk               /*!< I2C2 Reset */
22193 #define RCC_APB1RSTR1_CRSRST_Pos            (24U)
22194 #define RCC_APB1RSTR1_CRSRST_Msk            (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)     /*!< 0x01000000 */
22195 #define RCC_APB1RSTR1_CRSRST                RCC_APB1RSTR1_CRSRST_Msk                /*!< CRS Reset */
22196 #define RCC_APB1RSTR1_USART6RST_Pos         (25U)
22197 #define RCC_APB1RSTR1_USART6RST_Msk         (0x1UL << RCC_APB1RSTR1_USART6RST_Pos)  /*!< 0x02000000 */
22198 #define RCC_APB1RSTR1_USART6RST             RCC_APB1RSTR1_USART6RST_Msk
22199 
22200 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
22201 #define RCC_APB1RSTR2_I2C4RST_Pos           (1U)
22202 #define RCC_APB1RSTR2_I2C4RST_Msk           (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos)    /*!< 0x00000002 */
22203 #define RCC_APB1RSTR2_I2C4RST               RCC_APB1RSTR2_I2C4RST_Msk               /*!< I2C4 Reset */
22204 #define RCC_APB1RSTR2_LPTIM2RST_Pos         (5U)
22205 #define RCC_APB1RSTR2_LPTIM2RST_Msk         (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)  /*!< 0x00000020 */
22206 #define RCC_APB1RSTR2_LPTIM2RST             RCC_APB1RSTR2_LPTIM2RST_Msk             /*!< LPTIM2 Reset */
22207 #define RCC_APB1RSTR2_I2C5RST_Pos           (6U)
22208 #define RCC_APB1RSTR2_I2C5RST_Msk           (0x1UL << RCC_APB1RSTR2_I2C5RST_Pos)    /*!< 0x00000040 */
22209 #define RCC_APB1RSTR2_I2C5RST               RCC_APB1RSTR2_I2C5RST_Msk
22210 #define RCC_APB1RSTR2_I2C6RST_Pos           (7U)
22211 #define RCC_APB1RSTR2_I2C6RST_Msk           (0x1UL << RCC_APB1RSTR2_I2C6RST_Pos)    /*!< 0x00000080 */
22212 #define RCC_APB1RSTR2_I2C6RST               RCC_APB1RSTR2_I2C6RST_Msk
22213 #define RCC_APB1RSTR2_FDCAN1RST_Pos         (9U)
22214 #define RCC_APB1RSTR2_FDCAN1RST_Msk         (0x1UL << RCC_APB1RSTR2_FDCAN1RST_Pos)  /*!< 0x00000200 */
22215 #define RCC_APB1RSTR2_FDCAN1RST             RCC_APB1RSTR2_FDCAN1RST_Msk             /*!< FDCAN1 Reset */
22216 #define RCC_APB1RSTR2_UCPD1RST_Pos          (23U)
22217 #define RCC_APB1RSTR2_UCPD1RST_Msk          (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)   /*!< 0x00800000 */
22218 #define RCC_APB1RSTR2_UCPD1RST              RCC_APB1RSTR2_UCPD1RST_Msk              /*!< UCPD1 Reset */
22219 
22220 /********************  Bit definition for RCC_APB2RSTR register  **************/
22221 #define RCC_APB2RSTR_TIM1RST_Pos            (11U)
22222 #define RCC_APB2RSTR_TIM1RST_Msk            (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)     /*!< 0x00000800 */
22223 #define RCC_APB2RSTR_TIM1RST                RCC_APB2RSTR_TIM1RST_Msk                /*!< TIM1 Reset */
22224 #define RCC_APB2RSTR_SPI1RST_Pos            (12U)
22225 #define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)     /*!< 0x00001000 */
22226 #define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk                /*!< SPI1 Reset */
22227 #define RCC_APB2RSTR_TIM8RST_Pos            (13U)
22228 #define RCC_APB2RSTR_TIM8RST_Msk            (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)     /*!< 0x00002000 */
22229 #define RCC_APB2RSTR_TIM8RST                RCC_APB2RSTR_TIM8RST_Msk                /*!< TIM8 Reset */
22230 #define RCC_APB2RSTR_USART1RST_Pos          (14U)
22231 #define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos)   /*!< 0x00004000 */
22232 #define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk              /*!< USART1 Reset */
22233 #define RCC_APB2RSTR_TIM15RST_Pos           (16U)
22234 #define RCC_APB2RSTR_TIM15RST_Msk           (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)    /*!< 0x00010000 */
22235 #define RCC_APB2RSTR_TIM15RST               RCC_APB2RSTR_TIM15RST_Msk               /*!< TIM15 Reset */
22236 #define RCC_APB2RSTR_TIM16RST_Pos           (17U)
22237 #define RCC_APB2RSTR_TIM16RST_Msk           (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)    /*!< 0x00020000 */
22238 #define RCC_APB2RSTR_TIM16RST               RCC_APB2RSTR_TIM16RST_Msk               /*!< TIM16 Reset */
22239 #define RCC_APB2RSTR_TIM17RST_Pos           (18U)
22240 #define RCC_APB2RSTR_TIM17RST_Msk           (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)    /*!< 0x00040000 */
22241 #define RCC_APB2RSTR_TIM17RST               RCC_APB2RSTR_TIM17RST_Msk               /*!< TIM17 Reset */
22242 #define RCC_APB2RSTR_SAI1RST_Pos            (21U)
22243 #define RCC_APB2RSTR_SAI1RST_Msk            (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)     /*!< 0x00200000 */
22244 #define RCC_APB2RSTR_SAI1RST                RCC_APB2RSTR_SAI1RST_Msk                /*!< SAI1 Reset */
22245 #define RCC_APB2RSTR_SAI2RST_Pos            (22U)
22246 #define RCC_APB2RSTR_SAI2RST_Msk            (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)     /*!< 0x00400000 */
22247 #define RCC_APB2RSTR_SAI2RST                RCC_APB2RSTR_SAI2RST_Msk                /*!< SAI2 Reset */
22248 #define RCC_APB2RSTR_GFXTIMRST_Pos          (25U)
22249 #define RCC_APB2RSTR_GFXTIMRST_Msk          (0x1UL << RCC_APB2RSTR_GFXTIMRST_Pos)   /*!< 0x02000000 */
22250 #define RCC_APB2RSTR_GFXTIMRST              RCC_APB2RSTR_GFXTIMRST_Msk              /*!< GFXTIM Reset */
22251 #define RCC_APB2RSTR_LTDCRST_Pos            (26U)
22252 #define RCC_APB2RSTR_LTDCRST_Msk            (0x1UL << RCC_APB2RSTR_LTDCRST_Pos)     /*!< 0x04000000 */
22253 #define RCC_APB2RSTR_LTDCRST                RCC_APB2RSTR_LTDCRST_Msk
22254 #define RCC_APB2RSTR_DSIHOSTRST_Pos         (27U)
22255 #define RCC_APB2RSTR_DSIHOSTRST_Msk         (0x1UL << RCC_APB2RSTR_DSIHOSTRST_Pos)  /*!< 0x08000000 */
22256 #define RCC_APB2RSTR_DSIHOSTRST             RCC_APB2RSTR_DSIHOSTRST_Msk
22257 
22258 /********************  Bit definition for RCC_APB3RSTR register  **************/
22259 #define RCC_APB3RSTR_SYSCFGRST_Pos          (1U)
22260 #define RCC_APB3RSTR_SYSCFGRST_Msk          (0x1UL << RCC_APB3RSTR_SYSCFGRST_Pos)   /*!< 0x00000002 */
22261 #define RCC_APB3RSTR_SYSCFGRST              RCC_APB3RSTR_SYSCFGRST_Msk              /*!< SYSCFG Reset */
22262 #define RCC_APB3RSTR_SPI3RST_Pos            (5U)
22263 #define RCC_APB3RSTR_SPI3RST_Msk            (0x1UL << RCC_APB3RSTR_SPI3RST_Pos)     /*!< 0x00000020 */
22264 #define RCC_APB3RSTR_SPI3RST                RCC_APB3RSTR_SPI3RST_Msk                /*!< SPI3 Reset */
22265 #define RCC_APB3RSTR_LPUART1RST_Pos         (6U)
22266 #define RCC_APB3RSTR_LPUART1RST_Msk         (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos)  /*!< 0x00000040 */
22267 #define RCC_APB3RSTR_LPUART1RST             RCC_APB3RSTR_LPUART1RST_Msk             /*!< LPUART1 Reset */
22268 #define RCC_APB3RSTR_I2C3RST_Pos            (7U)
22269 #define RCC_APB3RSTR_I2C3RST_Msk            (0x1UL << RCC_APB3RSTR_I2C3RST_Pos)     /*!< 0x000000080 */
22270 #define RCC_APB3RSTR_I2C3RST                RCC_APB3RSTR_I2C3RST_Msk                /*!< I2C3 Reset */
22271 #define RCC_APB3RSTR_LPTIM1RST_Pos          (11U)
22272 #define RCC_APB3RSTR_LPTIM1RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos)   /*!< 0x000000800 */
22273 #define RCC_APB3RSTR_LPTIM1RST              RCC_APB3RSTR_LPTIM1RST_Msk              /*!< LPTIM1 Reset */
22274 #define RCC_APB3RSTR_LPTIM3RST_Pos          (12U)
22275 #define RCC_APB3RSTR_LPTIM3RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM3RST_Pos)   /*!< 0x000001000 */
22276 #define RCC_APB3RSTR_LPTIM3RST              RCC_APB3RSTR_LPTIM3RST_Msk              /*!< LPTIM3 Reset */
22277 #define RCC_APB3RSTR_LPTIM4RST_Pos          (13U)
22278 #define RCC_APB3RSTR_LPTIM4RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM4RST_Pos)   /*!< 0x0000002000 */
22279 #define RCC_APB3RSTR_LPTIM4RST              RCC_APB3RSTR_LPTIM4RST_Msk              /*!< LPTIM4 Reset */
22280 #define RCC_APB3RSTR_OPAMPRST_Pos           (14U)
22281 #define RCC_APB3RSTR_OPAMPRST_Msk           (0x1UL << RCC_APB3RSTR_OPAMPRST_Pos)    /*!< 0x000004000 */
22282 #define RCC_APB3RSTR_OPAMPRST               RCC_APB3RSTR_OPAMPRST_Msk               /*!< OPAMP Reset */
22283 #define RCC_APB3RSTR_COMPRST_Pos            (15U)
22284 #define RCC_APB3RSTR_COMPRST_Msk            (0x1UL << RCC_APB3RSTR_COMPRST_Pos)     /*!< 0x000008000 */
22285 #define RCC_APB3RSTR_COMPRST                RCC_APB3RSTR_COMPRST_Msk                /*!< COMP Reset */
22286 #define RCC_APB3RSTR_VREFRST_Pos            (20U)
22287 #define RCC_APB3RSTR_VREFRST_Msk            (0x1UL << RCC_APB3RSTR_VREFRST_Pos)     /*!< 0x000100000 */
22288 #define RCC_APB3RSTR_VREFRST                RCC_APB3RSTR_VREFRST_Msk                /*!< VREFBUF Reset */
22289 
22290 /********************  Bit definition for RCC_AHB1ENR register  **************/
22291 #define RCC_AHB1ENR_GPDMA1EN_Pos            (0U)
22292 #define RCC_AHB1ENR_GPDMA1EN_Msk            (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos)     /*!< 0x00000001 */
22293 #define RCC_AHB1ENR_GPDMA1EN                RCC_AHB1ENR_GPDMA1EN_Msk                /*!< GPDMA1 Clock Enable */
22294 #define RCC_AHB1ENR_CORDICEN_Pos            (1U)
22295 #define RCC_AHB1ENR_CORDICEN_Msk            (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)     /*!< 0x00000001 */
22296 #define RCC_AHB1ENR_CORDICEN                RCC_AHB1ENR_CORDICEN_Msk                /*!< CORDIC Clock Enable */
22297 #define RCC_AHB1ENR_FMACEN_Pos              (2U)
22298 #define RCC_AHB1ENR_FMACEN_Msk              (0x1UL << RCC_AHB1ENR_FMACEN_Pos)       /*!< 0x00000001 */
22299 #define RCC_AHB1ENR_FMACEN                  RCC_AHB1ENR_FMACEN_Msk                  /*!< FMAC Clock Enable */
22300 #define RCC_AHB1ENR_MDF1EN_Pos              (3U)
22301 #define RCC_AHB1ENR_MDF1EN_Msk              (0x1UL << RCC_AHB1ENR_MDF1EN_Pos)       /*!< 0x00000008 */
22302 #define RCC_AHB1ENR_MDF1EN                  RCC_AHB1ENR_MDF1EN_Msk                  /*!< MDF1 Clock Enable */
22303 #define RCC_AHB1ENR_FLASHEN_Pos             (8U)
22304 #define RCC_AHB1ENR_FLASHEN_Msk             (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)      /*!< 0x00000100 */
22305 #define RCC_AHB1ENR_FLASHEN                 RCC_AHB1ENR_FLASHEN_Msk                 /*!< FLASH Clock Enable */
22306 #define RCC_AHB1ENR_CRCEN_Pos               (12U)
22307 #define RCC_AHB1ENR_CRCEN_Msk               (0x1UL << RCC_AHB1ENR_CRCEN_Pos)        /*!< 0x00001000 */
22308 #define RCC_AHB1ENR_CRCEN                   RCC_AHB1ENR_CRCEN_Msk                   /*!< CRC Clock Enable */
22309 #define RCC_AHB1ENR_JPEGEN_Pos              (15U)
22310 #define RCC_AHB1ENR_JPEGEN_Msk              (0x1UL << RCC_AHB1ENR_JPEGEN_Pos)       /*!< 0x00008000 */
22311 #define RCC_AHB1ENR_JPEGEN                  RCC_AHB1ENR_JPEGEN_Msk                  /*!< JPEG Clock Enable */
22312 #define RCC_AHB1ENR_TSCEN_Pos               (16U)
22313 #define RCC_AHB1ENR_TSCEN_Msk               (0x1UL << RCC_AHB1ENR_TSCEN_Pos)        /*!< 0x00010000 */
22314 #define RCC_AHB1ENR_TSCEN                   RCC_AHB1ENR_TSCEN_Msk                   /*!< Touch Sensing Controller Clock Enable */
22315 #define RCC_AHB1ENR_RAMCFGEN_Pos            (17U)
22316 #define RCC_AHB1ENR_RAMCFGEN_Msk            (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos)     /*!< 0x00020000 */
22317 #define RCC_AHB1ENR_RAMCFGEN                RCC_AHB1ENR_RAMCFGEN_Msk                /*!< RAMCFG Clock Enable */
22318 #define RCC_AHB1ENR_DMA2DEN_Pos             (18U)
22319 #define RCC_AHB1ENR_DMA2DEN_Msk             (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)      /*!< 0x00040000 */
22320 #define RCC_AHB1ENR_DMA2DEN                 RCC_AHB1ENR_DMA2DEN_Msk                 /*!< DMA2D Clock Enable */
22321 #define RCC_AHB1ENR_GFXMMUEN_Pos            (19U)
22322 #define RCC_AHB1ENR_GFXMMUEN_Msk            (0x1UL << RCC_AHB1ENR_GFXMMUEN_Pos)     /*!< 0x00080000 */
22323 #define RCC_AHB1ENR_GFXMMUEN                RCC_AHB1ENR_GFXMMUEN_Msk                /*!< GFXMMU Clock Enable */
22324 #define RCC_AHB1ENR_GPU2DEN_Pos             (20U)
22325 #define RCC_AHB1ENR_GPU2DEN_Msk             (0x1UL << RCC_AHB1ENR_GPU2DEN_Pos)      /*!< 0x00100000 */
22326 #define RCC_AHB1ENR_GPU2DEN                 RCC_AHB1ENR_GPU2DEN_Msk                 /*!< GPU2D Clock Enable */
22327 #define RCC_AHB1ENR_DCACHE2EN_Pos           (21U)
22328 #define RCC_AHB1ENR_DCACHE2EN_Msk           (0x1UL << RCC_AHB1ENR_DCACHE2EN_Pos)   /*!< 0x00200000 */
22329 #define RCC_AHB1ENR_DCACHE2EN               RCC_AHB1ENR_DCACHE2EN_Msk              /*!< DCACHE2 Clock Enable */
22330 #define RCC_AHB1ENR_GTZC1EN_Pos             (24U)
22331 #define RCC_AHB1ENR_GTZC1EN_Msk             (0x1UL << RCC_AHB1ENR_GTZC1EN_Pos)      /*!< 0x01000000 */
22332 #define RCC_AHB1ENR_GTZC1EN                 RCC_AHB1ENR_GTZC1EN_Msk                 /*!< GTZC1 Clock Enable */
22333 #define RCC_AHB1ENR_BKPSRAMEN_Pos           (28U)
22334 #define RCC_AHB1ENR_BKPSRAMEN_Msk           (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)    /*!< 0x10000000 */
22335 #define RCC_AHB1ENR_BKPSRAMEN               RCC_AHB1ENR_BKPSRAMEN_Msk               /*!< BKPSRAM Clock Enable */
22336 #define RCC_AHB1ENR_DCACHE1EN_Pos           (30U)
22337 #define RCC_AHB1ENR_DCACHE1EN_Msk           (0x1UL << RCC_AHB1ENR_DCACHE1EN_Pos)    /*!< 0x40000000 */
22338 #define RCC_AHB1ENR_DCACHE1EN               RCC_AHB1ENR_DCACHE1EN_Msk               /*!< DCACHE1 Clock Enable */
22339 #define RCC_AHB1ENR_SRAM1EN_Pos             (31U)
22340 #define RCC_AHB1ENR_SRAM1EN_Msk             (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos)      /*!< 0x80000000 */
22341 #define RCC_AHB1ENR_SRAM1EN                 RCC_AHB1ENR_SRAM1EN_Msk                 /*!< SRAM1 Clock Enable */
22342 
22343 /********************  Bit definition for RCC_AHB2ENR1 register  **************/
22344 #define RCC_AHB2ENR1_GPIOAEN_Pos            (0U)
22345 #define RCC_AHB2ENR1_GPIOAEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOAEN_Pos)     /*!< 0x00000001 */
22346 #define RCC_AHB2ENR1_GPIOAEN                RCC_AHB2ENR1_GPIOAEN_Msk                /*!< IO port A Clock Enable */
22347 #define RCC_AHB2ENR1_GPIOBEN_Pos            (1U)
22348 #define RCC_AHB2ENR1_GPIOBEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOBEN_Pos)     /*!< 0x00000002 */
22349 #define RCC_AHB2ENR1_GPIOBEN                RCC_AHB2ENR1_GPIOBEN_Msk                /*!< IO port B Clock Enable */
22350 #define RCC_AHB2ENR1_GPIOCEN_Pos            (2U)
22351 #define RCC_AHB2ENR1_GPIOCEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOCEN_Pos)     /*!< 0x00000004 */
22352 #define RCC_AHB2ENR1_GPIOCEN                RCC_AHB2ENR1_GPIOCEN_Msk                /*!< IO port C Clock Enable */
22353 #define RCC_AHB2ENR1_GPIODEN_Pos            (3U)
22354 #define RCC_AHB2ENR1_GPIODEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIODEN_Pos)     /*!< 0x00000008 */
22355 #define RCC_AHB2ENR1_GPIODEN                RCC_AHB2ENR1_GPIODEN_Msk                /*!< IO port D Clock Enable */
22356 #define RCC_AHB2ENR1_GPIOEEN_Pos            (4U)
22357 #define RCC_AHB2ENR1_GPIOEEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOEEN_Pos)     /*!< 0x00000010 */
22358 #define RCC_AHB2ENR1_GPIOEEN                RCC_AHB2ENR1_GPIOEEN_Msk                /*!< IO port E Clock Enable */
22359 #define RCC_AHB2ENR1_GPIOFEN_Pos            (5U)
22360 #define RCC_AHB2ENR1_GPIOFEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOFEN_Pos)     /*!< 0x00000020 */
22361 #define RCC_AHB2ENR1_GPIOFEN                RCC_AHB2ENR1_GPIOFEN_Msk                /*!< IO port F Clock Enable */
22362 #define RCC_AHB2ENR1_GPIOGEN_Pos            (6U)
22363 #define RCC_AHB2ENR1_GPIOGEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOGEN_Pos)     /*!< 0x00000040 */
22364 #define RCC_AHB2ENR1_GPIOGEN                RCC_AHB2ENR1_GPIOGEN_Msk                /*!< IO port G Clock Enable */
22365 #define RCC_AHB2ENR1_GPIOHEN_Pos            (7U)
22366 #define RCC_AHB2ENR1_GPIOHEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOHEN_Pos)     /*!< 0x00000080 */
22367 #define RCC_AHB2ENR1_GPIOHEN                RCC_AHB2ENR1_GPIOHEN_Msk                /*!< IO port H Clock Enable */
22368 #define RCC_AHB2ENR1_GPIOIEN_Pos            (8U)
22369 #define RCC_AHB2ENR1_GPIOIEN_Msk            (0x1UL << RCC_AHB2ENR1_GPIOIEN_Pos)     /*!< 0x00000100 */
22370 #define RCC_AHB2ENR1_GPIOIEN                RCC_AHB2ENR1_GPIOIEN_Msk                /*!< IO port I Clock Enable */
22371 #define RCC_AHB2ENR1_GPIOJEN_Pos             (9U)
22372 #define RCC_AHB2ENR1_GPIOJEN_Msk             (0x1UL << RCC_AHB2ENR1_GPIOJEN_Pos)    /*!< 0x00000200 */
22373 #define RCC_AHB2ENR1_GPIOJEN                 RCC_AHB2ENR1_GPIOJEN_Msk               /*!< GPIOJ Clock Enable */
22374 #define RCC_AHB2ENR1_ADC12EN_Pos             (10U)
22375 #define RCC_AHB2ENR1_ADC12EN_Msk             (0x1UL << RCC_AHB2ENR1_ADC12EN_Pos)    /*!< 0x00000400 */
22376 #define RCC_AHB2ENR1_ADC12EN                 RCC_AHB2ENR1_ADC12EN_Msk               /*!< ADC1 Clock Enable */
22377 #define RCC_AHB2ENR1_DCMI_PSSIEN_Pos        (12U)
22378 #define RCC_AHB2ENR1_DCMI_PSSIEN_Msk        (0x1UL << RCC_AHB2ENR1_DCMI_PSSIEN_Pos) /*!< 0x00001000 */
22379 #define RCC_AHB2ENR1_DCMI_PSSIEN            RCC_AHB2ENR1_DCMI_PSSIEN_Msk            /*!< DCMI and PSSI Clock Enable */
22380 #define RCC_AHB2ENR1_OTGEN_Pos              (14U)
22381 #define RCC_AHB2ENR1_OTGEN_Msk              (0x1UL << RCC_AHB2ENR1_OTGEN_Pos)       /*!< 0x00004000 */
22382 #define RCC_AHB2ENR1_OTGEN                  RCC_AHB2ENR1_OTGEN_Msk                  /*!< OTG Clock Enable */
22383 #define RCC_AHB2ENR1_USBPHYCEN_Pos           (15U)
22384 #define RCC_AHB2ENR1_USBPHYCEN_Msk           (0x1UL << RCC_AHB2ENR1_USBPHYCEN_Pos)  /*!< 0x00008000 */
22385 #define RCC_AHB2ENR1_USBPHYCEN               RCC_AHB2ENR1_USBPHYCEN_Msk
22386 #define RCC_AHB2ENR1_AESEN_Pos              (16U)
22387 #define RCC_AHB2ENR1_AESEN_Msk              (0x1UL << RCC_AHB2ENR1_AESEN_Pos)       /*!< 0x00010000 */
22388 #define RCC_AHB2ENR1_AESEN                  RCC_AHB2ENR1_AESEN_Msk                  /*!< AES Clock Enable */
22389 #define RCC_AHB2ENR1_HASHEN_Pos             (17U)
22390 #define RCC_AHB2ENR1_HASHEN_Msk             (0x1UL << RCC_AHB2ENR1_HASHEN_Pos)      /*!< 0x00020000 */
22391 #define RCC_AHB2ENR1_HASHEN                 RCC_AHB2ENR1_HASHEN_Msk                 /*!< HASH Clock Enable */
22392 #define RCC_AHB2ENR1_RNGEN_Pos              (18U)
22393 #define RCC_AHB2ENR1_RNGEN_Msk              (0x1UL << RCC_AHB2ENR1_RNGEN_Pos)       /*!< 0x00040000 */
22394 #define RCC_AHB2ENR1_RNGEN                  RCC_AHB2ENR1_RNGEN_Msk                  /*!< RNG Clock Enable */
22395 #define RCC_AHB2ENR1_PKAEN_Pos              (19U)
22396 #define RCC_AHB2ENR1_PKAEN_Msk              (0x1UL << RCC_AHB2ENR1_PKAEN_Pos)       /*!< 0x00080000 */
22397 #define RCC_AHB2ENR1_PKAEN                  RCC_AHB2ENR1_PKAEN_Msk                  /*!< PKA Clock Enable */
22398 #define RCC_AHB2ENR1_SAESEN_Pos             (20U)
22399 #define RCC_AHB2ENR1_SAESEN_Msk             (0x1UL << RCC_AHB2ENR1_SAESEN_Pos)      /*!< 0x00100000 */
22400 #define RCC_AHB2ENR1_SAESEN                 RCC_AHB2ENR1_SAESEN_Msk                 /*!< SAES Clock Enable */
22401 #define RCC_AHB2ENR1_OCTOSPIMEN_Pos         (21U)
22402 #define RCC_AHB2ENR1_OCTOSPIMEN_Msk         (0x1UL << RCC_AHB2ENR1_OCTOSPIMEN_Pos)  /*!< 0x00200000 */
22403 #define RCC_AHB2ENR1_OCTOSPIMEN             RCC_AHB2ENR1_OCTOSPIMEN_Msk             /*!< OCTOSPIM Clock Enable */
22404 #define RCC_AHB2ENR1_OTFDEC1EN_Pos          (23U)
22405 #define RCC_AHB2ENR1_OTFDEC1EN_Msk          (0x1UL << RCC_AHB2ENR1_OTFDEC1EN_Pos)   /*!< 0x00800000 */
22406 #define RCC_AHB2ENR1_OTFDEC1EN              RCC_AHB2ENR1_OTFDEC1EN_Msk              /*!< OTFDEC1 Clock Enable */
22407 #define RCC_AHB2ENR1_OTFDEC2EN_Pos          (24U)
22408 #define RCC_AHB2ENR1_OTFDEC2EN_Msk          (0x1UL << RCC_AHB2ENR1_OTFDEC2EN_Pos)   /*!< 0x01000000 */
22409 #define RCC_AHB2ENR1_OTFDEC2EN              RCC_AHB2ENR1_OTFDEC2EN_Msk              /*!< OTFDEC2 Clock Enable */
22410 #define RCC_AHB2ENR1_SDMMC1EN_Pos           (27U)
22411 #define RCC_AHB2ENR1_SDMMC1EN_Msk           (0x1UL << RCC_AHB2ENR1_SDMMC1EN_Pos)    /*!< 0x08000000 */
22412 #define RCC_AHB2ENR1_SDMMC1EN               RCC_AHB2ENR1_SDMMC1EN_Msk               /*!< SDMMC1 Clock Enable */
22413 #define RCC_AHB2ENR1_SDMMC2EN_Pos           (28U)
22414 #define RCC_AHB2ENR1_SDMMC2EN_Msk           (0x1UL << RCC_AHB2ENR1_SDMMC2EN_Pos)    /*!< 0x10000000 */
22415 #define RCC_AHB2ENR1_SDMMC2EN               RCC_AHB2ENR1_SDMMC2EN_Msk               /*!< SDMMC2 Clock Enable */
22416 #define RCC_AHB2ENR1_SRAM2EN_Pos            (30U)
22417 #define RCC_AHB2ENR1_SRAM2EN_Msk            (0x1UL << RCC_AHB2ENR1_SRAM2EN_Pos)     /*!< 0x40000000 */
22418 #define RCC_AHB2ENR1_SRAM2EN                RCC_AHB2ENR1_SRAM2EN_Msk                /*!< SRAM2 Clock Enable */
22419 #define RCC_AHB2ENR1_SRAM3EN_Pos            (31U)
22420 #define RCC_AHB2ENR1_SRAM3EN_Msk            (0x1UL << RCC_AHB2ENR1_SRAM3EN_Pos)     /*!< 0x80000000 */
22421 #define RCC_AHB2ENR1_SRAM3EN                RCC_AHB2ENR1_SRAM3EN_Msk                /*!< SRAM3 Clock Enable */
22422 
22423 /********************  Bit definition for RCC_AHB2ENR2 register  **************/
22424 #define RCC_AHB2ENR2_FSMCEN_Pos             (0U)
22425 #define RCC_AHB2ENR2_FSMCEN_Msk             (0x1UL << RCC_AHB2ENR2_FSMCEN_Pos)      /*!< 0x00000001 */
22426 #define RCC_AHB2ENR2_FSMCEN                 RCC_AHB2ENR2_FSMCEN_Msk                 /*!< FSMC Clock Enable */
22427 #define RCC_AHB2ENR2_OCTOSPI1EN_Pos         (4U)
22428 #define RCC_AHB2ENR2_OCTOSPI1EN_Msk         (0x1UL << RCC_AHB2ENR2_OCTOSPI1EN_Pos)  /*!< 0x00000010 */
22429 #define RCC_AHB2ENR2_OCTOSPI1EN             RCC_AHB2ENR2_OCTOSPI1EN_Msk             /*!< OCTOSPI1 Clock Enable */
22430 #define RCC_AHB2ENR2_OCTOSPI2EN_Pos         (8U)
22431 #define RCC_AHB2ENR2_OCTOSPI2EN_Msk         (0x1UL << RCC_AHB2ENR2_OCTOSPI2EN_Pos)  /*!< 0x00000100 */
22432 #define RCC_AHB2ENR2_OCTOSPI2EN             RCC_AHB2ENR2_OCTOSPI2EN_Msk             /*!< OCTOSPI2 Clock Enable */
22433 #define RCC_AHB2ENR2_HSPI1EN_Pos            (12U)
22434 #define RCC_AHB2ENR2_HSPI1EN_Msk            (0x1UL << RCC_AHB2ENR2_HSPI1EN_Pos)     /*!< 0x00001000 */
22435 #define RCC_AHB2ENR2_HSPI1EN                RCC_AHB2ENR2_HSPI1EN_Msk                /*!< HSPI1 Clock Enable */
22436 #define RCC_AHB2ENR2_SRAM6EN_Pos            (30U)
22437 #define RCC_AHB2ENR2_SRAM6EN_Msk            (0x1UL << RCC_AHB2ENR2_SRAM6EN_Pos)     /*!< 0x40000000 */
22438 #define RCC_AHB2ENR2_SRAM6EN                RCC_AHB2ENR2_SRAM6EN_Msk                /*!< SRAM6 Clock Enable */
22439 #define RCC_AHB2ENR2_SRAM5EN_Pos            (31U)
22440 #define RCC_AHB2ENR2_SRAM5EN_Msk            (0x1UL << RCC_AHB2ENR2_SRAM5EN_Pos)     /*!< 0x80000000 */
22441 #define RCC_AHB2ENR2_SRAM5EN                RCC_AHB2ENR2_SRAM5EN_Msk                /*!< SRAM5 Clock Enable */
22442 
22443 /********************  Bit definition for RCC_AHB3ENR register  **************/
22444 #define RCC_AHB3ENR_LPGPIO1EN_Pos           (0U)
22445 #define RCC_AHB3ENR_LPGPIO1EN_Msk           (0x1UL << RCC_AHB3ENR_LPGPIO1EN_Pos)    /*!< 0x00000001 */
22446 #define RCC_AHB3ENR_LPGPIO1EN               RCC_AHB3ENR_LPGPIO1EN_Msk               /*!< LPGPIO1 Enable */
22447 #define RCC_AHB3ENR_PWREN_Pos               (2U)
22448 #define RCC_AHB3ENR_PWREN_Msk               (0x1UL << RCC_AHB3ENR_PWREN_Pos)        /*!< 0x00000004 */
22449 #define RCC_AHB3ENR_PWREN                   RCC_AHB3ENR_PWREN_Msk                   /*!< PWR Clock Enable */
22450 #define RCC_AHB3ENR_ADC4EN_Pos              (5U)
22451 #define RCC_AHB3ENR_ADC4EN_Msk              (0x1UL << RCC_AHB3ENR_ADC4EN_Pos)       /*!< 0x00000040 */
22452 #define RCC_AHB3ENR_ADC4EN                  RCC_AHB3ENR_ADC4EN_Msk                  /*!< ADC4 Clock Enable */
22453 #define RCC_AHB3ENR_DAC1EN_Pos              (6U)
22454 #define RCC_AHB3ENR_DAC1EN_Msk              (0x1UL << RCC_AHB3ENR_DAC1EN_Pos)       /*!< 0x00000040 */
22455 #define RCC_AHB3ENR_DAC1EN                  RCC_AHB3ENR_DAC1EN_Msk                  /*!< DAC1 Clock Enable */
22456 #define RCC_AHB3ENR_LPDMA1EN_Pos            (9U)
22457 #define RCC_AHB3ENR_LPDMA1EN_Msk            (0x1UL << RCC_AHB3ENR_LPDMA1EN_Pos)     /*!< 0x000000080 */
22458 #define RCC_AHB3ENR_LPDMA1EN                RCC_AHB3ENR_LPDMA1EN_Msk                /*!< LPDMA1 Clock Enable */
22459 #define RCC_AHB3ENR_ADF1EN_Pos              (10U)
22460 #define RCC_AHB3ENR_ADF1EN_Msk              (0x1UL << RCC_AHB3ENR_ADF1EN_Pos)       /*!< 0x000000400 */
22461 #define RCC_AHB3ENR_ADF1EN                  RCC_AHB3ENR_ADF1EN_Msk                  /*!< ADF1 Clock Enable */
22462 #define RCC_AHB3ENR_GTZC2EN_Pos             (12U)
22463 #define RCC_AHB3ENR_GTZC2EN_Msk             (0x1UL << RCC_AHB3ENR_GTZC2EN_Pos)      /*!< 0x000001000 */
22464 #define RCC_AHB3ENR_GTZC2EN                 RCC_AHB3ENR_GTZC2EN_Msk                 /*!< GTZC2 Clock Enable */
22465 #define RCC_AHB3ENR_SRAM4EN_Pos             (31U)
22466 #define RCC_AHB3ENR_SRAM4EN_Msk             (0x1UL << RCC_AHB3ENR_SRAM4EN_Pos)      /*!< 0x800000000 */
22467 #define RCC_AHB3ENR_SRAM4EN                 RCC_AHB3ENR_SRAM4EN_Msk                 /*!< SRAM4 Clock Enable */
22468 
22469 /********************  Bit definition for RCC_APB1ENR1 register  **************/
22470 #define RCC_APB1ENR1_TIM2EN_Pos             (0U)
22471 #define RCC_APB1ENR1_TIM2EN_Msk             (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)      /*!< 0x00000001 */
22472 #define RCC_APB1ENR1_TIM2EN                 RCC_APB1ENR1_TIM2EN_Msk                 /*!< TIM2 Clock Enable */
22473 #define RCC_APB1ENR1_TIM3EN_Pos             (1U)
22474 #define RCC_APB1ENR1_TIM3EN_Msk             (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)      /*!< 0x00000002 */
22475 #define RCC_APB1ENR1_TIM3EN                 RCC_APB1ENR1_TIM3EN_Msk                 /*!< TIM3 Clock Enable */
22476 #define RCC_APB1ENR1_TIM4EN_Pos             (2U)
22477 #define RCC_APB1ENR1_TIM4EN_Msk             (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)      /*!< 0x00000004 */
22478 #define RCC_APB1ENR1_TIM4EN                 RCC_APB1ENR1_TIM4EN_Msk                 /*!< TIM4 Clock Enable */
22479 #define RCC_APB1ENR1_TIM5EN_Pos             (3U)
22480 #define RCC_APB1ENR1_TIM5EN_Msk             (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)      /*!< 0x00000008 */
22481 #define RCC_APB1ENR1_TIM5EN                 RCC_APB1ENR1_TIM5EN_Msk                 /*!< TIM5 Clock Enable */
22482 #define RCC_APB1ENR1_TIM6EN_Pos             (4U)
22483 #define RCC_APB1ENR1_TIM6EN_Msk             (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)      /*!< 0x00000010 */
22484 #define RCC_APB1ENR1_TIM6EN                 RCC_APB1ENR1_TIM6EN_Msk                 /*!< TIM6 Clock Enable */
22485 #define RCC_APB1ENR1_TIM7EN_Pos             (5U)
22486 #define RCC_APB1ENR1_TIM7EN_Msk             (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)      /*!< 0x00000020 */
22487 #define RCC_APB1ENR1_TIM7EN                 RCC_APB1ENR1_TIM7EN_Msk                 /*!< TIM7 Clock Enable */
22488 #define RCC_APB1ENR1_WWDGEN_Pos             (11U)
22489 #define RCC_APB1ENR1_WWDGEN_Msk             (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)      /*!< 0x00000800 */
22490 #define RCC_APB1ENR1_WWDGEN                 RCC_APB1ENR1_WWDGEN_Msk                 /*!< WWDG Clock Enable */
22491 #define RCC_APB1ENR1_SPI2EN_Pos             (14U)
22492 #define RCC_APB1ENR1_SPI2EN_Msk             (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)      /*!< 0x00004000 */
22493 #define RCC_APB1ENR1_SPI2EN                 RCC_APB1ENR1_SPI2EN_Msk                 /*!< SPI2 Clock Enable */
22494 #define RCC_APB1ENR1_USART2EN_Pos           (17U)
22495 #define RCC_APB1ENR1_USART2EN_Msk           (0x1UL << RCC_APB1ENR1_USART2EN_Pos)    /*!< 0x00020000 */
22496 #define RCC_APB1ENR1_USART2EN               RCC_APB1ENR1_USART2EN_Msk               /*!< USART2 Clock Enable */
22497 #define RCC_APB1ENR1_USART3EN_Pos           (18U)
22498 #define RCC_APB1ENR1_USART3EN_Msk           (0x1UL << RCC_APB1ENR1_USART3EN_Pos)    /*!< 0x00040000 */
22499 #define RCC_APB1ENR1_USART3EN               RCC_APB1ENR1_USART3EN_Msk               /*!< USART3 Clock Enable */
22500 #define RCC_APB1ENR1_UART4EN_Pos            (19U)
22501 #define RCC_APB1ENR1_UART4EN_Msk            (0x1UL << RCC_APB1ENR1_UART4EN_Pos)     /*!< 0x00080000 */
22502 #define RCC_APB1ENR1_UART4EN                RCC_APB1ENR1_UART4EN_Msk                /*!< UART4 Clock Enable */
22503 #define RCC_APB1ENR1_UART5EN_Pos            (20U)
22504 #define RCC_APB1ENR1_UART5EN_Msk            (0x1UL << RCC_APB1ENR1_UART5EN_Pos)     /*!< 0x00100000 */
22505 #define RCC_APB1ENR1_UART5EN                RCC_APB1ENR1_UART5EN_Msk                /*!< UART5 Clock Enable */
22506 #define RCC_APB1ENR1_I2C1EN_Pos             (21U)
22507 #define RCC_APB1ENR1_I2C1EN_Msk             (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)      /*!< 0x00200000 */
22508 #define RCC_APB1ENR1_I2C1EN                 RCC_APB1ENR1_I2C1EN_Msk                 /*!< I2C1 Clock Enable */
22509 #define RCC_APB1ENR1_I2C2EN_Pos             (22U)
22510 #define RCC_APB1ENR1_I2C2EN_Msk             (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)      /*!< 0x00400000 */
22511 #define RCC_APB1ENR1_I2C2EN                 RCC_APB1ENR1_I2C2EN_Msk                 /*!< I2C2 Clock Enable */
22512 #define RCC_APB1ENR1_CRSEN_Pos              (24U)
22513 #define RCC_APB1ENR1_CRSEN_Msk              (0x1UL << RCC_APB1ENR1_CRSEN_Pos)       /*!< 0x01000000 */
22514 #define RCC_APB1ENR1_CRSEN                  RCC_APB1ENR1_CRSEN_Msk                  /*!< CRS Clock Enable */
22515 #define RCC_APB1ENR1_USART6EN_Pos           (25U)
22516 #define RCC_APB1ENR1_USART6EN_Msk           (0x1UL << RCC_APB1ENR1_USART6EN_Pos)    /*!< 0x02000000 */
22517 #define RCC_APB1ENR1_USART6EN               RCC_APB1ENR1_USART6EN_Msk               /*!< USART6 Clock Enable */
22518 
22519 /********************  Bit definition for RCC_APB1ENR2 register  **************/
22520 #define RCC_APB1ENR2_I2C4EN_Pos             (1U)
22521 #define RCC_APB1ENR2_I2C4EN_Msk             (0x1UL << RCC_APB1ENR2_I2C4EN_Pos)      /*!< 0x00000002 */
22522 #define RCC_APB1ENR2_I2C4EN                 RCC_APB1ENR2_I2C4EN_Msk                 /*!< I2C4 Clock Enable */
22523 #define RCC_APB1ENR2_LPTIM2EN_Pos           (5U)
22524 #define RCC_APB1ENR2_LPTIM2EN_Msk           (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)    /*!< 0x00000020 */
22525 #define RCC_APB1ENR2_LPTIM2EN               RCC_APB1ENR2_LPTIM2EN_Msk               /*!< LPTIM2 Clock Enable */
22526 #define RCC_APB1ENR2_I2C5EN_Pos             (6U)
22527 #define RCC_APB1ENR2_I2C5EN_Msk             (0x1UL << RCC_APB1ENR2_I2C5EN_Pos)      /*!< 0x00000040 */
22528 #define RCC_APB1ENR2_I2C5EN                 RCC_APB1ENR2_I2C5EN_Msk                 /*!< I2C5 Clock Enable */
22529 #define RCC_APB1ENR2_I2C6EN_Pos             (7U)
22530 #define RCC_APB1ENR2_I2C6EN_Msk             (0x1UL << RCC_APB1ENR2_I2C6EN_Pos)      /*!< 0x00000080 */
22531 #define RCC_APB1ENR2_I2C6EN                 RCC_APB1ENR2_I2C6EN_Msk                 /*!< I2C6 Clock Enable */
22532 #define RCC_APB1ENR2_FDCAN1EN_Pos           (9U)
22533 #define RCC_APB1ENR2_FDCAN1EN_Msk           (0x1UL << RCC_APB1ENR2_FDCAN1EN_Pos)    /*!< 0x00000200 */
22534 #define RCC_APB1ENR2_FDCAN1EN               RCC_APB1ENR2_FDCAN1EN_Msk               /*!< FDCAN1 Clock Enable */
22535 #define RCC_APB1ENR2_UCPD1EN_Pos            (23U)
22536 #define RCC_APB1ENR2_UCPD1EN_Msk            (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)     /*!< 0x00800000 */
22537 #define RCC_APB1ENR2_UCPD1EN                RCC_APB1ENR2_UCPD1EN_Msk                /*!< UCPD1 Clock Enable */
22538 
22539 /********************  Bit definition for RCC_APB2ENR register  **************/
22540 #define RCC_APB2ENR_TIM1EN_Pos              (11U)
22541 #define RCC_APB2ENR_TIM1EN_Msk              (0x1UL << RCC_APB2ENR_TIM1EN_Pos)       /*!< 0x00000800 */
22542 #define RCC_APB2ENR_TIM1EN                  RCC_APB2ENR_TIM1EN_Msk                  /*!< TIM1 Clock Enable */
22543 #define RCC_APB2ENR_SPI1EN_Pos              (12U)
22544 #define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)       /*!< 0x00001000 */
22545 #define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk                  /*!< SPI1 Clock Enable */
22546 #define RCC_APB2ENR_TIM8EN_Pos              (13U)
22547 #define RCC_APB2ENR_TIM8EN_Msk              (0x1UL << RCC_APB2ENR_TIM8EN_Pos)       /*!< 0x00002000 */
22548 #define RCC_APB2ENR_TIM8EN                  RCC_APB2ENR_TIM8EN_Msk                  /*!< TIM8 Clock Enable */
22549 #define RCC_APB2ENR_USART1EN_Pos            (14U)
22550 #define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos)     /*!< 0x00004000 */
22551 #define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk                /*!< USART1 Clock Enable */
22552 #define RCC_APB2ENR_TIM15EN_Pos             (16U)
22553 #define RCC_APB2ENR_TIM15EN_Msk             (0x1UL << RCC_APB2ENR_TIM15EN_Pos)      /*!< 0x00010000 */
22554 #define RCC_APB2ENR_TIM15EN                 RCC_APB2ENR_TIM15EN_Msk                 /*!< TIM15 Clock Enable */
22555 #define RCC_APB2ENR_TIM16EN_Pos             (17U)
22556 #define RCC_APB2ENR_TIM16EN_Msk             (0x1UL << RCC_APB2ENR_TIM16EN_Pos)      /*!< 0x00020000 */
22557 #define RCC_APB2ENR_TIM16EN                 RCC_APB2ENR_TIM16EN_Msk                 /*!< TIM16 Clock Enable */
22558 #define RCC_APB2ENR_TIM17EN_Pos             (18U)
22559 #define RCC_APB2ENR_TIM17EN_Msk             (0x1UL << RCC_APB2ENR_TIM17EN_Pos)      /*!< 0x00040000 */
22560 #define RCC_APB2ENR_TIM17EN                 RCC_APB2ENR_TIM17EN_Msk                 /*!< TIM17 Clock Enable */
22561 #define RCC_APB2ENR_SAI1EN_Pos              (21U)
22562 #define RCC_APB2ENR_SAI1EN_Msk              (0x1UL << RCC_APB2ENR_SAI1EN_Pos)       /*!< 0x00200000 */
22563 #define RCC_APB2ENR_SAI1EN                  RCC_APB2ENR_SAI1EN_Msk                  /*!< SAI1 Clock Enable */
22564 #define RCC_APB2ENR_SAI2EN_Pos              (22U)
22565 #define RCC_APB2ENR_SAI2EN_Msk              (0x1UL << RCC_APB2ENR_SAI2EN_Pos)       /*!< 0x00400000 */
22566 #define RCC_APB2ENR_SAI2EN                  RCC_APB2ENR_SAI2EN_Msk                  /*!< SAI2 Clock Enable */
22567 #define RCC_APB2ENR_GFXTIMEN_Pos            (25U)
22568 #define RCC_APB2ENR_GFXTIMEN_Msk            (0x1UL << RCC_APB2ENR_GFXTIMEN_Pos)     /*!< 0x02000000 */
22569 #define RCC_APB2ENR_GFXTIMEN                RCC_APB2ENR_GFXTIMEN_Msk                /*!< GFXTIM Clock Enable */
22570 #define RCC_APB2ENR_LTDCEN_Pos              (26U)
22571 #define RCC_APB2ENR_LTDCEN_Msk              (0x1UL << RCC_APB2ENR_LTDCEN_Pos)       /*!< 0x04000000 */
22572 #define RCC_APB2ENR_LTDCEN                  RCC_APB2ENR_LTDCEN_Msk                  /*!< LTDC Clock Enable */
22573 #define RCC_APB2ENR_DSIHOSTEN_Pos           (27U)
22574 #define RCC_APB2ENR_DSIHOSTEN_Msk           (0x1UL << RCC_APB2ENR_DSIHOSTEN_Pos)    /*!< 0x08000000 */
22575 #define RCC_APB2ENR_DSIHOSTEN               RCC_APB2ENR_DSIHOSTEN_Msk               /*!< DSI Clock Enable */
22576 
22577 /********************  Bit definition for RCC_APB3ENR register  **************/
22578 #define RCC_APB3ENR_SYSCFGEN_Pos            (1U)
22579 #define RCC_APB3ENR_SYSCFGEN_Msk            (0x1UL << RCC_APB3ENR_SYSCFGEN_Pos)      /*!< 0x00000002 */
22580 #define RCC_APB3ENR_SYSCFGEN                RCC_APB3ENR_SYSCFGEN_Msk                 /*!< SYSCFG Clock Enable */
22581 #define RCC_APB3ENR_SPI3EN_Pos              (5U)
22582 #define RCC_APB3ENR_SPI3EN_Msk              (0x1UL << RCC_APB3ENR_SPI3EN_Pos)        /*!< 0x00000010 */
22583 #define RCC_APB3ENR_SPI3EN                  RCC_APB3ENR_SPI3EN_Msk                   /*!< SPI3 Clock Enable */
22584 #define RCC_APB3ENR_LPUART1EN_Pos           (6U)
22585 #define RCC_APB3ENR_LPUART1EN_Msk           (0x1UL << RCC_APB3ENR_LPUART1EN_Pos)     /*!< 0x00000040 */
22586 #define RCC_APB3ENR_LPUART1EN               RCC_APB3ENR_LPUART1EN_Msk                /*!< LPUART1 Clock Enable */
22587 #define RCC_APB3ENR_I2C3EN_Pos              (7U)
22588 #define RCC_APB3ENR_I2C3EN_Msk              (0x1UL << RCC_APB3ENR_I2C3EN_Pos)        /*!< 0x000000080 */
22589 #define RCC_APB3ENR_I2C3EN                  RCC_APB3ENR_I2C3EN_Msk                   /*!< I2C3 Clock Enable */
22590 #define RCC_APB3ENR_LPTIM1EN_Pos            (11U)
22591 #define RCC_APB3ENR_LPTIM1EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos)      /*!< 0x000000800 */
22592 #define RCC_APB3ENR_LPTIM1EN                RCC_APB3ENR_LPTIM1EN_Msk                 /*!< LPTIM1 Clock Enable */
22593 #define RCC_APB3ENR_LPTIM3EN_Pos            (12U)
22594 #define RCC_APB3ENR_LPTIM3EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM3EN_Pos)      /*!< 0x000001000 */
22595 #define RCC_APB3ENR_LPTIM3EN                RCC_APB3ENR_LPTIM3EN_Msk                 /*!< LPTIM3 Clock Enable */
22596 #define RCC_APB3ENR_LPTIM4EN_Pos            (13U)
22597 #define RCC_APB3ENR_LPTIM4EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM4EN_Pos)      /*!< 0x0000002000 */
22598 #define RCC_APB3ENR_LPTIM4EN                RCC_APB3ENR_LPTIM4EN_Msk                 /*!< LPTIM4 Clock Enable */
22599 #define RCC_APB3ENR_OPAMPEN_Pos             (14U)
22600 #define RCC_APB3ENR_OPAMPEN_Msk             (0x1UL << RCC_APB3ENR_OPAMPEN_Pos)       /*!< 0x000004000 */
22601 #define RCC_APB3ENR_OPAMPEN                 RCC_APB3ENR_OPAMPEN_Msk                  /*!< OPAMP Clock Enable */
22602 #define RCC_APB3ENR_COMPEN_Pos              (15U)
22603 #define RCC_APB3ENR_COMPEN_Msk              (0x1UL << RCC_APB3ENR_COMPEN_Pos)        /*!< 0x000004000 */
22604 #define RCC_APB3ENR_COMPEN                  RCC_APB3ENR_COMPEN_Msk                   /*!< COMP Clock Enable */
22605 #define RCC_APB3ENR_VREFEN_Pos              (20U)
22606 #define RCC_APB3ENR_VREFEN_Msk              (0x1UL << RCC_APB3ENR_VREFEN_Pos)        /*!< 0x000100000 */
22607 #define RCC_APB3ENR_VREFEN                  RCC_APB3ENR_VREFEN_Msk                   /*!< VREFBUF Clock Enable */
22608 #define RCC_APB3ENR_RTCAPBEN_Pos            (21U)
22609 #define RCC_APB3ENR_RTCAPBEN_Msk            (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos)      /*!< 0x000200000 */
22610 #define RCC_APB3ENR_RTCAPBEN                RCC_APB3ENR_RTCAPBEN_Msk                 /*!< RTC APB Clock Enable */
22611 
22612 /********************  Bit definition for RCC_AHB1SMENR register  **************/
22613 #define RCC_AHB1SMENR_GPDMA1SMEN_Pos        (0U)
22614 #define RCC_AHB1SMENR_GPDMA1SMEN_Msk        (0x1UL << RCC_AHB1SMENR_GPDMA1SMEN_Pos)  /*!< 0x00000000*/
22615 #define RCC_AHB1SMENR_GPDMA1SMEN            RCC_AHB1SMENR_GPDMA1SMEN_Msk             /*!< GPDMA1 Clocks Enable During Sleep and Stop Modes */
22616 #define RCC_AHB1SMENR_CORDICSMEN_Pos        (1U)
22617 #define RCC_AHB1SMENR_CORDICSMEN_Msk        (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)  /*!< 0x00000001*/
22618 #define RCC_AHB1SMENR_CORDICSMEN            RCC_AHB1SMENR_CORDICSMEN_Msk             /*!< CORDIC Clocks Enable During Sleep and Stop Modes */
22619 #define RCC_AHB1SMENR_FMACSMEN_Pos          (2U)
22620 #define RCC_AHB1SMENR_FMACSMEN_Msk          (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos)    /*!< 0x00000002*/
22621 #define RCC_AHB1SMENR_FMACSMEN              RCC_AHB1SMENR_FMACSMEN_Msk               /*!< FMAC Clocks Enable During Sleep and Stop Modes */
22622 #define RCC_AHB1SMENR_MDF1SMEN_Pos          (3U)
22623 #define RCC_AHB1SMENR_MDF1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_MDF1SMEN_Pos)    /*!< 0x00000004 */
22624 #define RCC_AHB1SMENR_MDF1SMEN              RCC_AHB1SMENR_MDF1SMEN_Msk               /*!< MDF1 Clocks Enable During Sleep and Stop Modes */
22625 #define RCC_AHB1SMENR_FLASHSMEN_Pos         (8U)
22626 #define RCC_AHB1SMENR_FLASHSMEN_Msk         (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)   /*!< 0x00000100 */
22627 #define RCC_AHB1SMENR_FLASHSMEN             RCC_AHB1SMENR_FLASHSMEN_Msk              /*!< FLASH Clocks Enable During Sleep and Stop Modes */
22628 #define RCC_AHB1SMENR_CRCSMEN_Pos           (12U)
22629 #define RCC_AHB1SMENR_CRCSMEN_Msk           (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)     /*!< 0x00001000 */
22630 #define RCC_AHB1SMENR_CRCSMEN               RCC_AHB1SMENR_CRCSMEN_Msk                /*!< CRC Clocks Enable During Sleep and Stop Modes */
22631 #define RCC_AHB1SMENR_JPEGSMEN_Pos         (15U)
22632 #define RCC_AHB1SMENR_JPEGSMEN_Msk         (0x1UL << RCC_AHB1SMENR_JPEGSMEN_Pos)    /*!< 0x00008000 */
22633 #define RCC_AHB1SMENR_JPEGSMEN              RCC_AHB1SMENR_JPEGSMEN_Msk               /*!< JPEG Clocks Enable During Sleep and Stop Modes */
22634 #define RCC_AHB1SMENR_TSCSMEN_Pos           (16U)
22635 #define RCC_AHB1SMENR_TSCSMEN_Msk           (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos)     /*!< 0x00010000 */
22636 #define RCC_AHB1SMENR_TSCSMEN               RCC_AHB1SMENR_TSCSMEN_Msk                /*!< TSC Clocks Enable During Sleep and Stop Modes */
22637 #define RCC_AHB1SMENR_RAMCFGSMEN_Pos        (17U)
22638 #define RCC_AHB1SMENR_RAMCFGSMEN_Msk        (0x1UL << RCC_AHB1SMENR_RAMCFGSMEN_Pos)  /*!< 0x00020000 */
22639 #define RCC_AHB1SMENR_RAMCFGSMEN            RCC_AHB1SMENR_RAMCFGSMEN_Msk             /*!< RAMCFG Clocks Enable During Sleep and Stop Modes */
22640 #define RCC_AHB1SMENR_DMA2DSMEN_Pos         (18U)
22641 #define RCC_AHB1SMENR_DMA2DSMEN_Msk         (0x1UL << RCC_AHB1SMENR_DMA2DSMEN_Pos)   /*!< 0x00040000 */
22642 #define RCC_AHB1SMENR_DMA2DSMEN             RCC_AHB1SMENR_DMA2DSMEN_Msk              /*!< DMA2D Clocks Enable During Sleep and Stop Modes */
22643 #define RCC_AHB1SMENR_GFXMMUSMEN_Pos        (19U)
22644 #define RCC_AHB1SMENR_GFXMMUSMEN_Msk        (0x1UL << RCC_AHB1SMENR_GFXMMUSMEN_Pos)  /*!< 0x00080000 */
22645 #define RCC_AHB1SMENR_GFXMMUSMEN            RCC_AHB1SMENR_GFXMMUSMEN_Msk             /*!< GFXMMU Clocks Enable During Sleep and Stop Modes */
22646 #define RCC_AHB1SMENR_GPU2DSMEN_Pos         (20U)
22647 #define RCC_AHB1SMENR_GPU2DSMEN_Msk         (0x1UL << RCC_AHB1SMENR_GPU2DSMEN_Pos)   /*!< 0x00100000 */
22648 #define RCC_AHB1SMENR_GPU2DSMEN             RCC_AHB1SMENR_GPU2DSMEN_Msk              /*!< GPU2D Clocks Enable During Sleep and Stop Modes */
22649 #define RCC_AHB1SMENR_DCACHE2SMEN_Pos       (21U)
22650 #define RCC_AHB1SMENR_DCACHE2SMEN_Msk       (0x1UL << RCC_AHB1SMENR_DCACHE2SMEN_Pos) /*!< 0x00200000 */
22651 #define RCC_AHB1SMENR_DCACHE2SMEN           RCC_AHB1SMENR_DCACHE2SMEN_Msk            /*!< DCACHE2 Clocks Enable During Sleep and Stop Modes */
22652 #define RCC_AHB1SMENR_GTZC1SMEN_Pos         (24U)
22653 #define RCC_AHB1SMENR_GTZC1SMEN_Msk         (0x1UL << RCC_AHB1SMENR_GTZC1SMEN_Pos)   /*!< 0x01000000 */
22654 #define RCC_AHB1SMENR_GTZC1SMEN             RCC_AHB1SMENR_GTZC1SMEN_Msk              /*!< GTZC1 Clocks Enable During Sleep and Stop Modes */
22655 #define RCC_AHB1SMENR_BKPSRAMSMEN_Pos       (28U)
22656 #define RCC_AHB1SMENR_BKPSRAMSMEN_Msk       (0x1UL << RCC_AHB1SMENR_BKPSRAMSMEN_Pos) /*!< 0x10000000 */
22657 #define RCC_AHB1SMENR_BKPSRAMSMEN           RCC_AHB1SMENR_BKPSRAMSMEN_Msk            /*!< BKPSRAM Clocks Enable During Sleep and Stop Modes */
22658 #define RCC_AHB1SMENR_ICACHESMEN_Pos        (29U)
22659 #define RCC_AHB1SMENR_ICACHESMEN_Msk        (0x1UL << RCC_AHB1SMENR_ICACHESMEN_Pos)  /*!< 0x20000000 */
22660 #define RCC_AHB1SMENR_ICACHESMEN            RCC_AHB1SMENR_ICACHESMEN_Msk             /*!< ICACHE Clocks Enable During Sleep and Stop Modes */
22661 #define RCC_AHB1SMENR_DCACHE1SMEN_Pos       (30U)
22662 #define RCC_AHB1SMENR_DCACHE1SMEN_Msk       (0x1UL << RCC_AHB1SMENR_DCACHE1SMEN_Pos) /*!< 0x40000000 */
22663 #define RCC_AHB1SMENR_DCACHE1SMEN           RCC_AHB1SMENR_DCACHE1SMEN_Msk            /*!< DCACHE1 Clocks Enable During Sleep and Stop Modes */
22664 #define RCC_AHB1SMENR_SRAM1SMEN_Pos         (31U)
22665 #define RCC_AHB1SMENR_SRAM1SMEN_Msk         (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)   /*!< 0x80000000 */
22666 #define RCC_AHB1SMENR_SRAM1SMEN             RCC_AHB1SMENR_SRAM1SMEN_Msk              /*!< SRAM1 Clocks Enable During Sleep and Stop Modes */
22667 
22668 /********************  Bit definition for RCC_AHB2SMENR1 register  **************/
22669 #define RCC_AHB2SMENR1_GPIOASMEN_Pos        (0U)
22670 #define RCC_AHB2SMENR1_GPIOASMEN_Msk        (0x1UL << RCC_AHB2SMENR1_GPIOASMEN_Pos)  /*!< 0x00000001 */
22671 #define RCC_AHB2SMENR1_GPIOASMEN            RCC_AHB2SMENR1_GPIOASMEN_Msk             /*!< IO port A Clocks Enable During Sleep and Stop Modes */
22672 #define RCC_AHB2SMENR1_GPIOBSMEN_Pos        (1U)
22673 #define RCC_AHB2SMENR1_GPIOBSMEN_Msk        (0x1UL << RCC_AHB2SMENR1_GPIOBSMEN_Pos)  /*!< 0x00000002 */
22674 #define RCC_AHB2SMENR1_GPIOBSMEN            RCC_AHB2SMENR1_GPIOBSMEN_Msk             /*!< IO port B Clocks Enable During Sleep and Stop Modes */
22675 #define RCC_AHB2SMENR1_GPIOCSMEN_Pos        (2U)
22676 #define RCC_AHB2SMENR1_GPIOCSMEN_Msk        (0x1UL << RCC_AHB2SMENR1_GPIOCSMEN_Pos)  /*!< 0x00000004 */
22677 #define RCC_AHB2SMENR1_GPIOCSMEN            RCC_AHB2SMENR1_GPIOCSMEN_Msk             /*!< IO port C Clocks Enable During Sleep and Stop Modes */
22678 #define RCC_AHB2SMENR1_GPIODSMEN_Pos        (3U)
22679 #define RCC_AHB2SMENR1_GPIODSMEN_Msk        (0x1UL << RCC_AHB2SMENR1_GPIODSMEN_Pos)  /*!< 0x00000008 */
22680 #define RCC_AHB2SMENR1_GPIODSMEN            RCC_AHB2SMENR1_GPIODSMEN_Msk             /*!< IO port D Clocks Enable During Sleep and Stop Modes */
22681 #define RCC_AHB2SMENR1_GPIOESMEN_Pos        (4U)
22682 #define RCC_AHB2SMENR1_GPIOESMEN_Msk        (0x1UL << RCC_AHB2SMENR1_GPIOESMEN_Pos)  /*!< 0x00000010 */
22683 #define RCC_AHB2SMENR1_GPIOESMEN            RCC_AHB2SMENR1_GPIOESMEN_Msk             /*!< IO port E Clocks Enable During Sleep and Stop Modes */
22684 #define RCC_AHB2SMENR1_GPIOFSMEN_Pos        (5U)
22685 #define RCC_AHB2SMENR1_GPIOFSMEN_Msk        (0x1UL << RCC_AHB2SMENR1_GPIOFSMEN_Pos)  /*!< 0x00000020 */
22686 #define RCC_AHB2SMENR1_GPIOFSMEN            RCC_AHB2SMENR1_GPIOFSMEN_Msk             /*!< IO port F Clocks Enable During Sleep and Stop Modes */
22687 #define RCC_AHB2SMENR1_GPIOGSMEN_Pos        (6U)
22688 #define RCC_AHB2SMENR1_GPIOGSMEN_Msk        (0x1UL << RCC_AHB2SMENR1_GPIOGSMEN_Pos)  /*!< 0x00000040 */
22689 #define RCC_AHB2SMENR1_GPIOGSMEN            RCC_AHB2SMENR1_GPIOGSMEN_Msk             /*!< IO port G Clocks Enable During Sleep and Stop Modes */
22690 #define RCC_AHB2SMENR1_GPIOHSMEN_Pos        (7U)
22691 #define RCC_AHB2SMENR1_GPIOHSMEN_Msk        (0x1UL << RCC_AHB2SMENR1_GPIOHSMEN_Pos)  /*!< 0x00000080 */
22692 #define RCC_AHB2SMENR1_GPIOHSMEN            RCC_AHB2SMENR1_GPIOHSMEN_Msk             /*!< IO port H Clocks Enable During Sleep and Stop Modes */
22693 #define RCC_AHB2SMENR1_GPIOISMEN_Pos        (8U)
22694 #define RCC_AHB2SMENR1_GPIOISMEN_Msk        (0x1UL << RCC_AHB2SMENR1_GPIOISMEN_Pos)  /*!< 0x00000100 */
22695 #define RCC_AHB2SMENR1_GPIOISMEN            RCC_AHB2SMENR1_GPIOISMEN_Msk             /*!< IO port I Clocks Enable During Sleep and Stop Modes */
22696 #define RCC_AHB2SMENR1_GPIOJSMEN_Pos        (9U)
22697 #define RCC_AHB2SMENR1_GPIOJSMEN_Msk        (0x1UL << RCC_AHB2SMENR1_GPIOJSMEN_Pos)  /*!< 0x00000200 */
22698 #define RCC_AHB2SMENR1_GPIOJSMEN            RCC_AHB2SMENR1_GPIOJSMEN_Msk             /*!< IO port J Clocks Enable During Sleep and Stop Modes */
22699 #define RCC_AHB2SMENR1_ADC12SMEN_Pos        (10U)
22700 #define RCC_AHB2SMENR1_ADC12SMEN_Msk        (0x1UL << RCC_AHB2SMENR1_ADC12SMEN_Pos)   /*!< 0x00000400 */
22701 #define RCC_AHB2SMENR1_ADC12SMEN            RCC_AHB2SMENR1_ADC12SMEN_Msk              /*!< ADC1 Clocks Enable During Sleep and Stop Modes */
22702 #define RCC_AHB2SMENR1_DCMI_PSSISMEN_Pos    (12U)
22703 #define RCC_AHB2SMENR1_DCMI_PSSISMEN_Msk    (0x1UL << RCC_AHB2SMENR1_DCMI_PSSISMEN_Pos) /*!< 0x00001000 */
22704 #define RCC_AHB2SMENR1_DCMI_PSSISMEN        RCC_AHB2SMENR1_DCMI_PSSISMEN_Msk            /*!< DCMI and PSSI Clocks Enable During Sleep and Stop Modes */
22705 #define RCC_AHB2SMENR1_OTGSMEN_Pos          (14U)
22706 #define RCC_AHB2SMENR1_OTGSMEN_Msk          (0x1UL << RCC_AHB2SMENR1_OTGSMEN_Pos)       /*!< 0x00004000 */
22707 #define RCC_AHB2SMENR1_OTGSMEN              RCC_AHB2SMENR1_OTGSMEN_Msk                  /*!< OTG Clocks Enable During Sleep and Stop Modes */
22708 #define RCC_AHB2SMENR1_USBPHYCSMEN_Pos      (15U)
22709 #define RCC_AHB2SMENR1_USBPHYCSMEN_Msk      (0x1UL << RCC_AHB2SMENR1_USBPHYCSMEN_Pos) /*!< 0x00008000 */
22710 #define RCC_AHB2SMENR1_USBPHYCSMEN          RCC_AHB2SMENR1_USBPHYCSMEN_Msk
22711 #define RCC_AHB2SMENR1_AESSMEN_Pos          (16U)
22712 #define RCC_AHB2SMENR1_AESSMEN_Msk          (0x1UL << RCC_AHB2SMENR1_AESSMEN_Pos)    /*!< 0x00010000 */
22713 #define RCC_AHB2SMENR1_AESSMEN              RCC_AHB2SMENR1_AESSMEN_Msk               /*!< AES Clocks Enable During Sleep and Stop Modes */
22714 #define RCC_AHB2SMENR1_HASHSMEN_Pos         (17U)
22715 #define RCC_AHB2SMENR1_HASHSMEN_Msk         (0x1UL << RCC_AHB2SMENR1_HASHSMEN_Pos)   /*!< 0x00020000 */
22716 #define RCC_AHB2SMENR1_HASHSMEN             RCC_AHB2SMENR1_HASHSMEN_Msk              /*!< HASH Clocks Enable During Sleep and Stop Modes */
22717 #define RCC_AHB2SMENR1_RNGSMEN_Pos          (18U)
22718 #define RCC_AHB2SMENR1_RNGSMEN_Msk          (0x1UL << RCC_AHB2SMENR1_RNGSMEN_Pos)    /*!< 0x00040000 */
22719 #define RCC_AHB2SMENR1_RNGSMEN              RCC_AHB2SMENR1_RNGSMEN_Msk               /*!< Random Number Generator (RNG) Clocks Enable During Sleep and Stop Modes */
22720 #define RCC_AHB2SMENR1_PKASMEN_Pos          (19U)
22721 #define RCC_AHB2SMENR1_PKASMEN_Msk          (0x1UL << RCC_AHB2SMENR1_PKASMEN_Pos)    /*!< 0x00080000 */
22722 #define RCC_AHB2SMENR1_PKASMEN              RCC_AHB2SMENR1_PKASMEN_Msk               /*!< PKA Clocks Enable During Sleep and Stop Modes */
22723 #define RCC_AHB2SMENR1_SAESSMEN_Pos         (20U)
22724 #define RCC_AHB2SMENR1_SAESSMEN_Msk         (0x1UL << RCC_AHB2SMENR1_SAESSMEN_Pos)   /*!< 0x00100000 */
22725 #define RCC_AHB2SMENR1_SAESSMEN              RCC_AHB2SMENR1_SAESSMEN_Msk              /*!< SAES Clocks Enable During Sleep and Stop Modes */
22726 #define RCC_AHB2SMENR1_OCTOSPIMSMEN_Pos     (21U)
22727 #define RCC_AHB2SMENR1_OCTOSPIMSMEN_Msk     (0x1UL << RCC_AHB2SMENR1_OCTOSPIMSMEN_Pos)  /*!< 0x00200000 */
22728 #define RCC_AHB2SMENR1_OCTOSPIMSMEN         RCC_AHB2SMENR1_OCTOSPIMSMEN_Msk             /*!< OCTOSPIM Clocks Enable During Sleep and Stop Modes */
22729 #define RCC_AHB2SMENR1_OTFDEC1SMEN_Pos      (23U)
22730 #define RCC_AHB2SMENR1_OTFDEC1SMEN_Msk      (0x1UL << RCC_AHB2SMENR1_OTFDEC1SMEN_Pos) /*!< 0x00800000 */
22731 #define RCC_AHB2SMENR1_OTFDEC1SMEN          RCC_AHB2SMENR1_OTFDEC1SMEN_Msk            /*!< OTFDEC1 Clocks Enable During Sleep and Stop Modes */
22732 #define RCC_AHB2SMENR1_OTFDEC2SMEN_Pos      (24U)
22733 #define RCC_AHB2SMENR1_OTFDEC2SMEN_Msk      (0x1UL << RCC_AHB2SMENR1_OTFDEC2SMEN_Pos) /*!< 0x01000000 */
22734 #define RCC_AHB2SMENR1_OTFDEC2SMEN          RCC_AHB2SMENR1_OTFDEC2SMEN_Msk            /*!< OTFDEC2 Clocks Enable During Sleep and Stop Modes */
22735 #define RCC_AHB2SMENR1_SDMMC1SMEN_Pos       (27U)
22736 #define RCC_AHB2SMENR1_SDMMC1SMEN_Msk       (0x1UL << RCC_AHB2SMENR1_SDMMC1SMEN_Pos) /*!< 0x08000000 */
22737 #define RCC_AHB2SMENR1_SDMMC1SMEN           RCC_AHB2SMENR1_SDMMC1SMEN_Msk            /*!< SDMMC1 Clocks Enable During Sleep and Stop Modes */
22738 #define RCC_AHB2SMENR1_SDMMC2SMEN_Pos       (28U)
22739 #define RCC_AHB2SMENR1_SDMMC2SMEN_Msk       (0x1UL << RCC_AHB2SMENR1_SDMMC2SMEN_Pos) /*!< 0x10000000 */
22740 #define RCC_AHB2SMENR1_SDMMC2SMEN           RCC_AHB2SMENR1_SDMMC2SMEN_Msk            /*!< SDMMC2 Clocks Enable During Sleep and Stop Modes */
22741 #define RCC_AHB2SMENR1_SRAM2SMEN_Pos        (30U)
22742 #define RCC_AHB2SMENR1_SRAM2SMEN_Msk        (0x1UL << RCC_AHB2SMENR1_SRAM2SMEN_Pos)  /*!< 0x40000000 */
22743 #define RCC_AHB2SMENR1_SRAM2SMEN            RCC_AHB2SMENR1_SRAM2SMEN_Msk             /*!< SRAM2 Clocks Enable During Sleep and Stop Modes */
22744 #define RCC_AHB2SMENR1_SRAM3SMEN_Pos        (31U)
22745 #define RCC_AHB2SMENR1_SRAM3SMEN_Msk        (0x1UL << RCC_AHB2SMENR1_SRAM3SMEN_Pos)  /*!< 0x80000000 */
22746 #define RCC_AHB2SMENR1_SRAM3SMEN            RCC_AHB2SMENR1_SRAM3SMEN_Msk             /*!< SRAM3 Clocks Enable During Sleep and Stop Modes */
22747 
22748 /********************  Bit definition for RCC_AHB2SMENR2 register  **************/
22749 #define RCC_AHB2SMENR2_FSMCSMEN_Pos         (0U)
22750 #define RCC_AHB2SMENR2_FSMCSMEN_Msk         (0x1UL << RCC_AHB2SMENR2_FSMCSMEN_Pos)      /*!< 0x00000001 */
22751 #define RCC_AHB2SMENR2_FSMCSMEN             RCC_AHB2SMENR2_FSMCSMEN_Msk                 /*!< FSMC Clocks Enable During Sleep and Stop Modes */
22752 #define RCC_AHB2SMENR2_OCTOSPI1SMEN_Pos     (4U)
22753 #define RCC_AHB2SMENR2_OCTOSPI1SMEN_Msk     (0x1UL << RCC_AHB2SMENR2_OCTOSPI1SMEN_Pos)  /*!< 0x00000010 */
22754 #define RCC_AHB2SMENR2_OCTOSPI1SMEN         RCC_AHB2SMENR2_OCTOSPI1SMEN_Msk             /*!< OCTOSPI1 Clocks Enable During Sleep and Stop Modes */
22755 #define RCC_AHB2SMENR2_OCTOSPI2SMEN_Pos     (8U)
22756 #define RCC_AHB2SMENR2_OCTOSPI2SMEN_Msk     (0x1UL << RCC_AHB2SMENR2_OCTOSPI2SMEN_Pos)  /*!< 0x00000100 */
22757 #define RCC_AHB2SMENR2_OCTOSPI2SMEN         RCC_AHB2SMENR2_OCTOSPI2SMEN_Msk             /*!< OCTOSPI2 Clocks Enable During Sleep and Stop Modes */
22758 #define RCC_AHB2SMENR2_HSPI1SMEN_Pos        (12U)
22759 #define RCC_AHB2SMENR2_HSPI1SMEN_Msk        (0x1UL << RCC_AHB2SMENR2_HSPI1SMEN_Pos)     /*!< 0x00001000 */
22760 #define RCC_AHB2SMENR2_HSPI1SMEN            RCC_AHB2SMENR2_HSPI1SMEN_Msk                /*!< HSPI1 Clocks Enable During Sleep and Stop Modes */
22761 #define RCC_AHB2SMENR2_SRAM6SMEN_Pos        (30U)
22762 #define RCC_AHB2SMENR2_SRAM6SMEN_Msk        (0x1UL << RCC_AHB2SMENR2_SRAM6SMEN_Pos)     /*!< 0x40000000 */
22763 #define RCC_AHB2SMENR2_SRAM6SMEN            RCC_AHB2SMENR2_SRAM6SMEN_Msk                /*!< SRAM6 Clocks Enable During Sleep and Stop Modes */
22764 #define RCC_AHB2SMENR2_SRAM5SMEN_Pos        (31U)
22765 #define RCC_AHB2SMENR2_SRAM5SMEN_Msk        (0x1UL << RCC_AHB2SMENR2_SRAM5SMEN_Pos)     /*!< 0x80000000 */
22766 #define RCC_AHB2SMENR2_SRAM5SMEN            RCC_AHB2SMENR2_SRAM5SMEN_Msk                /*!< SRAM5 Clocks Enable During Sleep and Stop Modes */
22767 
22768 /********************  Bit definition for RCC_AHB3SMENR register  **************/
22769 #define RCC_AHB3SMENR_LPGPIO1SMEN_Pos       (0U)
22770 #define RCC_AHB3SMENR_LPGPIO1SMEN_Msk       (0x1UL << RCC_AHB3SMENR_LPGPIO1SMEN_Pos) /*!< 0x00000001 */
22771 #define RCC_AHB3SMENR_LPGPIO1SMEN           RCC_AHB3SMENR_LPGPIO1SMEN_Msk            /*!< LPGPIO1 Clocks Enable During Sleep and Stop Modes */
22772 #define RCC_AHB3SMENR_PWRSMEN_Pos           (2U)
22773 #define RCC_AHB3SMENR_PWRSMEN_Msk           (0x1UL << RCC_AHB3SMENR_PWRSMEN_Pos)     /*!< 0x00000004 */
22774 #define RCC_AHB3SMENR_PWRSMEN               RCC_AHB3SMENR_PWRSMEN_Msk                /*!< PWR Clocks Enable During Sleep and Stop Modes */
22775 #define RCC_AHB3SMENR_ADC4SMEN_Pos          (5U)
22776 #define RCC_AHB3SMENR_ADC4SMEN_Msk          (0x1UL << RCC_AHB3SMENR_ADC4SMEN_Pos)    /*!< 0x00000040 */
22777 #define RCC_AHB3SMENR_ADC4SMEN              RCC_AHB3SMENR_ADC4SMEN_Msk               /*!< ADC4 Clocks Enable During Sleep and Stop Modes */
22778 #define RCC_AHB3SMENR_DAC1SMEN_Pos          (6U)
22779 #define RCC_AHB3SMENR_DAC1SMEN_Msk          (0x1UL << RCC_AHB3SMENR_DAC1SMEN_Pos)    /*!< 0x00000040 */
22780 #define RCC_AHB3SMENR_DAC1SMEN              RCC_AHB3SMENR_DAC1SMEN_Msk               /*!< DAC1 Clocks Enable During Sleep and Stop Modes */
22781 #define RCC_AHB3SMENR_LPDMA1SMEN_Pos        (9U)
22782 #define RCC_AHB3SMENR_LPDMA1SMEN_Msk        (0x1UL << RCC_AHB3SMENR_LPDMA1SMEN_Pos)  /*!< 0x000000080 */
22783 #define RCC_AHB3SMENR_LPDMA1SMEN            RCC_AHB3SMENR_LPDMA1SMEN_Msk             /*!< LPDMA1 Clocks Enable During Sleep and Stop Modes */
22784 #define RCC_AHB3SMENR_ADF1SMEN_Pos          (10U)
22785 #define RCC_AHB3SMENR_ADF1SMEN_Msk          (0x1UL << RCC_AHB3SMENR_ADF1SMEN_Pos)    /*!< 0x000000400 */
22786 #define RCC_AHB3SMENR_ADF1SMEN              RCC_AHB3SMENR_ADF1SMEN_Msk               /*!< ADF1 Clocks Enable During Sleep and Stop Modes */
22787 #define RCC_AHB3SMENR_GTZC2SMEN_Pos         (12U)
22788 #define RCC_AHB3SMENR_GTZC2SMEN_Msk         (0x1UL << RCC_AHB3SMENR_GTZC2SMEN_Pos)   /*!< 0x000001000 */
22789 #define RCC_AHB3SMENR_GTZC2SMEN             RCC_AHB3SMENR_GTZC2SMEN_Msk              /*!< GTZC2 Clocks Enable During Sleep and Stop Modes */
22790 #define RCC_AHB3SMENR_SRAM4SMEN_Pos         (31U)
22791 #define RCC_AHB3SMENR_SRAM4SMEN_Msk         (0x1UL << RCC_AHB3SMENR_SRAM4SMEN_Pos)   /*!< 0x800000000 */
22792 #define RCC_AHB3SMENR_SRAM4SMEN             RCC_AHB3SMENR_SRAM4SMEN_Msk              /*!< SRAM4 Clocks Enable During Sleep and Stop Modes */
22793 
22794 /********************  Bit definition for RCC_APB1SMENR1 register  **************/
22795 #define RCC_APB1SMENR1_TIM2SMEN_Pos         (0U)
22796 #define RCC_APB1SMENR1_TIM2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)   /*!< 0x00000001 */
22797 #define RCC_APB1SMENR1_TIM2SMEN             RCC_APB1SMENR1_TIM2SMEN_Msk              /*!< TIM2 Clocks Enable During Sleep and Stop Modes */
22798 #define RCC_APB1SMENR1_TIM3SMEN_Pos         (1U)
22799 #define RCC_APB1SMENR1_TIM3SMEN_Msk         (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)   /*!< 0x00000002 */
22800 #define RCC_APB1SMENR1_TIM3SMEN             RCC_APB1SMENR1_TIM3SMEN_Msk              /*!< TIM3 Clocks Enable During Sleep and Stop Modes */
22801 #define RCC_APB1SMENR1_TIM4SMEN_Pos         (2U)
22802 #define RCC_APB1SMENR1_TIM4SMEN_Msk         (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)   /*!< 0x00000004 */
22803 #define RCC_APB1SMENR1_TIM4SMEN             RCC_APB1SMENR1_TIM4SMEN_Msk              /*!< TIM4 Clocks Enable During Sleep and Stop Modes */
22804 #define RCC_APB1SMENR1_TIM5SMEN_Pos         (3U)
22805 #define RCC_APB1SMENR1_TIM5SMEN_Msk         (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)   /*!< 0x00000008 */
22806 #define RCC_APB1SMENR1_TIM5SMEN             RCC_APB1SMENR1_TIM5SMEN_Msk              /*!< TIM5 Clocks Enable During Sleep and Stop Modes */
22807 #define RCC_APB1SMENR1_TIM6SMEN_Pos         (4U)
22808 #define RCC_APB1SMENR1_TIM6SMEN_Msk         (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)   /*!< 0x00000010 */
22809 #define RCC_APB1SMENR1_TIM6SMEN             RCC_APB1SMENR1_TIM6SMEN_Msk              /*!< TIM6 Clocks Enable During Sleep and Stop Modes */
22810 #define RCC_APB1SMENR1_TIM7SMEN_Pos         (5U)
22811 #define RCC_APB1SMENR1_TIM7SMEN_Msk         (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)   /*!< 0x00000020 */
22812 #define RCC_APB1SMENR1_TIM7SMEN             RCC_APB1SMENR1_TIM7SMEN_Msk              /*!< TIM7 Clocks Enable During Sleep and Stop Modes */
22813 #define RCC_APB1SMENR1_WWDGSMEN_Pos         (11U)
22814 #define RCC_APB1SMENR1_WWDGSMEN_Msk         (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)   /*!< 0x00000800 */
22815 #define RCC_APB1SMENR1_WWDGSMEN             RCC_APB1SMENR1_WWDGSMEN_Msk              /*!< Window Watchdog Clocks Enable During Sleep and Stop Modes */
22816 #define RCC_APB1SMENR1_SPI2SMEN_Pos         (14U)
22817 #define RCC_APB1SMENR1_SPI2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)   /*!< 0x00004000 */
22818 #define RCC_APB1SMENR1_SPI2SMEN             RCC_APB1SMENR1_SPI2SMEN_Msk              /*!< SPI2 Clocks Enable During Sleep and Stop Modes */
22819 #define RCC_APB1SMENR1_USART2SMEN_Pos       (17U)
22820 #define RCC_APB1SMENR1_USART2SMEN_Msk       (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)  /*!< 0x00020000 */
22821 #define RCC_APB1SMENR1_USART2SMEN           RCC_APB1SMENR1_USART2SMEN_Msk            /*!< USART2 Clocks Enable During Sleep and Stop Modes */
22822 #define RCC_APB1SMENR1_USART3SMEN_Pos       (18U)
22823 #define RCC_APB1SMENR1_USART3SMEN_Msk       (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)  /*!< 0x00040000 */
22824 #define RCC_APB1SMENR1_USART3SMEN           RCC_APB1SMENR1_USART3SMEN_Msk            /*!< USART3 Clocks Enable During Sleep and Stop Modes */
22825 #define RCC_APB1SMENR1_UART4SMEN_Pos        (19U)
22826 #define RCC_APB1SMENR1_UART4SMEN_Msk        (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)  /*!< 0x00080000 */
22827 #define RCC_APB1SMENR1_UART4SMEN            RCC_APB1SMENR1_UART4SMEN_Msk             /*!< UART4 Clocks Enable During Sleep and Stop Modes */
22828 #define RCC_APB1SMENR1_UART5SMEN_Pos        (20U)
22829 #define RCC_APB1SMENR1_UART5SMEN_Msk        (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)  /*!< 0x00100000 */
22830 #define RCC_APB1SMENR1_UART5SMEN            RCC_APB1SMENR1_UART5SMEN_Msk             /*!< UART5 Clocks Enable During Sleep and Stop Modes */
22831 #define RCC_APB1SMENR1_I2C1SMEN_Pos         (21U)
22832 #define RCC_APB1SMENR1_I2C1SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)   /*!< 0x00200000 */
22833 #define RCC_APB1SMENR1_I2C1SMEN             RCC_APB1SMENR1_I2C1SMEN_Msk              /*!< I2C1 Clocks Enable During Sleep and Stop Modes */
22834 #define RCC_APB1SMENR1_I2C2SMEN_Pos         (22U)
22835 #define RCC_APB1SMENR1_I2C2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)   /*!< 0x00400000 */
22836 #define RCC_APB1SMENR1_I2C2SMEN             RCC_APB1SMENR1_I2C2SMEN_Msk              /*!< I2C2 Clocks Enable During Sleep and Stop Modes */
22837 #define RCC_APB1SMENR1_CRSSMEN_Pos          (24U)
22838 #define RCC_APB1SMENR1_CRSSMEN_Msk          (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)    /*!< 0x01000000 */
22839 #define RCC_APB1SMENR1_CRSSMEN              RCC_APB1SMENR1_CRSSMEN_Msk               /*!< CRS Clocks Enable During Sleep and Stop Modes */
22840 #define RCC_APB1SMENR1_USART6SMEN_Pos       (25U)
22841 #define RCC_APB1SMENR1_USART6SMEN_Msk       (0x1UL << RCC_APB1SMENR1_USART6SMEN_Pos) /*!< 0x02000000 */
22842 #define RCC_APB1SMENR1_USART6SMEN           RCC_APB1SMENR1_USART6SMEN_Msk
22843 
22844 /********************  Bit definition for RCC_APB1SMENR2 register  **************/
22845 #define RCC_APB1SMENR2_I2C4SMEN_Pos         (1U)
22846 #define RCC_APB1SMENR2_I2C4SMEN_Msk         (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos)   /*!< 0x00000002 */
22847 #define RCC_APB1SMENR2_I2C4SMEN             RCC_APB1SMENR2_I2C4SMEN_Msk              /*!< I2C4 Clocks Enable During Sleep and Stop Modes */
22848 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos       (5U)
22849 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
22850 #define RCC_APB1SMENR2_LPTIM2SMEN           RCC_APB1SMENR2_LPTIM2SMEN_Msk            /*!< LPTIM2 Clocks Enable During Sleep and Stop Modes */
22851 #define RCC_APB1SMENR2_I2C5SMEN_Pos         (6U)
22852 #define RCC_APB1SMENR2_I2C5SMEN_Msk         (0x1UL << RCC_APB1SMENR2_I2C5SMEN_Pos)   /*!< 0x00000040 */
22853 #define RCC_APB1SMENR2_I2C5SMEN             RCC_APB1SMENR2_I2C5SMEN_Msk              /*!< I2C5 Clocks Enable During Sleep and Stop Modes */
22854 #define RCC_APB1SMENR2_I2C6SMEN_Pos         (7U)
22855 #define RCC_APB1SMENR2_I2C6SMEN_Msk         (0x1UL << RCC_APB1SMENR2_I2C6SMEN_Pos)   /*!< 0x00000080 */
22856 #define RCC_APB1SMENR2_I2C6SMEN             RCC_APB1SMENR2_I2C6SMEN_Msk              /*!< I2C6 Clocks Enable During Sleep and Stop Modes */
22857 #define RCC_APB1SMENR2_FDCAN1SMEN_Pos       (9U)
22858 #define RCC_APB1SMENR2_FDCAN1SMEN_Msk       (0x1UL << RCC_APB1SMENR2_FDCAN1SMEN_Pos) /*!< 0x00000200 */
22859 #define RCC_APB1SMENR2_FDCAN1SMEN           RCC_APB1SMENR2_FDCAN1SMEN_Msk            /*!< FDCAN1 Clocks Enable During Sleep and Stop Modes */
22860 #define RCC_APB1SMENR2_UCPD1SMEN_Pos        (23U)
22861 #define RCC_APB1SMENR2_UCPD1SMEN_Msk        (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)  /*!< 0x00800000 */
22862 #define RCC_APB1SMENR2_UCPD1SMEN            RCC_APB1SMENR2_UCPD1SMEN_Msk             /*!< UCPD1 Clocks Enable During Sleep and Stop Modes */
22863 
22864 /********************  Bit definition for RCC_APB2SMENR register  **************/
22865 #define RCC_APB2SMENR_TIM1SMEN_Pos          (11U)
22866 #define RCC_APB2SMENR_TIM1SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)    /*!< 0x00000800 */
22867 #define RCC_APB2SMENR_TIM1SMEN              RCC_APB2SMENR_TIM1SMEN_Msk               /*!< TIM1 Clocks Enable During Sleep and Stop Modes */
22868 #define RCC_APB2SMENR_SPI1SMEN_Pos          (12U)
22869 #define RCC_APB2SMENR_SPI1SMEN_Msk          (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)    /*!< 0x00001000 */
22870 #define RCC_APB2SMENR_SPI1SMEN              RCC_APB2SMENR_SPI1SMEN_Msk               /*!< SPI1 Clocks Enable During Sleep and Stop Modes */
22871 #define RCC_APB2SMENR_TIM8SMEN_Pos          (13U)
22872 #define RCC_APB2SMENR_TIM8SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)    /*!< 0x00002000 */
22873 #define RCC_APB2SMENR_TIM8SMEN              RCC_APB2SMENR_TIM8SMEN_Msk               /*!< TIM8 Clocks Enable During Sleep and Stop Modes */
22874 #define RCC_APB2SMENR_USART1SMEN_Pos        (14U)
22875 #define RCC_APB2SMENR_USART1SMEN_Msk        (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)  /*!< 0x00004000 */
22876 #define RCC_APB2SMENR_USART1SMEN            RCC_APB2SMENR_USART1SMEN_Msk             /*!< USART1 Clocks Enable During Sleep and Stop Modes */
22877 #define RCC_APB2SMENR_TIM15SMEN_Pos         (16U)
22878 #define RCC_APB2SMENR_TIM15SMEN_Msk         (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)   /*!< 0x00010000 */
22879 #define RCC_APB2SMENR_TIM15SMEN             RCC_APB2SMENR_TIM15SMEN_Msk              /*!< TIM15 Clocks Enable During Sleep and Stop Modes */
22880 #define RCC_APB2SMENR_TIM16SMEN_Pos         (17U)
22881 #define RCC_APB2SMENR_TIM16SMEN_Msk         (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)   /*!< 0x00020000 */
22882 #define RCC_APB2SMENR_TIM16SMEN             RCC_APB2SMENR_TIM16SMEN_Msk              /*!< TIM16 Clocks Enable During Sleep and Stop Modes */
22883 #define RCC_APB2SMENR_TIM17SMEN_Pos         (18U)
22884 #define RCC_APB2SMENR_TIM17SMEN_Msk         (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)   /*!< 0x00040000 */
22885 #define RCC_APB2SMENR_TIM17SMEN             RCC_APB2SMENR_TIM17SMEN_Msk              /*!< TIM17 Clocks Enable During Sleep and Stop Modes */
22886 #define RCC_APB2SMENR_SAI1SMEN_Pos          (21U)
22887 #define RCC_APB2SMENR_SAI1SMEN_Msk          (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)    /*!< 0x00200000 */
22888 #define RCC_APB2SMENR_SAI1SMEN              RCC_APB2SMENR_SAI1SMEN_Msk               /*!< SAI1 Clocks Enable During Sleep and Stop Modes */
22889 #define RCC_APB2SMENR_SAI2SMEN_Pos          (22U)
22890 #define RCC_APB2SMENR_SAI2SMEN_Msk          (0x1UL << RCC_APB2SMENR_SAI2SMEN_Pos)    /*!< 0x00400000 */
22891 #define RCC_APB2SMENR_SAI2SMEN              RCC_APB2SMENR_SAI2SMEN_Msk               /*!< SAI2 Clocks Enable During Sleep and Stop Modes */
22892 #define RCC_APB2SMENR_GFXTIMSMEN_Pos       (25U)
22893 #define RCC_APB2SMENR_GFXTIMSMEN_Msk       (0x1UL << RCC_APB2SMENR_GFXTIMSMEN_Pos)   /*!< 0x02000000 */
22894 #define RCC_APB2SMENR_GFXTIMSMEN           RCC_APB2SMENR_GFXTIMSMEN_Msk              /*!< GFXTIM Clocks Enable During Sleep and Stop Modes */
22895 #define RCC_APB2SMENR_LTDCSMEN_Pos         (26U)
22896 #define RCC_APB2SMENR_LTDCSMEN_Msk         (0x1UL << RCC_APB2SMENR_LTDCSMEN_Pos)     /*!< 0x04000000 */
22897 #define RCC_APB2SMENR_LTDCSMEN             RCC_APB2SMENR_LTDCSMEN_Msk                /*!< SAI2 Clocks Enable During Sleep and Stop Modes */
22898 #define RCC_APB2SMENR_DSIHOSTSMEN_Pos      (27U)
22899 #define RCC_APB2SMENR_DSIHOSTSMEN_Msk      (0x1UL << RCC_APB2SMENR_DSIHOSTSMEN_Pos)  /*!< 0x08000000 */
22900 #define RCC_APB2SMENR_DSIHOSTSMEN          RCC_APB2SMENR_DSIHOSTSMEN_Msk             /*!< SAI2 Clocks Enable During Sleep and Stop Modes */
22901 
22902 /********************  Bit definition for RCC_APB3SMENR register  **************/
22903 #define RCC_APB3SMENR_SYSCFGSMEN_Pos        (1U)
22904 #define RCC_APB3SMENR_SYSCFGSMEN_Msk        (0x1UL << RCC_APB3SMENR_SYSCFGSMEN_Pos)  /*!< 0x00000001 */
22905 #define RCC_APB3SMENR_SYSCFGSMEN            RCC_APB3SMENR_SYSCFGSMEN_Msk             /*!< SYSCFG Clocks Enable During Sleep and Stop Modes */
22906 #define RCC_APB3SMENR_SPI3SMEN_Pos          (5U)
22907 #define RCC_APB3SMENR_SPI3SMEN_Msk          (0x1UL << RCC_APB3SMENR_SPI3SMEN_Pos)    /*!< 0x00000010 */
22908 #define RCC_APB3SMENR_SPI3SMEN              RCC_APB3SMENR_SPI3SMEN_Msk               /*!< SPI3 Clocks Enable During Sleep and Stop Modes */
22909 #define RCC_APB3SMENR_LPUART1SMEN_Pos       (6U)
22910 #define RCC_APB3SMENR_LPUART1SMEN_Msk       (0x1UL << RCC_APB3SMENR_LPUART1SMEN_Pos)   /*!< 0x00000040 */
22911 #define RCC_APB3SMENR_LPUART1SMEN           RCC_APB3SMENR_LPUART1SMEN_Msk             /*!< LPUART1 Clocks Enable During Sleep and Stop Modes */
22912 #define RCC_APB3SMENR_I2C3SMEN_Pos          (7U)
22913 #define RCC_APB3SMENR_I2C3SMEN_Msk          (0x1UL << RCC_APB3SMENR_I2C3SMEN_Pos)    /*!< 0x000000080 */
22914 #define RCC_APB3SMENR_I2C3SMEN              RCC_APB3SMENR_I2C3SMEN_Msk               /*!< I2C3 Clocks Enable During Sleep and Stop Modes */
22915 #define RCC_APB3SMENR_LPTIM1SMEN_Pos        (11U)
22916 #define RCC_APB3SMENR_LPTIM1SMEN_Msk        (0x1UL << RCC_APB3SMENR_LPTIM1SMEN_Pos)  /*!< 0x000000800 */
22917 #define RCC_APB3SMENR_LPTIM1SMEN            RCC_APB3SMENR_LPTIM1SMEN_Msk             /*!< LPTIM1 Clocks Enable During Sleep and Stop Modes */
22918 #define RCC_APB3SMENR_LPTIM3SMEN_Pos        (12U)
22919 #define RCC_APB3SMENR_LPTIM3SMEN_Msk        (0x1UL << RCC_APB3SMENR_LPTIM3SMEN_Pos)  /*!< 0x000001000 */
22920 #define RCC_APB3SMENR_LPTIM3SMEN            RCC_APB3SMENR_LPTIM3SMEN_Msk             /*!< LPTIM3 Clocks Enable During Sleep and Stop Modes */
22921 #define RCC_APB3SMENR_LPTIM4SMEN_Pos        (13U)
22922 #define RCC_APB3SMENR_LPTIM4SMEN_Msk        (0x1UL << RCC_APB3SMENR_LPTIM4SMEN_Pos)  /*!< 0x0000002000*/
22923 #define RCC_APB3SMENR_LPTIM4SMEN            RCC_APB3SMENR_LPTIM4SMEN_Msk             /*!< LPTIM4 Clocks Enable During Sleep and Stop Modes */
22924 #define RCC_APB3SMENR_OPAMPSMEN_Pos         (14U)
22925 #define RCC_APB3SMENR_OPAMPSMEN_Msk         (0x1UL << RCC_APB3SMENR_OPAMPSMEN_Pos)   /*!< 0x000004000 */
22926 #define RCC_APB3SMENR_OPAMPSMEN             RCC_APB3SMENR_OPAMPSMEN_Msk              /*!< OPAMP Clocks Enable During Sleep and Stop Modes */
22927 #define RCC_APB3SMENR_COMPSMEN_Pos          (15U)
22928 #define RCC_APB3SMENR_COMPSMEN_Msk          (0x1UL << RCC_APB3SMENR_COMPSMEN_Pos)    /*!< 0x000004000 */
22929 #define RCC_APB3SMENR_COMPSMEN              RCC_APB3SMENR_COMPSMEN_Msk               /*!< COMP Clocks Enable During Sleep and Stop Modes */
22930 #define RCC_APB3SMENR_VREFSMEN_Pos          (20U)
22931 #define RCC_APB3SMENR_VREFSMEN_Msk          (0x1UL << RCC_APB3SMENR_VREFSMEN_Pos)    /*!< 0x000100000 */
22932 #define RCC_APB3SMENR_VREFSMEN              RCC_APB3SMENR_VREFSMEN_Msk               /*!< VREFBUF Clocks Enable During Sleep and Stop Modes */
22933 #define RCC_APB3SMENR_RTCAPBSMEN_Pos        (21U)
22934 #define RCC_APB3SMENR_RTCAPBSMEN_Msk        (0x1UL << RCC_APB3SMENR_RTCAPBSMEN_Pos)  /*!< 0x000100000 */
22935 #define RCC_APB3SMENR_RTCAPBSMEN            RCC_APB3SMENR_RTCAPBSMEN_Msk             /*!< RTC APB Clocks Enable During Sleep and Stop Modes */
22936 
22937 /********************  Bit definition for RCC_SRDAMR register  ********************/
22938 #define RCC_SRDAMR_SPI3AMEN_Pos             (5U)
22939 #define RCC_SRDAMR_SPI3AMEN_Msk             (0x1UL << RCC_SRDAMR_SPI3AMEN_Pos)       /*!< 0x00000020 */
22940 #define RCC_SRDAMR_SPI3AMEN                 RCC_SRDAMR_SPI3AMEN_Msk                  /*!< SPI3 Autonomous Mode Enable in Stop 0,1,2 Mode */
22941 #define RCC_SRDAMR_LPUART1AMEN_Pos          (6U)
22942 #define RCC_SRDAMR_LPUART1AMEN_Msk          (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos)    /*!< 0x00000040 */
22943 #define RCC_SRDAMR_LPUART1AMEN              RCC_SRDAMR_LPUART1AMEN_Msk               /*!< LPUART1 Autonomous Mode Enable in Stop 0,1,2 Mode */
22944 #define RCC_SRDAMR_I2C3AMEN_Pos             (7U)
22945 #define RCC_SRDAMR_I2C3AMEN_Msk             (0x1UL << RCC_SRDAMR_I2C3AMEN_Pos)       /*!< 0x00000080 */
22946 #define RCC_SRDAMR_I2C3AMEN                 RCC_SRDAMR_I2C3AMEN_Msk                  /*!< I2C3 Autonomous Mode Enable in Stop 0,1,2 Mode */
22947 #define RCC_SRDAMR_LPTIM1AMEN_Pos           (11U)
22948 #define RCC_SRDAMR_LPTIM1AMEN_Msk           (0x1UL << RCC_SRDAMR_LPTIM1AMEN_Pos)     /*!< 0x00000800 */
22949 #define RCC_SRDAMR_LPTIM1AMEN               RCC_SRDAMR_LPTIM1AMEN_Msk                /*!< LPTIM1 Autonomous Mode Enable in Stop 0,1,2 Mode */
22950 #define RCC_SRDAMR_LPTIM3AMEN_Pos           (12U)
22951 #define RCC_SRDAMR_LPTIM3AMEN_Msk           (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos)     /*!< 0x00001000 */
22952 #define RCC_SRDAMR_LPTIM3AMEN               RCC_SRDAMR_LPTIM3AMEN_Msk                /*!< LPTIM3 Autonomous Mode Enable in Stop 0,1,2 Mode */
22953 #define RCC_SRDAMR_LPTIM4AMEN_Pos           (13U)
22954 #define RCC_SRDAMR_LPTIM4AMEN_Msk           (0x1UL << RCC_SRDAMR_LPTIM4AMEN_Pos)     /*!< 0x00002000 */
22955 #define RCC_SRDAMR_LPTIM4AMEN               RCC_SRDAMR_LPTIM4AMEN_Msk                /*!< LPTIM4 Autonomous Mode Enable in Stop 0,1,2 Mode */
22956 #define RCC_SRDAMR_OPAMPAMEN_Pos            (14U)
22957 #define RCC_SRDAMR_OPAMPAMEN_Msk            (0x1UL << RCC_SRDAMR_OPAMPAMEN_Pos)      /*!< 0x00004000 */
22958 #define RCC_SRDAMR_OPAMPAMEN                RCC_SRDAMR_OPAMPAMEN_Msk                 /*!< OPAMP Autonomous Mode Enable in Stop 0,1,2 Mode */
22959 #define RCC_SRDAMR_COMPAMEN_Pos             (15U)
22960 #define RCC_SRDAMR_COMPAMEN_Msk             (0x1UL << RCC_SRDAMR_COMPAMEN_Pos)       /*!< 0x00008000 */
22961 #define RCC_SRDAMR_COMPAMEN                 RCC_SRDAMR_COMPAMEN_Msk                  /*!< COMP Autonomous Mode Enable in Stop 0,1,2 Mode */
22962 #define RCC_SRDAMR_VREFAMEN_Pos             (20U)
22963 #define RCC_SRDAMR_VREFAMEN_Msk             (0x1UL << RCC_SRDAMR_VREFAMEN_Pos)       /*!< 0x00100000 */
22964 #define RCC_SRDAMR_VREFAMEN                 RCC_SRDAMR_VREFAMEN_Msk                  /*!< VREFBUF Autonomous Mode Enable in Stop 0,1,2 Mode */
22965 #define RCC_SRDAMR_RTCAPBAMEN_Pos           (21U)
22966 #define RCC_SRDAMR_RTCAPBAMEN_Msk           (0x1UL << RCC_SRDAMR_RTCAPBAMEN_Pos)     /*!< 0x00200000 */
22967 #define RCC_SRDAMR_RTCAPBAMEN               RCC_SRDAMR_RTCAPBAMEN_Msk                /*!< RTC Autonomous Mode Enable in Stop 0,1,2 Mode */
22968 #define RCC_SRDAMR_ADC4AMEN_Pos             (25U)
22969 #define RCC_SRDAMR_ADC4AMEN_Msk             (0x1UL << RCC_SRDAMR_ADC4AMEN_Pos)       /*!< 0x02000000 */
22970 #define RCC_SRDAMR_ADC4AMEN                 RCC_SRDAMR_ADC4AMEN_Msk                  /*!< ADC4 Autonomous Mode Enable in Stop 0,1,2 Mode */
22971 #define RCC_SRDAMR_LPGPIO1AMEN_Pos          (26U)
22972 #define RCC_SRDAMR_LPGPIO1AMEN_Msk          (0x1UL << RCC_SRDAMR_LPGPIO1AMEN_Pos)    /*!< 0x04000000 */
22973 #define RCC_SRDAMR_LPGPIO1AMEN              RCC_SRDAMR_LPGPIO1AMEN_Msk               /*!< LPGPIO1 Autonomous Mode Enable in Stop 0,1,2 Mode */
22974 #define RCC_SRDAMR_DAC1AMEN_Pos             (27U)
22975 #define RCC_SRDAMR_DAC1AMEN_Msk             (0x1UL << RCC_SRDAMR_DAC1AMEN_Pos)       /*!< 0x08000000 */
22976 #define RCC_SRDAMR_DAC1AMEN                 RCC_SRDAMR_DAC1AMEN_Msk                  /*!< DAC1 Autonomous Mode Enable in Stop 0,1,2 Mode */
22977 #define RCC_SRDAMR_LPDMA1AMEN_Pos           (28U)
22978 #define RCC_SRDAMR_LPDMA1AMEN_Msk           (0x1UL << RCC_SRDAMR_LPDMA1AMEN_Pos)     /*!< 0x10000000 */
22979 #define RCC_SRDAMR_LPDMA1AMEN               RCC_SRDAMR_LPDMA1AMEN_Msk                /*!< LPDMA1 Autonomous Mode Enable in Stop 0,1,2 Mode */
22980 #define RCC_SRDAMR_ADF1AMEN_Pos             (29U)
22981 #define RCC_SRDAMR_ADF1AMEN_Msk             (0x1UL << RCC_SRDAMR_ADF1AMEN_Pos)       /*!< 0x20000000 */
22982 #define RCC_SRDAMR_ADF1AMEN                 RCC_SRDAMR_ADF1AMEN_Msk                  /*!< ADF1 Autonomous Mode Enable in Stop 0,1,2 Mode */
22983 #define RCC_SRDAMR_SRAM4AMEN_Pos            (31U)
22984 #define RCC_SRDAMR_SRAM4AMEN_Msk            (0x1UL << RCC_SRDAMR_SRAM4AMEN_Pos)      /*!< 0x80000000 */
22985 #define RCC_SRDAMR_SRAM4AMEN                RCC_SRDAMR_SRAM4AMEN_Msk                 /*!< SRAM4 Autonomous Mode Enable in Stop 0,1,2 Mode */
22986 
22987 /********************  Bit definition for RCC_CCIPR1 register  ******************/
22988 #define RCC_CCIPR1_USART1SEL_Pos            (0U)
22989 #define RCC_CCIPR1_USART1SEL_Msk            (0x3UL << RCC_CCIPR1_USART1SEL_Pos)      /*!< 0x00000003 */
22990 #define RCC_CCIPR1_USART1SEL                RCC_CCIPR1_USART1SEL_Msk                 /*!< USART1SEL[1:0]: bits (USART1 Kernel Clock Source Selection) */
22991 #define RCC_CCIPR1_USART1SEL_0              (0x1UL << RCC_CCIPR1_USART1SEL_Pos)      /*!< 0x00000001 */
22992 #define RCC_CCIPR1_USART1SEL_1              (0x2UL << RCC_CCIPR1_USART1SEL_Pos)      /*!< 0x00000002 */
22993 #define RCC_CCIPR1_USART2SEL_Pos            (2U)
22994 #define RCC_CCIPR1_USART2SEL_Msk            (0x3UL << RCC_CCIPR1_USART2SEL_Pos)      /*!< 0x0000000C */
22995 #define RCC_CCIPR1_USART2SEL                RCC_CCIPR1_USART2SEL_Msk                 /*!< USART2SEL[1:0]: bits (USART2 Kernel Clock Source Selection) */
22996 #define RCC_CCIPR1_USART2SEL_0              (0x1UL << RCC_CCIPR1_USART2SEL_Pos)      /*!< 0x00000004 */
22997 #define RCC_CCIPR1_USART2SEL_1              (0x2UL << RCC_CCIPR1_USART2SEL_Pos)      /*!< 0x00000008 */
22998 #define RCC_CCIPR1_USART3SEL_Pos            (4U)
22999 #define RCC_CCIPR1_USART3SEL_Msk            (0x3UL << RCC_CCIPR1_USART3SEL_Pos)      /*!< 0x00000030 */
23000 #define RCC_CCIPR1_USART3SEL                RCC_CCIPR1_USART3SEL_Msk                 /*!< USART3SEL[1:0]: bits (USART3 Kernel Clock Source Selection) */
23001 #define RCC_CCIPR1_USART3SEL_0              (0x1UL << RCC_CCIPR1_USART3SEL_Pos)      /*!< 0x00000010 */
23002 #define RCC_CCIPR1_USART3SEL_1              (0x2UL << RCC_CCIPR1_USART3SEL_Pos)      /*!< 0x00000020 */
23003 #define RCC_CCIPR1_UART4SEL_Pos             (6U)
23004 #define RCC_CCIPR1_UART4SEL_Msk             (0x3UL << RCC_CCIPR1_UART4SEL_Pos)       /*!< 0x000000C0 */
23005 #define RCC_CCIPR1_UART4SEL                 RCC_CCIPR1_UART4SEL_Msk                  /*!< UART4SEL[1:0]: bits (UART4 Kernel Clock Source Selection) */
23006 #define RCC_CCIPR1_UART4SEL_0               (0x1UL << RCC_CCIPR1_UART4SEL_Pos)       /*!< 0x00000040 */
23007 #define RCC_CCIPR1_UART4SEL_1               (0x2UL << RCC_CCIPR1_UART4SEL_Pos)       /*!< 0x00000080 */
23008 #define RCC_CCIPR1_UART5SEL_Pos             (8U)
23009 #define RCC_CCIPR1_UART5SEL_Msk             (0x3UL << RCC_CCIPR1_UART5SEL_Pos)       /*!< 0x00000300 */
23010 #define RCC_CCIPR1_UART5SEL                 RCC_CCIPR1_UART5SEL_Msk                  /*!< UART5SEL[1:0]: bits (UART5 Kernel Clock Source Selection) */
23011 #define RCC_CCIPR1_UART5SEL_0               (0x1UL << RCC_CCIPR1_UART5SEL_Pos)       /*!< 0x00000100 */
23012 #define RCC_CCIPR1_UART5SEL_1               (0x2UL << RCC_CCIPR1_UART5SEL_Pos)       /*!< 0x00000200 */
23013 #define RCC_CCIPR1_I2C1SEL_Pos              (10U)
23014 #define RCC_CCIPR1_I2C1SEL_Msk              (0x3UL << RCC_CCIPR1_I2C1SEL_Pos)        /*!< 0x00000C00 */
23015 #define RCC_CCIPR1_I2C1SEL                  RCC_CCIPR1_I2C1SEL_Msk                   /*!< I2C1SEL[1:0]: bits (I2C1 Kernel Clock Source Selection) */
23016 #define RCC_CCIPR1_I2C1SEL_0                (0x1UL << RCC_CCIPR1_I2C1SEL_Pos)        /*!< 0x00000400 */
23017 #define RCC_CCIPR1_I2C1SEL_1                (0x2UL << RCC_CCIPR1_I2C1SEL_Pos)        /*!< 0x00000800 */
23018 #define RCC_CCIPR1_I2C2SEL_Pos              (12U)
23019 #define RCC_CCIPR1_I2C2SEL_Msk              (0x3UL << RCC_CCIPR1_I2C2SEL_Pos)        /*!< 0x00003000 */
23020 #define RCC_CCIPR1_I2C2SEL                  RCC_CCIPR1_I2C2SEL_Msk                   /*!< I2C2SEL[1:0]: bits (I2C2 Kernel Clock Source Selection) */
23021 #define RCC_CCIPR1_I2C2SEL_0                (0x1UL << RCC_CCIPR1_I2C2SEL_Pos)        /*!< 0x00001000 */
23022 #define RCC_CCIPR1_I2C2SEL_1                (0x2UL << RCC_CCIPR1_I2C2SEL_Pos)        /*!< 0x00002000 */
23023 #define RCC_CCIPR1_I2C4SEL_Pos              (14U)
23024 #define RCC_CCIPR1_I2C4SEL_Msk              (0x3UL << RCC_CCIPR1_I2C4SEL_Pos)        /*!< 0x0000C000 */
23025 #define RCC_CCIPR1_I2C4SEL                  RCC_CCIPR1_I2C4SEL_Msk                   /*!< I2C4SEL[1:0]: bits (I2C4 Kernel Clock Source Selection) */
23026 #define RCC_CCIPR1_I2C4SEL_0                (0x1UL << RCC_CCIPR1_I2C4SEL_Pos)        /*!< 0x00004000 */
23027 #define RCC_CCIPR1_I2C4SEL_1                (0x2UL << RCC_CCIPR1_I2C4SEL_Pos)        /*!< 0x00008000 */
23028 #define RCC_CCIPR1_SPI2SEL_Pos              (16U)
23029 #define RCC_CCIPR1_SPI2SEL_Msk              (0x3UL << RCC_CCIPR1_SPI2SEL_Pos)        /*!< 0x00030000 */
23030 #define RCC_CCIPR1_SPI2SEL                  RCC_CCIPR1_SPI2SEL_Msk                   /*!< SPI2SEL[1:0]: bits (SPI2 Kernel Clock Source Selection) */
23031 #define RCC_CCIPR1_SPI2SEL_0                (0x1UL << RCC_CCIPR1_SPI2SEL_Pos)        /*!< 0x00010000 */
23032 #define RCC_CCIPR1_SPI2SEL_1                (0x2UL << RCC_CCIPR1_SPI2SEL_Pos)        /*!< 0x00020000 */
23033 #define RCC_CCIPR1_LPTIM2SEL_Pos            (18U)
23034 #define RCC_CCIPR1_LPTIM2SEL_Msk            (0x3UL << RCC_CCIPR1_LPTIM2SEL_Pos)      /*!< 0x000C0000 */
23035 #define RCC_CCIPR1_LPTIM2SEL                RCC_CCIPR1_LPTIM2SEL_Msk                 /*!< LPTIM2SEL[1:0]: bits (Low-power Timer 2 Kernel Clock Source Selection) */
23036 #define RCC_CCIPR1_LPTIM2SEL_0              (0x1UL << RCC_CCIPR1_LPTIM2SEL_Pos)      /*!< 0x00040000 */
23037 #define RCC_CCIPR1_LPTIM2SEL_1              (0x2UL << RCC_CCIPR1_LPTIM2SEL_Pos)      /*!< 0x00080000 */
23038 #define RCC_CCIPR1_SPI1SEL_Pos              (20U)
23039 #define RCC_CCIPR1_SPI1SEL_Msk              (0x3UL << RCC_CCIPR1_SPI1SEL_Pos)        /*!< 0x00300000 */
23040 #define RCC_CCIPR1_SPI1SEL                  RCC_CCIPR1_SPI1SEL_Msk                   /*!< SPI1SEL[1:0]: bits (SPI1 Kernel Clock Source Selection) */
23041 #define RCC_CCIPR1_SPI1SEL_0                (0x1UL << RCC_CCIPR1_SPI1SEL_Pos)        /*!< 0x00100000 */
23042 #define RCC_CCIPR1_SPI1SEL_1                (0x2UL << RCC_CCIPR1_SPI1SEL_Pos)        /*!< 0x00200000 */
23043 #define RCC_CCIPR1_SYSTICKSEL_Pos           (22U)
23044 #define RCC_CCIPR1_SYSTICKSEL_Msk           (0x3UL << RCC_CCIPR1_SYSTICKSEL_Pos)     /*!< 0x00C00000 */
23045 #define RCC_CCIPR1_SYSTICKSEL               RCC_CCIPR1_SYSTICKSEL_Msk                /*!< SYSTICKSEL[1:0]: bits (SYSTICK Clock Source Selection) */
23046 #define RCC_CCIPR1_SYSTICKSEL_0             (0x1UL << RCC_CCIPR1_SYSTICKSEL_Pos)     /*!< 0x00400000 */
23047 #define RCC_CCIPR1_SYSTICKSEL_1             (0x2UL << RCC_CCIPR1_SYSTICKSEL_Pos)     /*!< 0x00800000 */
23048 #define RCC_CCIPR1_FDCANSEL_Pos             (24U)
23049 #define RCC_CCIPR1_FDCANSEL_Msk             (0x3UL << RCC_CCIPR1_FDCANSEL_Pos)       /*!< 0x03000000 */
23050 #define RCC_CCIPR1_FDCANSEL                 RCC_CCIPR1_FDCANSEL_Msk                  /*!< FDCAN1SEL[1:0]: bits (FDCAN1 Kernel Clock Source Selection) */
23051 #define RCC_CCIPR1_FDCANSEL_0               (0x1UL << RCC_CCIPR1_FDCANSEL_Pos)       /*!< 0x01000000 */
23052 #define RCC_CCIPR1_FDCANSEL_1               (0x2UL << RCC_CCIPR1_FDCANSEL_Pos)       /*!< 0x02000000 */
23053 #define RCC_CCIPR1_ICLKSEL_Pos              (26U)
23054 #define RCC_CCIPR1_ICLKSEL_Msk              (0x3UL << RCC_CCIPR1_ICLKSEL_Pos)        /*!< 0x0C000000 */
23055 #define RCC_CCIPR1_ICLKSEL                  RCC_CCIPR1_ICLKSEL_Msk                   /*!< ICLKSEL[1:0]: bits (48 MHz Clock Source Selection) */
23056 #define RCC_CCIPR1_ICLKSEL_0                (0x1UL << RCC_CCIPR1_ICLKSEL_Pos)        /*!< 0x04000000 */
23057 #define RCC_CCIPR1_ICLKSEL_1                (0x2UL << RCC_CCIPR1_ICLKSEL_Pos)        /*!< 0x08000000 */
23058 #define RCC_CCIPR1_TIMICSEL_Pos             (29U)
23059 #define RCC_CCIPR1_TIMICSEL_Msk             (0x7UL << RCC_CCIPR1_TIMICSEL_Pos)       /*!< 0xE0000000 */
23060 #define RCC_CCIPR1_TIMICSEL                 RCC_CCIPR1_TIMICSEL_Msk                  /*!< TIMICSEL[2:0]: bits (Clocks Sources for TIM16,TIM17 and LPTIM2 Internal Input Capture) */
23061 #define RCC_CCIPR1_TIMICSEL_0               (0x1UL << RCC_CCIPR1_TIMICSEL_Pos)       /*!< 0x20000000 */
23062 #define RCC_CCIPR1_TIMICSEL_1               (0x2UL << RCC_CCIPR1_TIMICSEL_Pos)       /*!< 0x40000000 */
23063 #define RCC_CCIPR1_TIMICSEL_2               (0x4UL << RCC_CCIPR1_TIMICSEL_Pos)       /*!< 0x80000000 */
23064 
23065 /********************  Bit definition for RCC_CCIPR2 register  ******************/
23066 #define RCC_CCIPR2_MDF1SEL_Pos              (0U)
23067 #define RCC_CCIPR2_MDF1SEL_Msk              (0x7UL << RCC_CCIPR2_MDF1SEL_Pos)        /*!< 0x00000007 */
23068 #define RCC_CCIPR2_MDF1SEL                  RCC_CCIPR2_MDF1SEL_Msk                   /*!< MDF1SEL[2:0]: bits (MDF1 Kernel Clock Source Selection) */
23069 #define RCC_CCIPR2_MDF1SEL_0                (0x1UL << RCC_CCIPR2_MDF1SEL_Pos)        /*!< 0x00000001 */
23070 #define RCC_CCIPR2_MDF1SEL_1                (0x2UL << RCC_CCIPR2_MDF1SEL_Pos)        /*!< 0x00000002 */
23071 #define RCC_CCIPR2_MDF1SEL_2                (0x4UL << RCC_CCIPR2_MDF1SEL_Pos)        /*!< 0x00000004 */
23072 #define RCC_CCIPR2_SAI1SEL_Pos              (5U)
23073 #define RCC_CCIPR2_SAI1SEL_Msk              (0x7UL << RCC_CCIPR2_SAI1SEL_Pos)        /*!< 0x000000E0 */
23074 #define RCC_CCIPR2_SAI1SEL                  RCC_CCIPR2_SAI1SEL_Msk                   /*!< SAI1SEL[2:0]: bits (SAI1 Kernel Clock Source Selection) */
23075 #define RCC_CCIPR2_SAI1SEL_0                (0x1UL << RCC_CCIPR2_SAI1SEL_Pos)        /*!< 0x00000020 */
23076 #define RCC_CCIPR2_SAI1SEL_1                (0x2UL << RCC_CCIPR2_SAI1SEL_Pos)        /*!< 0x00000040 */
23077 #define RCC_CCIPR2_SAI1SEL_2                (0x4UL << RCC_CCIPR2_SAI1SEL_Pos)        /*!< 0x00000080 */
23078 #define RCC_CCIPR2_SAI2SEL_Pos              (8U)
23079 #define RCC_CCIPR2_SAI2SEL_Msk              (0x7UL << RCC_CCIPR2_SAI2SEL_Pos)        /*!< 0x00000700 */
23080 #define RCC_CCIPR2_SAI2SEL                  RCC_CCIPR2_SAI2SEL_Msk                   /*!< SAI2SEL[2:0]: bits (SAI2 Kernel Clock Source Selection) */
23081 #define RCC_CCIPR2_SAI2SEL_0                (0x1UL << RCC_CCIPR2_SAI2SEL_Pos)        /*!< 0x00000100 */
23082 #define RCC_CCIPR2_SAI2SEL_1                (0x2UL << RCC_CCIPR2_SAI2SEL_Pos)        /*!< 0x00000200 */
23083 #define RCC_CCIPR2_SAI2SEL_2                (0x4UL << RCC_CCIPR2_SAI2SEL_Pos)        /*!< 0x00000400 */
23084 #define RCC_CCIPR2_SAESSEL_Pos              (11U)
23085 #define RCC_CCIPR2_SAESSEL_Msk              (0x1UL << RCC_CCIPR2_SAESSEL_Pos)        /*!< 0x00004000 */
23086 #define RCC_CCIPR2_SAESSEL                  RCC_CCIPR2_SAESSEL_Msk                   /*!< SAES Kernel Clock Source Selection */
23087 #define RCC_CCIPR2_RNGSEL_Pos               (12U)
23088 #define RCC_CCIPR2_RNGSEL_Msk               (0x3UL << RCC_CCIPR2_RNGSEL_Pos)         /*!< 0x00300000 */
23089 #define RCC_CCIPR2_RNGSEL                   RCC_CCIPR2_RNGSEL_Msk                    /*!< RNGSEL[1:0]: bits (RNGSEL Kernel Clock Source Selection) */
23090 #define RCC_CCIPR2_RNGSEL_0                 (0x1UL << RCC_CCIPR2_RNGSEL_Pos)         /*!< 0x00100000 */
23091 #define RCC_CCIPR2_RNGSEL_1                 (0x2UL << RCC_CCIPR2_RNGSEL_Pos)         /*!< 0x00200000 */
23092 #define RCC_CCIPR2_SDMMCSEL_Pos             (14U)
23093 #define RCC_CCIPR2_SDMMCSEL_Msk             (0x1UL << RCC_CCIPR2_SDMMCSEL_Pos)       /*!< 0x00004000 */
23094 #define RCC_CCIPR2_SDMMCSEL                 RCC_CCIPR2_SDMMCSEL_Msk                  /*!< SDMMC1 Kernel Clock Source Selection */
23095 #define RCC_CCIPR2_DSIHOSTSEL_Pos           (15U)
23096 #define RCC_CCIPR2_DSIHOSTSEL_Msk           (0x1UL << RCC_CCIPR2_DSIHOSTSEL_Pos)     /*!< 0x00008000 */
23097 #define RCC_CCIPR2_DSIHOSTSEL               RCC_CCIPR2_DSIHOSTSEL_Msk                /*!< DSI Kernel Clock Source Selection */
23098 #define RCC_CCIPR2_USART6SEL_Pos            (16U)
23099 #define RCC_CCIPR2_USART6SEL_Msk            (0x3UL << RCC_CCIPR2_USART6SEL_Pos)      /*!< 0x00030000 */
23100 #define RCC_CCIPR2_USART6SEL                RCC_CCIPR2_USART6SEL_Msk                 /*!< USART6 Kernel Clock Source Selection */
23101 #define RCC_CCIPR2_USART6SEL_0              (0x1UL << RCC_CCIPR2_USART6SEL_Pos)      /*!< 0x00010000 */
23102 #define RCC_CCIPR2_USART6SEL_1              (0x2UL << RCC_CCIPR2_USART6SEL_Pos)      /*!< 0x00020000 */
23103 #define RCC_CCIPR2_LTDCSEL_Pos              (18U)
23104 #define RCC_CCIPR2_LTDCSEL_Msk              (0x1UL << RCC_CCIPR2_LTDCSEL_Pos)        /*!< 0x00040000 */
23105 #define RCC_CCIPR2_LTDCSEL                  RCC_CCIPR2_LTDCSEL_Msk                   /*!< LTDC Kernel Clock Source Selection */
23106 #define RCC_CCIPR2_OCTOSPISEL_Pos           (20U)
23107 #define RCC_CCIPR2_OCTOSPISEL_Msk           (0x3UL << RCC_CCIPR2_OCTOSPISEL_Pos)     /*!< 0x00300000 */
23108 #define RCC_CCIPR2_OCTOSPISEL               RCC_CCIPR2_OCTOSPISEL_Msk                /*!< OCTOSPISEL[1:0]: bits (OCTOSPI1 and OCTOSPI2 Kernel Clock Source Selection) */
23109 #define RCC_CCIPR2_OCTOSPISEL_0             (0x1UL << RCC_CCIPR2_OCTOSPISEL_Pos)     /*!< 0x00100000 */
23110 #define RCC_CCIPR2_OCTOSPISEL_1             (0x2UL << RCC_CCIPR2_OCTOSPISEL_Pos)     /*!< 0x00200000 */
23111 #define RCC_CCIPR2_HSPISEL_Pos              (22U)
23112 #define RCC_CCIPR2_HSPISEL_Msk              (0x3UL << RCC_CCIPR2_HSPISEL_Pos)        /*!< 0x00C00000 */
23113 #define RCC_CCIPR2_HSPISEL                  RCC_CCIPR2_HSPISEL_Msk                   /*!< HSPI1 Kernel Clock Source Selection */
23114 #define RCC_CCIPR2_HSPISEL_0                (0x1UL << RCC_CCIPR2_HSPISEL_Pos)        /*!< 0x00400000 */
23115 #define RCC_CCIPR2_HSPISEL_1                (0x2UL << RCC_CCIPR2_HSPISEL_Pos)        /*!< 0x00800000 */
23116 #define RCC_CCIPR2_I2C5SEL_Pos              (24U)
23117 #define RCC_CCIPR2_I2C5SEL_Msk              (0x3UL << RCC_CCIPR2_I2C5SEL_Pos)        /*!< 0x03000000 */
23118 #define RCC_CCIPR2_I2C5SEL                  RCC_CCIPR2_I2C5SEL_Msk                   /*!< I2C5 Kernel Clock Source Selection */
23119 #define RCC_CCIPR2_I2C5SEL_0                (0x1UL << RCC_CCIPR2_I2C5SEL_Pos)        /*!< 0x01000000 */
23120 #define RCC_CCIPR2_I2C5SEL_1                (0x2UL << RCC_CCIPR2_I2C5SEL_Pos)        /*!< 0x02000000 */
23121 #define RCC_CCIPR2_I2C6SEL_Pos              (26U)
23122 #define RCC_CCIPR2_I2C6SEL_Msk              (0x3UL << RCC_CCIPR2_I2C6SEL_Pos)        /*!< 0x0C000000 */
23123 #define RCC_CCIPR2_I2C6SEL                  RCC_CCIPR2_I2C6SEL_Msk                   /*!< I2C6 Kernel Clock Source Selection */
23124 #define RCC_CCIPR2_I2C6SEL_0                (0x1UL << RCC_CCIPR2_I2C6SEL_Pos)        /*!< 0x04000000 */
23125 #define RCC_CCIPR2_I2C6SEL_1                (0x2UL << RCC_CCIPR2_I2C6SEL_Pos)        /*!< 0x08000000 */
23126 #define RCC_CCIPR2_USBPHYCSEL_Pos           (30U)
23127 #define RCC_CCIPR2_USBPHYCSEL_Msk           (0x3UL << RCC_CCIPR2_USBPHYCSEL_Pos)     /*!< 0xC0000000 */
23128 #define RCC_CCIPR2_USBPHYCSEL               RCC_CCIPR2_USBPHYCSEL_Msk                /*!< OTG Kernel Clock Source Selection */
23129 #define RCC_CCIPR2_USBPHYCSEL_0             (0x1UL << RCC_CCIPR2_USBPHYCSEL_Pos)     /*!< 0x40000000 */
23130 #define RCC_CCIPR2_USBPHYCSEL_1             (0x2UL << RCC_CCIPR2_USBPHYCSEL_Pos)     /*!< 0x80000000 */
23131 
23132 /********************  Bit definition for RCC_CCIPR3 register  ***************/
23133 #define RCC_CCIPR3_LPUART1SEL_Pos           (0U)
23134 #define RCC_CCIPR3_LPUART1SEL_Msk           (0x7UL << RCC_CCIPR3_LPUART1SEL_Pos)     /*!< 0x00000007 */
23135 #define RCC_CCIPR3_LPUART1SEL               RCC_CCIPR3_LPUART1SEL_Msk                /*!< LPUART1SEL[2:0]: bits (LPUART1 Kernel Clock Source Selection) */
23136 #define RCC_CCIPR3_LPUART1SEL_0             (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos)     /*!< 0x00000001 */
23137 #define RCC_CCIPR3_LPUART1SEL_1             (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos)     /*!< 0x00000002 */
23138 #define RCC_CCIPR3_LPUART1SEL_2             (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos)     /*!< 0x00000004 */
23139 #define RCC_CCIPR3_SPI3SEL_Pos              (3U)
23140 #define RCC_CCIPR3_SPI3SEL_Msk              (0x3UL << RCC_CCIPR3_SPI3SEL_Pos)        /*!< 0x00000008 */
23141 #define RCC_CCIPR3_SPI3SEL                  RCC_CCIPR3_SPI3SEL_Msk                   /*!< SPI3SEL[1:0]: bits (SPI3 Kernel Clock Source Selection) */
23142 #define RCC_CCIPR3_SPI3SEL_0                (0x1UL << RCC_CCIPR3_SPI3SEL_Pos)        /*!< 0x00000008 */
23143 #define RCC_CCIPR3_SPI3SEL_1                (0x2UL << RCC_CCIPR3_SPI3SEL_Pos)        /*!< 0x00000010 */
23144 #define RCC_CCIPR3_I2C3SEL_Pos              (6U)
23145 #define RCC_CCIPR3_I2C3SEL_Msk              (0x3UL << RCC_CCIPR3_I2C3SEL_Pos)        /*!< 0x00000300 */
23146 #define RCC_CCIPR3_I2C3SEL                  RCC_CCIPR3_I2C3SEL_Msk                   /*!< I2C3SEL[1:0]: bits (I2C3 Kernel Clock Source Selection) */
23147 #define RCC_CCIPR3_I2C3SEL_0                (0x1UL << RCC_CCIPR3_I2C3SEL_Pos)        /*!< 0x00000100 */
23148 #define RCC_CCIPR3_I2C3SEL_1                (0x2UL << RCC_CCIPR3_I2C3SEL_Pos)        /*!< 0x00000200 */
23149 #define RCC_CCIPR3_LPTIM34SEL_Pos           (8U)
23150 #define RCC_CCIPR3_LPTIM34SEL_Msk           (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos)     /*!< 0x0000E000 */
23151 #define RCC_CCIPR3_LPTIM34SEL               RCC_CCIPR3_LPTIM34SEL_Msk                /*!< LPTIM34SEL[1:0]: bits (LPTIM3 and LPTIM4 Kernel Clock Source Selection) */
23152 #define RCC_CCIPR3_LPTIM34SEL_0             (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos)     /*!< 0x00002000 */
23153 #define RCC_CCIPR3_LPTIM34SEL_1             (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos)     /*!< 0x00004000 */
23154 #define RCC_CCIPR3_LPTIM1SEL_Pos            (10U)
23155 #define RCC_CCIPR3_LPTIM1SEL_Msk            (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos)      /*!< 0x0000E000 */
23156 #define RCC_CCIPR3_LPTIM1SEL                RCC_CCIPR3_LPTIM1SEL_Msk                 /*!< LPTIM1SEL[1:0]: bits (LPTIM1 Kernel Clock Source Selection) */
23157 #define RCC_CCIPR3_LPTIM1SEL_0              (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos)      /*!< 0x00002000 */
23158 #define RCC_CCIPR3_LPTIM1SEL_1              (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos)      /*!< 0x00004000 */
23159 #define RCC_CCIPR3_ADCDACSEL_Pos            (12U)
23160 #define RCC_CCIPR3_ADCDACSEL_Msk            (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos)      /*!< 0x00030000 */
23161 #define RCC_CCIPR3_ADCDACSEL                RCC_CCIPR3_ADCDACSEL_Msk                 /*!< ADCDACSEL[2:0]: bits (ADC1, ADC4 and DAC1 Kernel Clock Source Selection) */
23162 #define RCC_CCIPR3_ADCDACSEL_0              (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos)      /*!< 0x00010000 */
23163 #define RCC_CCIPR3_ADCDACSEL_1              (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos)      /*!< 0x00020000 */
23164 #define RCC_CCIPR3_ADCDACSEL_2              (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos)      /*!< 0x00040000 */
23165 #define RCC_CCIPR3_DAC1SEL_Pos              (15U)
23166 #define RCC_CCIPR3_DAC1SEL_Msk              (0x1UL << RCC_CCIPR3_DAC1SEL_Pos)        /*!< 0x00300000 */
23167 #define RCC_CCIPR3_DAC1SEL                  RCC_CCIPR3_DAC1SEL_Msk                   /*!< DAC1 Sample & Hold Clock Source Selection */
23168 #define RCC_CCIPR3_ADF1SEL_Pos              (16U)
23169 #define RCC_CCIPR3_ADF1SEL_Msk              (0x7UL << RCC_CCIPR3_ADF1SEL_Pos)       /*!< 0x00070000 */
23170 #define RCC_CCIPR3_ADF1SEL                  RCC_CCIPR3_ADF1SEL_Msk                  /*!< ADF1SEL[2:0]: bits (ADF1 Kernel Clock Source Selection) */
23171 #define RCC_CCIPR3_ADF1SEL_0                (0x1UL << RCC_CCIPR3_ADF1SEL_Pos)       /*!< 0x00010000 */
23172 #define RCC_CCIPR3_ADF1SEL_1                (0x2UL << RCC_CCIPR3_ADF1SEL_Pos)       /*!< 0x00020000 */
23173 #define RCC_CCIPR3_ADF1SEL_2                (0x4UL << RCC_CCIPR3_ADF1SEL_Pos)       /*!< 0x00040000 */
23174 
23175 /********************  Bit definition for RCC_BDCR register  ******************/
23176 #define RCC_BDCR_LSEON_Pos                  (0U)
23177 #define RCC_BDCR_LSEON_Msk                  (0x1UL << RCC_BDCR_LSEON_Pos)           /*!< 0x00000001 */
23178 #define RCC_BDCR_LSEON                      RCC_BDCR_LSEON_Msk                      /*!< LSE Oscillator Enable */
23179 #define RCC_BDCR_LSERDY_Pos                 (1U)
23180 #define RCC_BDCR_LSERDY_Msk                 (0x1UL << RCC_BDCR_LSERDY_Pos)          /*!< 0x00000002 */
23181 #define RCC_BDCR_LSERDY                     RCC_BDCR_LSERDY_Msk                     /*!< LSE Oscillator Ready */
23182 #define RCC_BDCR_LSEBYP_Pos                 (2U)
23183 #define RCC_BDCR_LSEBYP_Msk                 (0x1UL << RCC_BDCR_LSEBYP_Pos)          /*!< 0x00000004 */
23184 #define RCC_BDCR_LSEBYP                     RCC_BDCR_LSEBYP_Msk                     /*!< LSE Oscillator Bypass */
23185 #define RCC_BDCR_LSEDRV_Pos                 (3U)
23186 #define RCC_BDCR_LSEDRV_Msk                 (0x3UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000018 */
23187 #define RCC_BDCR_LSEDRV                     RCC_BDCR_LSEDRV_Msk                     /*!< LSEDRV[1:0]: bits (LSE Oscillator Drive Capability) */
23188 #define RCC_BDCR_LSEDRV_0                   (0x1UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000008 */
23189 #define RCC_BDCR_LSEDRV_1                   (0x2UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000010 */
23190 #define RCC_BDCR_LSECSSON_Pos               (5U)
23191 #define RCC_BDCR_LSECSSON_Msk               (0x1UL << RCC_BDCR_LSECSSON_Pos)        /*!< 0x00000020 */
23192 #define RCC_BDCR_LSECSSON                   RCC_BDCR_LSECSSON_Msk                   /*!< CSS on LSE Enable */
23193 #define RCC_BDCR_LSECSSD_Pos                (6U)
23194 #define RCC_BDCR_LSECSSD_Msk                (0x1UL << RCC_BDCR_LSECSSD_Pos)         /*!< 0x00000040 */
23195 #define RCC_BDCR_LSECSSD                    RCC_BDCR_LSECSSD_Msk                    /*!< CSS on LSE failure Detection */
23196 #define RCC_BDCR_LSESYSEN_Pos               (7U)
23197 #define RCC_BDCR_LSESYSEN_Msk               (0x1UL << RCC_BDCR_LSESYSEN_Pos)        /*!< 0x00000080 */
23198 #define RCC_BDCR_LSESYSEN                   RCC_BDCR_LSESYSEN_Msk                   /*!< LSE System Clock (LSESYS) Enable */
23199 #define RCC_BDCR_RTCSEL_Pos                 (8U)
23200 #define RCC_BDCR_RTCSEL_Msk                 (0x3UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000300 */
23201 #define RCC_BDCR_RTCSEL                     RCC_BDCR_RTCSEL_Msk                     /*!< RTCSEL[1:0]: bits (RTC Clock Source Selection) */
23202 #define RCC_BDCR_RTCSEL_0                   (0x1UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000100 */
23203 #define RCC_BDCR_RTCSEL_1                   (0x2UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000200 */
23204 #define RCC_BDCR_LSESYSRDY_Pos              (11U)
23205 #define RCC_BDCR_LSESYSRDY_Msk              (0x1UL << RCC_BDCR_LSESYSRDY_Pos)       /*!< 0x00000800 */
23206 #define RCC_BDCR_LSESYSRDY                  RCC_BDCR_LSESYSRDY_Msk                  /*!< LSE System Clock (LSESYS) Ready */
23207 #define RCC_BDCR_LSEGFON_Pos                (12U)
23208 #define RCC_BDCR_LSEGFON_Msk                (0x1UL << RCC_BDCR_LSEGFON_Pos)         /*!< 0x00001000 */
23209 #define RCC_BDCR_LSEGFON                    RCC_BDCR_LSEGFON_Msk                    /*!< LSE Clock Glitch Filter Enable */
23210 #define RCC_BDCR_RTCEN_Pos                  (15U)
23211 #define RCC_BDCR_RTCEN_Msk                  (0x1UL << RCC_BDCR_RTCEN_Pos)           /*!< 0x00008000 */
23212 #define RCC_BDCR_RTCEN                      RCC_BDCR_RTCEN_Msk                      /*!< RTC Clock Enable */
23213 #define RCC_BDCR_BDRST_Pos                  (16U)
23214 #define RCC_BDCR_BDRST_Msk                  (0x1UL << RCC_BDCR_BDRST_Pos)           /*!< 0x00010000 */
23215 #define RCC_BDCR_BDRST                      RCC_BDCR_BDRST_Msk                      /*!< Backup Domain Software Reset */
23216 #define RCC_BDCR_LSCOEN_Pos                 (24U)
23217 #define RCC_BDCR_LSCOEN_Msk                 (0x1UL << RCC_BDCR_LSCOEN_Pos)          /*!< 0x01000000 */
23218 #define RCC_BDCR_LSCOEN                     RCC_BDCR_LSCOEN_Msk                     /*!< Low-speed Clock Output (LSCO) Enable */
23219 #define RCC_BDCR_LSCOSEL_Pos                (25U)
23220 #define RCC_BDCR_LSCOSEL_Msk                (0x1UL << RCC_BDCR_LSCOSEL_Pos)         /*!< 0x02000000 */
23221 #define RCC_BDCR_LSCOSEL                    RCC_BDCR_LSCOSEL_Msk                    /*!< Low-speed Clock Output Selection */
23222 #define RCC_BDCR_LSION_Pos                  (26U)
23223 #define RCC_BDCR_LSION_Msk                  (0x1UL << RCC_BDCR_LSION_Pos)           /*!< 0x00010000 */
23224 #define RCC_BDCR_LSION                      RCC_BDCR_LSION_Msk                      /*!< LSI Oscillator Enable */
23225 #define RCC_BDCR_LSIRDY_Pos                 (27U)
23226 #define RCC_BDCR_LSIRDY_Msk                 (0x1UL << RCC_BDCR_LSIRDY_Pos)          /*!< 0x01000000 */
23227 #define RCC_BDCR_LSIRDY                     RCC_BDCR_LSIRDY_Msk                     /*!< LSI Oscillator Ready */
23228 #define RCC_BDCR_LSIPREDIV_Pos              (28U)
23229 #define RCC_BDCR_LSIPREDIV_Msk              (0x1UL << RCC_BDCR_LSIPREDIV_Pos)       /*!< 0x02000000 */
23230 #define RCC_BDCR_LSIPREDIV                  RCC_BDCR_LSIPREDIV_Msk                  /*!< Low-speed Clock Divider Configuration */
23231 
23232 /********************  Bit definition for RCC_CSR register  *******************/
23233 #define RCC_CSR_MSIKSRANGE_Pos              (8U)
23234 #define RCC_CSR_MSIKSRANGE_Msk              (0xFUL << RCC_CSR_MSIKSRANGE_Pos)       /*!< 0x00000F00 */
23235 #define RCC_CSR_MSIKSRANGE                  RCC_CSR_MSIKSRANGE_Msk                  /*!< MSIKSRANGE[3:0]:bits (MSIK Range After Standby Mode) */
23236 #define RCC_CSR_MSIKSRANGE_0                (0x1UL << RCC_CSR_MSIKSRANGE_Pos)       /*!< 0x00000100 */
23237 #define RCC_CSR_MSIKSRANGE_1                (0x2UL << RCC_CSR_MSIKSRANGE_Pos)       /*!< 0x00000200 */
23238 #define RCC_CSR_MSIKSRANGE_2                (0x4UL << RCC_CSR_MSIKSRANGE_Pos)       /*!< 0x00000400 */
23239 #define RCC_CSR_MSIKSRANGE_3                (0x8UL << RCC_CSR_MSIKSRANGE_Pos)       /*!< 0x00000800 */
23240 #define RCC_CSR_MSISSRANGE_Pos              (12U)
23241 #define RCC_CSR_MSISSRANGE_Msk              (0xFUL << RCC_CSR_MSISSRANGE_Pos)       /*!< 0x0000F000 */
23242 #define RCC_CSR_MSISSRANGE                  RCC_CSR_MSISSRANGE_Msk                  /*!< MSISSRANGE[3:0]:bits (MSIS Range After Standby Mode) */
23243 #define RCC_CSR_MSISSRANGE_0                (0x1UL << RCC_CSR_MSISSRANGE_Pos)       /*!< 0x00001000 */
23244 #define RCC_CSR_MSISSRANGE_1                (0x2UL << RCC_CSR_MSISSRANGE_Pos)       /*!< 0x00002000 */
23245 #define RCC_CSR_MSISSRANGE_2                (0x4UL << RCC_CSR_MSISSRANGE_Pos)       /*!< 0x00004000 */
23246 #define RCC_CSR_MSISSRANGE_3                (0x8UL << RCC_CSR_MSISSRANGE_Pos)       /*!< 0x00008000 */
23247 #define RCC_CSR_RMVF_Pos                    (23U)
23248 #define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)             /*!< 0x00800000 */
23249 #define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                        /*!< Remove Reset Flag */
23250 #define RCC_CSR_OBLRSTF_Pos                 (25U)
23251 #define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)          /*!< 0x02000000 */
23252 #define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                     /*!< Option Byte Loader Reset Flag */
23253 #define RCC_CSR_PINRSTF_Pos                 (26U)
23254 #define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)          /*!< 0x04000000 */
23255 #define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                     /*!< NRST Pin Reset Flag */
23256 #define RCC_CSR_BORRSTF_Pos                 (27U)
23257 #define RCC_CSR_BORRSTF_Msk                 (0x1UL << RCC_CSR_BORRSTF_Pos)          /*!< 0x08000000 */
23258 #define RCC_CSR_BORRSTF                     RCC_CSR_BORRSTF_Msk                     /*!< BOR Flag */
23259 #define RCC_CSR_SFTRSTF_Pos                 (28U)
23260 #define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)          /*!< 0x10000000 */
23261 #define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                     /*!< Software Reset Flag */
23262 #define RCC_CSR_IWDGRSTF_Pos                (29U)
23263 #define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)         /*!< 0x20000000 */
23264 #define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk                    /*!< Independent Watchdog Reset Flag */
23265 #define RCC_CSR_WWDGRSTF_Pos                (30U)
23266 #define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)         /*!< 0x40000000 */
23267 #define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk                    /*!< Window Watchdog Reset Flag */
23268 #define RCC_CSR_LPWRRSTF_Pos                (31U)
23269 #define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)         /*!< 0x80000000 */
23270 #define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk                    /*!< Low-power Reset Flag */
23271 
23272 /********************  Bit definition for RCC_SECCFGR register  **************/
23273 #define RCC_SECCFGR_HSISEC_Pos              (0U)
23274 #define RCC_SECCFGR_HSISEC_Msk              (0x1UL << RCC_SECCFGR_HSISEC_Pos)       /*!< 0x00000001 */
23275 #define RCC_SECCFGR_HSISEC                  RCC_SECCFGR_HSISEC_Msk                  /*!< HSI Clock Configuration and Status Bits Security */
23276 #define RCC_SECCFGR_HSESEC_Pos              (1U)
23277 #define RCC_SECCFGR_HSESEC_Msk              (0x1UL << RCC_SECCFGR_HSESEC_Pos)       /*!< 0x00000002 */
23278 #define RCC_SECCFGR_HSESEC                  RCC_SECCFGR_HSESEC_Msk                  /*!< HSE Clock Configuration Bits, Status Bits and HSE_CSS Security */
23279 #define RCC_SECCFGR_MSISEC_Pos              (2U)
23280 #define RCC_SECCFGR_MSISEC_Msk              (0x1UL << RCC_SECCFGR_MSISEC_Pos)       /*!< 0x00000004 */
23281 #define RCC_SECCFGR_MSISEC                  RCC_SECCFGR_MSISEC_Msk                  /*!< MSI Clock Configuration and Status Bits Security */
23282 #define RCC_SECCFGR_LSISEC_Pos              (3U)
23283 #define RCC_SECCFGR_LSISEC_Msk              (0x1UL << RCC_SECCFGR_LSISEC_Pos)       /*!< 0x00000008 */
23284 #define RCC_SECCFGR_LSISEC                  RCC_SECCFGR_LSISEC_Msk                  /*!< LSI Clock Configuration and Status Bits Security */
23285 #define RCC_SECCFGR_LSESEC_Pos              (4U)
23286 #define RCC_SECCFGR_LSESEC_Msk              (0x1UL << RCC_SECCFGR_LSESEC_Pos)       /*!< 0x00000010 */
23287 #define RCC_SECCFGR_LSESEC                  RCC_SECCFGR_LSESEC_Msk                  /*!< LSE Clock Configuration and Status Bits Security */
23288 #define RCC_SECCFGR_SYSCLKSEC_Pos           (5U)
23289 #define RCC_SECCFGR_SYSCLKSEC_Msk           (0x1UL << RCC_SECCFGR_SYSCLKSEC_Pos)    /*!< 0x00000020 */
23290 #define RCC_SECCFGR_SYSCLKSEC               RCC_SECCFGR_SYSCLKSEC_Msk               /*!< SYSCLK Clock Selection, STOPWUCK bit, Clock Output on MCO Configuration Security */
23291 #define RCC_SECCFGR_PRESCSEC_Pos            (6U)
23292 #define RCC_SECCFGR_PRESCSEC_Msk            (0x1UL << RCC_SECCFGR_PRESCSEC_Pos)     /*!< 0x00000040 */
23293 #define RCC_SECCFGR_PRESCSEC                RCC_SECCFGR_PRESCSEC_Msk                /*!< AHBx/APBx Prescaler Configuration Bits Security */
23294 #define RCC_SECCFGR_PLL1SEC_Pos             (7U)
23295 #define RCC_SECCFGR_PLL1SEC_Msk             (0x1UL << RCC_SECCFGR_PLL1SEC_Pos)      /*!< 0x00000080 */
23296 #define RCC_SECCFGR_PLL1SEC                 RCC_SECCFGR_PLL1SEC_Msk                 /*!< PLL1 Clock Configuration and Status Bits Security */
23297 #define RCC_SECCFGR_PLL2SEC_Pos             (8U)
23298 #define RCC_SECCFGR_PLL2SEC_Msk             (0x1UL << RCC_SECCFGR_PLL2SEC_Pos)      /*!< 0x00000100 */
23299 #define RCC_SECCFGR_PLL2SEC                 RCC_SECCFGR_PLL2SEC_Msk                 /*!< PLL2 Clock Configuration and Status Bits Security */
23300 #define RCC_SECCFGR_PLL3SEC_Pos             (9U)
23301 #define RCC_SECCFGR_PLL3SEC_Msk             (0x1UL << RCC_SECCFGR_PLL3SEC_Pos)      /*!< 0x00000200 */
23302 #define RCC_SECCFGR_PLL3SEC                 RCC_SECCFGR_PLL3SEC_Msk                 /*!< PLL3 Clock Configuration and Status Bits Security */
23303 #define RCC_SECCFGR_ICLKSEC_Pos             (10U)
23304 #define RCC_SECCFGR_ICLKSEC_Msk             (0x1UL << RCC_SECCFGR_ICLKSEC_Pos)    /*!< 0x00000400 */
23305 #define RCC_SECCFGR_ICLKSEC                 RCC_SECCFGR_ICLKSEC_Msk               /*!< 48 MHz Clock Source Selection Security */
23306 #define RCC_SECCFGR_HSI48SEC_Pos            (11U)
23307 #define RCC_SECCFGR_HSI48SEC_Msk            (0x1UL << RCC_SECCFGR_HSI48SEC_Pos)     /*!< 0x00000800 */
23308 #define RCC_SECCFGR_HSI48SEC                RCC_SECCFGR_HSI48SEC_Msk                /*!< HSI48 Clock Configuration and Status Bits Security */
23309 #define RCC_SECCFGR_RMVFSEC_Pos             (12U)
23310 #define RCC_SECCFGR_RMVFSEC_Msk             (0x1UL << RCC_SECCFGR_RMVFSEC_Pos)      /*!< 0x00001000 */
23311 #define RCC_SECCFGR_RMVFSEC                 RCC_SECCFGR_RMVFSEC_Msk                 /*!< Remove Reset Flag Security */
23312 
23313 /********************  Bit definition for RCC_PRIVCFGR register  **************/
23314 #define RCC_PRIVCFGR_SPRIV_Pos              (0U)
23315 #define RCC_PRIVCFGR_SPRIV_Msk              (0x1UL << RCC_PRIVCFGR_SPRIV_Pos)       /*!< 0x00000001 */
23316 #define RCC_PRIVCFGR_SPRIV                  RCC_PRIVCFGR_SPRIV_Msk                  /*!< RCC Secure Functions Privilege Configuration */
23317 #define RCC_PRIVCFGR_NSPRIV_Pos             (1U)
23318 #define RCC_PRIVCFGR_NSPRIV_Msk             (0x1UL << RCC_PRIVCFGR_NSPRIV_Pos)      /*!< 0x00000002 */
23319 #define RCC_PRIVCFGR_NSPRIV                 RCC_PRIVCFGR_NSPRIV_Msk                 /*!< RCC Non-Secure Functions Privilege Configuration */
23320 
23321 /******************************************************************************/
23322 /*                                                                            */
23323 /*                           Real-Time Clock (RTC)                            */
23324 /*                                                                            */
23325 /******************************************************************************/
23326 /********************  Bits definition for RTC_TR register  *******************/
23327 #define RTC_TR_SU_Pos                       (0U)
23328 #define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
23329 #define RTC_TR_SU                           RTC_TR_SU_Msk
23330 #define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
23331 #define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
23332 #define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
23333 #define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
23334 #define RTC_TR_ST_Pos                       (4U)
23335 #define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
23336 #define RTC_TR_ST                           RTC_TR_ST_Msk
23337 #define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
23338 #define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
23339 #define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
23340 #define RTC_TR_MNU_Pos                      (8U)
23341 #define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
23342 #define RTC_TR_MNU                          RTC_TR_MNU_Msk
23343 #define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
23344 #define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
23345 #define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
23346 #define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
23347 #define RTC_TR_MNT_Pos                      (12U)
23348 #define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
23349 #define RTC_TR_MNT                          RTC_TR_MNT_Msk
23350 #define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
23351 #define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
23352 #define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
23353 #define RTC_TR_HU_Pos                       (16U)
23354 #define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
23355 #define RTC_TR_HU                           RTC_TR_HU_Msk
23356 #define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
23357 #define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
23358 #define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
23359 #define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
23360 #define RTC_TR_HT_Pos                       (20U)
23361 #define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
23362 #define RTC_TR_HT                           RTC_TR_HT_Msk
23363 #define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
23364 #define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
23365 #define RTC_TR_PM_Pos                       (22U)
23366 #define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
23367 #define RTC_TR_PM                           RTC_TR_PM_Msk
23368 
23369 /********************  Bits definition for RTC_DR register  *******************/
23370 #define RTC_DR_DU_Pos                       (0U)
23371 #define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
23372 #define RTC_DR_DU                           RTC_DR_DU_Msk
23373 #define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
23374 #define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
23375 #define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
23376 #define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
23377 #define RTC_DR_DT_Pos                       (4U)
23378 #define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
23379 #define RTC_DR_DT                           RTC_DR_DT_Msk
23380 #define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
23381 #define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
23382 #define RTC_DR_MU_Pos                       (8U)
23383 #define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
23384 #define RTC_DR_MU                           RTC_DR_MU_Msk
23385 #define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
23386 #define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
23387 #define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
23388 #define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
23389 #define RTC_DR_MT_Pos                       (12U)
23390 #define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
23391 #define RTC_DR_MT                           RTC_DR_MT_Msk
23392 #define RTC_DR_WDU_Pos                      (13U)
23393 #define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
23394 #define RTC_DR_WDU                          RTC_DR_WDU_Msk
23395 #define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
23396 #define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
23397 #define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
23398 #define RTC_DR_YU_Pos                       (16U)
23399 #define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
23400 #define RTC_DR_YU                           RTC_DR_YU_Msk
23401 #define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
23402 #define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
23403 #define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
23404 #define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
23405 #define RTC_DR_YT_Pos                       (20U)
23406 #define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
23407 #define RTC_DR_YT                           RTC_DR_YT_Msk
23408 #define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
23409 #define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
23410 #define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
23411 #define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */
23412 
23413 /********************  Bits definition for RTC_SSR register  ******************/
23414 #define RTC_SSR_SS_Pos                      (0U)
23415 #define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
23416 #define RTC_SSR_SS                          RTC_SSR_SS_Msk
23417 
23418 /********************  Bits definition for RTC_ICSR register  ******************/
23419 #define RTC_ICSR_WUTWF_Pos                  (2U)
23420 #define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
23421 #define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
23422 #define RTC_ICSR_SHPF_Pos                   (3U)
23423 #define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
23424 #define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
23425 #define RTC_ICSR_INITS_Pos                  (4U)
23426 #define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
23427 #define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
23428 #define RTC_ICSR_RSF_Pos                    (5U)
23429 #define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
23430 #define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
23431 #define RTC_ICSR_INITF_Pos                  (6U)
23432 #define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
23433 #define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
23434 #define RTC_ICSR_INIT_Pos                   (7U)
23435 #define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
23436 #define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
23437 #define RTC_ICSR_BIN_Pos                    (8U)
23438 #define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
23439 #define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
23440 #define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
23441 #define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
23442 #define RTC_ICSR_BCDU_Pos                   (10U)
23443 #define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
23444 #define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
23445 #define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
23446 #define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
23447 #define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
23448 #define RTC_ICSR_RECALPF_Pos                (16U)
23449 #define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
23450 #define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk
23451 
23452 /********************  Bits definition for RTC_PRER register  *****************/
23453 #define RTC_PRER_PREDIV_S_Pos               (0U)
23454 #define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
23455 #define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
23456 #define RTC_PRER_PREDIV_A_Pos               (16U)
23457 #define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
23458 #define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk
23459 
23460 /********************  Bits definition for RTC_WUTR register  *****************/
23461 #define RTC_WUTR_WUT_Pos                    (0U)
23462 #define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
23463 #define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
23464 #define RTC_WUTR_WUTOCLR_Pos                (16U)
23465 #define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
23466 #define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk
23467 
23468 /********************  Bits definition for RTC_CR register  *******************/
23469 #define RTC_CR_WUCKSEL_Pos                  (0U)
23470 #define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
23471 #define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
23472 #define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
23473 #define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
23474 #define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
23475 #define RTC_CR_TSEDGE_Pos                   (3U)
23476 #define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
23477 #define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
23478 #define RTC_CR_REFCKON_Pos                  (4U)
23479 #define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
23480 #define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
23481 #define RTC_CR_BYPSHAD_Pos                  (5U)
23482 #define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
23483 #define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
23484 #define RTC_CR_FMT_Pos                      (6U)
23485 #define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
23486 #define RTC_CR_FMT                          RTC_CR_FMT_Msk
23487 #define RTC_CR_SSRUIE_Pos                   (7U)
23488 #define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
23489 #define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
23490 #define RTC_CR_ALRAE_Pos                    (8U)
23491 #define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
23492 #define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
23493 #define RTC_CR_ALRBE_Pos                    (9U)
23494 #define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
23495 #define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
23496 #define RTC_CR_WUTE_Pos                     (10U)
23497 #define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
23498 #define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
23499 #define RTC_CR_TSE_Pos                      (11U)
23500 #define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
23501 #define RTC_CR_TSE                          RTC_CR_TSE_Msk
23502 #define RTC_CR_ALRAIE_Pos                   (12U)
23503 #define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
23504 #define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
23505 #define RTC_CR_ALRBIE_Pos                   (13U)
23506 #define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
23507 #define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
23508 #define RTC_CR_WUTIE_Pos                    (14U)
23509 #define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
23510 #define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
23511 #define RTC_CR_TSIE_Pos                     (15U)
23512 #define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
23513 #define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
23514 #define RTC_CR_ADD1H_Pos                    (16U)
23515 #define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
23516 #define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
23517 #define RTC_CR_SUB1H_Pos                    (17U)
23518 #define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
23519 #define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
23520 #define RTC_CR_BKP_Pos                      (18U)
23521 #define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
23522 #define RTC_CR_BKP                          RTC_CR_BKP_Msk
23523 #define RTC_CR_COSEL_Pos                    (19U)
23524 #define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
23525 #define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
23526 #define RTC_CR_POL_Pos                      (20U)
23527 #define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
23528 #define RTC_CR_POL                          RTC_CR_POL_Msk
23529 #define RTC_CR_OSEL_Pos                     (21U)
23530 #define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
23531 #define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
23532 #define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
23533 #define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
23534 #define RTC_CR_COE_Pos                      (23U)
23535 #define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
23536 #define RTC_CR_COE                          RTC_CR_COE_Msk
23537 #define RTC_CR_ITSE_Pos                     (24U)
23538 #define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
23539 #define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
23540 #define RTC_CR_TAMPTS_Pos                   (25U)
23541 #define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
23542 #define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
23543 #define RTC_CR_TAMPOE_Pos                   (26U)
23544 #define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
23545 #define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
23546 #define RTC_CR_ALRAFCLR_Pos                 (27U)
23547 #define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
23548 #define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
23549 #define RTC_CR_ALRBFCLR_Pos                 (28U)
23550 #define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
23551 #define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
23552 #define RTC_CR_TAMPALRM_PU_Pos              (29U)
23553 #define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
23554 #define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
23555 #define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
23556 #define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
23557 #define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
23558 #define RTC_CR_OUT2EN_Pos                   (31U)
23559 #define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
23560 #define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */
23561 
23562 /********************  Bits definition for RTC_PRIVCFGR register  *****************/
23563 #define RTC_PRIVCFGR_ALRAPRIV_Pos           (0U)
23564 #define RTC_PRIVCFGR_ALRAPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos)    /*!< 0x00000001 */
23565 #define RTC_PRIVCFGR_ALRAPRIV               RTC_PRIVCFGR_ALRAPRIV_Msk
23566 #define RTC_PRIVCFGR_ALRBPRIV_Pos           (1U)
23567 #define RTC_PRIVCFGR_ALRBPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos)    /*!< 0x00000002 */
23568 #define RTC_PRIVCFGR_ALRBPRIV               RTC_PRIVCFGR_ALRBPRIV_Msk
23569 #define RTC_PRIVCFGR_WUTPRIV_Pos            (2U)
23570 #define RTC_PRIVCFGR_WUTPRIV_Msk            (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos)     /*!< 0x00000004 */
23571 #define RTC_PRIVCFGR_WUTPRIV                RTC_PRIVCFGR_WUTPRIV_Msk
23572 #define RTC_PRIVCFGR_TSPRIV_Pos             (3U)
23573 #define RTC_PRIVCFGR_TSPRIV_Msk             (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos)      /*!< 0x00000008 */
23574 #define RTC_PRIVCFGR_TSPRIV                 RTC_PRIVCFGR_TSPRIV_Msk
23575 #define RTC_PRIVCFGR_CALPRIV_Pos            (13U)
23576 #define RTC_PRIVCFGR_CALPRIV_Msk            (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos)     /*!< 0x00002000 */
23577 #define RTC_PRIVCFGR_CALPRIV                RTC_PRIVCFGR_CALPRIV_Msk
23578 #define RTC_PRIVCFGR_INITPRIV_Pos           (14U)
23579 #define RTC_PRIVCFGR_INITPRIV_Msk           (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos)    /*!< 0x00004000 */
23580 #define RTC_PRIVCFGR_INITPRIV               RTC_PRIVCFGR_INITPRIV_Msk
23581 #define RTC_PRIVCFGR_PRIV_Pos               (15U)
23582 #define RTC_PRIVCFGR_PRIV_Msk               (0x1UL << RTC_PRIVCFGR_PRIV_Pos)        /*!< 0x00008000 */
23583 #define RTC_PRIVCFGR_PRIV                   RTC_PRIVCFGR_PRIV_Msk
23584 
23585 /********************  Bits definition for RTC_SECCFGR register  ******************/
23586 #define RTC_SECCFGR_ALRASEC_Pos             (0U)
23587 #define RTC_SECCFGR_ALRASEC_Msk             (0x1UL << RTC_SECCFGR_ALRASEC_Pos)      /*!< 0x00000001 */
23588 #define RTC_SECCFGR_ALRASEC                 RTC_SECCFGR_ALRASEC_Msk
23589 #define RTC_SECCFGR_ALRBSEC_Pos             (1U)
23590 #define RTC_SECCFGR_ALRBSEC_Msk             (0x1UL << RTC_SECCFGR_ALRBSEC_Pos)      /*!< 0x00000002 */
23591 #define RTC_SECCFGR_ALRBSEC                 RTC_SECCFGR_ALRBSEC_Msk
23592 #define RTC_SECCFGR_WUTSEC_Pos              (2U)
23593 #define RTC_SECCFGR_WUTSEC_Msk              (0x1UL << RTC_SECCFGR_WUTSEC_Pos)       /*!< 0x00000004 */
23594 #define RTC_SECCFGR_WUTSEC                  RTC_SECCFGR_WUTSEC_Msk
23595 #define RTC_SECCFGR_TSSEC_Pos               (3U)
23596 #define RTC_SECCFGR_TSSEC_Msk               (0x1UL << RTC_SECCFGR_TSSEC_Pos)        /*!< 0x00000008 */
23597 #define RTC_SECCFGR_TSSEC                   RTC_SECCFGR_TSSEC_Msk
23598 #define RTC_SECCFGR_CALSEC_Pos              (13U)
23599 #define RTC_SECCFGR_CALSEC_Msk              (0x1UL << RTC_SECCFGR_CALSEC_Pos)       /*!< 0x00002000 */
23600 #define RTC_SECCFGR_CALSEC                  RTC_SECCFGR_CALSEC_Msk
23601 #define RTC_SECCFGR_INITSEC_Pos             (14U)
23602 #define RTC_SECCFGR_INITSEC_Msk             (0x1UL << RTC_SECCFGR_INITSEC_Pos)      /*!< 0x00004000 */
23603 #define RTC_SECCFGR_INITSEC                 RTC_SECCFGR_INITSEC_Msk
23604 #define RTC_SECCFGR_SEC_Pos                 (15U)
23605 #define RTC_SECCFGR_SEC_Msk                 (0x1UL << RTC_SECCFGR_SEC_Pos)          /*!< 0x00008000 */
23606 #define RTC_SECCFGR_SEC                     RTC_SECCFGR_SEC_Msk
23607 
23608 /********************  Bits definition for RTC_WPR register  ******************/
23609 #define RTC_WPR_KEY_Pos                     (0U)
23610 #define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
23611 #define RTC_WPR_KEY                         RTC_WPR_KEY_Msk
23612 
23613 /********************  Bits definition for RTC_CALR register  *****************/
23614 #define RTC_CALR_CALM_Pos                   (0U)
23615 #define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
23616 #define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
23617 #define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
23618 #define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
23619 #define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
23620 #define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
23621 #define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
23622 #define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
23623 #define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
23624 #define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
23625 #define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
23626 #define RTC_CALR_LPCAL_Pos                  (12U)
23627 #define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
23628 #define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
23629 #define RTC_CALR_CALW16_Pos                 (13U)
23630 #define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
23631 #define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
23632 #define RTC_CALR_CALW8_Pos                  (14U)
23633 #define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
23634 #define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
23635 #define RTC_CALR_CALP_Pos                   (15U)
23636 #define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
23637 #define RTC_CALR_CALP                       RTC_CALR_CALP_Msk
23638 
23639 /********************  Bits definition for RTC_SHIFTR register  ***************/
23640 #define RTC_SHIFTR_SUBFS_Pos                (0U)
23641 #define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
23642 #define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
23643 #define RTC_SHIFTR_ADD1S_Pos                (31U)
23644 #define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
23645 #define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk
23646 
23647 /********************  Bits definition for RTC_TSTR register  *****************/
23648 #define RTC_TSTR_SU_Pos                     (0U)
23649 #define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
23650 #define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
23651 #define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
23652 #define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
23653 #define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
23654 #define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
23655 #define RTC_TSTR_ST_Pos                     (4U)
23656 #define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
23657 #define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
23658 #define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
23659 #define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
23660 #define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
23661 #define RTC_TSTR_MNU_Pos                    (8U)
23662 #define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
23663 #define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
23664 #define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
23665 #define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
23666 #define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
23667 #define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
23668 #define RTC_TSTR_MNT_Pos                    (12U)
23669 #define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
23670 #define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
23671 #define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
23672 #define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
23673 #define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
23674 #define RTC_TSTR_HU_Pos                     (16U)
23675 #define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
23676 #define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
23677 #define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
23678 #define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
23679 #define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
23680 #define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
23681 #define RTC_TSTR_HT_Pos                     (20U)
23682 #define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
23683 #define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
23684 #define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
23685 #define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
23686 #define RTC_TSTR_PM_Pos                     (22U)
23687 #define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
23688 #define RTC_TSTR_PM                         RTC_TSTR_PM_Msk
23689 
23690 /********************  Bits definition for RTC_TSDR register  *****************/
23691 #define RTC_TSDR_DU_Pos                     (0U)
23692 #define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
23693 #define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
23694 #define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
23695 #define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
23696 #define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
23697 #define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
23698 #define RTC_TSDR_DT_Pos                     (4U)
23699 #define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
23700 #define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
23701 #define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
23702 #define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
23703 #define RTC_TSDR_MU_Pos                     (8U)
23704 #define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
23705 #define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
23706 #define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
23707 #define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
23708 #define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
23709 #define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
23710 #define RTC_TSDR_MT_Pos                     (12U)
23711 #define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
23712 #define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
23713 #define RTC_TSDR_WDU_Pos                    (13U)
23714 #define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
23715 #define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
23716 #define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
23717 #define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
23718 #define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */
23719 
23720 /********************  Bits definition for RTC_TSSSR register  ****************/
23721 #define RTC_TSSSR_SS_Pos                    (0U)
23722 #define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
23723 #define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */
23724 
23725 /********************  Bits definition for RTC_ALRMAR register  ***************/
23726 #define RTC_ALRMAR_SU_Pos                   (0U)
23727 #define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
23728 #define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
23729 #define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
23730 #define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
23731 #define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
23732 #define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
23733 #define RTC_ALRMAR_ST_Pos                   (4U)
23734 #define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
23735 #define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
23736 #define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
23737 #define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
23738 #define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
23739 #define RTC_ALRMAR_MSK1_Pos                 (7U)
23740 #define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
23741 #define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
23742 #define RTC_ALRMAR_MNU_Pos                  (8U)
23743 #define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
23744 #define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
23745 #define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
23746 #define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
23747 #define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
23748 #define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
23749 #define RTC_ALRMAR_MNT_Pos                  (12U)
23750 #define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
23751 #define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
23752 #define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
23753 #define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
23754 #define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
23755 #define RTC_ALRMAR_MSK2_Pos                 (15U)
23756 #define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
23757 #define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
23758 #define RTC_ALRMAR_HU_Pos                   (16U)
23759 #define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
23760 #define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
23761 #define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
23762 #define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
23763 #define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
23764 #define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
23765 #define RTC_ALRMAR_HT_Pos                   (20U)
23766 #define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
23767 #define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
23768 #define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
23769 #define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
23770 #define RTC_ALRMAR_PM_Pos                   (22U)
23771 #define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
23772 #define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
23773 #define RTC_ALRMAR_MSK3_Pos                 (23U)
23774 #define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
23775 #define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
23776 #define RTC_ALRMAR_DU_Pos                   (24U)
23777 #define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
23778 #define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
23779 #define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
23780 #define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
23781 #define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
23782 #define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
23783 #define RTC_ALRMAR_DT_Pos                   (28U)
23784 #define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
23785 #define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
23786 #define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
23787 #define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
23788 #define RTC_ALRMAR_WDSEL_Pos                (30U)
23789 #define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
23790 #define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
23791 #define RTC_ALRMAR_MSK4_Pos                 (31U)
23792 #define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
23793 #define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk
23794 
23795 /********************  Bits definition for RTC_ALRMASSR register  *************/
23796 #define RTC_ALRMASSR_SS_Pos                 (0U)
23797 #define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
23798 #define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
23799 #define RTC_ALRMASSR_MASKSS_Pos             (24U)
23800 #define RTC_ALRMASSR_MASKSS_Msk             (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */
23801 #define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
23802 #define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
23803 #define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
23804 #define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
23805 #define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
23806 #define RTC_ALRMASSR_SSCLR_Pos              (31U)
23807 #define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
23808 #define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk
23809 
23810 /********************  Bits definition for RTC_ALRMBR register  ***************/
23811 #define RTC_ALRMBR_SU_Pos                   (0U)
23812 #define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
23813 #define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
23814 #define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
23815 #define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
23816 #define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
23817 #define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
23818 #define RTC_ALRMBR_ST_Pos                   (4U)
23819 #define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
23820 #define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
23821 #define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
23822 #define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
23823 #define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
23824 #define RTC_ALRMBR_MSK1_Pos                 (7U)
23825 #define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
23826 #define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
23827 #define RTC_ALRMBR_MNU_Pos                  (8U)
23828 #define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
23829 #define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
23830 #define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
23831 #define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
23832 #define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
23833 #define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
23834 #define RTC_ALRMBR_MNT_Pos                  (12U)
23835 #define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
23836 #define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
23837 #define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
23838 #define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
23839 #define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
23840 #define RTC_ALRMBR_MSK2_Pos                 (15U)
23841 #define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
23842 #define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
23843 #define RTC_ALRMBR_HU_Pos                   (16U)
23844 #define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
23845 #define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
23846 #define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
23847 #define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
23848 #define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
23849 #define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
23850 #define RTC_ALRMBR_HT_Pos                   (20U)
23851 #define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
23852 #define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
23853 #define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
23854 #define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
23855 #define RTC_ALRMBR_PM_Pos                   (22U)
23856 #define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
23857 #define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
23858 #define RTC_ALRMBR_MSK3_Pos                 (23U)
23859 #define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
23860 #define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
23861 #define RTC_ALRMBR_DU_Pos                   (24U)
23862 #define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
23863 #define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
23864 #define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
23865 #define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
23866 #define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
23867 #define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
23868 #define RTC_ALRMBR_DT_Pos                   (28U)
23869 #define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
23870 #define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
23871 #define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
23872 #define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
23873 #define RTC_ALRMBR_WDSEL_Pos                (30U)
23874 #define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
23875 #define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
23876 #define RTC_ALRMBR_MSK4_Pos                 (31U)
23877 #define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
23878 #define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk
23879 
23880 /********************  Bits definition for RTC_ALRMBSSR register  *************/
23881 #define RTC_ALRMBSSR_SS_Pos                 (0U)
23882 #define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
23883 #define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
23884 #define RTC_ALRMBSSR_MASKSS_Pos             (24U)
23885 #define RTC_ALRMBSSR_MASKSS_Msk             (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */
23886 #define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
23887 #define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
23888 #define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
23889 #define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
23890 #define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
23891 #define RTC_ALRMBSSR_SSCLR_Pos              (31U)
23892 #define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
23893 #define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk
23894 
23895 /********************  Bits definition for RTC_SR register  *******************/
23896 #define RTC_SR_ALRAF_Pos                    (0U)
23897 #define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
23898 #define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
23899 #define RTC_SR_ALRBF_Pos                    (1U)
23900 #define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
23901 #define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
23902 #define RTC_SR_WUTF_Pos                     (2U)
23903 #define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
23904 #define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
23905 #define RTC_SR_TSF_Pos                      (3U)
23906 #define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
23907 #define RTC_SR_TSF                          RTC_SR_TSF_Msk
23908 #define RTC_SR_TSOVF_Pos                    (4U)
23909 #define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
23910 #define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
23911 #define RTC_SR_ITSF_Pos                     (5U)
23912 #define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
23913 #define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
23914 #define RTC_SR_SSRUF_Pos                    (6U)
23915 #define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
23916 #define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk
23917 
23918 /********************  Bits definition for RTC_MISR register  *****************/
23919 #define RTC_MISR_ALRAMF_Pos                 (0U)
23920 #define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
23921 #define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
23922 #define RTC_MISR_ALRBMF_Pos                 (1U)
23923 #define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
23924 #define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
23925 #define RTC_MISR_WUTMF_Pos                  (2U)
23926 #define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
23927 #define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
23928 #define RTC_MISR_TSMF_Pos                   (3U)
23929 #define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
23930 #define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
23931 #define RTC_MISR_TSOVMF_Pos                 (4U)
23932 #define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
23933 #define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
23934 #define RTC_MISR_ITSMF_Pos                  (5U)
23935 #define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
23936 #define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
23937 #define RTC_MISR_SSRUMF_Pos                 (6U)
23938 #define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
23939 #define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk
23940 
23941 /********************  Bits definition for RTC_SMISR register  *****************/
23942 #define RTC_SMISR_ALRAMF_Pos                (0U)
23943 #define RTC_SMISR_ALRAMF_Msk                (0x1UL << RTC_SMISR_ALRAMF_Pos)         /*!< 0x00000001 */
23944 #define RTC_SMISR_ALRAMF                    RTC_SMISR_ALRAMF_Msk
23945 #define RTC_SMISR_ALRBMF_Pos                (1U)
23946 #define RTC_SMISR_ALRBMF_Msk                (0x1UL << RTC_SMISR_ALRBMF_Pos)         /*!< 0x00000002 */
23947 #define RTC_SMISR_ALRBMF                    RTC_SMISR_ALRBMF_Msk
23948 #define RTC_SMISR_WUTMF_Pos                 (2U)
23949 #define RTC_SMISR_WUTMF_Msk                 (0x1UL << RTC_SMISR_WUTMF_Pos)          /*!< 0x00000004 */
23950 #define RTC_SMISR_WUTMF                     RTC_SMISR_WUTMF_Msk
23951 #define RTC_SMISR_TSMF_Pos                  (3U)
23952 #define RTC_SMISR_TSMF_Msk                  (0x1UL << RTC_SMISR_TSMF_Pos)           /*!< 0x00000008 */
23953 #define RTC_SMISR_TSMF                      RTC_SMISR_TSMF_Msk
23954 #define RTC_SMISR_TSOVMF_Pos                (4U)
23955 #define RTC_SMISR_TSOVMF_Msk                (0x1UL << RTC_SMISR_TSOVMF_Pos)         /*!< 0x00000010 */
23956 #define RTC_SMISR_TSOVMF                    RTC_SMISR_TSOVMF_Msk
23957 #define RTC_SMISR_ITSMF_Pos                 (5U)
23958 #define RTC_SMISR_ITSMF_Msk                 (0x1UL << RTC_SMISR_ITSMF_Pos)          /*!< 0x00000020 */
23959 #define RTC_SMISR_ITSMF                     RTC_SMISR_ITSMF_Msk
23960 #define RTC_SMISR_SSRUMF_Pos                (6U)
23961 #define RTC_SMISR_SSRUMF_Msk                (0x1UL << RTC_SMISR_SSRUMF_Pos)         /*!< 0x00000040 */
23962 #define RTC_SMISR_SSRUMF                    RTC_SMISR_SSRUMF_Msk
23963 
23964 /********************  Bits definition for RTC_SCR register  ******************/
23965 #define RTC_SCR_CALRAF_Pos                  (0U)
23966 #define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
23967 #define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
23968 #define RTC_SCR_CALRBF_Pos                  (1U)
23969 #define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
23970 #define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
23971 #define RTC_SCR_CWUTF_Pos                   (2U)
23972 #define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
23973 #define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
23974 #define RTC_SCR_CTSF_Pos                    (3U)
23975 #define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
23976 #define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
23977 #define RTC_SCR_CTSOVF_Pos                  (4U)
23978 #define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
23979 #define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
23980 #define RTC_SCR_CITSF_Pos                   (5U)
23981 #define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
23982 #define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
23983 #define RTC_SCR_CSSRUF_Pos                  (6U)
23984 #define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
23985 #define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk
23986 
23987 /********************  Bits definition for RTC_ALRABINR register  ******************/
23988 #define RTC_ALRABINR_SS_Pos                 (0U)
23989 #define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
23990 #define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk
23991 
23992 /********************  Bits definition for RTC_ALRBBINR register  ******************/
23993 #define RTC_ALRBBINR_SS_Pos                 (0U)
23994 #define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
23995 #define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk
23996 
23997 /******************************************************************************/
23998 /*                                                                            */
23999 /*                     Tamper and backup register (TAMP)                      */
24000 /*                                                                            */
24001 /******************************************************************************/
24002 /********************  Bits definition for TAMP_CR1 register  *****************/
24003 #define TAMP_CR1_TAMP1E_Pos                 (0U)
24004 #define TAMP_CR1_TAMP1E_Msk                 (0x1UL << TAMP_CR1_TAMP1E_Pos)          /*!< 0x00000001 */
24005 #define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk
24006 #define TAMP_CR1_TAMP2E_Pos                 (1U)
24007 #define TAMP_CR1_TAMP2E_Msk                 (0x1UL << TAMP_CR1_TAMP2E_Pos)          /*!< 0x00000002 */
24008 #define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk
24009 #define TAMP_CR1_TAMP3E_Pos                 (2U)
24010 #define TAMP_CR1_TAMP3E_Msk                 (0x1UL << TAMP_CR1_TAMP3E_Pos)          /*!< 0x00000004 */
24011 #define TAMP_CR1_TAMP3E                     TAMP_CR1_TAMP3E_Msk
24012 #define TAMP_CR1_TAMP4E_Pos                 (3U)
24013 #define TAMP_CR1_TAMP4E_Msk                 (0x1UL << TAMP_CR1_TAMP4E_Pos)          /*!< 0x00000008 */
24014 #define TAMP_CR1_TAMP4E                     TAMP_CR1_TAMP4E_Msk
24015 #define TAMP_CR1_TAMP5E_Pos                 (4U)
24016 #define TAMP_CR1_TAMP5E_Msk                 (0x1UL << TAMP_CR1_TAMP5E_Pos)          /*!< 0x00000010 */
24017 #define TAMP_CR1_TAMP5E                     TAMP_CR1_TAMP5E_Msk
24018 #define TAMP_CR1_TAMP6E_Pos                 (5U)
24019 #define TAMP_CR1_TAMP6E_Msk                 (0x1UL << TAMP_CR1_TAMP6E_Pos)          /*!< 0x00000020 */
24020 #define TAMP_CR1_TAMP6E                     TAMP_CR1_TAMP6E_Msk
24021 #define TAMP_CR1_TAMP7E_Pos                 (6U)
24022 #define TAMP_CR1_TAMP7E_Msk                 (0x1UL << TAMP_CR1_TAMP7E_Pos)          /*!< 0x00000040 */
24023 #define TAMP_CR1_TAMP7E                     TAMP_CR1_TAMP7E_Msk
24024 #define TAMP_CR1_TAMP8E_Pos                 (7U)
24025 #define TAMP_CR1_TAMP8E_Msk                 (0x1UL << TAMP_CR1_TAMP8E_Pos)          /*!< 0x00000080 */
24026 #define TAMP_CR1_TAMP8E                     TAMP_CR1_TAMP8E_Msk
24027 #define TAMP_CR1_ITAMP1E_Pos                (16U)
24028 #define TAMP_CR1_ITAMP1E_Msk                (0x1UL << TAMP_CR1_ITAMP1E_Pos)         /*!< 0x00010000 */
24029 #define TAMP_CR1_ITAMP1E                    TAMP_CR1_ITAMP1E_Msk
24030 #define TAMP_CR1_ITAMP2E_Pos                (17U)
24031 #define TAMP_CR1_ITAMP2E_Msk                (0x1UL << TAMP_CR1_ITAMP2E_Pos)         /*!< 0x00040000 */
24032 #define TAMP_CR1_ITAMP2E                    TAMP_CR1_ITAMP2E_Msk
24033 #define TAMP_CR1_ITAMP3E_Pos                (18U)
24034 #define TAMP_CR1_ITAMP3E_Msk                (0x1UL << TAMP_CR1_ITAMP3E_Pos)         /*!< 0x00040000 */
24035 #define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk
24036 #define TAMP_CR1_ITAMP5E_Pos                (20U)
24037 #define TAMP_CR1_ITAMP5E_Msk                (0x1UL << TAMP_CR1_ITAMP5E_Pos)         /*!< 0x00100000 */
24038 #define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk
24039 #define TAMP_CR1_ITAMP6E_Pos                (21U)
24040 #define TAMP_CR1_ITAMP6E_Msk                (0x1UL << TAMP_CR1_ITAMP6E_Pos)         /*!< 0x00200000 */
24041 #define TAMP_CR1_ITAMP6E                    TAMP_CR1_ITAMP6E_Msk
24042 #define TAMP_CR1_ITAMP7E_Pos                (22U)
24043 #define TAMP_CR1_ITAMP7E_Msk                (0x1UL << TAMP_CR1_ITAMP7E_Pos)         /*!< 0x00400000 */
24044 #define TAMP_CR1_ITAMP7E                    TAMP_CR1_ITAMP7E_Msk
24045 #define TAMP_CR1_ITAMP8E_Pos                (23U)
24046 #define TAMP_CR1_ITAMP8E_Msk                (0x1UL << TAMP_CR1_ITAMP8E_Pos)         /*!< 0x00800000 */
24047 #define TAMP_CR1_ITAMP8E                    TAMP_CR1_ITAMP8E_Msk
24048 #define TAMP_CR1_ITAMP9E_Pos                (24U)
24049 #define TAMP_CR1_ITAMP9E_Msk                (0x1UL << TAMP_CR1_ITAMP9E_Pos)         /*!< 0x01000000 */
24050 #define TAMP_CR1_ITAMP9E                    TAMP_CR1_ITAMP9E_Msk
24051 #define TAMP_CR1_ITAMP11E_Pos               (26U)
24052 #define TAMP_CR1_ITAMP11E_Msk               (0x1UL << TAMP_CR1_ITAMP11E_Pos)        /*!< 0x04000000 */
24053 #define TAMP_CR1_ITAMP11E                   TAMP_CR1_ITAMP11E_Msk
24054 #define TAMP_CR1_ITAMP12E_Pos               (27U)
24055 #define TAMP_CR1_ITAMP12E_Msk               (0x1UL << TAMP_CR1_ITAMP12E_Pos)        /*!< 0x04000000 */
24056 #define TAMP_CR1_ITAMP12E                   TAMP_CR1_ITAMP12E_Msk
24057 #define TAMP_CR1_ITAMP13E_Pos               (28U)
24058 #define TAMP_CR1_ITAMP13E_Msk               (0x1UL << TAMP_CR1_ITAMP13E_Pos)        /*!< 0x04000000 */
24059 #define TAMP_CR1_ITAMP13E                   TAMP_CR1_ITAMP13E_Msk
24060 
24061 /********************  Bits definition for TAMP_CR2 register  *****************/
24062 #define TAMP_CR2_TAMP1NOERASE_Pos           (0U)
24063 #define TAMP_CR2_TAMP1NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)    /*!< 0x00000001 */
24064 #define TAMP_CR2_TAMP1NOERASE               TAMP_CR2_TAMP1NOERASE_Msk
24065 #define TAMP_CR2_TAMP2NOERASE_Pos           (1U)
24066 #define TAMP_CR2_TAMP2NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)    /*!< 0x00000002 */
24067 #define TAMP_CR2_TAMP2NOERASE               TAMP_CR2_TAMP2NOERASE_Msk
24068 #define TAMP_CR2_TAMP3NOERASE_Pos           (2U)
24069 #define TAMP_CR2_TAMP3NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)    /*!< 0x00000004 */
24070 #define TAMP_CR2_TAMP3NOERASE               TAMP_CR2_TAMP3NOERASE_Msk
24071 #define TAMP_CR2_TAMP4NOERASE_Pos           (3U)
24072 #define TAMP_CR2_TAMP4NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos)    /*!< 0x00000008 */
24073 #define TAMP_CR2_TAMP4NOERASE               TAMP_CR2_TAMP4NOERASE_Msk
24074 #define TAMP_CR2_TAMP5NOERASE_Pos           (4U)
24075 #define TAMP_CR2_TAMP5NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos)    /*!< 0x00000010 */
24076 #define TAMP_CR2_TAMP5NOERASE               TAMP_CR2_TAMP5NOERASE_Msk
24077 #define TAMP_CR2_TAMP6NOERASE_Pos           (5U)
24078 #define TAMP_CR2_TAMP6NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos)    /*!< 0x00000020 */
24079 #define TAMP_CR2_TAMP6NOERASE               TAMP_CR2_TAMP6NOERASE_Msk
24080 #define TAMP_CR2_TAMP7NOERASE_Pos           (6U)
24081 #define TAMP_CR2_TAMP7NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos)    /*!< 0x00000040 */
24082 #define TAMP_CR2_TAMP7NOERASE               TAMP_CR2_TAMP7NOERASE_Msk
24083 #define TAMP_CR2_TAMP8NOERASE_Pos           (7U)
24084 #define TAMP_CR2_TAMP8NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos)    /*!< 0x00000080 */
24085 #define TAMP_CR2_TAMP8NOERASE               TAMP_CR2_TAMP8NOERASE_Msk
24086 #define TAMP_CR2_TAMP1MSK_Pos               (16U)
24087 #define TAMP_CR2_TAMP1MSK_Msk               (0x1UL << TAMP_CR2_TAMP1MSK_Pos)        /*!< 0x00010000 */
24088 #define TAMP_CR2_TAMP1MSK                   TAMP_CR2_TAMP1MSK_Msk
24089 #define TAMP_CR2_TAMP2MSK_Pos               (17U)
24090 #define TAMP_CR2_TAMP2MSK_Msk               (0x1UL << TAMP_CR2_TAMP2MSK_Pos)        /*!< 0x00020000 */
24091 #define TAMP_CR2_TAMP2MSK                   TAMP_CR2_TAMP2MSK_Msk
24092 #define TAMP_CR2_TAMP3MSK_Pos               (18U)
24093 #define TAMP_CR2_TAMP3MSK_Msk               (0x1UL << TAMP_CR2_TAMP3MSK_Pos)        /*!< 0x00040000 */
24094 #define TAMP_CR2_TAMP3MSK                   TAMP_CR2_TAMP3MSK_Msk
24095 #define TAMP_CR2_BKBLOCK_Pos                (22U)
24096 #define TAMP_CR2_BKBLOCK_Msk                (0x1UL << TAMP_CR2_BKBLOCK_Pos)         /*!< 0x00800000 */
24097 #define TAMP_CR2_BKBLOCK                    TAMP_CR2_BKBLOCK_Msk
24098 #define TAMP_CR2_BKERASE_Pos                (23U)
24099 #define TAMP_CR2_BKERASE_Msk                (0x1UL << TAMP_CR2_BKERASE_Pos)         /*!< 0x00800000 */
24100 #define TAMP_CR2_BKERASE                    TAMP_CR2_BKERASE_Msk
24101 #define TAMP_CR2_TAMP1TRG_Pos               (24U)
24102 #define TAMP_CR2_TAMP1TRG_Msk               (0x1UL << TAMP_CR2_TAMP1TRG_Pos)        /*!< 0x01000000 */
24103 #define TAMP_CR2_TAMP1TRG                   TAMP_CR2_TAMP1TRG_Msk
24104 #define TAMP_CR2_TAMP2TRG_Pos               (25U)
24105 #define TAMP_CR2_TAMP2TRG_Msk               (0x1UL << TAMP_CR2_TAMP2TRG_Pos)        /*!< 0x02000000 */
24106 #define TAMP_CR2_TAMP2TRG                   TAMP_CR2_TAMP2TRG_Msk
24107 #define TAMP_CR2_TAMP3TRG_Pos               (26U)
24108 #define TAMP_CR2_TAMP3TRG_Msk               (0x1UL << TAMP_CR2_TAMP3TRG_Pos)        /*!< 0x02000000 */
24109 #define TAMP_CR2_TAMP3TRG                   TAMP_CR2_TAMP3TRG_Msk
24110 #define TAMP_CR2_TAMP4TRG_Pos               (27U)
24111 #define TAMP_CR2_TAMP4TRG_Msk               (0x1UL << TAMP_CR2_TAMP4TRG_Pos)        /*!< 0x02000000 */
24112 #define TAMP_CR2_TAMP4TRG                   TAMP_CR2_TAMP4TRG_Msk
24113 #define TAMP_CR2_TAMP5TRG_Pos               (28U)
24114 #define TAMP_CR2_TAMP5TRG_Msk               (0x1UL << TAMP_CR2_TAMP5TRG_Pos)        /*!< 0x02000000 */
24115 #define TAMP_CR2_TAMP5TRG                   TAMP_CR2_TAMP5TRG_Msk
24116 #define TAMP_CR2_TAMP6TRG_Pos               (29U)
24117 #define TAMP_CR2_TAMP6TRG_Msk               (0x1UL << TAMP_CR2_TAMP6TRG_Pos)        /*!< 0x02000000 */
24118 #define TAMP_CR2_TAMP6TRG                   TAMP_CR2_TAMP6TRG_Msk
24119 #define TAMP_CR2_TAMP7TRG_Pos               (30U)
24120 #define TAMP_CR2_TAMP7TRG_Msk               (0x1UL << TAMP_CR2_TAMP7TRG_Pos)        /*!< 0x02000000 */
24121 #define TAMP_CR2_TAMP7TRG                   TAMP_CR2_TAMP7TRG_Msk
24122 #define TAMP_CR2_TAMP8TRG_Pos               (31U)
24123 #define TAMP_CR2_TAMP8TRG_Msk               (0x1UL << TAMP_CR2_TAMP8TRG_Pos)        /*!< 0x02000000 */
24124 #define TAMP_CR2_TAMP8TRG                   TAMP_CR2_TAMP8TRG_Msk
24125 
24126 /********************  Bits definition for TAMP_CR3 register  *****************/
24127 #define TAMP_CR3_ITAMP1NOER_Pos             (0U)
24128 #define TAMP_CR3_ITAMP1NOER_Msk             (0x1UL << TAMP_CR3_ITAMP1NOER_Pos)      /*!< 0x00000001 */
24129 #define TAMP_CR3_ITAMP1NOER                 TAMP_CR3_ITAMP1NOER_Msk
24130 #define TAMP_CR3_ITAMP2NOER_Pos             (1U)
24131 #define TAMP_CR3_ITAMP2NOER_Msk             (0x1UL << TAMP_CR3_ITAMP2NOER_Pos)      /*!< 0x00000002 */
24132 #define TAMP_CR3_ITAMP2NOER                 TAMP_CR3_ITAMP2NOER_Msk
24133 #define TAMP_CR3_ITAMP3NOER_Pos             (2U)
24134 #define TAMP_CR3_ITAMP3NOER_Msk             (0x1UL << TAMP_CR3_ITAMP3NOER_Pos)      /*!< 0x00000004 */
24135 #define TAMP_CR3_ITAMP3NOER                 TAMP_CR3_ITAMP3NOER_Msk
24136 #define TAMP_CR3_ITAMP5NOER_Pos             (4U)
24137 #define TAMP_CR3_ITAMP5NOER_Msk             (0x1UL << TAMP_CR3_ITAMP5NOER_Pos)      /*!< 0x00000010 */
24138 #define TAMP_CR3_ITAMP5NOER                 TAMP_CR3_ITAMP5NOER_Msk
24139 #define TAMP_CR3_ITAMP6NOER_Pos             (5U)
24140 #define TAMP_CR3_ITAMP6NOER_Msk             (0x1UL << TAMP_CR3_ITAMP6NOER_Pos)      /*!< 0x00000020 */
24141 #define TAMP_CR3_ITAMP6NOER                 TAMP_CR3_ITAMP6NOER_Msk
24142 #define TAMP_CR3_ITAMP7NOER_Pos             (6U)
24143 #define TAMP_CR3_ITAMP7NOER_Msk             (0x1UL << TAMP_CR3_ITAMP7NOER_Pos)
24144 #define TAMP_CR3_ITAMP7NOER                 TAMP_CR3_ITAMP7NOER_Msk
24145 #define TAMP_CR3_ITAMP8NOER_Pos             (7U)
24146 #define TAMP_CR3_ITAMP8NOER_Msk             (0x1UL << TAMP_CR3_ITAMP8NOER_Pos)      /*!< 0x00000040 */
24147 #define TAMP_CR3_ITAMP8NOER                 TAMP_CR3_ITAMP8NOER_Msk
24148 #define TAMP_CR3_ITAMP9NOER_Pos             (8U)
24149 #define TAMP_CR3_ITAMP9NOER_Msk             (0x1UL << TAMP_CR3_ITAMP9NOER_Pos)      /*!< 0x00000100 */
24150 #define TAMP_CR3_ITAMP9NOER                 TAMP_CR3_ITAMP9NOER_Msk
24151 #define TAMP_CR3_ITAMP11NOER_Pos            (10U)
24152 #define TAMP_CR3_ITAMP11NOER_Msk            (0x1UL << TAMP_CR3_ITAMP11NOER_Pos)     /*!< 0x00000800 */
24153 #define TAMP_CR3_ITAMP11NOER                TAMP_CR3_ITAMP11NOER_Msk
24154 #define TAMP_CR3_ITAMP12NOER_Pos            (11U)
24155 #define TAMP_CR3_ITAMP12NOER_Msk            (0x1UL << TAMP_CR3_ITAMP12NOER_Pos)     /*!< 0x00000800 */
24156 #define TAMP_CR3_ITAMP12NOER                TAMP_CR3_ITAMP12NOER_Msk
24157 #define TAMP_CR3_ITAMP13NOER_Pos            (12U)
24158 #define TAMP_CR3_ITAMP13NOER_Msk            (0x1UL << TAMP_CR3_ITAMP13NOER_Pos)     /*!< 0x00000800 */
24159 #define TAMP_CR3_ITAMP13NOER                TAMP_CR3_ITAMP13NOER_Msk
24160 
24161 /********************  Bits definition for TAMP_FLTCR register  ***************/
24162 #define TAMP_FLTCR_TAMPFREQ_Pos             (0U)
24163 #define TAMP_FLTCR_TAMPFREQ_Msk             (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000007 */
24164 #define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk
24165 #define TAMP_FLTCR_TAMPFREQ_0               (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000001 */
24166 #define TAMP_FLTCR_TAMPFREQ_1               (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000002 */
24167 #define TAMP_FLTCR_TAMPFREQ_2               (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000004 */
24168 #define TAMP_FLTCR_TAMPFLT_Pos              (3U)
24169 #define TAMP_FLTCR_TAMPFLT_Msk              (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000018 */
24170 #define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk
24171 #define TAMP_FLTCR_TAMPFLT_0                (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000008 */
24172 #define TAMP_FLTCR_TAMPFLT_1                (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000010 */
24173 #define TAMP_FLTCR_TAMPPRCH_Pos             (5U)
24174 #define TAMP_FLTCR_TAMPPRCH_Msk             (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000060 */
24175 #define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk
24176 #define TAMP_FLTCR_TAMPPRCH_0               (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000020 */
24177 #define TAMP_FLTCR_TAMPPRCH_1               (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000040 */
24178 #define TAMP_FLTCR_TAMPPUDIS_Pos            (7U)
24179 #define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)     /*!< 0x00000080 */
24180 #define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk
24181 
24182 /********************  Bits definition for TAMP_ATCR1 register  ***************/
24183 #define TAMP_ATCR1_TAMP1AM_Pos              (0U)
24184 #define TAMP_ATCR1_TAMP1AM_Msk              (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)       /*!< 0x00000001 */
24185 #define TAMP_ATCR1_TAMP1AM                  TAMP_ATCR1_TAMP1AM_Msk
24186 #define TAMP_ATCR1_TAMP2AM_Pos              (1U)
24187 #define TAMP_ATCR1_TAMP2AM_Msk              (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)       /*!< 0x00000002 */
24188 #define TAMP_ATCR1_TAMP2AM                  TAMP_ATCR1_TAMP2AM_Msk
24189 #define TAMP_ATCR1_TAMP3AM_Pos              (2U)
24190 #define TAMP_ATCR1_TAMP3AM_Msk              (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)       /*!< 0x00000004 */
24191 #define TAMP_ATCR1_TAMP3AM                  TAMP_ATCR1_TAMP3AM_Msk
24192 #define TAMP_ATCR1_TAMP4AM_Pos              (3U)
24193 #define TAMP_ATCR1_TAMP4AM_Msk              (0x1UL << TAMP_ATCR1_TAMP4AM_Pos)       /*!< 0x00000008 */
24194 #define TAMP_ATCR1_TAMP4AM                  TAMP_ATCR1_TAMP4AM_Msk
24195 #define TAMP_ATCR1_TAMP5AM_Pos              (4U)
24196 #define TAMP_ATCR1_TAMP5AM_Msk              (0x1UL << TAMP_ATCR1_TAMP5AM_Pos)       /*!< 0x00000010 */
24197 #define TAMP_ATCR1_TAMP5AM                  TAMP_ATCR1_TAMP5AM_Msk
24198 #define TAMP_ATCR1_TAMP6AM_Pos              (5U)
24199 #define TAMP_ATCR1_TAMP6AM_Msk              (0x1UL << TAMP_ATCR1_TAMP6AM_Pos)       /*!< 0x00000010 */
24200 #define TAMP_ATCR1_TAMP6AM                  TAMP_ATCR1_TAMP6AM_Msk
24201 #define TAMP_ATCR1_TAMP7AM_Pos              (6U)
24202 #define TAMP_ATCR1_TAMP7AM_Msk              (0x1UL << TAMP_ATCR1_TAMP7AM_Pos)       /*!< 0x00000040 */
24203 #define TAMP_ATCR1_TAMP7AM                  TAMP_ATCR1_TAMP7AM_Msk
24204 #define TAMP_ATCR1_TAMP8AM_Pos              (7U)
24205 #define TAMP_ATCR1_TAMP8AM_Msk              (0x1UL << TAMP_ATCR1_TAMP8AM_Pos)       /*!< 0x00000080 */
24206 #define TAMP_ATCR1_TAMP8AM                  TAMP_ATCR1_TAMP8AM_Msk
24207 #define TAMP_ATCR1_ATOSEL1_Pos              (8U)
24208 #define TAMP_ATCR1_ATOSEL1_Msk              (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000300 */
24209 #define TAMP_ATCR1_ATOSEL1                  TAMP_ATCR1_ATOSEL1_Msk
24210 #define TAMP_ATCR1_ATOSEL1_0                (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000100 */
24211 #define TAMP_ATCR1_ATOSEL1_1                (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000200 */
24212 #define TAMP_ATCR1_ATOSEL2_Pos              (10U)
24213 #define TAMP_ATCR1_ATOSEL2_Msk              (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000C00 */
24214 #define TAMP_ATCR1_ATOSEL2                  TAMP_ATCR1_ATOSEL2_Msk
24215 #define TAMP_ATCR1_ATOSEL2_0                (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000400 */
24216 #define TAMP_ATCR1_ATOSEL2_1                (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000800 */
24217 #define TAMP_ATCR1_ATOSEL3_Pos              (12U)
24218 #define TAMP_ATCR1_ATOSEL3_Msk              (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00003000 */
24219 #define TAMP_ATCR1_ATOSEL3                  TAMP_ATCR1_ATOSEL3_Msk
24220 #define TAMP_ATCR1_ATOSEL3_0                (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00001000 */
24221 #define TAMP_ATCR1_ATOSEL3_1                (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)       /*!< 0x00002000 */
24222 #define TAMP_ATCR1_ATOSEL4_Pos              (14U)
24223 #define TAMP_ATCR1_ATOSEL4_Msk              (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x0000C000 */
24224 #define TAMP_ATCR1_ATOSEL4                  TAMP_ATCR1_ATOSEL4_Msk
24225 #define TAMP_ATCR1_ATOSEL4_0                (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00004000 */
24226 #define TAMP_ATCR1_ATOSEL4_1                (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)       /*!< 0x00008000 */
24227 #define TAMP_ATCR1_ATCKSEL_Pos              (16U)
24228 #define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
24229 #define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
24230 #define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
24231 #define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
24232 #define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
24233 #define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
24234 #define TAMP_ATCR1_ATPER_Pos                (24U)
24235 #define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
24236 #define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
24237 #define TAMP_ATCR1_ATPER_0                  (0x1UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x01000000 */
24238 #define TAMP_ATCR1_ATPER_1                  (0x2UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x02000000 */
24239 #define TAMP_ATCR1_ATPER_2                  (0x4UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x04000000 */
24240 #define TAMP_ATCR1_ATOSHARE_Pos             (30U)
24241 #define TAMP_ATCR1_ATOSHARE_Msk             (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)      /*!< 0x40000000 */
24242 #define TAMP_ATCR1_ATOSHARE                 TAMP_ATCR1_ATOSHARE_Msk
24243 #define TAMP_ATCR1_FLTEN_Pos                (31U)
24244 #define TAMP_ATCR1_FLTEN_Msk                (0x1UL << TAMP_ATCR1_FLTEN_Pos)         /*!< 0x80000000 */
24245 #define TAMP_ATCR1_FLTEN                    TAMP_ATCR1_FLTEN_Msk
24246 
24247 /********************  Bits definition for TAMP_ATSEEDR register  ******************/
24248 #define TAMP_ATSEEDR_SEED_Pos               (0U)
24249 #define TAMP_ATSEEDR_SEED_Msk               (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
24250 #define TAMP_ATSEEDR_SEED                   TAMP_ATSEEDR_SEED_Msk
24251 
24252 /********************  Bits definition for TAMP_ATOR register  ******************/
24253 #define TAMP_ATOR_PRNG_Pos                  (0U)
24254 #define TAMP_ATOR_PRNG_Msk                  (0xFF << TAMP_ATOR_PRNG_Pos)            /*!< 0x000000FF */
24255 #define TAMP_ATOR_PRNG                      TAMP_ATOR_PRNG_Msk
24256 #define TAMP_ATOR_PRNG_0                    (0x1UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000001 */
24257 #define TAMP_ATOR_PRNG_1                    (0x2UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000002 */
24258 #define TAMP_ATOR_PRNG_2                    (0x4UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000004 */
24259 #define TAMP_ATOR_PRNG_3                    (0x8UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000008 */
24260 #define TAMP_ATOR_PRNG_4                    (0x10UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000010 */
24261 #define TAMP_ATOR_PRNG_5                    (0x20UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000020 */
24262 #define TAMP_ATOR_PRNG_6                    (0x40UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000040 */
24263 #define TAMP_ATOR_PRNG_7                    (0x80UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000080 */
24264 #define TAMP_ATOR_SEEDF_Pos                 (14U)
24265 #define TAMP_ATOR_SEEDF_Msk                 (1UL << TAMP_ATOR_SEEDF_Pos)            /*!< 0x00004000 */
24266 #define TAMP_ATOR_SEEDF                     TAMP_ATOR_SEEDF_Msk
24267 #define TAMP_ATOR_INITS_Pos                 (15U)
24268 #define TAMP_ATOR_INITS_Msk                 (1UL << TAMP_ATOR_INITS_Pos)            /*!< 0x00008000 */
24269 #define TAMP_ATOR_INITS                     TAMP_ATOR_INITS_Msk
24270 
24271 /********************  Bits definition for TAMP_ATCR2 register  ***************/
24272 #define TAMP_ATCR2_ATOSEL1_Pos              (8U)
24273 #define TAMP_ATCR2_ATOSEL1_Msk              (0x7UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000700 */
24274 #define TAMP_ATCR2_ATOSEL1                  TAMP_ATCR2_ATOSEL1_Msk
24275 #define TAMP_ATCR2_ATOSEL1_0                (0x1UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000100 */
24276 #define TAMP_ATCR2_ATOSEL1_1                (0x2UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000200 */
24277 #define TAMP_ATCR2_ATOSEL1_2                (0x4UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000400 */
24278 #define TAMP_ATCR2_ATOSEL2_Pos              (11U)
24279 #define TAMP_ATCR2_ATOSEL2_Msk              (0x7UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00003800 */
24280 #define TAMP_ATCR2_ATOSEL2                  TAMP_ATCR2_ATOSEL2_Msk
24281 #define TAMP_ATCR2_ATOSEL2_0                (0x1UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00000800 */
24282 #define TAMP_ATCR2_ATOSEL2_1                (0x2UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00001000 */
24283 #define TAMP_ATCR2_ATOSEL2_2                (0x4UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00002000 */
24284 #define TAMP_ATCR2_ATOSEL3_Pos              (14U)
24285 #define TAMP_ATCR2_ATOSEL3_Msk              (0x7UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x0001C000 */
24286 #define TAMP_ATCR2_ATOSEL3                  TAMP_ATCR2_ATOSEL3_Msk
24287 #define TAMP_ATCR2_ATOSEL3_0                (0x1UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00004000 */
24288 #define TAMP_ATCR2_ATOSEL3_1                (0x2UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00008000 */
24289 #define TAMP_ATCR2_ATOSEL3_2                (0x4UL << TAMP_ATCR2_ATOSEL3_Pos)       /*!< 0x00010000 */
24290 #define TAMP_ATCR2_ATOSEL4_Pos              (17U)
24291 #define TAMP_ATCR2_ATOSEL4_Msk              (0x7UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x000E0000 */
24292 #define TAMP_ATCR2_ATOSEL4                  TAMP_ATCR2_ATOSEL4_Msk
24293 #define TAMP_ATCR2_ATOSEL4_0                (0x1UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00020000 */
24294 #define TAMP_ATCR2_ATOSEL4_1                (0x2UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00040000 */
24295 #define TAMP_ATCR2_ATOSEL4_2                (0x4UL << TAMP_ATCR2_ATOSEL4_Pos)       /*!< 0x00080000 */
24296 #define TAMP_ATCR2_ATOSEL5_Pos              (20U)
24297 #define TAMP_ATCR2_ATOSEL5_Msk              (0x7UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00700000 */
24298 #define TAMP_ATCR2_ATOSEL5                  TAMP_ATCR2_ATOSEL5_Msk
24299 #define TAMP_ATCR2_ATOSEL5_0                (0x1UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00100000 */
24300 #define TAMP_ATCR2_ATOSEL5_1                (0x2UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00200000 */
24301 #define TAMP_ATCR2_ATOSEL5_2                (0x4UL << TAMP_ATCR2_ATOSEL5_Pos)       /*!< 0x00400000 */
24302 #define TAMP_ATCR2_ATOSEL6_Pos              (23U)
24303 #define TAMP_ATCR2_ATOSEL6_Msk              (0x7UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x03800000 */
24304 #define TAMP_ATCR2_ATOSEL6                  TAMP_ATCR2_ATOSEL6_Msk
24305 #define TAMP_ATCR2_ATOSEL6_0                (0x1UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x00800000 */
24306 #define TAMP_ATCR2_ATOSEL6_1                (0x2UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x01000000 */
24307 #define TAMP_ATCR2_ATOSEL6_2                (0x4UL << TAMP_ATCR2_ATOSEL6_Pos)       /*!< 0x02000000 */
24308 #define TAMP_ATCR2_ATOSEL7_Pos              (26U)
24309 #define TAMP_ATCR2_ATOSEL7_Msk              (0x7UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x1C000000 */
24310 #define TAMP_ATCR2_ATOSEL7                  TAMP_ATCR2_ATOSEL7_Msk
24311 #define TAMP_ATCR2_ATOSEL7_0                (0x1UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x04000000 */
24312 #define TAMP_ATCR2_ATOSEL7_1                (0x2UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x08000000 */
24313 #define TAMP_ATCR2_ATOSEL7_2                (0x4UL << TAMP_ATCR2_ATOSEL7_Pos)       /*!< 0x10000000 */
24314 #define TAMP_ATCR2_ATOSEL8_Pos              (29U)
24315 #define TAMP_ATCR2_ATOSEL8_Msk              (0x7UL << TAMP_ATCR2_ATOSEL8_Pos)       /*!< 0xE0000000 */
24316 #define TAMP_ATCR2_ATOSEL8                  TAMP_ATCR2_ATOSEL8_Msk
24317 #define TAMP_ATCR2_ATOSEL8_0                (0x1UL << TAMP_ATCR2_ATOSEL8_Pos)       /*!< 0x20000000 */
24318 #define TAMP_ATCR2_ATOSEL8_1                (0x2UL << TAMP_ATCR2_ATOSEL8_Pos)       /*!< 0x40000000 */
24319 #define TAMP_ATCR2_ATOSEL8_2                (0x4UL << TAMP_ATCR2_ATOSEL8_Pos)       /*!< 0x80000000 */
24320 
24321 /********************  Bits definition for TAMP_SECCFGR register  *************/
24322 #define TAMP_SECCFGR_BKPRWSEC_Pos           (0U)
24323 #define TAMP_SECCFGR_BKPRWSEC_Msk           (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x000000FF */
24324 #define TAMP_SECCFGR_BKPRWSEC               TAMP_SECCFGR_BKPRWSEC_Msk
24325 #define TAMP_SECCFGR_BKPRWSEC_0             (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000001 */
24326 #define TAMP_SECCFGR_BKPRWSEC_1             (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000002 */
24327 #define TAMP_SECCFGR_BKPRWSEC_2             (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000004 */
24328 #define TAMP_SECCFGR_BKPRWSEC_3             (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000008 */
24329 #define TAMP_SECCFGR_BKPRWSEC_4             (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000010 */
24330 #define TAMP_SECCFGR_BKPRWSEC_5             (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000020 */
24331 #define TAMP_SECCFGR_BKPRWSEC_6             (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000040 */
24332 #define TAMP_SECCFGR_BKPRWSEC_7             (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000080 */
24333 #define TAMP_SECCFGR_CNT1SEC_Pos            (15U)
24334 #define TAMP_SECCFGR_CNT1SEC_Msk            (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos)     /*!< 0x00008000 */
24335 #define TAMP_SECCFGR_CNT1SEC                TAMP_SECCFGR_CNT1SEC_Msk
24336 #define TAMP_SECCFGR_BKPWSEC_Pos            (16U)
24337 #define TAMP_SECCFGR_BKPWSEC_Msk            (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00FF0000 */
24338 #define TAMP_SECCFGR_BKPWSEC                TAMP_SECCFGR_BKPWSEC_Msk
24339 #define TAMP_SECCFGR_BKPWSEC_0              (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00010000 */
24340 #define TAMP_SECCFGR_BKPWSEC_1              (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00020000 */
24341 #define TAMP_SECCFGR_BKPWSEC_2              (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00040000 */
24342 #define TAMP_SECCFGR_BKPWSEC_3              (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00080000 */
24343 #define TAMP_SECCFGR_BKPWSEC_4              (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00100000 */
24344 #define TAMP_SECCFGR_BKPWSEC_5              (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00200000 */
24345 #define TAMP_SECCFGR_BKPWSEC_6              (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00400000 */
24346 #define TAMP_SECCFGR_BKPWSEC_7              (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00800000 */
24347 #define TAMP_SECCFGR_BHKLOCK_Pos            (30U)
24348 #define TAMP_SECCFGR_BHKLOCK_Msk            (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos)     /*!< 0x40000000 */
24349 #define TAMP_SECCFGR_BHKLOCK                TAMP_SECCFGR_BHKLOCK_Msk
24350 #define TAMP_SECCFGR_TAMPSEC_Pos            (31U)
24351 #define TAMP_SECCFGR_TAMPSEC_Msk            (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos)     /*!< 0x80000000 */
24352 #define TAMP_SECCFGR_TAMPSEC                TAMP_SECCFGR_TAMPSEC_Msk
24353 
24354 /********************  Bits definition for TAMP_PRIVCFGR register  ************/
24355 #define TAMP_PRIVCFGR_CNT1PRIV_Pos          (15U)
24356 #define TAMP_PRIVCFGR_CNT1PRIV_Msk          (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos)   /*!< 0x20000000 */
24357 #define TAMP_PRIVCFGR_CNT1PRIV              TAMP_PRIVCFGR_CNT1PRIV_Msk
24358 #define TAMP_PRIVCFGR_BKPRWPRIV_Pos         (29U)
24359 #define TAMP_PRIVCFGR_BKPRWPRIV_Msk         (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos)  /*!< 0x20000000 */
24360 #define TAMP_PRIVCFGR_BKPRWPRIV             TAMP_PRIVCFGR_BKPRWPRIV_Msk
24361 #define TAMP_PRIVCFGR_BKPWPRIV_Pos          (30U)
24362 #define TAMP_PRIVCFGR_BKPWPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos)   /*!< 0x40000000 */
24363 #define TAMP_PRIVCFGR_BKPWPRIV              TAMP_PRIVCFGR_BKPWPRIV_Msk
24364 #define TAMP_PRIVCFGR_TAMPPRIV_Pos          (31U)
24365 #define TAMP_PRIVCFGR_TAMPPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos)   /*!< 0x80000000 */
24366 #define TAMP_PRIVCFGR_TAMPPRIV              TAMP_PRIVCFGR_TAMPPRIV_Msk
24367 
24368 /********************  Bits definition for TAMP_IER register  *****************/
24369 #define TAMP_IER_TAMP1IE_Pos                (0U)
24370 #define TAMP_IER_TAMP1IE_Msk                (0x1UL << TAMP_IER_TAMP1IE_Pos)         /*!< 0x00000001 */
24371 #define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk
24372 #define TAMP_IER_TAMP2IE_Pos                (1U)
24373 #define TAMP_IER_TAMP2IE_Msk                (0x1UL << TAMP_IER_TAMP2IE_Pos)         /*!< 0x00000002 */
24374 #define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk
24375 #define TAMP_IER_TAMP3IE_Pos                (2U)
24376 #define TAMP_IER_TAMP3IE_Msk                (0x1UL << TAMP_IER_TAMP3IE_Pos)         /*!< 0x00000004 */
24377 #define TAMP_IER_TAMP3IE                    TAMP_IER_TAMP3IE_Msk
24378 #define TAMP_IER_TAMP4IE_Pos                (3U)
24379 #define TAMP_IER_TAMP4IE_Msk                (0x1UL << TAMP_IER_TAMP4IE_Pos)         /*!< 0x00000008 */
24380 #define TAMP_IER_TAMP4IE                    TAMP_IER_TAMP4IE_Msk
24381 #define TAMP_IER_TAMP5IE_Pos                (4U)
24382 #define TAMP_IER_TAMP5IE_Msk                (0x1UL << TAMP_IER_TAMP5IE_Pos)         /*!< 0x00000010 */
24383 #define TAMP_IER_TAMP5IE                    TAMP_IER_TAMP5IE_Msk
24384 #define TAMP_IER_TAMP6IE_Pos                (5U)
24385 #define TAMP_IER_TAMP6IE_Msk                (0x1UL << TAMP_IER_TAMP6IE_Pos)         /*!< 0x00000020 */
24386 #define TAMP_IER_TAMP6IE                    TAMP_IER_TAMP6IE_Msk
24387 #define TAMP_IER_TAMP7IE_Pos                (6U)
24388 #define TAMP_IER_TAMP7IE_Msk                (0x1UL << TAMP_IER_TAMP7IE_Pos)         /*!< 0x00000040 */
24389 #define TAMP_IER_TAMP7IE                    TAMP_IER_TAMP7IE_Msk
24390 #define TAMP_IER_TAMP8IE_Pos                (7U)
24391 #define TAMP_IER_TAMP8IE_Msk                (0x1UL << TAMP_IER_TAMP8IE_Pos)         /*!< 0x00000080 */
24392 #define TAMP_IER_TAMP8IE                    TAMP_IER_TAMP8IE_Msk
24393 #define TAMP_IER_ITAMP1IE_Pos               (16U)
24394 #define TAMP_IER_ITAMP1IE_Msk               (0x1UL << TAMP_IER_ITAMP1IE_Pos)        /*!< 0x00010000 */
24395 #define TAMP_IER_ITAMP1IE                   TAMP_IER_ITAMP1IE_Msk
24396 #define TAMP_IER_ITAMP2IE_Pos               (17U)
24397 #define TAMP_IER_ITAMP2IE_Msk               (0x1UL << TAMP_IER_ITAMP2IE_Pos)        /*!< 0x00020000 */
24398 #define TAMP_IER_ITAMP2IE                   TAMP_IER_ITAMP2IE_Msk
24399 #define TAMP_IER_ITAMP3IE_Pos               (18U)
24400 #define TAMP_IER_ITAMP3IE_Msk               (0x1UL << TAMP_IER_ITAMP3IE_Pos)        /*!< 0x00040000 */
24401 #define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk
24402 #define TAMP_IER_ITAMP5IE_Pos               (20U)
24403 #define TAMP_IER_ITAMP5IE_Msk               (0x1UL << TAMP_IER_ITAMP5IE_Pos)        /*!< 0x00100000 */
24404 #define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk
24405 #define TAMP_IER_ITAMP6IE_Pos               (21U)
24406 #define TAMP_IER_ITAMP6IE_Msk               (0x1UL << TAMP_IER_ITAMP6IE_Pos)        /*!< 0x00200000 */
24407 #define TAMP_IER_ITAMP6IE                   TAMP_IER_ITAMP6IE_Msk
24408 #define TAMP_IER_ITAMP7IE_Pos               (22U)
24409 #define TAMP_IER_ITAMP7IE_Msk               (0x1UL << TAMP_IER_ITAMP7IE_Pos)        /*!< 0x00400000 */
24410 #define TAMP_IER_ITAMP7IE                   TAMP_IER_ITAMP7IE_Msk
24411 #define TAMP_IER_ITAMP8IE_Pos               (23U)
24412 #define TAMP_IER_ITAMP8IE_Msk               (0x1UL << TAMP_IER_ITAMP8IE_Pos)        /*!< 0x00800000 */
24413 #define TAMP_IER_ITAMP8IE                   TAMP_IER_ITAMP8IE_Msk
24414 #define TAMP_IER_ITAMP9IE_Pos               (24U)
24415 #define TAMP_IER_ITAMP9IE_Msk               (0x1UL << TAMP_IER_ITAMP9IE_Pos)        /*!< 0x01000000 */
24416 #define TAMP_IER_ITAMP9IE                   TAMP_IER_ITAMP9IE_Msk
24417 #define TAMP_IER_ITAMP11IE_Pos              (26U)
24418 #define TAMP_IER_ITAMP11IE_Msk              (0x1UL << TAMP_IER_ITAMP11IE_Pos)       /*!< 0x04000000 */
24419 #define TAMP_IER_ITAMP11IE                  TAMP_IER_ITAMP11IE_Msk
24420 #define TAMP_IER_ITAMP12IE_Pos              (27U)
24421 #define TAMP_IER_ITAMP12IE_Msk              (0x1UL << TAMP_IER_ITAMP12IE_Pos)       /*!< 0x08000000 */
24422 #define TAMP_IER_ITAMP12IE                  TAMP_IER_ITAMP12IE_Msk
24423 #define TAMP_IER_ITAMP13IE_Pos              (28U)
24424 #define TAMP_IER_ITAMP13IE_Msk              (0x1UL << TAMP_IER_ITAMP13IE_Pos)       /*!< 0x10000000 */
24425 #define TAMP_IER_ITAMP13IE                  TAMP_IER_ITAMP13IE_Msk
24426 
24427 /********************  Bits definition for TAMP_SR register  *****************/
24428 #define TAMP_SR_TAMP1F_Pos                  (0U)
24429 #define TAMP_SR_TAMP1F_Msk                  (0x1UL << TAMP_SR_TAMP1F_Pos)           /*!< 0x00000001 */
24430 #define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk
24431 #define TAMP_SR_TAMP2F_Pos                  (1U)
24432 #define TAMP_SR_TAMP2F_Msk                  (0x1UL << TAMP_SR_TAMP2F_Pos)           /*!< 0x00000002 */
24433 #define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk
24434 #define TAMP_SR_TAMP3F_Pos                  (2U)
24435 #define TAMP_SR_TAMP3F_Msk                  (0x1UL << TAMP_SR_TAMP3F_Pos)           /*!< 0x00000004 */
24436 #define TAMP_SR_TAMP3F                      TAMP_SR_TAMP3F_Msk
24437 #define TAMP_SR_TAMP4F_Pos                  (3U)
24438 #define TAMP_SR_TAMP4F_Msk                  (0x1UL << TAMP_SR_TAMP4F_Pos)           /*!< 0x00000008 */
24439 #define TAMP_SR_TAMP4F                      TAMP_SR_TAMP4F_Msk
24440 #define TAMP_SR_TAMP5F_Pos                  (4U)
24441 #define TAMP_SR_TAMP5F_Msk                  (0x1UL << TAMP_SR_TAMP5F_Pos)           /*!< 0x00000010 */
24442 #define TAMP_SR_TAMP5F                      TAMP_SR_TAMP5F_Msk
24443 #define TAMP_SR_TAMP6F_Pos                  (5U)
24444 #define TAMP_SR_TAMP6F_Msk                  (0x1UL << TAMP_SR_TAMP6F_Pos)           /*!< 0x00000020 */
24445 #define TAMP_SR_TAMP6F                      TAMP_SR_TAMP6F_Msk
24446 #define TAMP_SR_TAMP7F_Pos                  (6U)
24447 #define TAMP_SR_TAMP7F_Msk                  (0x1UL << TAMP_SR_TAMP7F_Pos)           /*!< 0x00000040 */
24448 #define TAMP_SR_TAMP7F                      TAMP_SR_TAMP7F_Msk
24449 #define TAMP_SR_TAMP8F_Pos                  (7U)
24450 #define TAMP_SR_TAMP8F_Msk                  (0x1UL << TAMP_SR_TAMP8F_Pos)           /*!< 0x00000080 */
24451 #define TAMP_SR_TAMP8F                      TAMP_SR_TAMP8F_Msk
24452 #define TAMP_SR_ITAMP1F_Pos                 (16U)
24453 #define TAMP_SR_ITAMP1F_Msk                 (0x1UL << TAMP_SR_ITAMP1F_Pos)          /*!< 0x00010000 */
24454 #define TAMP_SR_ITAMP1F                     TAMP_SR_ITAMP1F_Msk
24455 #define TAMP_SR_ITAMP2F_Pos                 (17U)
24456 #define TAMP_SR_ITAMP2F_Msk                 (0x1UL << TAMP_SR_ITAMP2F_Pos)          /*!< 0x00010000 */
24457 #define TAMP_SR_ITAMP2F                     TAMP_SR_ITAMP2F_Msk
24458 #define TAMP_SR_ITAMP3F_Pos                 (18U)
24459 #define TAMP_SR_ITAMP3F_Msk                 (0x1UL << TAMP_SR_ITAMP3F_Pos)          /*!< 0x00040000 */
24460 #define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk
24461 #define TAMP_SR_ITAMP5F_Pos                 (20U)
24462 #define TAMP_SR_ITAMP5F_Msk                 (0x1UL << TAMP_SR_ITAMP5F_Pos)          /*!< 0x00100000 */
24463 #define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk
24464 #define TAMP_SR_ITAMP6F_Pos                 (21U)
24465 #define TAMP_SR_ITAMP6F_Msk                 (0x1UL << TAMP_SR_ITAMP6F_Pos)          /*!< 0x00200000 */
24466 #define TAMP_SR_ITAMP6F                     TAMP_SR_ITAMP6F_Msk
24467 #define TAMP_SR_ITAMP7F_Pos                 (22U)
24468 #define TAMP_SR_ITAMP7F_Msk                 (0x1UL << TAMP_SR_ITAMP7F_Pos)          /*!< 0x00400000 */
24469 #define TAMP_SR_ITAMP7F                     TAMP_SR_ITAMP7F_Msk
24470 #define TAMP_SR_ITAMP8F_Pos                 (23U)
24471 #define TAMP_SR_ITAMP8F_Msk                 (0x1UL << TAMP_SR_ITAMP8F_Pos)          /*!< 0x00800000 */
24472 #define TAMP_SR_ITAMP8F                     TAMP_SR_ITAMP8F_Msk
24473 #define TAMP_SR_ITAMP9F_Pos                 (24U)
24474 #define TAMP_SR_ITAMP9F_Msk                 (0x1UL << TAMP_SR_ITAMP9F_Pos)          /*!< 0x01000000 */
24475 #define TAMP_SR_ITAMP9F                     TAMP_SR_ITAMP9F_Msk
24476 #define TAMP_SR_ITAMP11F_Pos                (26U)
24477 #define TAMP_SR_ITAMP11F_Msk                (0x1UL << TAMP_SR_ITAMP11F_Pos)         /*!< 0x04000000 */
24478 #define TAMP_SR_ITAMP11F                    TAMP_SR_ITAMP11F_Msk
24479 #define TAMP_SR_ITAMP12F_Pos                (27U)
24480 #define TAMP_SR_ITAMP12F_Msk                (0x1UL << TAMP_SR_ITAMP12F_Pos)         /*!< 0x08000000 */
24481 #define TAMP_SR_ITAMP12F                    TAMP_SR_ITAMP12F_Msk
24482 #define TAMP_SR_ITAMP13F_Pos                (28U)
24483 #define TAMP_SR_ITAMP13F_Msk                (0x1UL << TAMP_SR_ITAMP13F_Pos)         /*!< 0x10000000 */
24484 #define TAMP_SR_ITAMP13F                    TAMP_SR_ITAMP13F_Msk
24485 
24486 /********************  Bits definition for TAMP_MISR register  ****************/
24487 #define TAMP_MISR_TAMP1MF_Pos               (0U)
24488 #define TAMP_MISR_TAMP1MF_Msk               (0x1UL << TAMP_MISR_TAMP1MF_Pos)        /*!< 0x00000001 */
24489 #define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk
24490 #define TAMP_MISR_TAMP2MF_Pos               (1U)
24491 #define TAMP_MISR_TAMP2MF_Msk               (0x1UL << TAMP_MISR_TAMP2MF_Pos)        /*!< 0x00000002 */
24492 #define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk
24493 #define TAMP_MISR_TAMP3MF_Pos               (2U)
24494 #define TAMP_MISR_TAMP3MF_Msk               (0x1UL << TAMP_MISR_TAMP3MF_Pos)        /*!< 0x00000004 */
24495 #define TAMP_MISR_TAMP3MF                   TAMP_MISR_TAMP3MF_Msk
24496 #define TAMP_MISR_TAMP4MF_Pos               (3U)
24497 #define TAMP_MISR_TAMP4MF_Msk               (0x1UL << TAMP_MISR_TAMP4MF_Pos)        /*!< 0x00000008 */
24498 #define TAMP_MISR_TAMP4MF                   TAMP_MISR_TAMP4MF_Msk
24499 #define TAMP_MISR_TAMP5MF_Pos               (4U)
24500 #define TAMP_MISR_TAMP5MF_Msk               (0x1UL << TAMP_MISR_TAMP5MF_Pos)        /*!< 0x00000010 */
24501 #define TAMP_MISR_TAMP5MF                   TAMP_MISR_TAMP5MF_Msk
24502 #define TAMP_MISR_TAMP6MF_Pos               (5U)
24503 #define TAMP_MISR_TAMP6MF_Msk               (0x1UL << TAMP_MISR_TAMP6MF_Pos)        /*!< 0x00000020 */
24504 #define TAMP_MISR_TAMP6MF                   TAMP_MISR_TAMP6MF_Msk
24505 #define TAMP_MISR_TAMP7MF_Pos               (6U)
24506 #define TAMP_MISR_TAMP7MF_Msk               (0x1UL << TAMP_MISR_TAMP7MF_Pos)        /*!< 0x00000040 */
24507 #define TAMP_MISR_TAMP7MF                   TAMP_MISR_TAMP7MF_Msk
24508 #define TAMP_MISR_TAMP8MF_Pos               (7U)
24509 #define TAMP_MISR_TAMP8MF_Msk               (0x1UL << TAMP_MISR_TAMP8MF_Pos)        /*!< 0x00000080 */
24510 #define TAMP_MISR_TAMP8MF                   TAMP_MISR_TAMP8MF_Msk
24511 #define TAMP_MISR_ITAMP1MF_Pos              (16U)
24512 #define TAMP_MISR_ITAMP1MF_Msk              (0x1UL << TAMP_MISR_ITAMP1MF_Pos)       /*!< 0x00010000 */
24513 #define TAMP_MISR_ITAMP1MF                  TAMP_MISR_ITAMP1MF_Msk
24514 #define TAMP_MISR_ITAMP2MF_Pos              (17U)
24515 #define TAMP_MISR_ITAMP2MF_Msk              (0x1UL << TAMP_MISR_ITAMP2MF_Pos)       /*!< 0x00010000 */
24516 #define TAMP_MISR_ITAMP2MF                  TAMP_MISR_ITAMP2MF_Msk
24517 #define TAMP_MISR_ITAMP3MF_Pos              (18U)
24518 #define TAMP_MISR_ITAMP3MF_Msk              (0x1UL << TAMP_MISR_ITAMP3MF_Pos)       /*!< 0x00040000 */
24519 #define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk
24520 #define TAMP_MISR_ITAMP5MF_Pos              (20U)
24521 #define TAMP_MISR_ITAMP5MF_Msk              (0x1UL << TAMP_MISR_ITAMP5MF_Pos)       /*!< 0x00100000 */
24522 #define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk
24523 #define TAMP_MISR_ITAMP6MF_Pos              (21U)
24524 #define TAMP_MISR_ITAMP6MF_Msk              (0x1UL << TAMP_MISR_ITAMP6MF_Pos)       /*!< 0x00200000 */
24525 #define TAMP_MISR_ITAMP6MF                  TAMP_MISR_ITAMP6MF_Msk
24526 #define TAMP_MISR_ITAMP7MF_Pos              (22U)
24527 #define TAMP_MISR_ITAMP7MF_Msk              (0x1UL << TAMP_MISR_ITAMP7MF_Pos)       /*!< 0x00400000 */
24528 #define TAMP_MISR_ITAMP7MF                  TAMP_MISR_ITAMP7MF_Msk
24529 #define TAMP_MISR_ITAMP8MF_Pos              (23U)
24530 #define TAMP_MISR_ITAMP8MF_Msk              (0x1UL << TAMP_MISR_ITAMP8MF_Pos)       /*!< 0x00800000 */
24531 #define TAMP_MISR_ITAMP8MF                  TAMP_MISR_ITAMP8MF_Msk
24532 #define TAMP_MISR_ITAMP9MF_Pos              (24U)
24533 #define TAMP_MISR_ITAMP9MF_Msk              (0x1UL << TAMP_MISR_ITAMP9MF_Pos)       /*!< 0x01000000 */
24534 #define TAMP_MISR_ITAMP9MF                  TAMP_MISR_ITAMP9MF_Msk
24535 #define TAMP_MISR_ITAMP11MF_Pos             (26U)
24536 #define TAMP_MISR_ITAMP11MF_Msk             (0x1UL << TAMP_MISR_ITAMP11MF_Pos)      /*!< 0x04000000 */
24537 #define TAMP_MISR_ITAMP11MF                 TAMP_MISR_ITAMP11MF_Msk
24538 #define TAMP_MISR_ITAMP12MF_Pos             (27U)
24539 #define TAMP_MISR_ITAMP12MF_Msk             (0x1UL << TAMP_MISR_ITAMP12MF_Pos)      /*!< 0x08000000 */
24540 #define TAMP_MISR_ITAMP12MF                 TAMP_MISR_ITAMP12MF_Msk
24541 #define TAMP_MISR_ITAMP13MF_Pos             (28U)
24542 #define TAMP_MISR_ITAMP13MF_Msk             (0x1UL << TAMP_MISR_ITAMP13MF_Pos)      /*!< 0x10000000 */
24543 #define TAMP_MISR_ITAMP13MF                 TAMP_MISR_ITAMP13MF_Msk
24544 
24545 /********************  Bits definition for TAMP_SMISR register  ************ *****/
24546 #define TAMP_SMISR_TAMP1MF_Pos              (0U)
24547 #define TAMP_SMISR_TAMP1MF_Msk              (0x1UL << TAMP_SMISR_TAMP1MF_Pos)       /*!< 0x00000001 */
24548 #define TAMP_SMISR_TAMP1MF                  TAMP_SMISR_TAMP1MF_Msk
24549 #define TAMP_SMISR_TAMP2MF_Pos              (1U)
24550 #define TAMP_SMISR_TAMP2MF_Msk              (0x1UL << TAMP_SMISR_TAMP2MF_Pos)       /*!< 0x00000002 */
24551 #define TAMP_SMISR_TAMP2MF                  TAMP_SMISR_TAMP2MF_Msk
24552 #define TAMP_SMISR_TAMP3MF_Pos              (2U)
24553 #define TAMP_SMISR_TAMP3MF_Msk              (0x1UL << TAMP_SMISR_TAMP3MF_Pos)       /*!< 0x00000004 */
24554 #define TAMP_SMISR_TAMP3MF                  TAMP_SMISR_TAMP3MF_Msk
24555 #define TAMP_SMISR_TAMP4MF_Pos              (3U)
24556 #define TAMP_SMISR_TAMP4MF_Msk              (0x1UL << TAMP_SMISR_TAMP4MF_Pos)       /*!< 0x00000008 */
24557 #define TAMP_SMISR_TAMP4MF                  TAMP_SMISR_TAMP4MF_Msk
24558 #define TAMP_SMISR_TAMP5MF_Pos              (4U)
24559 #define TAMP_SMISR_TAMP5MF_Msk              (0x1UL << TAMP_SMISR_TAMP5MF_Pos)       /*!< 0x00000010 */
24560 #define TAMP_SMISR_TAMP5MF                  TAMP_SMISR_TAMP5MF_Msk
24561 #define TAMP_SMISR_TAMP6MF_Pos              (5U)
24562 #define TAMP_SMISR_TAMP6MF_Msk              (0x1UL << TAMP_SMISR_TAMP6MF_Pos)       /*!< 0x00000020 */
24563 #define TAMP_SMISR_TAMP6MF                  TAMP_SMISR_TAMP6MF_Msk
24564 #define TAMP_SMISR_TAMP7MF_Pos              (6U)
24565 #define TAMP_SMISR_TAMP7MF_Msk              (0x1UL << TAMP_SMISR_TAMP7MF_Pos)       /*!< 0x00000040 */
24566 #define TAMP_SMISR_TAMP7MF                  TAMP_SMISR_TAMP7MF_Msk
24567 #define TAMP_SMISR_TAMP8MF_Pos              (7U)
24568 #define TAMP_SMISR_TAMP8MF_Msk              (0x1UL << TAMP_SMISR_TAMP8MF_Pos)       /*!< 0x00000080 */
24569 #define TAMP_SMISR_TAMP8MF                  TAMP_SMISR_TAMP8MF_Msk
24570 #define TAMP_SMISR_ITAMP1MF_Pos             (16U)
24571 #define TAMP_SMISR_ITAMP1MF_Msk             (0x1UL << TAMP_SMISR_ITAMP1MF_Pos)      /*!< 0x00010000 */
24572 #define TAMP_SMISR_ITAMP1MF                 TAMP_SMISR_ITAMP1MF_Msk
24573 #define TAMP_SMISR_ITAMP2MF_Pos             (17U)
24574 #define TAMP_SMISR_ITAMP2MF_Msk             (0x1UL << TAMP_SMISR_ITAMP2MF_Pos)      /*!< 0x00010000 */
24575 #define TAMP_SMISR_ITAMP2MF                 TAMP_SMISR_ITAMP2MF_Msk
24576 #define TAMP_SMISR_ITAMP3MF_Pos             (18U)
24577 #define TAMP_SMISR_ITAMP3MF_Msk             (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
24578 #define TAMP_SMISR_ITAMP3MF                 TAMP_SMISR_ITAMP3MF_Msk
24579 #define TAMP_SMISR_ITAMP5MF_Pos             (20U)
24580 #define TAMP_SMISR_ITAMP5MF_Msk             (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
24581 #define TAMP_SMISR_ITAMP5MF                 TAMP_SMISR_ITAMP5MF_Msk
24582 #define TAMP_SMISR_ITAMP6MF_Pos             (21U)
24583 #define TAMP_SMISR_ITAMP6MF_Msk             (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
24584 #define TAMP_SMISR_ITAMP6MF                 TAMP_SMISR_ITAMP6MF_Msk
24585 #define TAMP_SMISR_ITAMP7MF_Pos             (22U)
24586 #define TAMP_SMISR_ITAMP7MF_Msk             (0x1UL << TAMP_SMISR_ITAMP7MF_Pos)      /*!< 0x00400000 */
24587 #define TAMP_SMISR_ITAMP7MF                 TAMP_SMISR_ITAMP7MF_Msk
24588 #define TAMP_SMISR_ITAMP8MF_Pos             (23U)
24589 #define TAMP_SMISR_ITAMP8MF_Msk             (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)      /*!< 0x00800000 */
24590 #define TAMP_SMISR_ITAMP8MF                 TAMP_SMISR_ITAMP8MF_Msk
24591 #define TAMP_SMISR_ITAMP9MF_Pos             (24U)
24592 #define TAMP_SMISR_ITAMP9MF_Msk             (0x1UL << TAMP_SMISR_ITAMP9MF_Pos)      /*!< 0x01000000 */
24593 #define TAMP_SMISR_ITAMP9MF                 TAMP_SMISR_ITAMP9MF_Msk
24594 #define TAMP_SMISR_ITAMP11MF_Pos            (26U)
24595 #define TAMP_SMISR_ITAMP11MF_Msk            (0x1UL << TAMP_SMISR_ITAMP11MF_Pos)     /*!< 0x04000000 */
24596 #define TAMP_SMISR_ITAMP11MF                TAMP_SMISR_ITAMP11MF_Msk
24597 #define TAMP_SMISR_ITAMP12MF_Pos            (27U)
24598 #define TAMP_SMISR_ITAMP12MF_Msk            (0x1UL << TAMP_SMISR_ITAMP12MF_Pos)     /*!< 0x08000000 */
24599 #define TAMP_SMISR_ITAMP12MF                TAMP_SMISR_ITAMP12MF_Msk
24600 #define TAMP_SMISR_ITAMP13MF_Pos            (28U)
24601 #define TAMP_SMISR_ITAMP13MF_Msk            (0x1UL << TAMP_SMISR_ITAMP13MF_Pos)     /*!< 0x10000000 */
24602 #define TAMP_SMISR_ITAMP13MF                TAMP_SMISR_ITAMP13MF_Msk
24603 
24604 /********************  Bits definition for TAMP_SCR register  *****************/
24605 #define TAMP_SCR_CTAMP1F_Pos                (0U)
24606 #define TAMP_SCR_CTAMP1F_Msk                (0x1UL << TAMP_SCR_CTAMP1F_Pos)         /*!< 0x00000001 */
24607 #define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk
24608 #define TAMP_SCR_CTAMP2F_Pos                (1U)
24609 #define TAMP_SCR_CTAMP2F_Msk                (0x1UL << TAMP_SCR_CTAMP2F_Pos)         /*!< 0x00000002 */
24610 #define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk
24611 #define TAMP_SCR_CTAMP3F_Pos                (2U)
24612 #define TAMP_SCR_CTAMP3F_Msk                (0x1UL << TAMP_SCR_CTAMP3F_Pos)         /*!< 0x00000004 */
24613 #define TAMP_SCR_CTAMP3F                    TAMP_SCR_CTAMP3F_Msk
24614 #define TAMP_SCR_CTAMP4F_Pos                (3U)
24615 #define TAMP_SCR_CTAMP4F_Msk                (0x1UL << TAMP_SCR_CTAMP4F_Pos)         /*!< 0x00000008 */
24616 #define TAMP_SCR_CTAMP4F                    TAMP_SCR_CTAMP4F_Msk
24617 #define TAMP_SCR_CTAMP5F_Pos                (4U)
24618 #define TAMP_SCR_CTAMP5F_Msk                (0x1UL << TAMP_SCR_CTAMP5F_Pos)         /*!< 0x00000010 */
24619 #define TAMP_SCR_CTAMP5F                    TAMP_SCR_CTAMP5F_Msk
24620 #define TAMP_SCR_CTAMP6F_Pos                (5U)
24621 #define TAMP_SCR_CTAMP6F_Msk                (0x1UL << TAMP_SCR_CTAMP6F_Pos)         /*!< 0x00000020 */
24622 #define TAMP_SCR_CTAMP6F                    TAMP_SCR_CTAMP6F_Msk
24623 #define TAMP_SCR_CTAMP7F_Pos                (6U)
24624 #define TAMP_SCR_CTAMP7F_Msk                (0x1UL << TAMP_SCR_CTAMP7F_Pos)         /*!< 0x00000040 */
24625 #define TAMP_SCR_CTAMP7F                    TAMP_SCR_CTAMP7F_Msk
24626 #define TAMP_SCR_CTAMP8F_Pos                (7U)
24627 #define TAMP_SCR_CTAMP8F_Msk                (0x1UL << TAMP_SCR_CTAMP8F_Pos)         /*!< 0x00000080 */
24628 #define TAMP_SCR_CTAMP8F                    TAMP_SCR_CTAMP8F_Msk
24629 #define TAMP_SCR_CITAMP1F_Pos               (16U)
24630 #define TAMP_SCR_CITAMP1F_Msk               (0x1UL << TAMP_SCR_CITAMP1F_Pos)        /*!< 0x00010000 */
24631 #define TAMP_SCR_CITAMP1F                   TAMP_SCR_CITAMP1F_Msk
24632 #define TAMP_SCR_CITAMP2F_Pos               (17U)
24633 #define TAMP_SCR_CITAMP2F_Msk               (0x1UL << TAMP_SCR_CITAMP2F_Pos)        /*!< 0x00010000 */
24634 #define TAMP_SCR_CITAMP2F                   TAMP_SCR_CITAMP2F_Msk
24635 #define TAMP_SCR_CITAMP3F_Pos               (18U)
24636 #define TAMP_SCR_CITAMP3F_Msk               (0x1UL << TAMP_SCR_CITAMP3F_Pos)        /*!< 0x00040000 */
24637 #define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk
24638 #define TAMP_SCR_CITAMP5F_Pos               (20U)
24639 #define TAMP_SCR_CITAMP5F_Msk               (0x1UL << TAMP_SCR_CITAMP5F_Pos)        /*!< 0x00100000 */
24640 #define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk
24641 #define TAMP_SCR_CITAMP6F_Pos               (21U)
24642 #define TAMP_SCR_CITAMP6F_Msk               (0x1UL << TAMP_SCR_CITAMP6F_Pos)        /*!< 0x00200000 */
24643 #define TAMP_SCR_CITAMP6F                   TAMP_SCR_CITAMP6F_Msk
24644 #define TAMP_SCR_CITAMP7F_Pos               (22U)
24645 #define TAMP_SCR_CITAMP7F_Msk               (0x1UL << TAMP_SCR_CITAMP7F_Pos)        /*!< 0x00400000 */
24646 #define TAMP_SCR_CITAMP7F                   TAMP_SCR_CITAMP7F_Msk
24647 #define TAMP_SCR_CITAMP8F_Pos               (23U)
24648 #define TAMP_SCR_CITAMP8F_Msk               (0x1UL << TAMP_SCR_CITAMP8F_Pos)        /*!< 0x00800000 */
24649 #define TAMP_SCR_CITAMP8F                   TAMP_SCR_CITAMP8F_Msk
24650 #define TAMP_SCR_CITAMP9F_Pos               (24U)
24651 #define TAMP_SCR_CITAMP9F_Msk               (0x1UL << TAMP_SCR_CITAMP9F_Pos)        /*!< 0x01000000 */
24652 #define TAMP_SCR_CITAMP9F                   TAMP_SCR_CITAMP9F_Msk
24653 #define TAMP_SCR_CITAMP11F_Pos              (26U)
24654 #define TAMP_SCR_CITAMP11F_Msk              (0x1UL << TAMP_SCR_CITAMP11F_Pos)       /*!< 0x04000000 */
24655 #define TAMP_SCR_CITAMP11F                  TAMP_SCR_CITAMP11F_Msk
24656 #define TAMP_SCR_CITAMP12F_Pos              (27U)
24657 #define TAMP_SCR_CITAMP12F_Msk              (0x1UL << TAMP_SCR_CITAMP12F_Pos)       /*!< 0x08000000 */
24658 #define TAMP_SCR_CITAMP12F                  TAMP_SCR_CITAMP12F_Msk
24659 #define TAMP_SCR_CITAMP13F_Pos              (28U)
24660 #define TAMP_SCR_CITAMP13F_Msk              (0x1UL << TAMP_SCR_CITAMP13F_Pos)       /*!< 0x10000000 */
24661 #define TAMP_SCR_CITAMP13F                  TAMP_SCR_CITAMP13F_Msk
24662 
24663 /********************  Bits definition for TAMP_COUNTR register  ***************/
24664 #define TAMP_COUNTR_Pos                     (16U)
24665 #define TAMP_COUNTR_Msk                     (0xFFFFUL << TAMP_COUNTR_Pos)           /*!< 0xFFFF0000 */
24666 #define TAMP_COUNTR                         TAMP_COUNTR_Msk
24667 
24668 /********************  Bits definition for TAMP_ERCFGR register  ***************/
24669 #define TAMP_ERCFGR0_Pos                    (0U)
24670 #define TAMP_ERCFGR0_Msk                    (0x1UL << TAMP_ERCFGR0_Pos)            /*!< 0x00000001 */
24671 #define TAMP_ERCFGR0                        TAMP_ERCFGR0_Msk
24672 
24673 /********************  Bits definition for TAMP_BKP0R register  ***************/
24674 #define TAMP_BKP0R_Pos                      (0U)
24675 #define TAMP_BKP0R_Msk                      (0xFFFFFFFFUL << TAMP_BKP0R_Pos)        /*!< 0xFFFFFFFF */
24676 #define TAMP_BKP0R                          TAMP_BKP0R_Msk
24677 
24678 /********************  Bits definition for TAMP_BKP1R register  ****************/
24679 #define TAMP_BKP1R_Pos                      (0U)
24680 #define TAMP_BKP1R_Msk                      (0xFFFFFFFFUL << TAMP_BKP1R_Pos)        /*!< 0xFFFFFFFF */
24681 #define TAMP_BKP1R                          TAMP_BKP1R_Msk
24682 
24683 /********************  Bits definition for TAMP_BKP2R register  ****************/
24684 #define TAMP_BKP2R_Pos                      (0U)
24685 #define TAMP_BKP2R_Msk                      (0xFFFFFFFFUL << TAMP_BKP2R_Pos)        /*!< 0xFFFFFFFF */
24686 #define TAMP_BKP2R                          TAMP_BKP2R_Msk
24687 
24688 /********************  Bits definition for TAMP_BKP3R register  ****************/
24689 #define TAMP_BKP3R_Pos                      (0U)
24690 #define TAMP_BKP3R_Msk                      (0xFFFFFFFFUL << TAMP_BKP3R_Pos)        /*!< 0xFFFFFFFF */
24691 #define TAMP_BKP3R                          TAMP_BKP3R_Msk
24692 
24693 /********************  Bits definition for TAMP_BKP4R register  ****************/
24694 #define TAMP_BKP4R_Pos                      (0U)
24695 #define TAMP_BKP4R_Msk                      (0xFFFFFFFFUL << TAMP_BKP4R_Pos)        /*!< 0xFFFFFFFF */
24696 #define TAMP_BKP4R                          TAMP_BKP4R_Msk
24697 
24698 /********************  Bits definition for TAMP_BKP5R register  ****************/
24699 #define TAMP_BKP5R_Pos                      (0U)
24700 #define TAMP_BKP5R_Msk                      (0xFFFFFFFFUL << TAMP_BKP5R_Pos)        /*!< 0xFFFFFFFF */
24701 #define TAMP_BKP5R                          TAMP_BKP5R_Msk
24702 
24703 /********************  Bits definition for TAMP_BKP6R register  ****************/
24704 #define TAMP_BKP6R_Pos                      (0U)
24705 #define TAMP_BKP6R_Msk                      (0xFFFFFFFFUL << TAMP_BKP6R_Pos)        /*!< 0xFFFFFFFF */
24706 #define TAMP_BKP6R                          TAMP_BKP6R_Msk
24707 
24708 /********************  Bits definition for TAMP_BKP7R register  ****************/
24709 #define TAMP_BKP7R_Pos                      (0U)
24710 #define TAMP_BKP7R_Msk                      (0xFFFFFFFFUL << TAMP_BKP7R_Pos)        /*!< 0xFFFFFFFF */
24711 #define TAMP_BKP7R                          TAMP_BKP7R_Msk
24712 
24713 /********************  Bits definition for TAMP_BKP8R register  ****************/
24714 #define TAMP_BKP8R_Pos                      (0U)
24715 #define TAMP_BKP8R_Msk                      (0xFFFFFFFFUL << TAMP_BKP8R_Pos)        /*!< 0xFFFFFFFF */
24716 #define TAMP_BKP8R                          TAMP_BKP8R_Msk
24717 
24718 /********************  Bits definition for TAMP_BKP9R register  ****************/
24719 #define TAMP_BKP9R_Pos                      (0U)
24720 #define TAMP_BKP9R_Msk                      (0xFFFFFFFFUL << TAMP_BKP9R_Pos)        /*!< 0xFFFFFFFF */
24721 #define TAMP_BKP9R                          TAMP_BKP9R_Msk
24722 
24723 /********************  Bits definition for TAMP_BKP10R register  ***************/
24724 #define TAMP_BKP10R_Pos                     (0U)
24725 #define TAMP_BKP10R_Msk                     (0xFFFFFFFFUL << TAMP_BKP10R_Pos)       /*!< 0xFFFFFFFF */
24726 #define TAMP_BKP10R                         TAMP_BKP10R_Msk
24727 
24728 /********************  Bits definition for TAMP_BKP11R register  ***************/
24729 #define TAMP_BKP11R_Pos                     (0U)
24730 #define TAMP_BKP11R_Msk                     (0xFFFFFFFFUL << TAMP_BKP11R_Pos)       /*!< 0xFFFFFFFF */
24731 #define TAMP_BKP11R                         TAMP_BKP11R_Msk
24732 
24733 /********************  Bits definition for TAMP_BKP12R register  ***************/
24734 #define TAMP_BKP12R_Pos                     (0U)
24735 #define TAMP_BKP12R_Msk                     (0xFFFFFFFFUL << TAMP_BKP12R_Pos)       /*!< 0xFFFFFFFF */
24736 #define TAMP_BKP12R                         TAMP_BKP12R_Msk
24737 
24738 /********************  Bits definition for TAMP_BKP13R register  ***************/
24739 #define TAMP_BKP13R_Pos                     (0U)
24740 #define TAMP_BKP13R_Msk                     (0xFFFFFFFFUL << TAMP_BKP13R_Pos)       /*!< 0xFFFFFFFF */
24741 #define TAMP_BKP13R                         TAMP_BKP13R_Msk
24742 
24743 /********************  Bits definition for TAMP_BKP14R register  ***************/
24744 #define TAMP_BKP14R_Pos                     (0U)
24745 #define TAMP_BKP14R_Msk                     (0xFFFFFFFFUL << TAMP_BKP14R_Pos)       /*!< 0xFFFFFFFF */
24746 #define TAMP_BKP14R                         TAMP_BKP14R_Msk
24747 
24748 /********************  Bits definition for TAMP_BKP15R register  ***************/
24749 #define TAMP_BKP15R_Pos                     (0U)
24750 #define TAMP_BKP15R_Msk                     (0xFFFFFFFFUL << TAMP_BKP15R_Pos)       /*!< 0xFFFFFFFF */
24751 #define TAMP_BKP15R                         TAMP_BKP15R_Msk
24752 
24753 /********************  Bits definition for TAMP_BKP16R register  ***************/
24754 #define TAMP_BKP16R_Pos                     (0U)
24755 #define TAMP_BKP16R_Msk                     (0xFFFFFFFFUL << TAMP_BKP16R_Pos)       /*!< 0xFFFFFFFF */
24756 #define TAMP_BKP16R                         TAMP_BKP16R_Msk
24757 
24758 /********************  Bits definition for TAMP_BKP17R register  ***************/
24759 #define TAMP_BKP17R_Pos                     (0U)
24760 #define TAMP_BKP17R_Msk                     (0xFFFFFFFFUL << TAMP_BKP17R_Pos)       /*!< 0xFFFFFFFF */
24761 #define TAMP_BKP17R                         TAMP_BKP17R_Msk
24762 
24763 /********************  Bits definition for TAMP_BKP18R register  ***************/
24764 #define TAMP_BKP18R_Pos                     (0U)
24765 #define TAMP_BKP18R_Msk                     (0xFFFFFFFFUL << TAMP_BKP18R_Pos)       /*!< 0xFFFFFFFF */
24766 #define TAMP_BKP18R                         TAMP_BKP18R_Msk
24767 
24768 /********************  Bits definition for TAMP_BKP19R register  ***************/
24769 #define TAMP_BKP19R_Pos                     (0U)
24770 #define TAMP_BKP19R_Msk                     (0xFFFFFFFFUL << TAMP_BKP19R_Pos)       /*!< 0xFFFFFFFF */
24771 #define TAMP_BKP19R                         TAMP_BKP19R_Msk
24772 
24773 /********************  Bits definition for TAMP_BKP20R register  ***************/
24774 #define TAMP_BKP20R_Pos                     (0U)
24775 #define TAMP_BKP20R_Msk                     (0xFFFFFFFFUL << TAMP_BKP20R_Pos)       /*!< 0xFFFFFFFF */
24776 #define TAMP_BKP20R                         TAMP_BKP20R_Msk
24777 
24778 /********************  Bits definition for TAMP_BKP21R register  ***************/
24779 #define TAMP_BKP21R_Pos                     (0U)
24780 #define TAMP_BKP21R_Msk                     (0xFFFFFFFFUL << TAMP_BKP21R_Pos)       /*!< 0xFFFFFFFF */
24781 #define TAMP_BKP21R                         TAMP_BKP21R_Msk
24782 
24783 /********************  Bits definition for TAMP_BKP22R register  ***************/
24784 #define TAMP_BKP22R_Pos                     (0U)
24785 #define TAMP_BKP22R_Msk                     (0xFFFFFFFFUL << TAMP_BKP22R_Pos)       /*!< 0xFFFFFFFF */
24786 #define TAMP_BKP22R                         TAMP_BKP22R_Msk
24787 
24788 /********************  Bits definition for TAMP_BKP23R register  ***************/
24789 #define TAMP_BKP23R_Pos                     (0U)
24790 #define TAMP_BKP23R_Msk                     (0xFFFFFFFFUL << TAMP_BKP23R_Pos)       /*!< 0xFFFFFFFF */
24791 #define TAMP_BKP23R                         TAMP_BKP23R_Msk
24792 
24793 /********************  Bits definition for TAMP_BKP24R register  ***************/
24794 #define TAMP_BKP24R_Pos                     (0U)
24795 #define TAMP_BKP24R_Msk                     (0xFFFFFFFFUL << TAMP_BKP24R_Pos)       /*!< 0xFFFFFFFF */
24796 #define TAMP_BKP24R                         TAMP_BKP24R_Msk
24797 
24798 /********************  Bits definition for TAMP_BKP25R register  ***************/
24799 #define TAMP_BKP25R_Pos                     (0U)
24800 #define TAMP_BKP25R_Msk                     (0xFFFFFFFFUL << TAMP_BKP25R_Pos)       /*!< 0xFFFFFFFF */
24801 #define TAMP_BKP25R                         TAMP_BKP25R_Msk
24802 
24803 /********************  Bits definition for TAMP_BKP26R register  ***************/
24804 #define TAMP_BKP26R_Pos                     (0U)
24805 #define TAMP_BKP26R_Msk                     (0xFFFFFFFFUL << TAMP_BKP26R_Pos)       /*!< 0xFFFFFFFF */
24806 #define TAMP_BKP26R                         TAMP_BKP26R_Msk
24807 
24808 /********************  Bits definition for TAMP_BKP27R register  ***************/
24809 #define TAMP_BKP27R_Pos                     (0U)
24810 #define TAMP_BKP27R_Msk                     (0xFFFFFFFFUL << TAMP_BKP27R_Pos)       /*!< 0xFFFFFFFF */
24811 #define TAMP_BKP27R                         TAMP_BKP27R_Msk
24812 
24813 /********************  Bits definition for TAMP_BKP28R register  ***************/
24814 #define TAMP_BKP28R_Pos                     (0U)
24815 #define TAMP_BKP28R_Msk                     (0xFFFFFFFFUL << TAMP_BKP28R_Pos)       /*!< 0xFFFFFFFF */
24816 #define TAMP_BKP28R                         TAMP_BKP28R_Msk
24817 
24818 /********************  Bits definition for TAMP_BKP29R register  ***************/
24819 #define TAMP_BKP29R_Pos                     (0U)
24820 #define TAMP_BKP29R_Msk                     (0xFFFFFFFFUL << TAMP_BKP29R_Pos)       /*!< 0xFFFFFFFF */
24821 #define TAMP_BKP29R                         TAMP_BKP29R_Msk
24822 
24823 /********************  Bits definition for TAMP_BKP30R register  ***************/
24824 #define TAMP_BKP30R_Pos                     (0U)
24825 #define TAMP_BKP30R_Msk                     (0xFFFFFFFFUL << TAMP_BKP30R_Pos)       /*!< 0xFFFFFFFF */
24826 #define TAMP_BKP30R                         TAMP_BKP30R_Msk
24827 
24828 /********************  Bits definition for TAMP_BKP31R register  ***************/
24829 #define TAMP_BKP31R_Pos                     (0U)
24830 #define TAMP_BKP31R_Msk                     (0xFFFFFFFFUL << TAMP_BKP31R_Pos)       /*!< 0xFFFFFFFF */
24831 #define TAMP_BKP31R                         TAMP_BKP31R_Msk
24832 
24833 /******************************************************************************/
24834 /*                                                                            */
24835 /*                          Touch Sensing Controller (TSC)                    */
24836 /*                                                                            */
24837 /******************************************************************************/
24838 /*******************  Bit definition for TSC_CR register  *********************/
24839 #define TSC_CR_TSCE_Pos          (0U)
24840 #define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                    /*!< 0x00000001 */
24841 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
24842 #define TSC_CR_START_Pos         (1U)
24843 #define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                   /*!< 0x00000002 */
24844 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
24845 #define TSC_CR_AM_Pos            (2U)
24846 #define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                      /*!< 0x00000004 */
24847 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
24848 #define TSC_CR_SYNCPOL_Pos       (3U)
24849 #define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                 /*!< 0x00000008 */
24850 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
24851 #define TSC_CR_IODEF_Pos         (4U)
24852 #define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                   /*!< 0x00000010 */
24853 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
24854 
24855 #define TSC_CR_MCV_Pos           (5U)
24856 #define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                     /*!< 0x000000E0 */
24857 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
24858 #define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                     /*!< 0x00000020 */
24859 #define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                     /*!< 0x00000040 */
24860 #define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                     /*!< 0x00000080 */
24861 
24862 #define TSC_CR_PGPSC_Pos         (12U)
24863 #define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00007000 */
24864 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
24865 #define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00001000 */
24866 #define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00002000 */
24867 #define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00004000 */
24868 
24869 #define TSC_CR_SSPSC_Pos         (15U)
24870 #define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                   /*!< 0x00008000 */
24871 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
24872 #define TSC_CR_SSE_Pos           (16U)
24873 #define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                     /*!< 0x00010000 */
24874 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
24875 
24876 #define TSC_CR_SSD_Pos           (17U)
24877 #define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                    /*!< 0x00FE0000 */
24878 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
24879 #define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                    /*!< 0x00020000 */
24880 #define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                    /*!< 0x00040000 */
24881 #define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                    /*!< 0x00080000 */
24882 #define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                    /*!< 0x00100000 */
24883 #define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                    /*!< 0x00200000 */
24884 #define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                    /*!< 0x00400000 */
24885 #define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                    /*!< 0x00800000 */
24886 
24887 #define TSC_CR_CTPL_Pos          (24U)
24888 #define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                    /*!< 0x0F000000 */
24889 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
24890 #define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                    /*!< 0x01000000 */
24891 #define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                    /*!< 0x02000000 */
24892 #define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                    /*!< 0x04000000 */
24893 #define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                    /*!< 0x08000000 */
24894 
24895 #define TSC_CR_CTPH_Pos          (28U)
24896 #define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                    /*!< 0xF0000000 */
24897 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
24898 #define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                    /*!< 0x10000000 */
24899 #define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                    /*!< 0x20000000 */
24900 #define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                    /*!< 0x40000000 */
24901 #define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                    /*!< 0x80000000 */
24902 
24903 /*******************  Bit definition for TSC_IER register  ********************/
24904 #define TSC_IER_EOAIE_Pos        (0U)
24905 #define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                  /*!< 0x00000001 */
24906 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
24907 #define TSC_IER_MCEIE_Pos        (1U)
24908 #define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                  /*!< 0x00000002 */
24909 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
24910 
24911 /*******************  Bit definition for TSC_ICR register  ********************/
24912 #define TSC_ICR_EOAIC_Pos        (0U)
24913 #define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                  /*!< 0x00000001 */
24914 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
24915 #define TSC_ICR_MCEIC_Pos        (1U)
24916 #define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                  /*!< 0x00000002 */
24917 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
24918 
24919 /*******************  Bit definition for TSC_ISR register  ********************/
24920 #define TSC_ISR_EOAF_Pos         (0U)
24921 #define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                   /*!< 0x00000001 */
24922 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
24923 #define TSC_ISR_MCEF_Pos         (1U)
24924 #define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                   /*!< 0x00000002 */
24925 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
24926 
24927 /*******************  Bit definition for TSC_IOHCR register  ******************/
24928 #define TSC_IOHCR_G1_IO1_Pos     (0U)
24929 #define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)               /*!< 0x00000001 */
24930 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
24931 #define TSC_IOHCR_G1_IO2_Pos     (1U)
24932 #define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)               /*!< 0x00000002 */
24933 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
24934 #define TSC_IOHCR_G1_IO3_Pos     (2U)
24935 #define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)               /*!< 0x00000004 */
24936 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
24937 #define TSC_IOHCR_G1_IO4_Pos     (3U)
24938 #define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)               /*!< 0x00000008 */
24939 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
24940 #define TSC_IOHCR_G2_IO1_Pos     (4U)
24941 #define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)               /*!< 0x00000010 */
24942 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
24943 #define TSC_IOHCR_G2_IO2_Pos     (5U)
24944 #define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)               /*!< 0x00000020 */
24945 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
24946 #define TSC_IOHCR_G2_IO3_Pos     (6U)
24947 #define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)               /*!< 0x00000040 */
24948 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
24949 #define TSC_IOHCR_G2_IO4_Pos     (7U)
24950 #define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)               /*!< 0x00000080 */
24951 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
24952 #define TSC_IOHCR_G3_IO1_Pos     (8U)
24953 #define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)               /*!< 0x00000100 */
24954 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
24955 #define TSC_IOHCR_G3_IO2_Pos     (9U)
24956 #define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)               /*!< 0x00000200 */
24957 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
24958 #define TSC_IOHCR_G3_IO3_Pos     (10U)
24959 #define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)               /*!< 0x00000400 */
24960 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
24961 #define TSC_IOHCR_G3_IO4_Pos     (11U)
24962 #define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)               /*!< 0x00000800 */
24963 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
24964 #define TSC_IOHCR_G4_IO1_Pos     (12U)
24965 #define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)               /*!< 0x00001000 */
24966 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
24967 #define TSC_IOHCR_G4_IO2_Pos     (13U)
24968 #define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)               /*!< 0x00002000 */
24969 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
24970 #define TSC_IOHCR_G4_IO3_Pos     (14U)
24971 #define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)               /*!< 0x00004000 */
24972 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
24973 #define TSC_IOHCR_G4_IO4_Pos     (15U)
24974 #define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)               /*!< 0x00008000 */
24975 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
24976 #define TSC_IOHCR_G5_IO1_Pos     (16U)
24977 #define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)               /*!< 0x00010000 */
24978 #define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
24979 #define TSC_IOHCR_G5_IO2_Pos     (17U)
24980 #define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)               /*!< 0x00020000 */
24981 #define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
24982 #define TSC_IOHCR_G5_IO3_Pos     (18U)
24983 #define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)               /*!< 0x00040000 */
24984 #define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
24985 #define TSC_IOHCR_G5_IO4_Pos     (19U)
24986 #define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)               /*!< 0x00080000 */
24987 #define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
24988 #define TSC_IOHCR_G6_IO1_Pos     (20U)
24989 #define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)               /*!< 0x00100000 */
24990 #define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
24991 #define TSC_IOHCR_G6_IO2_Pos     (21U)
24992 #define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)               /*!< 0x00200000 */
24993 #define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
24994 #define TSC_IOHCR_G6_IO3_Pos     (22U)
24995 #define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)               /*!< 0x00400000 */
24996 #define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
24997 #define TSC_IOHCR_G6_IO4_Pos     (23U)
24998 #define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)               /*!< 0x00800000 */
24999 #define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
25000 #define TSC_IOHCR_G7_IO1_Pos     (24U)
25001 #define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)               /*!< 0x01000000 */
25002 #define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
25003 #define TSC_IOHCR_G7_IO2_Pos     (25U)
25004 #define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)               /*!< 0x02000000 */
25005 #define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
25006 #define TSC_IOHCR_G7_IO3_Pos     (26U)
25007 #define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)               /*!< 0x04000000 */
25008 #define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
25009 #define TSC_IOHCR_G7_IO4_Pos     (27U)
25010 #define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)               /*!< 0x08000000 */
25011 #define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
25012 #define TSC_IOHCR_G8_IO1_Pos     (28U)
25013 #define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)               /*!< 0x10000000 */
25014 #define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
25015 #define TSC_IOHCR_G8_IO2_Pos     (29U)
25016 #define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)               /*!< 0x20000000 */
25017 #define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
25018 #define TSC_IOHCR_G8_IO3_Pos     (30U)
25019 #define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)               /*!< 0x40000000 */
25020 #define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
25021 #define TSC_IOHCR_G8_IO4_Pos     (31U)
25022 #define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)               /*!< 0x80000000 */
25023 #define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
25024 
25025 /*******************  Bit definition for TSC_IOASCR register  *****************/
25026 #define TSC_IOASCR_G1_IO1_Pos    (0U)
25027 #define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)              /*!< 0x00000001 */
25028 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
25029 #define TSC_IOASCR_G1_IO2_Pos    (1U)
25030 #define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)              /*!< 0x00000002 */
25031 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
25032 #define TSC_IOASCR_G1_IO3_Pos    (2U)
25033 #define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)              /*!< 0x00000004 */
25034 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
25035 #define TSC_IOASCR_G1_IO4_Pos    (3U)
25036 #define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)              /*!< 0x00000008 */
25037 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
25038 #define TSC_IOASCR_G2_IO1_Pos    (4U)
25039 #define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)              /*!< 0x00000010 */
25040 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
25041 #define TSC_IOASCR_G2_IO2_Pos    (5U)
25042 #define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)              /*!< 0x00000020 */
25043 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
25044 #define TSC_IOASCR_G2_IO3_Pos    (6U)
25045 #define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)              /*!< 0x00000040 */
25046 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
25047 #define TSC_IOASCR_G2_IO4_Pos    (7U)
25048 #define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)              /*!< 0x00000080 */
25049 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
25050 #define TSC_IOASCR_G3_IO1_Pos    (8U)
25051 #define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)              /*!< 0x00000100 */
25052 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
25053 #define TSC_IOASCR_G3_IO2_Pos    (9U)
25054 #define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)              /*!< 0x00000200 */
25055 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
25056 #define TSC_IOASCR_G3_IO3_Pos    (10U)
25057 #define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)              /*!< 0x00000400 */
25058 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
25059 #define TSC_IOASCR_G3_IO4_Pos    (11U)
25060 #define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)              /*!< 0x00000800 */
25061 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
25062 #define TSC_IOASCR_G4_IO1_Pos    (12U)
25063 #define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)              /*!< 0x00001000 */
25064 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
25065 #define TSC_IOASCR_G4_IO2_Pos    (13U)
25066 #define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)              /*!< 0x00002000 */
25067 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
25068 #define TSC_IOASCR_G4_IO3_Pos    (14U)
25069 #define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)              /*!< 0x00004000 */
25070 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
25071 #define TSC_IOASCR_G4_IO4_Pos    (15U)
25072 #define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)              /*!< 0x00008000 */
25073 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
25074 #define TSC_IOASCR_G5_IO1_Pos    (16U)
25075 #define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)              /*!< 0x00010000 */
25076 #define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
25077 #define TSC_IOASCR_G5_IO2_Pos    (17U)
25078 #define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)              /*!< 0x00020000 */
25079 #define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
25080 #define TSC_IOASCR_G5_IO3_Pos    (18U)
25081 #define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)              /*!< 0x00040000 */
25082 #define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
25083 #define TSC_IOASCR_G5_IO4_Pos    (19U)
25084 #define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)              /*!< 0x00080000 */
25085 #define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
25086 #define TSC_IOASCR_G6_IO1_Pos    (20U)
25087 #define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)              /*!< 0x00100000 */
25088 #define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
25089 #define TSC_IOASCR_G6_IO2_Pos    (21U)
25090 #define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)              /*!< 0x00200000 */
25091 #define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
25092 #define TSC_IOASCR_G6_IO3_Pos    (22U)
25093 #define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)              /*!< 0x00400000 */
25094 #define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
25095 #define TSC_IOASCR_G6_IO4_Pos    (23U)
25096 #define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)              /*!< 0x00800000 */
25097 #define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
25098 #define TSC_IOASCR_G7_IO1_Pos    (24U)
25099 #define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)              /*!< 0x01000000 */
25100 #define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
25101 #define TSC_IOASCR_G7_IO2_Pos    (25U)
25102 #define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)              /*!< 0x02000000 */
25103 #define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
25104 #define TSC_IOASCR_G7_IO3_Pos    (26U)
25105 #define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)              /*!< 0x04000000 */
25106 #define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
25107 #define TSC_IOASCR_G7_IO4_Pos    (27U)
25108 #define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)              /*!< 0x08000000 */
25109 #define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
25110 #define TSC_IOASCR_G8_IO1_Pos    (28U)
25111 #define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)              /*!< 0x10000000 */
25112 #define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
25113 #define TSC_IOASCR_G8_IO2_Pos    (29U)
25114 #define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)              /*!< 0x20000000 */
25115 #define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
25116 #define TSC_IOASCR_G8_IO3_Pos    (30U)
25117 #define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)              /*!< 0x40000000 */
25118 #define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
25119 #define TSC_IOASCR_G8_IO4_Pos    (31U)
25120 #define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)              /*!< 0x80000000 */
25121 #define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
25122 
25123 /*******************  Bit definition for TSC_IOSCR register  ******************/
25124 #define TSC_IOSCR_G1_IO1_Pos     (0U)
25125 #define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)               /*!< 0x00000001 */
25126 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
25127 #define TSC_IOSCR_G1_IO2_Pos     (1U)
25128 #define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)               /*!< 0x00000002 */
25129 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
25130 #define TSC_IOSCR_G1_IO3_Pos     (2U)
25131 #define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)               /*!< 0x00000004 */
25132 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
25133 #define TSC_IOSCR_G1_IO4_Pos     (3U)
25134 #define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)               /*!< 0x00000008 */
25135 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
25136 #define TSC_IOSCR_G2_IO1_Pos     (4U)
25137 #define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)               /*!< 0x00000010 */
25138 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
25139 #define TSC_IOSCR_G2_IO2_Pos     (5U)
25140 #define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)               /*!< 0x00000020 */
25141 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
25142 #define TSC_IOSCR_G2_IO3_Pos     (6U)
25143 #define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)               /*!< 0x00000040 */
25144 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
25145 #define TSC_IOSCR_G2_IO4_Pos     (7U)
25146 #define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)               /*!< 0x00000080 */
25147 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
25148 #define TSC_IOSCR_G3_IO1_Pos     (8U)
25149 #define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)               /*!< 0x00000100 */
25150 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
25151 #define TSC_IOSCR_G3_IO2_Pos     (9U)
25152 #define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)               /*!< 0x00000200 */
25153 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
25154 #define TSC_IOSCR_G3_IO3_Pos     (10U)
25155 #define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)               /*!< 0x00000400 */
25156 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
25157 #define TSC_IOSCR_G3_IO4_Pos     (11U)
25158 #define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)               /*!< 0x00000800 */
25159 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
25160 #define TSC_IOSCR_G4_IO1_Pos     (12U)
25161 #define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)               /*!< 0x00001000 */
25162 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
25163 #define TSC_IOSCR_G4_IO2_Pos     (13U)
25164 #define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)               /*!< 0x00002000 */
25165 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
25166 #define TSC_IOSCR_G4_IO3_Pos     (14U)
25167 #define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)               /*!< 0x00004000 */
25168 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
25169 #define TSC_IOSCR_G4_IO4_Pos     (15U)
25170 #define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)               /*!< 0x00008000 */
25171 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
25172 #define TSC_IOSCR_G5_IO1_Pos     (16U)
25173 #define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)               /*!< 0x00010000 */
25174 #define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
25175 #define TSC_IOSCR_G5_IO2_Pos     (17U)
25176 #define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)               /*!< 0x00020000 */
25177 #define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
25178 #define TSC_IOSCR_G5_IO3_Pos     (18U)
25179 #define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)               /*!< 0x00040000 */
25180 #define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
25181 #define TSC_IOSCR_G5_IO4_Pos     (19U)
25182 #define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)               /*!< 0x00080000 */
25183 #define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
25184 #define TSC_IOSCR_G6_IO1_Pos     (20U)
25185 #define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)               /*!< 0x00100000 */
25186 #define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
25187 #define TSC_IOSCR_G6_IO2_Pos     (21U)
25188 #define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)               /*!< 0x00200000 */
25189 #define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
25190 #define TSC_IOSCR_G6_IO3_Pos     (22U)
25191 #define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)               /*!< 0x00400000 */
25192 #define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
25193 #define TSC_IOSCR_G6_IO4_Pos     (23U)
25194 #define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)               /*!< 0x00800000 */
25195 #define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
25196 #define TSC_IOSCR_G7_IO1_Pos     (24U)
25197 #define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)               /*!< 0x01000000 */
25198 #define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
25199 #define TSC_IOSCR_G7_IO2_Pos     (25U)
25200 #define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)               /*!< 0x02000000 */
25201 #define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
25202 #define TSC_IOSCR_G7_IO3_Pos     (26U)
25203 #define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)               /*!< 0x04000000 */
25204 #define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
25205 #define TSC_IOSCR_G7_IO4_Pos     (27U)
25206 #define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)               /*!< 0x08000000 */
25207 #define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
25208 #define TSC_IOSCR_G8_IO1_Pos     (28U)
25209 #define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)               /*!< 0x10000000 */
25210 #define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
25211 #define TSC_IOSCR_G8_IO2_Pos     (29U)
25212 #define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)               /*!< 0x20000000 */
25213 #define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
25214 #define TSC_IOSCR_G8_IO3_Pos     (30U)
25215 #define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)               /*!< 0x40000000 */
25216 #define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
25217 #define TSC_IOSCR_G8_IO4_Pos     (31U)
25218 #define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)               /*!< 0x80000000 */
25219 #define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
25220 
25221 /*******************  Bit definition for TSC_IOCCR register  ******************/
25222 #define TSC_IOCCR_G1_IO1_Pos     (0U)
25223 #define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)               /*!< 0x00000001 */
25224 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
25225 #define TSC_IOCCR_G1_IO2_Pos     (1U)
25226 #define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)               /*!< 0x00000002 */
25227 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
25228 #define TSC_IOCCR_G1_IO3_Pos     (2U)
25229 #define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)               /*!< 0x00000004 */
25230 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
25231 #define TSC_IOCCR_G1_IO4_Pos     (3U)
25232 #define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)               /*!< 0x00000008 */
25233 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
25234 #define TSC_IOCCR_G2_IO1_Pos     (4U)
25235 #define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)               /*!< 0x00000010 */
25236 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
25237 #define TSC_IOCCR_G2_IO2_Pos     (5U)
25238 #define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)               /*!< 0x00000020 */
25239 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
25240 #define TSC_IOCCR_G2_IO3_Pos     (6U)
25241 #define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)               /*!< 0x00000040 */
25242 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
25243 #define TSC_IOCCR_G2_IO4_Pos     (7U)
25244 #define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)               /*!< 0x00000080 */
25245 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
25246 #define TSC_IOCCR_G3_IO1_Pos     (8U)
25247 #define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)               /*!< 0x00000100 */
25248 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
25249 #define TSC_IOCCR_G3_IO2_Pos     (9U)
25250 #define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)               /*!< 0x00000200 */
25251 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
25252 #define TSC_IOCCR_G3_IO3_Pos     (10U)
25253 #define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)               /*!< 0x00000400 */
25254 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
25255 #define TSC_IOCCR_G3_IO4_Pos     (11U)
25256 #define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)               /*!< 0x00000800 */
25257 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
25258 #define TSC_IOCCR_G4_IO1_Pos     (12U)
25259 #define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)               /*!< 0x00001000 */
25260 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
25261 #define TSC_IOCCR_G4_IO2_Pos     (13U)
25262 #define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)               /*!< 0x00002000 */
25263 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
25264 #define TSC_IOCCR_G4_IO3_Pos     (14U)
25265 #define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)               /*!< 0x00004000 */
25266 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
25267 #define TSC_IOCCR_G4_IO4_Pos     (15U)
25268 #define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)               /*!< 0x00008000 */
25269 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
25270 #define TSC_IOCCR_G5_IO1_Pos     (16U)
25271 #define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)               /*!< 0x00010000 */
25272 #define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
25273 #define TSC_IOCCR_G5_IO2_Pos     (17U)
25274 #define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)               /*!< 0x00020000 */
25275 #define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
25276 #define TSC_IOCCR_G5_IO3_Pos     (18U)
25277 #define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)               /*!< 0x00040000 */
25278 #define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
25279 #define TSC_IOCCR_G5_IO4_Pos     (19U)
25280 #define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)               /*!< 0x00080000 */
25281 #define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
25282 #define TSC_IOCCR_G6_IO1_Pos     (20U)
25283 #define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)               /*!< 0x00100000 */
25284 #define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
25285 #define TSC_IOCCR_G6_IO2_Pos     (21U)
25286 #define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)               /*!< 0x00200000 */
25287 #define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
25288 #define TSC_IOCCR_G6_IO3_Pos     (22U)
25289 #define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)               /*!< 0x00400000 */
25290 #define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
25291 #define TSC_IOCCR_G6_IO4_Pos     (23U)
25292 #define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)               /*!< 0x00800000 */
25293 #define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
25294 #define TSC_IOCCR_G7_IO1_Pos     (24U)
25295 #define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)               /*!< 0x01000000 */
25296 #define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
25297 #define TSC_IOCCR_G7_IO2_Pos     (25U)
25298 #define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)               /*!< 0x02000000 */
25299 #define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
25300 #define TSC_IOCCR_G7_IO3_Pos     (26U)
25301 #define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)               /*!< 0x04000000 */
25302 #define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
25303 #define TSC_IOCCR_G7_IO4_Pos     (27U)
25304 #define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)               /*!< 0x08000000 */
25305 #define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
25306 #define TSC_IOCCR_G8_IO1_Pos     (28U)
25307 #define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)               /*!< 0x10000000 */
25308 #define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
25309 #define TSC_IOCCR_G8_IO2_Pos     (29U)
25310 #define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)               /*!< 0x20000000 */
25311 #define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
25312 #define TSC_IOCCR_G8_IO3_Pos     (30U)
25313 #define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)               /*!< 0x40000000 */
25314 #define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
25315 #define TSC_IOCCR_G8_IO4_Pos     (31U)
25316 #define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)               /*!< 0x80000000 */
25317 #define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
25318 
25319 /*******************  Bit definition for TSC_IOGCSR register  *****************/
25320 #define TSC_IOGCSR_G1E_Pos       (0U)
25321 #define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                 /*!< 0x00000001 */
25322 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
25323 #define TSC_IOGCSR_G2E_Pos       (1U)
25324 #define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                 /*!< 0x00000002 */
25325 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
25326 #define TSC_IOGCSR_G3E_Pos       (2U)
25327 #define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                 /*!< 0x00000004 */
25328 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
25329 #define TSC_IOGCSR_G4E_Pos       (3U)
25330 #define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                 /*!< 0x00000008 */
25331 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
25332 #define TSC_IOGCSR_G5E_Pos       (4U)
25333 #define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                 /*!< 0x00000010 */
25334 #define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
25335 #define TSC_IOGCSR_G6E_Pos       (5U)
25336 #define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                 /*!< 0x00000020 */
25337 #define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
25338 #define TSC_IOGCSR_G7E_Pos       (6U)
25339 #define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                 /*!< 0x00000040 */
25340 #define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
25341 #define TSC_IOGCSR_G8E_Pos       (7U)
25342 #define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                 /*!< 0x00000080 */
25343 #define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
25344 #define TSC_IOGCSR_G1S_Pos       (16U)
25345 #define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                 /*!< 0x00010000 */
25346 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
25347 #define TSC_IOGCSR_G2S_Pos       (17U)
25348 #define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                 /*!< 0x00020000 */
25349 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
25350 #define TSC_IOGCSR_G3S_Pos       (18U)
25351 #define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                 /*!< 0x00040000 */
25352 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
25353 #define TSC_IOGCSR_G4S_Pos       (19U)
25354 #define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                 /*!< 0x00080000 */
25355 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
25356 #define TSC_IOGCSR_G5S_Pos       (20U)
25357 #define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                 /*!< 0x00100000 */
25358 #define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
25359 #define TSC_IOGCSR_G6S_Pos       (21U)
25360 #define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                 /*!< 0x00200000 */
25361 #define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
25362 #define TSC_IOGCSR_G7S_Pos       (22U)
25363 #define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                 /*!< 0x00400000 */
25364 #define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
25365 #define TSC_IOGCSR_G8S_Pos       (23U)
25366 #define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                 /*!< 0x00800000 */
25367 #define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
25368 
25369 /*******************  Bit definition for TSC_IOGXCR register  *****************/
25370 #define TSC_IOGXCR_CNT_Pos       (0U)
25371 #define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)              /*!< 0x00003FFF */
25372 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
25373 
25374 /******************************************************************************/
25375 /*                                                                            */
25376 /*                          Serial Audio Interface                            */
25377 /*                                                                            */
25378 /******************************************************************************/
25379 /********************  Bit definition for SAI_GCR register  *******************/
25380 #define SAI_GCR_SYNCIN_Pos                  (0U)
25381 #define SAI_GCR_SYNCIN_Msk                  (0x3UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000003 */
25382 #define SAI_GCR_SYNCIN                      SAI_GCR_SYNCIN_Msk                      /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
25383 #define SAI_GCR_SYNCIN_0                    (0x1UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000001 */
25384 #define SAI_GCR_SYNCIN_1                    (0x2UL << SAI_GCR_SYNCIN_Pos)           /*!< 0x00000002 */
25385 #define SAI_GCR_SYNCOUT_Pos                 (4U)
25386 #define SAI_GCR_SYNCOUT_Msk                 (0x3UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000030 */
25387 #define SAI_GCR_SYNCOUT                     SAI_GCR_SYNCOUT_Msk                     /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
25388 #define SAI_GCR_SYNCOUT_0                   (0x1UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000010 */
25389 #define SAI_GCR_SYNCOUT_1                   (0x2UL << SAI_GCR_SYNCOUT_Pos)          /*!< 0x00000020 */
25390 
25391 /*******************  Bit definition for SAI_xCR1 register  *******************/
25392 #define SAI_xCR1_MODE_Pos                   (0U)
25393 #define SAI_xCR1_MODE_Msk                   (0x3UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000003 */
25394 #define SAI_xCR1_MODE                       SAI_xCR1_MODE_Msk                       /*!<MODE[1:0] bits (Audio Block Mode)           */
25395 #define SAI_xCR1_MODE_0                     (0x1UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000001 */
25396 #define SAI_xCR1_MODE_1                     (0x2UL << SAI_xCR1_MODE_Pos)            /*!< 0x00000002 */
25397 #define SAI_xCR1_PRTCFG_Pos                 (2U)
25398 #define SAI_xCR1_PRTCFG_Msk                 (0x3UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x0000000C */
25399 #define SAI_xCR1_PRTCFG                     SAI_xCR1_PRTCFG_Msk                     /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
25400 #define SAI_xCR1_PRTCFG_0                   (0x1UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000004 */
25401 #define SAI_xCR1_PRTCFG_1                   (0x2UL << SAI_xCR1_PRTCFG_Pos)          /*!< 0x00000008 */
25402 #define SAI_xCR1_DS_Pos                     (5U)
25403 #define SAI_xCR1_DS_Msk                     (0x7UL << SAI_xCR1_DS_Pos)              /*!< 0x000000E0 */
25404 #define SAI_xCR1_DS                         SAI_xCR1_DS_Msk                         /*!<DS[1:0] bits (Data Size) */
25405 #define SAI_xCR1_DS_0                       (0x1UL << SAI_xCR1_DS_Pos)              /*!< 0x00000020 */
25406 #define SAI_xCR1_DS_1                       (0x2UL << SAI_xCR1_DS_Pos)              /*!< 0x00000040 */
25407 #define SAI_xCR1_DS_2                       (0x4UL << SAI_xCR1_DS_Pos)              /*!< 0x00000080 */
25408 #define SAI_xCR1_LSBFIRST_Pos               (8U)
25409 #define SAI_xCR1_LSBFIRST_Msk               (0x1UL << SAI_xCR1_LSBFIRST_Pos)        /*!< 0x00000100 */
25410 #define SAI_xCR1_LSBFIRST                   SAI_xCR1_LSBFIRST_Msk                   /*!<LSB First Configuration  */
25411 #define SAI_xCR1_CKSTR_Pos                  (9U)
25412 #define SAI_xCR1_CKSTR_Msk                  (0x1UL << SAI_xCR1_CKSTR_Pos)           /*!< 0x00000200 */
25413 #define SAI_xCR1_CKSTR                      SAI_xCR1_CKSTR_Msk                      /*!<ClocK STRobing edge      */
25414 #define SAI_xCR1_SYNCEN_Pos                 (10U)
25415 #define SAI_xCR1_SYNCEN_Msk                 (0x3UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000C00 */
25416 #define SAI_xCR1_SYNCEN                     SAI_xCR1_SYNCEN_Msk                     /*!<SYNCEN[1:0](SYNChronization ENable) */
25417 #define SAI_xCR1_SYNCEN_0                   (0x1UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000400 */
25418 #define SAI_xCR1_SYNCEN_1                   (0x2UL << SAI_xCR1_SYNCEN_Pos)          /*!< 0x00000800 */
25419 #define SAI_xCR1_MONO_Pos                   (12U)
25420 #define SAI_xCR1_MONO_Msk                   (0x1UL << SAI_xCR1_MONO_Pos)            /*!< 0x00001000 */
25421 #define SAI_xCR1_MONO                       SAI_xCR1_MONO_Msk                       /*!<Mono mode                  */
25422 #define SAI_xCR1_OUTDRIV_Pos                (13U)
25423 #define SAI_xCR1_OUTDRIV_Msk                (0x1UL << SAI_xCR1_OUTDRIV_Pos)         /*!< 0x00002000 */
25424 #define SAI_xCR1_OUTDRIV                    SAI_xCR1_OUTDRIV_Msk                    /*!<Output Drive               */
25425 #define SAI_xCR1_SAIEN_Pos                  (16U)
25426 #define SAI_xCR1_SAIEN_Msk                  (0x1UL << SAI_xCR1_SAIEN_Pos)           /*!< 0x00010000 */
25427 #define SAI_xCR1_SAIEN                      SAI_xCR1_SAIEN_Msk                      /*!<Audio Block enable         */
25428 #define SAI_xCR1_DMAEN_Pos                  (17U)
25429 #define SAI_xCR1_DMAEN_Msk                  (0x1UL << SAI_xCR1_DMAEN_Pos)           /*!< 0x00020000 */
25430 #define SAI_xCR1_DMAEN                      SAI_xCR1_DMAEN_Msk                      /*!<DMA enable                 */
25431 #define SAI_xCR1_NODIV_Pos                  (19U)
25432 #define SAI_xCR1_NODIV_Msk                  (0x1UL << SAI_xCR1_NODIV_Pos)           /*!< 0x00080000 */
25433 #define SAI_xCR1_NODIV                      SAI_xCR1_NODIV_Msk                      /*!<No Divider Configuration   */
25434 #define SAI_xCR1_MCKDIV_Pos                 (20U)
25435 #define SAI_xCR1_MCKDIV_Msk                 (0x3FUL << SAI_xCR1_MCKDIV_Pos)         /*!< 0x03F00000 */
25436 #define SAI_xCR1_MCKDIV                     SAI_xCR1_MCKDIV_Msk                     /*!<MCKDIV[5:0] (Master ClocK Divider)  */
25437 #define SAI_xCR1_MCKDIV_0                   (0x00100000UL)                          /*!<Bit 0  */
25438 #define SAI_xCR1_MCKDIV_1                   (0x00200000UL)                          /*!<Bit 1  */
25439 #define SAI_xCR1_MCKDIV_2                   (0x00400000UL)                          /*!<Bit 2  */
25440 #define SAI_xCR1_MCKDIV_3                   (0x00800000UL)                          /*!<Bit 3  */
25441 #define SAI_xCR1_MCKDIV_4                   (0x01000000UL)                          /*!<Bit 4  */
25442 #define SAI_xCR1_MCKDIV_5                   (0x02000000UL)                          /*!<Bit 5  */
25443 #define SAI_xCR1_OSR_Pos                    (26U)
25444 #define SAI_xCR1_OSR_Msk                    (0x1UL << SAI_xCR1_OSR_Pos)             /*!< 0x04000000 */
25445 #define SAI_xCR1_OSR                        SAI_xCR1_OSR_Msk                        /*!<Oversampling ratio for master clock */
25446 #define SAI_xCR1_MCKEN_Pos                  (27U)
25447 #define SAI_xCR1_MCKEN_Msk                  (0x1UL << SAI_xCR1_MCKEN_Pos)           /*!< 0x08000000 */
25448 #define SAI_xCR1_MCKEN                      SAI_xCR1_MCKEN_Msk                      /*!<Master clock generation enable */
25449 
25450 /*******************  Bit definition for SAI_xCR2 register  *******************/
25451 #define SAI_xCR2_FTH_Pos                    (0U)
25452 #define SAI_xCR2_FTH_Msk                    (0x7UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000007 */
25453 #define SAI_xCR2_FTH                        SAI_xCR2_FTH_Msk                        /*!<FTH[2:0](Fifo THreshold)  */
25454 #define SAI_xCR2_FTH_0                      (0x1UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000001 */
25455 #define SAI_xCR2_FTH_1                      (0x2UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000002 */
25456 #define SAI_xCR2_FTH_2                      (0x4UL << SAI_xCR2_FTH_Pos)             /*!< 0x00000004 */
25457 #define SAI_xCR2_FFLUSH_Pos                 (3U)
25458 #define SAI_xCR2_FFLUSH_Msk                 (0x1UL << SAI_xCR2_FFLUSH_Pos)          /*!< 0x00000008 */
25459 #define SAI_xCR2_FFLUSH                     SAI_xCR2_FFLUSH_Msk                     /*!<Fifo FLUSH                       */
25460 #define SAI_xCR2_TRIS_Pos                   (4U)
25461 #define SAI_xCR2_TRIS_Msk                   (0x1UL << SAI_xCR2_TRIS_Pos)            /*!< 0x00000010 */
25462 #define SAI_xCR2_TRIS                       SAI_xCR2_TRIS_Msk                       /*!<TRIState Management on data line */
25463 #define SAI_xCR2_MUTE_Pos                   (5U)
25464 #define SAI_xCR2_MUTE_Msk                   (0x1UL << SAI_xCR2_MUTE_Pos)            /*!< 0x00000020 */
25465 #define SAI_xCR2_MUTE                       SAI_xCR2_MUTE_Msk                       /*!<Mute mode                        */
25466 #define SAI_xCR2_MUTEVAL_Pos                (6U)
25467 #define SAI_xCR2_MUTEVAL_Msk                (0x1UL << SAI_xCR2_MUTEVAL_Pos)         /*!< 0x00000040 */
25468 #define SAI_xCR2_MUTEVAL                    SAI_xCR2_MUTEVAL_Msk                    /*!<Muate value                      */
25469 #define SAI_xCR2_MUTECNT_Pos                (7U)
25470 #define SAI_xCR2_MUTECNT_Msk                (0x3FUL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001F80 */
25471 #define SAI_xCR2_MUTECNT                    SAI_xCR2_MUTECNT_Msk                    /*!<MUTECNT[5:0] (MUTE counter) */
25472 #define SAI_xCR2_MUTECNT_0                  (0x01UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000080 */
25473 #define SAI_xCR2_MUTECNT_1                  (0x02UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000100 */
25474 #define SAI_xCR2_MUTECNT_2                  (0x04UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000200 */
25475 #define SAI_xCR2_MUTECNT_3                  (0x08UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000400 */
25476 #define SAI_xCR2_MUTECNT_4                  (0x10UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00000800 */
25477 #define SAI_xCR2_MUTECNT_5                  (0x20UL << SAI_xCR2_MUTECNT_Pos)        /*!< 0x00001000 */
25478 #define SAI_xCR2_CPL_Pos                    (13U)
25479 #define SAI_xCR2_CPL_Msk                    (0x1UL << SAI_xCR2_CPL_Pos)             /*!< 0x00002000 */
25480 #define SAI_xCR2_CPL                        SAI_xCR2_CPL_Msk                        /*!<CPL mode                    */
25481 #define SAI_xCR2_COMP_Pos                   (14U)
25482 #define SAI_xCR2_COMP_Msk                   (0x3UL << SAI_xCR2_COMP_Pos)            /*!< 0x0000C000 */
25483 #define SAI_xCR2_COMP                       SAI_xCR2_COMP_Msk                       /*!<COMP[1:0] (Companding mode) */
25484 #define SAI_xCR2_COMP_0                     (0x1UL << SAI_xCR2_COMP_Pos)            /*!< 0x00004000 */
25485 #define SAI_xCR2_COMP_1                     (0x2UL << SAI_xCR2_COMP_Pos)            /*!< 0x00008000 */
25486 
25487 /******************  Bit definition for SAI_xFRCR register  *******************/
25488 #define SAI_xFRCR_FRL_Pos                   (0U)
25489 #define SAI_xFRCR_FRL_Msk                   (0xFFUL << SAI_xFRCR_FRL_Pos)           /*!< 0x000000FF */
25490 #define SAI_xFRCR_FRL                       SAI_xFRCR_FRL_Msk                       /*!<FRL[7:0](Frame length)  */
25491 #define SAI_xFRCR_FRL_0                     (0x01UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000001 */
25492 #define SAI_xFRCR_FRL_1                     (0x02UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000002 */
25493 #define SAI_xFRCR_FRL_2                     (0x04UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000004 */
25494 #define SAI_xFRCR_FRL_3                     (0x08UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000008 */
25495 #define SAI_xFRCR_FRL_4                     (0x10UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000010 */
25496 #define SAI_xFRCR_FRL_5                     (0x20UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000020 */
25497 #define SAI_xFRCR_FRL_6                     (0x40UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000040 */
25498 #define SAI_xFRCR_FRL_7                     (0x80UL << SAI_xFRCR_FRL_Pos)           /*!< 0x00000080 */
25499 #define SAI_xFRCR_FSALL_Pos                 (8U)
25500 #define SAI_xFRCR_FSALL_Msk                 (0x7FUL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00007F00 */
25501 #define SAI_xFRCR_FSALL                     SAI_xFRCR_FSALL_Msk                     /*!<FRL[6:0] (Frame synchronization active level length)  */
25502 #define SAI_xFRCR_FSALL_0                   (0x01UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000100 */
25503 #define SAI_xFRCR_FSALL_1                   (0x02UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000200 */
25504 #define SAI_xFRCR_FSALL_2                   (0x04UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000400 */
25505 #define SAI_xFRCR_FSALL_3                   (0x08UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00000800 */
25506 #define SAI_xFRCR_FSALL_4                   (0x10UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00001000 */
25507 #define SAI_xFRCR_FSALL_5                   (0x20UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00002000 */
25508 #define SAI_xFRCR_FSALL_6                   (0x40UL << SAI_xFRCR_FSALL_Pos)         /*!< 0x00004000 */
25509 #define SAI_xFRCR_FSDEF_Pos                 (16U)
25510 #define SAI_xFRCR_FSDEF_Msk                 (0x1UL << SAI_xFRCR_FSDEF_Pos)          /*!< 0x00010000 */
25511 #define SAI_xFRCR_FSDEF                     SAI_xFRCR_FSDEF_Msk                     /*!< Frame Synchronization Definition */
25512 #define SAI_xFRCR_FSPOL_Pos                 (17U)
25513 #define SAI_xFRCR_FSPOL_Msk                 (0x1UL << SAI_xFRCR_FSPOL_Pos)          /*!< 0x00020000 */
25514 #define SAI_xFRCR_FSPOL                     SAI_xFRCR_FSPOL_Msk                     /*!<Frame Synchronization POLarity    */
25515 #define SAI_xFRCR_FSOFF_Pos                 (18U)
25516 #define SAI_xFRCR_FSOFF_Msk                 (0x1UL << SAI_xFRCR_FSOFF_Pos)          /*!< 0x00040000 */
25517 #define SAI_xFRCR_FSOFF                     SAI_xFRCR_FSOFF_Msk                     /*!<Frame Synchronization OFFset      */
25518 
25519 /******************  Bit definition for SAI_xSLOTR register  *******************/
25520 #define SAI_xSLOTR_FBOFF_Pos                (0U)
25521 #define SAI_xSLOTR_FBOFF_Msk                (0x1FUL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x0000001F */
25522 #define SAI_xSLOTR_FBOFF                    SAI_xSLOTR_FBOFF_Msk                    /*!<FRL[4:0](First Bit Offset)  */
25523 #define SAI_xSLOTR_FBOFF_0                  (0x01UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000001 */
25524 #define SAI_xSLOTR_FBOFF_1                  (0x02UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000002 */
25525 #define SAI_xSLOTR_FBOFF_2                  (0x04UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000004 */
25526 #define SAI_xSLOTR_FBOFF_3                  (0x08UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000008 */
25527 #define SAI_xSLOTR_FBOFF_4                  (0x10UL << SAI_xSLOTR_FBOFF_Pos)        /*!< 0x00000010 */
25528 #define SAI_xSLOTR_SLOTSZ_Pos               (6U)
25529 #define SAI_xSLOTR_SLOTSZ_Msk               (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x000000C0 */
25530 #define SAI_xSLOTR_SLOTSZ                   SAI_xSLOTR_SLOTSZ_Msk                   /*!<SLOTSZ[1:0] (Slot size)  */
25531 #define SAI_xSLOTR_SLOTSZ_0                 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000040 */
25532 #define SAI_xSLOTR_SLOTSZ_1                 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)        /*!< 0x00000080 */
25533 #define SAI_xSLOTR_NBSLOT_Pos               (8U)
25534 #define SAI_xSLOTR_NBSLOT_Msk               (0xFUL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000F00 */
25535 #define SAI_xSLOTR_NBSLOT                   SAI_xSLOTR_NBSLOT_Msk                   /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
25536 #define SAI_xSLOTR_NBSLOT_0                 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000100 */
25537 #define SAI_xSLOTR_NBSLOT_1                 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000200 */
25538 #define SAI_xSLOTR_NBSLOT_2                 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000400 */
25539 #define SAI_xSLOTR_NBSLOT_3                 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)        /*!< 0x00000800 */
25540 #define SAI_xSLOTR_SLOTEN_Pos               (16U)
25541 #define SAI_xSLOTR_SLOTEN_Msk               (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)     /*!< 0xFFFF0000 */
25542 #define SAI_xSLOTR_SLOTEN                   SAI_xSLOTR_SLOTEN_Msk                   /*!<SLOTEN[15:0] (Slot Enable)  */
25543 
25544 /*******************  Bit definition for SAI_xIMR register  *******************/
25545 #define SAI_xIMR_OVRUDRIE_Pos               (0U)
25546 #define SAI_xIMR_OVRUDRIE_Msk               (0x1UL << SAI_xIMR_OVRUDRIE_Pos)        /*!< 0x00000001 */
25547 #define SAI_xIMR_OVRUDRIE                   SAI_xIMR_OVRUDRIE_Msk                   /*!<Overrun underrun interrupt enable                              */
25548 #define SAI_xIMR_MUTEDETIE_Pos              (1U)
25549 #define SAI_xIMR_MUTEDETIE_Msk              (0x1UL << SAI_xIMR_MUTEDETIE_Pos)       /*!< 0x00000002 */
25550 #define SAI_xIMR_MUTEDETIE                  SAI_xIMR_MUTEDETIE_Msk                  /*!<Mute detection interrupt enable                                */
25551 #define SAI_xIMR_WCKCFGIE_Pos               (2U)
25552 #define SAI_xIMR_WCKCFGIE_Msk               (0x1UL << SAI_xIMR_WCKCFGIE_Pos)        /*!< 0x00000004 */
25553 #define SAI_xIMR_WCKCFGIE                   SAI_xIMR_WCKCFGIE_Msk                   /*!<Wrong Clock Configuration interrupt enable                     */
25554 #define SAI_xIMR_FREQIE_Pos                 (3U)
25555 #define SAI_xIMR_FREQIE_Msk                 (0x1UL << SAI_xIMR_FREQIE_Pos)          /*!< 0x00000008 */
25556 #define SAI_xIMR_FREQIE                     SAI_xIMR_FREQIE_Msk                     /*!<FIFO request interrupt enable                                  */
25557 #define SAI_xIMR_CNRDYIE_Pos                (4U)
25558 #define SAI_xIMR_CNRDYIE_Msk                (0x1UL << SAI_xIMR_CNRDYIE_Pos)         /*!< 0x00000010 */
25559 #define SAI_xIMR_CNRDYIE                    SAI_xIMR_CNRDYIE_Msk                    /*!<Codec not ready interrupt enable                               */
25560 #define SAI_xIMR_AFSDETIE_Pos               (5U)
25561 #define SAI_xIMR_AFSDETIE_Msk               (0x1UL << SAI_xIMR_AFSDETIE_Pos)        /*!< 0x00000020 */
25562 #define SAI_xIMR_AFSDETIE                   SAI_xIMR_AFSDETIE_Msk                   /*!<Anticipated frame synchronization detection interrupt enable   */
25563 #define SAI_xIMR_LFSDETIE_Pos               (6U)
25564 #define SAI_xIMR_LFSDETIE_Msk               (0x1UL << SAI_xIMR_LFSDETIE_Pos)        /*!< 0x00000040 */
25565 #define SAI_xIMR_LFSDETIE                   SAI_xIMR_LFSDETIE_Msk                   /*!<Late frame synchronization detection interrupt enable          */
25566 
25567 /********************  Bit definition for SAI_xSR register  *******************/
25568 #define SAI_xSR_OVRUDR_Pos                  (0U)
25569 #define SAI_xSR_OVRUDR_Msk                  (0x1UL << SAI_xSR_OVRUDR_Pos)           /*!< 0x00000001 */
25570 #define SAI_xSR_OVRUDR                      SAI_xSR_OVRUDR_Msk                      /*!<Overrun underrun                               */
25571 #define SAI_xSR_MUTEDET_Pos                 (1U)
25572 #define SAI_xSR_MUTEDET_Msk                 (0x1UL << SAI_xSR_MUTEDET_Pos)          /*!< 0x00000002 */
25573 #define SAI_xSR_MUTEDET                     SAI_xSR_MUTEDET_Msk                     /*!<Mute detection                                 */
25574 #define SAI_xSR_WCKCFG_Pos                  (2U)
25575 #define SAI_xSR_WCKCFG_Msk                  (0x1UL << SAI_xSR_WCKCFG_Pos)           /*!< 0x00000004 */
25576 #define SAI_xSR_WCKCFG                      SAI_xSR_WCKCFG_Msk                      /*!<Wrong Clock Configuration                      */
25577 #define SAI_xSR_FREQ_Pos                    (3U)
25578 #define SAI_xSR_FREQ_Msk                    (0x1UL << SAI_xSR_FREQ_Pos)             /*!< 0x00000008 */
25579 #define SAI_xSR_FREQ                        SAI_xSR_FREQ_Msk                        /*!<FIFO request                                   */
25580 #define SAI_xSR_CNRDY_Pos                   (4U)
25581 #define SAI_xSR_CNRDY_Msk                   (0x1UL << SAI_xSR_CNRDY_Pos)            /*!< 0x00000010 */
25582 #define SAI_xSR_CNRDY                       SAI_xSR_CNRDY_Msk                       /*!<Codec not ready                                */
25583 #define SAI_xSR_AFSDET_Pos                  (5U)
25584 #define SAI_xSR_AFSDET_Msk                  (0x1UL << SAI_xSR_AFSDET_Pos)           /*!< 0x00000020 */
25585 #define SAI_xSR_AFSDET                      SAI_xSR_AFSDET_Msk                      /*!<Anticipated frame synchronization detection    */
25586 #define SAI_xSR_LFSDET_Pos                  (6U)
25587 #define SAI_xSR_LFSDET_Msk                  (0x1UL << SAI_xSR_LFSDET_Pos)           /*!< 0x00000040 */
25588 #define SAI_xSR_LFSDET                      SAI_xSR_LFSDET_Msk                      /*!<Late frame synchronization detection           */
25589 #define SAI_xSR_FLVL_Pos                    (16U)
25590 #define SAI_xSR_FLVL_Msk                    (0x7UL << SAI_xSR_FLVL_Pos)             /*!< 0x00070000 */
25591 #define SAI_xSR_FLVL                        SAI_xSR_FLVL_Msk                        /*!<FLVL[2:0] (FIFO Level Threshold)               */
25592 #define SAI_xSR_FLVL_0                      (0x1UL << SAI_xSR_FLVL_Pos)             /*!< 0x00010000 */
25593 #define SAI_xSR_FLVL_1                      (0x2UL << SAI_xSR_FLVL_Pos)             /*!< 0x00020000 */
25594 #define SAI_xSR_FLVL_2                      (0x4UL << SAI_xSR_FLVL_Pos)             /*!< 0x00040000 */
25595 
25596 /******************  Bit definition for SAI_xCLRFR register  ******************/
25597 #define SAI_xCLRFR_COVRUDR_Pos              (0U)
25598 #define SAI_xCLRFR_COVRUDR_Msk              (0x1UL << SAI_xCLRFR_COVRUDR_Pos)       /*!< 0x00000001 */
25599 #define SAI_xCLRFR_COVRUDR                  SAI_xCLRFR_COVRUDR_Msk                  /*!<Clear Overrun underrun                               */
25600 #define SAI_xCLRFR_CMUTEDET_Pos             (1U)
25601 #define SAI_xCLRFR_CMUTEDET_Msk             (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)      /*!< 0x00000002 */
25602 #define SAI_xCLRFR_CMUTEDET                 SAI_xCLRFR_CMUTEDET_Msk                 /*!<Clear Mute detection                                 */
25603 #define SAI_xCLRFR_CWCKCFG_Pos              (2U)
25604 #define SAI_xCLRFR_CWCKCFG_Msk              (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)       /*!< 0x00000004 */
25605 #define SAI_xCLRFR_CWCKCFG                  SAI_xCLRFR_CWCKCFG_Msk                  /*!<Clear Wrong Clock Configuration                      */
25606 #define SAI_xCLRFR_CFREQ_Pos                (3U)
25607 #define SAI_xCLRFR_CFREQ_Msk                (0x1UL << SAI_xCLRFR_CFREQ_Pos)         /*!< 0x00000008 */
25608 #define SAI_xCLRFR_CFREQ                    SAI_xCLRFR_CFREQ_Msk                    /*!<Clear FIFO request                                   */
25609 #define SAI_xCLRFR_CCNRDY_Pos               (4U)
25610 #define SAI_xCLRFR_CCNRDY_Msk               (0x1UL << SAI_xCLRFR_CCNRDY_Pos)        /*!< 0x00000010 */
25611 #define SAI_xCLRFR_CCNRDY                   SAI_xCLRFR_CCNRDY_Msk                   /*!<Clear Codec not ready                                */
25612 #define SAI_xCLRFR_CAFSDET_Pos              (5U)
25613 #define SAI_xCLRFR_CAFSDET_Msk              (0x1UL << SAI_xCLRFR_CAFSDET_Pos)       /*!< 0x00000020 */
25614 #define SAI_xCLRFR_CAFSDET                  SAI_xCLRFR_CAFSDET_Msk                  /*!<Clear Anticipated frame synchronization detection    */
25615 #define SAI_xCLRFR_CLFSDET_Pos              (6U)
25616 #define SAI_xCLRFR_CLFSDET_Msk              (0x1UL << SAI_xCLRFR_CLFSDET_Pos)       /*!< 0x00000040 */
25617 #define SAI_xCLRFR_CLFSDET                  SAI_xCLRFR_CLFSDET_Msk                  /*!<Clear Late frame synchronization detection           */
25618 
25619 /******************  Bit definition for SAI_xDR register  ******************/
25620 #define SAI_xDR_DATA_Pos                    (0U)
25621 #define SAI_xDR_DATA_Msk                    (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)      /*!< 0xFFFFFFFF */
25622 #define SAI_xDR_DATA                        SAI_xDR_DATA_Msk
25623 
25624 /******************  Bit definition for SAI_PDMCR register  *******************/
25625 #define SAI_PDMCR_PDMEN_Pos                 (0U)
25626 #define SAI_PDMCR_PDMEN_Msk                 (0x1UL << SAI_PDMCR_PDMEN_Pos)          /*!< 0x00000001 */
25627 #define SAI_PDMCR_PDMEN                     SAI_PDMCR_PDMEN_Msk                     /*!<PDM enable */
25628 #define SAI_PDMCR_MICNBR_Pos                (4U)
25629 #define SAI_PDMCR_MICNBR_Msk                (0x3UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000030 */
25630 #define SAI_PDMCR_MICNBR                    SAI_PDMCR_MICNBR_Msk                    /*!<MICNBR[1:0] (Number of microphones) */
25631 #define SAI_PDMCR_MICNBR_0                  (0x1UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000010 */
25632 #define SAI_PDMCR_MICNBR_1                  (0x2UL << SAI_PDMCR_MICNBR_Pos)         /*!< 0x00000020 */
25633 #define SAI_PDMCR_CKEN1_Pos                 (8U)
25634 #define SAI_PDMCR_CKEN1_Msk                 (0x1UL << SAI_PDMCR_CKEN1_Pos)          /*!< 0x00000100 */
25635 #define SAI_PDMCR_CKEN1                     SAI_PDMCR_CKEN1_Msk                     /*!<Clock 1 enable */
25636 #define SAI_PDMCR_CKEN2_Pos                 (9U)
25637 #define SAI_PDMCR_CKEN2_Msk                 (0x1UL << SAI_PDMCR_CKEN2_Pos)          /*!< 0x00000200 */
25638 #define SAI_PDMCR_CKEN2                     SAI_PDMCR_CKEN2_Msk                     /*!<Clock 2 enable */
25639 #define SAI_PDMCR_CKEN3_Pos                 (10U)
25640 #define SAI_PDMCR_CKEN3_Msk                 (0x1UL << SAI_PDMCR_CKEN3_Pos)          /*!< 0x00000400 */
25641 #define SAI_PDMCR_CKEN3                     SAI_PDMCR_CKEN3_Msk                     /*!<Clock 3 enable */
25642 #define SAI_PDMCR_CKEN4_Pos                 (11U)
25643 #define SAI_PDMCR_CKEN4_Msk                 (0x1UL << SAI_PDMCR_CKEN4_Pos)          /*!< 0x00000800 */
25644 #define SAI_PDMCR_CKEN4                     SAI_PDMCR_CKEN4_Msk                     /*!<Clock 4 enable */
25645 
25646 /******************  Bit definition for SAI_PDMDLY register  ******************/
25647 #define SAI_PDMDLY_DLYM1L_Pos               (0U)
25648 #define SAI_PDMDLY_DLYM1L_Msk               (0x7UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000007 */
25649 #define SAI_PDMDLY_DLYM1L                   SAI_PDMDLY_DLYM1L_Msk                   /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
25650 #define SAI_PDMDLY_DLYM1L_0                 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000001 */
25651 #define SAI_PDMDLY_DLYM1L_1                 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000002 */
25652 #define SAI_PDMDLY_DLYM1L_2                 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)        /*!< 0x00000004 */
25653 #define SAI_PDMDLY_DLYM1R_Pos               (4U)
25654 #define SAI_PDMDLY_DLYM1R_Msk               (0x7UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000070 */
25655 #define SAI_PDMDLY_DLYM1R                   SAI_PDMDLY_DLYM1R_Msk                   /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
25656 #define SAI_PDMDLY_DLYM1R_0                 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000010 */
25657 #define SAI_PDMDLY_DLYM1R_1                 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000020 */
25658 #define SAI_PDMDLY_DLYM1R_2                 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)        /*!< 0x00000040 */
25659 #define SAI_PDMDLY_DLYM2L_Pos               (8U)
25660 #define SAI_PDMDLY_DLYM2L_Msk               (0x7UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000700 */
25661 #define SAI_PDMDLY_DLYM2L                   SAI_PDMDLY_DLYM2L_Msk                   /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
25662 #define SAI_PDMDLY_DLYM2L_0                 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000100 */
25663 #define SAI_PDMDLY_DLYM2L_1                 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000200 */
25664 #define SAI_PDMDLY_DLYM2L_2                 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)        /*!< 0x00000400 */
25665 #define SAI_PDMDLY_DLYM2R_Pos               (12U)
25666 #define SAI_PDMDLY_DLYM2R_Msk               (0x7UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00007000 */
25667 #define SAI_PDMDLY_DLYM2R                   SAI_PDMDLY_DLYM2R_Msk                   /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
25668 #define SAI_PDMDLY_DLYM2R_0                 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00001000 */
25669 #define SAI_PDMDLY_DLYM2R_1                 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00002000 */
25670 #define SAI_PDMDLY_DLYM2R_2                 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)        /*!< 0x00004000 */
25671 #define SAI_PDMDLY_DLYM3L_Pos               (16U)
25672 #define SAI_PDMDLY_DLYM3L_Msk               (0x7UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00070000 */
25673 #define SAI_PDMDLY_DLYM3L                   SAI_PDMDLY_DLYM3L_Msk                   /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
25674 #define SAI_PDMDLY_DLYM3L_0                 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00010000 */
25675 #define SAI_PDMDLY_DLYM3L_1                 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00020000 */
25676 #define SAI_PDMDLY_DLYM3L_2                 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)        /*!< 0x00040000 */
25677 #define SAI_PDMDLY_DLYM3R_Pos               (20U)
25678 #define SAI_PDMDLY_DLYM3R_Msk               (0x7UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00700000 */
25679 #define SAI_PDMDLY_DLYM3R                   SAI_PDMDLY_DLYM3R_Msk                   /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
25680 #define SAI_PDMDLY_DLYM3R_0                 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00100000 */
25681 #define SAI_PDMDLY_DLYM3R_1                 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00200000 */
25682 #define SAI_PDMDLY_DLYM3R_2                 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)        /*!< 0x00400000 */
25683 #define SAI_PDMDLY_DLYM4L_Pos               (24U)
25684 #define SAI_PDMDLY_DLYM4L_Msk               (0x7UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x07000000 */
25685 #define SAI_PDMDLY_DLYM4L                   SAI_PDMDLY_DLYM4L_Msk                   /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
25686 #define SAI_PDMDLY_DLYM4L_0                 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x01000000 */
25687 #define SAI_PDMDLY_DLYM4L_1                 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x02000000 */
25688 #define SAI_PDMDLY_DLYM4L_2                 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)        /*!< 0x04000000 */
25689 #define SAI_PDMDLY_DLYM4R_Pos               (28U)
25690 #define SAI_PDMDLY_DLYM4R_Msk               (0x7UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x70000000 */
25691 #define SAI_PDMDLY_DLYM4R                   SAI_PDMDLY_DLYM4R_Msk                   /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
25692 #define SAI_PDMDLY_DLYM4R_0                 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x10000000 */
25693 #define SAI_PDMDLY_DLYM4R_1                 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x20000000 */
25694 #define SAI_PDMDLY_DLYM4R_2                 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)        /*!< 0x40000000 */
25695 
25696 /******************************************************************************/
25697 /*                                                                            */
25698 /*                                 SYSCFG                                     */
25699 /*                                                                            */
25700 /******************************************************************************/
25701 /******************  Bit definition for SYSCFG_SECRX register  ****************/
25702 #define SYSCFG_SECCFGR_SYSCFGSEC_Pos        (0U)
25703 #define SYSCFG_SECCFGR_SYSCFGSEC_Msk        (0x1UL << SYSCFG_SECCFGR_SYSCFGSEC_Pos) /*!< 0x00000001 */
25704 #define SYSCFG_SECCFGR_SYSCFGSEC            SYSCFG_SECCFGR_SYSCFGSEC_Msk            /*!< SYSCFG clock control security enable */
25705 #define SYSCFG_SECCFGR_CLASSBSEC_Pos        (1U)
25706 #define SYSCFG_SECCFGR_CLASSBSEC_Msk        (0x1UL << SYSCFG_SECCFGR_CLASSBSEC_Pos) /*!< 0x00000002 */
25707 #define SYSCFG_SECCFGR_CLASSBSEC            SYSCFG_SECCFGR_CLASSBSEC_Msk            /*!< ClassB SYSCFG security enable */
25708 #define SYSCFG_SECCFGR_FPUSEC_Pos           (3U)
25709 #define SYSCFG_SECCFGR_FPUSEC_Msk           (0x1UL << SYSCFG_SECCFGR_FPUSEC_Pos)    /*!< 0x00000008 */
25710 #define SYSCFG_SECCFGR_FPUSEC               SYSCFG_SECCFGR_FPUSEC_Msk               /*!< FPU SYSCFG security enable */
25711 
25712 /******************  Bit definition for SYSCFG_CFGR1 register  ****************/
25713 #define SYSCFG_CFGR1_BOOSTEN_Pos            (8U)
25714 #define SYSCFG_CFGR1_BOOSTEN_Msk            (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)     /*!< 0x00000100 */
25715 #define SYSCFG_CFGR1_BOOSTEN                SYSCFG_CFGR1_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */
25716 #define SYSCFG_CFGR1_ANASWVDD_Pos           (9U)
25717 #define SYSCFG_CFGR1_ANASWVDD_Msk           (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos)    /*!< 0x00000200 */
25718 #define SYSCFG_CFGR1_ANASWVDD               SYSCFG_CFGR1_ANASWVDD_Msk               /*!< GPIO analog switch control voltage selection */
25719 #define SYSCFG_CFGR1_PB6_FMP_Pos            (16U)
25720 #define SYSCFG_CFGR1_PB6_FMP_Msk            (0x1UL << SYSCFG_CFGR1_PB6_FMP_Pos)     /*!< 0x00010000 */
25721 #define SYSCFG_CFGR1_PB6_FMP                SYSCFG_CFGR1_PB6_FMP_Msk                /*!< PB6 Fast mode plus */
25722 #define SYSCFG_CFGR1_PB7_FMP_Pos            (17U)
25723 #define SYSCFG_CFGR1_PB7_FMP_Msk            (0x1UL << SYSCFG_CFGR1_PB7_FMP_Pos)     /*!< 0x00020000 */
25724 #define SYSCFG_CFGR1_PB7_FMP                SYSCFG_CFGR1_PB7_FMP_Msk                /*!< PB7 Fast mode plus */
25725 #define SYSCFG_CFGR1_PB8_FMP_Pos            (18U)
25726 #define SYSCFG_CFGR1_PB8_FMP_Msk            (0x1UL << SYSCFG_CFGR1_PB8_FMP_Pos)     /*!< 0x00040000 */
25727 #define SYSCFG_CFGR1_PB8_FMP                SYSCFG_CFGR1_PB8_FMP_Msk                /*!< PB8 Fast mode plus */
25728 #define SYSCFG_CFGR1_PB9_FMP_Pos            (19U)
25729 #define SYSCFG_CFGR1_PB9_FMP_Msk            (0x1UL << SYSCFG_CFGR1_PB9_FMP_Pos)     /*!< 0x00080000 */
25730 #define SYSCFG_CFGR1_PB9_FMP                SYSCFG_CFGR1_PB9_FMP_Msk                /*!< PB9 Fast mode plus */
25731 #define SYSCFG_CFGR1_ENDCAP_Pos             (24U)
25732 #define SYSCFG_CFGR1_ENDCAP_Msk             (0x3UL << SYSCFG_CFGR1_ENDCAP_Pos)      /*!< 0x03000000 */
25733 #define SYSCFG_CFGR1_ENDCAP                 SYSCFG_CFGR1_ENDCAP_Msk                 /*!< Enable decoupling capacitance on HSPI supply */
25734 #define SYSCFG_CFGR1_ENDCAP_0               (0x1UL << SYSCFG_CFGR1_ENDCAP_Pos)      /*!< 0x01000000 */
25735 #define SYSCFG_CFGR1_ENDCAP_1               (0x2UL << SYSCFG_CFGR1_ENDCAP_Pos)      /*!< 0x02000000 */
25736 #define SYSCFG_CFGR1_SRAMCACHED_Pos         (28U)
25737 #define SYSCFG_CFGR1_SRAMCACHED_Msk         (0x1UL << SYSCFG_CFGR1_SRAMCACHED_Pos)  /*!< 0x10000000 */
25738 #define SYSCFG_CFGR1_SRAMCACHED             SYSCFG_CFGR1_SRAMCACHED_Msk             /*!< Enable the cachability of internal SRAMx by the DCACHE2 */
25739 
25740 /******************  Bit definition for SYSCFG_FPUIMR register  ***************/
25741 #define SYSCFG_FPUIMR_FPU_IE_Pos            (0U)
25742 #define SYSCFG_FPUIMR_FPU_IE_Msk            (0x3FUL << SYSCFG_FPUIMR_FPU_IE_Pos)    /*!< 0x0000003F - */
25743 #define SYSCFG_FPUIMR_FPU_IE                SYSCFG_FPUIMR_FPU_IE_Msk                /*!<  All FPU interrupts enable */
25744 #define SYSCFG_FPUIMR_FPU_IE_0              (0x1UL << SYSCFG_FPUIMR_FPU_IE_Pos)     /*!< 0x00000001 - Invalid operation Interrupt enable */
25745 #define SYSCFG_FPUIMR_FPU_IE_1              (0x2UL << SYSCFG_FPUIMR_FPU_IE_Pos)     /*!< 0x00000002 - Divide-by-zero Interrupt enable */
25746 #define SYSCFG_FPUIMR_FPU_IE_2              (0x4UL << SYSCFG_FPUIMR_FPU_IE_Pos)     /*!< 0x00000004 - Underflow Interrupt enable */
25747 #define SYSCFG_FPUIMR_FPU_IE_3              (0x8UL << SYSCFG_FPUIMR_FPU_IE_Pos)     /*!< 0x00000008 - Overflow Interrupt enable */
25748 #define SYSCFG_FPUIMR_FPU_IE_4              (0x10UL << SYSCFG_FPUIMR_FPU_IE_Pos)    /*!< 0x00000010 - Input denormal Interrupt enable */
25749 #define SYSCFG_FPUIMR_FPU_IE_5              (0x20UL << SYSCFG_FPUIMR_FPU_IE_Pos)    /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */
25750 
25751 /******************  Bit definition for SYSCFG_CNSLCKR register  **************/
25752 #define SYSCFG_CNSLCKR_LOCKNSVTOR_Pos       (0U)
25753 #define SYSCFG_CNSLCKR_LOCKNSVTOR_Msk       (0x1UL << SYSCFG_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */
25754 #define SYSCFG_CNSLCKR_LOCKNSVTOR           SYSCFG_CNSLCKR_LOCKNSVTOR_Msk           /*!< Disable VTOR_NS register writes by SW or debug agent */
25755 #define SYSCFG_CNSLCKR_LOCKNSMPU_Pos        (1U)
25756 #define SYSCFG_CNSLCKR_LOCKNSMPU_Msk        (0x1UL << SYSCFG_CNSLCKR_LOCKNSMPU_Pos) /*!< 0x00000002 */
25757 #define SYSCFG_CNSLCKR_LOCKNSMPU            SYSCFG_CNSLCKR_LOCKNSMPU_Msk            /*!< Disable Non-Secure MPU registers writes by SW or debug agent */
25758 
25759 /******************  Bit definition for SYSCFG_CSLCKR register  ***************/
25760 #define SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos      (0U)
25761 #define SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk      (0x1UL << SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */
25762 #define SYSCFG_CSLCKR_LOCKSVTAIRCR          SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk          /*!< Disable changes to the secure vector table address, handling of system faults */
25763 #define SYSCFG_CSLCKR_LOCKSMPU_Pos          (1U)
25764 #define SYSCFG_CSLCKR_LOCKSMPU_Msk          (0x1UL << SYSCFG_CSLCKR_LOCKSMPU_Pos)   /*!< 0x00000002 */
25765 #define SYSCFG_CSLCKR_LOCKSMPU              SYSCFG_CSLCKR_LOCKSMPU_Msk              /*!< Disable changes to the secure MPU registers writes by SW or debug agent */
25766 #define SYSCFG_CSLCKR_LOCKSAU_Pos           (2U)
25767 #define SYSCFG_CSLCKR_LOCKSAU_Msk           (0x1UL << SYSCFG_CSLCKR_LOCKSAU_Pos)    /*!< 0x00000004 */
25768 #define SYSCFG_CSLCKR_LOCKSAU               SYSCFG_CSLCKR_LOCKSAU_Msk               /*!< Disable changes to SAU registers */
25769 
25770 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
25771 #define SYSCFG_CFGR2_CLL_Pos                (0U)
25772 #define SYSCFG_CFGR2_CLL_Msk                (0x1UL << SYSCFG_CFGR2_CLL_Pos)         /*!< 0x00000001 */
25773 #define SYSCFG_CFGR2_CLL                    SYSCFG_CFGR2_CLL_Msk                    /*!< Core Lockup Lock */
25774 #define SYSCFG_CFGR2_SPL_Pos                (1U)
25775 #define SYSCFG_CFGR2_SPL_Msk                (0x1UL << SYSCFG_CFGR2_SPL_Pos)         /*!< 0x00000002 */
25776 #define SYSCFG_CFGR2_SPL                    SYSCFG_CFGR2_SPL_Msk                    /*!< SRAM ECC Lock */
25777 #define SYSCFG_CFGR2_PVDL_Pos               (2U)
25778 #define SYSCFG_CFGR2_PVDL_Msk               (0x1UL << SYSCFG_CFGR2_PVDL_Pos)        /*!< 0x00000004 */
25779 #define SYSCFG_CFGR2_PVDL                   SYSCFG_CFGR2_PVDL_Msk                   /*!<  PVD Lock */
25780 #define SYSCFG_CFGR2_ECCL_Pos               (3U)
25781 #define SYSCFG_CFGR2_ECCL_Msk               (0x1UL << SYSCFG_CFGR2_ECCL_Pos)        /*!< 0x00000008 */
25782 #define SYSCFG_CFGR2_ECCL                   SYSCFG_CFGR2_ECCL_Msk                   /*!< ECC Lock*/
25783 
25784 /******************  Bit definition for SYSCFG_MESR register  ****************/
25785 #define SYSCFG_MESR_MCLR_Pos                (0U)
25786 #define SYSCFG_MESR_MCLR_Msk                (0x1UL << SYSCFG_MESR_MCLR_Pos)         /*!< 0x00000001 */
25787 #define SYSCFG_MESR_MCLR                    SYSCFG_MESR_MCLR_Msk                    /*!< Status of Erase after Reset */
25788 #define SYSCFG_MESR_IPMEE_Pos               (16U)
25789 #define SYSCFG_MESR_IPMEE_Msk               (0x1UL << SYSCFG_MESR_IPMEE_Pos)        /*!< 0x00010000 */
25790 #define SYSCFG_MESR_IPMEE                   SYSCFG_MESR_IPMEE_Msk                   /*!< Status of End of Erase for ICache and PKA RAMs */
25791 
25792 /******************  Bit definition for SYSCFG_CCCSR register  ****************/
25793 #define SYSCFG_CCCSR_EN1_Pos                (0U)
25794 #define SYSCFG_CCCSR_EN1_Msk                (0x1UL << SYSCFG_CCCSR_EN1_Pos)         /*!< 0x00000001 */
25795 #define SYSCFG_CCCSR_EN1                    SYSCFG_CCCSR_EN1_Msk                    /*!< Enable compensation cell for VDD power rail */
25796 #define SYSCFG_CCCSR_CS1_Pos                (1U)
25797 #define SYSCFG_CCCSR_CS1_Msk                (0x1UL << SYSCFG_CCCSR_CS1_Pos)         /*!< 0x00000002 */
25798 #define SYSCFG_CCCSR_CS1                    SYSCFG_CCCSR_CS1_Msk                    /*!< Code selection for VDD power rail */
25799 #define SYSCFG_CCCSR_EN2_Pos                (2U)
25800 #define SYSCFG_CCCSR_EN2_Msk                (0x1UL << SYSCFG_CCCSR_EN2_Pos)         /*!< 0x00000004 */
25801 #define SYSCFG_CCCSR_EN2                    SYSCFG_CCCSR_EN2_Msk                    /*!< Enable compensation cell for VDDIO power rail */
25802 #define SYSCFG_CCCSR_CS2_Pos                (3U)
25803 #define SYSCFG_CCCSR_CS2_Msk                (0x1UL << SYSCFG_CCCSR_CS2_Pos)         /*!< 0x00000008 */
25804 #define SYSCFG_CCCSR_CS2                    SYSCFG_CCCSR_CS2_Msk                    /*!< Code selection for VDDIO power rail */
25805 #define SYSCFG_CCCSR_EN3_Pos                (4U)
25806 #define SYSCFG_CCCSR_EN3_Msk                (0x1UL << SYSCFG_CCCSR_EN3_Pos)         /*!< 0x00000010 */
25807 #define SYSCFG_CCCSR_EN3                    SYSCFG_CCCSR_EN3_Msk                    /*!< Enable compensation cell for HSPI I/Os */
25808 #define SYSCFG_CCCSR_CS3_Pos                (5U)
25809 #define SYSCFG_CCCSR_CS3_Msk                (0x1UL << SYSCFG_CCCSR_CS3_Pos)         /*!< 0x00000020 */
25810 #define SYSCFG_CCCSR_CS3                    SYSCFG_CCCSR_CS3_Msk                    /*!< Code selection for HSPI I/Os */
25811 #define SYSCFG_CCCSR_RDY1_Pos               (8U)
25812 #define SYSCFG_CCCSR_RDY1_Msk               (0x1UL << SYSCFG_CCCSR_RDY1_Pos)        /*!< 0x00000100 */
25813 #define SYSCFG_CCCSR_RDY1                   SYSCFG_CCCSR_RDY1_Msk                   /*!< VDD compensation cell ready flag */
25814 #define SYSCFG_CCCSR_RDY2_Pos               (9U)
25815 #define SYSCFG_CCCSR_RDY2_Msk               (0x1UL << SYSCFG_CCCSR_RDY2_Pos)        /*!< 0x00000200 */
25816 #define SYSCFG_CCCSR_RDY2                   SYSCFG_CCCSR_RDY2_Msk                   /*!< VDDIO compensation cell ready flag */
25817 #define SYSCFG_CCCSR_RDY3_Pos               (10U)
25818 #define SYSCFG_CCCSR_RDY3_Msk               (0x1UL << SYSCFG_CCCSR_RDY3_Pos)        /*!< 0x00000400 */
25819 #define SYSCFG_CCCSR_RDY3                   SYSCFG_CCCSR_RDY3_Msk                   /*!< HSPI I/Os compensation cell ready flag */
25820 
25821 /******************  Bit definition for SYSCFG_CCVR register  ****************/
25822 #define SYSCFG_CCVR_NCV1_Pos                (0U)
25823 #define SYSCFG_CCVR_NCV1_Msk                (0xFUL << SYSCFG_CCVR_NCV1_Pos)         /*!< 0x0000000F */
25824 #define SYSCFG_CCVR_NCV1                    SYSCFG_CCVR_NCV1_Msk                    /*!< NMOS compensation value for VDD Power Rail */
25825 #define SYSCFG_CCVR_PCV1_Pos                (4U)
25826 #define SYSCFG_CCVR_PCV1_Msk                (0xFUL << SYSCFG_CCVR_PCV1_Pos)         /*!< 0x000000F0 */
25827 #define SYSCFG_CCVR_PCV1                    SYSCFG_CCVR_PCV1_Msk                    /*!< PMOS compensation value for VDD Power Rail */
25828 #define SYSCFG_CCVR_NCV2_Pos                (8U)
25829 #define SYSCFG_CCVR_NCV2_Msk                (0xFUL << SYSCFG_CCVR_NCV2_Pos)         /*!< 0x00000F00 */
25830 #define SYSCFG_CCVR_NCV2                    SYSCFG_CCVR_NCV2_Msk                    /*!< NMOS compensation value for VDDIO Power Rail */
25831 #define SYSCFG_CCVR_PCV2_Pos                (12U)
25832 #define SYSCFG_CCVR_PCV2_Msk                (0xFUL << SYSCFG_CCVR_PCV2_Pos)         /*!< 0x0000F000 */
25833 #define SYSCFG_CCVR_PCV2                    SYSCFG_CCVR_PCV2_Msk                    /*!< PMOS compensation value for VDDIO Power Rail */
25834 #define SYSCFG_CCVR_NCV3_Pos                (16U)
25835 #define SYSCFG_CCVR_NCV3_Msk                (0xFUL << SYSCFG_CCVR_NCV3_Pos)         /*!< 0x000F0000 */
25836 #define SYSCFG_CCVR_NCV3                    SYSCFG_CCVR_NCV3_Msk                    /*!< NMOS compensation value of the HSPI I/Os supplied by VDD */
25837 #define SYSCFG_CCVR_PCV3_Pos                (20U)
25838 #define SYSCFG_CCVR_PCV3_Msk                (0xFUL << SYSCFG_CCVR_PCV3_Pos)         /*!< 0x00F00000 */
25839 #define SYSCFG_CCVR_PCV3                    SYSCFG_CCVR_PCV3_Msk                    /*!< PMOS compensation value of the HSPI I/Os supplied by VDD */
25840 
25841 /******************  Bit definition for SYSCFG_CCCR register  ****************/
25842 #define SYSCFG_CCCR_NCC1_Pos                (0U)
25843 #define SYSCFG_CCCR_NCC1_Msk                (0xFUL << SYSCFG_CCCR_NCC1_Pos)         /*!< 0x0000000F */
25844 #define SYSCFG_CCCR_NCC1                    SYSCFG_CCCR_NCC1_Msk                    /*!< NMOS compensation code for VDD Power Rail */
25845 #define SYSCFG_CCCR_PCC1_Pos                (4U)
25846 #define SYSCFG_CCCR_PCC1_Msk                (0xFUL << SYSCFG_CCCR_PCC1_Pos)         /*!< 0x000000F0 */
25847 #define SYSCFG_CCCR_PCC1                    SYSCFG_CCCR_PCC1_Msk                    /*!< PMOS compensation code for VDD Power Rail */
25848 #define SYSCFG_CCCR_NCC2_Pos                (8U)
25849 #define SYSCFG_CCCR_NCC2_Msk                (0xFUL << SYSCFG_CCCR_NCC2_Pos)         /*!< 0x00000F00 */
25850 #define SYSCFG_CCCR_NCC2                    SYSCFG_CCCR_NCC2_Msk                    /*!< NMOS compensation code for VDDIO Power Rail */
25851 #define SYSCFG_CCCR_PCC2_Pos                (12U)
25852 #define SYSCFG_CCCR_PCC2_Msk                (0xFUL << SYSCFG_CCCR_PCC2_Pos)         /*!< 0x0000F000 */
25853 #define SYSCFG_CCCR_PCC2                    SYSCFG_CCCR_PCC2_Msk                    /*!< PMOS compensation code for VDDIO Power Rail */
25854 #define SYSCFG_CCCR_NCC3_Pos                (16U)
25855 #define SYSCFG_CCCR_NCC3_Msk                (0xFUL << SYSCFG_CCCR_NCC3_Pos)         /*!< 0x000F0000 */
25856 #define SYSCFG_CCCR_NCC3                    SYSCFG_CCCR_NCC3_Msk                    /*!< NMOS compensation code of the HSPI I/Os supplied by VDD */
25857 #define SYSCFG_CCCR_PCC3_Pos                (20U)
25858 #define SYSCFG_CCCR_PCC3_Msk                (0xFUL << SYSCFG_CCCR_PCC3_Pos)         /*!< 0x00F00000 */
25859 #define SYSCFG_CCCR_PCC3                    SYSCFG_CCCR_PCC3_Msk                    /*!< PMOS compensation code of the HSPI I/Os supplied by VDD */
25860 
25861 /******************  Bit definition for SYSCFG_RSSCMDR register  *************/
25862 #define SYSCFG_RSSCMDR_RSSCMD_Pos           (0U)
25863 #define SYSCFG_RSSCMDR_RSSCMD_Msk           (0xFFFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */
25864 #define SYSCFG_RSSCMDR_RSSCMD               SYSCFG_RSSCMDR_RSSCMD_Msk               /*!< RSS command */
25865 
25866 /******************  Bit definition for SYSCFG_OTGHSPHYCR register  *********/
25867 #define SYSCFG_OTGHSPHYCR_EN_Pos            (0U)
25868 #define SYSCFG_OTGHSPHYCR_EN_Msk            (0x1UL << SYSCFG_OTGHSPHYCR_EN_Pos)        /*!< 0x0000001 */
25869 #define SYSCFG_OTGHSPHYCR_EN                SYSCFG_OTGHSPHYCR_EN_Msk                   /*!< USB OTG_HS PHY enable */
25870 #define SYSCFG_OTGHSPHYCR_PDCTRL_Pos        (1U)
25871 #define SYSCFG_OTGHSPHYCR_PDCTRL_Msk        (0x1UL << SYSCFG_OTGHSPHYCR_PDCTRL_Pos)    /*!< 0x0000002 */
25872 #define SYSCFG_OTGHSPHYCR_PDCTRL            SYSCFG_OTGHSPHYCR_PDCTRL_Msk               /*!< USB OTG_HS PHY common block power-down control*/
25873 #define SYSCFG_OTGHSPHYCR_CLKSEL_Pos        (2U)
25874 #define SYSCFG_OTGHSPHYCR_CLKSEL_Msk        (0xFUL << SYSCFG_OTGHSPHYCR_CLKSEL_Pos)    /*!< 0x0000003C */
25875 #define SYSCFG_OTGHSPHYCR_CLKSEL            SYSCFG_OTGHSPHYCR_CLKSEL_Msk               /*!< USB OTG_HS PHY reference clock frequency selection */
25876 #define SYSCFG_OTGHSPHYCR_CLKSEL_0          (0x1UL << SYSCFG_OTGHSPHYCR_CLKSEL_Pos)    /*!< 0x00000004 */
25877 #define SYSCFG_OTGHSPHYCR_CLKSEL_1          (0x2UL << SYSCFG_OTGHSPHYCR_CLKSEL_Pos)    /*!< 0x00000008 */
25878 #define SYSCFG_OTGHSPHYCR_CLKSEL_2          (0x4UL << SYSCFG_OTGHSPHYCR_CLKSEL_Pos)    /*!< 0x00000010 */
25879 #define SYSCFG_OTGHSPHYCR_CLKSEL_3          (0x8UL << SYSCFG_OTGHSPHYCR_CLKSEL_Pos)    /*!< 0x00000020 */
25880 
25881 /******************  Bit definition for SYSCFG_OTGHSPHYTUNER2 register  *********/
25882 #define SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Pos     (0U)
25883 #define SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Msk     (0x7UL << SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Pos)     /*!< 0x0000007 */
25884 #define SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE         SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Msk                /*!< Disconnect threshold adjustment */
25885 #define SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0       (0x1UL << SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Pos)     /*!< 0x00000001 */
25886 #define SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1       (0x2UL << SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Pos)     /*!< 0x00000002 */
25887 #define SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_2       (0x4UL << SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Pos)     /*!< 0x00000004 */
25888 #define SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Pos        (4U)
25889 #define SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Msk        (0x7UL << SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Pos)        /*!< 0x00000070 */
25890 #define SYSCFG_OTGHSPHYTUNER2_SQRXTUNE            SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Msk                   /*!< Squelch threshold adjustment*/
25891 #define SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0          (0x1UL << SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Pos)        /*!< 0x00000010 */
25892 #define SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1          (0x2UL << SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Pos)        /*!< 0x00000020 */
25893 #define SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_2          (0x4UL << SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Pos)        /*!< 0x00000040 */
25894 #define SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_Pos (13U)
25895 #define SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_Msk (0x3UL << SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_Pos) /*!< 0x00006000 */
25896 #define SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE     SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_Msk            /*!< High-speed transmitter preemphasis current control */
25897 #define SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0   (0x1UL << SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_Pos) /*!< 0x00002000 */
25898 #define SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1   (0x2UL << SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_Pos) /*!< 0x00004000 */
25899 
25900 /*****************************************************************************/
25901 /*                                                                           */
25902 /*                        Global TrustZone Control                           */
25903 /*                                                                           */
25904 /*****************************************************************************/
25905 /*******************  Bits definition for GTZC_TZSC_CR register  ******************/
25906 #define GTZC_TZSC_CR_LCK_Pos                (0U)
25907 #define GTZC_TZSC_CR_LCK_Msk                (0x01UL << GTZC_TZSC_CR_LCK_Pos)        /*!< 0x00000001 */
25908 
25909 /*******************  Bits definition for GTZC_TZSC_MPCWM_CFGR register  **********/
25910 #define GTZC_TZSC_MPCWM_CFGR_SREN_Pos       (0U)
25911 #define GTZC_TZSC_MPCWM_CFGR_SREN_Msk       (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos)
25912 #define GTZC_TZSC_MPCWM_CFGR_SREN           GTZC_TZSC_MPCWM_CFGR_SREN_Msk
25913 #define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos     (1U)
25914 #define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk     (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos)
25915 #define GTZC_TZSC_MPCWM_CFGR_SRLOCK         GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk
25916 #define GTZC_TZSC_MPCWM_CFGR_SEC_Pos        (8U)
25917 #define GTZC_TZSC_MPCWM_CFGR_SEC_Msk        (0x1UL << GTZC_TZSC_MPCWM_CFGR_SEC_Pos)
25918 #define GTZC_TZSC_MPCWM_CFGR_SEC            GTZC_TZSC_MPCWM_CFGR_SEC_Msk
25919 #define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos       (9U)
25920 #define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk       (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos)
25921 #define GTZC_TZSC_MPCWM_CFGR_PRIV           GTZC_TZSC_MPCWM_CFGR_PRIV_Msk
25922 
25923 /*******************  Bits definition for GTZC_TZSC_MPCWMR register  **************/
25924 #define GTZC_TZSC_MPCWMR_SUBZ_START_Pos     (0U)
25925 #define GTZC_TZSC_MPCWMR_SUBZ_START_Msk     (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos)
25926 #define GTZC_TZSC_MPCWMR_SUBZ_START         GTZC_TZSC_MPCWMR_SUBZ_START_Msk
25927 #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos    (16U)
25928 #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk    (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos)
25929 #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH        GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk
25930 
25931 /*******  Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers  *****/
25932 /*******  Bits definition for TZIC _IERx/_SRx/_IFCRx registers  ********/
25933 
25934 /***************  Bits definition for register x=1 (GTZC1) *************/
25935 #define GTZC_CFGR1_TIM2_Pos                 (0U)
25936 #define GTZC_CFGR1_TIM2_Msk                 (0x01UL << GTZC_CFGR1_TIM2_Pos)
25937 #define GTZC_CFGR1_TIM3_Pos                 (1U)
25938 #define GTZC_CFGR1_TIM3_Msk                 (0x01UL << GTZC_CFGR1_TIM3_Pos)
25939 #define GTZC_CFGR1_TIM4_Pos                 (2U)
25940 #define GTZC_CFGR1_TIM4_Msk                 (0x01UL << GTZC_CFGR1_TIM4_Pos)
25941 #define GTZC_CFGR1_TIM5_Pos                 (3U)
25942 #define GTZC_CFGR1_TIM5_Msk                 (0x01UL << GTZC_CFGR1_TIM5_Pos)
25943 #define GTZC_CFGR1_TIM6_Pos                 (4U)
25944 #define GTZC_CFGR1_TIM6_Msk                 (0x01UL << GTZC_CFGR1_TIM6_Pos)
25945 #define GTZC_CFGR1_TIM7_Pos                 (5U)
25946 #define GTZC_CFGR1_TIM7_Msk                 (0x01UL << GTZC_CFGR1_TIM7_Pos)
25947 #define GTZC_CFGR1_WWDG_Pos                 (6U)
25948 #define GTZC_CFGR1_WWDG_Msk                 (0x01UL << GTZC_CFGR1_WWDG_Pos)
25949 #define GTZC_CFGR1_IWDG_Pos                 (7U)
25950 #define GTZC_CFGR1_IWDG_Msk                 (0x01UL << GTZC_CFGR1_IWDG_Pos)
25951 #define GTZC_CFGR1_SPI2_Pos                 (8U)
25952 #define GTZC_CFGR1_SPI2_Msk                 (0x01UL << GTZC_CFGR1_SPI2_Pos)
25953 #define GTZC_CFGR1_USART2_Pos               (9U)
25954 #define GTZC_CFGR1_USART2_Msk               (0x01UL << GTZC_CFGR1_USART2_Pos)
25955 #define GTZC_CFGR1_USART3_Pos               (10U)
25956 #define GTZC_CFGR1_USART3_Msk               (0x01UL << GTZC_CFGR1_USART3_Pos)
25957 #define GTZC_CFGR1_UART4_Pos                (11U)
25958 #define GTZC_CFGR1_UART4_Msk                (0x01UL << GTZC_CFGR1_UART4_Pos)
25959 #define GTZC_CFGR1_UART5_Pos                (12U)
25960 #define GTZC_CFGR1_UART5_Msk                (0x01UL << GTZC_CFGR1_UART5_Pos)
25961 #define GTZC_CFGR1_I2C1_Pos                 (13U)
25962 #define GTZC_CFGR1_I2C1_Msk                 (0x01UL << GTZC_CFGR1_I2C1_Pos)
25963 #define GTZC_CFGR1_I2C2_Pos                 (14U)
25964 #define GTZC_CFGR1_I2C2_Msk                 (0x01UL << GTZC_CFGR1_I2C2_Pos)
25965 #define GTZC_CFGR1_CRS_Pos                  (15U)
25966 #define GTZC_CFGR1_CRS_Msk                  (0x01UL << GTZC_CFGR1_CRS_Pos)
25967 #define GTZC_CFGR1_I2C4_Pos                 (16U)
25968 #define GTZC_CFGR1_I2C4_Msk                 (0x01UL << GTZC_CFGR1_I2C4_Pos)
25969 #define GTZC_CFGR1_LPTIM2_Pos               (17U)
25970 #define GTZC_CFGR1_LPTIM2_Msk               (0x01UL << GTZC_CFGR1_LPTIM2_Pos)
25971 #define GTZC_CFGR1_FDCAN1_Pos               (18U)
25972 #define GTZC_CFGR1_FDCAN1_Msk               (0x01UL << GTZC_CFGR1_FDCAN1_Pos)
25973 #define GTZC_CFGR1_UCPD1_Pos                (19U)
25974 #define GTZC_CFGR1_UCPD1_Msk                (0x01UL << GTZC_CFGR1_UCPD1_Pos)
25975 #define GTZC_CFGR1_USART6_Pos               (21U)
25976 #define GTZC_CFGR1_USART6_Msk               (0x01UL << GTZC_CFGR1_USART6_Pos)
25977 #define GTZC_CFGR1_I2C5_Pos                 (22U)
25978 #define GTZC_CFGR1_I2C5_Msk                 (0x01UL << GTZC_CFGR1_I2C5_Pos)
25979 #define GTZC_CFGR1_I2C6_Pos                 (23U)
25980 #define GTZC_CFGR1_I2C6_Msk                 (0x01UL << GTZC_CFGR1_I2C6_Pos)
25981 
25982 /***************  Bits definition for register x=2 (GTZC1) *************/
25983 #define GTZC_CFGR2_TIM1_Pos                 (0U)
25984 #define GTZC_CFGR2_TIM1_Msk                 (0x01UL << GTZC_CFGR2_TIM1_Pos)
25985 #define GTZC_CFGR2_SPI1_Pos                 (1U)
25986 #define GTZC_CFGR2_SPI1_Msk                 (0x01UL << GTZC_CFGR2_SPI1_Pos)
25987 #define GTZC_CFGR2_TIM8_Pos                 (2U)
25988 #define GTZC_CFGR2_TIM8_Msk                 (0x01UL << GTZC_CFGR2_TIM8_Pos)
25989 #define GTZC_CFGR2_USART1_Pos               (3U)
25990 #define GTZC_CFGR2_USART1_Msk               (0x01UL << GTZC_CFGR2_USART1_Pos)
25991 #define GTZC_CFGR2_TIM15_Pos                (4U)
25992 #define GTZC_CFGR2_TIM15_Msk                (0x01UL << GTZC_CFGR2_TIM15_Pos)
25993 #define GTZC_CFGR2_TIM16_Pos                (5U)
25994 #define GTZC_CFGR2_TIM16_Msk                (0x01UL << GTZC_CFGR2_TIM16_Pos)
25995 #define GTZC_CFGR2_TIM17_Pos                (6U)
25996 #define GTZC_CFGR2_TIM17_Msk                (0x01UL << GTZC_CFGR2_TIM17_Pos)
25997 #define GTZC_CFGR2_SAI1_Pos                 (7U)
25998 #define GTZC_CFGR2_SAI1_Msk                 (0x01UL << GTZC_CFGR2_SAI1_Pos)
25999 #define GTZC_CFGR2_SAI2_Pos                 (8U)
26000 #define GTZC_CFGR2_SAI2_Msk                 (0x01UL << GTZC_CFGR2_SAI2_Pos)
26001 #define GTZC_CFGR2_LTDCUSB_Pos              (9U)
26002 #define GTZC_CFGR2_LTDCUSB_Msk              (0x01UL << GTZC_CFGR2_LTDCUSB_Pos)
26003 #define GTZC_CFGR2_DSI_Pos                  (10U)
26004 #define GTZC_CFGR2_DSI_Msk                  (0x01UL << GTZC_CFGR2_DSI_Pos)
26005 #define GTZC_CFGR2_GFXTIM_Pos               (11U)
26006 #define GTZC_CFGR2_GFXTIM_Msk               (0x01UL << GTZC_CFGR2_GFXTIM_Pos)
26007 
26008 /***************  Bits definition for register x=3 (GTZC1) *************/
26009 #define GTZC_CFGR3_MDF1_Pos                 (0U)
26010 #define GTZC_CFGR3_MDF1_Msk                 (0x01UL << GTZC_CFGR3_MDF1_Pos)
26011 #define GTZC_CFGR3_CORDIC_Pos               (1U)
26012 #define GTZC_CFGR3_CORDIC_Msk               (0x01UL << GTZC_CFGR3_CORDIC_Pos)
26013 #define GTZC_CFGR3_FMAC_Pos                 (2U)
26014 #define GTZC_CFGR3_FMAC_Msk                 (0x01UL << GTZC_CFGR3_FMAC_Pos)
26015 #define GTZC_CFGR3_CRC_Pos                  (3U)
26016 #define GTZC_CFGR3_CRC_Msk                  (0x01UL << GTZC_CFGR3_CRC_Pos)
26017 #define GTZC_CFGR3_TSC_Pos                  (4U)
26018 #define GTZC_CFGR3_TSC_Msk                  (0x01UL << GTZC_CFGR3_TSC_Pos)
26019 #define GTZC_CFGR3_DMA2D_Pos                (5U)
26020 #define GTZC_CFGR3_DMA2D_Msk                (0x01UL << GTZC_CFGR3_DMA2D_Pos)
26021 #define GTZC_CFGR3_ICACHE_REG_Pos           (6U)
26022 #define GTZC_CFGR3_ICACHE_REG_Msk           (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos)
26023 #define GTZC_CFGR3_DCACHE1_REG_Pos          (7U)
26024 #define GTZC_CFGR3_DCACHE1_REG_Msk          (0x01UL << GTZC_CFGR3_DCACHE1_REG_Pos)
26025 #define GTZC_CFGR3_ADC12_Pos                (8U)
26026 #define GTZC_CFGR3_ADC12_Msk                (0x01UL << GTZC_CFGR3_ADC12_Pos)
26027 #define GTZC_CFGR3_DCMI_Pos                 (9U)
26028 #define GTZC_CFGR3_DCMI_Msk                 (0x01UL << GTZC_CFGR3_DCMI_Pos)
26029 #define GTZC_CFGR3_OTG_Pos                  (10U)
26030 #define GTZC_CFGR3_OTG_Msk                  (0x01UL << GTZC_CFGR3_OTG_Pos)
26031 #define GTZC_CFGR3_AES_Pos                  (11U)
26032 #define GTZC_CFGR3_AES_Msk                  (0x01UL << GTZC_CFGR3_AES_Pos)
26033 #define GTZC_CFGR3_HASH_Pos                 (12U)
26034 #define GTZC_CFGR3_HASH_Msk                 (0x01UL << GTZC_CFGR3_HASH_Pos)
26035 #define GTZC_CFGR3_RNG_Pos                  (13U)
26036 #define GTZC_CFGR3_RNG_Msk                  (0x01UL << GTZC_CFGR3_RNG_Pos)
26037 #define GTZC_CFGR3_PKA_Pos                  (14U)
26038 #define GTZC_CFGR3_PKA_Msk                  (0x01UL << GTZC_CFGR3_PKA_Pos)
26039 #define GTZC_CFGR3_SAES_Pos                 (15U)
26040 #define GTZC_CFGR3_SAES_Msk                 (0x01UL << GTZC_CFGR3_SAES_Pos)
26041 #define GTZC_CFGR3_OCTOSPIM_Pos             (16U)
26042 #define GTZC_CFGR3_OCTOSPIM_Msk             (0x01UL << GTZC_CFGR3_OCTOSPIM_Pos)
26043 #define GTZC_CFGR3_SDMMC1_Pos               (17U)
26044 #define GTZC_CFGR3_SDMMC1_Msk               (0x01UL << GTZC_CFGR3_SDMMC1_Pos)
26045 #define GTZC_CFGR3_SDMMC2_Pos               (18U)
26046 #define GTZC_CFGR3_SDMMC2_Msk               (0x01UL << GTZC_CFGR3_SDMMC2_Pos)
26047 #define GTZC_CFGR3_FSMC_REG_Pos             (19U)
26048 #define GTZC_CFGR3_FSMC_REG_Msk             (0x01UL << GTZC_CFGR3_FSMC_REG_Pos)
26049 #define GTZC_CFGR3_OCTOSPI1_REG_Pos         (20U)
26050 #define GTZC_CFGR3_OCTOSPI1_REG_Msk         (0x01UL << GTZC_CFGR3_OCTOSPI1_REG_Pos)
26051 #define GTZC_CFGR3_OCTOSPI2_REG_Pos         (21U)
26052 #define GTZC_CFGR3_OCTOSPI2_REG_Msk         (0x01UL << GTZC_CFGR3_OCTOSPI2_REG_Pos)
26053 #define GTZC_CFGR3_RAMCFG_Pos               (22U)
26054 #define GTZC_CFGR3_RAMCFG_Msk               (0x01UL << GTZC_CFGR3_RAMCFG_Pos)
26055 #define GTZC_CFGR3_GPU2D_Pos                (23U)
26056 #define GTZC_CFGR3_GPU2D_Msk                (0x01UL << GTZC_CFGR3_GPU2D_Pos)
26057 #define GTZC_CFGR3_GFXMMU_Pos               (24U)
26058 #define GTZC_CFGR3_GFXMMU_Msk               (0x01UL << GTZC_CFGR3_GFXMMU_Pos)
26059 #define GTZC_CFGR3_GFXMMU_REG_Pos           (25U)
26060 #define GTZC_CFGR3_GFXMMU_REG_Msk           (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos)
26061 #define GTZC_CFGR3_HSPI1_REG_Pos            (26U)
26062 #define GTZC_CFGR3_HSPI1_REG_Msk            (0x01UL << GTZC_CFGR3_HSPI1_REG_Pos)
26063 #define GTZC_CFGR3_DCACHE2_REG_Pos          (27U)
26064 #define GTZC_CFGR3_DCACHE2_REG_Msk          (0x01UL << GTZC_CFGR3_DCACHE2_REG_Pos)
26065 #define GTZC_CFGR3_JPEG_Pos                 (28U)
26066 #define GTZC_CFGR3_JPEG_Msk                 (0x01UL << GTZC_CFGR3_JPEG_Pos)
26067 
26068 /***************  Bits definition for register x=4 (GTZC1) *************/
26069 #define GTZC_CFGR4_GPDMA1_Pos               (0U)
26070 #define GTZC_CFGR4_GPDMA1_Msk               (0x01UL << GTZC_CFGR4_GPDMA1_Pos)
26071 #define GTZC_CFGR4_FLASH_REG_Pos            (1U)
26072 #define GTZC_CFGR4_FLASH_REG_Msk            (0x01UL << GTZC_CFGR4_FLASH_REG_Pos)
26073 #define GTZC_CFGR4_FLASH_Pos                (2U)
26074 #define GTZC_CFGR4_FLASH_Msk                (0x01UL << GTZC_CFGR4_FLASH_Pos)
26075 #define GTZC_CFGR4_OTFDEC1_Pos              (3U)
26076 #define GTZC_CFGR4_OTFDEC1_Msk              (0x01UL << GTZC_CFGR4_OTFDEC1_Pos)
26077 #define GTZC_CFGR4_OTFDEC2_Pos              (4U)
26078 #define GTZC_CFGR4_OTFDEC2_Msk              (0x01UL << GTZC_CFGR4_OTFDEC2_Pos)
26079 #define GTZC_CFGR4_TZSC1_Pos                (14U)
26080 #define GTZC_CFGR4_TZSC1_Msk                (0x01UL << GTZC_CFGR4_TZSC1_Pos)
26081 #define GTZC_CFGR4_TZIC1_Pos                (15U)
26082 #define GTZC_CFGR4_TZIC1_Msk                (0x01UL << GTZC_CFGR4_TZIC1_Pos)
26083 #define GTZC_CFGR4_OCTOSPI1_MEM_Pos         (16U)
26084 #define GTZC_CFGR4_OCTOSPI1_MEM_Msk         (0x01UL << GTZC_CFGR4_OCTOSPI1_MEM_Pos)
26085 #define GTZC_CFGR4_FSMC_MEM_Pos             (17U)
26086 #define GTZC_CFGR4_FSMC_MEM_Msk             (0x01UL << GTZC_CFGR4_FSMC_MEM_Pos)
26087 #define GTZC_CFGR4_BKPSRAM_Pos              (18U)
26088 #define GTZC_CFGR4_BKPSRAM_Msk              (0x01UL << GTZC_CFGR4_BKPSRAM_Pos)
26089 #define GTZC_CFGR4_OCTOSPI2_MEM_Pos         (19U)
26090 #define GTZC_CFGR4_OCTOSPI2_MEM_Msk         (0x01UL << GTZC_CFGR4_OCTOSPI2_MEM_Pos)
26091 #define GTZC_CFGR4_HSPI1_MEM_Pos            (20U)
26092 #define GTZC_CFGR4_HSPI1_MEM_Msk            (0x01UL << GTZC_CFGR4_HSPI1_MEM_Pos)
26093 #define GTZC_CFGR4_SRAM6_Pos                (22U)
26094 #define GTZC_CFGR4_SRAM6_Msk                (0x01UL << GTZC_CFGR4_SRAM6_Pos)
26095 #define GTZC_CFGR4_MPCBB6_REG_Pos           (23U)
26096 #define GTZC_CFGR4_MPCBB6_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB6_REG_Pos)
26097 #define GTZC_CFGR4_SRAM1_Pos                (24U)
26098 #define GTZC_CFGR4_SRAM1_Msk                (0x01UL << GTZC_CFGR4_SRAM1_Pos)
26099 #define GTZC_CFGR4_MPCBB1_REG_Pos           (25U)
26100 #define GTZC_CFGR4_MPCBB1_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
26101 #define GTZC_CFGR4_SRAM2_Pos                (26U)
26102 #define GTZC_CFGR4_SRAM2_Msk                (0x01UL << GTZC_CFGR4_SRAM2_Pos)
26103 #define GTZC_CFGR4_MPCBB2_REG_Pos           (27U)
26104 #define GTZC_CFGR4_MPCBB2_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos)
26105 #define GTZC_CFGR4_SRAM3_Pos                (28U)
26106 #define GTZC_CFGR4_SRAM3_Msk                (0x01UL << GTZC_CFGR4_SRAM3_Pos)
26107 #define GTZC_CFGR4_MPCBB3_REG_Pos           (29U)
26108 #define GTZC_CFGR4_MPCBB3_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos)
26109 #define GTZC_CFGR4_SRAM5_Pos                (30U)
26110 #define GTZC_CFGR4_SRAM5_Msk                (0x01UL << GTZC_CFGR4_SRAM5_Pos)
26111 #define GTZC_CFGR4_MPCBB5_REG_Pos           (31U)
26112 #define GTZC_CFGR4_MPCBB5_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB5_REG_Pos)
26113 
26114 /***************  Bits definition for register x=1 (GTZC2) *************/
26115 #define GTZC_CFGR1_SPI3_Pos                 (0U)
26116 #define GTZC_CFGR1_SPI3_Msk                 (0x01UL << GTZC_CFGR1_SPI3_Pos)
26117 #define GTZC_CFGR1_LPUART1_Pos              (1U)
26118 #define GTZC_CFGR1_LPUART1_Msk              (0x01UL << GTZC_CFGR1_LPUART1_Pos)
26119 #define GTZC_CFGR1_I2C3_Pos                 (2U)
26120 #define GTZC_CFGR1_I2C3_Msk                 (0x01UL << GTZC_CFGR1_I2C3_Pos)
26121 #define GTZC_CFGR1_LPTIM1_Pos               (3U)
26122 #define GTZC_CFGR1_LPTIM1_Msk               (0x01UL << GTZC_CFGR1_LPTIM1_Pos)
26123 #define GTZC_CFGR1_LPTIM3_Pos               (4U)
26124 #define GTZC_CFGR1_LPTIM3_Msk               (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
26125 #define GTZC_CFGR1_LPTIM4_Pos               (5U)
26126 #define GTZC_CFGR1_LPTIM4_Msk               (0x01UL << GTZC_CFGR1_LPTIM4_Pos)
26127 #define GTZC_CFGR1_OPAMP_Pos                (6U)
26128 #define GTZC_CFGR1_OPAMP_Msk                (0x01UL << GTZC_CFGR1_OPAMP_Pos)
26129 #define GTZC_CFGR1_COMP_Pos                 (7U)
26130 #define GTZC_CFGR1_COMP_Msk                 (0x01UL << GTZC_CFGR1_COMP_Pos)
26131 #define GTZC_CFGR1_ADC4_Pos                 (8U)
26132 #define GTZC_CFGR1_ADC4_Msk                 (0x01UL << GTZC_CFGR1_ADC4_Pos)
26133 #define GTZC_CFGR1_VREFBUF_Pos              (9U)
26134 #define GTZC_CFGR1_VREFBUF_Msk              (0x01UL << GTZC_CFGR1_VREFBUF_Pos)
26135 #define GTZC_CFGR1_DAC1_Pos                 (11U)
26136 #define GTZC_CFGR1_DAC1_Msk                 (0x01UL << GTZC_CFGR1_DAC1_Pos)
26137 #define GTZC_CFGR1_ADF1_Pos                 (12U)
26138 #define GTZC_CFGR1_ADF1_Msk                 (0x01UL << GTZC_CFGR1_ADF1_Pos)
26139 
26140 /***************  Bits definition for register x=2 (GTZC2) *************/
26141 #define GTZC_CFGR2_SYSCFG_Pos               (0U)
26142 #define GTZC_CFGR2_SYSCFG_Msk               (0x01UL << GTZC_CFGR2_SYSCFG_Pos)
26143 #define GTZC_CFGR2_RTC_Pos                  (1U)
26144 #define GTZC_CFGR2_RTC_Msk                  (0x01UL << GTZC_CFGR2_RTC_Pos)
26145 #define GTZC_CFGR2_TAMP_Pos                 (2U)
26146 #define GTZC_CFGR2_TAMP_Msk                 (0x01UL << GTZC_CFGR2_TAMP_Pos)
26147 #define GTZC_CFGR2_PWR_Pos                  (3U)
26148 #define GTZC_CFGR2_PWR_Msk                  (0x01UL << GTZC_CFGR2_PWR_Pos)
26149 #define GTZC_CFGR2_RCC_Pos                  (4U)
26150 #define GTZC_CFGR2_RCC_Msk                  (0x01UL << GTZC_CFGR2_RCC_Pos)
26151 #define GTZC_CFGR2_LPDMA1_Pos               (5U)
26152 #define GTZC_CFGR2_LPDMA1_Msk               (0x01UL << GTZC_CFGR2_LPDMA1_Pos)
26153 #define GTZC_CFGR2_EXTI_Pos                 (6U)
26154 #define GTZC_CFGR2_EXTI_Msk                 (0x01UL << GTZC_CFGR2_EXTI_Pos)
26155 #define GTZC_CFGR2_TZSC2_Pos                (14U)
26156 #define GTZC_CFGR2_TZSC2_Msk                (0x01UL << GTZC_CFGR2_TZSC2_Pos)
26157 #define GTZC_CFGR2_TZIC2_Pos                (15U)
26158 #define GTZC_CFGR2_TZIC2_Msk                (0x01UL << GTZC_CFGR2_TZIC2_Pos)
26159 #define GTZC_CFGR2_SRAM4_Pos                (24U)
26160 #define GTZC_CFGR2_SRAM4_Msk                (0x01UL << GTZC_CFGR2_SRAM4_Pos)
26161 #define GTZC_CFGR2_MPCBB4_REG_Pos           (25U)
26162 #define GTZC_CFGR2_MPCBB4_REG_Msk           (0x01UL << GTZC_CFGR2_MPCBB4_REG_Pos)
26163 
26164 /*******************  Bits definition for GTZC_TZSC1_SECCFGR1 register  ***************/
26165 #define GTZC_TZSC1_SECCFGR1_TIM2_Pos            GTZC_CFGR1_TIM2_Pos
26166 #define GTZC_TZSC1_SECCFGR1_TIM2_Msk            GTZC_CFGR1_TIM2_Msk
26167 #define GTZC_TZSC1_SECCFGR1_TIM3_Pos            GTZC_CFGR1_TIM3_Pos
26168 #define GTZC_TZSC1_SECCFGR1_TIM3_Msk            GTZC_CFGR1_TIM3_Msk
26169 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos            GTZC_CFGR1_TIM4_Pos
26170 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk            GTZC_CFGR1_TIM4_Msk
26171 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos            GTZC_CFGR1_TIM5_Pos
26172 #define GTZC_TZSC1_SECCFGR1_TIM5_Msk            GTZC_CFGR1_TIM5_Msk
26173 #define GTZC_TZSC1_SECCFGR1_TIM6_Pos            GTZC_CFGR1_TIM6_Pos
26174 #define GTZC_TZSC1_SECCFGR1_TIM6_Msk            GTZC_CFGR1_TIM6_Msk
26175 #define GTZC_TZSC1_SECCFGR1_TIM7_Pos            GTZC_CFGR1_TIM7_Pos
26176 #define GTZC_TZSC1_SECCFGR1_TIM7_Msk            GTZC_CFGR1_TIM7_Msk
26177 #define GTZC_TZSC1_SECCFGR1_WWDG_Pos            GTZC_CFGR1_WWDG_Pos
26178 #define GTZC_TZSC1_SECCFGR1_WWDG_Msk            GTZC_CFGR1_WWDG_Msk
26179 #define GTZC_TZSC1_SECCFGR1_IWDG_Pos            GTZC_CFGR1_IWDG_Pos
26180 #define GTZC_TZSC1_SECCFGR1_IWDG_Msk            GTZC_CFGR1_IWDG_Msk
26181 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos            GTZC_CFGR1_SPI2_Pos
26182 #define GTZC_TZSC1_SECCFGR1_SPI2_Msk            GTZC_CFGR1_SPI2_Msk
26183 #define GTZC_TZSC1_SECCFGR1_USART2_Pos          GTZC_CFGR1_USART2_Pos
26184 #define GTZC_TZSC1_SECCFGR1_USART2_Msk          GTZC_CFGR1_USART2_Msk
26185 #define GTZC_TZSC1_SECCFGR1_USART3_Pos          GTZC_CFGR1_USART3_Pos
26186 #define GTZC_TZSC1_SECCFGR1_USART3_Msk          GTZC_CFGR1_USART3_Msk
26187 #define GTZC_TZSC1_SECCFGR1_UART4_Pos           GTZC_CFGR1_UART4_Pos
26188 #define GTZC_TZSC1_SECCFGR1_UART4_Msk           GTZC_CFGR1_UART4_Msk
26189 #define GTZC_TZSC1_SECCFGR1_UART5_Pos           GTZC_CFGR1_UART5_Pos
26190 #define GTZC_TZSC1_SECCFGR1_UART5_Msk           GTZC_CFGR1_UART5_Msk
26191 #define GTZC_TZSC1_SECCFGR1_I2C1_Pos            GTZC_CFGR1_I2C1_Pos
26192 #define GTZC_TZSC1_SECCFGR1_I2C1_Msk            GTZC_CFGR1_I2C1_Msk
26193 #define GTZC_TZSC1_SECCFGR1_I2C2_Pos            GTZC_CFGR1_I2C2_Pos
26194 #define GTZC_TZSC1_SECCFGR1_I2C2_Msk            GTZC_CFGR1_I2C2_Msk
26195 #define GTZC_TZSC1_SECCFGR1_CRS_Pos             GTZC_CFGR1_CRS_Pos
26196 #define GTZC_TZSC1_SECCFGR1_CRS_Msk             GTZC_CFGR1_CRS_Msk
26197 #define GTZC_TZSC1_SECCFGR1_I2C4_Pos            GTZC_CFGR1_I2C4_Pos
26198 #define GTZC_TZSC1_SECCFGR1_I2C4_Msk            GTZC_CFGR1_I2C4_Msk
26199 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos          GTZC_CFGR1_LPTIM2_Pos
26200 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk          GTZC_CFGR1_LPTIM2_Msk
26201 #define GTZC_TZSC1_SECCFGR1_FDCAN1_Pos          GTZC_CFGR1_FDCAN1_Pos
26202 #define GTZC_TZSC1_SECCFGR1_FDCAN1_Msk          GTZC_CFGR1_FDCAN1_Msk
26203 #define GTZC_TZSC1_SECCFGR1_UCPD1_Pos           GTZC_CFGR1_UCPD1_Pos
26204 #define GTZC_TZSC1_SECCFGR1_UCPD1_Msk           GTZC_CFGR1_UCPD1_Msk
26205 #define GTZC_TZSC1_SECCFGR1_USART6_Pos          GTZC_CFGR1_USART6_Pos
26206 #define GTZC_TZSC1_SECCFGR1_USART6_Msk          GTZC_CFGR1_USART6_Msk
26207 #define GTZC_TZSC1_SECCFGR1_I2C5_Pos            GTZC_CFGR1_I2C5_Pos
26208 #define GTZC_TZSC1_SECCFGR1_I2C5_Msk            GTZC_CFGR1_I2C5_Msk
26209 #define GTZC_TZSC1_SECCFGR1_I2C6_Pos            GTZC_CFGR1_I2C6_Pos
26210 #define GTZC_TZSC1_SECCFGR1_I2C6_Msk            GTZC_CFGR1_I2C6_Msk
26211 
26212 /*******************  Bits definition for GTZC_TZSC1_SECCFGR2 register  ***************/
26213 #define GTZC_TZSC1_SECCFGR2_TIM1_Pos            GTZC_CFGR2_TIM1_Pos
26214 #define GTZC_TZSC1_SECCFGR2_TIM1_Msk            GTZC_CFGR2_TIM1_Msk
26215 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos            GTZC_CFGR2_SPI1_Pos
26216 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk            GTZC_CFGR2_SPI1_Msk
26217 #define GTZC_TZSC1_SECCFGR2_TIM8_Pos            GTZC_CFGR2_TIM8_Pos
26218 #define GTZC_TZSC1_SECCFGR2_TIM8_Msk            GTZC_CFGR2_TIM8_Msk
26219 #define GTZC_TZSC1_SECCFGR2_USART1_Pos          GTZC_CFGR2_USART1_Pos
26220 #define GTZC_TZSC1_SECCFGR2_USART1_Msk          GTZC_CFGR2_USART1_Msk
26221 #define GTZC_TZSC1_SECCFGR2_TIM15_Pos           GTZC_CFGR2_TIM15_Pos
26222 #define GTZC_TZSC1_SECCFGR2_TIM15_Msk           GTZC_CFGR2_TIM15_Msk
26223 #define GTZC_TZSC1_SECCFGR2_TIM16_Pos           GTZC_CFGR2_TIM16_Pos
26224 #define GTZC_TZSC1_SECCFGR2_TIM16_Msk           GTZC_CFGR2_TIM16_Msk
26225 #define GTZC_TZSC1_SECCFGR2_TIM17_Pos           GTZC_CFGR2_TIM17_Pos
26226 #define GTZC_TZSC1_SECCFGR2_TIM17_Msk           GTZC_CFGR2_TIM17_Msk
26227 #define GTZC_TZSC1_SECCFGR2_SAI1_Pos            GTZC_CFGR2_SAI1_Pos
26228 #define GTZC_TZSC1_SECCFGR2_SAI1_Msk            GTZC_CFGR2_SAI1_Msk
26229 #define GTZC_TZSC1_SECCFGR2_SAI2_Pos            GTZC_CFGR2_SAI2_Pos
26230 #define GTZC_TZSC1_SECCFGR2_SAI2_Msk            GTZC_CFGR2_SAI2_Msk
26231 #define GTZC_TZSC1_SECCFGR2_LTDCUSB_Pos         GTZC_CFGR2_LTDCUSB_Pos
26232 #define GTZC_TZSC1_SECCFGR2_LTDCUSB_Msk         GTZC_CFGR2_LTDCUSB_Msk
26233 #define GTZC_TZSC1_SECCFGR2_DSI_Pos             GTZC_CFGR2_DSI_Pos
26234 #define GTZC_TZSC1_SECCFGR2_DSI_Msk             GTZC_CFGR2_DSI_Msk
26235 #define GTZC_TZSC1_SECCFGR2_GFXTIM_Pos          GTZC_CFGR2_GFXTIM_Pos
26236 #define GTZC_TZSC1_SECCFGR2_GFXTIM_Msk          GTZC_CFGR2_GFXTIM_Msk
26237 
26238 /*******************  Bits definition for GTZC_TZSC1_SECCFGR3 register  ***************/
26239 #define GTZC_TZSC1_SECCFGR3_MDF1_Pos            GTZC_CFGR3_MDF1_Pos
26240 #define GTZC_TZSC1_SECCFGR3_MDF1_Msk            GTZC_CFGR3_MDF1_Msk
26241 #define GTZC_TZSC1_SECCFGR3_CORDIC_Pos          GTZC_CFGR3_CORDIC_Pos
26242 #define GTZC_TZSC1_SECCFGR3_CORDIC_Msk          GTZC_CFGR3_CORDIC_Msk
26243 #define GTZC_TZSC1_SECCFGR3_FMAC_Pos            GTZC_CFGR3_FMAC_Pos
26244 #define GTZC_TZSC1_SECCFGR3_FMAC_Msk            GTZC_CFGR3_FMAC_Msk
26245 #define GTZC_TZSC1_SECCFGR3_CRC_Pos             GTZC_CFGR3_CRC_Pos
26246 #define GTZC_TZSC1_SECCFGR3_CRC_Msk             GTZC_CFGR3_CRC_Msk
26247 #define GTZC_TZSC1_SECCFGR3_TSC_Pos             GTZC_CFGR3_TSC_Pos
26248 #define GTZC_TZSC1_SECCFGR3_TSC_Msk             GTZC_CFGR3_TSC_Msk
26249 #define GTZC_TZSC1_SECCFGR3_DMA2D_Pos           GTZC_CFGR3_DMA2D_Pos
26250 #define GTZC_TZSC1_SECCFGR3_DMA2D_Msk           GTZC_CFGR3_DMA2D_Msk
26251 #define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos      GTZC_CFGR3_ICACHE_REG_Pos
26252 #define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk      GTZC_CFGR3_ICACHE_REG_Msk
26253 #define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Pos     GTZC_CFGR3_DCACHE1_REG_Pos
26254 #define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Msk     GTZC_CFGR3_DCACHE1_REG_Msk
26255 #define GTZC_TZSC1_SECCFGR3_ADC12_Pos           GTZC_CFGR3_ADC12_Pos
26256 #define GTZC_TZSC1_SECCFGR3_ADC12_Msk           GTZC_CFGR3_ADC12_Msk
26257 #define GTZC_TZSC1_SECCFGR3_DCMI_Pos            GTZC_CFGR3_DCMI_Pos
26258 #define GTZC_TZSC1_SECCFGR3_DCMI_Msk            GTZC_CFGR3_DCMI_Msk
26259 #define GTZC_TZSC1_SECCFGR3_OTG_Pos             GTZC_CFGR3_OTG_Pos
26260 #define GTZC_TZSC1_SECCFGR3_OTG_Msk             GTZC_CFGR3_OTG_Msk
26261 #define GTZC_TZSC1_SECCFGR3_AES_Pos             GTZC_CFGR3_AES_Pos
26262 #define GTZC_TZSC1_SECCFGR3_AES_Msk             GTZC_CFGR3_AES_Msk
26263 #define GTZC_TZSC1_SECCFGR3_HASH_Pos            GTZC_CFGR3_HASH_Pos
26264 #define GTZC_TZSC1_SECCFGR3_HASH_Msk            GTZC_CFGR3_HASH_Msk
26265 #define GTZC_TZSC1_SECCFGR3_RNG_Pos             GTZC_CFGR3_RNG_Pos
26266 #define GTZC_TZSC1_SECCFGR3_RNG_Msk             GTZC_CFGR3_RNG_Msk
26267 #define GTZC_TZSC1_SECCFGR3_PKA_Pos             GTZC_CFGR3_PKA_Pos
26268 #define GTZC_TZSC1_SECCFGR3_PKA_Msk             GTZC_CFGR3_PKA_Msk
26269 #define GTZC_TZSC1_SECCFGR3_SAES_Pos            GTZC_CFGR3_SAES_Pos
26270 #define GTZC_TZSC1_SECCFGR3_SAES_Msk            GTZC_CFGR3_SAES_Msk
26271 #define GTZC_TZSC1_SECCFGR3_OCTOSPIM_Pos        GTZC_CFGR3_OCTOSPIM_Pos
26272 #define GTZC_TZSC1_SECCFGR3_OCTOSPIM_Msk        GTZC_CFGR3_OCTOSPIM_Msk
26273 #define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos          GTZC_CFGR3_SDMMC1_Pos
26274 #define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk          GTZC_CFGR3_SDMMC1_Msk
26275 #define GTZC_TZSC1_SECCFGR3_SDMMC2_Pos          GTZC_CFGR3_SDMMC2_Pos
26276 #define GTZC_TZSC1_SECCFGR3_SDMMC2_Msk          GTZC_CFGR3_SDMMC2_Msk
26277 #define GTZC_TZSC1_SECCFGR3_FSMC_REG_Pos        GTZC_CFGR3_FSMC_REG_Pos
26278 #define GTZC_TZSC1_SECCFGR3_FSMC_REG_Msk        GTZC_CFGR3_FSMC_REG_Msk
26279 #define GTZC_TZSC1_SECCFGR3_OCTOSPI1_REG_Pos    GTZC_CFGR3_OCTOSPI1_REG_Pos
26280 #define GTZC_TZSC1_SECCFGR3_OCTOSPI1_REG_Msk    GTZC_CFGR3_OCTOSPI1_REG_Msk
26281 #define GTZC_TZSC1_SECCFGR3_OCTOSPI2_REG_Pos    GTZC_CFGR3_OCTOSPI2_REG_Pos
26282 #define GTZC_TZSC1_SECCFGR3_OCTOSPI2_REG_Msk    GTZC_CFGR3_OCTOSPI2_REG_Msk
26283 #define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos          GTZC_CFGR3_RAMCFG_Pos
26284 #define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk          GTZC_CFGR3_RAMCFG_Msk
26285 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos           GTZC_CFGR3_GPU2D_Pos
26286 #define GTZC_TZSC1_SECCFGR3_GPU2D_Msk           GTZC_CFGR3_GPU2D_Msk
26287 #define GTZC_TZSC1_SECCFGR3_GFXMMU_Pos          GTZC_CFGR3_GFXMMU_Pos
26288 #define GTZC_TZSC1_SECCFGR3_GFXMMU_Msk          GTZC_CFGR3_GFXMMU_Msk
26289 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Pos      GTZC_CFGR3_GFXMMU_REG_Pos
26290 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Msk      GTZC_CFGR3_GFXMMU_REG_Msk
26291 #define GTZC_TZSC1_SECCFGR3_HSPI1_REG_Pos       GTZC_CFGR3_HSPI1_REG_Pos
26292 #define GTZC_TZSC1_SECCFGR3_HSPI1_REG_Msk       GTZC_CFGR3_HSPI1_REG_Msk
26293 #define GTZC_TZSC1_SECCFGR3_DCACHE2_REG_Pos     GTZC_CFGR3_DCACHE2_REG_Pos
26294 #define GTZC_TZSC1_SECCFGR3_DCACHE2_REG_Msk     GTZC_CFGR3_DCACHE2_REG_Msk
26295 #define GTZC_TZSC1_SECCFGR3_JPEG_Pos            GTZC_CFGR3_JPEG_REG_Pos
26296 #define GTZC_TZSC1_SECCFGR3_JPEG_Msk            GTZC_CFGR3_JPEG_REG_Msk
26297 
26298 /*******************  Bits definition for GTZC_TZSC2_SECCFGR1 register  ***************/
26299 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos            GTZC_CFGR1_SPI3_Pos
26300 #define GTZC_TZSC2_SECCFGR1_SPI3_Msk            GTZC_CFGR1_SPI3_Msk
26301 #define GTZC_TZSC2_SECCFGR1_LPUART1_Pos         GTZC_CFGR1_LPUART1_Pos
26302 #define GTZC_TZSC2_SECCFGR1_LPUART1_Msk         GTZC_CFGR1_LPUART1_Msk
26303 #define GTZC_TZSC2_SECCFGR1_I2C3_Pos            GTZC_CFGR1_I2C3_Pos
26304 #define GTZC_TZSC2_SECCFGR1_I2C3_Msk            GTZC_CFGR1_I2C3_Msk
26305 #define GTZC_TZSC2_SECCFGR1_LPTIM1_Pos          GTZC_CFGR1_LPTIM1_Pos
26306 #define GTZC_TZSC2_SECCFGR1_LPTIM1_Msk          GTZC_CFGR1_LPTIM1_Msk
26307 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos          GTZC_CFGR1_LPTIM3_Pos
26308 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Msk          GTZC_CFGR1_LPTIM3_Msk
26309 #define GTZC_TZSC2_SECCFGR1_LPTIM4_Pos          GTZC_CFGR1_LPTIM4_Pos
26310 #define GTZC_TZSC2_SECCFGR1_LPTIM4_Msk          GTZC_CFGR1_LPTIM4_Msk
26311 #define GTZC_TZSC2_SECCFGR1_OPAMP_Pos           GTZC_CFGR1_OPAMP_Pos
26312 #define GTZC_TZSC2_SECCFGR1_OPAMP_Msk           GTZC_CFGR1_OPAMP_Msk
26313 #define GTZC_TZSC2_SECCFGR1_COMP_Pos            GTZC_CFGR1_COMP_Pos
26314 #define GTZC_TZSC2_SECCFGR1_COMP_Msk            GTZC_CFGR1_COMP_Msk
26315 #define GTZC_TZSC2_SECCFGR1_ADC4_Pos            GTZC_CFGR1_ADC4_Pos
26316 #define GTZC_TZSC2_SECCFGR1_ADC4_Msk            GTZC_CFGR1_ADC4_Msk
26317 #define GTZC_TZSC2_SECCFGR1_VREFBUF_Pos         GTZC_CFGR1_VREFBUF_Pos
26318 #define GTZC_TZSC2_SECCFGR1_VREFBUF_Msk         GTZC_CFGR1_VREFBUF_Msk
26319 #define GTZC_TZSC2_SECCFGR1_DAC1_Pos            GTZC_CFGR1_DAC1_Pos
26320 #define GTZC_TZSC2_SECCFGR1_DAC1_Msk            GTZC_CFGR1_DAC1_Msk
26321 #define GTZC_TZSC2_SECCFGR1_ADF1_Pos            GTZC_CFGR1_ADF1_Pos
26322 #define GTZC_TZSC2_SECCFGR1_ADF1_Msk            GTZC_CFGR1_ADF1_Msk
26323 
26324 /*******************  Bits definition for GTZC_TZSC1_PRIVCFGR1 register  ***************/
26325 #define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos           GTZC_CFGR1_TIM2_Pos
26326 #define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk           GTZC_CFGR1_TIM2_Msk
26327 #define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos           GTZC_CFGR1_TIM3_Pos
26328 #define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk           GTZC_CFGR1_TIM3_Msk
26329 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos           GTZC_CFGR1_TIM4_Pos
26330 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk           GTZC_CFGR1_TIM4_Msk
26331 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos           GTZC_CFGR1_TIM5_Pos
26332 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Msk           GTZC_CFGR1_TIM5_Msk
26333 #define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos           GTZC_CFGR1_TIM6_Pos
26334 #define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk           GTZC_CFGR1_TIM6_Msk
26335 #define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos           GTZC_CFGR1_TIM7_Pos
26336 #define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk           GTZC_CFGR1_TIM7_Msk
26337 #define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos           GTZC_CFGR1_WWDG_Pos
26338 #define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk           GTZC_CFGR1_WWDG_Msk
26339 #define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos           GTZC_CFGR1_IWDG_Pos
26340 #define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk           GTZC_CFGR1_IWDG_Msk
26341 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos           GTZC_CFGR1_SPI2_Pos
26342 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk           GTZC_CFGR1_SPI2_Msk
26343 #define GTZC_TZSC1_PRIVCFGR1_USART2_Pos         GTZC_CFGR1_USART2_Pos
26344 #define GTZC_TZSC1_PRIVCFGR1_USART2_Msk         GTZC_CFGR1_USART2_Msk
26345 #define GTZC_TZSC1_PRIVCFGR1_USART3_Pos         GTZC_CFGR1_USART3_Pos
26346 #define GTZC_TZSC1_PRIVCFGR1_USART3_Msk         GTZC_CFGR1_USART3_Msk
26347 #define GTZC_TZSC1_PRIVCFGR1_UART4_Pos          GTZC_CFGR1_UART4_Pos
26348 #define GTZC_TZSC1_PRIVCFGR1_UART4_Msk          GTZC_CFGR1_UART4_Msk
26349 #define GTZC_TZSC1_PRIVCFGR1_UART5_Pos          GTZC_CFGR1_UART5_Pos
26350 #define GTZC_TZSC1_PRIVCFGR1_UART5_Msk          GTZC_CFGR1_UART5_Msk
26351 #define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos           GTZC_CFGR1_I2C1_Pos
26352 #define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk           GTZC_CFGR1_I2C1_Msk
26353 #define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos           GTZC_CFGR1_I2C2_Pos
26354 #define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk           GTZC_CFGR1_I2C2_Msk
26355 #define GTZC_TZSC1_PRIVCFGR1_CRS_Pos            GTZC_CFGR1_CRS_Pos
26356 #define GTZC_TZSC1_PRIVCFGR1_CRS_Msk            GTZC_CFGR1_CRS_Msk
26357 #define GTZC_TZSC1_PRIVCFGR1_I2C4_Pos           GTZC_CFGR1_I2C4_Pos
26358 #define GTZC_TZSC1_PRIVCFGR1_I2C4_Msk           GTZC_CFGR1_I2C4_Msk
26359 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos         GTZC_CFGR1_LPTIM2_Pos
26360 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk         GTZC_CFGR1_LPTIM2_Msk
26361 #define GTZC_TZSC1_PRIVCFGR1_FDCAN1_Pos         GTZC_CFGR1_FDCAN1_Pos
26362 #define GTZC_TZSC1_PRIVCFGR1_FDCAN1_Msk         GTZC_CFGR1_FDCAN1_Msk
26363 #define GTZC_TZSC1_PRIVCFGR1_UCPD1_Pos          GTZC_CFGR1_UCPD1_Pos
26364 #define GTZC_TZSC1_PRIVCFGR1_UCPD1_Msk          GTZC_CFGR1_UCPD1_Msk
26365 #define GTZC_TZSC1_PRIVCFGR1_USART6_Pos         GTZC_CFGR1_USART6_Pos
26366 #define GTZC_TZSC1_PRIVCFGR1_USART6_Msk         GTZC_CFGR1_USART6_Msk
26367 #define GTZC_TZSC1_PRIVCFGR1_I2C5_Pos           GTZC_CFGR1_I2C5_Pos
26368 #define GTZC_TZSC1_PRIVCFGR1_I2C5_Msk           GTZC_CFGR1_I2C5_Msk
26369 #define GTZC_TZSC1_PRIVCFGR1_I2C6_Pos           GTZC_CFGR1_I2C6_Pos
26370 #define GTZC_TZSC1_PRIVCFGR1_I2C6_Msk           GTZC_CFGR1_I2C6_Msk
26371 
26372 /*******************  Bits definition for GTZC_TZSC1_PRIVCFGR2 register  ***************/
26373 #define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos           GTZC_CFGR2_TIM1_Pos
26374 #define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk           GTZC_CFGR2_TIM1_Msk
26375 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos           GTZC_CFGR2_SPI1_Pos
26376 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk           GTZC_CFGR2_SPI1_Msk
26377 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos           GTZC_CFGR2_TIM8_Pos
26378 #define GTZC_TZSC1_PRIVCFGR2_TIM8_Msk           GTZC_CFGR2_TIM8_Msk
26379 #define GTZC_TZSC1_PRIVCFGR2_USART1_Pos         GTZC_CFGR2_USART1_Pos
26380 #define GTZC_TZSC1_PRIVCFGR2_USART1_Msk         GTZC_CFGR2_USART1_Msk
26381 #define GTZC_TZSC1_PRIVCFGR2_TIM15_Pos          GTZC_CFGR2_TIM15_Pos
26382 #define GTZC_TZSC1_PRIVCFGR2_TIM15_Msk          GTZC_CFGR2_TIM15_Msk
26383 #define GTZC_TZSC1_PRIVCFGR2_TIM16_Pos          GTZC_CFGR2_TIM16_Pos
26384 #define GTZC_TZSC1_PRIVCFGR2_TIM16_Msk          GTZC_CFGR2_TIM16_Msk
26385 #define GTZC_TZSC1_PRIVCFGR2_TIM17_Pos          GTZC_CFGR2_TIM17_Pos
26386 #define GTZC_TZSC1_PRIVCFGR2_TIM17_Msk          GTZC_CFGR2_TIM17_Msk
26387 #define GTZC_TZSC1_PRIVCFGR2_SAI1_Pos           GTZC_CFGR2_SAI1_Pos
26388 #define GTZC_TZSC1_PRIVCFGR2_SAI1_Msk           GTZC_CFGR2_SAI1_Msk
26389 #define GTZC_TZSC1_PRIVCFGR2_SAI2_Pos           GTZC_CFGR2_SAI2_Pos
26390 #define GTZC_TZSC1_PRIVCFGR2_SAI2_Msk           GTZC_CFGR2_SAI2_Msk
26391 #define GTZC_TZSC1_PRIVCFGR2_LTDCUSB_Pos        GTZC_CFGR2_LTDCUSB_Pos
26392 #define GTZC_TZSC1_PRIVCFGR2_LTDCUSB_Msk        GTZC_CFGR2_LTDCUSB_Msk
26393 #define GTZC_TZSC1_PRIVCFGR2_DSI_Pos            GTZC_CFGR2_DSI_Pos
26394 #define GTZC_TZSC1_PRIVCFGR2_DSI_Msk            GTZC_CFGR2_DSI_Msk
26395 #define GTZC_TZSC1_PRIVCFGR2_GFXTIM_Pos         GTZC_CFGR2_GFXTIM_Pos
26396 #define GTZC_TZSC1_PRIVCFGR2_GFXTIM_Msk         GTZC_CFGR2_GFXTIM_Msk
26397 
26398 /*******************  Bits definition for GTZC_TZSC1_PRIVCFGR3 register  ***************/
26399 #define GTZC_TZSC1_PRIVCFGR3_MDF1_Pos           GTZC_CFGR3_MDF1_Pos
26400 #define GTZC_TZSC1_PRIVCFGR3_MDF1_Msk           GTZC_CFGR3_MDF1_Msk
26401 #define GTZC_TZSC1_PRIVCFGR3_CORDIC_Pos         GTZC_CFGR3_CORDIC_Pos
26402 #define GTZC_TZSC1_PRIVCFGR3_CORDIC_Msk         GTZC_CFGR3_CORDIC_Msk
26403 #define GTZC_TZSC1_PRIVCFGR3_FMAC_Pos           GTZC_CFGR3_FMAC_Pos
26404 #define GTZC_TZSC1_PRIVCFGR3_FMAC_Msk           GTZC_CFGR3_FMAC_Msk
26405 #define GTZC_TZSC1_PRIVCFGR3_CRC_Pos            GTZC_CFGR3_CRC_Pos
26406 #define GTZC_TZSC1_PRIVCFGR3_CRC_Msk            GTZC_CFGR3_CRC_Msk
26407 #define GTZC_TZSC1_PRIVCFGR3_TSC_Pos            GTZC_CFGR3_TSC_Pos
26408 #define GTZC_TZSC1_PRIVCFGR3_TSC_Msk            GTZC_CFGR3_TSC_Msk
26409 #define GTZC_TZSC1_PRIVCFGR3_DMA2D_Pos          GTZC_CFGR3_DMA2D_Pos
26410 #define GTZC_TZSC1_PRIVCFGR3_DMA2D_Msk          GTZC_CFGR3_DMA2D_Msk
26411 #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos     GTZC_CFGR3_ICACHE_REG_Pos
26412 #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk     GTZC_CFGR3_ICACHE_REG_Msk
26413 #define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Pos    GTZC_CFGR3_DCACHE1_REG_Pos
26414 #define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Msk    GTZC_CFGR3_DCACHE1_REG_Msk
26415 #define GTZC_TZSC1_PRIVCFGR3_ADC12_Pos          GTZC_CFGR3_ADC12_Pos
26416 #define GTZC_TZSC1_PRIVCFGR3_ADC12_Msk          GTZC_CFGR3_ADC12_Msk
26417 #define GTZC_TZSC1_PRIVCFGR3_DCMI_Pos           GTZC_CFGR3_DCMI_Pos
26418 #define GTZC_TZSC1_PRIVCFGR3_DCMI_Msk           GTZC_CFGR3_DCMI_Msk
26419 #define GTZC_TZSC1_PRIVCFGR3_OTG_Pos            GTZC_CFGR3_OTG_Pos
26420 #define GTZC_TZSC1_PRIVCFGR3_OTG_Msk            GTZC_CFGR3_OTG_Msk
26421 #define GTZC_TZSC1_PRIVCFGR3_AES_Pos            GTZC_CFGR3_AES_Pos
26422 #define GTZC_TZSC1_PRIVCFGR3_AES_Msk            GTZC_CFGR3_AES_Msk
26423 #define GTZC_TZSC1_PRIVCFGR3_HASH_Pos           GTZC_CFGR3_HASH_Pos
26424 #define GTZC_TZSC1_PRIVCFGR3_HASH_Msk           GTZC_CFGR3_HASH_Msk
26425 #define GTZC_TZSC1_PRIVCFGR3_RNG_Pos            GTZC_CFGR3_RNG_Pos
26426 #define GTZC_TZSC1_PRIVCFGR3_RNG_Msk            GTZC_CFGR3_RNG_Msk
26427 #define GTZC_TZSC1_PRIVCFGR3_PKA_Pos            GTZC_CFGR3_PKA_Pos
26428 #define GTZC_TZSC1_PRIVCFGR3_PKA_Msk            GTZC_CFGR3_PKA_Msk
26429 #define GTZC_TZSC1_PRIVCFGR3_SAES_Pos           GTZC_CFGR3_SAES_Pos
26430 #define GTZC_TZSC1_PRIVCFGR3_SAES_Msk           GTZC_CFGR3_SAES_Msk
26431 #define GTZC_TZSC1_PRIVCFGR3_OCTOSPIM_Pos       GTZC_CFGR3_OCTOSPIM_Pos
26432 #define GTZC_TZSC1_PRIVCFGR3_OCTOSPIM_Msk       GTZC_CFGR3_OCTOSPIM_Msk
26433 #define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos         GTZC_CFGR3_SDMMC1_Pos
26434 #define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk         GTZC_CFGR3_SDMMC1_Msk
26435 #define GTZC_TZSC1_PRIVCFGR3_SDMMC2_Pos         GTZC_CFGR3_SDMMC2_Pos
26436 #define GTZC_TZSC1_PRIVCFGR3_SDMMC2_Msk         GTZC_CFGR3_SDMMC2_Msk
26437 #define GTZC_TZSC1_PRIVCFGR3_FSMC_REG_Pos       GTZC_CFGR3_FSMC_REG_Pos
26438 #define GTZC_TZSC1_PRIVCFGR3_FSMC_REG_Msk       GTZC_CFGR3_FSMC_REG_Msk
26439 #define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_REG_Pos   GTZC_CFGR3_OCTOSPI1_REG_Pos
26440 #define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_REG_Msk   GTZC_CFGR3_OCTOSPI1_REG_Msk
26441 #define GTZC_TZSC1_PRIVCFGR3_OCTOSPI2_REG_Pos   GTZC_CFGR3_OCTOSPI2_REG_Pos
26442 #define GTZC_TZSC1_PRIVCFGR3_OCTOSPI2_REG_Msk   GTZC_CFGR3_OCTOSPI2_REG_Msk
26443 #define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos         GTZC_CFGR3_RAMCFG_Pos
26444 #define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk         GTZC_CFGR3_RAMCFG_Msk
26445 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos          GTZC_CFGR3_GPU2D_Pos
26446 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Msk          GTZC_CFGR3_GPU2D_Msk
26447 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_Pos         GTZC_CFGR3_GFXMMU_Pos
26448 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_Msk         GTZC_CFGR3_GFXMMU_Msk
26449 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Pos     GTZC_CFGR3_GFXMMU_REG_Pos
26450 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Msk     GTZC_CFGR3_GFXMMU_REG_Msk
26451 #define GTZC_TZSC1_PRIVCFGR3_HSPI1_REG_Pos      GTZC_CFGR3_HSPI1_REG_Pos
26452 #define GTZC_TZSC1_PRIVCFGR3_HSPI1_REG_Msk      GTZC_CFGR3_HSPI1_REG_Msk
26453 #define GTZC_TZSC1_PRIVCFGR3_DCACHE2_REG_Pos    GTZC_CFGR3_DCACHE2_REG_Pos
26454 #define GTZC_TZSC1_PRIVCFGR3_DCACHE2_REG_Msk    GTZC_CFGR3_DCACHE2_REG_Msk
26455 #define GTZC_TZSC1_PRIVCFGR3_JPEG_Pos           GTZC_CFGR3_JPEG_REG_Pos
26456 #define GTZC_TZSC1_PRIVCFGR3_JPEG_Msk           GTZC_CFGR3_JPEG_REG_Msk
26457 
26458 /*******************  Bits definition for GTZC_TZSC2_SECCFGR1 register  ***************/
26459 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos           GTZC_CFGR1_SPI3_Pos
26460 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Msk           GTZC_CFGR1_SPI3_Msk
26461 #define GTZC_TZSC2_PRIVCFGR1_LPUART1_Pos        GTZC_CFGR1_LPUART1_Pos
26462 #define GTZC_TZSC2_PRIVCFGR1_LPUART1_Msk        GTZC_CFGR1_LPUART1_Msk
26463 #define GTZC_TZSC2_PRIVCFGR1_I2C3_Pos           GTZC_CFGR1_I2C3_Pos
26464 #define GTZC_TZSC2_PRIVCFGR1_I2C3_Msk           GTZC_CFGR1_I2C3_Msk
26465 #define GTZC_TZSC2_PRIVCFGR1_LPTIM1_Pos         GTZC_CFGR1_LPTIM1_Pos
26466 #define GTZC_TZSC2_PRIVCFGR1_LPTIM1_Msk         GTZC_CFGR1_LPTIM1_Msk
26467 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos         GTZC_CFGR1_LPTIM3_Pos
26468 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Msk         GTZC_CFGR1_LPTIM3_Msk
26469 #define GTZC_TZSC2_PRIVCFGR1_LPTIM4_Pos         GTZC_CFGR1_LPTIM4_Pos
26470 #define GTZC_TZSC2_PRIVCFGR1_LPTIM4_Msk         GTZC_CFGR1_LPTIM4_Msk
26471 #define GTZC_TZSC2_PRIVCFGR1_OPAMP_Pos          GTZC_CFGR1_OPAMP_Pos
26472 #define GTZC_TZSC2_PRIVCFGR1_OPAMP_Msk          GTZC_CFGR1_OPAMP_Msk
26473 #define GTZC_TZSC2_PRIVCFGR1_COMP_Pos           GTZC_CFGR1_COMP_Pos
26474 #define GTZC_TZSC2_PRIVCFGR1_COMP_Msk           GTZC_CFGR1_COMP_Msk
26475 #define GTZC_TZSC2_PRIVCFGR1_ADC4_Pos           GTZC_CFGR1_ADC4_Pos
26476 #define GTZC_TZSC2_PRIVCFGR1_ADC4_Msk           GTZC_CFGR1_ADC4_Msk
26477 #define GTZC_TZSC2_PRIVCFGR1_VREFBUF_Pos        GTZC_CFGR1_VREFBUF_Pos
26478 #define GTZC_TZSC2_PRIVCFGR1_VREFBUF_Msk        GTZC_CFGR1_VREFBUF_Msk
26479 #define GTZC_TZSC2_PRIVCFGR1_DAC1_Pos           GTZC_CFGR1_DAC1_Pos
26480 #define GTZC_TZSC2_PRIVCFGR1_DAC1_Msk           GTZC_CFGR1_DAC1_Msk
26481 #define GTZC_TZSC2_PRIVCFGR1_ADF1_Pos           GTZC_CFGR1_ADF1_Pos
26482 #define GTZC_TZSC2_PRIVCFGR1_ADF1_Msk           GTZC_CFGR1_ADF1_Msk
26483 
26484 /*******************  Bits definition for GTZC_TZIC1_IER1 register  ***************/
26485 #define GTZC_TZIC1_IER1_TIM2_Pos            GTZC_CFGR1_TIM2_Pos
26486 #define GTZC_TZIC1_IER1_TIM2_Msk            GTZC_CFGR1_TIM2_Msk
26487 #define GTZC_TZIC1_IER1_TIM3_Pos            GTZC_CFGR1_TIM3_Pos
26488 #define GTZC_TZIC1_IER1_TIM3_Msk            GTZC_CFGR1_TIM3_Msk
26489 #define GTZC_TZIC1_IER1_TIM4_Pos            GTZC_CFGR1_TIM4_Pos
26490 #define GTZC_TZIC1_IER1_TIM4_Msk            GTZC_CFGR1_TIM4_Msk
26491 #define GTZC_TZIC1_IER1_TIM5_Pos            GTZC_CFGR1_TIM5_Pos
26492 #define GTZC_TZIC1_IER1_TIM5_Msk            GTZC_CFGR1_TIM5_Msk
26493 #define GTZC_TZIC1_IER1_TIM6_Pos            GTZC_CFGR1_TIM6_Pos
26494 #define GTZC_TZIC1_IER1_TIM6_Msk            GTZC_CFGR1_TIM6_Msk
26495 #define GTZC_TZIC1_IER1_TIM7_Pos            GTZC_CFGR1_TIM7_Pos
26496 #define GTZC_TZIC1_IER1_TIM7_Msk            GTZC_CFGR1_TIM7_Msk
26497 #define GTZC_TZIC1_IER1_WWDG_Pos            GTZC_CFGR1_WWDG_Pos
26498 #define GTZC_TZIC1_IER1_WWDG_Msk            GTZC_CFGR1_WWDG_Msk
26499 #define GTZC_TZIC1_IER1_IWDG_Pos            GTZC_CFGR1_IWDG_Pos
26500 #define GTZC_TZIC1_IER1_IWDG_Msk            GTZC_CFGR1_IWDG_Msk
26501 #define GTZC_TZIC1_IER1_SPI2_Pos            GTZC_CFGR1_SPI2_Pos
26502 #define GTZC_TZIC1_IER1_SPI2_Msk            GTZC_CFGR1_SPI2_Msk
26503 #define GTZC_TZIC1_IER1_USART2_Pos          GTZC_CFGR1_USART2_Pos
26504 #define GTZC_TZIC1_IER1_USART2_Msk          GTZC_CFGR1_USART2_Msk
26505 #define GTZC_TZIC1_IER1_USART3_Pos          GTZC_CFGR1_USART3_Pos
26506 #define GTZC_TZIC1_IER1_USART3_Msk          GTZC_CFGR1_USART3_Msk
26507 #define GTZC_TZIC1_IER1_UART4_Pos           GTZC_CFGR1_UART4_Pos
26508 #define GTZC_TZIC1_IER1_UART4_Msk           GTZC_CFGR1_UART4_Msk
26509 #define GTZC_TZIC1_IER1_UART5_Pos           GTZC_CFGR1_UART5_Pos
26510 #define GTZC_TZIC1_IER1_UART5_Msk           GTZC_CFGR1_UART5_Msk
26511 #define GTZC_TZIC1_IER1_I2C1_Pos            GTZC_CFGR1_I2C1_Pos
26512 #define GTZC_TZIC1_IER1_I2C1_Msk            GTZC_CFGR1_I2C1_Msk
26513 #define GTZC_TZIC1_IER1_I2C2_Pos            GTZC_CFGR1_I2C2_Pos
26514 #define GTZC_TZIC1_IER1_I2C2_Msk            GTZC_CFGR1_I2C2_Msk
26515 #define GTZC_TZIC1_IER1_CRS_Pos             GTZC_CFGR1_CRS_Pos
26516 #define GTZC_TZIC1_IER1_CRS_Msk             GTZC_CFGR1_CRS_Msk
26517 #define GTZC_TZIC1_IER1_I2C4_Pos            GTZC_CFGR1_I2C4_Pos
26518 #define GTZC_TZIC1_IER1_I2C4_Msk            GTZC_CFGR1_I2C4_Msk
26519 #define GTZC_TZIC1_IER1_LPTIM2_Pos          GTZC_CFGR1_LPTIM2_Pos
26520 #define GTZC_TZIC1_IER1_LPTIM2_Msk          GTZC_CFGR1_LPTIM2_Msk
26521 #define GTZC_TZIC1_IER1_FDCAN1_Pos          GTZC_CFGR1_FDCAN1_Pos
26522 #define GTZC_TZIC1_IER1_FDCAN1_Msk          GTZC_CFGR1_FDCAN1_Msk
26523 #define GTZC_TZIC1_IER1_UCPD1_Pos           GTZC_CFGR1_UCPD1_Pos
26524 #define GTZC_TZIC1_IER1_UCPD1_Msk           GTZC_CFGR1_UCPD1_Msk
26525 #define GTZC_TZIC1_IER1_USART6_Pos          GTZC_CFGR1_USART6_Pos
26526 #define GTZC_TZIC1_IER1_USART6_Msk          GTZC_CFGR1_USART6_Msk
26527 #define GTZC_TZIC1_IER1_I2C5_Pos            GTZC_CFGR1_I2C5_Pos
26528 #define GTZC_TZIC1_IER1_I2C5_Msk            GTZC_CFGR1_I2C5_Msk
26529 #define GTZC_TZIC1_IER1_I2C6_Pos            GTZC_CFGR1_I2C6_Pos
26530 #define GTZC_TZIC1_IER1_I2C6_Msk            GTZC_CFGR1_I2C6_Msk
26531 
26532 /*******************  Bits definition for GTZC_TZIC1_IER2 register  ***************/
26533 #define GTZC_TZIC1_IER2_TIM1_Pos            GTZC_CFGR2_TIM1_Pos
26534 #define GTZC_TZIC1_IER2_TIM1_Msk            GTZC_CFGR2_TIM1_Msk
26535 #define GTZC_TZIC1_IER2_SPI1_Pos            GTZC_CFGR2_SPI1_Pos
26536 #define GTZC_TZIC1_IER2_SPI1_Msk            GTZC_CFGR2_SPI1_Msk
26537 #define GTZC_TZIC1_IER2_TIM8_Pos            GTZC_CFGR2_TIM8_Pos
26538 #define GTZC_TZIC1_IER2_TIM8_Msk            GTZC_CFGR2_TIM8_Msk
26539 #define GTZC_TZIC1_IER2_USART1_Pos          GTZC_CFGR2_USART1_Pos
26540 #define GTZC_TZIC1_IER2_USART1_Msk          GTZC_CFGR2_USART1_Msk
26541 #define GTZC_TZIC1_IER2_TIM15_Pos           GTZC_CFGR2_TIM15_Pos
26542 #define GTZC_TZIC1_IER2_TIM15_Msk           GTZC_CFGR2_TIM15_Msk
26543 #define GTZC_TZIC1_IER2_TIM16_Pos           GTZC_CFGR2_TIM16_Pos
26544 #define GTZC_TZIC1_IER2_TIM16_Msk           GTZC_CFGR2_TIM16_Msk
26545 #define GTZC_TZIC1_IER2_TIM17_Pos           GTZC_CFGR2_TIM17_Pos
26546 #define GTZC_TZIC1_IER2_TIM17_Msk           GTZC_CFGR2_TIM17_Msk
26547 #define GTZC_TZIC1_IER2_SAI1_Pos            GTZC_CFGR2_SAI1_Pos
26548 #define GTZC_TZIC1_IER2_SAI1_Msk            GTZC_CFGR2_SAI1_Msk
26549 #define GTZC_TZIC1_IER2_SAI2_Pos            GTZC_CFGR2_SAI2_Pos
26550 #define GTZC_TZIC1_IER2_SAI2_Msk            GTZC_CFGR2_SAI2_Msk
26551 #define GTZC_TZIC1_IER2_LTDCUSB_Pos         GTZC_CFGR2_LTDCUSB_Pos
26552 #define GTZC_TZIC1_IER2_LTDCUSB_Msk         GTZC_CFGR2_LTDCUSB_Msk
26553 #define GTZC_TZIC1_IER2_DSI_Pos             GTZC_CFGR2_DSI_Pos
26554 #define GTZC_TZIC1_IER2_DSI_Msk             GTZC_CFGR2_DSI_Msk
26555 #define GTZC_TZIC1_IER2_GFXTIM_Pos          GTZC_CFGR2_GFXTIM_Pos
26556 #define GTZC_TZIC1_IER2_GFXTIM_Msk          GTZC_CFGR2_GFXTIM_Msk
26557 
26558 /*******************  Bits definition for GTZC_TZIC1_IER3 register  ***************/
26559 #define GTZC_TZIC1_IER3_MDF1_Pos            GTZC_CFGR3_MDF1_Pos
26560 #define GTZC_TZIC1_IER3_MDF1_Msk            GTZC_CFGR3_MDF1_Msk
26561 #define GTZC_TZIC1_IER3_CORDIC_Pos          GTZC_CFGR3_CORDIC_Pos
26562 #define GTZC_TZIC1_IER3_CORDIC_Msk          GTZC_CFGR3_CORDIC_Msk
26563 #define GTZC_TZIC1_IER3_FMAC_Pos            GTZC_CFGR3_FMAC_Pos
26564 #define GTZC_TZIC1_IER3_FMAC_Msk            GTZC_CFGR3_FMAC_Msk
26565 #define GTZC_TZIC1_IER3_CRC_Pos             GTZC_CFGR3_CRC_Pos
26566 #define GTZC_TZIC1_IER3_CRC_Msk             GTZC_CFGR3_CRC_Msk
26567 #define GTZC_TZIC1_IER3_TSC_Pos             GTZC_CFGR3_TSC_Pos
26568 #define GTZC_TZIC1_IER3_TSC_Msk             GTZC_CFGR3_TSC_Msk
26569 #define GTZC_TZIC1_IER3_DMA2D_Pos           GTZC_CFGR3_DMA2D_Pos
26570 #define GTZC_TZIC1_IER3_DMA2D_Msk           GTZC_CFGR3_DMA2D_Msk
26571 #define GTZC_TZIC1_IER3_ICACHE_REG_Pos      GTZC_CFGR3_ICACHE_REG_Pos
26572 #define GTZC_TZIC1_IER3_ICACHE_REG_Msk      GTZC_CFGR3_ICACHE_REG_Msk
26573 #define GTZC_TZIC1_IER3_DCACHE1_REG_Pos     GTZC_CFGR3_DCACHE1_REG_Pos
26574 #define GTZC_TZIC1_IER3_DCACHE1_REG_Msk     GTZC_CFGR3_DCACHE1_REG_Msk
26575 #define GTZC_TZIC1_IER3_ADC12_Pos           GTZC_CFGR3_ADC12_Pos
26576 #define GTZC_TZIC1_IER3_ADC12_Msk           GTZC_CFGR3_ADC12_Msk
26577 #define GTZC_TZIC1_IER3_DCMI_Pos            GTZC_CFGR3_DCMI_Pos
26578 #define GTZC_TZIC1_IER3_DCMI_Msk            GTZC_CFGR3_DCMI_Msk
26579 #define GTZC_TZIC1_IER3_OTG_Pos             GTZC_CFGR3_OTG_Pos
26580 #define GTZC_TZIC1_IER3_OTG_Msk             GTZC_CFGR3_OTG_Msk
26581 #define GTZC_TZIC1_IER3_AES_Pos             GTZC_CFGR3_AES_Pos
26582 #define GTZC_TZIC1_IER3_AES_Msk             GTZC_CFGR3_AES_Msk
26583 #define GTZC_TZIC1_IER3_HASH_Pos            GTZC_CFGR3_HASH_Pos
26584 #define GTZC_TZIC1_IER3_HASH_Msk            GTZC_CFGR3_HASH_Msk
26585 #define GTZC_TZIC1_IER3_RNG_Pos             GTZC_CFGR3_RNG_Pos
26586 #define GTZC_TZIC1_IER3_RNG_Msk             GTZC_CFGR3_RNG_Msk
26587 #define GTZC_TZIC1_IER3_PKA_Pos             GTZC_CFGR3_PKA_Pos
26588 #define GTZC_TZIC1_IER3_PKA_Msk             GTZC_CFGR3_PKA_Msk
26589 #define GTZC_TZIC1_IER3_SAES_Pos            GTZC_CFGR3_SAES_Pos
26590 #define GTZC_TZIC1_IER3_SAES_Msk            GTZC_CFGR3_SAES_Msk
26591 #define GTZC_TZIC1_IER3_OCTOSPIM_Pos        GTZC_CFGR3_OCTOSPIM_Pos
26592 #define GTZC_TZIC1_IER3_OCTOSPIM_Msk        GTZC_CFGR3_OCTOSPIM_Msk
26593 #define GTZC_TZIC1_IER3_SDMMC1_Pos          GTZC_CFGR3_SDMMC1_Pos
26594 #define GTZC_TZIC1_IER3_SDMMC1_Msk          GTZC_CFGR3_SDMMC1_Msk
26595 #define GTZC_TZIC1_IER3_SDMMC2_Pos          GTZC_CFGR3_SDMMC2_Pos
26596 #define GTZC_TZIC1_IER3_SDMMC2_Msk          GTZC_CFGR3_SDMMC2_Msk
26597 #define GTZC_TZIC1_IER3_FSMC_REG_Pos        GTZC_CFGR3_FSMC_REG_Pos
26598 #define GTZC_TZIC1_IER3_FSMC_REG_Msk        GTZC_CFGR3_FSMC_REG_Msk
26599 #define GTZC_TZIC1_IER3_OCTOSPI1_REG_Pos    GTZC_CFGR3_OCTOSPI1_REG_Pos
26600 #define GTZC_TZIC1_IER3_OCTOSPI1_REG_Msk    GTZC_CFGR3_OCTOSPI1_REG_Msk
26601 #define GTZC_TZIC1_IER3_OCTOSPI2_REG_Pos    GTZC_CFGR3_OCTOSPI2_REG_Pos
26602 #define GTZC_TZIC1_IER3_OCTOSPI2_REG_Msk    GTZC_CFGR3_OCTOSPI2_REG_Msk
26603 #define GTZC_TZIC1_IER3_RAMCFG_Pos          GTZC_CFGR3_RAMCFG_Pos
26604 #define GTZC_TZIC1_IER3_RAMCFG_Msk          GTZC_CFGR3_RAMCFG_Msk
26605 #define GTZC_TZIC1_IER3_GPU2D_Pos           GTZC_CFGR3_GPU2D_Pos
26606 #define GTZC_TZIC1_IER3_GPU2D_Msk           GTZC_CFGR3_GPU2D_Msk
26607 #define GTZC_TZIC1_IER3_GFXMMU_Pos          GTZC_CFGR3_GFXMMU_Pos
26608 #define GTZC_TZIC1_IER3_GFXMMU_Msk          GTZC_CFGR3_GFXMMU_Msk
26609 #define GTZC_TZIC1_IER3_GFXMMU_REG_Pos      GTZC_CFGR3_GFXMMU_REG_Pos
26610 #define GTZC_TZIC1_IER3_GFXMMU_REG_Msk      GTZC_CFGR3_GFXMMU_REG_Msk
26611 #define GTZC_TZIC1_IER3_HSPI1_REG_Pos       GTZC_CFGR3_HSPI1_REG_Pos
26612 #define GTZC_TZIC1_IER3_HSPI1_REG_Msk       GTZC_CFGR3_HSPI1_REG_Msk
26613 #define GTZC_TZIC1_IER3_DCACHE2_REG_Pos     GTZC_CFGR3_DCACHE2_REG_Pos
26614 #define GTZC_TZIC1_IER3_DCACHE2_REG_Msk     GTZC_CFGR3_DCACHE2_REG_Msk
26615 #define GTZC_TZIC1_IER3_JPEG_Pos            GTZC_CFGR3_JPEG_REG_Pos
26616 #define GTZC_TZIC1_IER3_JPEG_Msk            GTZC_CFGR3_JPEG_REG_Msk
26617 
26618 /*******************  Bits definition for GTZC_TZIC1_IER4 register  ***************/
26619 #define GTZC_TZIC1_IER4_GPDMA1_Pos          GTZC_CFGR4_GPDMA1_Pos
26620 #define GTZC_TZIC1_IER4_GPDMA1_Msk          GTZC_CFGR4_GPDMA1_Msk
26621 #define GTZC_TZIC1_IER4_FLASH_REG_Pos       GTZC_CFGR4_FLASH_REG_Pos
26622 #define GTZC_TZIC1_IER4_FLASH_REG_Msk       GTZC_CFGR4_FLASH_REG_Msk
26623 #define GTZC_TZIC1_IER4_FLASH_Pos           GTZC_CFGR4_FLASH_Pos
26624 #define GTZC_TZIC1_IER4_FLASH_Msk           GTZC_CFGR4_FLASH_Msk
26625 #define GTZC_TZIC1_IER4_OTFDEC1_Pos         GTZC_CFGR4_OTFDEC1_Pos
26626 #define GTZC_TZIC1_IER4_OTFDEC1_Msk         GTZC_CFGR4_OTFDEC1_Msk
26627 #define GTZC_TZIC1_IER4_OTFDEC2_Pos         GTZC_CFGR4_OTFDEC2_Pos
26628 #define GTZC_TZIC1_IER4_OTFDEC2_Msk         GTZC_CFGR4_OTFDEC2_Msk
26629 #define GTZC_TZIC1_IER4_TZSC1_Pos           GTZC_CFGR4_TZSC1_Pos
26630 #define GTZC_TZIC1_IER4_TZSC1_Msk           GTZC_CFGR4_TZSC1_Msk
26631 #define GTZC_TZIC1_IER4_TZIC1_Pos           GTZC_CFGR4_TZIC1_Pos
26632 #define GTZC_TZIC1_IER4_TZIC1_Msk           GTZC_CFGR4_TZIC1_Msk
26633 #define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Pos    GTZC_CFGR4_OCTOSPI1_MEM_Pos
26634 #define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Msk    GTZC_CFGR4_OCTOSPI1_MEM_Msk
26635 #define GTZC_TZIC1_IER4_FSMC_MEM_Pos        GTZC_CFGR4_FSMC_MEM_Pos
26636 #define GTZC_TZIC1_IER4_FSMC_MEM_Msk        GTZC_CFGR4_FSMC_MEM_Msk
26637 #define GTZC_TZIC1_IER4_BKPSRAM_Pos         GTZC_CFGR4_BKPSRAM_Pos
26638 #define GTZC_TZIC1_IER4_BKPSRAM_Msk         GTZC_CFGR4_BKPSRAM_Msk
26639 #define GTZC_TZIC1_IER4_OCTOSPI2_MEM_Pos    GTZC_CFGR4_OCTOSPI2_MEM_Pos
26640 #define GTZC_TZIC1_IER4_OCTOSPI2_MEM_Msk    GTZC_CFGR4_OCTOSPI2_MEM_Msk
26641 #define GTZC_TZIC1_IER4_HSPI1_MEM_Pos       GTZC_CFGR4_HSPI1_MEM_Pos
26642 #define GTZC_TZIC1_IER4_HSPI1_MEM_Msk       GTZC_CFGR4_HSPI1_MEM_Msk
26643 #define GTZC_TZIC1_IER4_SRAM6_Pos           GTZC_CFGR4_SRAM6_Pos
26644 #define GTZC_TZIC1_IER4_SRAM6_Msk           GTZC_CFGR4_SRAM6_Msk
26645 #define GTZC_TZIC1_IER4_MPCBB6_REG_Pos      GTZC_CFGR4_MPCBB6_REG_Pos
26646 #define GTZC_TZIC1_IER4_MPCBB6_REG_Msk      GTZC_CFGR4_MPCBB6_REG_Msk
26647 #define GTZC_TZIC1_IER4_SRAM1_Pos           GTZC_CFGR4_SRAM1_Pos
26648 #define GTZC_TZIC1_IER4_SRAM1_Msk           GTZC_CFGR4_SRAM1_Msk
26649 #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos      GTZC_CFGR4_MPCBB1_REG_Pos
26650 #define GTZC_TZIC1_IER4_MPCBB1_REG_Msk      GTZC_CFGR4_MPCBB1_REG_Msk
26651 #define GTZC_TZIC1_IER4_SRAM2_Pos           GTZC_CFGR4_SRAM2_Pos
26652 #define GTZC_TZIC1_IER4_SRAM2_Msk           GTZC_CFGR4_SRAM2_Msk
26653 #define GTZC_TZIC1_IER4_MPCBB2_REG_Pos      GTZC_CFGR4_MPCBB2_REG_Pos
26654 #define GTZC_TZIC1_IER4_MPCBB2_REG_Msk      GTZC_CFGR4_MPCBB2_REG_Msk
26655 #define GTZC_TZIC1_IER4_SRAM3_Pos           GTZC_CFGR4_SRAM3_Pos
26656 #define GTZC_TZIC1_IER4_SRAM3_Msk           GTZC_CFGR4_SRAM3_Msk
26657 #define GTZC_TZIC1_IER4_MPCBB3_REG_Pos      GTZC_CFGR4_MPCBB3_REG_Pos
26658 #define GTZC_TZIC1_IER4_MPCBB3_REG_Msk      GTZC_CFGR4_MPCBB3_REG_Msk
26659 #define GTZC_TZIC1_IER4_SRAM5_Pos           GTZC_CFGR4_SRAM5_Pos
26660 #define GTZC_TZIC1_IER4_SRAM5_Msk           GTZC_CFGR4_SRAM5_Msk
26661 #define GTZC_TZIC1_IER4_MPCBB5_REG_Pos      GTZC_CFGR4_MPCBB5_REG_Pos
26662 #define GTZC_TZIC1_IER4_MPCBB5_REG_Msk      GTZC_CFGR4_MPCBB5_REG_Msk
26663 
26664 /*******************  Bits definition for GTZC_TZIC2_IER1 register  ***************/
26665 #define GTZC_TZIC2_IER1_SPI3_Pos            GTZC_CFGR1_SPI3_Pos
26666 #define GTZC_TZIC2_IER1_SPI3_Msk            GTZC_CFGR1_SPI3_Msk
26667 #define GTZC_TZIC2_IER1_LPUART1_Pos         GTZC_CFGR1_LPUART1_Pos
26668 #define GTZC_TZIC2_IER1_LPUART1_Msk         GTZC_CFGR1_LPUART1_Msk
26669 #define GTZC_TZIC2_IER1_I2C3_Pos            GTZC_CFGR1_I2C3_Pos
26670 #define GTZC_TZIC2_IER1_I2C3_Msk            GTZC_CFGR1_I2C3_Msk
26671 #define GTZC_TZIC2_IER1_LPTIM1_Pos          GTZC_CFGR1_LPTIM1_Pos
26672 #define GTZC_TZIC2_IER1_LPTIM1_Msk          GTZC_CFGR1_LPTIM1_Msk
26673 #define GTZC_TZIC2_IER1_LPTIM3_Pos          GTZC_CFGR1_LPTIM3_Pos
26674 #define GTZC_TZIC2_IER1_LPTIM3_Msk          GTZC_CFGR1_LPTIM3_Msk
26675 #define GTZC_TZIC2_IER1_LPTIM4_Pos          GTZC_CFGR1_LPTIM4_Pos
26676 #define GTZC_TZIC2_IER1_LPTIM4_Msk          GTZC_CFGR1_LPTIM4_Msk
26677 #define GTZC_TZIC2_IER1_OPAMP_Pos           GTZC_CFGR1_OPAMP_Pos
26678 #define GTZC_TZIC2_IER1_OPAMP_Msk           GTZC_CFGR1_OPAMP_Msk
26679 #define GTZC_TZIC2_IER1_COMP_Pos            GTZC_CFGR1_COMP_Pos
26680 #define GTZC_TZIC2_IER1_COMP_Msk            GTZC_CFGR1_COMP_Msk
26681 #define GTZC_TZIC2_IER1_ADC4_Pos            GTZC_CFGR1_ADC4_Pos
26682 #define GTZC_TZIC2_IER1_ADC4_Msk            GTZC_CFGR1_ADC4_Msk
26683 #define GTZC_TZIC2_IER1_VREFBUF_Pos         GTZC_CFGR1_VREFBUF_Pos
26684 #define GTZC_TZIC2_IER1_VREFBUF_Msk         GTZC_CFGR1_VREFBUF_Msk
26685 #define GTZC_TZIC2_IER1_DAC1_Pos            GTZC_CFGR1_DAC1_Pos
26686 #define GTZC_TZIC2_IER1_DAC1_Msk            GTZC_CFGR1_DAC1_Msk
26687 #define GTZC_TZIC2_IER1_ADF1_Pos            GTZC_CFGR1_ADF1_Pos
26688 #define GTZC_TZIC2_IER1_ADF1_Msk            GTZC_CFGR1_ADF1_Msk
26689 
26690 /*******************  Bits definition for GTZC_TZIC2_IER2 register  ***************/
26691 #define GTZC_TZIC2_IER2_SYSCFG_Pos          GTZC_CFGR2_SYSCFG_Pos
26692 #define GTZC_TZIC2_IER2_SYSCFG_Msk          GTZC_CFGR2_SYSCFG_Msk
26693 #define GTZC_TZIC2_IER2_RTC_Pos             GTZC_CFGR2_RTC_Pos
26694 #define GTZC_TZIC2_IER2_RTC_Msk             GTZC_CFGR2_RTC_Msk
26695 #define GTZC_TZIC2_IER2_TAMP_Pos            GTZC_CFGR2_TAMP_Pos
26696 #define GTZC_TZIC2_IER2_TAMP_Msk            GTZC_CFGR2_TAMP_Msk
26697 #define GTZC_TZIC2_IER2_PWR_Pos             GTZC_CFGR2_PWR_Pos
26698 #define GTZC_TZIC2_IER2_PWR_Msk             GTZC_CFGR2_PWR_Msk
26699 #define GTZC_TZIC2_IER2_RCC_Pos             GTZC_CFGR2_RCC_Pos
26700 #define GTZC_TZIC2_IER2_RCC_Msk             GTZC_CFGR2_RCC_Msk
26701 #define GTZC_TZIC2_IER2_LPDMA1_Pos          GTZC_CFGR2_LPDMA1_Pos
26702 #define GTZC_TZIC2_IER2_LPDMA1_Msk          GTZC_CFGR2_LPDMA1_Msk
26703 #define GTZC_TZIC2_IER2_EXTI_Pos            GTZC_CFGR2_EXTI_Pos
26704 #define GTZC_TZIC2_IER2_EXTI_Msk            GTZC_CFGR2_EXTI_Msk
26705 #define GTZC_TZIC2_IER2_TZSC2_Pos           GTZC_CFGR2_TZSC2_Pos
26706 #define GTZC_TZIC2_IER2_TZSC2_Msk           GTZC_CFGR2_TZSC2_Msk
26707 #define GTZC_TZIC2_IER2_TZIC2_Pos           GTZC_CFGR2_TZIC2_Pos
26708 #define GTZC_TZIC2_IER2_TZIC2_Msk           GTZC_CFGR2_TZIC2_Msk
26709 #define GTZC_TZIC2_IER2_SRAM4_Pos           GTZC_CFGR2_SRAM4_Pos
26710 #define GTZC_TZIC2_IER2_SRAM4_Msk           GTZC_CFGR2_SRAM4_Msk
26711 #define GTZC_TZIC2_IER2_MPCBB4_REG_Pos      GTZC_CFGR2_MPCBB4_REG_Pos
26712 #define GTZC_TZIC2_IER2_MPCBB4_REG_Msk      GTZC_CFGR2_MPCBB4_REG_Msk
26713 
26714 /*******************  Bits definition for GTZC_TZIC1_SR1 register  **************/
26715 #define GTZC_TZIC1_SR1_TIM2_Pos             GTZC_CFGR1_TIM2_Pos
26716 #define GTZC_TZIC1_SR1_TIM2_Msk             GTZC_CFGR1_TIM2_Msk
26717 #define GTZC_TZIC1_SR1_TIM3_Pos             GTZC_CFGR1_TIM3_Pos
26718 #define GTZC_TZIC1_SR1_TIM3_Msk             GTZC_CFGR1_TIM3_Msk
26719 #define GTZC_TZIC1_SR1_TIM4_Pos             GTZC_CFGR1_TIM4_Pos
26720 #define GTZC_TZIC1_SR1_TIM4_Msk             GTZC_CFGR1_TIM4_Msk
26721 #define GTZC_TZIC1_SR1_TIM5_Pos             GTZC_CFGR1_TIM5_Pos
26722 #define GTZC_TZIC1_SR1_TIM5_Msk             GTZC_CFGR1_TIM5_Msk
26723 #define GTZC_TZIC1_SR1_TIM6_Pos             GTZC_CFGR1_TIM6_Pos
26724 #define GTZC_TZIC1_SR1_TIM6_Msk             GTZC_CFGR1_TIM6_Msk
26725 #define GTZC_TZIC1_SR1_TIM7_Pos             GTZC_CFGR1_TIM7_Pos
26726 #define GTZC_TZIC1_SR1_TIM7_Msk             GTZC_CFGR1_TIM7_Msk
26727 #define GTZC_TZIC1_SR1_WWDG_Pos             GTZC_CFGR1_WWDG_Pos
26728 #define GTZC_TZIC1_SR1_WWDG_Msk             GTZC_CFGR1_WWDG_Msk
26729 #define GTZC_TZIC1_SR1_IWDG_Pos             GTZC_CFGR1_IWDG_Pos
26730 #define GTZC_TZIC1_SR1_IWDG_Msk             GTZC_CFGR1_IWDG_Msk
26731 #define GTZC_TZIC1_SR1_SPI2_Pos             GTZC_CFGR1_SPI2_Pos
26732 #define GTZC_TZIC1_SR1_SPI2_Msk             GTZC_CFGR1_SPI2_Msk
26733 #define GTZC_TZIC1_SR1_USART2_Pos           GTZC_CFGR1_USART2_Pos
26734 #define GTZC_TZIC1_SR1_USART2_Msk           GTZC_CFGR1_USART2_Msk
26735 #define GTZC_TZIC1_SR1_USART3_Pos           GTZC_CFGR1_USART3_Pos
26736 #define GTZC_TZIC1_SR1_USART3_Msk           GTZC_CFGR1_USART3_Msk
26737 #define GTZC_TZIC1_SR1_UART4_Pos            GTZC_CFGR1_UART4_Pos
26738 #define GTZC_TZIC1_SR1_UART4_Msk            GTZC_CFGR1_UART4_Msk
26739 #define GTZC_TZIC1_SR1_UART5_Pos            GTZC_CFGR1_UART5_Pos
26740 #define GTZC_TZIC1_SR1_UART5_Msk            GTZC_CFGR1_UART5_Msk
26741 #define GTZC_TZIC1_SR1_I2C1_Pos             GTZC_CFGR1_I2C1_Pos
26742 #define GTZC_TZIC1_SR1_I2C1_Msk             GTZC_CFGR1_I2C1_Msk
26743 #define GTZC_TZIC1_SR1_I2C2_Pos             GTZC_CFGR1_I2C2_Pos
26744 #define GTZC_TZIC1_SR1_I2C2_Msk             GTZC_CFGR1_I2C2_Msk
26745 #define GTZC_TZIC1_SR1_CRS_Pos              GTZC_CFGR1_CRS_Pos
26746 #define GTZC_TZIC1_SR1_CRS_Msk              GTZC_CFGR1_CRS_Msk
26747 #define GTZC_TZIC1_SR1_I2C4_Pos             GTZC_CFGR1_I2C4_Pos
26748 #define GTZC_TZIC1_SR1_I2C4_Msk             GTZC_CFGR1_I2C4_Msk
26749 #define GTZC_TZIC1_SR1_LPTIM2_Pos           GTZC_CFGR1_LPTIM2_Pos
26750 #define GTZC_TZIC1_SR1_LPTIM2_Msk           GTZC_CFGR1_LPTIM2_Msk
26751 #define GTZC_TZIC1_SR1_FDCAN1_Pos           GTZC_CFGR1_FDCAN1_Pos
26752 #define GTZC_TZIC1_SR1_FDCAN1_Msk           GTZC_CFGR1_FDCAN1_Msk
26753 #define GTZC_TZIC1_SR1_UCPD1_Pos            GTZC_CFGR1_UCPD1_Pos
26754 #define GTZC_TZIC1_SR1_UCPD1_Msk            GTZC_CFGR1_UCPD1_Msk
26755 #define GTZC_TZIC1_SR1_USART6_Pos           GTZC_CFGR1_USART6_Pos
26756 #define GTZC_TZIC1_SR1_USART6_Msk           GTZC_CFGR1_USART6_Msk
26757 #define GTZC_TZIC1_SR1_I2C5_Pos             GTZC_CFGR1_I2C5_Pos
26758 #define GTZC_TZIC1_SR1_I2C5_Msk             GTZC_CFGR1_I2C5_Msk
26759 #define GTZC_TZIC1_SR1_I2C6_Pos             GTZC_CFGR1_I2C6_Pos
26760 #define GTZC_TZIC1_SR1_I2C6_Msk             GTZC_CFGR1_I2C6_Msk
26761 
26762 /*******************  Bits definition for GTZC_TZIC1_SR2 register  **************/
26763 #define GTZC_TZIC1_SR2_TIM1_Pos             GTZC_CFGR2_TIM1_Pos
26764 #define GTZC_TZIC1_SR2_TIM1_Msk             GTZC_CFGR2_TIM1_Msk
26765 #define GTZC_TZIC1_SR2_SPI1_Pos             GTZC_CFGR2_SPI1_Pos
26766 #define GTZC_TZIC1_SR2_SPI1_Msk             GTZC_CFGR2_SPI1_Msk
26767 #define GTZC_TZIC1_SR2_TIM8_Pos             GTZC_CFGR2_TIM8_Pos
26768 #define GTZC_TZIC1_SR2_TIM8_Msk             GTZC_CFGR2_TIM8_Msk
26769 #define GTZC_TZIC1_SR2_USART1_Pos           GTZC_CFGR2_USART1_Pos
26770 #define GTZC_TZIC1_SR2_USART1_Msk           GTZC_CFGR2_USART1_Msk
26771 #define GTZC_TZIC1_SR2_TIM15_Pos            GTZC_CFGR2_TIM15_Pos
26772 #define GTZC_TZIC1_SR2_TIM15_Msk            GTZC_CFGR2_TIM15_Msk
26773 #define GTZC_TZIC1_SR2_TIM16_Pos            GTZC_CFGR2_TIM16_Pos
26774 #define GTZC_TZIC1_SR2_TIM16_Msk            GTZC_CFGR2_TIM16_Msk
26775 #define GTZC_TZIC1_SR2_TIM17_Pos            GTZC_CFGR2_TIM17_Pos
26776 #define GTZC_TZIC1_SR2_TIM17_Msk            GTZC_CFGR2_TIM17_Msk
26777 #define GTZC_TZIC1_SR2_SAI1_Pos             GTZC_CFGR2_SAI1_Pos
26778 #define GTZC_TZIC1_SR2_SAI1_Msk             GTZC_CFGR2_SAI1_Msk
26779 #define GTZC_TZIC1_SR2_SAI2_Pos             GTZC_CFGR2_SAI2_Pos
26780 #define GTZC_TZIC1_SR2_SAI2_Msk             GTZC_CFGR2_SAI2_Msk
26781 #define GTZC_TZIC1_SR2_LTDCUSB_Pos          GTZC_CFGR2_LTDCUSB_Pos
26782 #define GTZC_TZIC1_SR2_LTDCUSB_Msk          GTZC_CFGR2_LTDCUSB_Msk
26783 #define GTZC_TZIC1_SR2_DSI_Pos              GTZC_CFGR2_DSI_Pos
26784 #define GTZC_TZIC1_SR2_DSI_Msk              GTZC_CFGR2_DSI_Msk
26785 #define GTZC_TZIC1_SR2_GFXTIM_Pos           GTZC_CFGR2_GFXTIM_Pos
26786 #define GTZC_TZIC1_SR2_GFXTIM_Msk           GTZC_CFGR2_GFXTIM_Msk
26787 
26788 /*******************  Bits definition for GTZC_TZIC1_SR3 register  **************/
26789 #define GTZC_TZIC1_SR3_MDF1_Pos             GTZC_CFGR3_MDF1_Pos
26790 #define GTZC_TZIC1_SR3_MDF1_Msk             GTZC_CFGR3_MDF1_Msk
26791 #define GTZC_TZIC1_SR3_CORDIC_Pos           GTZC_CFGR3_CORDIC_Pos
26792 #define GTZC_TZIC1_SR3_CORDIC_Msk           GTZC_CFGR3_CORDIC_Msk
26793 #define GTZC_TZIC1_SR3_FMAC_Pos             GTZC_CFGR3_FMAC_Pos
26794 #define GTZC_TZIC1_SR3_FMAC_Msk             GTZC_CFGR3_FMAC_Msk
26795 #define GTZC_TZIC1_SR3_CRC_Pos              GTZC_CFGR3_CRC_Pos
26796 #define GTZC_TZIC1_SR3_CRC_Msk              GTZC_CFGR3_CRC_Msk
26797 #define GTZC_TZIC1_SR3_TSC_Pos              GTZC_CFGR3_TSC_Pos
26798 #define GTZC_TZIC1_SR3_TSC_Msk              GTZC_CFGR3_TSC_Msk
26799 #define GTZC_TZIC1_SR3_DMA2D_Pos            GTZC_CFGR3_DMA2D_Pos
26800 #define GTZC_TZIC1_SR3_DMA2D_Msk            GTZC_CFGR3_DMA2D_Msk
26801 #define GTZC_TZIC1_SR3_ICACHE_REG_Pos       GTZC_CFGR3_ICACHE_REG_Pos
26802 #define GTZC_TZIC1_SR3_ICACHE_REG_Msk       GTZC_CFGR3_ICACHE_REG_Msk
26803 #define GTZC_TZIC1_SR3_DCACHE1_REG_Pos      GTZC_CFGR3_DCACHE1_REG_Pos
26804 #define GTZC_TZIC1_SR3_DCACHE1_REG_Msk      GTZC_CFGR3_DCACHE1_REG_Msk
26805 #define GTZC_TZIC1_SR3_ADC12_Pos            GTZC_CFGR3_ADC12_Pos
26806 #define GTZC_TZIC1_SR3_ADC12_Msk            GTZC_CFGR3_ADC12_Msk
26807 #define GTZC_TZIC1_SR3_DCMI_Pos             GTZC_CFGR3_DCMI_Pos
26808 #define GTZC_TZIC1_SR3_DCMI_Msk             GTZC_CFGR3_DCMI_Msk
26809 #define GTZC_TZIC1_SR3_OTG_Pos              GTZC_CFGR3_OTG_Pos
26810 #define GTZC_TZIC1_SR3_OTG_Msk              GTZC_CFGR3_OTG_Msk
26811 #define GTZC_TZIC1_SR3_AES_Pos              GTZC_CFGR3_AES_Pos
26812 #define GTZC_TZIC1_SR3_AES_Msk              GTZC_CFGR3_AES_Msk
26813 #define GTZC_TZIC1_SR3_HASH_Pos             GTZC_CFGR3_HASH_Pos
26814 #define GTZC_TZIC1_SR3_HASH_Msk             GTZC_CFGR3_HASH_Msk
26815 #define GTZC_TZIC1_SR3_RNG_Pos              GTZC_CFGR3_RNG_Pos
26816 #define GTZC_TZIC1_SR3_RNG_Msk              GTZC_CFGR3_RNG_Msk
26817 #define GTZC_TZIC1_SR3_PKA_Pos              GTZC_CFGR3_PKA_Pos
26818 #define GTZC_TZIC1_SR3_PKA_Msk              GTZC_CFGR3_PKA_Msk
26819 #define GTZC_TZIC1_SR3_SAES_Pos             GTZC_CFGR3_SAES_Pos
26820 #define GTZC_TZIC1_SR3_SAES_Msk             GTZC_CFGR3_SAES_Msk
26821 #define GTZC_TZIC1_SR3_OCTOSPIM_Pos         GTZC_CFGR3_OCTOSPIM_Pos
26822 #define GTZC_TZIC1_SR3_OCTOSPIM_Msk         GTZC_CFGR3_OCTOSPIM_Msk
26823 #define GTZC_TZIC1_SR3_SDMMC1_Pos           GTZC_CFGR3_SDMMC1_Pos
26824 #define GTZC_TZIC1_SR3_SDMMC1_Msk           GTZC_CFGR3_SDMMC1_Msk
26825 #define GTZC_TZIC1_SR3_SDMMC2_Pos           GTZC_CFGR3_SDMMC2_Pos
26826 #define GTZC_TZIC1_SR3_SDMMC2_Msk           GTZC_CFGR3_SDMMC2_Msk
26827 #define GTZC_TZIC1_SR3_FSMC_REG_Pos         GTZC_CFGR3_FSMC_REG_Pos
26828 #define GTZC_TZIC1_SR3_FSMC_REG_Msk         GTZC_CFGR3_FSMC_REG_Msk
26829 #define GTZC_TZIC1_SR3_OCTOSPI1_REG_Pos     GTZC_CFGR3_OCTOSPI1_REG_Pos
26830 #define GTZC_TZIC1_SR3_OCTOSPI1_REG_Msk     GTZC_CFGR3_OCTOSPI1_REG_Msk
26831 #define GTZC_TZIC1_SR3_OCTOSPI2_REG_Pos     GTZC_CFGR3_OCTOSPI2_REG_Pos
26832 #define GTZC_TZIC1_SR3_OCTOSPI2_REG_Msk     GTZC_CFGR3_OCTOSPI2_REG_Msk
26833 #define GTZC_TZIC1_SR3_RAMCFG_Pos           GTZC_CFGR3_RAMCFG_Pos
26834 #define GTZC_TZIC1_SR3_RAMCFG_Msk           GTZC_CFGR3_RAMCFG_Msk
26835 #define GTZC_TZIC1_SR3_GPU2D_Pos            GTZC_CFGR3_GPU2D_Pos
26836 #define GTZC_TZIC1_SR3_GPU2D_Msk            GTZC_CFGR3_GPU2D_Msk
26837 #define GTZC_TZIC1_SR3_GFXMMU_Pos           GTZC_CFGR3_GFXMMU_Pos
26838 #define GTZC_TZIC1_SR3_GFXMMU_Msk           GTZC_CFGR3_GFXMMU_Msk
26839 #define GTZC_TZIC1_SR3_GFXMMU_REG_Pos       GTZC_CFGR3_GFXMMU_REG_Pos
26840 #define GTZC_TZIC1_SR3_GFXMMU_REG_Msk       GTZC_CFGR3_GFXMMU_REG_Msk
26841 #define GTZC_TZIC1_SR3_HSPI1_REG_Pos        GTZC_CFGR3_HSPI1_REG_Pos
26842 #define GTZC_TZIC1_SR3_HSPI1_REG_Msk        GTZC_CFGR3_HSPI1_REG_Msk
26843 #define GTZC_TZIC1_SR3_DCACHE2_REG_Pos      GTZC_CFGR3_DCACHE2_REG_Pos
26844 #define GTZC_TZIC1_SR3_DCACHE2_REG_Msk      GTZC_CFGR3_DCACHE2_REG_Msk
26845 #define GTZC_TZIC1_SR3_JPEG_Pos             GTZC_CFGR3_JPEG_REG_Pos
26846 #define GTZC_TZIC1_SR3_JPEG_Msk             GTZC_CFGR3_JPEG_REG_Msk
26847 
26848 /*******************  Bits definition for GTZC_TZIC1_SR4 register  ***************/
26849 #define GTZC_TZIC1_SR4_GPDMA1_Pos           GTZC_CFGR4_GPDMA1_Pos
26850 #define GTZC_TZIC1_SR4_GPDMA1_Msk           GTZC_CFGR4_GPDMA1_Msk
26851 #define GTZC_TZIC1_SR4_FLASH_REG_Pos        GTZC_CFGR4_FLASH_REG_Pos
26852 #define GTZC_TZIC1_SR4_FLASH_REG_Msk        GTZC_CFGR4_FLASH_REG_Msk
26853 #define GTZC_TZIC1_SR4_FLASH_Pos            GTZC_CFGR4_FLASH_Pos
26854 #define GTZC_TZIC1_SR4_FLASH_Msk            GTZC_CFGR4_FLASH_Msk
26855 #define GTZC_TZIC1_SR4_OTFDEC1_Pos          GTZC_CFGR4_OTFDEC1_Pos
26856 #define GTZC_TZIC1_SR4_OTFDEC1_Msk          GTZC_CFGR4_OTFDEC1_Msk
26857 #define GTZC_TZIC1_SR4_OTFDEC2_Pos          GTZC_CFGR4_OTFDEC2_Pos
26858 #define GTZC_TZIC1_SR4_OTFDEC2_Msk          GTZC_CFGR4_OTFDEC2_Msk
26859 #define GTZC_TZIC1_SR4_TZSC1_Pos            GTZC_CFGR4_TZSC1_Pos
26860 #define GTZC_TZIC1_SR4_TZSC1_Msk            GTZC_CFGR4_TZSC1_Msk
26861 #define GTZC_TZIC1_SR4_TZIC1_Pos            GTZC_CFGR4_TZIC1_Pos
26862 #define GTZC_TZIC1_SR4_TZIC1_Msk            GTZC_CFGR4_TZIC1_Msk
26863 #define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Pos     GTZC_CFGR4_OCTOSPI1_MEM_Pos
26864 #define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Msk     GTZC_CFGR4_OCTOSPI1_MEM_Msk
26865 #define GTZC_TZIC1_SR4_FSMC_MEM_Pos         GTZC_CFGR4_FSMC_MEM_Pos
26866 #define GTZC_TZIC1_SR4_FSMC_MEM_Msk         GTZC_CFGR4_FSMC_MEM_Msk
26867 #define GTZC_TZIC1_SR4_BKPSRAM_Pos          GTZC_CFGR4_BKPSRAM_Pos
26868 #define GTZC_TZIC1_SR4_BKPSRAM_Msk          GTZC_CFGR4_BKPSRAM_Msk
26869 #define GTZC_TZIC1_SR4_OCTOSPI2_MEM_Pos     GTZC_CFGR4_OCTOSPI2_MEM_Pos
26870 #define GTZC_TZIC1_SR4_OCTOSPI2_MEM_Msk     GTZC_CFGR4_OCTOSPI2_MEM_Msk
26871 #define GTZC_TZIC1_SR4_HSPI1_MEM_Pos        GTZC_CFGR4_HSPI1_MEM_Pos
26872 #define GTZC_TZIC1_SR4_HSPI1_MEM_Msk        GTZC_CFGR4_HSPI1_MEM_Msk
26873 #define GTZC_TZIC1_SR4_SRAM6_Pos            GTZC_CFGR4_SRAM6_Pos
26874 #define GTZC_TZIC1_SR4_SRAM6_Msk            GTZC_CFGR4_SRAM6_Msk
26875 #define GTZC_TZIC1_SR4_MPCBB6_REG_Pos       GTZC_CFGR4_MPCBB6_REG_Pos
26876 #define GTZC_TZIC1_SR4_MPCBB6_REG_Msk       GTZC_CFGR4_MPCBB6_REG_Msk
26877 #define GTZC_TZIC1_SR4_SRAM1_Pos            GTZC_CFGR4_SRAM1_Pos
26878 #define GTZC_TZIC1_SR4_SRAM1_Msk            GTZC_CFGR4_SRAM1_Msk
26879 #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos       GTZC_CFGR4_MPCBB1_REG_Pos
26880 #define GTZC_TZIC1_SR4_MPCBB1_REG_Msk       GTZC_CFGR4_MPCBB1_REG_Msk
26881 #define GTZC_TZIC1_SR4_SRAM2_Pos            GTZC_CFGR4_SRAM2_Pos
26882 #define GTZC_TZIC1_SR4_SRAM2_Msk            GTZC_CFGR4_SRAM2_Msk
26883 #define GTZC_TZIC1_SR4_MPCBB2_REG_Pos       GTZC_CFGR4_MPCBB2_REG_Pos
26884 #define GTZC_TZIC1_SR4_MPCBB2_REG_Msk       GTZC_CFGR4_MPCBB2_REG_Msk
26885 #define GTZC_TZIC1_SR4_SRAM3_Pos            GTZC_CFGR4_SRAM3_Pos
26886 #define GTZC_TZIC1_SR4_SRAM3_Msk            GTZC_CFGR4_SRAM3_Msk
26887 #define GTZC_TZIC1_SR4_MPCBB3_REG_Pos       GTZC_CFGR4_MPCBB3_REG_Pos
26888 #define GTZC_TZIC1_SR4_MPCBB3_REG_Msk       GTZC_CFGR4_MPCBB3_REG_Msk
26889 #define GTZC_TZIC1_SR4_SRAM5_Pos            GTZC_CFGR4_SRAM5_Pos
26890 #define GTZC_TZIC1_SR4_SRAM5_Msk            GTZC_CFGR4_SRAM5_Msk
26891 #define GTZC_TZIC1_SR4_MPCBB5_REG_Pos       GTZC_CFGR4_MPCBB5_REG_Pos
26892 #define GTZC_TZIC1_SR4_MPCBB5_REG_Msk       GTZC_CFGR4_MPCBB5_REG_Msk
26893 
26894 /*******************  Bits definition for GTZC_TZIC2_SR1 register  ***************/
26895 #define GTZC_TZIC2_SR1_SPI3_Pos             GTZC_CFGR1_SPI3_Pos
26896 #define GTZC_TZIC2_SR1_SPI3_Msk             GTZC_CFGR1_SPI3_Msk
26897 #define GTZC_TZIC2_SR1_LPUART1_Pos          GTZC_CFGR1_LPUART1_Pos
26898 #define GTZC_TZIC2_SR1_LPUART1_Msk          GTZC_CFGR1_LPUART1_Msk
26899 #define GTZC_TZIC2_SR1_I2C3_Pos             GTZC_CFGR1_I2C3_Pos
26900 #define GTZC_TZIC2_SR1_I2C3_Msk             GTZC_CFGR1_I2C3_Msk
26901 #define GTZC_TZIC2_SR1_LPTIM1_Pos           GTZC_CFGR1_LPTIM1_Pos
26902 #define GTZC_TZIC2_SR1_LPTIM1_Msk           GTZC_CFGR1_LPTIM1_Msk
26903 #define GTZC_TZIC2_SR1_LPTIM3_Pos           GTZC_CFGR1_LPTIM3_Pos
26904 #define GTZC_TZIC2_SR1_LPTIM3_Msk           GTZC_CFGR1_LPTIM3_Msk
26905 #define GTZC_TZIC2_SR1_LPTIM4_Pos           GTZC_CFGR1_LPTIM4_Pos
26906 #define GTZC_TZIC2_SR1_LPTIM4_Msk           GTZC_CFGR1_LPTIM4_Msk
26907 #define GTZC_TZIC2_SR1_OPAMP_Pos            GTZC_CFGR1_OPAMP_Pos
26908 #define GTZC_TZIC2_SR1_OPAMP_Msk            GTZC_CFGR1_OPAMP_Msk
26909 #define GTZC_TZIC2_SR1_COMP_Pos             GTZC_CFGR1_COMP_Pos
26910 #define GTZC_TZIC2_SR1_COMP_Msk             GTZC_CFGR1_COMP_Msk
26911 #define GTZC_TZIC2_SR1_ADC4_Pos             GTZC_CFGR1_ADC4_Pos
26912 #define GTZC_TZIC2_SR1_ADC4_Msk             GTZC_CFGR1_ADC4_Msk
26913 #define GTZC_TZIC2_SR1_VREFBUF_Pos          GTZC_CFGR1_VREFBUF_Pos
26914 #define GTZC_TZIC2_SR1_VREFBUF_Msk          GTZC_CFGR1_VREFBUF_Msk
26915 #define GTZC_TZIC2_SR1_DAC1_Pos             GTZC_CFGR1_DAC1_Pos
26916 #define GTZC_TZIC2_SR1_DAC1_Msk             GTZC_CFGR1_DAC1_Msk
26917 #define GTZC_TZIC2_SR1_ADF1_Pos             GTZC_CFGR1_ADF1_Pos
26918 #define GTZC_TZIC2_SR1_ADF1_Msk             GTZC_CFGR1_ADF1_Msk
26919 
26920 /*******************  Bits definition for GTZC_TZIC2_SR2 register  ***************/
26921 #define GTZC_TZIC2_SR2_SYSCFG_Pos           GTZC_CFGR2_SYSCFG_Pos
26922 #define GTZC_TZIC2_SR2_SYSCFG_Msk           GTZC_CFGR2_SYSCFG_Msk
26923 #define GTZC_TZIC2_SR2_RTC_Pos              GTZC_CFGR2_RTC_Pos
26924 #define GTZC_TZIC2_SR2_RTC_Msk              GTZC_CFGR2_RTC_Msk
26925 #define GTZC_TZIC2_SR2_TAMP_Pos             GTZC_CFGR2_TAMP_Pos
26926 #define GTZC_TZIC2_SR2_TAMP_Msk             GTZC_CFGR2_TAMP_Msk
26927 #define GTZC_TZIC2_SR2_PWR_Pos              GTZC_CFGR2_PWR_Pos
26928 #define GTZC_TZIC2_SR2_PWR_Msk              GTZC_CFGR2_PWR_Msk
26929 #define GTZC_TZIC2_SR2_RCC_Pos              GTZC_CFGR2_RCC_Pos
26930 #define GTZC_TZIC2_SR2_RCC_Msk              GTZC_CFGR2_RCC_Msk
26931 #define GTZC_TZIC2_SR2_LPDMA1_Pos           GTZC_CFGR2_LPDMA1_Pos
26932 #define GTZC_TZIC2_SR2_LPDMA1_Msk           GTZC_CFGR2_LPDMA1_Msk
26933 #define GTZC_TZIC2_SR2_EXTI_Pos             GTZC_CFGR2_EXTI_Pos
26934 #define GTZC_TZIC2_SR2_EXTI_Msk             GTZC_CFGR2_EXTI_Msk
26935 #define GTZC_TZIC2_SR2_TZSC2_Pos            GTZC_CFGR2_TZSC2_Pos
26936 #define GTZC_TZIC2_SR2_TZSC2_Msk            GTZC_CFGR2_TZSC2_Msk
26937 #define GTZC_TZIC2_SR2_TZIC2_Pos            GTZC_CFGR2_TZIC2_Pos
26938 #define GTZC_TZIC2_SR2_TZIC2_Msk            GTZC_CFGR2_TZIC2_Msk
26939 #define GTZC_TZIC2_SR2_SRAM4_Pos            GTZC_CFGR2_SRAM4_Pos
26940 #define GTZC_TZIC2_SR2_SRAM4_Msk            GTZC_CFGR2_SRAM4_Msk
26941 #define GTZC_TZIC2_SR2_MPCBB4_REG_Pos       GTZC_CFGR2_MPCBB4_REG_Pos
26942 #define GTZC_TZIC2_SR2_MPCBB4_REG_Msk       GTZC_CFGR2_MPCBB4_REG_Msk
26943 
26944 /******************  Bits definition for GTZC_TZIC1_FCR1 register  ****************/
26945 #define GTZC_TZIC1_FCR1_TIM2_Pos            GTZC_CFGR1_TIM2_Pos
26946 #define GTZC_TZIC1_FCR1_TIM2_Msk            GTZC_CFGR1_TIM2_Msk
26947 #define GTZC_TZIC1_FCR1_TIM3_Pos            GTZC_CFGR1_TIM3_Pos
26948 #define GTZC_TZIC1_FCR1_TIM3_Msk            GTZC_CFGR1_TIM3_Msk
26949 #define GTZC_TZIC1_FCR1_TIM4_Pos            GTZC_CFGR1_TIM4_Pos
26950 #define GTZC_TZIC1_FCR1_TIM4_Msk            GTZC_CFGR1_TIM4_Msk
26951 #define GTZC_TZIC1_FCR1_TIM5_Pos            GTZC_CFGR1_TIM5_Pos
26952 #define GTZC_TZIC1_FCR1_TIM5_Msk            GTZC_CFGR1_TIM5_Msk
26953 #define GTZC_TZIC1_FCR1_TIM6_Pos            GTZC_CFGR1_TIM6_Pos
26954 #define GTZC_TZIC1_FCR1_TIM6_Msk            GTZC_CFGR1_TIM6_Msk
26955 #define GTZC_TZIC1_FCR1_TIM7_Pos            GTZC_CFGR1_TIM7_Pos
26956 #define GTZC_TZIC1_FCR1_TIM7_Msk            GTZC_CFGR1_TIM7_Msk
26957 #define GTZC_TZIC1_FCR1_WWDG_Pos            GTZC_CFGR1_WWDG_Pos
26958 #define GTZC_TZIC1_FCR1_WWDG_Msk            GTZC_CFGR1_WWDG_Msk
26959 #define GTZC_TZIC1_FCR1_IWDG_Pos            GTZC_CFGR1_IWDG_Pos
26960 #define GTZC_TZIC1_FCR1_IWDG_Msk            GTZC_CFGR1_IWDG_Msk
26961 #define GTZC_TZIC1_FCR1_SPI2_Pos            GTZC_CFGR1_SPI2_Pos
26962 #define GTZC_TZIC1_FCR1_SPI2_Msk            GTZC_CFGR1_SPI2_Msk
26963 #define GTZC_TZIC1_FCR1_USART2_Pos          GTZC_CFGR1_USART2_Pos
26964 #define GTZC_TZIC1_FCR1_USART2_Msk          GTZC_CFGR1_USART2_Msk
26965 #define GTZC_TZIC1_FCR1_USART3_Pos          GTZC_CFGR1_USART3_Pos
26966 #define GTZC_TZIC1_FCR1_USART3_Msk          GTZC_CFGR1_USART3_Msk
26967 #define GTZC_TZIC1_FCR1_UART4_Pos           GTZC_CFGR1_UART4_Pos
26968 #define GTZC_TZIC1_FCR1_UART4_Msk           GTZC_CFGR1_UART4_Msk
26969 #define GTZC_TZIC1_FCR1_UART5_Pos           GTZC_CFGR1_UART5_Pos
26970 #define GTZC_TZIC1_FCR1_UART5_Msk           GTZC_CFGR1_UART5_Msk
26971 #define GTZC_TZIC1_FCR1_I2C1_Pos            GTZC_CFGR1_I2C1_Pos
26972 #define GTZC_TZIC1_FCR1_I2C1_Msk            GTZC_CFGR1_I2C1_Msk
26973 #define GTZC_TZIC1_FCR1_I2C2_Pos            GTZC_CFGR1_I2C2_Pos
26974 #define GTZC_TZIC1_FCR1_I2C2_Msk            GTZC_CFGR1_I2C2_Msk
26975 #define GTZC_TZIC1_FCR1_CRS_Pos             GTZC_CFGR1_CRS_Pos
26976 #define GTZC_TZIC1_FCR1_CRS_Msk             GTZC_CFGR1_CRS_Msk
26977 #define GTZC_TZIC1_FCR1_I2C4_Pos            GTZC_CFGR1_I2C4_Pos
26978 #define GTZC_TZIC1_FCR1_I2C4_Msk            GTZC_CFGR1_I2C4_Msk
26979 #define GTZC_TZIC1_FCR1_LPTIM2_Pos          GTZC_CFGR1_LPTIM2_Pos
26980 #define GTZC_TZIC1_FCR1_LPTIM2_Msk          GTZC_CFGR1_LPTIM2_Msk
26981 #define GTZC_TZIC1_FCR1_FDCAN1_Pos          GTZC_CFGR1_FDCAN1_Pos
26982 #define GTZC_TZIC1_FCR1_FDCAN1_Msk          GTZC_CFGR1_FDCAN1_Msk
26983 #define GTZC_TZIC1_FCR1_UCPD1_Pos           GTZC_CFGR1_UCPD1_Pos
26984 #define GTZC_TZIC1_FCR1_UCPD1_Msk           GTZC_CFGR1_UCPD1_Msk
26985 #define GTZC_TZIC1_FCR1_USART6_Pos          GTZC_CFGR1_USART6_Pos
26986 #define GTZC_TZIC1_FCR1_USART6_Msk          GTZC_CFGR1_USART6_Msk
26987 #define GTZC_TZIC1_FCR1_I2C5_Pos            GTZC_CFGR1_I2C5_Pos
26988 #define GTZC_TZIC1_FCR1_I2C5_Msk            GTZC_CFGR1_I2C5_Msk
26989 #define GTZC_TZIC1_FCR1_I2C6_Pos            GTZC_CFGR1_I2C6_Pos
26990 #define GTZC_TZIC1_FCR1_I2C6_Msk            GTZC_CFGR1_I2C6_Msk
26991 
26992 /*******************  Bits definition for GTZC_TZIC1_FCR2 register  **************/
26993 #define GTZC_TZIC1_FCR2_TIM1_Pos            GTZC_CFGR2_TIM1_Pos
26994 #define GTZC_TZIC1_FCR2_TIM1_Msk            GTZC_CFGR2_TIM1_Msk
26995 #define GTZC_TZIC1_FCR2_SPI1_Pos            GTZC_CFGR2_SPI1_Pos
26996 #define GTZC_TZIC1_FCR2_SPI1_Msk            GTZC_CFGR2_SPI1_Msk
26997 #define GTZC_TZIC1_FCR2_TIM8_Pos            GTZC_CFGR2_TIM8_Pos
26998 #define GTZC_TZIC1_FCR2_TIM8_Msk            GTZC_CFGR2_TIM8_Msk
26999 #define GTZC_TZIC1_FCR2_USART1_Pos          GTZC_CFGR2_USART1_Pos
27000 #define GTZC_TZIC1_FCR2_USART1_Msk          GTZC_CFGR2_USART1_Msk
27001 #define GTZC_TZIC1_FCR2_TIM15_Pos           GTZC_CFGR2_TIM15_Pos
27002 #define GTZC_TZIC1_FCR2_TIM15_Msk           GTZC_CFGR2_TIM15_Msk
27003 #define GTZC_TZIC1_FCR2_TIM16_Pos           GTZC_CFGR2_TIM16_Pos
27004 #define GTZC_TZIC1_FCR2_TIM16_Msk           GTZC_CFGR2_TIM16_Msk
27005 #define GTZC_TZIC1_FCR2_TIM17_Pos           GTZC_CFGR2_TIM17_Pos
27006 #define GTZC_TZIC1_FCR2_TIM17_Msk           GTZC_CFGR2_TIM17_Msk
27007 #define GTZC_TZIC1_FCR2_SAI1_Pos            GTZC_CFGR2_SAI1_Pos
27008 #define GTZC_TZIC1_FCR2_SAI1_Msk            GTZC_CFGR2_SAI1_Msk
27009 #define GTZC_TZIC1_FCR2_SAI2_Pos            GTZC_CFGR2_SAI2_Pos
27010 #define GTZC_TZIC1_FCR2_SAI2_Msk            GTZC_CFGR2_SAI2_Msk
27011 #define GTZC_TZIC1_FCR2_LTDCUSB_Pos         GTZC_CFGR2_LTDCUSB_Pos
27012 #define GTZC_TZIC1_FCR2_LTDCUSB_Msk         GTZC_CFGR2_LTDCUSB_Msk
27013 #define GTZC_TZIC1_FCR2_DSI_Pos             GTZC_CFGR2_DSI_Pos
27014 #define GTZC_TZIC1_FCR2_DSI_Msk             GTZC_CFGR2_DSI_Msk
27015 #define GTZC_TZIC1_FCR2_GFXTIM_Pos          GTZC_CFGR2_GFXTIM_Pos
27016 #define GTZC_TZIC1_FCR2_GFXTIM_Msk          GTZC_CFGR2_GFXTIM_Msk
27017 
27018 /******************  Bits definition for GTZC_TZIC1_FCR3 register  ****************/
27019 #define GTZC_TZIC1_FCR3_MDF1_Pos            GTZC_CFGR3_MDF1_Pos
27020 #define GTZC_TZIC1_FCR3_MDF1_Msk            GTZC_CFGR3_MDF1_Msk
27021 #define GTZC_TZIC1_FCR3_CORDIC_Pos          GTZC_CFGR3_CORDIC_Pos
27022 #define GTZC_TZIC1_FCR3_CORDIC_Msk          GTZC_CFGR3_CORDIC_Msk
27023 #define GTZC_TZIC1_FCR3_FMAC_Pos            GTZC_CFGR3_FMAC_Pos
27024 #define GTZC_TZIC1_FCR3_FMAC_Msk            GTZC_CFGR3_FMAC_Msk
27025 #define GTZC_TZIC1_FCR3_CRC_Pos             GTZC_CFGR3_CRC_Pos
27026 #define GTZC_TZIC1_FCR3_CRC_Msk             GTZC_CFGR3_CRC_Msk
27027 #define GTZC_TZIC1_FCR3_TSC_Pos             GTZC_CFGR3_TSC_Pos
27028 #define GTZC_TZIC1_FCR3_TSC_Msk             GTZC_CFGR3_TSC_Msk
27029 #define GTZC_TZIC1_FCR3_DMA2D_Pos           GTZC_CFGR3_DMA2D_Pos
27030 #define GTZC_TZIC1_FCR3_DMA2D_Msk           GTZC_CFGR3_DMA2D_Msk
27031 #define GTZC_TZIC1_FCR3_ICACHE_REG_Pos      GTZC_CFGR3_ICACHE_REG_Pos
27032 #define GTZC_TZIC1_FCR3_ICACHE_REG_Msk      GTZC_CFGR3_ICACHE_REG_Msk
27033 #define GTZC_TZIC1_FCR3_DCACHE1_REG_Pos     GTZC_CFGR3_DCACHE1_REG_Pos
27034 #define GTZC_TZIC1_FCR3_DCACHE1_REG_Msk     GTZC_CFGR3_DCACHE1_REG_Msk
27035 #define GTZC_TZIC1_FCR3_ADC12_Pos           GTZC_CFGR3_ADC12_Pos
27036 #define GTZC_TZIC1_FCR3_ADC12_Msk           GTZC_CFGR3_ADC12_Msk
27037 #define GTZC_TZIC1_FCR3_DCMI_Pos            GTZC_CFGR3_DCMI_Pos
27038 #define GTZC_TZIC1_FCR3_DCMI_Msk            GTZC_CFGR3_DCMI_Msk
27039 #define GTZC_TZIC1_FCR3_OTG_Pos             GTZC_CFGR3_OTG_Pos
27040 #define GTZC_TZIC1_FCR3_OTG_Msk             GTZC_CFGR3_OTG_Msk
27041 #define GTZC_TZIC1_FCR3_AES_Pos             GTZC_CFGR3_AES_Pos
27042 #define GTZC_TZIC1_FCR3_AES_Msk             GTZC_CFGR3_AES_Msk
27043 #define GTZC_TZIC1_FCR3_HASH_Pos            GTZC_CFGR3_HASH_Pos
27044 #define GTZC_TZIC1_FCR3_HASH_Msk            GTZC_CFGR3_HASH_Msk
27045 #define GTZC_TZIC1_FCR3_RNG_Pos             GTZC_CFGR3_RNG_Pos
27046 #define GTZC_TZIC1_FCR3_RNG_Msk             GTZC_CFGR3_RNG_Msk
27047 #define GTZC_TZIC1_FCR3_PKA_Pos             GTZC_CFGR3_PKA_Pos
27048 #define GTZC_TZIC1_FCR3_PKA_Msk             GTZC_CFGR3_PKA_Msk
27049 #define GTZC_TZIC1_FCR3_SAES_Pos            GTZC_CFGR3_SAES_Pos
27050 #define GTZC_TZIC1_FCR3_SAES_Msk            GTZC_CFGR3_SAES_Msk
27051 #define GTZC_TZIC1_FCR3_OCTOSPIM_Pos        GTZC_CFGR3_OCTOSPIM_Pos
27052 #define GTZC_TZIC1_FCR3_OCTOSPIM_Msk        GTZC_CFGR3_OCTOSPIM_Msk
27053 #define GTZC_TZIC1_FCR3_SDMMC1_Pos          GTZC_CFGR3_SDMMC1_Pos
27054 #define GTZC_TZIC1_FCR3_SDMMC1_Msk          GTZC_CFGR3_SDMMC1_Msk
27055 #define GTZC_TZIC1_FCR3_SDMMC2_Pos          GTZC_CFGR3_SDMMC2_Pos
27056 #define GTZC_TZIC1_FCR3_SDMMC2_Msk          GTZC_CFGR3_SDMMC2_Msk
27057 #define GTZC_TZIC1_FCR3_FSMC_REG_Pos        GTZC_CFGR3_FSMC_REG_Pos
27058 #define GTZC_TZIC1_FCR3_FSMC_REG_Msk        GTZC_CFGR3_FSMC_REG_Msk
27059 #define GTZC_TZIC1_FCR3_OCTOSPI1_REG_Pos    GTZC_CFGR3_OCTOSPI1_REG_Pos
27060 #define GTZC_TZIC1_FCR3_OCTOSPI1_REG_Msk    GTZC_CFGR3_OCTOSPI1_REG_Msk
27061 #define GTZC_TZIC1_FCR3_OCTOSPI2_REG_Pos    GTZC_CFGR3_OCTOSPI2_REG_Pos
27062 #define GTZC_TZIC1_FCR3_OCTOSPI2_REG_Msk    GTZC_CFGR3_OCTOSPI2_REG_Msk
27063 #define GTZC_TZIC1_FCR3_RAMCFG_Pos          GTZC_CFGR3_RAMCFG_Pos
27064 #define GTZC_TZIC1_FCR3_RAMCFG_Msk          GTZC_CFGR3_RAMCFG_Msk
27065 #define GTZC_TZIC1_FCR3_GPU2D_Pos           GTZC_CFGR3_GPU2D_Pos
27066 #define GTZC_TZIC1_FCR3_GPU2D_Msk           GTZC_CFGR3_GPU2D_Msk
27067 #define GTZC_TZIC1_FCR3_GFXMMU_Pos          GTZC_CFGR3_GFXMMU_Pos
27068 #define GTZC_TZIC1_FCR3_GFXMMU_Msk          GTZC_CFGR3_GFXMMU_Msk
27069 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Pos      GTZC_CFGR3_GFXMMU_REG_Pos
27070 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Msk      GTZC_CFGR3_GFXMMU_REG_Msk
27071 #define GTZC_TZIC1_FCR3_HSPI1_REG_Pos       GTZC_CFGR3_HSPI1_REG_Pos
27072 #define GTZC_TZIC1_FCR3_HSPI1_REG_Msk       GTZC_CFGR3_HSPI1_REG_Msk
27073 #define GTZC_TZIC1_FCR3_DCACHE2_REG_Pos     GTZC_CFGR3_DCACHE2_REG_Pos
27074 #define GTZC_TZIC1_FCR3_DCACHE2_REG_Msk     GTZC_CFGR3_DCACHE2_REG_Msk
27075 #define GTZC_TZIC1_FCR3_JPEG_Pos            GTZC_CFGR3_JPEG_REG_Pos
27076 #define GTZC_TZIC1_FCR3_JPEG_Msk            GTZC_CFGR3_JPEG_REG_Msk
27077 
27078 /*******************  Bits definition for GTZC_TZIC1_FCR4 register  ***************/
27079 #define GTZC_TZIC1_FCR4_GPDMA1_Pos          GTZC_CFGR4_GPDMA1_Pos
27080 #define GTZC_TZIC1_FCR4_GPDMA1_Msk          GTZC_CFGR4_GPDMA1_Msk
27081 #define GTZC_TZIC1_FCR4_FLASH_REG_Pos       GTZC_CFGR4_FLASH_REG_Pos
27082 #define GTZC_TZIC1_FCR4_FLASH_REG_Msk       GTZC_CFGR4_FLASH_REG_Msk
27083 #define GTZC_TZIC1_FCR4_FLASH_Pos           GTZC_CFGR4_FLASH_Pos
27084 #define GTZC_TZIC1_FCR4_FLASH_Msk           GTZC_CFGR4_FLASH_Msk
27085 #define GTZC_TZIC1_FCR4_OTFDEC1_Pos         GTZC_CFGR4_OTFDEC1_Pos
27086 #define GTZC_TZIC1_FCR4_OTFDEC1_Msk         GTZC_CFGR4_OTFDEC1_Msk
27087 #define GTZC_TZIC1_FCR4_OTFDEC2_Pos         GTZC_CFGR4_OTFDEC2_Pos
27088 #define GTZC_TZIC1_FCR4_OTFDEC2_Msk         GTZC_CFGR4_OTFDEC2_Msk
27089 #define GTZC_TZIC1_FCR4_TZSC1_Pos           GTZC_CFGR4_TZSC1_Pos
27090 #define GTZC_TZIC1_FCR4_TZSC1_Msk           GTZC_CFGR4_TZSC1_Msk
27091 #define GTZC_TZIC1_FCR4_TZIC1_Pos           GTZC_CFGR4_TZIC1_Pos
27092 #define GTZC_TZIC1_FCR4_TZIC1_Msk           GTZC_CFGR4_TZIC1_Msk
27093 #define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Pos    GTZC_CFGR4_OCTOSPI1_MEM_Pos
27094 #define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Msk    GTZC_CFGR4_OCTOSPI1_MEM_Msk
27095 #define GTZC_TZIC1_FCR4_FSMC_MEM_Pos        GTZC_CFGR4_FSMC_MEM_Pos
27096 #define GTZC_TZIC1_FCR4_FSMC_MEM_Msk        GTZC_CFGR4_FSMC_MEM_Msk
27097 #define GTZC_TZIC1_FCR4_BKPSRAM_Pos         GTZC_CFGR4_BKPSRAM_Pos
27098 #define GTZC_TZIC1_FCR4_BKPSRAM_Msk         GTZC_CFGR4_BKPSRAM_Msk
27099 #define GTZC_TZIC1_FCR4_OCTOSPI2_MEM_Pos    GTZC_CFGR4_OCTOSPI2_MEM_Pos
27100 #define GTZC_TZIC1_FCR4_OCTOSPI2_MEM_Msk    GTZC_CFGR4_OCTOSPI2_MEM_Msk
27101 #define GTZC_TZIC1_FCR4_HSPI1_MEM_Pos       GTZC_CFGR4_HSPI1_MEM_Pos
27102 #define GTZC_TZIC1_FCR4_HSPI1_MEM_Msk       GTZC_CFGR4_HSPI1_MEM_Msk
27103 #define GTZC_TZIC1_FCR4_SRAM6_Pos           GTZC_CFGR4_SRAM6_Pos
27104 #define GTZC_TZIC1_FCR4_SRAM6_Msk           GTZC_CFGR4_SRAM6_Msk
27105 #define GTZC_TZIC1_FCR4_MPCBB6_REG_Pos      GTZC_CFGR4_MPCBB6_REG_Pos
27106 #define GTZC_TZIC1_FCR4_MPCBB6_REG_Msk      GTZC_CFGR4_MPCBB6_REG_Msk
27107 #define GTZC_TZIC1_FCR4_SRAM1_Pos           GTZC_CFGR4_SRAM1_Pos
27108 #define GTZC_TZIC1_FCR4_SRAM1_Msk           GTZC_CFGR4_SRAM1_Msk
27109 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos      GTZC_CFGR4_MPCBB1_REG_Pos
27110 #define GTZC_TZIC1_FCR4_MPCBB1_REG_Msk      GTZC_CFGR4_MPCBB1_REG_Msk
27111 #define GTZC_TZIC1_FCR4_SRAM2_Pos           GTZC_CFGR4_SRAM2_Pos
27112 #define GTZC_TZIC1_FCR4_SRAM2_Msk           GTZC_CFGR4_SRAM2_Msk
27113 #define GTZC_TZIC1_FCR4_MPCBB2_REG_Pos      GTZC_CFGR4_MPCBB2_REG_Pos
27114 #define GTZC_TZIC1_FCR4_MPCBB2_REG_Msk      GTZC_CFGR4_MPCBB2_REG_Msk
27115 #define GTZC_TZIC1_FCR4_SRAM3_Pos           GTZC_CFGR4_SRAM3_Pos
27116 #define GTZC_TZIC1_FCR4_SRAM3_Msk           GTZC_CFGR4_SRAM3_Msk
27117 #define GTZC_TZIC1_FCR4_MPCBB3_REG_Pos      GTZC_CFGR4_MPCBB3_REG_Pos
27118 #define GTZC_TZIC1_FCR4_MPCBB3_REG_Msk      GTZC_CFGR4_MPCBB3_REG_Msk
27119 #define GTZC_TZIC1_FCR4_SRAM5_Pos           GTZC_CFGR4_SRAM5_Pos
27120 #define GTZC_TZIC1_FCR4_SRAM5_Msk           GTZC_CFGR4_SRAM5_Msk
27121 #define GTZC_TZIC1_FCR4_MPCBB5_REG_Pos      GTZC_CFGR4_MPCBB5_REG_Pos
27122 #define GTZC_TZIC1_FCR4_MPCBB5_REG_Msk      GTZC_CFGR4_MPCBB5_REG_Msk
27123 
27124 /*******************  Bits definition for GTZC_TZIC2_FCR1 register  ***************/
27125 #define GTZC_TZIC2_FCR1_SPI3_Pos            GTZC_CFGR1_SPI3_Pos
27126 #define GTZC_TZIC2_FCR1_SPI3_Msk            GTZC_CFGR1_SPI3_Msk
27127 #define GTZC_TZIC2_FCR1_LPUART1_Pos         GTZC_CFGR1_LPUART1_Pos
27128 #define GTZC_TZIC2_FCR1_LPUART1_Msk         GTZC_CFGR1_LPUART1_Msk
27129 #define GTZC_TZIC2_FCR1_I2C3_Pos            GTZC_CFGR1_I2C3_Pos
27130 #define GTZC_TZIC2_FCR1_I2C3_Msk            GTZC_CFGR1_I2C3_Msk
27131 #define GTZC_TZIC2_FCR1_LPTIM1_Pos          GTZC_CFGR1_LPTIM1_Pos
27132 #define GTZC_TZIC2_FCR1_LPTIM1_Msk          GTZC_CFGR1_LPTIM1_Msk
27133 #define GTZC_TZIC2_FCR1_LPTIM3_Pos          GTZC_CFGR1_LPTIM3_Pos
27134 #define GTZC_TZIC2_FCR1_LPTIM3_Msk          GTZC_CFGR1_LPTIM3_Msk
27135 #define GTZC_TZIC2_FCR1_LPTIM4_Pos          GTZC_CFGR1_LPTIM4_Pos
27136 #define GTZC_TZIC2_FCR1_LPTIM4_Msk          GTZC_CFGR1_LPTIM4_Msk
27137 #define GTZC_TZIC2_FCR1_OPAMP_Pos           GTZC_CFGR1_OPAMP_Pos
27138 #define GTZC_TZIC2_FCR1_OPAMP_Msk           GTZC_CFGR1_OPAMP_Msk
27139 #define GTZC_TZIC2_FCR1_COMP_Pos            GTZC_CFGR1_COMP_Pos
27140 #define GTZC_TZIC2_FCR1_COMP_Msk            GTZC_CFGR1_COMP_Msk
27141 #define GTZC_TZIC2_FCR1_ADC4_Pos            GTZC_CFGR1_ADC4_Pos
27142 #define GTZC_TZIC2_FCR1_ADC4_Msk            GTZC_CFGR1_ADC4_Msk
27143 #define GTZC_TZIC2_FCR1_VREFBUF_Pos         GTZC_CFGR1_VREFBUF_Pos
27144 #define GTZC_TZIC2_FCR1_VREFBUF_Msk         GTZC_CFGR1_VREFBUF_Msk
27145 #define GTZC_TZIC2_FCR1_DAC1_Pos            GTZC_CFGR1_DAC1_Pos
27146 #define GTZC_TZIC2_FCR1_DAC1_Msk            GTZC_CFGR1_DAC1_Msk
27147 #define GTZC_TZIC2_FCR1_ADF1_Pos            GTZC_CFGR1_ADF1_Pos
27148 #define GTZC_TZIC2_FCR1_ADF1_Msk            GTZC_CFGR1_ADF1_Msk
27149 
27150 /*******************  Bits definition for GTZC_TZIC2_FCR2 register  ***************/
27151 #define GTZC_TZIC2_FCR2_SYSCFG_Pos          GTZC_CFGR2_SYSCFG_Pos
27152 #define GTZC_TZIC2_FCR2_SYSCFG_Msk          GTZC_CFGR2_SYSCFG_Msk
27153 #define GTZC_TZIC2_FCR2_RTC_Pos             GTZC_CFGR2_RTC_Pos
27154 #define GTZC_TZIC2_FCR2_RTC_Msk             GTZC_CFGR2_RTC_Msk
27155 #define GTZC_TZIC2_FCR2_TAMP_Pos            GTZC_CFGR2_TAMP_Pos
27156 #define GTZC_TZIC2_FCR2_TAMP_Msk            GTZC_CFGR2_TAMP_Msk
27157 #define GTZC_TZIC2_FCR2_PWR_Pos             GTZC_CFGR2_PWR_Pos
27158 #define GTZC_TZIC2_FCR2_PWR_Msk             GTZC_CFGR2_PWR_Msk
27159 #define GTZC_TZIC2_FCR2_RCC_Pos             GTZC_CFGR2_RCC_Pos
27160 #define GTZC_TZIC2_FCR2_RCC_Msk             GTZC_CFGR2_RCC_Msk
27161 #define GTZC_TZIC2_FCR2_LPDMA1_Pos          GTZC_CFGR2_LPDMA1_Pos
27162 #define GTZC_TZIC2_FCR2_LPDMA1_Msk          GTZC_CFGR2_LPDMA1_Msk
27163 #define GTZC_TZIC2_FCR2_EXTI_Pos            GTZC_CFGR2_EXTI_Pos
27164 #define GTZC_TZIC2_FCR2_EXTI_Msk            GTZC_CFGR2_EXTI_Msk
27165 #define GTZC_TZIC2_FCR2_TZSC2_Pos           GTZC_CFGR2_TZSC2_Pos
27166 #define GTZC_TZIC2_FCR2_TZSC2_Msk           GTZC_CFGR2_TZSC2_Msk
27167 #define GTZC_TZIC2_FCR2_TZIC2_Pos           GTZC_CFGR2_TZIC2_Pos
27168 #define GTZC_TZIC2_FCR2_TZIC2_Msk           GTZC_CFGR2_TZIC2_Msk
27169 #define GTZC_TZIC2_FCR2_SRAM4_Pos           GTZC_CFGR2_SRAM4_Pos
27170 #define GTZC_TZIC2_FCR2_SRAM4_Msk           GTZC_CFGR2_SRAM4_Msk
27171 #define GTZC_TZIC2_FCR2_MPCBB4_REG_Pos      GTZC_CFGR2_MPCBB4_REG_Pos
27172 #define GTZC_TZIC2_FCR2_MPCBB4_REG_Msk      GTZC_CFGR2_MPCBB4_REG_Msk
27173 
27174 /*******************  Bits definition for GTZC_MPCBB_CR register  *****************/
27175 #define GTZC_MPCBB_CR_GLOCK_Pos             (0U)
27176 #define GTZC_MPCBB_CR_GLOCK_Msk             (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos)       /*!< 0x00000001 */
27177 #define GTZC_MPCBB_CR_INVSECSTATE_Pos       (30U)
27178 #define GTZC_MPCBB_CR_INVSECSTATE_Msk       (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */
27179 #define GTZC_MPCBB_CR_SRWILADIS_Pos         (31U)
27180 #define GTZC_MPCBB_CR_SRWILADIS_Msk         (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */
27181 
27182 /*******************  Bits definition for GTZC_MPCBB_CFGLOCKR1 register  ************/
27183 #define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos      (0U)
27184 #define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */
27185 #define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos      (1U)
27186 #define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */
27187 #define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos      (2U)
27188 #define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */
27189 #define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos      (3U)
27190 #define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */
27191 #define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos      (4U)
27192 #define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */
27193 #define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos      (5U)
27194 #define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */
27195 #define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos      (6U)
27196 #define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */
27197 #define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos      (7U)
27198 #define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */
27199 #define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos      (8U)
27200 #define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */
27201 #define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos      (9U)
27202 #define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */
27203 #define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos     (10U)
27204 #define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */
27205 #define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos     (11U)
27206 #define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */
27207 #define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos     (12U)
27208 #define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */
27209 #define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos     (13U)
27210 #define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */
27211 #define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos     (14U)
27212 #define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */
27213 #define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos     (15U)
27214 #define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */
27215 #define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos     (16U)
27216 #define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */
27217 #define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos     (17U)
27218 #define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */
27219 #define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos     (18U)
27220 #define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */
27221 #define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos     (19U)
27222 #define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */
27223 #define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos     (20U)
27224 #define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */
27225 #define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos     (21U)
27226 #define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */
27227 #define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos     (22U)
27228 #define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */
27229 #define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos     (23U)
27230 #define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */
27231 #define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos     (24U)
27232 #define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */
27233 #define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos     (25U)
27234 #define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */
27235 #define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos     (26U)
27236 #define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */
27237 #define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos     (27U)
27238 #define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */
27239 #define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos     (28U)
27240 #define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */
27241 #define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos     (29U)
27242 #define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */
27243 #define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos     (30U)
27244 #define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */
27245 #define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos     (31U)
27246 #define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */
27247 
27248 /*******************  Bits definition for GTZC_MPCBB_CFGLOCKR2 register  ************/
27249 #define GTZC_MPCBB_CFGLOCKR2_SPLCK32_Pos     (0U)
27250 #define GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK32_Pos) /*!< 0x00000001 */
27251 #define GTZC_MPCBB_CFGLOCKR2_SPLCK33_Pos     (1U)
27252 #define GTZC_MPCBB_CFGLOCKR2_SPLCK33_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK33_Pos) /*!< 0x00000002 */
27253 #define GTZC_MPCBB_CFGLOCKR2_SPLCK34_Pos     (2U)
27254 #define GTZC_MPCBB_CFGLOCKR2_SPLCK34_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK34_Pos) /*!< 0x00000004 */
27255 #define GTZC_MPCBB_CFGLOCKR2_SPLCK35_Pos     (3U)
27256 #define GTZC_MPCBB_CFGLOCKR2_SPLCK35_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK35_Pos) /*!< 0x00000008 */
27257 #define GTZC_MPCBB_CFGLOCKR2_SPLCK36_Pos     (4U)
27258 #define GTZC_MPCBB_CFGLOCKR2_SPLCK36_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK36_Pos) /*!< 0x00000010 */
27259 #define GTZC_MPCBB_CFGLOCKR2_SPLCK37_Pos     (5U)
27260 #define GTZC_MPCBB_CFGLOCKR2_SPLCK37_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK37_Pos) /*!< 0x00000020 */
27261 #define GTZC_MPCBB_CFGLOCKR2_SPLCK38_Pos     (6U)
27262 #define GTZC_MPCBB_CFGLOCKR2_SPLCK38_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK38_Pos) /*!< 0x00000040 */
27263 #define GTZC_MPCBB_CFGLOCKR2_SPLCK39_Pos     (7U)
27264 #define GTZC_MPCBB_CFGLOCKR2_SPLCK39_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK39_Pos) /*!< 0x00000080 */
27265 #define GTZC_MPCBB_CFGLOCKR2_SPLCK40_Pos     (8U)
27266 #define GTZC_MPCBB_CFGLOCKR2_SPLCK40_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK40_Pos) /*!< 0x00000100 */
27267 #define GTZC_MPCBB_CFGLOCKR2_SPLCK41_Pos     (9U)
27268 #define GTZC_MPCBB_CFGLOCKR2_SPLCK41_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK41_Pos) /*!< 0x00000200 */
27269 #define GTZC_MPCBB_CFGLOCKR2_SPLCK42_Pos     (10U)
27270 #define GTZC_MPCBB_CFGLOCKR2_SPLCK42_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK42_Pos) /*!< 0x00000400 */
27271 #define GTZC_MPCBB_CFGLOCKR2_SPLCK43_Pos     (11U)
27272 #define GTZC_MPCBB_CFGLOCKR2_SPLCK43_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK43_Pos) /*!< 0x00000800 */
27273 #define GTZC_MPCBB_CFGLOCKR2_SPLCK44_Pos     (12U)
27274 #define GTZC_MPCBB_CFGLOCKR2_SPLCK44_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK44_Pos) /*!< 0x00001000 */
27275 #define GTZC_MPCBB_CFGLOCKR2_SPLCK45_Pos     (13U)
27276 #define GTZC_MPCBB_CFGLOCKR2_SPLCK45_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK45_Pos) /*!< 0x00002000 */
27277 #define GTZC_MPCBB_CFGLOCKR2_SPLCK46_Pos     (14U)
27278 #define GTZC_MPCBB_CFGLOCKR2_SPLCK46_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK46_Pos) /*!< 0x00004000 */
27279 #define GTZC_MPCBB_CFGLOCKR2_SPLCK47_Pos     (15U)
27280 #define GTZC_MPCBB_CFGLOCKR2_SPLCK47_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK47_Pos) /*!< 0x00008000 */
27281 #define GTZC_MPCBB_CFGLOCKR2_SPLCK48_Pos     (16U)
27282 #define GTZC_MPCBB_CFGLOCKR2_SPLCK48_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK48_Pos) /*!< 0x00010000 */
27283 #define GTZC_MPCBB_CFGLOCKR2_SPLCK49_Pos     (17U)
27284 #define GTZC_MPCBB_CFGLOCKR2_SPLCK49_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK49_Pos) /*!< 0x00020000 */
27285 #define GTZC_MPCBB_CFGLOCKR2_SPLCK50_Pos     (18U)
27286 #define GTZC_MPCBB_CFGLOCKR2_SPLCK50_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK50_Pos) /*!< 0x00040000 */
27287 #define GTZC_MPCBB_CFGLOCKR2_SPLCK51_Pos     (19U)
27288 #define GTZC_MPCBB_CFGLOCKR2_SPLCK51_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK51_Pos) /*!< 0x00080000 */
27289 
27290 /******************************************************************************/
27291 /*                                                                            */
27292 /*                                    UCPD                                    */
27293 /*                                                                            */
27294 /******************************************************************************/
27295 /********************  Bits definition for UCPD_CFG1 register  *******************/
27296 #define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
27297 #define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x0000003F */
27298 #define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk                /*!< Number of cycles (minus 1) for a half bit clock */
27299 #define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x00000001 */
27300 #define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x00000002 */
27301 #define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x00000004 */
27302 #define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x00000008 */
27303 #define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x00000010 */
27304 #define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos)    /*!< 0x00000020 */
27305 #define UCPD_CFG1_IFRGAP_Pos                (6U)
27306 #define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)        /*!< 0x000007C0 */
27307 #define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                    /*!< Clock divider value to generates Interframe gap */
27308 #define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)        /*!< 0x00000040 */
27309 #define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)        /*!< 0x00000080 */
27310 #define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)        /*!< 0x00000100 */
27311 #define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)        /*!< 0x00000200 */
27312 #define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)        /*!< 0x00000400 */
27313 #define UCPD_CFG1_TRANSWIN_Pos              (11U)
27314 #define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)      /*!< 0x0000F800 */
27315 #define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk                  /*!< Number of cycles (minus 1) of the half bit clock */
27316 #define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)      /*!< 0x00000800 */
27317 #define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)      /*!< 0x00001000 */
27318 #define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)      /*!< 0x00002000 */
27319 #define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)      /*!< 0x00004000 */
27320 #define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)      /*!< 0x00008000 */
27321 #define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
27322 #define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos)    /*!< 0x000E0000 */
27323 #define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk               /*!< Prescaler for UCPDCLK */
27324 #define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos)    /*!< 0x00020000 */
27325 #define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos)    /*!< 0x00040000 */
27326 #define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos)    /*!< 0x00080000 */
27327 #define UCPD_CFG1_RXORDSETEN_Pos            (20U)
27328 #define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x1FF00000 */
27329 #define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk                /*!< Receiver ordered set detection enable */
27330 #define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x00100000 */
27331 #define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x00200000 */
27332 #define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x00400000 */
27333 #define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x00800000 */
27334 #define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x01000000 */
27335 #define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x02000000 */
27336 #define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x04000000 */
27337 #define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x08000000 */
27338 #define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)   /*!< 0x10000000 */
27339 #define UCPD_CFG1_TXDMAEN_Pos               (29U)
27340 #define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)        /*!< 0x20000000 */
27341 #define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                   /*!< DMA transmission requests enable   */
27342 #define UCPD_CFG1_RXDMAEN_Pos               (30U)
27343 #define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)        /*!< 0x40000000 */
27344 #define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                   /*!< DMA reception requests enable   */
27345 #define UCPD_CFG1_UCPDEN_Pos                (31U)
27346 #define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)         /*!< 0x80000000 */
27347 #define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                    /*!< USB Power Delivery Block Enable */
27348 
27349 /********************  Bits definition for UCPD_CFG2 register  *******************/
27350 #define UCPD_CFG2_RXFILTDIS_Pos             (0U)
27351 #define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)      /*!< 0x00000001 */
27352 #define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk                 /*!< Enables an Rx pre-filter for the BMC decoder */
27353 #define UCPD_CFG2_RXFILT2N3_Pos             (1U)
27354 #define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)      /*!< 0x00000002 */
27355 #define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk                 /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
27356 #define UCPD_CFG2_FORCECLK_Pos              (2U)
27357 #define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)       /*!< 0x00000004 */
27358 #define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk                  /*!< Controls forcing of the clock request UCPDCLK_REQ */
27359 #define UCPD_CFG2_WUPEN_Pos                 (3U)
27360 #define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)          /*!< 0x00000008 */
27361 #define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                     /*!< Wakeup from STOP enable */
27362 #define UCPD_CFG2_RXAFILTEN_Pos             (8U)
27363 #define UCPD_CFG2_RXAFILTEN_Msk             (0x1UL << UCPD_CFG2_RXAFILTEN_Pos)      /*!< 0x00000100 */
27364 #define UCPD_CFG2_RXAFILTEN                 UCPD_CFG2_RXAFILTEN_Msk                 /*!< RX Analog Filter enable */
27365 
27366 /********************  Bits definition for UCPD_CFG3 register  *******************/
27367 #define UCPD_CFG3_TRIM_CC1_RD_Pos           (0U)
27368 #define UCPD_CFG3_TRIM_CC1_RD_Msk           (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos)   /*!< 0x0000000F */
27369 #define UCPD_CFG3_TRIM_CC1_RD               UCPD_CFG3_TRIM_CC1_RD_Msk              /*!< SW trim value for RD resistor (CC1) */
27370 #define UCPD_CFG3_TRIM_CC1_RP_Pos           (9U)
27371 #define UCPD_CFG3_TRIM_CC1_RP_Msk           (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos)   /*!< 0x00001E00 */
27372 #define UCPD_CFG3_TRIM_CC1_RP               UCPD_CFG3_TRIM_CC1_RP_Msk              /*!< SW trim value for RP current sources (CC1) */
27373 #define UCPD_CFG3_TRIM_CC2_RD_Pos           (16U)
27374 #define UCPD_CFG3_TRIM_CC2_RD_Msk           (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos)   /*!< 0x000F0000 */
27375 #define UCPD_CFG3_TRIM_CC2_RD               UCPD_CFG3_TRIM_CC2_RD_Msk              /*!< SW trim value for RD resistor (CC2) */
27376 #define UCPD_CFG3_TRIM_CC2_RP_Pos           (25U)
27377 #define UCPD_CFG3_TRIM_CC2_RP_Msk           (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos)   /*!< 0x1E000000 */
27378 #define UCPD_CFG3_TRIM_CC2_RP               UCPD_CFG3_TRIM_CC2_RP_Msk              /*!< SW trim value for RP current sources (CC2) */
27379 
27380 /********************  Bits definition for UCPD_CR register  ********************/
27381 #define UCPD_CR_TXMODE_Pos                  (0U)
27382 #define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)           /*!< 0x00000003 */
27383 #define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                      /*!< Type of Tx packet  */
27384 #define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)           /*!< 0x00000001 */
27385 #define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)           /*!< 0x00000002 */
27386 #define UCPD_CR_TXSEND_Pos                  (2U)
27387 #define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)           /*!< 0x00000004 */
27388 #define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                      /*!< Type of Tx packet  */
27389 #define UCPD_CR_TXHRST_Pos                  (3U)
27390 #define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)           /*!< 0x00000008 */
27391 #define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                      /*!< Command to send a Tx Hard Reset  */
27392 #define UCPD_CR_RXMODE_Pos                  (4U)
27393 #define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)           /*!< 0x00000010 */
27394 #define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                      /*!< Receiver mode  */
27395 #define UCPD_CR_PHYRXEN_Pos                 (5U)
27396 #define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)          /*!< 0x00000020 */
27397 #define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                     /*!< Controls enable of USB Power Delivery receiver  */
27398 #define UCPD_CR_PHYCCSEL_Pos                (6U)
27399 #define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)         /*!< 0x00000040 */
27400 #define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                    /*!<  */
27401 #define UCPD_CR_ANASUBMODE_Pos              (7U)
27402 #define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)       /*!< 0x00000180 */
27403 #define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk                  /*!< Analog PHY sub-mode   */
27404 #define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)       /*!< 0x00000080 */
27405 #define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)       /*!< 0x00000100 */
27406 #define UCPD_CR_ANAMODE_Pos                 (9U)
27407 #define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)          /*!< 0x00000200 */
27408 #define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                     /*!< Analog PHY working mode   */
27409 #define UCPD_CR_CCENABLE_Pos                (10U)
27410 #define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)         /*!< 0x00000C00 */
27411 #define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                    /*!<  */
27412 #define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)         /*!< 0x00000400 */
27413 #define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)         /*!< 0x00000800 */
27414 #define UCPD_CR_FRSRXEN_Pos                 (16U)
27415 #define UCPD_CR_FRSRXEN_Msk                 (0x1UL << UCPD_CR_FRSRXEN_Pos)          /*!< 0x00010000 */
27416 #define UCPD_CR_FRSRXEN                     UCPD_CR_FRSRXEN_Msk                     /*!< Enable FRS request detection function */
27417 #define UCPD_CR_FRSTX_Pos                   (17U)
27418 #define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)            /*!< 0x00020000 */
27419 #define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                       /*!< Signal Fast Role Swap request */
27420 #define UCPD_CR_RDCH_Pos                    (18U)
27421 #define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)             /*!< 0x00040000 */
27422 #define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                        /*!<  */
27423 #define UCPD_CR_CC1TCDIS_Pos                (20U)
27424 #define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)         /*!< 0x00100000 */
27425 #define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                    /*!< The bit allows the Type-C detector for CC0 to be disabled. */
27426 #define UCPD_CR_CC2TCDIS_Pos                (21U)
27427 #define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)         /*!< 0x00200000 */
27428 #define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                    /*!< The bit allows the Type-C detector for CC2 to be disabled. */
27429 
27430 /********************  Bits definition for UCPD_IMR register  *******************/
27431 #define UCPD_IMR_TXISIE_Pos                 (0U)
27432 #define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)          /*!< 0x00000001 */
27433 #define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                     /*!< Enable TXIS interrupt  */
27434 #define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
27435 #define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)     /*!< 0x00000002 */
27436 #define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk                /*!< Enable TXMSGDISC interrupt  */
27437 #define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
27438 #define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)     /*!< 0x00000004 */
27439 #define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk                /*!< Enable TXMSGSENT interrupt  */
27440 #define UCPD_IMR_TXMSGABTIE_Pos             (3U)
27441 #define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)      /*!< 0x00000008 */
27442 #define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk                 /*!< Enable TXMSGABT interrupt  */
27443 #define UCPD_IMR_HRSTDISCIE_Pos             (4U)
27444 #define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)      /*!< 0x00000010 */
27445 #define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk                 /*!< Enable HRSTDISC interrupt  */
27446 #define UCPD_IMR_HRSTSENTIE_Pos             (5U)
27447 #define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)      /*!< 0x00000020 */
27448 #define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk                 /*!< Enable HRSTSENT interrupt  */
27449 #define UCPD_IMR_TXUNDIE_Pos                (6U)
27450 #define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)         /*!< 0x00000040 */
27451 #define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                    /*!< Enable TXUND interrupt  */
27452 #define UCPD_IMR_RXNEIE_Pos                 (8U)
27453 #define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)          /*!< 0x00000100 */
27454 #define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                     /*!< Enable RXNE interrupt  */
27455 #define UCPD_IMR_RXORDDETIE_Pos             (9U)
27456 #define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)      /*!< 0x00000200 */
27457 #define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk                 /*!< Enable RXORDDET interrupt  */
27458 #define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
27459 #define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)     /*!< 0x00000400 */
27460 #define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk                /*!< Enable RXHRSTDET interrupt  */
27461 #define UCPD_IMR_RXOVRIE_Pos                (11U)
27462 #define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)         /*!< 0x00000800 */
27463 #define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                    /*!< Enable RXOVR interrupt  */
27464 #define UCPD_IMR_RXMSGENDIE_Pos             (12U)
27465 #define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)      /*!< 0x00001000 */
27466 #define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk                 /*!< Enable RXMSGEND interrupt  */
27467 #define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
27468 #define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)     /*!< 0x00004000 */
27469 #define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk                /*!< Enable TYPECEVT1IE interrupt  */
27470 #define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
27471 #define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)     /*!< 0x00008000 */
27472 #define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk                /*!< Enable TYPECEVT2IE interrupt  */
27473 #define UCPD_IMR_FRSEVTIE_Pos               (20U)
27474 #define UCPD_IMR_FRSEVTIE_Msk               (0x1UL << UCPD_IMR_FRSEVTIE_Pos)        /*!< 0x00100000 */
27475 #define UCPD_IMR_FRSEVTIE                   UCPD_IMR_FRSEVTIE_Msk                   /*!< Fast Role Swap interrupt  */
27476 
27477 /********************  Bits definition for UCPD_SR register  ********************/
27478 #define UCPD_SR_TXIS_Pos                    (0U)
27479 #define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)             /*!< 0x00000001 */
27480 #define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                        /*!< Transmit interrupt status  */
27481 #define UCPD_SR_TXMSGDISC_Pos               (1U)
27482 #define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)        /*!< 0x00000002 */
27483 #define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                   /*!< Transmit message discarded interrupt  */
27484 #define UCPD_SR_TXMSGSENT_Pos               (2U)
27485 #define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)        /*!< 0x00000004 */
27486 #define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                   /*!< Transmit message sent interrupt  */
27487 #define UCPD_SR_TXMSGABT_Pos                (3U)
27488 #define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)         /*!< 0x00000008 */
27489 #define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                    /*!< Transmit message abort interrupt  */
27490 #define UCPD_SR_HRSTDISC_Pos                (4U)
27491 #define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)         /*!< 0x00000010 */
27492 #define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                    /*!< HRST discarded interrupt  */
27493 #define UCPD_SR_HRSTSENT_Pos                (5U)
27494 #define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)         /*!< 0x00000020 */
27495 #define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                    /*!< HRST sent interrupt  */
27496 #define UCPD_SR_TXUND_Pos                   (6U)
27497 #define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)            /*!< 0x00000040 */
27498 #define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                       /*!< Tx data underrun condition interrupt  */
27499 #define UCPD_SR_RXNE_Pos                    (8U)
27500 #define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)             /*!< 0x00000100 */
27501 #define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                        /*!< Receive data register not empty interrupt  */
27502 #define UCPD_SR_RXORDDET_Pos                (9U)
27503 #define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)         /*!< 0x00000200 */
27504 #define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                    /*!< Rx ordered set (4 K-codes) detected interrupt  */
27505 #define UCPD_SR_RXHRSTDET_Pos               (10U)
27506 #define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)        /*!< 0x00000400 */
27507 #define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                   /*!< Rx Hard Reset detect interrupt  */
27508 #define UCPD_SR_RXOVR_Pos                   (11U)
27509 #define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)            /*!< 0x00000800 */
27510 #define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                       /*!< Rx data overflow interrupt  */
27511 #define UCPD_SR_RXMSGEND_Pos                (12U)
27512 #define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)         /*!< 0x00001000 */
27513 #define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                    /*!< Rx message received  */
27514 #define UCPD_SR_RXERR_Pos                   (13U)
27515 #define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)            /*!< 0x00002000 */
27516 #define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                       /*!< RX Error */
27517 #define UCPD_SR_TYPECEVT1_Pos               (14U)
27518 #define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)        /*!< 0x00004000 */
27519 #define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                   /*!< Type C voltage level event on CC1  */
27520 #define UCPD_SR_TYPECEVT2_Pos               (15U)
27521 #define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)        /*!< 0x00008000 */
27522 #define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                   /*!< Type C voltage level event on CC2  */
27523 #define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
27524 #define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00030000 */
27525 #define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk            /*!< Status of DC level on CC1 pin  */
27526 #define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00010000 */
27527 #define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00020000 */
27528 #define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
27529 #define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x000C0000 */
27530 #define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk            /*!<Status of DC level on CC2 pin  */
27531 #define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x00040000 */
27532 #define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x00080000 */
27533 #define UCPD_SR_FRSEVT_Pos                  (20U)
27534 #define UCPD_SR_FRSEVT_Msk                  (0x1UL << UCPD_SR_FRSEVT_Pos)           /*!< 0x00100000 */
27535 #define UCPD_SR_FRSEVT                      UCPD_SR_FRSEVT_Msk                      /*!< Fast Role Swap detection event  */
27536 
27537 /********************  Bits definition for UCPD_ICR register  *******************/
27538 #define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
27539 #define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)     /*!< 0x00000002 */
27540 #define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk                /*!< Tx message discarded flag (TXMSGDISC) clear  */
27541 #define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
27542 #define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)     /*!< 0x00000004 */
27543 #define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk                /*!< Tx message sent flag (TXMSGSENT) clear  */
27544 #define UCPD_ICR_TXMSGABTCF_Pos             (3U)
27545 #define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)      /*!< 0x00000008 */
27546 #define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk                 /*!< Tx message abort flag (TXMSGABT) clear  */
27547 #define UCPD_ICR_HRSTDISCCF_Pos             (4U)
27548 #define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)      /*!< 0x00000010 */
27549 #define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk                 /*!< Hard reset discarded flag (HRSTDISC) clear  */
27550 #define UCPD_ICR_HRSTSENTCF_Pos             (5U)
27551 #define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)      /*!< 0x00000020 */
27552 #define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk                 /*!< Hard reset sent flag (HRSTSENT) clear  */
27553 #define UCPD_ICR_TXUNDCF_Pos                (6U)
27554 #define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)         /*!< 0x00000040 */
27555 #define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                    /*!< Tx underflow flag (TXUND) clear  */
27556 #define UCPD_ICR_RXORDDETCF_Pos             (9U)
27557 #define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)      /*!< 0x00000200 */
27558 #define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk                 /*!< Rx ordered set detect flag (RXORDDET) clear  */
27559 #define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
27560 #define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)     /*!< 0x00000400 */
27561 #define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk                /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
27562 #define UCPD_ICR_RXOVRCF_Pos                (11U)
27563 #define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)         /*!< 0x00000800 */
27564 #define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                    /*!< Rx overflow flag (RXOVR) clear  */
27565 #define UCPD_ICR_RXMSGENDCF_Pos             (12U)
27566 #define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)      /*!< 0x00001000 */
27567 #define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk                 /*!< Rx message received flag (RXMSGEND) clear  */
27568 #define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
27569 #define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)     /*!< 0x00004000 */
27570 #define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk                /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
27571 #define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
27572 #define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)     /*!< 0x00008000 */
27573 #define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk                /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
27574 #define UCPD_ICR_FRSEVTCF_Pos               (20U)
27575 #define UCPD_ICR_FRSEVTCF_Msk               (0x1UL << UCPD_ICR_FRSEVTCF_Pos)        /*!< 0x00100000 */
27576 #define UCPD_ICR_FRSEVTCF                   UCPD_ICR_FRSEVTCF_Msk                   /*!< Fast Role Swap event flag clear  */
27577 
27578 /********************  Bits definition for UCPD_TXORDSET register  **************/
27579 #define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
27580 #define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos) /*!< 0x000FFFFF */
27581 #define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk             /*!< Tx Ordered Set */
27582 
27583 /********************  Bits definition for UCPD_TXPAYSZ register  ****************/
27584 #define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
27585 #define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)  /*!< 0x000003FF */
27586 #define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk               /*!< Tx payload size in bytes  */
27587 
27588 /********************  Bits definition for UCPD_TXDR register  *******************/
27589 #define UCPD_TXDR_TXDATA_Pos                (0U)
27590 #define UCPD_TXDR_TXDATA_Msk                (0xFFUL << UCPD_TXDR_TXDATA_Pos)        /*!< 0x000000FF */
27591 #define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                    /*!< Tx Data Register */
27592 
27593 /********************  Bits definition for UCPD_RXORDSET register  **************/
27594 #define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
27595 #define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos)  /*!< 0x00000007 */
27596 #define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk             /*!< Rx Ordered Set Code detected  */
27597 #define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos)  /*!< 0x00000001 */
27598 #define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos)  /*!< 0x00000002 */
27599 #define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos)  /*!< 0x00000004 */
27600 #define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
27601 #define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos) /*!< 0x00000008 */
27602 #define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk            /*!< Rx Ordered Set Debug indication */
27603 #define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
27604 #define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos) /*!< 0x00000070 */
27605 #define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk        /*!< Rx Ordered Set corrupted K-Codes (Debug) */
27606 
27607 /********************  Bits definition for UCPD_RXPAYSZ register  ****************/
27608 #define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
27609 #define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)  /*!< 0x000003FF */
27610 #define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk               /*!< Rx payload size in bytes  */
27611 
27612 /********************  Bits definition for UCPD_RXDR register  *******************/
27613 #define UCPD_RXDR_RXDATA_Pos                (0U)
27614 #define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)        /*!< 0x000000FF */
27615 #define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                    /*!< 8-bit receive data  */
27616 
27617 /********************  Bits definition for UCPD_RXORDEXT1 register  **************/
27618 #define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
27619 #define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos) /*!< 0x000FFFFF */
27620 #define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk             /*!< RX Ordered Set Extension Register 1 */
27621 
27622 /********************  Bits definition for UCPD_RXORDEXT2 register  **************/
27623 #define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
27624 #define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos) /*!< 0x000FFFFF */
27625 #define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk             /*!< RX Ordered Set Extension Register 1 */
27626 
27627 /******************************************************************************/
27628 /*                                                                            */
27629 /*                                       USB_OTG                              */
27630 /*                                                                            */
27631 /******************************************************************************/
27632 /********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
27633 #define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
27634 #define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos)      /*!< 0x00000001 */
27635 #define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk                /*!< Session request success */
27636 #define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
27637 #define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos)         /*!< 0x00000002 */
27638 #define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk                   /*!< Session request */
27639 #define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
27640 #define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos)    /*!< 0x00000004 */
27641 #define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk              /*!< VBUS valid override enable */
27642 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
27643 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos)   /*!< 0x00000008 */
27644 #define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk             /*!< VBUS valid override value */
27645 #define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
27646 #define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos)     /*!< 0x00000010 */
27647 #define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk               /*!< A-peripheral session valid override enable */
27648 #define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
27649 #define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos)    /*!< 0x00000020 */
27650 #define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk              /*!< A-peripheral session valid override value */
27651 #define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
27652 #define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos)     /*!< 0x00000040 */
27653 #define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk               /*!< B-peripheral session valid override enable */
27654 #define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
27655 #define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos)    /*!< 0x00000080 */
27656 #define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk              /*!< B-peripheral session valid override value  */
27657 #define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
27658 #define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1U << USB_OTG_GOTGCTL_EHEN_Pos)        /*!< 0x00001000 */
27659 #define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk                  /*!< Embedded host enable  */
27660 #define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
27661 #define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos)      /*!< 0x00010000 */
27662 #define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk                /*!< Connector ID status  */
27663 #define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
27664 #define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1U << USB_OTG_GOTGCTL_DBCT_Pos)        /*!< 0x00020000 */
27665 #define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk                  /*!< Long/short debounce time  */
27666 #define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
27667 #define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos)        /*!< 0x00040000 */
27668 #define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk                  /*!< A-session valid  */
27669 #define USB_OTG_GOTGCTL_BSVLD_Pos                (19U)
27670 #define USB_OTG_GOTGCTL_BSVLD_Msk                (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos)       /*!< 0x00080000 */
27671 #define USB_OTG_GOTGCTL_BSVLD                    USB_OTG_GOTGCTL_BSVLD_Msk                 /*!<  B-session valid  */
27672 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
27673 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos)        /*!< 0x00100000 */
27674 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk                  /*!< OTG version  */
27675 #define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
27676 #define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos)       /*!< 0x00200000 */
27677 #define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk                 /*!<  Current mode of operation  */
27678 
27679 /********************  Bit definition for USB_OTG_HCFG register  ********************/
27680 #define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
27681 #define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos)        /*!< 0x00000003 */
27682 #define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk                  /*!< FS/LS PHY clock select */
27683 #define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos)        /*!< 0x00000001 */
27684 #define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos)        /*!< 0x00000002 */
27685 #define USB_OTG_HCFG_FSLSS_Pos                   (2U)
27686 #define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos)          /*!< 0x00000004 */
27687 #define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk                    /*!< FS- and LS-only support */
27688 
27689 /********************  Bit definition for USB_OTG_DCFG register  ********************/
27690 #define USB_OTG_DCFG_DSPD_Pos                    (0U)
27691 #define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos)           /*!< 0x00000003 */
27692 #define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk                     /*!< Device speed */
27693 #define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos)           /*!< 0x00000001 */
27694 #define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos)           /*!< 0x00000002 */
27695 #define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
27696 #define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos)       /*!< 0x00000004 */
27697 #define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk                 /*!< Nonzero-length status OUT handshake */
27698 #define USB_OTG_DCFG_DAD_Pos                     (4U)
27699 #define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos)           /*!< 0x000007F0 */
27700 #define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk                      /*!< Device address */
27701 #define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000010 */
27702 #define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000020 */
27703 #define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000040 */
27704 #define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000080 */
27705 #define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000100 */
27706 #define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000200 */
27707 #define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos)           /*!< 0x00000400 */
27708 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
27709 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos)          /*!< 0x00001800 */
27710 #define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk                    /*!< Periodic (micro)frame interval */
27711 #define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos)          /*!< 0x00000800 */
27712 #define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos)          /*!< 0x00001000 */
27713 #define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
27714 #define USB_OTG_DCFG_ERRATIM_Msk                 (0x1U << USB_OTG_DCFG_ERRATIM_Pos)        /*!< 0x00008000 */
27715 #define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk                  /*!< Erratic error interrupt mask */
27716 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
27717 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos)      /*!< 0x03000000 */
27718 #define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk                /*!< Periodic scheduling interval */
27719 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos)      /*!< 0x01000000 */
27720 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos)      /*!< 0x02000000 */
27721 
27722 /********************  Bit definition for USB_OTG_PCGCR register  ********************/
27723 #define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
27724 #define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos)       /*!< 0x00000001 */
27725 #define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk                 /*!< Stop PHY clock */
27726 #define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
27727 #define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos)      /*!< 0x00000002 */
27728 #define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk                /*!< Gate HCLK */
27729 #define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
27730 #define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos)       /*!< 0x00000010 */
27731 #define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk                 /*!< PHY suspended */
27732 
27733 /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
27734 #define USB_OTG_GOTGINT_SEDET_Pos                (2U)
27735 #define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos)       /*!< 0x00000004 */
27736 #define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk                 /*!< Session end detected */
27737 #define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
27738 #define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos)     /*!< 0x00000100 */
27739 #define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk               /*!< Session request success status change */
27740 #define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
27741 #define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos)     /*!< 0x00000200 */
27742 #define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk               /*!< Host negotiation success status change */
27743 #define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
27744 #define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos)      /*!< 0x00020000 */
27745 #define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk                /*!< Host negotiation detected */
27746 #define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
27747 #define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos)     /*!< 0x00040000 */
27748 #define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk               /*!< A-device timeout change */
27749 #define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
27750 #define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos)      /*!< 0x00080000 */
27751 #define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk                /*!< Debounce done */
27752 
27753 /********************  Bit definition for USB_OTG_DCTL register  ********************/
27754 #define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
27755 #define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos)         /*!< 0x00000001 */
27756 #define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk                   /*!< Remote wakeup signaling */
27757 #define USB_OTG_DCTL_SDIS_Pos                    (1U)
27758 #define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos)           /*!< 0x00000002 */
27759 #define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk                     /*!< Soft disconnect */
27760 #define USB_OTG_DCTL_GINSTS_Pos                  (2U)
27761 #define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos)         /*!< 0x00000004 */
27762 #define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk                   /*!< Global IN NAK status */
27763 #define USB_OTG_DCTL_GONSTS_Pos                  (3U)
27764 #define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos)         /*!< 0x00000008 */
27765 #define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk                   /*!< Global OUT NAK status */
27766 #define USB_OTG_DCTL_TCTL_Pos                    (4U)
27767 #define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos)           /*!< 0x00000070 */
27768 #define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk                     /*!< Test control */
27769 #define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos)           /*!< 0x00000010 */
27770 #define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos)           /*!< 0x00000020 */
27771 #define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos)           /*!< 0x00000040 */
27772 #define USB_OTG_DCTL_SGINAK_Pos                  (7U)
27773 #define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos)         /*!< 0x00000080 */
27774 #define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk                   /*!< Set global IN NAK */
27775 #define USB_OTG_DCTL_CGINAK_Pos                  (8U)
27776 #define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos)         /*!< 0x00000100 */
27777 #define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk                   /*!< Clear global IN NAK */
27778 #define USB_OTG_DCTL_SGONAK_Pos                  (9U)
27779 #define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos)         /*!< 0x00000200 */
27780 #define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk                   /*!< Set global OUT NAK */
27781 #define USB_OTG_DCTL_CGONAK_Pos                  (10U)
27782 #define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos)         /*!< 0x00000400 */
27783 #define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk                   /*!< Clear global OUT NAK */
27784 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
27785 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos)       /*!< 0x00000800 */
27786 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk                 /*!< Power-on programming done */
27787 #define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
27788 #define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos)     /*!< 0x00040000 */
27789 #define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk               /*!< Deep sleep BESL reject */
27790 
27791 /********************  Bit definition for USB_OTG_HFIR register  ********************/
27792 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
27793 #define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos)       /*!< 0x0000FFFF */
27794 #define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk                    /*!< Frame interval */
27795 #define USB_OTG_HFIR_RLDCTRL_Pos                 (16U)
27796 #define USB_OTG_HFIR_RLDCTRL_Msk                 (0x1U << USB_OTG_HFIR_RLDCTRL_Pos)        /*!< 0x00010000 */
27797 #define USB_OTG_HFIR_RLDCTRL                     USB_OTG_HFIR_RLDCTRL_Msk                  /*!<  Reload control */
27798 
27799 /********************  Bit definition for USB_OTG_HFNUM register  ********************/
27800 #define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
27801 #define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos)      /*!< 0x0000FFFF */
27802 #define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk                   /*!< Frame number */
27803 #define USB_OTG_HFNUM_FTREM_Pos                  (16U)
27804 #define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos)      /*!< 0xFFFF0000 */
27805 #define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk                   /*!< Frame time remaining */
27806 
27807 /********************  Bit definition for USB_OTG_DSTS register  ********************/
27808 #define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
27809 #define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos)        /*!< 0x00000001 */
27810 #define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk                  /*!< Suspend status */
27811 
27812 #define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
27813 #define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos)        /*!< 0x00000006 */
27814 #define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk                  /*!< Enumerated speed */
27815 #define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos)        /*!< 0x00000002 */
27816 #define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos)        /*!< 0x00000004 */
27817 #define USB_OTG_DSTS_EERR_Pos                    (3U)
27818 #define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos)           /*!< 0x00000008 */
27819 #define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk                     /*!< Erratic error */
27820 #define USB_OTG_DSTS_FNSOF_Pos                   (8U)
27821 #define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos)       /*!< 0x003FFF00 */
27822 #define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk                    /*!< Frame number of the received SOF */
27823 #define USB_OTG_DSTS_DEVLNSTS_Pos                (22U)
27824 #define USB_OTG_DSTS_DEVLNSTS_Msk                (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos)       /*!< 0x00C00000 */
27825 #define USB_OTG_DSTS_DEVLNSTS                    USB_OTG_DSTS_DEVLNSTS_Msk                 /*!< Device line status */
27826 
27827 /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
27828 #define USB_OTG_GAHBCFG_GINTMSK_Pos              (0U)
27829 #define USB_OTG_GAHBCFG_GINTMSK_Msk              (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos)     /*!< 0x00000001 */
27830 #define USB_OTG_GAHBCFG_GINTMSK                  USB_OTG_GAHBCFG_GINTMSK_Msk               /*!< Global interrupt mask */
27831 #define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
27832 #define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos)     /*!< 0x0000001E */
27833 #define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk               /*!< Burst length/type */
27834 #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos)     /*!< 0x00000002 */
27835 #define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos)     /*!< 0x00000004 */
27836 #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos)     /*!< 0x00000008 */
27837 #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos)     /*!< 0x00000010 */
27838 #define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
27839 #define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos)       /*!< 0x00000020 */
27840 #define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk                 /*!< DMA enable */
27841 #define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
27842 #define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos)     /*!< 0x00000080 */
27843 #define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk               /*!< TxFIFO empty level */
27844 #define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
27845 #define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos)    /*!< 0x00000100 */
27846 #define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk              /*!< Periodic TxFIFO empty level */
27847 
27848 /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
27849 #define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
27850 #define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos)       /*!< 0x00000007 */
27851 #define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk                 /*!< FS timeout calibration */
27852 #define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos)       /*!< 0x00000001 */
27853 #define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos)       /*!< 0x00000002 */
27854 #define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos)       /*!< 0x00000004 */
27855 #define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
27856 #define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos)      /*!< 0x00000040 */
27857 #define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk                /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
27858 #define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
27859 #define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos)      /*!< 0x00000100 */
27860 #define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk                /*!< SRP-capable */
27861 #define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
27862 #define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos)      /*!< 0x00000200 */
27863 #define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk                /*!< HNP-capable */
27864 #define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
27865 #define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos)        /*!< 0x00003C00 */
27866 #define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk                  /*!< USB turnaround time */
27867 #define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos)        /*!< 0x00000400 */
27868 #define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos)        /*!< 0x00000800 */
27869 #define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos)        /*!< 0x00001000 */
27870 #define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos)        /*!< 0x00002000 */
27871 #define USB_OTG_GUSBCFG_PHYLPC_Pos               (15U)
27872 #define USB_OTG_GUSBCFG_PHYLPC_Msk               (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos)     /*!< 0x00008000 */
27873 #define USB_OTG_GUSBCFG_PHYLPC                   USB_OTG_GUSBCFG_PHYLPC_Msk               /*!< PHY Low-power clock select */
27874 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
27875 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos)    /*!< 0x00020000 */
27876 #define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk              /*!< ULPI FS/LS select */
27877 #define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
27878 #define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos)      /*!< 0x00040000 */
27879 #define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk                /*!< ULPI Auto-resume */
27880 #define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
27881 #define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos)     /*!< 0x00080000 */
27882 #define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk               /*!< ULPI Clock SuspendM */
27883 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
27884 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)  /*!< 0x00100000 */
27885 #define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk            /*!< ULPI External VBUS Drive */
27886 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
27887 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)  /*!< 0x00200000 */
27888 #define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk            /*!< ULPI external VBUS indicator */
27889 #define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
27890 #define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos)       /*!< 0x00400000 */
27891 #define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk                 /*!< TermSel DLine pulsing selection */
27892 #define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
27893 #define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos)        /*!< 0x00800000 */
27894 #define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk                  /*!< Indicator complement */
27895 #define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
27896 #define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos)        /*!< 0x01000000 */
27897 #define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk                  /*!< Indicator pass through */
27898 #define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
27899 #define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos)     /*!< 0x02000000 */
27900 #define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk               /*!< ULPI interface protect disable */
27901 #define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
27902 #define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos)       /*!< 0x20000000 */
27903 #define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk                 /*!< Forced host mode */
27904 #define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
27905 #define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos)       /*!< 0x40000000 */
27906 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk                 /*!< Forced peripheral mode */
27907 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
27908 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos)      /*!< 0x80000000 */
27909 #define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk                /*!< Corrupt Tx packet */
27910 
27911 /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
27912 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
27913 #define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos)       /*!< 0x00000001 */
27914 #define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk                 /*!< Core soft reset */
27915 #define USB_OTG_GRSTCTL_PSRST_Pos                (1U)
27916 #define USB_OTG_GRSTCTL_PSRST_Msk                (0x1U << USB_OTG_GRSTCTL_PSRST_Pos)       /*!< 0x00000002 */
27917 #define USB_OTG_GRSTCTL_PSRST                    USB_OTG_GRSTCTL_PSRST_Msk                 /*!<  Partial soft reset */
27918 #define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
27919 #define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos)       /*!< 0x00000004 */
27920 #define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk                 /*!< Host frame counter reset */
27921 #define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
27922 #define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos)     /*!< 0x00000010 */
27923 #define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk               /*!< RxFIFO flush */
27924 #define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
27925 #define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos)     /*!< 0x00000020 */
27926 #define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk               /*!< TxFIFO flush */
27927 #define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
27928 #define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos)     /*!< 0x000007C0 */
27929 #define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk                /*!< TxFIFO number */
27930 #define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos)     /*!< 0x00000040 */
27931 #define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos)     /*!< 0x00000080 */
27932 #define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos)     /*!< 0x00000100 */
27933 #define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos)     /*!< 0x00000200 */
27934 #define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos)     /*!< 0x00000400 */
27935 #define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
27936 #define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos)      /*!< 0x40000000 */
27937 #define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk                /*!< DMA request signal */
27938 #define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
27939 #define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos)      /*!< 0x80000000 */
27940 #define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk                /*!< AHB master idle */
27941 
27942 /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
27943 #define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
27944 #define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos)       /*!< 0x00000001 */
27945 #define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk                 /*!< Transfer completed interrupt mask */
27946 #define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
27947 #define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos)        /*!< 0x00000002 */
27948 #define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk                  /*!< Endpoint disabled interrupt mask */
27949 #define USB_OTG_DIEPMSK_AHBERRM_Pos              (2U)
27950 #define USB_OTG_DIEPMSK_AHBERRM_Msk              (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos)     /*!< 0x00000004 */
27951 #define USB_OTG_DIEPMSK_AHBERRM                  USB_OTG_DIEPMSK_AHBERRM_Msk               /*!< AHB error mask */
27952 #define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
27953 #define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos)         /*!< 0x00000008 */
27954 #define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk                   /*!< Timeout condition mask (nonisochronous endpoints) */
27955 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
27956 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)   /*!< 0x00000010 */
27957 #define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk             /*!< IN token received when TxFIFO empty mask */
27958 #define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
27959 #define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos)     /*!< 0x00000020 */
27960 #define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk               /*!< IN token received with EP mismatch mask */
27961 #define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
27962 #define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos)     /*!< 0x00000040 */
27963 #define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk               /*!< IN endpoint NAK effective mask */
27964 #define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
27965 #define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos)      /*!< 0x00000100 */
27966 #define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk                /*!< FIFO underrun mask */
27967 #define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
27968 #define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos)         /*!< 0x00000200 */
27969 #define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk                   /*!< BNA interrupt mask */
27970 #define USB_OTG_DIEPMSK_NAKM_Pos                 (13U)
27971 #define USB_OTG_DIEPMSK_NAKM_Msk                 (0x1U << USB_OTG_DIEPMSK_NAKM_Pos)        /*!< 0x00002000 */
27972 #define USB_OTG_DIEPMSK_NAKM                     USB_OTG_DIEPMSK_NAKM_Msk                  /*!< NAK interrupt mask */
27973 
27974 /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
27975 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
27976 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
27977 #define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk              /*!< Periodic transmit data FIFO space available */
27978 #define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
27979 #define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00FF0000 */
27980 #define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk               /*!< Periodic transmit request queue space available */
27981 #define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00010000 */
27982 #define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00020000 */
27983 #define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00040000 */
27984 #define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00080000 */
27985 #define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00100000 */
27986 #define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00200000 */
27987 #define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00400000 */
27988 #define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos)    /*!< 0x00800000 */
27989 
27990 #define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
27991 #define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0xFF000000 */
27992 #define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk               /*!< Top of the periodic transmit request queue */
27993 #define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x01000000 */
27994 #define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x02000000 */
27995 #define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x04000000 */
27996 #define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x08000000 */
27997 #define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x10000000 */
27998 #define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x20000000 */
27999 #define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x40000000 */
28000 #define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos)    /*!< 0x80000000 */
28001 
28002 /********************  Bit definition for USB_OTG_HAINT register  ********************/
28003 #define USB_OTG_HAINT_HAINT_Pos                  (0U)
28004 #define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos)      /*!< 0x0000FFFF */
28005 #define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk                   /*!< Channel interrupts */
28006 
28007 /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
28008 #define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
28009 #define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos)       /*!< 0x00000001 */
28010 #define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk                 /*!< Transfer completed interrupt mask */
28011 #define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
28012 #define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos)        /*!< 0x00000002 */
28013 #define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk                  /*!< Endpoint disabled interrupt mask */
28014 #define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
28015 #define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos)     /*!< 0x00000004 */
28016 #define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk               /*!< AHB error mask */
28017 #define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
28018 #define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos)       /*!< 0x00000008 */
28019 #define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk                 /*!< SETUP phase done mask */
28020 #define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
28021 #define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos)      /*!< 0x00000010 */
28022 #define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk                /*!< OUT token received when endpoint disabled mask */
28023 #define USB_OTG_DOEPMSK_STSPHSRXM_Pos            (5U)
28024 #define USB_OTG_DOEPMSK_STSPHSRXM_Msk            (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos)   /*!< 0x00000020 */
28025 #define USB_OTG_DOEPMSK_STSPHSRXM                USB_OTG_DOEPMSK_STSPHSRXM_Msk             /*!< Status phase received for control write mask */
28026 #define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
28027 #define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos)     /*!< 0x00000040 */
28028 #define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk               /*!< Back-to-back SETUP packets received mask */
28029 #define USB_OTG_DOEPMSK_OUTPKTERRM_Pos           (8U)
28030 #define USB_OTG_DOEPMSK_OUTPKTERRM_Msk           (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos)  /*!< 0x00000100 */
28031 #define USB_OTG_DOEPMSK_OUTPKTERRM               USB_OTG_DOEPMSK_OUTPKTERRM_Msk            /*!< OUT packet error mask */
28032 #define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
28033 #define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos)        /*!< 0x00000200 */
28034 #define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk                  /*!< BNA interrupt mask */
28035 #define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
28036 #define USB_OTG_DOEPMSK_BERRM_Msk                (0x1U << USB_OTG_DOEPMSK_BERRM_Pos)       /*!< 0x00001000 */
28037 #define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk                 /*!< Babble error interrupt mask */
28038 #define USB_OTG_DOEPMSK_NAKMSK_Pos               (13U)
28039 #define USB_OTG_DOEPMSK_NAKMSK_Msk               (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos)      /*!< 0x00002000 */
28040 #define USB_OTG_DOEPMSK_NAKMSK                   USB_OTG_DOEPMSK_NAKMSK_Msk                /*!< NAK interrupt mask */
28041 #define USB_OTG_DOEPMSK_NYETMSK_Pos              (14U)
28042 #define USB_OTG_DOEPMSK_NYETMSK_Msk              (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos)     /*!< 0x00004000 */
28043 #define USB_OTG_DOEPMSK_NYETMSK                  USB_OTG_DOEPMSK_NYETMSK_Msk               /*!< NYET interrupt mask */
28044 
28045 /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
28046 #define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
28047 #define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos)              /*!< 0x00000001 */
28048 #define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk                        /*!< Current mode of operation */
28049 #define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
28050 #define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos)              /*!< 0x00000002 */
28051 #define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk                        /*!< Mode mismatch interrupt */
28052 #define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
28053 #define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos)            /*!< 0x00000004 */
28054 #define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk                      /*!< OTG interrupt */
28055 #define USB_OTG_GINTSTS_SOF_Pos                  (3U)
28056 #define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos)               /*!< 0x00000008 */
28057 #define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk                         /*!< Start of frame */
28058 #define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
28059 #define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos)            /*!< 0x00000010 */
28060 #define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk                      /*!< RxFIFO nonempty */
28061 #define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
28062 #define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos)            /*!< 0x00000020 */
28063 #define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk                      /*!< Nonperiodic TxFIFO empty */
28064 #define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
28065 #define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos)          /*!< 0x00000040 */
28066 #define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk                    /*!< Global IN nonperiodic NAK effective */
28067 #define USB_OTG_GINTSTS_GONAKEFF_Pos             (7U)
28068 #define USB_OTG_GINTSTS_GONAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos)        /*!< 0x00000080 */
28069 #define USB_OTG_GINTSTS_GONAKEFF                 USB_OTG_GINTSTS_GONAKEFF_Msk                  /*!< Global OUT NAK effective */
28070 #define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
28071 #define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos)             /*!< 0x00000400 */
28072 #define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk                       /*!< Early suspend */
28073 #define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
28074 #define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos)           /*!< 0x00000800 */
28075 #define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk                     /*!< USB suspend */
28076 #define USB_OTG_GINTSTS_USBRST_Pos               (12U)
28077 #define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos)            /*!< 0x00001000 */
28078 #define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk                      /*!< USB reset */
28079 #define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
28080 #define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos)           /*!< 0x00002000 */
28081 #define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk                     /*!< Enumeration done */
28082 #define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
28083 #define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos)           /*!< 0x00004000 */
28084 #define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk                     /*!< Isochronous OUT packet dropped interrupt */
28085 #define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
28086 #define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos)              /*!< 0x00008000 */
28087 #define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk                        /*!< End of periodic frame interrupt */
28088 #define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
28089 #define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos)            /*!< 0x00040000 */
28090 #define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk                      /*!< IN endpoint interrupt */
28091 #define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
28092 #define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos)            /*!< 0x00080000 */
28093 #define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk                      /*!< OUT endpoint interrupt */
28094 #define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
28095 #define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos)          /*!< 0x00100000 */
28096 #define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk                    /*!< Incomplete isochronous IN transfer */
28097 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
28098 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
28099 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk           /*!< Incomplete periodic transfer */
28100 #define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
28101 #define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos)         /*!< 0x00400000 */
28102 #define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk                   /*!< Data fetch suspended */
28103 #define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
28104 #define USB_OTG_GINTSTS_RSTDET_Msk               (0x1U << USB_OTG_GINTSTS_RSTDET_Pos)            /*!< 0x00800000 */
28105 #define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk                      /*!< Reset detected interrupt */
28106 #define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
28107 #define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos)           /*!< 0x01000000 */
28108 #define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk                     /*!< Host port interrupt */
28109 #define USB_OTG_GINTSTS_HCINT_Pos                (25U)
28110 #define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos)             /*!< 0x02000000 */
28111 #define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk                       /*!< Host channels interrupt */
28112 #define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
28113 #define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos)             /*!< 0x04000000 */
28114 #define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk                       /*!< Periodic TxFIFO empty */
28115 #define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
28116 #define USB_OTG_GINTSTS_LPMINT_Msk               (0x1U << USB_OTG_GINTSTS_LPMINT_Pos)            /*!< 0x08000000 */
28117 #define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk                      /*!< LPM interrupt */
28118 #define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
28119 #define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos)           /*!< 0x10000000 */
28120 #define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk                     /*!< Connector ID status change */
28121 #define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
28122 #define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos)           /*!< 0x20000000 */
28123 #define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk                     /*!< Disconnect detected interrupt */
28124 #define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
28125 #define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos)            /*!< 0x40000000 */
28126 #define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk                      /*!< Session request/new session detected interrupt */
28127 #define USB_OTG_GINTSTS_WKUPINT_Pos               (31U)
28128 #define USB_OTG_GINTSTS_WKUPINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos)          /*!< 0x80000000 */
28129 #define USB_OTG_GINTSTS_WKUPINT                   USB_OTG_GINTSTS_WKUPINT_Msk                    /*!< Resume/remote wakeup detected interrupt */
28130 
28131 /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
28132 #define USB_OTG_GINTMSK_MMISM_Pos                (1U)
28133 #define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos)           /*!< 0x00000002 */
28134 #define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk                     /*!< Mode mismatch interrupt mask */
28135 #define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
28136 #define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos)          /*!< 0x00000004 */
28137 #define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk                    /*!< OTG interrupt mask */
28138 #define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
28139 #define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos)            /*!< 0x00000008 */
28140 #define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk                      /*!< Start of frame mask */
28141 #define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
28142 #define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos)         /*!< 0x00000010 */
28143 #define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk                   /*!< Receive FIFO nonempty mask */
28144 #define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
28145 #define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos)         /*!< 0x00000020 */
28146 #define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk                   /*!< Nonperiodic TxFIFO empty mask */
28147 #define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
28148 #define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos)       /*!< 0x00000040 */
28149 #define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk                 /*!< Global nonperiodic IN NAK effective mask */
28150 #define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
28151 #define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos)       /*!< 0x00000080 */
28152 #define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk                 /*!< Global OUT NAK effective mask */
28153 #define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
28154 #define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos)          /*!< 0x00000400 */
28155 #define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk                    /*!< Early suspend mask */
28156 #define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
28157 #define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos)        /*!< 0x00000800 */
28158 #define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk                  /*!< USB suspend mask */
28159 #define USB_OTG_GINTMSK_USBRST_Pos               (12U)
28160 #define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos)          /*!< 0x00001000 */
28161 #define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk                    /*!< USB reset mask */
28162 #define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
28163 #define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos)        /*!< 0x00002000 */
28164 #define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk                  /*!< Enumeration done mask */
28165 #define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
28166 #define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos)        /*!< 0x00004000 */
28167 #define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk                  /*!< Isochronous OUT packet dropped interrupt mask */
28168 #define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
28169 #define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos)           /*!< 0x00008000 */
28170 #define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk                     /*!< End of periodic frame interrupt mask */
28171 #define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
28172 #define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos)          /*!< 0x00020000 */
28173 #define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk                    /*!< Endpoint mismatch interrupt mask */
28174 #define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
28175 #define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos)          /*!< 0x00040000 */
28176 #define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk                    /*!< IN endpoints interrupt mask */
28177 #define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
28178 #define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos)          /*!< 0x00080000 */
28179 #define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk                    /*!< OUT endpoints interrupt mask */
28180 #define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
28181 #define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos)       /*!< 0x00100000 */
28182 #define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk                 /*!< Incomplete isochronous IN transfer mask */
28183 #define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos     (21U)
28184 #define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk     (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */
28185 #define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM         USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk          /*!< Incomplete periodic transfer mask */
28186 #define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
28187 #define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos)          /*!< 0x00400000 */
28188 #define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk                    /*!< Data fetch suspended mask */
28189 #define USB_OTG_GINTMSK_RSTDETM_Pos              (23U)
28190 #define USB_OTG_GINTMSK_RSTDETM_Msk              (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos)          /*!< 0x00800000 */
28191 #define USB_OTG_GINTMSK_RSTDETM                  USB_OTG_GINTMSK_RSTDETM_Msk                    /*!< Reset detected interrupt mask */
28192 #define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
28193 #define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos)           /*!< 0x01000000 */
28194 #define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk                     /*!< Host port interrupt mask */
28195 #define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
28196 #define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos)            /*!< 0x02000000 */
28197 #define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk                      /*!< Host channels interrupt mask */
28198 #define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
28199 #define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos)          /*!< 0x04000000 */
28200 #define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk                    /*!< Periodic TxFIFO empty mask */
28201 #define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
28202 #define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos)         /*!< 0x08000000 */
28203 #define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk                   /*!< LPM interrupt Mask */
28204 #define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
28205 #define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos)        /*!< 0x10000000 */
28206 #define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk                  /*!< Connector ID status change mask */
28207 #define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
28208 #define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos)         /*!< 0x20000000 */
28209 #define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk                   /*!< Disconnect detected interrupt mask */
28210 #define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
28211 #define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos)           /*!< 0x40000000 */
28212 #define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk                     /*!< Session request/new session detected interrupt mask */
28213 #define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
28214 #define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos)            /*!< 0x80000000 */
28215 #define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk                      /*!< Resume/remote wakeup detected interrupt mask */
28216 
28217 /********************  Bit definition for USB_OTG_DAINT register  ********************/
28218 #define USB_OTG_DAINT_IEPINT_Pos                 (0U)
28219 #define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos)         /*!< 0x0000FFFF */
28220 #define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk                      /*!< IN endpoint interrupt bits */
28221 #define USB_OTG_DAINT_OEPINT_Pos                 (16U)
28222 #define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos)         /*!< 0xFFFF0000 */
28223 #define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk                      /*!< OUT endpoint interrupt bits */
28224 
28225 /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
28226 #define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
28227 #define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos)      /*!< 0x0000FFFF */
28228 #define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk                   /*!< Channel interrupt mask */
28229 
28230 /********************  Bit definition for USB_OTG_GRXSTSR register  ********************/
28231 #define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos          (0U)
28232 #define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk          (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos)     /*!< 0x0000000F */
28233 #define USB_OTG_GRXSTSR_EPNUM_CHNUM              USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk               /*!< Endpoint/Channel number */
28234 #define USB_OTG_GRXSTSR_BCNT_Pos                 (4U)
28235 #define USB_OTG_GRXSTSR_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos)          /*!< 0x00007FF0 */
28236 #define USB_OTG_GRXSTSR_BCNT                     USB_OTG_GRXSTSR_BCNT_Msk                      /*!< Byte count */
28237 #define USB_OTG_GRXSTSR_DPID_Pos                 (15U)
28238 #define USB_OTG_GRXSTSR_DPID_Msk                 (0x3U << USB_OTG_GRXSTSR_DPID_Pos)            /*!< 0x00018000 */
28239 #define USB_OTG_GRXSTSR_DPID                     USB_OTG_GRXSTSR_DPID_Msk                      /*!< Data PID */
28240 #define USB_OTG_GRXSTSR_PKTSTS_Pos               (17U)
28241 #define USB_OTG_GRXSTSR_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos)          /*!< 0x001E0000 */
28242 #define USB_OTG_GRXSTSR_PKTSTS                   USB_OTG_GRXSTSR_PKTSTS_Msk                    /*!< Packet status */
28243 #define USB_OTG_GRXSTSR_FRMNUM_Pos               (21U)
28244 #define USB_OTG_GRXSTSR_FRMNUM_Msk               (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos)          /*!< 0x01E00000 */
28245 #define USB_OTG_GRXSTSR_FRMNUM                   USB_OTG_GRXSTSR_FRMNUM_Msk                    /*!< Frame number */
28246 #define USB_OTG_GRXSTSR_STSPHST_Pos              (27U)
28247 #define USB_OTG_GRXSTSR_STSPHST_Msk              (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos)          /*!< 0x08000000 */
28248 #define USB_OTG_GRXSTSR_STSPHST                  USB_OTG_GRXSTSR_STSPHST_Msk                    /*!< Status phase start */
28249 
28250 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
28251 #define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos          (0U)
28252 #define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk          (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos)     /*!< 0x0000000F */
28253 #define USB_OTG_GRXSTSP_EPNUM_CHNUM              USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk               /*!< Endpoint/Channel number */
28254 #define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
28255 #define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos)          /*!< 0x00007FF0 */
28256 #define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk                      /*!< Byte count */
28257 #define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
28258 #define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos)            /*!< 0x00018000 */
28259 #define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk                      /*!< Data PID */
28260 #define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
28261 #define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos)          /*!< 0x001E0000 */
28262 #define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk                    /*!< Packet status */
28263 #define USB_OTG_GRXSTSP_FRMNUM_Pos               (21U)
28264 #define USB_OTG_GRXSTSP_FRMNUM_Msk               (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos)          /*!< 0x01E00000 */
28265 #define USB_OTG_GRXSTSP_FRMNUM                   USB_OTG_GRXSTSP_FRMNUM_Msk                    /*!< Frame number */
28266 #define USB_OTG_GRXSTSP_STSPHST_Pos              (27U)
28267 #define USB_OTG_GRXSTSP_STSPHST_Msk              (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos)          /*!< 0x08000000 */
28268 #define USB_OTG_GRXSTSP_STSPHST                  USB_OTG_GRXSTSP_STSPHST_Msk                    /*!< Status phase start */
28269 
28270 /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
28271 #define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
28272 #define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos)        /*!< 0x0000FFFF */
28273 #define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk                     /*!< IN EP interrupt mask bits */
28274 #define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
28275 #define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos)        /*!< 0xFFFF0000 */
28276 #define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk                     /*!< OUT EP interrupt mask bits */
28277 
28278 /********************  Bit definition for OTG register  ********************/
28279 #define USB_OTG_CHNUM_Pos                        (0U)
28280 #define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)                  /*!< 0x0000000F */
28281 #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk                            /*!< Channel number */
28282 #define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)                  /*!< 0x00000001 */
28283 #define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)                  /*!< 0x00000002 */
28284 #define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)                  /*!< 0x00000004 */
28285 #define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)                  /*!< 0x00000008 */
28286 #define USB_OTG_BCNT_Pos                         (4U)
28287 #define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)                 /*!< 0x00007FF0 */
28288 #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk                             /*!< Byte count */
28289 #define USB_OTG_DPID_Pos                         (15U)
28290 #define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)                   /*!< 0x00018000 */
28291 #define USB_OTG_DPID                             USB_OTG_DPID_Msk                             /*!< Data PID */
28292 #define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)                   /*!< 0x00008000 */
28293 #define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)                   /*!< 0x00010000 */
28294 #define USB_OTG_PKTSTS_Pos                       (17U)
28295 #define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)                 /*!< 0x001E0000 */
28296 #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk                           /*!< Packet status */
28297 #define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)                 /*!< 0x00020000 */
28298 #define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)                 /*!< 0x00040000 */
28299 #define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)                 /*!< 0x00080000 */
28300 #define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)                 /*!< 0x00100000 */
28301 #define USB_OTG_EPNUM_Pos                        (0U)
28302 #define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)                  /*!< 0x0000000F */
28303 #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk                            /*!< Endpoint number */
28304 #define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)                  /*!< 0x00000001 */
28305 #define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)                  /*!< 0x00000002 */
28306 #define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)                  /*!< 0x00000004 */
28307 #define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)                  /*!< 0x00000008 */
28308 #define USB_OTG_FRMNUM_Pos                       (21U)
28309 #define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)                 /*!< 0x01E00000 */
28310 #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk                           /*!< Frame number */
28311 #define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)                 /*!< 0x00200000 */
28312 #define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)                 /*!< 0x00400000 */
28313 #define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)                 /*!< 0x00800000 */
28314 #define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)                 /*!< 0x01000000 */
28315 
28316 /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
28317 #define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
28318 #define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos)        /*!< 0x0000FFFF */
28319 #define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk                     /*!< RxFIFO depth */
28320 
28321 /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
28322 #define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
28323 #define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos)     /*!< 0x0000FFFF */
28324 #define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk                  /*!< Device VBUS discharge time */
28325 
28326 /********************  Bit definition for OTG register  ********************/
28327 #define USB_OTG_NPTXFSA_Pos                      (0U)
28328 #define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos)             /*!< 0x0000FFFF */
28329 #define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk                          /*!< Nonperiodic transmit RAM start address */
28330 #define USB_OTG_NPTXFD_Pos                       (16U)
28331 #define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos)              /*!< 0xFFFF0000 */
28332 #define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk                           /*!< Nonperiodic TxFIFO depth */
28333 #define USB_OTG_TX0FSA_Pos                       (0U)
28334 #define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos)              /*!< 0x0000FFFF */
28335 #define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk                           /*!< Endpoint 0 transmit RAM start address */
28336 #define USB_OTG_TX0FD_Pos                        (16U)
28337 #define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos)               /*!< 0xFFFF0000 */
28338 #define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk                            /*!< Endpoint 0 TxFIFO depth */
28339 
28340 /********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
28341 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
28342 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos)    /*!< 0x00000FFF */
28343 #define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk                /*!< Device VBUS pulsing time */
28344 
28345 /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
28346 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
28347 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)   /*!< 0x0000FFFF */
28348 #define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk                /*!< Nonperiodic TxFIFO space available */
28349 
28350 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
28351 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00FF0000 */
28352 #define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk                /*!< Nonperiodic transmit request queue space available */
28353 #define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00010000 */
28354 #define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00020000 */
28355 #define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00040000 */
28356 #define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00080000 */
28357 #define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00100000 */
28358 #define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00200000 */
28359 #define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00400000 */
28360 #define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)     /*!< 0x00800000 */
28361 
28362 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
28363 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x7F000000 */
28364 #define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk                /*!< Top of the nonperiodic transmit request queue */
28365 #define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x01000000 */
28366 #define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x02000000 */
28367 #define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x04000000 */
28368 #define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x08000000 */
28369 #define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x10000000 */
28370 #define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x20000000 */
28371 #define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)     /*!< 0x40000000 */
28372 
28373 /********************  Bit definition for USB_OTG_DTHRCTL register  ***************/
28374 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
28375 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos)    /*!< 0x00000001 */
28376 #define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk              /*!< Nonisochronous IN endpoints threshold enable */
28377 #define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
28378 #define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos)       /*!< 0x00000002 */
28379 #define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk                 /*!< ISO IN endpoint threshold enable */
28380 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
28381 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x000007FC */
28382 #define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk                 /*!< Transmit threshold length */
28383 #define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000004 */
28384 #define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000008 */
28385 #define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000010 */
28386 #define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000020 */
28387 #define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000040 */
28388 #define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000080 */
28389 #define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000100 */
28390 #define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000200 */
28391 #define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos)     /*!< 0x00000400 */
28392 
28393 #define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
28394 #define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos)        /*!< 0x00010000 */
28395 #define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk                  /*!< Receive threshold enable */
28396 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
28397 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x03FE0000 */
28398 #define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk                 /*!< Receive threshold length */
28399 #define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00020000 */
28400 #define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00040000 */
28401 #define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00080000 */
28402 #define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00100000 */
28403 #define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00200000 */
28404 #define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00400000 */
28405 #define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x00800000 */
28406 #define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x01000000 */
28407 #define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos)     /*!< 0x02000000 */
28408 #define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
28409 #define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos)          /*!< 0x08000000 */
28410 #define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk                    /*!< Arbiter parking enable */
28411 
28412 /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ***************/
28413 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
28414 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
28415 #define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk              /*!< IN EP Tx FIFO empty interrupt mask bits */
28416 
28417 /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
28418 #define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
28419 #define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos)       /*!< 0x00000002 */
28420 #define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk                 /*!< IN endpoint 1interrupt bit */
28421 #define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
28422 #define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos)       /*!< 0x00020000 */
28423 #define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk                 /*!< OUT endpoint 1 interrupt bit */
28424 
28425 /********************  Bit definition for USB_OTG_GCCFG register  ********************/
28426 #define USB_OTG_GCCFG_CHGDET_Pos                 (0U)
28427 #define USB_OTG_GCCFG_CHGDET_Msk                 (0x1U << USB_OTG_GCCFG_CHGDET_Pos)           /*!< 0x00000001 */
28428 #define USB_OTG_GCCFG_CHGDET                     USB_OTG_GCCFG_CHGDET_Msk                     /*!< Battery Charger Detection */
28429 #define USB_OTG_GCCFG_FSVPLUS_Pos                (1U)
28430 #define USB_OTG_GCCFG_FSVPLUS_Msk                (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos)          /*!< 0x00000002 */
28431 #define USB_OTG_GCCFG_FSVPLUS                    USB_OTG_GCCFG_FSVPLUS_Msk                    /*!< Single-Ended DP2 indicator DP voltage level  */
28432 #define USB_OTG_GCCFG_FSVMINUS_Pos               (2U)
28433 #define USB_OTG_GCCFG_FSVMINUS_Msk               (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos)        /*!< 0x00000004 */
28434 #define USB_OTG_GCCFG_FSVMINUS                   USB_OTG_GCCFG_FSVMINUS_Msk                  /*!< Single-Ended DM2 indicator DM voltage level  */
28435 #define USB_OTG_GCCFG_SESSVLD_Pos                (3U)
28436 #define USB_OTG_GCCFG_SESSVLD_Msk                (0x1U << USB_OTG_GCCFG_SESSVLD_Pos)          /*!< 0x00000008 */
28437 #define USB_OTG_GCCFG_SESSVLD                    USB_OTG_GCCFG_SESSVLD_Msk                    /*!< VBUS session valid indicator Vbus voltage level  */
28438 #define USB_OTG_GCCFG_H_CDPEN_Pos                (16U)
28439 #define USB_OTG_GCCFG_H_CDPEN_Msk                (0x1U << USB_OTG_GCCFG_H_CDPEN_Pos)          /*!< 0x00010000 */
28440 #define USB_OTG_GCCFG_H_CDPEN                    USB_OTG_GCCFG_H_CDPEN_Msk                    /*!< VBUS session valid indicator Vbus voltage level  */
28441 #define USB_OTG_GCCFG_H_CDPDETEN_Pos             (17U)
28442 #define USB_OTG_GCCFG_H_CDPDETEN_Msk             (0x1U << USB_OTG_GCCFG_H_CDPDETEN_Pos)       /*!< 0x00020000 */
28443 #define USB_OTG_GCCFG_H_CDPDETEN                 USB_OTG_GCCFG_H_CDPDETEN_Msk                 /*!< Enable of voltage detector on DP for CDP port  */
28444 #define USB_OTG_GCCFG_H_VDMSRCEN_Pos             (18U)
28445 #define USB_OTG_GCCFG_H_VDMSRCEN_Msk             (0x1U << USB_OTG_GCCFG_H_VDMSRCEN_Pos)       /*!< 0x00040000 */
28446 #define USB_OTG_GCCFG_H_VDMSRCEN                 USB_OTG_GCCFG_H_VDMSRCEN_Msk                 /*!< Enable Voltage source on DM for CDP port */
28447 #define USB_OTG_GCCFG_DCDEN_Pos                  (19U)
28448 #define USB_OTG_GCCFG_DCDEN_Msk                  (0x1U << USB_OTG_GCCFG_DCDEN_Pos)            /*!< 0x00080000 */
28449 #define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk                      /*!< Data contact detection (DCD) mode enable */
28450 #define USB_OTG_GCCFG_PDEN_Pos                   (20U)
28451 #define USB_OTG_GCCFG_PDEN_Msk                   (0x1U << USB_OTG_GCCFG_PDEN_Pos)             /*!< 0x00080000 */
28452 #define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk                       /*!< Primary detection (PD) mode enable */
28453 #define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
28454 #define USB_OTG_GCCFG_VBDEN_Msk                  (0x1U << USB_OTG_GCCFG_VBDEN_Pos)            /*!< 0x00200000 */
28455 #define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk                      /*!< Vbus detection enable */
28456 #define USB_OTG_GCCFG_SDEN_Pos                   (22U)
28457 #define USB_OTG_GCCFG_SDEN_Msk                   (0x1U << USB_OTG_GCCFG_SDEN_Pos)             /*!< 0x00400000 */
28458 #define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk                       /*!< Secondary detection (PD) mode enable */
28459 #define USB_OTG_GCCFG_VBVALOVAL_Pos              (23U)
28460 #define USB_OTG_GCCFG_VBVALOVAL_Msk              (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos)        /*!< 0x00800000 */
28461 #define USB_OTG_GCCFG_VBVALOVAL                  USB_OTG_GCCFG_VBVALOVAL_Msk                  /*!< Value of VBUSVLDEXT0 PHY input */
28462 #define USB_OTG_GCCFG_VBVALEXTOEN_Pos            (24U)
28463 #define USB_OTG_GCCFG_VBVALEXTOEN_Msk            (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos)      /*!< 0x01000000 */
28464 #define USB_OTG_GCCFG_VBVALEXTOEN                USB_OTG_GCCFG_VBVALEXTOEN_Msk                /*!< Enables of VBUSVLDEXT0 PHY input override */
28465 #define USB_OTG_GCCFG_PULLDOWNEN_Pos             (25U)
28466 #define USB_OTG_GCCFG_PULLDOWNEN_Msk             (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos)       /*!< 0x02000000 */
28467 #define USB_OTG_GCCFG_PULLDOWNEN                 USB_OTG_GCCFG_PULLDOWNEN_Msk                 /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */
28468 
28469 /********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
28470 #define USB_OTG_GPWRDN_DISABLEVBUS_Pos           (6U)
28471 #define USB_OTG_GPWRDN_DISABLEVBUS_Msk           (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos)     /*!< 0x00000040 */
28472 #define USB_OTG_GPWRDN_DISABLEVBUS               USB_OTG_GPWRDN_DISABLEVBUS_Msk               /*!< Power down */
28473 
28474 /********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
28475 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
28476 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)   /*!< 0x00000002 */
28477 #define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk             /*!< IN Endpoint 1 interrupt mask bit */
28478 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
28479 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)   /*!< 0x00020000 */
28480 #define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk             /*!< OUT Endpoint 1 interrupt mask bit */
28481 
28482 /********************  Bit definition for USB_OTG_CID register  ********************/
28483 #define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
28484 #define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos)  /*!< 0xFFFFFFFF */
28485 #define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk                   /*!< Product ID field */
28486 
28487 /********************  Bit definition for USB_OTG_GHWCFG3 register  ********************/
28488 #define USB_OTG_GHWCFG3_LPMMode_Pos              (14U)
28489 #define USB_OTG_GHWCFG3_LPMMode_Msk              (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos)        /*!< 0x00004000 */
28490 #define USB_OTG_GHWCFG3_LPMMode                  USB_OTG_GHWCFG3_LPMMode_Msk                  /* LPM mode specified for Mode of Operation */
28491 
28492 /********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
28493 #define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
28494 #define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos)          /*!< 0x00000001 */
28495 #define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk                    /* LPM support enable  */
28496 #define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
28497 #define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos)         /*!< 0x00000002 */
28498 #define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk                   /* LPM Token acknowledge enable*/
28499 #define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
28500 #define USB_OTG_GLPMCFG_BESL_Msk                 (0xFU << USB_OTG_GLPMCFG_BESL_Pos)           /*!< 0x0000003C */
28501 #define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk                     /* BESL value received with last ACKed LPM Token  */
28502 #define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
28503 #define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos)        /*!< 0x00000040 */
28504 #define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk                  /* bRemoteWake value received with last ACKed LPM Token */
28505 #define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
28506 #define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos)         /*!< 0x00000080 */
28507 #define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk                   /* L1 shallow sleep enable */
28508 #define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
28509 #define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos)       /*!< 0x00000F00 */
28510 #define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk                 /* BESL threshold */
28511 #define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
28512 #define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos)         /*!< 0x00001000 */
28513 #define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk                   /* L1 deep sleep enable */
28514 #define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
28515 #define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos)         /*!< 0x00006000 */
28516 #define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk                   /* LPM response */
28517 #define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
28518 #define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos)         /*!< 0x00008000 */
28519 #define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk                   /* Port sleep status */
28520 #define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
28521 #define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos)        /*!< 0x00010000 */
28522 #define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk                  /* Sleep State Resume OK */
28523 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
28524 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos)       /*!< 0x001E0000 */
28525 #define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk                 /* LPMCHIDX: */
28526 #define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
28527 #define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos)        /*!< 0x00E00000 */
28528 #define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk                  /* LPM retry count */
28529 #define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
28530 #define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos)         /*!< 0x01000000 */
28531 #define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk                   /* Send LPM transaction */
28532 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
28533 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)     /*!< 0x0E000000 */
28534 #define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk               /* LPM retry count status */
28535 #define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
28536 #define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos)         /*!< 0x10000000 */
28537 #define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk                   /* Enable best effort service latency */
28538 
28539 /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
28540 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
28541 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)     /*!< 0x00000001 */
28542 #define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk               /*!< Transfer completed interrupt mask */
28543 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
28544 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos)      /*!< 0x00000002 */
28545 #define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk                /*!< Endpoint disabled interrupt mask */
28546 #define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
28547 #define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos)       /*!< 0x00000008 */
28548 #define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk                 /*!< Timeout condition mask (nonisochronous endpoints) */
28549 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
28550 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
28551 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk           /*!< IN token received when TxFIFO empty mask */
28552 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
28553 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)   /*!< 0x00000020 */
28554 #define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk             /*!< IN token received with EP mismatch mask */
28555 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
28556 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)   /*!< 0x00000040 */
28557 #define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk             /*!< IN endpoint NAK effective mask */
28558 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
28559 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)    /*!< 0x00000100 */
28560 #define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk              /*!< FIFO underrun mask */
28561 #define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
28562 #define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos)       /*!< 0x00000200 */
28563 #define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk                 /*!< BNA interrupt mask */
28564 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
28565 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos)      /*!< 0x00002000 */
28566 #define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk                /*!< NAK interrupt mask */
28567 
28568 /********************  Bit definition for USB_OTG_HPRT register  ********************/
28569 #define USB_OTG_HPRT_PCSTS_Pos                   (0U)
28570 #define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos)             /*!< 0x00000001 */
28571 #define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk                       /*!< Port connect status */
28572 #define USB_OTG_HPRT_PCDET_Pos                   (1U)
28573 #define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos)             /*!< 0x00000002 */
28574 #define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk                       /*!< Port connect detected */
28575 #define USB_OTG_HPRT_PENA_Pos                    (2U)
28576 #define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos)              /*!< 0x00000004 */
28577 #define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk                        /*!< Port enable */
28578 #define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
28579 #define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos)           /*!< 0x00000008 */
28580 #define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk                     /*!< Port enable/disable change */
28581 #define USB_OTG_HPRT_POCA_Pos                    (4U)
28582 #define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos)              /*!< 0x00000010 */
28583 #define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk                        /*!< Port overcurrent active */
28584 #define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
28585 #define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos)           /*!< 0x00000020 */
28586 #define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk                     /*!< Port overcurrent change */
28587 #define USB_OTG_HPRT_PRES_Pos                    (6U)
28588 #define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos)              /*!< 0x00000040 */
28589 #define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk                        /*!< Port resume */
28590 #define USB_OTG_HPRT_PSUSP_Pos                   (7U)
28591 #define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos)             /*!< 0x00000080 */
28592 #define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk                       /*!< Port suspend */
28593 #define USB_OTG_HPRT_PRST_Pos                    (8U)
28594 #define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos)              /*!< 0x00000100 */
28595 #define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk                        /*!< Port reset */
28596 #define USB_OTG_HPRT_PLSTS_Pos                   (10U)
28597 #define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos)             /*!< 0x00000C00 */
28598 #define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk                       /*!< Port line status */
28599 #define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos)             /*!< 0x00000400 */
28600 #define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos)             /*!< 0x00000800 */
28601 #define USB_OTG_HPRT_PPWR_Pos                    (12U)
28602 #define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos)              /*!< 0x00001000 */
28603 #define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk                        /*!< Port power */
28604 #define USB_OTG_HPRT_PTCTL_Pos                   (13U)
28605 #define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos)             /*!< 0x0001E000 */
28606 #define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk                       /*!< Port test control */
28607 #define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos)             /*!< 0x00002000 */
28608 #define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos)             /*!< 0x00004000 */
28609 #define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos)             /*!< 0x00008000 */
28610 #define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos)             /*!< 0x00010000 */
28611 #define USB_OTG_HPRT_PSPD_Pos                    (17U)
28612 #define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos)              /*!< 0x00060000 */
28613 #define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk                        /*!< Port speed */
28614 #define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos)              /*!< 0x00020000 */
28615 #define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos)              /*!< 0x00040000 */
28616 
28617 /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
28618 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
28619 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)     /*!< 0x00000001 */
28620 #define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk               /*!< Transfer completed interrupt mask */
28621 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
28622 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos)      /*!< 0x00000002 */
28623 #define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk                /*!< Endpoint disabled interrupt mask */
28624 #define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
28625 #define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos)       /*!< 0x00000008 */
28626 #define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk                 /*!< Timeout condition mask */
28627 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
28628 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
28629 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk           /*!< IN token received when TxFIFO empty mask */
28630 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
28631 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)   /*!< 0x00000020 */
28632 #define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk             /*!< IN token received with EP mismatch mask */
28633 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
28634 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)   /*!< 0x00000040 */
28635 #define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk             /*!< IN endpoint NAK effective mask */
28636 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
28637 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)    /*!< 0x00000100 */
28638 #define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk              /*!< OUT packet error mask */
28639 #define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
28640 #define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos)       /*!< 0x00000200 */
28641 #define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk                 /*!< BNA interrupt mask */
28642 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
28643 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos)     /*!< 0x00001000 */
28644 #define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk               /*!< Bubble error interrupt mask */
28645 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
28646 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos)      /*!< 0x00002000 */
28647 #define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk                /*!< NAK interrupt mask */
28648 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
28649 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos)     /*!< 0x00004000 */
28650 #define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk               /*!< NYET interrupt mask */
28651 
28652 /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
28653 #define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
28654 #define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos)      /*!< 0x0000FFFF */
28655 #define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk                   /*!< Host periodic TxFIFO start address */
28656 #define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos             (16U)
28657 #define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk             (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos)    /*!< 0xFFFF0000 */
28658 #define USB_OTG_HPTXFSIZ_PTXFSIZ                 USB_OTG_HPTXFSIZ_PTXFSIZ_Msk                 /*!< Host periodic TxFIFO depth */
28659 
28660 /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
28661 #define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
28662 #define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos)        /*!< 0x000007FF */
28663 #define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk                    /*!< Maximum packet size */
28664 #define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
28665 #define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos)         /*!< 0x00008000 */
28666 #define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk                   /*!< USB active endpoint */
28667 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
28668 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos)     /*!< 0x00010000 */
28669 #define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk               /*!< Even/odd frame */
28670 #define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
28671 #define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos)         /*!< 0x00020000 */
28672 #define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk                   /*!< NAK status */
28673 
28674 #define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
28675 #define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos)          /*!< 0x000C0000 */
28676 #define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk                    /*!< Endpoint type */
28677 #define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos)          /*!< 0x00040000 */
28678 #define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos)          /*!< 0x00080000 */
28679 #define USB_OTG_DIEPCTL_STALL_Pos                (21U)
28680 #define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos)          /*!< 0x00200000 */
28681 #define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk                    /*!< STALL handshake */
28682 
28683 #define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
28684 #define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos)         /*!< 0x03C00000 */
28685 #define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk                   /*!< TxFIFO number */
28686 #define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos)         /*!< 0x00400000 */
28687 #define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos)         /*!< 0x00800000 */
28688 #define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos)         /*!< 0x01000000 */
28689 #define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos)         /*!< 0x02000000 */
28690 #define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
28691 #define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos)           /*!< 0x04000000 */
28692 #define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk                     /*!< Clear NAK */
28693 #define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
28694 #define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos)           /*!< 0x08000000 */
28695 #define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk                     /*!< Set NAK */
28696 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
28697 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
28698 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk           /*!< Set DATA0 PID/Set even frame */
28699 #define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos       (29U)
28700 #define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */
28701 #define USB_OTG_DIEPCTL_SD1PID_SODDFRM           USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk           /*!< Set DATA1 PID/Set odd frame */
28702 #define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
28703 #define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos)          /*!< 0x40000000 */
28704 #define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk                    /*!< Endpoint disable */
28705 #define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
28706 #define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos)          /*!< 0x80000000 */
28707 #define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk                    /*!< Endpoint enable */
28708 
28709 /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
28710 #define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
28711 #define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos)         /*!< 0x000007FF */
28712 #define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk                     /*!< Maximum packet size */
28713 #define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
28714 #define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos)           /*!< 0x00007800 */
28715 #define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk                     /*!< Endpoint number */
28716 #define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos)           /*!< 0x00000800 */
28717 #define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos)           /*!< 0x00001000 */
28718 #define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos)           /*!< 0x00002000 */
28719 #define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos)           /*!< 0x00004000 */
28720 #define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
28721 #define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos)           /*!< 0x00008000 */
28722 #define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk                     /*!< Endpoint direction */
28723 #define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
28724 #define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos)           /*!< 0x00020000 */
28725 #define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk                     /*!< Low-speed device */
28726 #define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
28727 #define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos)           /*!< 0x000C0000 */
28728 #define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk                     /*!< Endpoint type */
28729 #define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos)           /*!< 0x00040000 */
28730 #define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos)           /*!< 0x00080000 */
28731 #define USB_OTG_HCCHAR_MCNT_Pos                  (20U)
28732 #define USB_OTG_HCCHAR_MCNT_Msk                  (0x3U << USB_OTG_HCCHAR_MCNT_Pos)            /*!< 0x00300000 */
28733 #define USB_OTG_HCCHAR_MCNT                      USB_OTG_HCCHAR_MCNT_Msk                      /*!< Multi Count (MC) / Error Count (EC) */
28734 #define USB_OTG_HCCHAR_MCNT_0                    (0x1U << USB_OTG_HCCHAR_MCNT_Pos)            /*!< 0x00100000 */
28735 #define USB_OTG_HCCHAR_MCNT_1                    (0x2U << USB_OTG_HCCHAR_MCNT_Pos)            /*!< 0x00200000 */
28736 #define USB_OTG_HCCHAR_DAD_Pos                   (22U)
28737 #define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x1FC00000 */
28738 #define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk                       /*!< Device address */
28739 #define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x00400000 */
28740 #define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x00800000 */
28741 #define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x01000000 */
28742 #define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x02000000 */
28743 #define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x04000000 */
28744 #define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x08000000 */
28745 #define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos)            /*!< 0x10000000 */
28746 #define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
28747 #define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos)          /*!< 0x20000000 */
28748 #define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk                    /*!< Odd frame */
28749 #define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
28750 #define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos)           /*!< 0x40000000 */
28751 #define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk                     /*!< Channel disable */
28752 #define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
28753 #define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos)           /*!< 0x80000000 */
28754 #define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk                     /*!< Channel enable */
28755 
28756 /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
28757 #define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
28758 #define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x0000007F */
28759 #define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk                   /*!< Port address */
28760 #define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000001 */
28761 #define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000002 */
28762 #define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000004 */
28763 #define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000008 */
28764 #define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000010 */
28765 #define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000020 */
28766 #define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos)        /*!< 0x00000040 */
28767 
28768 #define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
28769 #define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00003F80 */
28770 #define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk                   /*!< Hub address */
28771 #define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00000080 */
28772 #define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00000100 */
28773 #define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00000200 */
28774 #define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00000400 */
28775 #define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00000800 */
28776 #define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00001000 */
28777 #define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos)        /*!< 0x00002000 */
28778 
28779 #define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
28780 #define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos)         /*!< 0x0000C000 */
28781 #define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk                   /*!< XACTPOS */
28782 #define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos)         /*!< 0x00004000 */
28783 #define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos)         /*!< 0x00008000 */
28784 #define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
28785 #define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos)       /*!< 0x00010000 */
28786 #define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk                 /*!< Do complete split */
28787 #define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
28788 #define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos)         /*!< 0x80000000 */
28789 #define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk                   /*!< Split enable */
28790 
28791 /********************  Bit definition for USB_OTG_HCINT register  ********************/
28792 #define USB_OTG_HCINT_XFRC_Pos                   (0U)
28793 #define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos)             /*!< 0x00000001 */
28794 #define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk                       /*!< Transfer completed */
28795 #define USB_OTG_HCINT_CHH_Pos                    (1U)
28796 #define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos)              /*!< 0x00000002 */
28797 #define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk                        /*!< Channel halted */
28798 #define USB_OTG_HCINT_AHBERR_Pos                 (2U)
28799 #define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos)           /*!< 0x00000004 */
28800 #define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk                     /*!< AHB error */
28801 #define USB_OTG_HCINT_STALL_Pos                  (3U)
28802 #define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos)            /*!< 0x00000008 */
28803 #define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk                      /*!< STALL response received interrupt */
28804 #define USB_OTG_HCINT_NAK_Pos                    (4U)
28805 #define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos)              /*!< 0x00000010 */
28806 #define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk                        /*!< NAK response received interrupt */
28807 #define USB_OTG_HCINT_ACK_Pos                    (5U)
28808 #define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos)              /*!< 0x00000020 */
28809 #define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk                        /*!< ACK response received/transmitted interrupt */
28810 #define USB_OTG_HCINT_NYET_Pos                   (6U)
28811 #define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos)             /*!< 0x00000040 */
28812 #define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk                       /*!< Response received interrupt */
28813 #define USB_OTG_HCINT_TXERR_Pos                  (7U)
28814 #define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos)            /*!< 0x00000080 */
28815 #define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk                      /*!< Transaction error */
28816 #define USB_OTG_HCINT_BBERR_Pos                  (8U)
28817 #define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos)            /*!< 0x00000100 */
28818 #define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk                      /*!< Babble error */
28819 #define USB_OTG_HCINT_FRMOR_Pos                  (9U)
28820 #define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos)            /*!< 0x00000200 */
28821 #define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk                      /*!< Frame overrun */
28822 #define USB_OTG_HCINT_DTERR_Pos                  (10U)
28823 #define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos)            /*!< 0x00000400 */
28824 #define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk                      /*!< Data toggle error */
28825 
28826 /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
28827 #define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
28828 #define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos)           /*!< 0x00000001 */
28829 #define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk                     /*!< Transfer completed interrupt */
28830 #define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
28831 #define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos)         /*!< 0x00000002 */
28832 #define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk                   /*!< Endpoint disabled interrupt */
28833 #define USB_OTG_DIEPINT_TOC_Pos                  (3U)
28834 #define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos)            /*!< 0x00000008 */
28835 #define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk                      /*!< Timeout condition */
28836 #define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
28837 #define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos)         /*!< 0x00000010 */
28838 #define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk                   /*!< IN token received when TxFIFO is empty */
28839 #define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
28840 #define USB_OTG_DIEPINT_INEPNM_Msk               (0x1U << USB_OTG_DIEPINT_INEPNM_Pos)         /*!< 0x00000020 */
28841 #define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk                   /*!< IN token received with EP mismatch */
28842 #define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
28843 #define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos)         /*!< 0x00000040 */
28844 #define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk                   /*!< IN endpoint NAK effective */
28845 #define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
28846 #define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos)           /*!< 0x00000080 */
28847 #define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk                     /*!< Transmit FIFO empty */
28848 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
28849 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)     /*!< 0x00000100 */
28850 #define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk               /*!< Transmit Fifo Underrun */
28851 #define USB_OTG_DIEPINT_BNA_Pos                  (9U)
28852 #define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos)            /*!< 0x00000200 */
28853 #define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk                      /*!< Buffer not available interrupt */
28854 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
28855 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos)      /*!< 0x00000800 */
28856 #define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk                /*!< Packet dropped status */
28857 #define USB_OTG_DIEPINT_BERR_Pos                 (12U)
28858 #define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos)           /*!< 0x00001000 */
28859 #define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk                     /*!< Babble error interrupt */
28860 #define USB_OTG_DIEPINT_NAK_Pos                  (13U)
28861 #define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos)            /*!< 0x00002000 */
28862 #define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk                      /*!< NAK interrupt */
28863 
28864 /********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
28865 #define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
28866 #define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos)         /*!< 0x00000001 */
28867 #define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk                   /*!< Transfer completed mask */
28868 #define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
28869 #define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos)          /*!< 0x00000002 */
28870 #define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk                    /*!< Channel halted mask */
28871 #define USB_OTG_HCINTMSK_AHBERRM_Pos             (2U)
28872 #define USB_OTG_HCINTMSK_AHBERRM_Msk             (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos)       /*!< 0x00000004 */
28873 #define USB_OTG_HCINTMSK_AHBERRM                 USB_OTG_HCINTMSK_AHBERRM_Msk                 /*!< AHB error */
28874 #define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
28875 #define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos)        /*!< 0x00000008 */
28876 #define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk                  /*!< STALL response received interrupt mask */
28877 #define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
28878 #define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos)          /*!< 0x00000010 */
28879 #define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk                    /*!< NAK response received interrupt mask */
28880 #define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
28881 #define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos)          /*!< 0x00000020 */
28882 #define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk                    /*!< ACK response received/transmitted interrupt mask */
28883 #define USB_OTG_HCINTMSK_NYET_Pos                (6U)
28884 #define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos)          /*!< 0x00000040 */
28885 #define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk                    /*!< response received interrupt mask */
28886 #define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
28887 #define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos)        /*!< 0x00000080 */
28888 #define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk                  /*!< Transaction error mask */
28889 #define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
28890 #define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos)        /*!< 0x00000100 */
28891 #define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk                  /*!< Babble error mask */
28892 #define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
28893 #define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos)        /*!< 0x00000200 */
28894 #define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk                  /*!< Frame overrun mask */
28895 #define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
28896 #define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos)        /*!< 0x00000400 */
28897 #define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk                  /*!< Data toggle error mask */
28898 
28899 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
28900 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
28901 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)    /*!< 0x0007FFFF */
28902 #define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk                  /*!< Transfer size */
28903 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
28904 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos)      /*!< 0x1FF80000 */
28905 #define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk                  /*!< Packet count */
28906 #define USB_OTG_DIEPTSIZ_MCNT_Pos                (29U)
28907 #define USB_OTG_DIEPTSIZ_MCNT_Msk                (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos)          /*!< 0x60000000 */
28908 #define USB_OTG_DIEPTSIZ_MCNT                    USB_OTG_DIEPTSIZ_MCNT_Msk                    /*!< Multi count */
28909 
28910 /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
28911 #define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
28912 #define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos)      /*!< 0x0007FFFF */
28913 #define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk                    /*!< Transfer size */
28914 #define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
28915 #define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos)        /*!< 0x1FF80000 */
28916 #define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk                    /*!< Packet count */
28917 #define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
28918 #define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos)            /*!< 0x60000000 */
28919 #define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk                      /*!< Data PID */
28920 #define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos)            /*!< 0x20000000 */
28921 #define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos)            /*!< 0x40000000 */
28922 #define USB_OTG_HCTSIZ_DOPNG_Pos                 (31U)
28923 #define USB_OTG_HCTSIZ_DOPNG_Msk                 (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos)           /*!< 0x80000000 */
28924 #define USB_OTG_HCTSIZ_DOPNG                     USB_OTG_HCTSIZ_DOPNG_Msk                     /*!< Do PING */
28925 
28926 /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
28927 #define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
28928 #define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
28929 #define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk                  /*!< DMA address */
28930 
28931 /********************  Bit definition for USB_OTG_HCDMA register  ********************/
28932 #define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
28933 #define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos)   /*!< 0xFFFFFFFF */
28934 #define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk                    /*!< DMA address */
28935 
28936 /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
28937 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
28938 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos)   /*!< 0x0000FFFF */
28939 #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk                /*!< IN endpoint TxFIFO space avail */
28940 
28941 /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
28942 #define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
28943 #define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos)    /*!< 0x0000FFFF */
28944 #define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk                 /*!< IN endpoint FIFOx transmit RAM start address */
28945 #define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
28946 #define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos)    /*!< 0xFFFF0000 */
28947 #define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk                 /*!< IN endpoint TxFIFO depth */
28948 
28949 /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
28950 #define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
28951 #define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos)        /*!< 0x000007FF */
28952 #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk                    /*!< Maximum packet size */
28953 #define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
28954 #define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos)         /*!< 0x00008000 */
28955 #define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk                   /*!< USB active endpoint */
28956 #define USB_OTG_DOEPCTL_DPID_EONUM_Pos           (16U)
28957 #define USB_OTG_DOEPCTL_DPID_EONUM_Msk           (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos)     /*!< 0x00010000 */
28958 #define USB_OTG_DOEPCTL_DPID_EONUM               USB_OTG_DOEPCTL_DPID_EONUM_Msk               /*!< Endpoint data PID */
28959 #define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
28960 #define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos)         /*!< 0x00020000 */
28961 #define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk                   /*!< NAK status */
28962 #define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
28963 #define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos)          /*!< 0x000C0000 */
28964 #define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk                    /*!< Endpoint type */
28965 #define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos)          /*!< 0x00040000 */
28966 #define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos)          /*!< 0x00080000 */
28967 #define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
28968 #define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos)           /*!< 0x00100000 */
28969 #define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk                     /*!< Snoop mode */
28970 #define USB_OTG_DOEPCTL_STALL_Pos                (21U)
28971 #define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos)          /*!< 0x00200000 */
28972 #define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk                    /*!< STALL handshake */
28973 #define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
28974 #define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos)           /*!< 0x04000000 */
28975 #define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk                     /*!< Clear NAK */
28976 #define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
28977 #define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos)           /*!< 0x08000000 */
28978 #define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk                     /*!< Set NAK */
28979 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
28980 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
28981 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk           /*!< Set DATA0 PID/Set even frame */
28982 #define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos       (29U)
28983 #define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */
28984 #define USB_OTG_DOEPCTL_SD1PID_SODDFRM           USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk           /*!< Set DATA1 PID/Set odd frame */
28985 #define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
28986 #define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos)          /*!< 0x40000000 */
28987 #define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk                    /*!< Endpoint disable */
28988 #define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
28989 #define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos)          /*!< 0x80000000 */
28990 #define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk                    /*!< Endpoint enable */
28991 
28992 /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
28993 #define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
28994 #define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos)           /*!< 0x00000001 */
28995 #define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk                     /*!< Transfer completed interrupt */
28996 #define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
28997 #define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos)         /*!< 0x00000002 */
28998 #define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk                   /*!< Endpoint disabled interrupt */
28999 #define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
29000 #define USB_OTG_DOEPINT_AHBERR_Msk               (0x1U << USB_OTG_DOEPINT_AHBERR_Pos)         /*!< 0x00000004 */
29001 #define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk                   /*!< AHB error */
29002 #define USB_OTG_DOEPINT_STUP_Pos                 (3U)
29003 #define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos)           /*!< 0x00000008 */
29004 #define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk                     /*!< SETUP phase done */
29005 #define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
29006 #define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos)        /*!< 0x00000010 */
29007 #define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk                  /*!< OUT token received when endpoint disabled */
29008 #define USB_OTG_DOEPINT_STSPHSRX_Pos             (5U)
29009 #define USB_OTG_DOEPINT_STSPHSRX_Msk             (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos)        /*!< 0x00000010 */
29010 #define USB_OTG_DOEPINT_STSPHSRX                 USB_OTG_DOEPINT_STSPHSRX_Msk                  /*!< OUT token received when endpoint disabled */
29011 #define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
29012 #define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos)        /*!< 0x00000040 */
29013 #define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk                  /*!< Back-to-back SETUP packets received */
29014 #define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
29015 #define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos)      /*!< 0x00000100 */
29016 #define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk                /*!< OUT packet error */
29017 #define USB_OTG_DOEPINT_BERR_Pos                 (12U)
29018 #define USB_OTG_DOEPINT_BERR_Msk                 (0x1U << USB_OTG_DOEPINT_BERR_Pos)           /*!< 0x00001000 */
29019 #define USB_OTG_DOEPINT_BERR                     USB_OTG_DOEPINT_BERR_Msk                     /*!< Babble error interrupt */
29020 #define USB_OTG_DOEPINT_NAK_Pos                  (13U)
29021 #define USB_OTG_DOEPINT_NAK_Msk                  (0x1U << USB_OTG_DOEPINT_NAK_Pos)            /*!< 0x00002000 */
29022 #define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk                      /*!< NAK input */
29023 #define USB_OTG_DOEPINT_NYET_Pos                 (14U)
29024 #define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos)           /*!< 0x00004000 */
29025 #define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk                     /*!< NYET interrupt */
29026 #define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
29027 #define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos)        /*!< 0x00008000 */
29028 #define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk                  /*!< Setup packet received */
29029 
29030 /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
29031 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
29032 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)    /*!< 0x0007FFFF */
29033 #define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk                  /*!< Transfer size */
29034 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
29035 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos)      /*!< 0x1FF80000 */
29036 #define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk                  /*!< Packet count */
29037 
29038 #define USB_OTG_DOEPTSIZ_RXDPID_Pos             (29U)
29039 #define USB_OTG_DOEPTSIZ_RXDPID_Msk             (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos)         /*!< 0x60000000 */
29040 #define USB_OTG_DOEPTSIZ_RXDPID                 USB_OTG_DOEPTSIZ_RXDPID_Msk                   /*!< SETUP packet count */
29041 #define USB_OTG_DOEPTSIZ_RXDPID_0               (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos)         /*!< 0x20000000 */
29042 #define USB_OTG_DOEPTSIZ_RXDPID_1               (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos)         /*!< 0x40000000 */
29043 
29044 /********************  Bit definition for PCGCCTL register  ********************/
29045 #define USB_OTG_PCGCCTL_STPPCLK_Pos              (0U)
29046 #define USB_OTG_PCGCCTL_STPPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STPPCLK_Pos)        /*!< 0x00000001 */
29047 #define USB_OTG_PCGCCTL_STPPCLK                  USB_OTG_PCGCCTL_STPPCLK_Msk                  /*!< SETUP packet count */
29048 #define USB_OTG_PCGCCTL_GATEHCLK_Pos             (1U)
29049 #define USB_OTG_PCGCCTL_GATEHCLK_Msk             (0x1U << USB_OTG_PCGCCTL_GATEHCLK_Pos)       /*!< 0x00000002 */
29050 #define USB_OTG_PCGCCTL_GATEHCLK                 USB_OTG_PCGCCTL_GATEHCLK_Msk                 /*!< Gate HCLK */
29051 #define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
29052 #define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos)        /*!< 0x00000010 */
29053 #define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk                  /*!< PHY suspended */
29054 #define USB_OTG_PCGCCTL_ENL1GTG_Pos              (5U)
29055 #define USB_OTG_PCGCCTL_ENL1GTG_Msk              (0x1U << USB_OTG_PCGCCTL_ENL1GTG_Pos)        /*!< 0x00000020 */
29056 #define USB_OTG_PCGCCTL_ENL1GTG                  USB_OTG_PCGCCTL_ENL1GTG_Msk                  /*!< Enable sleep clock gating */
29057 #define USB_OTG_PCGCCTL_PHYSLEEP_Pos             (6U)
29058 #define USB_OTG_PCGCCTL_PHYSLEEP_Msk             (0x1U << USB_OTG_PCGCCTL_PHYSLEEP_Pos)       /*!< 0x00000040 */
29059 #define USB_OTG_PCGCCTL_PHYSLEEP                 USB_OTG_PCGCCTL_PHYSLEEP_Msk                 /*!< PHY in Sleep */
29060 #define USB_OTG_PCGCCTL_SUSP_Pos                 (7U)
29061 #define USB_OTG_PCGCCTL_SUSP_Msk                 (0x1U << USB_OTG_PCGCCTL_SUSP_Pos)           /*!< 0x00000080 */
29062 #define USB_OTG_PCGCCTL_SUSP                     USB_OTG_PCGCCTL_SUSP_Msk                     /*!< Deep Sleep */
29063 
29064 
29065 /******************************************************************************/
29066 /*                                                                            */
29067 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
29068 /*                                                                            */
29069 /******************************************************************************/
29070 /******************  Bit definition for USART_CR1 register  *******************/
29071 #define USART_CR1_UE_Pos                    (0U)
29072 #define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)             /*!< 0x00000001 */
29073 #define USART_CR1_UE                        USART_CR1_UE_Msk                        /*!< USART Enable */
29074 #define USART_CR1_UESM_Pos                  (1U)
29075 #define USART_CR1_UESM_Msk                  (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
29076 #define USART_CR1_UESM                      USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
29077 #define USART_CR1_RE_Pos                    (2U)
29078 #define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
29079 #define USART_CR1_RE                        USART_CR1_RE_Msk                        /*!< Receiver Enable */
29080 #define USART_CR1_TE_Pos                    (3U)
29081 #define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
29082 #define USART_CR1_TE                        USART_CR1_TE_Msk                        /*!< Transmitter Enable */
29083 #define USART_CR1_IDLEIE_Pos                (4U)
29084 #define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
29085 #define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
29086 #define USART_CR1_RXNEIE_Pos                (5U)
29087 #define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
29088 #define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
29089 #define USART_CR1_RXNEIE_RXFNEIE_Pos        USART_CR1_RXNEIE_Pos
29090 #define USART_CR1_RXNEIE_RXFNEIE_Msk        USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
29091 #define USART_CR1_RXNEIE_RXFNEIE            USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
29092 #define USART_CR1_TCIE_Pos                  (6U)
29093 #define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
29094 #define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
29095 #define USART_CR1_TXEIE_Pos                 (7U)
29096 #define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
29097 #define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
29098 #define USART_CR1_TXEIE_TXFNFIE_Pos         (7U)
29099 #define USART_CR1_TXEIE_TXFNFIE_Msk         (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
29100 #define USART_CR1_TXEIE_TXFNFIE             USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
29101 #define USART_CR1_PEIE_Pos                  (8U)
29102 #define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
29103 #define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
29104 #define USART_CR1_PS_Pos                    (9U)
29105 #define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
29106 #define USART_CR1_PS                        USART_CR1_PS_Msk                        /*!< Parity Selection */
29107 #define USART_CR1_PCE_Pos                   (10U)
29108 #define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
29109 #define USART_CR1_PCE                       USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
29110 #define USART_CR1_WAKE_Pos                  (11U)
29111 #define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
29112 #define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
29113 #define USART_CR1_M_Pos                     (12U)
29114 #define USART_CR1_M_Msk                     (0x10001UL << USART_CR1_M_Pos)          /*!< 0x10001000 */
29115 #define USART_CR1_M                         USART_CR1_M_Msk                         /*!< Word length */
29116 #define USART_CR1_M0_Pos                    (12U)
29117 #define USART_CR1_M0_Msk                    (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
29118 #define USART_CR1_M0                        USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
29119 #define USART_CR1_MME_Pos                   (13U)
29120 #define USART_CR1_MME_Msk                   (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
29121 #define USART_CR1_MME                       USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
29122 #define USART_CR1_CMIE_Pos                  (14U)
29123 #define USART_CR1_CMIE_Msk                  (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
29124 #define USART_CR1_CMIE                      USART_CR1_CMIE_Msk                      /*!< Character match interrupt enable */
29125 #define USART_CR1_OVER8_Pos                 (15U)
29126 #define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
29127 #define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
29128 #define USART_CR1_DEDT_Pos                  (16U)
29129 #define USART_CR1_DEDT_Msk                  (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
29130 #define USART_CR1_DEDT                      USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
29131 #define USART_CR1_DEDT_0                    (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
29132 #define USART_CR1_DEDT_1                    (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
29133 #define USART_CR1_DEDT_2                    (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
29134 #define USART_CR1_DEDT_3                    (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
29135 #define USART_CR1_DEDT_4                    (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
29136 #define USART_CR1_DEAT_Pos                  (21U)
29137 #define USART_CR1_DEAT_Msk                  (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
29138 #define USART_CR1_DEAT                      USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
29139 #define USART_CR1_DEAT_0                    (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
29140 #define USART_CR1_DEAT_1                    (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
29141 #define USART_CR1_DEAT_2                    (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
29142 #define USART_CR1_DEAT_3                    (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
29143 #define USART_CR1_DEAT_4                    (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
29144 #define USART_CR1_RTOIE_Pos                 (26U)
29145 #define USART_CR1_RTOIE_Msk                 (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
29146 #define USART_CR1_RTOIE                     USART_CR1_RTOIE_Msk                     /*!< Receive Time Out interrupt enable */
29147 #define USART_CR1_EOBIE_Pos                 (27U)
29148 #define USART_CR1_EOBIE_Msk                 (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
29149 #define USART_CR1_EOBIE                     USART_CR1_EOBIE_Msk                     /*!< End of Block interrupt enable */
29150 #define USART_CR1_M1_Pos                    (28U)
29151 #define USART_CR1_M1_Msk                    (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
29152 #define USART_CR1_M1                        USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
29153 #define USART_CR1_FIFOEN_Pos                (29U)
29154 #define USART_CR1_FIFOEN_Msk                (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
29155 #define USART_CR1_FIFOEN                    USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
29156 #define USART_CR1_TXFEIE_Pos                (30U)
29157 #define USART_CR1_TXFEIE_Msk                (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
29158 #define USART_CR1_TXFEIE                    USART_CR1_TXFEIE_Msk                    /*!< TXFIFO empty interrupt enable */
29159 #define USART_CR1_RXFFIE_Pos                (31U)
29160 #define USART_CR1_RXFFIE_Msk                (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
29161 #define USART_CR1_RXFFIE                    USART_CR1_RXFFIE_Msk                    /*!< RXFIFO Full interrupt enable */
29162 
29163 /******************  Bit definition for USART_CR2 register  *******************/
29164 #define USART_CR2_SLVEN_Pos                 (0U)
29165 #define USART_CR2_SLVEN_Msk                 (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
29166 #define USART_CR2_SLVEN                     USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
29167 #define USART_CR2_DIS_NSS_Pos               (3U)
29168 #define USART_CR2_DIS_NSS_Msk               (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
29169 #define USART_CR2_DIS_NSS                   USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
29170 #define USART_CR2_ADDM7_Pos                 (4U)
29171 #define USART_CR2_ADDM7_Msk                 (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
29172 #define USART_CR2_ADDM7                     USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
29173 #define USART_CR2_LBDL_Pos                  (5U)
29174 #define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
29175 #define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
29176 #define USART_CR2_LBDIE_Pos                 (6U)
29177 #define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
29178 #define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
29179 #define USART_CR2_LBCL_Pos                  (8U)
29180 #define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
29181 #define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
29182 #define USART_CR2_CPHA_Pos                  (9U)
29183 #define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
29184 #define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                      /*!< Clock Phase */
29185 #define USART_CR2_CPOL_Pos                  (10U)
29186 #define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
29187 #define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
29188 #define USART_CR2_CLKEN_Pos                 (11U)
29189 #define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
29190 #define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
29191 #define USART_CR2_STOP_Pos                  (12U)
29192 #define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
29193 #define USART_CR2_STOP                      USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
29194 #define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
29195 #define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
29196 #define USART_CR2_LINEN_Pos                 (14U)
29197 #define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
29198 #define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
29199 #define USART_CR2_SWAP_Pos                  (15U)
29200 #define USART_CR2_SWAP_Msk                  (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
29201 #define USART_CR2_SWAP                      USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
29202 #define USART_CR2_RXINV_Pos                 (16U)
29203 #define USART_CR2_RXINV_Msk                 (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
29204 #define USART_CR2_RXINV                     USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
29205 #define USART_CR2_TXINV_Pos                 (17U)
29206 #define USART_CR2_TXINV_Msk                 (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
29207 #define USART_CR2_TXINV                     USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
29208 #define USART_CR2_DATAINV_Pos               (18U)
29209 #define USART_CR2_DATAINV_Msk               (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
29210 #define USART_CR2_DATAINV                   USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
29211 #define USART_CR2_MSBFIRST_Pos              (19U)
29212 #define USART_CR2_MSBFIRST_Msk              (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
29213 #define USART_CR2_MSBFIRST                  USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
29214 #define USART_CR2_ABREN_Pos                 (20U)
29215 #define USART_CR2_ABREN_Msk                 (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
29216 #define USART_CR2_ABREN                     USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
29217 #define USART_CR2_ABRMODE_Pos               (21U)
29218 #define USART_CR2_ABRMODE_Msk               (0x3UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00600000 */
29219 #define USART_CR2_ABRMODE                   USART_CR2_ABRMODE_Msk                   /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
29220 #define USART_CR2_ABRMODE_0                 (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
29221 #define USART_CR2_ABRMODE_1                 (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
29222 #define USART_CR2_RTOEN_Pos                 (23U)
29223 #define USART_CR2_RTOEN_Msk                 (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
29224 #define USART_CR2_RTOEN                     USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
29225 #define USART_CR2_ADD_Pos                   (24U)
29226 #define USART_CR2_ADD_Msk                   (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
29227 #define USART_CR2_ADD                       USART_CR2_ADD_Msk                       /*!< Address of the USART node */
29228 
29229 /******************  Bit definition for USART_CR3 register  *******************/
29230 #define USART_CR3_EIE_Pos                   (0U)
29231 #define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
29232 #define USART_CR3_EIE                       USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
29233 #define USART_CR3_IREN_Pos                  (1U)
29234 #define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
29235 #define USART_CR3_IREN                      USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
29236 #define USART_CR3_IRLP_Pos                  (2U)
29237 #define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
29238 #define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
29239 #define USART_CR3_HDSEL_Pos                 (3U)
29240 #define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
29241 #define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
29242 #define USART_CR3_NACK_Pos                  (4U)
29243 #define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
29244 #define USART_CR3_NACK                      USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
29245 #define USART_CR3_SCEN_Pos                  (5U)
29246 #define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
29247 #define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
29248 #define USART_CR3_DMAR_Pos                  (6U)
29249 #define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
29250 #define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
29251 #define USART_CR3_DMAT_Pos                  (7U)
29252 #define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
29253 #define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
29254 #define USART_CR3_RTSE_Pos                  (8U)
29255 #define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
29256 #define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                      /*!< RTS Enable */
29257 #define USART_CR3_CTSE_Pos                  (9U)
29258 #define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
29259 #define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                      /*!< CTS Enable */
29260 #define USART_CR3_CTSIE_Pos                 (10U)
29261 #define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
29262 #define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
29263 #define USART_CR3_ONEBIT_Pos                (11U)
29264 #define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
29265 #define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
29266 #define USART_CR3_OVRDIS_Pos                (12U)
29267 #define USART_CR3_OVRDIS_Msk                (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
29268 #define USART_CR3_OVRDIS                    USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
29269 #define USART_CR3_DDRE_Pos                  (13U)
29270 #define USART_CR3_DDRE_Msk                  (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
29271 #define USART_CR3_DDRE                      USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
29272 #define USART_CR3_DEM_Pos                   (14U)
29273 #define USART_CR3_DEM_Msk                   (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
29274 #define USART_CR3_DEM                       USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
29275 #define USART_CR3_DEP_Pos                   (15U)
29276 #define USART_CR3_DEP_Msk                   (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
29277 #define USART_CR3_DEP                       USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
29278 #define USART_CR3_SCARCNT_Pos               (17U)
29279 #define USART_CR3_SCARCNT_Msk               (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
29280 #define USART_CR3_SCARCNT                   USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
29281 #define USART_CR3_SCARCNT_0                 (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
29282 #define USART_CR3_SCARCNT_1                 (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
29283 #define USART_CR3_SCARCNT_2                 (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
29284 #define USART_CR3_TXFTIE_Pos                (23U)
29285 #define USART_CR3_TXFTIE_Msk                (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
29286 #define USART_CR3_TXFTIE                    USART_CR3_TXFTIE_Msk                    /*!< TXFIFO threshold interrupt enable */
29287 #define USART_CR3_TCBGTIE_Pos               (24U)
29288 #define USART_CR3_TCBGTIE_Msk               (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
29289 #define USART_CR3_TCBGTIE                   USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
29290 #define USART_CR3_RXFTCFG_Pos               (25U)
29291 #define USART_CR3_RXFTCFG_Msk               (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
29292 #define USART_CR3_RXFTCFG                   USART_CR3_RXFTCFG_Msk                   /*!< RXFIFO FIFO threshold configuration */
29293 #define USART_CR3_RXFTCFG_0                 (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
29294 #define USART_CR3_RXFTCFG_1                 (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
29295 #define USART_CR3_RXFTCFG_2                 (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
29296 #define USART_CR3_RXFTIE_Pos                (28U)
29297 #define USART_CR3_RXFTIE_Msk                (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
29298 #define USART_CR3_RXFTIE                    USART_CR3_RXFTIE_Msk                    /*!< RXFIFO threshold interrupt enable */
29299 #define USART_CR3_TXFTCFG_Pos               (29U)
29300 #define USART_CR3_TXFTCFG_Msk               (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
29301 #define USART_CR3_TXFTCFG                   USART_CR3_TXFTCFG_Msk                   /*!< TXFIFO threshold configuration */
29302 #define USART_CR3_TXFTCFG_0                 (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
29303 #define USART_CR3_TXFTCFG_1                 (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
29304 #define USART_CR3_TXFTCFG_2                 (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
29305 
29306 /******************  Bit definition for USART_BRR register  *******************/
29307 #define USART_BRR_LPUART_Pos                (0U)
29308 #define USART_BRR_LPUART_Msk                (0xFFFFFUL << USART_BRR_LPUART_Pos)     /*!< 0x000FFFFF */
29309 #define USART_BRR_LPUART                    USART_BRR_LPUART_Msk                    /*!< LPUART Baud rate register [19:0] */
29310 #define USART_BRR_BRR                       ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */
29311 
29312 /******************  Bit definition for USART_GTPR register  ******************/
29313 #define USART_GTPR_PSC_Pos                  (0U)
29314 #define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
29315 #define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
29316 #define USART_GTPR_GT_Pos                   (8U)
29317 #define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
29318 #define USART_GTPR_GT                       USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */
29319 
29320 /*******************  Bit definition for USART_RTOR register  *****************/
29321 #define USART_RTOR_RTO_Pos                  (0U)
29322 #define USART_RTOR_RTO_Msk                  (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
29323 #define USART_RTOR_RTO                      USART_RTOR_RTO_Msk                      /*!< Receiver Time Out Value */
29324 #define USART_RTOR_BLEN_Pos                 (24U)
29325 #define USART_RTOR_BLEN_Msk                 (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
29326 #define USART_RTOR_BLEN                     USART_RTOR_BLEN_Msk                     /*!< Block Length */
29327 
29328 /*******************  Bit definition for USART_RQR register  ******************/
29329 #define USART_RQR_ABRRQ                     ((uint16_t)0x0001)                      /*!< Auto-Baud Rate Request */
29330 #define USART_RQR_SBKRQ                     ((uint16_t)0x0002)                      /*!< Send Break Request */
29331 #define USART_RQR_MMRQ                      ((uint16_t)0x0004)                      /*!< Mute Mode Request */
29332 #define USART_RQR_RXFRQ                     ((uint16_t)0x0008)                      /*!< Receive Data flush Request */
29333 #define USART_RQR_TXFRQ                     ((uint16_t)0x0010)                      /*!< Transmit data flush Request */
29334 
29335 /*******************  Bit definition for USART_ISR register  ******************/
29336 #define USART_ISR_PE_Pos                    (0U)
29337 #define USART_ISR_PE_Msk                    (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
29338 #define USART_ISR_PE                        USART_ISR_PE_Msk                        /*!< Parity Error */
29339 #define USART_ISR_FE_Pos                    (1U)
29340 #define USART_ISR_FE_Msk                    (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
29341 #define USART_ISR_FE                        USART_ISR_FE_Msk                        /*!< Framing Error */
29342 #define USART_ISR_NE_Pos                    (2U)
29343 #define USART_ISR_NE_Msk                    (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
29344 #define USART_ISR_NE                        USART_ISR_NE_Msk                        /*!< Noise detected Flag */
29345 #define USART_ISR_ORE_Pos                   (3U)
29346 #define USART_ISR_ORE_Msk                   (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
29347 #define USART_ISR_ORE                       USART_ISR_ORE_Msk                       /*!< OverRun Error */
29348 #define USART_ISR_IDLE_Pos                  (4U)
29349 #define USART_ISR_IDLE_Msk                  (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
29350 #define USART_ISR_IDLE                      USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
29351 #define USART_ISR_RXNE_Pos                  (5U)
29352 #define USART_ISR_RXNE_Msk                  (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
29353 #define USART_ISR_RXNE                      USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
29354 #define USART_ISR_RXNE_RXFNE_Pos            USART_ISR_RXNE_Pos
29355 #define USART_ISR_RXNE_RXFNE_Msk            USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
29356 #define USART_ISR_RXNE_RXFNE                USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
29357 #define USART_ISR_TC_Pos                    (6U)
29358 #define USART_ISR_TC_Msk                    (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
29359 #define USART_ISR_TC                        USART_ISR_TC_Msk                        /*!< Transmission Complete */
29360 #define USART_ISR_TXE_Pos                   (7U)
29361 #define USART_ISR_TXE_Msk                   (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
29362 #define USART_ISR_TXE                       USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
29363 #define USART_ISR_TXE_TXFNF_Pos             USART_ISR_TXE_Pos
29364 #define USART_ISR_TXE_TXFNF_Msk             USART_ISR_TXE_Msk                       /*!< 0x00000080 */
29365 #define USART_ISR_TXE_TXFNF                 USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
29366 #define USART_ISR_LBDF_Pos                  (8U)
29367 #define USART_ISR_LBDF_Msk                  (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
29368 #define USART_ISR_LBDF                      USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
29369 #define USART_ISR_CTSIF_Pos                 (9U)
29370 #define USART_ISR_CTSIF_Msk                 (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
29371 #define USART_ISR_CTSIF                     USART_ISR_CTSIF_Msk                     /*!< CTS interrupt flag */
29372 #define USART_ISR_CTS_Pos                   (10U)
29373 #define USART_ISR_CTS_Msk                   (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
29374 #define USART_ISR_CTS                       USART_ISR_CTS_Msk                       /*!< CTS flag */
29375 #define USART_ISR_RTOF_Pos                  (11U)
29376 #define USART_ISR_RTOF_Msk                  (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
29377 #define USART_ISR_RTOF                      USART_ISR_RTOF_Msk                      /*!< Receiver Time Out */
29378 #define USART_ISR_EOBF_Pos                  (12U)
29379 #define USART_ISR_EOBF_Msk                  (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
29380 #define USART_ISR_EOBF                      USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
29381 #define USART_ISR_UDR_Pos                   (13U)
29382 #define USART_ISR_UDR_Msk                   (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
29383 #define USART_ISR_UDR                       USART_ISR_UDR_Msk                       /*!< SPI slave underrun error flag */
29384 #define USART_ISR_ABRE_Pos                  (14U)
29385 #define USART_ISR_ABRE_Msk                  (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
29386 #define USART_ISR_ABRE                      USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
29387 #define USART_ISR_ABRF_Pos                  (15U)
29388 #define USART_ISR_ABRF_Msk                  (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
29389 #define USART_ISR_ABRF                      USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
29390 #define USART_ISR_BUSY_Pos                  (16U)
29391 #define USART_ISR_BUSY_Msk                  (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
29392 #define USART_ISR_BUSY                      USART_ISR_BUSY_Msk                      /*!< Busy Flag */
29393 #define USART_ISR_CMF_Pos                   (17U)
29394 #define USART_ISR_CMF_Msk                   (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
29395 #define USART_ISR_CMF                       USART_ISR_CMF_Msk                       /*!< Character Match Flag */
29396 #define USART_ISR_SBKF_Pos                  (18U)
29397 #define USART_ISR_SBKF_Msk                  (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
29398 #define USART_ISR_SBKF                      USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
29399 #define USART_ISR_RWU_Pos                   (19U)
29400 #define USART_ISR_RWU_Msk                   (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
29401 #define USART_ISR_RWU                       USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
29402 #define USART_ISR_TEACK_Pos                 (21U)
29403 #define USART_ISR_TEACK_Msk                 (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
29404 #define USART_ISR_TEACK                     USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
29405 #define USART_ISR_REACK_Pos                 (22U)
29406 #define USART_ISR_REACK_Msk                 (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
29407 #define USART_ISR_REACK                     USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
29408 #define USART_ISR_TXFE_Pos                  (23U)
29409 #define USART_ISR_TXFE_Msk                  (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
29410 #define USART_ISR_TXFE                      USART_ISR_TXFE_Msk                      /*!< TXFIFO Empty */
29411 #define USART_ISR_RXFF_Pos                  (24U)
29412 #define USART_ISR_RXFF_Msk                  (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
29413 #define USART_ISR_RXFF                      USART_ISR_RXFF_Msk                      /*!< RXFIFO Full */
29414 #define USART_ISR_TCBGT_Pos                 (25U)
29415 #define USART_ISR_TCBGT_Msk                 (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
29416 #define USART_ISR_TCBGT                     USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
29417 #define USART_ISR_RXFT_Pos                  (26U)
29418 #define USART_ISR_RXFT_Msk                  (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
29419 #define USART_ISR_RXFT                      USART_ISR_RXFT_Msk                      /*!< RXFIFO threshold flag */
29420 #define USART_ISR_TXFT_Pos                  (27U)
29421 #define USART_ISR_TXFT_Msk                  (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
29422 #define USART_ISR_TXFT                      USART_ISR_TXFT_Msk                      /*!< TXFIFO threshold flag */
29423 
29424 /*******************  Bit definition for USART_ICR register  ******************/
29425 #define USART_ICR_PECF_Pos                  (0U)
29426 #define USART_ICR_PECF_Msk                  (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
29427 #define USART_ICR_PECF                      USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
29428 #define USART_ICR_FECF_Pos                  (1U)
29429 #define USART_ICR_FECF_Msk                  (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
29430 #define USART_ICR_FECF                      USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
29431 #define USART_ICR_NECF_Pos                  (2U)
29432 #define USART_ICR_NECF_Msk                  (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
29433 #define USART_ICR_NECF                      USART_ICR_NECF_Msk                      /*!< Noise detected Clear Flag */
29434 #define USART_ICR_ORECF_Pos                 (3U)
29435 #define USART_ICR_ORECF_Msk                 (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
29436 #define USART_ICR_ORECF                     USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
29437 #define USART_ICR_IDLECF_Pos                (4U)
29438 #define USART_ICR_IDLECF_Msk                (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
29439 #define USART_ICR_IDLECF                    USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
29440 #define USART_ICR_TXFECF_Pos                (5U)
29441 #define USART_ICR_TXFECF_Msk                (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
29442 #define USART_ICR_TXFECF                    USART_ICR_TXFECF_Msk                    /*!< TXFIFO empty Clear flag */
29443 #define USART_ICR_TCCF_Pos                  (6U)
29444 #define USART_ICR_TCCF_Msk                  (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
29445 #define USART_ICR_TCCF                      USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
29446 #define USART_ICR_TCBGTCF_Pos               (7U)
29447 #define USART_ICR_TCBGTCF_Msk               (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
29448 #define USART_ICR_TCBGTCF                   USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
29449 #define USART_ICR_LBDCF_Pos                 (8U)
29450 #define USART_ICR_LBDCF_Msk                 (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
29451 #define USART_ICR_LBDCF                     USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
29452 #define USART_ICR_CTSCF_Pos                 (9U)
29453 #define USART_ICR_CTSCF_Msk                 (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
29454 #define USART_ICR_CTSCF                     USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
29455 #define USART_ICR_RTOCF_Pos                 (11U)
29456 #define USART_ICR_RTOCF_Msk                 (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
29457 #define USART_ICR_RTOCF                     USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
29458 #define USART_ICR_EOBCF_Pos                 (12U)
29459 #define USART_ICR_EOBCF_Msk                 (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
29460 #define USART_ICR_EOBCF                     USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
29461 #define USART_ICR_UDRCF_Pos                 (13U)
29462 #define USART_ICR_UDRCF_Msk                 (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
29463 #define USART_ICR_UDRCF                     USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
29464 #define USART_ICR_CMCF_Pos                  (17U)
29465 #define USART_ICR_CMCF_Msk                  (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
29466 #define USART_ICR_CMCF                      USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */
29467 
29468 /*******************  Bit definition for USART_RDR register  ******************/
29469 #define USART_RDR_RDR                       ((uint16_t)0x01FF)                      /*!< RDR[8:0] bits (Receive Data value) */
29470 
29471 /*******************  Bit definition for USART_TDR register  ******************/
29472 #define USART_TDR_TDR                       ((uint16_t)0x01FF)                      /*!< TDR[8:0] bits (Transmit Data value) */
29473 
29474 /*******************  Bit definition for USART_PRESC register  ****************/
29475 #define USART_PRESC_PRESCALER_Pos           (0U)
29476 #define USART_PRESC_PRESCALER_Msk           (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
29477 #define USART_PRESC_PRESCALER               USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
29478 #define USART_PRESC_PRESCALER_0             (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
29479 #define USART_PRESC_PRESCALER_1             (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
29480 #define USART_PRESC_PRESCALER_2             (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
29481 #define USART_PRESC_PRESCALER_3             (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
29482 
29483 /*******************  Bit definition for USART_AUTOCR register  ******************/
29484 #define USART_AUTOCR_TDN_Pos                (0U)
29485 #define USART_AUTOCR_TDN_Msk                (0xFFFFUL << USART_AUTOCR_TDN_Pos)      /*!< 0x0000FFFF */
29486 #define USART_AUTOCR_TDN                    USART_AUTOCR_TDN_Msk                    /*!< TDN[15:0] bits (Transmission Data Number) */
29487 #define USART_AUTOCR_TRIGPOL_Pos            (16U)
29488 #define USART_AUTOCR_TRIGPOL_Msk            (0x1UL << USART_AUTOCR_TRIGPOL_Pos)     /*!< 0x00010000 */
29489 #define USART_AUTOCR_TRIGPOL                USART_AUTOCR_TRIGPOL_Msk                /*!< Trigger Polarity Bit (Rising/Falling edge) */
29490 #define USART_AUTOCR_TRIGEN_Pos             (17U)
29491 #define USART_AUTOCR_TRIGEN_Msk             (0x1UL << USART_AUTOCR_TRIGEN_Pos)      /*!< 0x00020000 */
29492 #define USART_AUTOCR_TRIGEN                 USART_AUTOCR_TRIGEN_Msk                 /*!< Trigger Enable Bit */
29493 #define USART_AUTOCR_IDLEDIS_Pos            (18U)
29494 #define USART_AUTOCR_IDLEDIS_Msk            (0x1UL << USART_AUTOCR_IDLEDIS_Pos)     /*!< 0x00040000 */
29495 #define USART_AUTOCR_IDLEDIS                USART_AUTOCR_IDLEDIS_Msk                /*!< Idle Frame Transmission Disable Bit*/
29496 #define USART_AUTOCR_TRIGSEL_Pos            (19U)
29497 #define USART_AUTOCR_TRIGSEL_Msk            (0xFUL << USART_AUTOCR_TRIGSEL_Pos)     /*!< 0x00780000 */
29498 #define USART_AUTOCR_TRIGSEL                USART_AUTOCR_TRIGSEL_Msk                /*!< Trigger Selection Bits */
29499 #define USART_AUTOCR_TRIGSEL_0              (0x0001UL << USART_AUTOCR_TRIGSEL_Pos)  /*!< 0x00000001 */
29500 #define USART_AUTOCR_TRIGSEL_1              (0x0002UL << USART_AUTOCR_TRIGSEL_Pos)  /*!< 0x00000002 */
29501 #define USART_AUTOCR_TRIGSEL_2              (0x0004UL << USART_AUTOCR_TRIGSEL_Pos)  /*!< 0x00000004 */
29502 #define USART_AUTOCR_TRIGSEL_3              (0x0008UL << USART_AUTOCR_TRIGSEL_Pos)  /*!< 0x00000008 */
29503 
29504 /*******************  Bit definition for USART_HWCFGR2 register  **************/
29505 #define USART_HWCFGR2_CFG1_Pos              (0U)
29506 #define USART_HWCFGR2_CFG1_Msk              (0xFUL << USART_HWCFGR2_CFG1_Pos)       /*!< 0x0000000F */
29507 #define USART_HWCFGR2_CFG1                  USART_HWCFGR2_CFG1_Msk                  /*!< CFG1[3:0] bits (USART hardware configuration 1) */
29508 #define USART_HWCFGR2_CFG2_Pos              (4U)
29509 #define USART_HWCFGR2_CFG2_Msk              (0xFUL << USART_HWCFGR2_CFG2_Pos)       /*!< 0x000000F0 */
29510 #define USART_HWCFGR2_CFG2                  USART_HWCFGR2_CFG2_Msk                  /*!< CFG2[7:4] bits (USART hardware configuration 2) */
29511 
29512 /*******************  Bit definition for USART_HWCFGR1 register  **************/
29513 #define USART_HWCFGR1_CFG1_Pos              (0U)
29514 #define USART_HWCFGR1_CFG1_Msk              (0xFUL << USART_HWCFGR1_CFG1_Pos)       /*!< 0x0000000F */
29515 #define USART_HWCFGR1_CFG1                  USART_HWCFGR1_CFG1_Msk                  /*!< CFG1[3:0] bits (USART hardware configuration 1) */
29516 #define USART_HWCFGR1_CFG2_Pos              (4U)
29517 #define USART_HWCFGR1_CFG2_Msk              (0xFUL << USART_HWCFGR1_CFG2_Pos)       /*!< 0x000000F0 */
29518 #define USART_HWCFGR1_CFG2                  USART_HWCFGR1_CFG2_Msk                  /*!< CFG2[7:4] bits (USART hardware configuration 2) */
29519 #define USART_HWCFGR1_CFG3_Pos              (8U)
29520 #define USART_HWCFGR1_CFG3_Msk              (0xFUL << USART_HWCFGR1_CFG3_Pos)       /*!< 0x00000F00 */
29521 #define USART_HWCFGR1_CFG3                  USART_HWCFGR1_CFG3_Msk                  /*!< CFG3[11:8] bits (USART hardware configuration 3) */
29522 #define USART_HWCFGR1_CFG4_Pos              (12U)
29523 #define USART_HWCFGR1_CFG4_Msk              (0xFUL << USART_HWCFGR1_CFG4_Pos)       /*!< 0x0000F000 */
29524 #define USART_HWCFGR1_CFG4                  USART_HWCFGR1_CFG4_Msk                  /*!< CFG4[15:12] bits (USART hardware configuration 4) */
29525 #define USART_HWCFGR1_CFG5_Pos              (16U)
29526 #define USART_HWCFGR1_CFG5_Msk              (0xFUL << USART_HWCFGR1_CFG5_Pos)       /*!< 0x000F0000 */
29527 #define USART_HWCFGR1_CFG5                  USART_HWCFGR1_CFG5_Msk                  /*!< CFG5[19:16] bits (USART hardware configuration 5) */
29528 #define USART_HWCFGR1_CFG6_Pos              (20U)
29529 #define USART_HWCFGR1_CFG6_Msk              (0xFUL << USART_HWCFGR1_CFG6_Pos)       /*!< 0x00F00000 */
29530 #define USART_HWCFGR1_CFG6                  USART_HWCFGR1_CFG6_Msk                  /*!< CFG6[23:20] bits (USART hardware configuration 6) */
29531 #define USART_HWCFGR1_CFG7_Pos              (24U)
29532 #define USART_HWCFGR1_CFG7_Msk              (0xFUL << USART_HWCFGR1_CFG7_Pos)       /*!< 0x0F000000 */
29533 #define USART_HWCFGR1_CFG7                  USART_HWCFGR1_CFG7_Msk                  /*!< CFG7[27:24] bits (USART hardware configuration 7) */
29534 #define USART_HWCFGR1_CFG8_Pos              (28U)
29535 #define USART_HWCFGR1_CFG8_Msk              (0xFUL << USART_HWCFGR1_CFG8_Pos)       /*!< 0xF0000000 */
29536 #define USART_HWCFGR1_CFG8                  USART_HWCFGR1_CFG8_Msk                  /*!< CFG8[31:28] bits (USART hardware configuration 8) */
29537 
29538 /*******************  Bit definition for USART_VERR register  *****************/
29539 #define USART_VERR_MINREV_Pos               (0U)
29540 #define USART_VERR_MINREV_Msk               (0xFUL << USART_VERR_MINREV_Pos)        /*!< 0x0000000F */
29541 #define USART_VERR_MINREV                   USART_VERR_MINREV_Msk                   /*!< MAJREV[3:0] bits (Minor revision) */
29542 #define USART_VERR_MAJREV_Pos               (4U)
29543 #define USART_VERR_MAJREV_Msk               (0xFUL << USART_VERR_MAJREV_Pos)        /*!< 0x000000F0 */
29544 #define USART_VERR_MAJREV                   USART_VERR_MAJREV_Msk                   /*!< MINREV[3:0] bits (Major revision) */
29545 
29546 /*******************  Bit definition for USART_IPIDR register  ****************/
29547 #define USART_IPIDR_ID_Pos                  (0U)
29548 #define USART_IPIDR_ID_Msk                  (0xFFFFFFFFUL << USART_IPIDR_ID_Pos)    /*!< 0xFFFFFFFF */
29549 #define USART_IPIDR_ID                      USART_IPIDR_ID_Msk                      /*!< ID[31:0] bits (Peripheral identifier) */
29550 
29551 /*******************  Bit definition for USART_SIDR register  ****************/
29552 #define USART_SIDR_ID_Pos                   (0U)
29553 #define USART_SIDR_ID_Msk                   (0xFFFFFFFFUL << USART_SIDR_ID_Pos)     /*!< 0xFFFFFFFF */
29554 #define USART_SIDR_ID                       USART_SIDR_ID_Msk                       /*!< SID[31:0] bits (Size identification) */
29555 
29556 /******************************************************************************/
29557 /*                                                                            */
29558 /*                      Inter-integrated Circuit Interface (I2C)              */
29559 /*                                                                            */
29560 /******************************************************************************/
29561 /*******************  Bit definition for I2C_CR1 register  *******************/
29562 #define I2C_CR1_PE_Pos                      (0U)
29563 #define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
29564 #define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
29565 #define I2C_CR1_TXIE_Pos                    (1U)
29566 #define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
29567 #define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
29568 #define I2C_CR1_RXIE_Pos                    (2U)
29569 #define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
29570 #define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
29571 #define I2C_CR1_ADDRIE_Pos                  (3U)
29572 #define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
29573 #define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
29574 #define I2C_CR1_NACKIE_Pos                  (4U)
29575 #define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
29576 #define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
29577 #define I2C_CR1_STOPIE_Pos                  (5U)
29578 #define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
29579 #define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
29580 #define I2C_CR1_TCIE_Pos                    (6U)
29581 #define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
29582 #define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
29583 #define I2C_CR1_ERRIE_Pos                   (7U)
29584 #define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
29585 #define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
29586 #define I2C_CR1_DNF_Pos                     (8U)
29587 #define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
29588 #define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
29589 #define I2C_CR1_ANFOFF_Pos                  (12U)
29590 #define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
29591 #define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
29592 #define I2C_CR1_SWRST_Pos                   (13U)
29593 #define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)            /*!< 0x00002000 */
29594 #define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                       /*!< Software reset */
29595 #define I2C_CR1_TXDMAEN_Pos                 (14U)
29596 #define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
29597 #define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
29598 #define I2C_CR1_RXDMAEN_Pos                 (15U)
29599 #define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
29600 #define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
29601 #define I2C_CR1_SBC_Pos                     (16U)
29602 #define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
29603 #define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
29604 #define I2C_CR1_NOSTRETCH_Pos               (17U)
29605 #define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
29606 #define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
29607 #define I2C_CR1_WUPEN_Pos                   (18U)
29608 #define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
29609 #define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
29610 #define I2C_CR1_GCEN_Pos                    (19U)
29611 #define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
29612 #define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
29613 #define I2C_CR1_SMBHEN_Pos                  (20U)
29614 #define I2C_CR1_SMBHEN_Msk                  (0x1UL << I2C_CR1_SMBHEN_Pos)           /*!< 0x00100000 */
29615 #define I2C_CR1_SMBHEN                      I2C_CR1_SMBHEN_Msk                      /*!< SMBus host address enable */
29616 #define I2C_CR1_SMBDEN_Pos                  (21U)
29617 #define I2C_CR1_SMBDEN_Msk                  (0x1UL << I2C_CR1_SMBDEN_Pos)           /*!< 0x00200000 */
29618 #define I2C_CR1_SMBDEN                      I2C_CR1_SMBDEN_Msk                      /*!< SMBus device default address enable */
29619 #define I2C_CR1_ALERTEN_Pos                 (22U)
29620 #define I2C_CR1_ALERTEN_Msk                 (0x1UL << I2C_CR1_ALERTEN_Pos)          /*!< 0x00400000 */
29621 #define I2C_CR1_ALERTEN                     I2C_CR1_ALERTEN_Msk                     /*!< SMBus alert enable */
29622 #define I2C_CR1_PECEN_Pos                   (23U)
29623 #define I2C_CR1_PECEN_Msk                   (0x1UL << I2C_CR1_PECEN_Pos)            /*!< 0x00800000 */
29624 #define I2C_CR1_PECEN                       I2C_CR1_PECEN_Msk                       /*!< PEC enable */
29625 #define I2C_CR1_FMP_Pos                     (24U)
29626 #define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)              /*!< 0x01000000 */
29627 #define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                         /*!< FMP enable */
29628 #define I2C_CR1_ADDRACLR_Pos                (30U)
29629 #define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
29630 #define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
29631 #define I2C_CR1_STOPFACLR_Pos               (31U)
29632 #define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
29633 #define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */
29634 
29635 /******************  Bit definition for I2C_CR2 register  ********************/
29636 #define I2C_CR2_SADD_Pos                    (0U)
29637 #define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
29638 #define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
29639 #define I2C_CR2_RD_WRN_Pos                  (10U)
29640 #define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
29641 #define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
29642 #define I2C_CR2_ADD10_Pos                   (11U)
29643 #define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
29644 #define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
29645 #define I2C_CR2_HEAD10R_Pos                 (12U)
29646 #define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
29647 #define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
29648 #define I2C_CR2_START_Pos                   (13U)
29649 #define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
29650 #define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
29651 #define I2C_CR2_STOP_Pos                    (14U)
29652 #define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
29653 #define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
29654 #define I2C_CR2_NACK_Pos                    (15U)
29655 #define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
29656 #define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
29657 #define I2C_CR2_NBYTES_Pos                  (16U)
29658 #define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
29659 #define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
29660 #define I2C_CR2_RELOAD_Pos                  (24U)
29661 #define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
29662 #define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
29663 #define I2C_CR2_AUTOEND_Pos                 (25U)
29664 #define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
29665 #define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
29666 #define I2C_CR2_PECBYTE_Pos                 (26U)
29667 #define I2C_CR2_PECBYTE_Msk                 (0x1UL << I2C_CR2_PECBYTE_Pos)          /*!< 0x04000000 */
29668 #define I2C_CR2_PECBYTE                     I2C_CR2_PECBYTE_Msk                     /*!< Packet error checking byte */
29669 
29670 /*******************  Bit definition for I2C_OAR1 register  ******************/
29671 #define I2C_OAR1_OA1_Pos                    (0U)
29672 #define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
29673 #define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
29674 #define I2C_OAR1_OA1MODE_Pos                (10U)
29675 #define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
29676 #define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
29677 #define I2C_OAR1_OA1EN_Pos                  (15U)
29678 #define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
29679 #define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */
29680 
29681 /*******************  Bit definition for I2C_OAR2 register  ******************/
29682 #define I2C_OAR2_OA2_Pos                    (1U)
29683 #define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
29684 #define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
29685 #define I2C_OAR2_OA2MSK_Pos                 (8U)
29686 #define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
29687 #define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
29688 #define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
29689 #define I2C_OAR2_OA2MASK01_Pos              (8U)
29690 #define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
29691 #define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
29692 #define I2C_OAR2_OA2MASK02_Pos              (9U)
29693 #define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
29694 #define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
29695 #define I2C_OAR2_OA2MASK03_Pos              (8U)
29696 #define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
29697 #define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
29698 #define I2C_OAR2_OA2MASK04_Pos              (10U)
29699 #define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
29700 #define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
29701 #define I2C_OAR2_OA2MASK05_Pos              (8U)
29702 #define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
29703 #define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
29704 #define I2C_OAR2_OA2MASK06_Pos              (9U)
29705 #define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
29706 #define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
29707 #define I2C_OAR2_OA2MASK07_Pos              (8U)
29708 #define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
29709 #define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
29710 #define I2C_OAR2_OA2EN_Pos                  (15U)
29711 #define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
29712 #define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */
29713 
29714 /*******************  Bit definition for I2C_TIMINGR register *******************/
29715 #define I2C_TIMINGR_SCLL_Pos                (0U)
29716 #define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
29717 #define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
29718 #define I2C_TIMINGR_SCLH_Pos                (8U)
29719 #define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
29720 #define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
29721 #define I2C_TIMINGR_SDADEL_Pos              (16U)
29722 #define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
29723 #define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
29724 #define I2C_TIMINGR_SCLDEL_Pos              (20U)
29725 #define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
29726 #define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
29727 #define I2C_TIMINGR_PRESC_Pos               (28U)
29728 #define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
29729 #define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */
29730 
29731 /******************* Bit definition for I2C_TIMEOUTR register *******************/
29732 #define I2C_TIMEOUTR_TIMEOUTA_Pos           (0U)
29733 #define I2C_TIMEOUTR_TIMEOUTA_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)  /*!< 0x00000FFF */
29734 #define I2C_TIMEOUTR_TIMEOUTA               I2C_TIMEOUTR_TIMEOUTA_Msk               /*!< Bus timeout A */
29735 #define I2C_TIMEOUTR_TIDLE_Pos              (12U)
29736 #define I2C_TIMEOUTR_TIDLE_Msk              (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)       /*!< 0x00001000 */
29737 #define I2C_TIMEOUTR_TIDLE                  I2C_TIMEOUTR_TIDLE_Msk                  /*!< Idle clock timeout detection */
29738 #define I2C_TIMEOUTR_TIMOUTEN_Pos           (15U)
29739 #define I2C_TIMEOUTR_TIMOUTEN_Msk           (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)    /*!< 0x00008000 */
29740 #define I2C_TIMEOUTR_TIMOUTEN               I2C_TIMEOUTR_TIMOUTEN_Msk               /*!< Clock timeout enable */
29741 #define I2C_TIMEOUTR_TIMEOUTB_Pos           (16U)
29742 #define I2C_TIMEOUTR_TIMEOUTB_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)  /*!< 0x0FFF0000 */
29743 #define I2C_TIMEOUTR_TIMEOUTB               I2C_TIMEOUTR_TIMEOUTB_Msk               /*!< Bus timeout B*/
29744 #define I2C_TIMEOUTR_TEXTEN_Pos             (31U)
29745 #define I2C_TIMEOUTR_TEXTEN_Msk             (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)      /*!< 0x80000000 */
29746 #define I2C_TIMEOUTR_TEXTEN                 I2C_TIMEOUTR_TEXTEN_Msk                 /*!< Extended clock timeout enable */
29747 
29748 /******************  Bit definition for I2C_ISR register  *********************/
29749 #define I2C_ISR_TXE_Pos                     (0U)
29750 #define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
29751 #define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
29752 #define I2C_ISR_TXIS_Pos                    (1U)
29753 #define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
29754 #define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
29755 #define I2C_ISR_RXNE_Pos                    (2U)
29756 #define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
29757 #define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
29758 #define I2C_ISR_ADDR_Pos                    (3U)
29759 #define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
29760 #define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
29761 #define I2C_ISR_NACKF_Pos                   (4U)
29762 #define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
29763 #define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
29764 #define I2C_ISR_STOPF_Pos                   (5U)
29765 #define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
29766 #define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
29767 #define I2C_ISR_TC_Pos                      (6U)
29768 #define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
29769 #define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
29770 #define I2C_ISR_TCR_Pos                     (7U)
29771 #define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
29772 #define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
29773 #define I2C_ISR_BERR_Pos                    (8U)
29774 #define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
29775 #define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
29776 #define I2C_ISR_ARLO_Pos                    (9U)
29777 #define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
29778 #define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
29779 #define I2C_ISR_OVR_Pos                     (10U)
29780 #define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
29781 #define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
29782 #define I2C_ISR_PECERR_Pos                  (11U)
29783 #define I2C_ISR_PECERR_Msk                  (0x1UL << I2C_ISR_PECERR_Pos)           /*!< 0x00000800 */
29784 #define I2C_ISR_PECERR                      I2C_ISR_PECERR_Msk                      /*!< PEC error in reception */
29785 #define I2C_ISR_TIMEOUT_Pos                 (12U)
29786 #define I2C_ISR_TIMEOUT_Msk                 (0x1UL << I2C_ISR_TIMEOUT_Pos)          /*!< 0x00001000 */
29787 #define I2C_ISR_TIMEOUT                     I2C_ISR_TIMEOUT_Msk                     /*!< Timeout or Tlow detection flag */
29788 #define I2C_ISR_ALERT_Pos                   (13U)
29789 #define I2C_ISR_ALERT_Msk                   (0x1UL << I2C_ISR_ALERT_Pos)            /*!< 0x00002000 */
29790 #define I2C_ISR_ALERT                       I2C_ISR_ALERT_Msk                       /*!< SMBus alert */
29791 #define I2C_ISR_BUSY_Pos                    (15U)
29792 #define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
29793 #define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
29794 #define I2C_ISR_DIR_Pos                     (16U)
29795 #define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
29796 #define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
29797 #define I2C_ISR_ADDCODE_Pos                 (17U)
29798 #define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
29799 #define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */
29800 
29801 /******************  Bit definition for I2C_ICR register  *********************/
29802 #define I2C_ICR_ADDRCF_Pos                  (3U)
29803 #define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
29804 #define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
29805 #define I2C_ICR_NACKCF_Pos                  (4U)
29806 #define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
29807 #define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
29808 #define I2C_ICR_STOPCF_Pos                  (5U)
29809 #define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
29810 #define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
29811 #define I2C_ICR_BERRCF_Pos                  (8U)
29812 #define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
29813 #define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
29814 #define I2C_ICR_ARLOCF_Pos                  (9U)
29815 #define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
29816 #define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
29817 #define I2C_ICR_OVRCF_Pos                   (10U)
29818 #define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
29819 #define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
29820 #define I2C_ICR_PECCF_Pos                   (11U)
29821 #define I2C_ICR_PECCF_Msk                   (0x1UL << I2C_ICR_PECCF_Pos)            /*!< 0x00000800 */
29822 #define I2C_ICR_PECCF                       I2C_ICR_PECCF_Msk                       /*!< PAC error clear flag */
29823 #define I2C_ICR_TIMOUTCF_Pos                (12U)
29824 #define I2C_ICR_TIMOUTCF_Msk                (0x1UL << I2C_ICR_TIMOUTCF_Pos)         /*!< 0x00001000 */
29825 #define I2C_ICR_TIMOUTCF                    I2C_ICR_TIMOUTCF_Msk                    /*!< Timeout clear flag */
29826 #define I2C_ICR_ALERTCF_Pos                 (13U)
29827 #define I2C_ICR_ALERTCF_Msk                 (0x1UL << I2C_ICR_ALERTCF_Pos)          /*!< 0x00002000 */
29828 #define I2C_ICR_ALERTCF                     I2C_ICR_ALERTCF_Msk                     /*!< Alert clear flag */
29829 
29830 /******************  Bit definition for I2C_PECR register  *********************/
29831 #define I2C_PECR_PEC_Pos                    (0U)
29832 #define I2C_PECR_PEC_Msk                    (0xFFUL << I2C_PECR_PEC_Pos)            /*!< 0x000000FF */
29833 #define I2C_PECR_PEC                        I2C_PECR_PEC_Msk                        /*!< PEC register */
29834 
29835 /******************  Bit definition for I2C_RXDR register  *********************/
29836 #define I2C_RXDR_RXDATA_Pos                 (0U)
29837 #define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
29838 #define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */
29839 
29840 /******************  Bit definition for I2C_TXDR register  *********************/
29841 #define I2C_TXDR_TXDATA_Pos                 (0U)
29842 #define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
29843 #define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */
29844 
29845 /******************  Bit definition for I2C_AUTOCR register  ********************/
29846 #define I2C_AUTOCR_TCDMAEN_Pos              (6U)
29847 #define I2C_AUTOCR_TCDMAEN_Msk              (0x1UL << I2C_AUTOCR_TCDMAEN_Pos)       /*!< 0x00000040 */
29848 #define I2C_AUTOCR_TCDMAEN                  I2C_AUTOCR_TCDMAEN_Msk                  /*!< DMA request enable on Transfer Complete event */
29849 #define I2C_AUTOCR_TCRDMAEN_Pos             (7U)
29850 #define I2C_AUTOCR_TCRDMAEN_Msk             (0x1UL << I2C_AUTOCR_TCRDMAEN_Pos)      /*!< 0x00000080 */
29851 #define I2C_AUTOCR_TCRDMAEN                 I2C_AUTOCR_TCRDMAEN_Msk                 /*!< DMA request enable on Transfer Complete Reload event */
29852 #define I2C_AUTOCR_TRIGSEL_Pos              (16U)
29853 #define I2C_AUTOCR_TRIGSEL_Msk              (0xFUL << I2C_AUTOCR_TRIGSEL_Pos)       /*!< 0x000F0000 */
29854 #define I2C_AUTOCR_TRIGSEL                  I2C_AUTOCR_TRIGSEL_Msk                  /*!< Trigger selection */
29855 #define I2C_AUTOCR_TRIGPOL_Pos              (20U)
29856 #define I2C_AUTOCR_TRIGPOL_Msk              (0x1UL << I2C_AUTOCR_TRIGPOL_Pos)       /*!< 0x000100000 */
29857 #define I2C_AUTOCR_TRIGPOL                  I2C_AUTOCR_TRIGPOL_Msk                  /*!< Trigger polarity */
29858 #define I2C_AUTOCR_TRIGEN_Pos               (21U)
29859 #define I2C_AUTOCR_TRIGEN_Msk               (0x1UL << I2C_AUTOCR_TRIGEN_Pos)        /*!< 0x000200000 */
29860 #define I2C_AUTOCR_TRIGEN                   I2C_AUTOCR_TRIGEN_Msk                   /*!< Trigger enable */
29861 
29862 /******************************************************************************/
29863 /*                                                                            */
29864 /*                           Independent WATCHDOG                             */
29865 /*                                                                            */
29866 /******************************************************************************/
29867 /*******************  Bit definition for IWDG_KR register  ********************/
29868 #define IWDG_KR_KEY_Pos                     (0U)
29869 #define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)           /*!< 0x0000FFFF */
29870 #define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                         /*!<Key value (write only, read 0000h)  */
29871 
29872 /*******************  Bit definition for IWDG_PR register  ********************/
29873 #define IWDG_PR_PR_Pos                      (0U)
29874 #define IWDG_PR_PR_Msk                      (0xFUL << IWDG_PR_PR_Pos)               /*!< 0x0000000F */
29875 #define IWDG_PR_PR                          IWDG_PR_PR_Msk                          /*!<PR[3:0] (Prescaler divider)         */
29876 #define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)               /*!< 0x00000001 */
29877 #define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)               /*!< 0x00000002 */
29878 #define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)               /*!< 0x00000004 */
29879 #define IWDG_PR_PR_3                        (0x8UL << IWDG_PR_PR_Pos)               /*!< 0x00000008 */
29880 
29881 /*******************  Bit definition for IWDG_RLR register  *******************/
29882 #define IWDG_RLR_RL_Pos                     (0U)
29883 #define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)            /*!< 0x00000FFF */
29884 #define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                         /*!<Watchdog counter reload value        */
29885 
29886 /*******************  Bit definition for IWDG_SR register  ********************/
29887 #define IWDG_SR_PVU_Pos                     (0U)
29888 #define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)              /*!< 0x00000001 */
29889 #define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                         /*!< Watchdog prescaler value update */
29890 #define IWDG_SR_RVU_Pos                     (1U)
29891 #define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)              /*!< 0x00000002 */
29892 #define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                         /*!< Watchdog counter reload value update */
29893 #define IWDG_SR_WVU_Pos                     (2U)
29894 #define IWDG_SR_WVU_Msk                     (0x1UL << IWDG_SR_WVU_Pos)              /*!< 0x00000004 */
29895 #define IWDG_SR_WVU                         IWDG_SR_WVU_Msk                         /*!< Watchdog counter window value update */
29896 #define IWDG_SR_EWU_Pos                     (3U)
29897 #define IWDG_SR_EWU_Msk                     (0x1UL << IWDG_SR_EWU_Pos)              /*!< 0x00000008 */
29898 #define IWDG_SR_EWU                         IWDG_SR_EWU_Msk                         /*!< Watchdog interrupt comparator value update */
29899 #define IWDG_SR_EWIF_Pos                    (14U)
29900 #define IWDG_SR_EWIF_Msk                    (0x1UL << IWDG_SR_EWIF_Pos)             /*!< 0x00004000 */
29901 #define IWDG_SR_EWIF                        IWDG_SR_EWIF_Msk                        /*!< Watchdog early interrupt flag */
29902 
29903 /******************  Bit definition for IWDG_WINR register  *******************/
29904 #define IWDG_WINR_WIN_Pos                   (0U)
29905 #define IWDG_WINR_WIN_Msk                   (0xFFFUL << IWDG_WINR_WIN_Pos)          /*!< 0x00000FFF */
29906 #define IWDG_WINR_WIN                       IWDG_WINR_WIN_Msk                       /*!< Watchdog counter window value */
29907 
29908 /******************  Bit definition for IWDG_EWCR register  *******************/
29909 #define IWDG_EWCR_EWIT_Pos                  (0U)
29910 #define IWDG_EWCR_EWIT_Msk                  (0xFFFUL << IWDG_EWCR_EWIT_Pos)         /*!< 0x00000FFF */
29911 #define IWDG_EWCR_EWIT                      IWDG_EWCR_EWIT_Msk                      /*!< Watchdog early wakeup comparator value */
29912 #define IWDG_EWCR_EWIC_Pos                  (14U)
29913 #define IWDG_EWCR_EWIC_Msk                  (0x1UL << IWDG_EWCR_EWIC_Pos)           /*!< 0x00000FFF */
29914 #define IWDG_EWCR_EWIC                      IWDG_EWCR_EWIC_Msk                      /*!< Watchdog early wakeup comparator value */
29915 #define IWDG_EWCR_EWIE_Pos                  (15U)
29916 #define IWDG_EWCR_EWIE_Msk                  (0x1UL << IWDG_EWCR_EWIE_Pos)           /*!< 0x00000FFF */
29917 #define IWDG_EWCR_EWIE                      IWDG_EWCR_EWIE_Msk                      /*!< Watchdog early wakeup comparator value */
29918 
29919 /******************************************************************************/
29920 /*                                                                            */
29921 /*                   Serial Peripheral Interface (SPI)                        */
29922 /*                                                                            */
29923 /******************************************************************************/
29924 /*******************  Bit definition for SPI_CR1 register  ********************/
29925 #define SPI_CR1_SPE_Pos                     (0U)
29926 #define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)              /*!< 0x00000001 */
29927 #define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                         /*!<Serial Peripheral Enable */
29928 #define SPI_CR1_MASRX_Pos                   (8U)
29929 #define SPI_CR1_MASRX_Msk                   (0x1UL << SPI_CR1_MASRX_Pos)            /*!< 0x00000100 */
29930 #define SPI_CR1_MASRX                       SPI_CR1_MASRX_Msk                       /*!<Master automatic SUSP in Receive mode */
29931 #define SPI_CR1_CSTART_Pos                  (9U)
29932 #define SPI_CR1_CSTART_Msk                  (0x1UL << SPI_CR1_CSTART_Pos)           /*!< 0x00000200 */
29933 #define SPI_CR1_CSTART                      SPI_CR1_CSTART_Msk                      /*!<Master transfer start  */
29934 #define SPI_CR1_CSUSP_Pos                   (10U)
29935 #define SPI_CR1_CSUSP_Msk                   (0x1UL << SPI_CR1_CSUSP_Pos)            /*!< 0x00000400 */
29936 #define SPI_CR1_CSUSP                       SPI_CR1_CSUSP_Msk                       /*!<Master SUSPend request */
29937 #define SPI_CR1_HDDIR_Pos                   (11U)
29938 #define SPI_CR1_HDDIR_Msk                   (0x1UL << SPI_CR1_HDDIR_Pos)            /*!< 0x00000800 */
29939 #define SPI_CR1_HDDIR                       SPI_CR1_HDDIR_Msk                       /*!<Rx/Tx direction at Half-duplex mode */
29940 #define SPI_CR1_SSI_Pos                     (12U)
29941 #define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)              /*!< 0x00001000 */
29942 #define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                         /*!<Internal SS signal input level */
29943 #define SPI_CR1_CRC33_17_Pos                (13U)
29944 #define SPI_CR1_CRC33_17_Msk                (0x1UL << SPI_CR1_CRC33_17_Pos)         /*!< 0x00002000 */
29945 #define SPI_CR1_CRC33_17                    SPI_CR1_CRC33_17_Msk                    /*!<32-bit CRC polynomial configuration */
29946 #define SPI_CR1_RCRCINI_Pos                 (14U)
29947 #define SPI_CR1_RCRCINI_Msk                 (0x1UL << SPI_CR1_RCRCINI_Pos)          /*!< 0x00004000 */
29948 #define SPI_CR1_RCRCINI                     SPI_CR1_RCRCINI_Msk                     /*!<CRC init pattern control for receiver */
29949 #define SPI_CR1_TCRCINI_Pos                 (15U)
29950 #define SPI_CR1_TCRCINI_Msk                 (0x1UL << SPI_CR1_TCRCINI_Pos)          /*!< 0x00008000 */
29951 #define SPI_CR1_TCRCINI                     SPI_CR1_TCRCINI_Msk                     /*!<CRC init pattern control for transmitter */
29952 #define SPI_CR1_IOLOCK_Pos                  (16U)
29953 #define SPI_CR1_IOLOCK_Msk                  (0x1UL << SPI_CR1_IOLOCK_Pos)           /*!< 0x00010000 */
29954 #define SPI_CR1_IOLOCK                      SPI_CR1_IOLOCK_Msk                      /*!<Locking the AF configuration of associated IOs */
29955 
29956 /*******************  Bit definition for SPI_CR2 register  ********************/
29957 #define SPI_CR2_TSIZE_Pos                   (0U)
29958 #define SPI_CR2_TSIZE_Msk                   (0xFFFFUL << SPI_CR2_TSIZE_Pos)         /*!< 0x0000FFFF */
29959 #define SPI_CR2_TSIZE                       SPI_CR2_TSIZE_Msk                       /*!<Number of data at current transfer */
29960 
29961 /*******************  Bit definition for SPI_CFG1 register  ********************/
29962 #define SPI_CFG1_DSIZE_Pos                  (0U)
29963 #define SPI_CFG1_DSIZE_Msk                  (0x1FUL << SPI_CFG1_DSIZE_Pos)          /*!< 0x0000001F */
29964 #define SPI_CFG1_DSIZE                      SPI_CFG1_DSIZE_Msk                      /*!<DSIZE[4:0]: Bits number in single SPI data frame */
29965 #define SPI_CFG1_DSIZE_0                    (0x01UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000001 */
29966 #define SPI_CFG1_DSIZE_1                    (0x02UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000002 */
29967 #define SPI_CFG1_DSIZE_2                    (0x04UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000004 */
29968 #define SPI_CFG1_DSIZE_3                    (0x08UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000008 */
29969 #define SPI_CFG1_DSIZE_4                    (0x10UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000010 */
29970 #define SPI_CFG1_FTHLV_Pos                  (5U)
29971 #define SPI_CFG1_FTHLV_Msk                  (0xFUL << SPI_CFG1_FTHLV_Pos)           /*!< 0x000001E0 */
29972 #define SPI_CFG1_FTHLV                      SPI_CFG1_FTHLV_Msk                      /*!<FTHVL [3:0]: FIFO threshold level*/
29973 #define SPI_CFG1_FTHLV_0                    (0x1UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000020 */
29974 #define SPI_CFG1_FTHLV_1                    (0x2UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000040 */
29975 #define SPI_CFG1_FTHLV_2                    (0x4UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000080 */
29976 #define SPI_CFG1_FTHLV_3                    (0x8UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000100 */
29977 #define SPI_CFG1_UDRCFG_Pos                 (9U)
29978 #define SPI_CFG1_UDRCFG_Msk                 (0x1UL << SPI_CFG1_UDRCFG_Pos)          /*!< 0x00000600 */
29979 #define SPI_CFG1_UDRCFG                     SPI_CFG1_UDRCFG_Msk                     /*!<Behavior of Slave transmitter at underrun */
29980 #define SPI_CFG1_RXDMAEN_Pos                (14U)
29981 #define SPI_CFG1_RXDMAEN_Msk                (0x1UL << SPI_CFG1_RXDMAEN_Pos)         /*!< 0x00004000 */
29982 #define SPI_CFG1_RXDMAEN                    SPI_CFG1_RXDMAEN_Msk                    /*!<Rx DMA stream enable */
29983 #define SPI_CFG1_TXDMAEN_Pos                (15U)
29984 #define SPI_CFG1_TXDMAEN_Msk                (0x1UL << SPI_CFG1_TXDMAEN_Pos)         /*!< 0x00008000 */
29985 #define SPI_CFG1_TXDMAEN                    SPI_CFG1_TXDMAEN_Msk                    /*!<Tx DMA stream enable */
29986 #define SPI_CFG1_CRCSIZE_Pos                (16U)
29987 #define SPI_CFG1_CRCSIZE_Msk                (0x1FUL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x001F0000 */
29988 #define SPI_CFG1_CRCSIZE                    SPI_CFG1_CRCSIZE_Msk                    /*!<CRCSIZE [4:0]: Length of CRC frame */
29989 #define SPI_CFG1_CRCSIZE_0                  (0x01UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00010000 */
29990 #define SPI_CFG1_CRCSIZE_1                  (0x02UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00020000 */
29991 #define SPI_CFG1_CRCSIZE_2                  (0x04UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00040000 */
29992 #define SPI_CFG1_CRCSIZE_3                  (0x08UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00080000 */
29993 #define SPI_CFG1_CRCSIZE_4                  (0x10UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00100000 */
29994 #define SPI_CFG1_CRCEN_Pos                  (22U)
29995 #define SPI_CFG1_CRCEN_Msk                  (0x1UL << SPI_CFG1_CRCEN_Pos)           /*!< 0x00400000 */
29996 #define SPI_CFG1_CRCEN                      SPI_CFG1_CRCEN_Msk                      /*!<Hardware CRC computation enable */
29997 #define SPI_CFG1_MBR_Pos                    (28U)
29998 #define SPI_CFG1_MBR_Msk                    (0x7UL << SPI_CFG1_MBR_Pos)             /*!< 0x70000000 */
29999 #define SPI_CFG1_MBR                        SPI_CFG1_MBR_Msk                        /*!<Master baud rate */
30000 #define SPI_CFG1_MBR_0                      (0x1UL << SPI_CFG1_MBR_Pos)             /*!< 0x10000000 */
30001 #define SPI_CFG1_MBR_1                      (0x2UL << SPI_CFG1_MBR_Pos)             /*!< 0x20000000 */
30002 #define SPI_CFG1_MBR_2                      (0x4UL << SPI_CFG1_MBR_Pos)             /*!< 0x40000000 */
30003 #define SPI_CFG1_BPASS_Pos                  (31U)
30004 #define SPI_CFG1_BPASS_Msk                  (0x1UL << SPI_CFG1_BPASS_Pos)           /*!< 0x80000000 */
30005 #define SPI_CFG1_BPASS                      SPI_CFG1_BPASS_Msk                      /*!<Bypass of the prescaler */
30006 
30007 /*******************  Bit definition for SPI_CFG2 register  ********************/
30008 #define SPI_CFG2_MSSI_Pos                   (0U)
30009 #define SPI_CFG2_MSSI_Msk                   (0xFUL << SPI_CFG2_MSSI_Pos)            /*!< 0x0000000F */
30010 #define SPI_CFG2_MSSI                       SPI_CFG2_MSSI_Msk                       /*!<Master SS Idleness */
30011 #define SPI_CFG2_MSSI_0                     (0x1UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000001 */
30012 #define SPI_CFG2_MSSI_1                     (0x2UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000002 */
30013 #define SPI_CFG2_MSSI_2                     (0x4UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000004 */
30014 #define SPI_CFG2_MSSI_3                     (0x8UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000008 */
30015 #define SPI_CFG2_MIDI_Pos                   (4U)
30016 #define SPI_CFG2_MIDI_Msk                   (0xFUL << SPI_CFG2_MIDI_Pos)            /*!< 0x000000F0 */
30017 #define SPI_CFG2_MIDI                       SPI_CFG2_MIDI_Msk                       /*!<Master Inter-Data Idleness */
30018 #define SPI_CFG2_MIDI_0                     (0x1UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000010 */
30019 #define SPI_CFG2_MIDI_1                     (0x2UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000020 */
30020 #define SPI_CFG2_MIDI_2                     (0x4UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000040 */
30021 #define SPI_CFG2_MIDI_3                     (0x8UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000080 */
30022 #define SPI_CFG2_RDIMM_Pos                  (13U)
30023 #define SPI_CFG2_RDIMM_Msk                  (0x1UL << SPI_CFG2_RDIMM_Pos)           /*!< 0x00002000 */
30024 #define SPI_CFG2_RDIMM                      SPI_CFG2_RDIMM_Msk                      /*!<RDY signal input master management */
30025 #define SPI_CFG2_RDIOP_Pos                  (14U)
30026 #define SPI_CFG2_RDIOP_Msk                  (0x1UL << SPI_CFG2_RDIOP_Pos)           /*!< 0x00004000 */
30027 #define SPI_CFG2_RDIOP                      SPI_CFG2_RDIOP_Msk                      /*!<RDY signal input/output polarity */
30028 #define SPI_CFG2_IOSWP_Pos                  (15U)
30029 #define SPI_CFG2_IOSWP_Msk                  (0x1UL << SPI_CFG2_IOSWP_Pos)           /*!< 0x00008000 */
30030 #define SPI_CFG2_IOSWP                      SPI_CFG2_IOSWP_Msk                      /*!<Swap functionality of MISO and MOSI pins */
30031 #define SPI_CFG2_COMM_Pos                   (17U)
30032 #define SPI_CFG2_COMM_Msk                   (0x3UL << SPI_CFG2_COMM_Pos)            /*!< 0x00060000 */
30033 #define SPI_CFG2_COMM                       SPI_CFG2_COMM_Msk                       /*!<COMM [1:0]: SPI Communication Mode*/
30034 #define SPI_CFG2_COMM_0                     (0x1UL << SPI_CFG2_COMM_Pos)            /*!< 0x00020000 */
30035 #define SPI_CFG2_COMM_1                     (0x2UL << SPI_CFG2_COMM_Pos)            /*!< 0x00040000 */
30036 #define SPI_CFG2_SP_Pos                     (19U)
30037 #define SPI_CFG2_SP_Msk                     (0x7UL << SPI_CFG2_SP_Pos)              /*!< 0x00380000 */
30038 #define SPI_CFG2_SP                         SPI_CFG2_SP_Msk                         /*!<SP[2:0]: Serial Protocol */
30039 #define SPI_CFG2_SP_0                       (0x1UL << SPI_CFG2_SP_Pos)              /*!< 0x00080000 */
30040 #define SPI_CFG2_SP_1                       (0x2UL << SPI_CFG2_SP_Pos)              /*!< 0x00100000 */
30041 #define SPI_CFG2_SP_2                       (0x4UL << SPI_CFG2_SP_Pos)              /*!< 0x00200000 */
30042 #define SPI_CFG2_MASTER_Pos                 (22U)
30043 #define SPI_CFG2_MASTER_Msk                 (0x1UL << SPI_CFG2_MASTER_Pos)          /*!< 0x00400000 */
30044 #define SPI_CFG2_MASTER                     SPI_CFG2_MASTER_Msk                     /*!<SPI Master */
30045 #define SPI_CFG2_LSBFRST_Pos                (23U)
30046 #define SPI_CFG2_LSBFRST_Msk                (0x1UL << SPI_CFG2_LSBFRST_Pos)         /*!< 0x00800000 */
30047 #define SPI_CFG2_LSBFRST                    SPI_CFG2_LSBFRST_Msk                    /*!<Data frame format */
30048 #define SPI_CFG2_CPHA_Pos                   (24U)
30049 #define SPI_CFG2_CPHA_Msk                   (0x1UL << SPI_CFG2_CPHA_Pos)            /*!< 0x01000000 */
30050 #define SPI_CFG2_CPHA                       SPI_CFG2_CPHA_Msk                       /*!<Clock Phase */
30051 #define SPI_CFG2_CPOL_Pos                   (25U)
30052 #define SPI_CFG2_CPOL_Msk                   (0x1UL << SPI_CFG2_CPOL_Pos)            /*!< 0x02000000 */
30053 #define SPI_CFG2_CPOL                       SPI_CFG2_CPOL_Msk                       /*!<Clock Polarity */
30054 #define SPI_CFG2_SSM_Pos                    (26U)
30055 #define SPI_CFG2_SSM_Msk                    (0x1UL << SPI_CFG2_SSM_Pos)             /*!< 0x04000000 */
30056 #define SPI_CFG2_SSM                        SPI_CFG2_SSM_Msk                        /*!<Software slave management */
30057 #define SPI_CFG2_SSIOP_Pos                  (28U)
30058 #define SPI_CFG2_SSIOP_Msk                  (0x1UL << SPI_CFG2_SSIOP_Pos)           /*!< 0x10000000 */
30059 #define SPI_CFG2_SSIOP                      SPI_CFG2_SSIOP_Msk                      /*!<SS input/output polarity */
30060 #define SPI_CFG2_SSOE_Pos                   (29U)
30061 #define SPI_CFG2_SSOE_Msk                   (0x1UL << SPI_CFG2_SSOE_Pos)            /*!< 0x20000000 */
30062 #define SPI_CFG2_SSOE                       SPI_CFG2_SSOE_Msk                       /*!<SS output enable */
30063 #define SPI_CFG2_SSOM_Pos                   (30U)
30064 #define SPI_CFG2_SSOM_Msk                   (0x1UL << SPI_CFG2_SSOM_Pos)            /*!< 0x40000000 */
30065 #define SPI_CFG2_SSOM                       SPI_CFG2_SSOM_Msk                       /*!<SS output management in master mode */
30066 #define SPI_CFG2_AFCNTR_Pos                 (31U)
30067 #define SPI_CFG2_AFCNTR_Msk                 (0x1UL << SPI_CFG2_AFCNTR_Pos)          /*!< 0x80000000 */
30068 #define SPI_CFG2_AFCNTR                     SPI_CFG2_AFCNTR_Msk                     /*!<Alternate function GPIOs control */
30069 
30070 /*******************  Bit definition for SPI_IER register  ********************/
30071 #define SPI_IER_RXPIE_Pos                   (0U)
30072 #define SPI_IER_RXPIE_Msk                   (0x1UL << SPI_IER_RXPIE_Pos)            /*!< 0x00000001 */
30073 #define SPI_IER_RXPIE                       SPI_IER_RXPIE_Msk                       /*!<RXP Interrupt Enable */
30074 #define SPI_IER_TXPIE_Pos                   (1U)
30075 #define SPI_IER_TXPIE_Msk                   (0x1UL << SPI_IER_TXPIE_Pos)            /*!< 0x00000002 */
30076 #define SPI_IER_TXPIE                       SPI_IER_TXPIE_Msk                       /*!<TXP interrupt enable */
30077 #define SPI_IER_DXPIE_Pos                   (2U)
30078 #define SPI_IER_DXPIE_Msk                   (0x1UL << SPI_IER_DXPIE_Pos)            /*!< 0x00000004 */
30079 #define SPI_IER_DXPIE                       SPI_IER_DXPIE_Msk                       /*!<DXP interrupt enable */
30080 #define SPI_IER_EOTIE_Pos                   (3U)
30081 #define SPI_IER_EOTIE_Msk                   (0x1UL << SPI_IER_EOTIE_Pos)            /*!< 0x00000008 */
30082 #define SPI_IER_EOTIE                       SPI_IER_EOTIE_Msk                       /*!<EOT/SUSP/TXC interrupt enable */
30083 #define SPI_IER_TXTFIE_Pos                  (4U)
30084 #define SPI_IER_TXTFIE_Msk                  (0x1UL << SPI_IER_TXTFIE_Pos)           /*!< 0x00000010 */
30085 #define SPI_IER_TXTFIE                      SPI_IER_TXTFIE_Msk                      /*!<TXTF interrupt enable */
30086 #define SPI_IER_UDRIE_Pos                   (5U)
30087 #define SPI_IER_UDRIE_Msk                   (0x1UL << SPI_IER_UDRIE_Pos)            /*!< 0x00000020 */
30088 #define SPI_IER_UDRIE                       SPI_IER_UDRIE_Msk                       /*!<UDR interrupt enable */
30089 #define SPI_IER_OVRIE_Pos                   (6U)
30090 #define SPI_IER_OVRIE_Msk                   (0x1UL << SPI_IER_OVRIE_Pos)            /*!< 0x00000040 */
30091 #define SPI_IER_OVRIE                       SPI_IER_OVRIE_Msk                       /*!<OVR interrupt enable */
30092 #define SPI_IER_CRCEIE_Pos                  (7U)
30093 #define SPI_IER_CRCEIE_Msk                  (0x1UL << SPI_IER_CRCEIE_Pos)           /*!< 0x00000080 */
30094 #define SPI_IER_CRCEIE                      SPI_IER_CRCEIE_Msk                      /*!<CRCE interrupt enable */
30095 #define SPI_IER_TIFREIE_Pos                 (8U)
30096 #define SPI_IER_TIFREIE_Msk                 (0x1UL << SPI_IER_TIFREIE_Pos)          /*!< 0x00000100 */
30097 #define SPI_IER_TIFREIE                     SPI_IER_TIFREIE_Msk                     /*!<TI Frame Error interrupt enable */
30098 #define SPI_IER_MODFIE_Pos                  (9U)
30099 #define SPI_IER_MODFIE_Msk                  (0x1UL << SPI_IER_MODFIE_Pos)           /*!< 0x00000200 */
30100 #define SPI_IER_MODFIE                      SPI_IER_MODFIE_Msk                      /*!<MODF interrupt enable */
30101 
30102 /*******************  Bit definition for SPI_SR register  ********************/
30103 #define SPI_SR_RXP_Pos                      (0U)
30104 #define SPI_SR_RXP_Msk                      (0x1UL << SPI_SR_RXP_Pos)               /*!< 0x00000001 */
30105 #define SPI_SR_RXP                          SPI_SR_RXP_Msk                          /*!<Rx-Packet available */
30106 #define SPI_SR_TXP_Pos                      (1U)
30107 #define SPI_SR_TXP_Msk                      (0x1UL << SPI_SR_TXP_Pos)               /*!< 0x00000002 */
30108 #define SPI_SR_TXP                          SPI_SR_TXP_Msk                          /*!<Tx-Packet space available */
30109 #define SPI_SR_DXP_Pos                      (2U)
30110 #define SPI_SR_DXP_Msk                      (0x1UL << SPI_SR_DXP_Pos)               /*!< 0x00000004 */
30111 #define SPI_SR_DXP                          SPI_SR_DXP_Msk                          /*!<Duplex Packet available */
30112 #define SPI_SR_EOT_Pos                      (3U)
30113 #define SPI_SR_EOT_Msk                      (0x1UL << SPI_SR_EOT_Pos)               /*!< 0x00000008 */
30114 #define SPI_SR_EOT                          SPI_SR_EOT_Msk                          /*!<Duplex Packet available */
30115 #define SPI_SR_TXTF_Pos                     (4U)
30116 #define SPI_SR_TXTF_Msk                     (0x1UL << SPI_SR_TXTF_Pos)              /*!< 0x00000010 */
30117 #define SPI_SR_TXTF                         SPI_SR_TXTF_Msk                         /*!<Transmission Transfer Filled */
30118 #define SPI_SR_UDR_Pos                      (5U)
30119 #define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)               /*!< 0x00000020 */
30120 #define SPI_SR_UDR                          SPI_SR_UDR_Msk                          /*!<UDR at Slave transmission */
30121 #define SPI_SR_OVR_Pos                      (6U)
30122 #define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)               /*!< 0x00000040 */
30123 #define SPI_SR_OVR                          SPI_SR_OVR_Msk                          /*!<Rx-Packet available */
30124 #define SPI_SR_CRCE_Pos                     (7U)
30125 #define SPI_SR_CRCE_Msk                     (0x1UL << SPI_SR_CRCE_Pos)              /*!< 0x00000080 */
30126 #define SPI_SR_CRCE                         SPI_SR_CRCE_Msk                         /*!<CRC Error Detected */
30127 #define SPI_SR_TIFRE_Pos                    (8U)
30128 #define SPI_SR_TIFRE_Msk                    (0x1UL << SPI_SR_TIFRE_Pos)             /*!< 0x00000100 */
30129 #define SPI_SR_TIFRE                        SPI_SR_TIFRE_Msk                        /*!<TI frame format error Detected */
30130 #define SPI_SR_MODF_Pos                     (9U)
30131 #define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)              /*!< 0x00000200 */
30132 #define SPI_SR_MODF                         SPI_SR_MODF_Msk                         /*!<Mode Fault Detected */
30133 #define SPI_SR_SUSP_Pos                     (11U)
30134 #define SPI_SR_SUSP_Msk                     (0x1UL << SPI_SR_SUSP_Pos)              /*!< 0x00000800 */
30135 #define SPI_SR_SUSP                         SPI_SR_SUSP_Msk                         /*!<SUSP is set by hardware */
30136 #define SPI_SR_TXC_Pos                      (12U)
30137 #define SPI_SR_TXC_Msk                      (0x1UL << SPI_SR_TXC_Pos)               /*!< 0x00001000 */
30138 #define SPI_SR_TXC                          SPI_SR_TXC_Msk                          /*!<TxFIFO transmission complete */
30139 #define SPI_SR_RXPLVL_Pos                   (13U)
30140 #define SPI_SR_RXPLVL_Msk                   (0x3UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00006000 */
30141 #define SPI_SR_RXPLVL                       SPI_SR_RXPLVL_Msk                       /*!<RxFIFO Packing Level */
30142 #define SPI_SR_RXPLVL_0                     (0x1UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00002000 */
30143 #define SPI_SR_RXPLVL_1                     (0x2UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00004000 */
30144 #define SPI_SR_RXWNE_Pos                    (15U)
30145 #define SPI_SR_RXWNE_Msk                    (0x1UL << SPI_SR_RXWNE_Pos)             /*!< 0x00008000 */
30146 #define SPI_SR_RXWNE                        SPI_SR_RXWNE_Msk                        /*!<Rx FIFO Word Not Empty */
30147 #define SPI_SR_CTSIZE_Pos                   (16U)
30148 #define SPI_SR_CTSIZE_Msk                   (0xFFFFUL << SPI_SR_CTSIZE_Pos)         /*!< 0xFFFF0000 */
30149 #define SPI_SR_CTSIZE                       SPI_SR_CTSIZE_Msk                       /*!<Number of data frames remaining in TSIZE */
30150 
30151 /*******************  Bit definition for SPI_IFCR register  ********************/
30152 #define SPI_IFCR_EOTC_Pos                   (3U)
30153 #define SPI_IFCR_EOTC_Msk                   (0x1UL << SPI_IFCR_EOTC_Pos)            /*!< 0x00000008 */
30154 #define SPI_IFCR_EOTC                       SPI_IFCR_EOTC_Msk                       /*!<End Of Transfer flag clear */
30155 #define SPI_IFCR_TXTFC_Pos                  (4U)
30156 #define SPI_IFCR_TXTFC_Msk                  (0x1UL << SPI_IFCR_TXTFC_Pos)           /*!< 0x00000010 */
30157 #define SPI_IFCR_TXTFC                      SPI_IFCR_TXTFC_Msk                      /*!<Transmission Transfer Filled flag clear */
30158 #define SPI_IFCR_UDRC_Pos                   (5U)
30159 #define SPI_IFCR_UDRC_Msk                   (0x1UL << SPI_IFCR_UDRC_Pos)            /*!< 0x00000020 */
30160 #define SPI_IFCR_UDRC                       SPI_IFCR_UDRC_Msk                       /*!<Underrun flag clear */
30161 #define SPI_IFCR_OVRC_Pos                   (6U)
30162 #define SPI_IFCR_OVRC_Msk                   (0x1UL << SPI_IFCR_OVRC_Pos)            /*!< 0x00000040 */
30163 #define SPI_IFCR_OVRC                       SPI_IFCR_OVRC_Msk                       /*!<Overrun flag clear */
30164 #define SPI_IFCR_CRCEC_Pos                  (7U)
30165 #define SPI_IFCR_CRCEC_Msk                  (0x1UL << SPI_IFCR_CRCEC_Pos)           /*!< 0x00000080 */
30166 #define SPI_IFCR_CRCEC                      SPI_IFCR_CRCEC_Msk                      /*!<CRC Error flag clear */
30167 #define SPI_IFCR_TIFREC_Pos                 (8U)
30168 #define SPI_IFCR_TIFREC_Msk                 (0x1UL << SPI_IFCR_TIFREC_Pos)          /*!< 0x00000100 */
30169 #define SPI_IFCR_TIFREC                     SPI_IFCR_TIFREC_Msk                     /*!<TI frame format error flag clear */
30170 #define SPI_IFCR_MODFC_Pos                  (9U)
30171 #define SPI_IFCR_MODFC_Msk                  (0x1UL << SPI_IFCR_MODFC_Pos)           /*!< 0x00000200 */
30172 #define SPI_IFCR_MODFC                      SPI_IFCR_MODFC_Msk                      /*!<Mode Fault flag clear */
30173 #define SPI_IFCR_SUSPC_Pos                  (11U)
30174 #define SPI_IFCR_SUSPC_Msk                  (0x1UL << SPI_IFCR_SUSPC_Pos)           /*!< 0x00000800 */
30175 #define SPI_IFCR_SUSPC                      SPI_IFCR_SUSPC_Msk                      /*!<SUSPend flag clear */
30176 
30177 /*******************  Bit definition for SPI_AUTOCR register  ********************/
30178 #define SPI_AUTOCR_TRIGSEL_Pos              (16U)
30179 #define SPI_AUTOCR_TRIGSEL_Msk              (0xFUL << SPI_AUTOCR_TRIGSEL_Pos)       /*!< 0x000F0000 */
30180 #define SPI_AUTOCR_TRIGSEL                  SPI_AUTOCR_TRIGSEL_Msk                  /*!<CTRIGSEL [3:0]: Trigger selection */
30181 #define SPI_AUTOCR_TRIGSEL_0                (0x01UL << SPI_AUTOCR_TRIGSEL_Pos)      /*!< 0x00010000 */
30182 #define SPI_AUTOCR_TRIGSEL_1                (0x02UL << SPI_AUTOCR_TRIGSEL_Pos)      /*!< 0x00020000 */
30183 #define SPI_AUTOCR_TRIGSEL_2                (0x04UL << SPI_AUTOCR_TRIGSEL_Pos)      /*!< 0x00040000 */
30184 #define SPI_AUTOCR_TRIGSEL_3                (0x08UL << SPI_AUTOCR_TRIGSEL_Pos)      /*!< 0x00080000 */
30185 #define SPI_AUTOCR_TRIGPOL_Pos              (20U)
30186 #define SPI_AUTOCR_TRIGPOL_Msk              (0x1UL << SPI_AUTOCR_TRIGPOL_Pos)       /*!< 0x00100000 */
30187 #define SPI_AUTOCR_TRIGPOL                  SPI_AUTOCR_TRIGPOL_Msk                  /*!<Trigger polarity */
30188 #define SPI_AUTOCR_TRIGEN_Pos               (21U)
30189 #define SPI_AUTOCR_TRIGEN_Msk               (0x1UL << SPI_AUTOCR_TRIGEN_Pos)        /*!< 0x00200000 */
30190 #define SPI_AUTOCR_TRIGEN                   SPI_AUTOCR_TRIGEN_Msk                   /*!<Trigger of CSTART control enable */
30191 
30192 /*******************  Bit definition for SPI_TXDR register  ********************/
30193 #define SPI_TXDR_TXDR_Pos                   (0U)
30194 #define SPI_TXDR_TXDR_Msk                   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)     /*!< 0xFFFFFFFF */
30195 #define SPI_TXDR_TXDR                       SPI_TXDR_TXDR_Msk                       /* Transmit Data Register */
30196 
30197 /*******************  Bit definition for SPI_RXDR register  ********************/
30198 #define SPI_RXDR_RXDR_Pos                   (0U)
30199 #define SPI_RXDR_RXDR_Msk                   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)     /*!< 0xFFFFFFFF */
30200 #define SPI_RXDR_RXDR                       SPI_RXDR_RXDR_Msk                       /* Receive Data Register */
30201 
30202 /*******************  Bit definition for SPI_CRCPOLY register  ********************/
30203 #define SPI_CRCPOLY_CRCPOLY_Pos             (0U)
30204 #define SPI_CRCPOLY_CRCPOLY_Msk             (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
30205 #define SPI_CRCPOLY_CRCPOLY                 SPI_CRCPOLY_CRCPOLY_Msk                 /* CRC Polynomial register */
30206 
30207 /*******************  Bit definition for SPI_TXCRC register  ********************/
30208 #define SPI_TXCRC_TXCRC_Pos                 (0U)
30209 #define SPI_TXCRC_TXCRC_Msk                 (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)   /*!< 0xFFFFFFFF */
30210 #define SPI_TXCRC_TXCRC                     SPI_TXCRC_TXCRC_Msk                     /* CRCRegister for transmitter */
30211 
30212 /*******************  Bit definition for SPI_RXCRC register  ********************/
30213 #define SPI_RXCRC_RXCRC_Pos                 (0U)
30214 #define SPI_RXCRC_RXCRC_Msk                 (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)   /*!< 0xFFFFFFFF */
30215 #define SPI_RXCRC_RXCRC                     SPI_RXCRC_RXCRC_Msk                     /* CRCRegister for receiver */
30216 
30217 /*******************  Bit definition for SPI_UDRDR register  ********************/
30218 #define SPI_UDRDR_UDRDR_Pos                 (0U)
30219 #define SPI_UDRDR_UDRDR_Msk                 (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)   /*!< 0xFFFFFFFF */
30220 #define SPI_UDRDR_UDRDR                     SPI_UDRDR_UDRDR_Msk                     /* Data at slave underrun condition */
30221 
30222 /******************************************************************************/
30223 /*                                                                            */
30224 /*                                 VREFBUF                                    */
30225 /*                                                                            */
30226 /******************************************************************************/
30227 /*******************  Bit definition for VREFBUF_CSR register  ****************/
30228 #define VREFBUF_CSR_ENVR_Pos    (0U)
30229 #define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                     /*!< 0x00000001 */
30230 #define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                                /*!<Voltage reference buffer enable */
30231 #define VREFBUF_CSR_HIZ_Pos     (1U)
30232 #define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                      /*!< 0x00000002 */
30233 #define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                                 /*!<High impedance mode             */
30234 #define VREFBUF_CSR_VRS_Pos     (4U)
30235 #define VREFBUF_CSR_VRS_Msk     (0x7UL << VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000004 */
30236 #define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                                 /*!<Voltage reference scale         */
30237 #define VREFBUF_CSR_VRS_0       (0x01UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x000O0010 */
30238 #define VREFBUF_CSR_VRS_1       (0x02UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000020 */
30239 #define VREFBUF_CSR_VRS_2       (0x04UL<< VREFBUF_CSR_VRS_Pos)                      /*!< 0x00000040 */
30240 #define VREFBUF_CSR_VRR_Pos     (3U)
30241 #define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                      /*!< 0x00000008 */
30242 #define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                                 /*!<Voltage reference buffer ready  */
30243 
30244 /*******************  Bit definition for VREFBUF_CCR register  ******************/
30245 #define VREFBUF_CCR_TRIM_Pos                (0U)
30246 #define VREFBUF_CCR_TRIM_Msk                (0x3FUL << VREFBUF_CCR_TRIM_Pos)        /*!< 0x0000003F */
30247 #define VREFBUF_CCR_TRIM                    VREFBUF_CCR_TRIM_Msk                    /*!<TRIM[5:0] bits (Trimming code)  */
30248 
30249 /******************************************************************************/
30250 /*                                                                            */
30251 /*                            Window WATCHDOG                                 */
30252 /*                                                                            */
30253 /******************************************************************************/
30254 /*******************  Bit definition for WWDG_CR register  ********************/
30255 #define WWDG_CR_T_Pos                       (0U)
30256 #define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)               /*!< 0x0000007F */
30257 #define WWDG_CR_T                           WWDG_CR_T_Msk                           /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
30258 #define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)               /*!< 0x00000001 */
30259 #define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)               /*!< 0x00000002 */
30260 #define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)               /*!< 0x00000004 */
30261 #define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)               /*!< 0x00000008 */
30262 #define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)               /*!< 0x00000010 */
30263 #define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)               /*!< 0x00000020 */
30264 #define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)               /*!< 0x00000040 */
30265 #define WWDG_CR_WDGA_Pos                    (7U)
30266 #define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)             /*!< 0x00000080 */
30267 #define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                        /*!<Activation bit */
30268 
30269 /*******************  Bit definition for WWDG_CFR register  *******************/
30270 #define WWDG_CFR_W_Pos                      (0U)
30271 #define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)              /*!< 0x0000007F */
30272 #define WWDG_CFR_W                          WWDG_CFR_W_Msk                          /*!<W[6:0] bits (7-bit window value) */
30273 #define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)              /*!< 0x00000001 */
30274 #define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)              /*!< 0x00000002 */
30275 #define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)              /*!< 0x00000004 */
30276 #define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)              /*!< 0x00000008 */
30277 #define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)              /*!< 0x00000010 */
30278 #define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)              /*!< 0x00000020 */
30279 #define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)              /*!< 0x00000040 */
30280 #define WWDG_CFR_WDGTB_Pos                  (11U)
30281 #define WWDG_CFR_WDGTB_Msk                  (0x7UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00003800 */
30282 #define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                      /*!<WDGTB[2:0] bits (Timer Base) */
30283 #define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00000800 */
30284 #define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00001000 */
30285 #define WWDG_CFR_WDGTB_2                    (0x4UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00002000 */
30286 #define WWDG_CFR_EWI_Pos                    (9U)
30287 #define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)             /*!< 0x00000200 */
30288 #define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                        /*!<Early Wakeup Interrupt */
30289 
30290 /*******************  Bit definition for WWDG_SR register  ********************/
30291 #define WWDG_SR_EWIF_Pos                    (0U)
30292 #define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)             /*!< 0x00000001 */
30293 #define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                        /*!<Early Wakeup Interrupt Flag */
30294 
30295 /******************************************************************************/
30296 /*                                                                            */
30297 /*                       Public Key Accelerator (PKA)                         */
30298 /*                                                                            */
30299 /******************************************************************************/
30300 /*******************  Bit definition for PKA_CR register  *********************/
30301 #define PKA_CR_EN_Pos                       (0U)
30302 #define PKA_CR_EN_Msk                       (0x1UL << PKA_CR_EN_Pos)                       /*!< 0x00000001 */
30303 #define PKA_CR_EN                           PKA_CR_EN_Msk                                  /*!< PKA enable */
30304 #define PKA_CR_START_Pos                    (1U)
30305 #define PKA_CR_START_Msk                    (0x1UL << PKA_CR_START_Pos)                    /*!< 0x00000002 */
30306 #define PKA_CR_START                        PKA_CR_START_Msk                               /*!< Start operation */
30307 #define PKA_CR_MODE_Pos                     (8U)
30308 #define PKA_CR_MODE_Msk                     (0x3FUL << PKA_CR_MODE_Pos)                    /*!< 0x00003F00 */
30309 #define PKA_CR_MODE                         PKA_CR_MODE_Msk                                /*!< MODE[5:0] PKA operation code */
30310 #define PKA_CR_MODE_0                       (0x01UL << PKA_CR_MODE_Pos)                    /*!< 0x00000100 */
30311 #define PKA_CR_MODE_1                       (0x02UL << PKA_CR_MODE_Pos)                    /*!< 0x00000200 */
30312 #define PKA_CR_MODE_2                       (0x04UL << PKA_CR_MODE_Pos)                    /*!< 0x00000400 */
30313 #define PKA_CR_MODE_3                       (0x08UL << PKA_CR_MODE_Pos)                    /*!< 0x00000800 */
30314 #define PKA_CR_MODE_4                       (0x10UL << PKA_CR_MODE_Pos)                    /*!< 0x00001000 */
30315 #define PKA_CR_MODE_5                       (0x20UL << PKA_CR_MODE_Pos)                    /*!< 0x00002000 */
30316 #define PKA_CR_PROCENDIE_Pos                (17U)
30317 #define PKA_CR_PROCENDIE_Msk                (0x1UL << PKA_CR_PROCENDIE_Pos)                /*!< 0x00020000 */
30318 #define PKA_CR_PROCENDIE                    PKA_CR_PROCENDIE_Msk                           /*!< End of operation interrupt enable */
30319 #define PKA_CR_RAMERRIE_Pos                 (19U)
30320 #define PKA_CR_RAMERRIE_Msk                 (0x1UL << PKA_CR_RAMERRIE_Pos)                 /*!< 0x00080000 */
30321 #define PKA_CR_RAMERRIE                     PKA_CR_RAMERRIE_Msk                            /*!< RAM error interrupt enable */
30322 #define PKA_CR_ADDRERRIE_Pos                (20U)
30323 #define PKA_CR_ADDRERRIE_Msk                (0x1UL << PKA_CR_ADDRERRIE_Pos)                /*!< 0x00100000 */
30324 #define PKA_CR_ADDRERRIE                    PKA_CR_ADDRERRIE_Msk                           /*!< Address error interrupt enable */
30325 #define PKA_CR_OPERRIE_Pos                  (21U)
30326 #define PKA_CR_OPERRIE_Msk                  (0x1UL << PKA_CR_OPERRIE_Pos)                  /*!< 0x00200000 */
30327 #define PKA_CR_OPERRIE                      PKA_CR_OPERRIE_Msk                             /*!< Operation Error interrupt enable */
30328 
30329 /*******************  Bit definition for PKA_SR register  *********************/
30330 #define PKA_SR_INITOK_Pos                   (0U)
30331 #define PKA_SR_INITOK_Msk                   (0x1UL << PKA_SR_INITOK_Pos)                   /*!< 0x00000001 */
30332 #define PKA_SR_INITOK                       PKA_SR_INITOK_Msk                              /*!< PKA initialisation flag */
30333 #define PKA_SR_BUSY_Pos                     (16U)
30334 #define PKA_SR_BUSY_Msk                     (0x1UL << PKA_SR_BUSY_Pos)                     /*!< 0x00010000 */
30335 #define PKA_SR_BUSY                         PKA_SR_BUSY_Msk                                /*!< PKA operation is in progress */
30336 #define PKA_SR_PROCENDF_Pos                 (17U)
30337 #define PKA_SR_PROCENDF_Msk                 (0x1UL << PKA_SR_PROCENDF_Pos)                 /*!< 0x00020000 */
30338 #define PKA_SR_PROCENDF                     PKA_SR_PROCENDF_Msk                            /*!< PKA end of operation flag */
30339 #define PKA_SR_RAMERRF_Pos                  (19U)
30340 #define PKA_SR_RAMERRF_Msk                  (0x1UL << PKA_SR_RAMERRF_Pos)                  /*!< 0x00080000 */
30341 #define PKA_SR_RAMERRF                      PKA_SR_RAMERRF_Msk                             /*!< PKA RAM error flag */
30342 #define PKA_SR_ADDRERRF_Pos                 (20U)
30343 #define PKA_SR_ADDRERRF_Msk                 (0x1UL << PKA_SR_ADDRERRF_Pos)                 /*!< 0x00100000 */
30344 #define PKA_SR_ADDRERRF                     PKA_SR_ADDRERRF_Msk                            /*!< Address error flag */
30345 #define PKA_SR_OPERRF_Pos                   (21U)
30346 #define PKA_SR_OPERRF_Msk                   (0x1UL << PKA_SR_OPERRF_Pos)                   /*!< 0x00200000 */
30347 #define PKA_SR_OPERRF                       PKA_SR_OPERRF_Msk                              /*!< PKA operation Error flag*/
30348 
30349 /*******************  Bit definition for PKA_CLRFR register  ******************/
30350 #define PKA_CLRFR_PROCENDFC_Pos             (17U)
30351 #define PKA_CLRFR_PROCENDFC_Msk             (0x1UL << PKA_CLRFR_PROCENDFC_Pos)             /*!< 0x00020000 */
30352 #define PKA_CLRFR_PROCENDFC                 PKA_CLRFR_PROCENDFC_Msk                        /*!< Clear PKA end of operation flag */
30353 #define PKA_CLRFR_RAMERRFC_Pos              (19U)
30354 #define PKA_CLRFR_RAMERRFC_Msk              (0x1UL << PKA_CLRFR_RAMERRFC_Pos)              /*!< 0x00080000 */
30355 #define PKA_CLRFR_RAMERRFC                  PKA_CLRFR_RAMERRFC_Msk                         /*!< Clear PKA RAM error flag */
30356 #define PKA_CLRFR_ADDRERRFC_Pos             (20U)
30357 #define PKA_CLRFR_ADDRERRFC_Msk             (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)             /*!< 0x00100000 */
30358 #define PKA_CLRFR_ADDRERRFC                 PKA_CLRFR_ADDRERRFC_Msk                        /*!< Clear address error flag */
30359 #define PKA_CLRFR_OPERRFC_Pos               (21U)
30360 #define PKA_CLRFR_OPERRFC_Msk               (0x1UL << PKA_CLRFR_OPERRFC_Pos)               /*!< 0x00200000 */
30361 #define PKA_CLRFR_OPERRFC                   PKA_CLRFR_OPERRFC_Msk                          /*!< Clear PKA operation Error flag*/
30362 
30363 /*******************  Bits definition for PKA RAM  *************************/
30364 #define PKA_RAM_OFFSET                                 (0x0400UL)                          /*!< PKA RAM address offset */
30365 
30366 /* Compute Montgomery parameter input data */
30367 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
30368 #define PKA_MONTGOMERY_PARAM_IN_MODULUS                ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
30369 
30370 /* Compute Montgomery parameter output data */
30371 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER             ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output Montgomery parameter */
30372 
30373 /* Compute modular exponentiation input data */
30374 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent number of bits */
30375 #define PKA_MODULAR_EXP_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
30376 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM            ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
30377 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE               ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
30378 #define PKA_MODULAR_EXP_IN_EXPONENT                    ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process */
30379 #define PKA_MODULAR_EXP_IN_MODULUS                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
30380 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE       ((0x16C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the protected exponentiation */
30381 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT            ((0x14B8UL - PKA_RAM_OFFSET)>>2)    /*!< Input exponent to process protected exponentiation*/
30382 #define PKA_MODULAR_EXP_PROTECT_IN_MODULUS             ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus to process protected exponentiation */
30383 #define PKA_MODULAR_EXP_PROTECT_IN_PHI                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input phi to process protected exponentiation */
30384 
30385 /* Compute modular exponentiation output data */
30386 #define PKA_MODULAR_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result of the exponentiation */
30387 #define PKA_MODULAR_EXP_OUT_ERROR                      ((0x1298UL - PKA_RAM_OFFSET)>>2)    /*!< Output error of the exponentiation */
30388 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM           ((0x0620UL - PKA_RAM_OFFSET)>>2)    /*!< Output storage area for Montgomery parameter */
30389 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE              ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Output base of the exponentiation */
30390 
30391 /* Compute ECC scalar multiplication input data */
30392 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS              ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input curve prime order n number of bits */
30393 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
30394 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN             ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
30395 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF                  ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
30396 #define PKA_ECC_SCALAR_MUL_IN_B_COEFF                  ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
30397 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF                   ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
30398 #define PKA_ECC_SCALAR_MUL_IN_K                        ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' of KP */
30399 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X          ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
30400 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y          ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
30401 #define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER            ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input prime order n */
30402 
30403 /* Compute ECC scalar multiplication output data */
30404 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X                ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate */
30405 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y                ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate */
30406 #define PKA_ECC_SCALAR_MUL_OUT_ERROR                   ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */
30407 
30408 /* Point check input data */
30409 #define PKA_POINT_CHECK_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
30410 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN                ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
30411 #define PKA_POINT_CHECK_IN_A_COEFF                     ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
30412 #define PKA_POINT_CHECK_IN_B_COEFF                     ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
30413 #define PKA_POINT_CHECK_IN_MOD_GF                      ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
30414 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
30415 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y             ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
30416 #define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM            ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
30417 
30418 /* Point check output data */
30419 #define PKA_POINT_CHECK_OUT_ERROR                      ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
30420 
30421 /* ECDSA signature input data */
30422 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS                ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
30423 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
30424 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN                 ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
30425 #define PKA_ECDSA_SIGN_IN_A_COEFF                      ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
30426 #define PKA_ECDSA_SIGN_IN_B_COEFF                      ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'b' coefficient */
30427 #define PKA_ECDSA_SIGN_IN_MOD_GF                       ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
30428 #define PKA_ECDSA_SIGN_IN_K                            ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input k value of the ECDSA */
30429 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X              ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
30430 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y              ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
30431 #define PKA_ECDSA_SIGN_IN_HASH_E                       ((0x0FE8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
30432 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D                ((0x0F28UL - PKA_RAM_OFFSET)>>2)    /*!< Input d, private key */
30433 #define PKA_ECDSA_SIGN_IN_ORDER_N                      ((0x0F88UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
30434 
30435 /* ECDSA signature output data */
30436 #define PKA_ECDSA_SIGN_OUT_ERROR                       ((0x0FE0UL - PKA_RAM_OFFSET)>>2)    /*!< Output error */
30437 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R                 ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature r */
30438 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S                 ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Output signature s */
30439 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X               ((0x1400UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point X coordinate */
30440 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y               ((0x1458UL - PKA_RAM_OFFSET)>>2)    /*!< Extended output result point Y coordinate */
30441 
30442 /* ECDSA verification input data */
30443 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input order number of bits */
30444 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS                 ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus number of bits */
30445 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN                ((0x0468UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
30446 #define PKA_ECDSA_VERIF_IN_A_COEFF                     ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve 'a' coefficient */
30447 #define PKA_ECDSA_VERIF_IN_MOD_GF                      ((0x04D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
30448 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X             ((0x0678UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
30449 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y             ((0x06D0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
30450 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X          ((0x12F8UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point X coordinate */
30451 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y          ((0x1350UL - PKA_RAM_OFFSET)>>2)    /*!< Input public key point Y coordinate */
30452 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R                 ((0x10E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input r, part of the signature */
30453 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S                 ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input s, part of the signature */
30454 #define PKA_ECDSA_VERIF_IN_HASH_E                      ((0x13A8UL - PKA_RAM_OFFSET)>>2)    /*!< Input e, hash of the message */
30455 #define PKA_ECDSA_VERIF_IN_ORDER_N                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
30456 
30457 /* ECDSA verification output data */
30458 #define PKA_ECDSA_VERIF_OUT_RESULT                     ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
30459 
30460 /* RSA CRT exponentiation input data */
30461 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operands number of bits */
30462 #define PKA_RSA_CRT_EXP_IN_DP_CRT                      ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dp CRT parameter */
30463 #define PKA_RSA_CRT_EXP_IN_DQ_CRT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Input Dq CRT parameter */
30464 #define PKA_RSA_CRT_EXP_IN_QINV_CRT                    ((0x0948UL - PKA_RAM_OFFSET)>>2)    /*!< Input qInv CRT parameter */
30465 #define PKA_RSA_CRT_EXP_IN_PRIME_P                     ((0x0B60UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime p */
30466 #define PKA_RSA_CRT_EXP_IN_PRIME_Q                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input Prime q */
30467 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE               ((0x12A0UL - PKA_RAM_OFFSET)>>2)    /*!< Input base of the exponentiation */
30468 
30469 /* RSA CRT exponentiation output data */
30470 #define PKA_RSA_CRT_EXP_OUT_RESULT                     ((0x0838UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
30471 
30472 /* Modular reduction input data */
30473 #define PKA_MODULAR_REDUC_IN_OP_LENGTH                 ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand length */
30474 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH                ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus length */
30475 #define PKA_MODULAR_REDUC_IN_OPERAND                   ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand */
30476 #define PKA_MODULAR_REDUC_IN_MODULUS                   ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
30477 
30478 /* Modular reduction output data */
30479 #define PKA_MODULAR_REDUC_OUT_RESULT                   ((0xE78UL - PKA_RAM_OFFSET)>>2)     /*!< Output result */
30480 
30481 /* Arithmetic addition input data */
30482 #define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
30483 #define PKA_ARITHMETIC_ADD_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
30484 #define PKA_ARITHMETIC_ADD_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
30485 
30486 /* Arithmetic addition output data */
30487 #define PKA_ARITHMETIC_ADD_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
30488 
30489 /* Arithmetic subtraction input data */
30490 #define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
30491 #define PKA_ARITHMETIC_SUB_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
30492 #define PKA_ARITHMETIC_SUB_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
30493 
30494 /* Arithmetic subtraction output data */
30495 #define PKA_ARITHMETIC_SUB_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
30496 
30497 /* Arithmetic multiplication input data */
30498 #define PKA_ARITHMETIC_MUL_NB_BITS                     ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
30499 #define PKA_ARITHMETIC_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
30500 #define PKA_ARITHMETIC_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
30501 
30502 /* Arithmetic multiplication output data */
30503 #define PKA_ARITHMETIC_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
30504 
30505 /* Comparison input data */
30506 #define PKA_COMPARISON_IN_OP_NB_BITS                   ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
30507 #define PKA_COMPARISON_IN_OP1                          ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
30508 #define PKA_COMPARISON_IN_OP2                          ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
30509 
30510 /* Comparison output data */
30511 #define PKA_COMPARISON_OUT_RESULT                      ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
30512 
30513 /* Modular addition input data */
30514 #define PKA_MODULAR_ADD_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
30515 #define PKA_MODULAR_ADD_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
30516 #define PKA_MODULAR_ADD_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
30517 #define PKA_MODULAR_ADD_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op3 (modulus) */
30518 
30519 /* Modular addition output data */
30520 #define PKA_MODULAR_ADD_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
30521 
30522 /* Modular inversion input data */
30523 #define PKA_MODULAR_INV_NB_BITS                        ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
30524 #define PKA_MODULAR_INV_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
30525 #define PKA_MODULAR_INV_IN_OP2_MOD                     ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 (modulus) */
30526 
30527 /* Modular inversion output data */
30528 #define PKA_MODULAR_INV_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
30529 
30530 /* Modular subtraction input data */
30531 #define PKA_MODULAR_SUB_IN_OP_NB_BITS                  ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
30532 #define PKA_MODULAR_SUB_IN_OP1                         ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
30533 #define PKA_MODULAR_SUB_IN_OP2                         ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
30534 #define PKA_MODULAR_SUB_IN_OP3_MOD                     ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op3 */
30535 
30536 /* Modular subtraction output data */
30537 #define PKA_MODULAR_SUB_OUT_RESULT                     ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
30538 
30539 /* Montgomery multiplication input data */
30540 #define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS               ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
30541 #define PKA_MONTGOMERY_MUL_IN_OP1                      ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
30542 #define PKA_MONTGOMERY_MUL_IN_OP2                      ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
30543 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD                  ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus */
30544 
30545 /* Montgomery multiplication output data */
30546 #define PKA_MONTGOMERY_MUL_OUT_RESULT                  ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result */
30547 
30548 /* Generic Arithmetic input data */
30549 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS                 ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand number of bits */
30550 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1                  ((0x0A50UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op1 */
30551 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2                  ((0x0C68UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
30552 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3                  ((0x1088UL - PKA_RAM_OFFSET)>>2)    /*!< Input operand op2 */
30553 
30554 /* Generic Arithmetic output data */
30555 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT              ((0x0E78UL - PKA_RAM_OFFSET)>>2)    /*!< Output result for arithmetic operations */
30556 
30557 /* Compute ECC complete addition input data */
30558 #define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS            ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
30559 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN           ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
30560 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF                ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve '|a|' coefficient */
30561 #define PKA_ECC_COMPLETE_ADD_IN_MOD_P                  ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
30562 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_X               ((0x0628UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
30563 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y               ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
30564 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z               ((0x06D8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Z coordinate */
30565 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_X               ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q X coordinate */
30566 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y               ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Y coordinate */
30567 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z               ((0x07E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Z coordinate */
30568 
30569 /* Compute ECC complete addition output data */
30570 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X              ((0x0D60UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate */
30571 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y              ((0x0DB8UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate */
30572 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z              ((0x0E10UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Z coordinate */
30573 
30574 /* Compute ECC double base ladder input data */
30575 #define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS   ((0x0400UL - PKA_RAM_OFFSET)>>2)    /*!< Input n, order of the curve */
30576 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS           ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
30577 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN          ((0x0410UL - PKA_RAM_OFFSET)>>2)    /*!< Input sign of the 'a' coefficient */
30578 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF               ((0x0418UL - PKA_RAM_OFFSET)>>2)    /*!< Input ECC curve '|a|' coefficient */
30579 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_P                 ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
30580 #define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER             ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'k' integer coefficient */
30581 #define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Input 'm' integer coefficient */
30582 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X              ((0x0628UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P X coordinate */
30583 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y              ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Y coordinate */
30584 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z              ((0x06D8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point P Z coordinate */
30585 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X              ((0x0730UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q X coordinate */
30586 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y              ((0x0788UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Y coordinate */
30587 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z              ((0x07E0UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial point Q Z coordinate */
30588 
30589 /* Compute ECC double base ladder output data */
30590 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X             ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result X coordinate (affine coordinate) */
30591 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y             ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result Y coordinate (affine coordinate) */
30592 #define PKA_ECC_DOUBLE_LADDER_OUT_ERROR                ((0x0520UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */
30593 
30594 /* Compute ECC projective to affine conversion input data */
30595 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS          ((0x0408UL - PKA_RAM_OFFSET)>>2)    /*!< Input Modulus number of bits */
30596 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P                ((0x0470UL - PKA_RAM_OFFSET)>>2)    /*!< Input modulus GF(p) */
30597 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X              ((0x0D60UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial projective point P X coordinate */
30598 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y              ((0x0DB8UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial projective point P Y coordinate */
30599 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z              ((0x0E10UL - PKA_RAM_OFFSET)>>2)    /*!< Input initial projective point P Z coordinate */
30600 #define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2  ((0x04C8UL - PKA_RAM_OFFSET)>>2)    /*!< Input storage area for Montgomery parameter */
30601 
30602 /* Compute ECC projective to affine conversion output data */
30603 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X            ((0x0578UL - PKA_RAM_OFFSET)>>2)    /*!< Output result x affine coordinate */
30604 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y            ((0x05D0UL - PKA_RAM_OFFSET)>>2)    /*!< Output result y affine coordinate */
30605 #define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR               ((0x0680UL - PKA_RAM_OFFSET)>>2)    /*!< Output result error */
30606 
30607 /** @addtogroup STM32U5xx_Peripheral_Exported_macros
30608   * @{
30609   */
30610 
30611 /******************************* ADC Instances ********************************/
30612 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) ||                   \
30613                                        ((INSTANCE) == ADC1_S)  ||                   \
30614                                        ((INSTANCE) == ADC2_NS) ||                   \
30615                                        ((INSTANCE) == ADC2_S)  ||                   \
30616                                        ((INSTANCE) == ADC4_NS) ||                   \
30617                                        ((INSTANCE) == ADC4_S))
30618 
30619 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \
30620                                                     ((INSTANCE) == ADC1_S))
30621 
30622 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) ||         \
30623                                           ((INSTANCE) == ADC12_COMMON_S)  ||         \
30624                                           ((INSTANCE) == ADC4_COMMON_NS)  ||         \
30625                                           ((INSTANCE) == ADC4_COMMON_S))
30626 
30627 /******************************* AES Instances ********************************/
30628 #define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S))
30629 
30630 /******************************* PKA Instances ********************************/
30631 #define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S))
30632 
30633 /******************************** FDCAN Instances *****************************/
30634 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S))
30635 
30636 /******************************** COMP Instances ******************************/
30637 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \
30638                                         ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S))
30639 
30640 /******************** COMP Instances with window mode capability **************/
30641 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \
30642                                                ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S))
30643 
30644 /******************************* CORDIC Instances *****************************/
30645 #define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S))
30646 
30647 /******************************* CRC Instances ********************************/
30648 #define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S))
30649 
30650 /******************************* DAC Instances ********************************/
30651 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S))
30652 
30653 /******************************* DELAYBLOCK Instances *******************************/
30654 #define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1_NS)   || \
30655                                          ((INSTANCE) == DLYB_SDMMC2_NS)   || \
30656                                          ((INSTANCE) == DLYB_SDMMC1_S)    || \
30657                                          ((INSTANCE) == DLYB_SDMMC2_S)    || \
30658                                          ((INSTANCE) == DLYB_OCTOSPI1_NS) || \
30659                                          ((INSTANCE) == DLYB_OCTOSPI2_NS) || \
30660                                          ((INSTANCE) == DLYB_OCTOSPI1_S)  || \
30661                                          ((INSTANCE) == DLYB_OCTOSPI2_S ))
30662 
30663 /******************************** DMA Instances *******************************/
30664 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || ((INSTANCE) == GPDMA1_Channel0_S)  || \
30665                                        ((INSTANCE) == GPDMA1_Channel1_NS)  || ((INSTANCE) == GPDMA1_Channel1_S)  || \
30666                                        ((INSTANCE) == GPDMA1_Channel2_NS)  || ((INSTANCE) == GPDMA1_Channel2_S)  || \
30667                                        ((INSTANCE) == GPDMA1_Channel3_NS)  || ((INSTANCE) == GPDMA1_Channel3_S)  || \
30668                                        ((INSTANCE) == GPDMA1_Channel4_NS)  || ((INSTANCE) == GPDMA1_Channel4_S)  || \
30669                                        ((INSTANCE) == GPDMA1_Channel5_NS)  || ((INSTANCE) == GPDMA1_Channel5_S)  || \
30670                                        ((INSTANCE) == GPDMA1_Channel6_NS)  || ((INSTANCE) == GPDMA1_Channel6_S)  || \
30671                                        ((INSTANCE) == GPDMA1_Channel7_NS)  || ((INSTANCE) == GPDMA1_Channel7_S)  || \
30672                                        ((INSTANCE) == GPDMA1_Channel8_NS)  || ((INSTANCE) == GPDMA1_Channel8_S)  || \
30673                                        ((INSTANCE) == GPDMA1_Channel9_NS)  || ((INSTANCE) == GPDMA1_Channel9_S)  || \
30674                                        ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \
30675                                        ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \
30676                                        ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \
30677                                        ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \
30678                                        ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \
30679                                        ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \
30680                                        ((INSTANCE) == LPDMA1_Channel0_NS)  || ((INSTANCE) == LPDMA1_Channel0_S)  || \
30681                                        ((INSTANCE) == LPDMA1_Channel1_NS)  || ((INSTANCE) == LPDMA1_Channel1_S)  || \
30682                                        ((INSTANCE) == LPDMA1_Channel2_NS)  || ((INSTANCE) == LPDMA1_Channel2_S)  || \
30683                                        ((INSTANCE) == LPDMA1_Channel3_NS)  || ((INSTANCE) == LPDMA1_Channel3_S))
30684 
30685 #define IS_GPDMA_INSTANCE(INSTANCE)   (((INSTANCE) == GPDMA1_Channel0_NS)  || ((INSTANCE) == GPDMA1_Channel0_S)  || \
30686                                        ((INSTANCE) == GPDMA1_Channel1_NS)  || ((INSTANCE) == GPDMA1_Channel1_S)  || \
30687                                        ((INSTANCE) == GPDMA1_Channel2_NS)  || ((INSTANCE) == GPDMA1_Channel2_S)  || \
30688                                        ((INSTANCE) == GPDMA1_Channel3_NS)  || ((INSTANCE) == GPDMA1_Channel3_S)  || \
30689                                        ((INSTANCE) == GPDMA1_Channel4_NS)  || ((INSTANCE) == GPDMA1_Channel4_S)  || \
30690                                        ((INSTANCE) == GPDMA1_Channel5_NS)  || ((INSTANCE) == GPDMA1_Channel5_S)  || \
30691                                        ((INSTANCE) == GPDMA1_Channel6_NS)  || ((INSTANCE) == GPDMA1_Channel6_S)  || \
30692                                        ((INSTANCE) == GPDMA1_Channel7_NS)  || ((INSTANCE) == GPDMA1_Channel7_S)  || \
30693                                        ((INSTANCE) == GPDMA1_Channel8_NS)  || ((INSTANCE) == GPDMA1_Channel8_S)  || \
30694                                        ((INSTANCE) == GPDMA1_Channel9_NS)  || ((INSTANCE) == GPDMA1_Channel9_S)  || \
30695                                        ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \
30696                                        ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \
30697                                        ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \
30698                                        ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \
30699                                        ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \
30700                                        ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S))
30701 
30702 #define IS_LPDMA_INSTANCE(INSTANCE)   (((INSTANCE) == LPDMA1_Channel0_NS)  || ((INSTANCE) == LPDMA1_Channel0_S)  || \
30703                                        ((INSTANCE) == LPDMA1_Channel1_NS)  || ((INSTANCE) == LPDMA1_Channel1_S)  || \
30704                                        ((INSTANCE) == LPDMA1_Channel2_NS)  || ((INSTANCE) == LPDMA1_Channel2_S)  || \
30705                                        ((INSTANCE) == LPDMA1_Channel3_NS)  || ((INSTANCE) == LPDMA1_Channel3_S))
30706 
30707 #define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS)  || ((INSTANCE) == GPDMA1_Channel12_S)  || \
30708                                                  ((INSTANCE) == GPDMA1_Channel13_NS)  || ((INSTANCE) == GPDMA1_Channel13_S)  || \
30709                                                  ((INSTANCE) == GPDMA1_Channel14_NS)  || ((INSTANCE) == GPDMA1_Channel14_S)  || \
30710                                                  ((INSTANCE) == GPDMA1_Channel15_NS)  || ((INSTANCE) == GPDMA1_Channel15_S))
30711 
30712 /****************************** OTFDEC Instances ********************************/
30713 #define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S)  || \
30714                                           ((INSTANCE) == OTFDEC2_NS) || ((INSTANCE) == OTFDEC2_S))
30715 
30716 /****************************** RAMCFG Instances ********************************/
30717 #define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS)  || ((INSTANCE) == RAMCFG_SRAM1_S)  || \
30718                                           ((INSTANCE) == RAMCFG_SRAM2_NS)  || ((INSTANCE) == RAMCFG_SRAM2_S)  || \
30719                                           ((INSTANCE) == RAMCFG_SRAM3_NS)  || ((INSTANCE) == RAMCFG_SRAM3_S)  || \
30720                                           ((INSTANCE) == RAMCFG_SRAM4_NS)  || ((INSTANCE) == RAMCFG_SRAM4_S)  || \
30721                                           ((INSTANCE) == RAMCFG_SRAM5_NS)  || ((INSTANCE) == RAMCFG_SRAM5_S)  || \
30722                                           ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S) || \
30723                                           ((INSTANCE) == RAMCFG_SRAM6_NS)  || ((INSTANCE) == RAMCFG_SRAM6_S))
30724 
30725 /***************************** RAMCFG ECC Instances *****************************/
30726 #define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS)  || ((INSTANCE) == RAMCFG_SRAM2_S)  || \
30727                                           ((INSTANCE) == RAMCFG_SRAM3_NS)  || ((INSTANCE) == RAMCFG_SRAM3_S)  || \
30728                                           ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S))
30729 
30730 /***************************** RAMCFG IT Instances ******************************/
30731 #define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS)  || ((INSTANCE) == RAMCFG_SRAM2_S)  || \
30732                                          ((INSTANCE) == RAMCFG_SRAM3_NS)  || ((INSTANCE) == RAMCFG_SRAM3_S)  || \
30733                                          ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S))
30734 
30735 /************************ RAMCFG Write Protection Instances *********************/
30736 #define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS)  || ((INSTANCE) == RAMCFG_SRAM2_S))
30737 
30738 /******************************** FMAC Instances ******************************/
30739 #define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S))
30740 
30741 /******************************* GFXMMU Instances *******************************/
30742 #define IS_GFXMMU_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXMMU_NS) || ((INSTANCE) == GFXMMU_S))
30743 
30744 /******************************* GPIO Instances *******************************/
30745 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \
30746                                         ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \
30747                                         ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \
30748                                         ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \
30749                                         ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \
30750                                         ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \
30751                                         ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \
30752                                         ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \
30753                                         ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S) || \
30754                                         ((INSTANCE) == GPIOJ_NS) || ((INSTANCE) == GPIOJ_S) || \
30755                                         ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S))
30756 
30757 /******************************* LPGPIO Instances *****************************/
30758 #define IS_LPGPIO_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S))
30759 
30760 /****************************** LTDC Instances ********************************/
30761 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == LTDC_NS) || ((__INSTANCE__) == LTDC_S))
30762 
30763 /****************************** DSI Instances ********************************/
30764 #define IS_DSI_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == DSI_NS) || ((__INSTANCE__) == DSI_S))
30765 
30766 /******************************* DMA2D Instances *******************************/
30767 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA2D_NS) || ((__INSTANCE__) == DMA2D_S))
30768 
30769 /******************************* DCMI Instances *******************************/
30770 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S))
30771 
30772 /******************************* DCACHE Instances *****************************/
30773 #define IS_DCACHE_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S) || \
30774                                            ((INSTANCE) == DCACHE2_NS) || ((INSTANCE) == DCACHE2_S))
30775 
30776 /******************************* PSSI Instances *******************************/
30777 #define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S))
30778 
30779 /******************************* GPIO AF Instances ****************************/
30780 /* On U5, all GPIO Bank support AF */
30781 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
30782 
30783 /**************************** GPIO Lock Instances *****************************/
30784 /* On U5, all GPIO Bank support the Lock mechanism */
30785 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
30786 
30787 /******************************** I2C Instances *******************************/
30788 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
30789                                        ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \
30790                                        ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \
30791                                        ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \
30792                                        ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \
30793                                        ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S))
30794 
30795 /****************** I2C Instances : wakeup capability from stop modes *********/
30796 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
30797 
30798 /******************* I2C Instances : Group belongingness *********************/
30799 #define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
30800                                         ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \
30801                                         ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \
30802                                         ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \
30803                                         ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S))
30804 
30805 #define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S))
30806 
30807 /****************************** OPAMP Instances *******************************/
30808 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S) || \
30809                                          ((INSTANCE) == OPAMP2_NS) || ((INSTANCE) == OPAMP2_S))
30810 
30811 /******************************* OSPI Instances *******************************/
30812 #define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S) || \
30813                                         ((INSTANCE) == OCTOSPI2_NS) || ((INSTANCE) == OCTOSPI2_S))
30814 
30815 /******************************* HSPI Instances *******************************/
30816 #define IS_HSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HSPI1_NS) || ((INSTANCE) == HSPI1_S))
30817 
30818 /******************************* RNG Instances ********************************/
30819 #define IS_RNG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S))
30820 
30821 /****************************** RTC Instances *********************************/
30822 #define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S))
30823 
30824 /******************************** SAI Instances *******************************/
30825 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \
30826                                        ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \
30827                                        ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \
30828                                        ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S))
30829 
30830 /****************************** SDMMC Instances *******************************/
30831 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \
30832                                          ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S))
30833 
30834 /****************************** SMBUS Instances *******************************/
30835 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
30836                                          ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \
30837                                          ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \
30838                                          ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \
30839                                          ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \
30840                                          ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S))
30841 
30842 /******************* SMBUS Instances : Group belongingness *********************/
30843 #define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \
30844                                           ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \
30845                                           ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \
30846                                           ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \
30847                                           ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S))
30848 
30849 #define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S))
30850 
30851 /******************************** SPI Instances *******************************/
30852 #define IS_SPI_ALL_INSTANCE(INSTANCE)     (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
30853                                            ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \
30854                                            ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))
30855 
30856 #define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))
30857 
30858 #define IS_SPI_FULL_INSTANCE(INSTANCE)    (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
30859                                            ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S))
30860 
30861 #define IS_SPI_GRP1_INSTANCE(INSTANCE)    (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \
30862                                            ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S))
30863 
30864 #define IS_SPI_GRP2_INSTANCE(INSTANCE)    (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S))
30865 
30866 /****************** LPTIM Instances : All supported instances *****************/
30867 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
30868                                          ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
30869                                          ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\
30870                                          ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S))
30871 
30872 /****************** LPTIM Instances : DMA supported instances *****************/
30873 #define IS_LPTIM_DMA_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
30874                                           ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
30875                                           ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S))
30876 
30877 /************* LPTIM Instances : at least 1 capture/compare channel ***********/
30878 #define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS)  || ((INSTANCE) == LPTIM1_S) ||\
30879                                          ((INSTANCE) == LPTIM2_NS)  || ((INSTANCE) == LPTIM2_S) ||\
30880                                          ((INSTANCE) == LPTIM3_NS)  || ((INSTANCE) == LPTIM3_S) ||\
30881                                          ((INSTANCE) == LPTIM4_NS)  || ((INSTANCE) == LPTIM4_S))
30882 
30883 /************* LPTIM Instances : at least 2 capture/compare channel ***********/
30884 #define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
30885                                          ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
30886                                          ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S))
30887 
30888 /****************** LPTIM Instances : supporting encoder interface **************/
30889 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
30890                                                         ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S))
30891 
30892 /****************** LPTIM Instances : supporting Input Capture **************/
30893 #define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\
30894                                                     ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\
30895                                                     ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S))
30896 
30897 /****************** TIM Instances : All supported instances *******************/
30898 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
30899                                          ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
30900                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
30901                                          ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
30902                                          ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
30903                                          ((INSTANCE) == TIM6_NS)  || ((INSTANCE) == TIM6_S)  || \
30904                                          ((INSTANCE) == TIM7_NS)  || ((INSTANCE) == TIM7_S)  || \
30905                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
30906                                          ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
30907                                          ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
30908                                          ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
30909 
30910 /****************** TIM Instances : supporting 32 bits counter ****************/
30911 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
30912                                                ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
30913                                                ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
30914                                                ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S))
30915 
30916 /****************** TIM Instances : supporting the break function *************/
30917 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
30918                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
30919                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
30920                                             ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
30921                                             ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
30922 
30923 /************** TIM Instances : supporting Break source selection *************/
30924 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
30925                                                ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
30926                                                ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
30927                                                ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
30928                                                ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
30929 
30930 /****************** TIM Instances : supporting 2 break inputs *****************/
30931 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
30932                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
30933 
30934 /************* TIM Instances : at least 1 capture/compare channel *************/
30935 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
30936                                          ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
30937                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
30938                                          ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
30939                                          ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
30940                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
30941                                          ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
30942                                          ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
30943                                          ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
30944 
30945 /************ TIM Instances : at least 2 capture/compare channels *************/
30946 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
30947                                          ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
30948                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
30949                                          ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
30950                                          ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
30951                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
30952                                          ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
30953 
30954 /************ TIM Instances : at least 3 capture/compare channels *************/
30955 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
30956                                          ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
30957                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
30958                                          ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
30959                                          ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
30960                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
30961 
30962 /************ TIM Instances : at least 4 capture/compare channels *************/
30963 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
30964                                          ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
30965                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
30966                                          ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
30967                                          ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
30968                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
30969 
30970 /****************** TIM Instances : at least 5 capture/compare channels *******/
30971 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
30972                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
30973 
30974 /****************** TIM Instances : at least 6 capture/compare channels *******/
30975 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
30976                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
30977 
30978 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
30979 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
30980                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
30981                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
30982                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
30983                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
30984                                             ((INSTANCE) == TIM6_NS)  || ((INSTANCE) == TIM6_S)  || \
30985                                             ((INSTANCE) == TIM7_NS)  || ((INSTANCE) == TIM7_S)  || \
30986                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
30987                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
30988                                             ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
30989                                             ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
30990 
30991 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
30992 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
30993                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
30994                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
30995                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
30996                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
30997                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
30998                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
30999                                             ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
31000                                             ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
31001 
31002 /******************** TIM Instances : DMA burst feature ***********************/
31003 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31004                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31005                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31006                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31007                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31008                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
31009                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
31010                                             ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
31011                                             ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
31012 
31013 /******************* TIM Instances : output(s) available **********************/
31014 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
31015     (((((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))  && \
31016      (((CHANNEL) == TIM_CHANNEL_1) ||          \
31017       ((CHANNEL) == TIM_CHANNEL_2) ||          \
31018       ((CHANNEL) == TIM_CHANNEL_3) ||          \
31019       ((CHANNEL) == TIM_CHANNEL_4) ||          \
31020       ((CHANNEL) == TIM_CHANNEL_5) ||          \
31021       ((CHANNEL) == TIM_CHANNEL_6)))           \
31022      ||                                        \
31023      ((((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S))  && \
31024      (((CHANNEL) == TIM_CHANNEL_1) ||          \
31025       ((CHANNEL) == TIM_CHANNEL_2) ||          \
31026       ((CHANNEL) == TIM_CHANNEL_3) ||          \
31027       ((CHANNEL) == TIM_CHANNEL_4)))           \
31028      ||                                        \
31029      ((((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S))  && \
31030      (((CHANNEL) == TIM_CHANNEL_1) ||          \
31031       ((CHANNEL) == TIM_CHANNEL_2) ||          \
31032       ((CHANNEL) == TIM_CHANNEL_3) ||          \
31033       ((CHANNEL) == TIM_CHANNEL_4)))           \
31034      ||                                        \
31035      ((((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S))  && \
31036      (((CHANNEL) == TIM_CHANNEL_1) ||          \
31037       ((CHANNEL) == TIM_CHANNEL_2) ||          \
31038       ((CHANNEL) == TIM_CHANNEL_3) ||          \
31039       ((CHANNEL) == TIM_CHANNEL_4)))           \
31040      ||                                        \
31041      ((((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S))  && \
31042      (((CHANNEL) == TIM_CHANNEL_1) ||          \
31043       ((CHANNEL) == TIM_CHANNEL_2) ||          \
31044       ((CHANNEL) == TIM_CHANNEL_3) ||          \
31045       ((CHANNEL) == TIM_CHANNEL_4)))           \
31046      ||                                        \
31047      ((((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))  && \
31048      (((CHANNEL) == TIM_CHANNEL_1) ||          \
31049       ((CHANNEL) == TIM_CHANNEL_2) ||          \
31050       ((CHANNEL) == TIM_CHANNEL_3) ||          \
31051       ((CHANNEL) == TIM_CHANNEL_4) ||          \
31052       ((CHANNEL) == TIM_CHANNEL_5) ||          \
31053       ((CHANNEL) == TIM_CHANNEL_6)))           \
31054      ||                                        \
31055      ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \
31056      (((CHANNEL) == TIM_CHANNEL_1) ||          \
31057       ((CHANNEL) == TIM_CHANNEL_2)))           \
31058      ||                                        \
31059      ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \
31060      (((CHANNEL) == TIM_CHANNEL_1)))           \
31061      ||                                        \
31062      ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \
31063      (((CHANNEL) == TIM_CHANNEL_1))))
31064 
31065 /****************** TIM Instances : supporting complementary output(s) ********/
31066 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
31067     (((((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S))  && \
31068      (((CHANNEL) == TIM_CHANNEL_1) ||           \
31069       ((CHANNEL) == TIM_CHANNEL_2) ||           \
31070       ((CHANNEL) == TIM_CHANNEL_3) ||           \
31071       ((CHANNEL) == TIM_CHANNEL_4)))            \
31072     ||                                          \
31073     ((((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))  && \
31074      (((CHANNEL) == TIM_CHANNEL_1) ||           \
31075       ((CHANNEL) == TIM_CHANNEL_2) ||           \
31076       ((CHANNEL) == TIM_CHANNEL_3) ||           \
31077       ((CHANNEL) == TIM_CHANNEL_4)))            \
31078     ||                                          \
31079     ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \
31080      ((CHANNEL) == TIM_CHANNEL_1))              \
31081     ||                                          \
31082     ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \
31083      ((CHANNEL) == TIM_CHANNEL_1))              \
31084     ||                                          \
31085     ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \
31086      ((CHANNEL) == TIM_CHANNEL_1)))
31087 
31088 /****************** TIM Instances : supporting clock division *****************/
31089 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31090                                                     ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31091                                                     ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31092                                                     ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31093                                                     ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31094                                                     ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
31095                                                     ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
31096                                                     ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
31097                                                     ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
31098 
31099 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
31100 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31101                                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31102                                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31103                                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31104                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31105                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
31106 
31107 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
31108 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31109                                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31110                                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31111                                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31112                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31113                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
31114 
31115 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
31116 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31117                                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31118                                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31119                                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31120                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31121                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
31122                                                         ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
31123 
31124 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
31125 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31126                                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31127                                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31128                                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31129                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31130                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
31131                                                         ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
31132 
31133 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
31134 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31135                                                      ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
31136 
31137 /****************** TIM Instances : supporting commutation event generation ***/
31138 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31139                                                      ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
31140                                                      ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
31141                                                      ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
31142                                                      ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
31143 
31144 /****************** TIM Instances : supporting counting mode selection ********/
31145 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31146                                                         ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31147                                                         ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31148                                                         ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31149                                                         ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31150                                                         ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
31151 
31152 /****************** TIM Instances : supporting encoder interface **************/
31153 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31154                                                       ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31155                                                       ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31156                                                       ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31157                                                       ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31158                                                       ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
31159 
31160 /****************** TIM Instances : supporting Hall sensor interface **********/
31161 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)   || ((INSTANCE) == TIM1_S)  || \
31162                                                          ((INSTANCE) == TIM2_NS)   || ((INSTANCE) == TIM2_S)  || \
31163                                                          ((INSTANCE) == TIM3_NS)   || ((INSTANCE) == TIM3_S)  || \
31164                                                          ((INSTANCE) == TIM4_NS)   || ((INSTANCE) == TIM4_S)  || \
31165                                                          ((INSTANCE) == TIM5_NS)   || ((INSTANCE) == TIM5_S)  || \
31166                                                          ((INSTANCE) == TIM8_NS)   || ((INSTANCE) == TIM8_S))
31167 
31168 /**************** TIM Instances : external trigger input available ************/
31169 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31170                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31171                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31172                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31173                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31174                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
31175 
31176 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
31177 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31178                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31179                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31180                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31181                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31182                                             ((INSTANCE) == TIM6_NS)  || ((INSTANCE) == TIM6_S)  || \
31183                                             ((INSTANCE) == TIM7_NS)  || ((INSTANCE) == TIM7_S)  || \
31184                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
31185                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
31186 
31187 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
31188 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31189                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31190                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31191                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31192                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31193                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
31194                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
31195 
31196 /****************** TIM Instances : supporting OCxREF clear *******************/
31197 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31198                                                        ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31199                                                        ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31200                                                        ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31201                                                        ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31202                                                        ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
31203                                                        ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
31204                                                        ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
31205                                                        ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
31206 
31207 /****************** TIM Instances : remapping capability **********************/
31208 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31209                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31210                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31211                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31212                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31213                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
31214 
31215 /****************** TIM Instances : supporting repetition counter *************/
31216 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31217                                                        ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
31218                                                        ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \
31219                                                        ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \
31220                                                        ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
31221 
31222 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
31223 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) || \
31224                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
31225 
31226 /******************* TIM Instances : Timer input XOR function *****************/
31227 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S)  || \
31228                                             ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S)  || \
31229                                             ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S)  || \
31230                                             ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S)  || \
31231                                             ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S)  || \
31232                                             ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S)  || \
31233                                             ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S))
31234 
31235 /******************* TIM Instances : Timer input selection ********************/
31236 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) ||\
31237                                          ((INSTANCE) == TIM2_NS)  || ((INSTANCE) == TIM2_S) ||\
31238                                          ((INSTANCE) == TIM3_NS)  || ((INSTANCE) == TIM3_S) ||\
31239                                          ((INSTANCE) == TIM4_NS)  || ((INSTANCE) == TIM4_S) ||\
31240                                          ((INSTANCE) == TIM5_NS)  || ((INSTANCE) == TIM5_S) ||\
31241                                          ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S) ||\
31242                                          ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\
31243                                          ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\
31244                                          ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
31245 
31246 /******************* TIM Instances : supporting HSE32 as input  ********************/
31247 #define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS)  || ((INSTANCE) == TIM16_S) ||\
31248                                          ((INSTANCE) == TIM17_NS)  || ((INSTANCE) == TIM17_S))
31249 
31250 /****************** TIM Instances : Advanced timer instances *******************/
31251 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || ((INSTANCE) == TIM1_S) || \
31252                                                   ((INSTANCE) == TIM8_NS)  || ((INSTANCE) == TIM8_S))
31253 
31254 /****************** TIM Instances : supporting synchronization ****************/
31255 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1_NS)  || ((__INSTANCE__) == TIM1_S) || \
31256                                                 ((__INSTANCE__) == TIM2_NS)  || ((__INSTANCE__) == TIM2_S) || \
31257                                                 ((__INSTANCE__) == TIM3_NS)  || ((__INSTANCE__) == TIM3_S) || \
31258                                                 ((__INSTANCE__) == TIM4_NS)  || ((__INSTANCE__) == TIM4_S) || \
31259                                                 ((__INSTANCE__) == TIM5_NS)  || ((__INSTANCE__) == TIM5_S) || \
31260                                                 ((__INSTANCE__) == TIM6_NS)  || ((__INSTANCE__) == TIM6_S) || \
31261                                                 ((__INSTANCE__) == TIM7_NS)  || ((__INSTANCE__) == TIM7_S) || \
31262                                                 ((__INSTANCE__) == TIM8_NS)  || ((__INSTANCE__) == TIM8_S) || \
31263                                                 ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S))
31264 
31265 /****************************** TSC Instances *********************************/
31266 #define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S))
31267 
31268 /******************** USART Instances : Synchronous mode **********************/
31269 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
31270                                      ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
31271                                      ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
31272                                      ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S))
31273 
31274 /******************** UART Instances : Asynchronous mode **********************/
31275 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
31276                                     ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
31277                                     ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
31278                                     ((INSTANCE) == UART4_NS)  || ((INSTANCE) == UART4_S)  || \
31279                                     ((INSTANCE) == UART5_NS)  || ((INSTANCE) == UART5_S)  || \
31280                                     ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S))
31281 
31282 /*********************** UART Instances : FIFO mode ***************************/
31283 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S) || \
31284                                          ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S) || \
31285                                          ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S) || \
31286                                          ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)  || \
31287                                          ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)  || \
31288                                          ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S) || \
31289                                          ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
31290 
31291 /*********************** UART Instances : SPI Slave mode **********************/
31292 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
31293                                               ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
31294                                               ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \
31295                                               ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)
31296 
31297 /****************** UART Instances : Auto Baud Rate detection ****************/
31298 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
31299                                                             ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
31300                                                             ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
31301                                                             ((INSTANCE) == UART4_NS)  || ((INSTANCE) == UART4_S)  || \
31302                                                             ((INSTANCE) == UART5_NS)  || ((INSTANCE) == UART5_S)) || \
31303                                                             ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)
31304 
31305 /****************** UART Instances : Driver Enable *****************/
31306 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S) || \
31307                                                       ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S) || \
31308                                                       ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S) || \
31309                                                       ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)  || \
31310                                                       ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)  || \
31311                                                       ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S) || \
31312                                                       ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
31313 
31314 /******************** UART Instances : Half-Duplex mode **********************/
31315 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S) || \
31316                                                  ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S) || \
31317                                                  ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S) || \
31318                                                  ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)  || \
31319                                                  ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)  || \
31320                                                  ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S) || \
31321                                                  ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
31322 
31323 /****************** UART Instances : Hardware Flow control ********************/
31324 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S) || \
31325                                            ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S) || \
31326                                            ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S) || \
31327                                            ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)  || \
31328                                            ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)  || \
31329                                            ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S) || \
31330                                            ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
31331 
31332 /******************** UART Instances : LIN mode **********************/
31333 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
31334                                           ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
31335                                           ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
31336                                           ((INSTANCE) == UART4_NS)  || ((INSTANCE) == UART4_S)  || \
31337                                           ((INSTANCE) == UART5_NS)  || ((INSTANCE) == UART5_S)) || \
31338                                           ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)
31339 
31340 /******************** UART Instances : Wake-up from Stop mode **********************/
31341 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S) || \
31342                                                       ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S) || \
31343                                                       ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S) || \
31344                                                       ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)  || \
31345                                                       ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)  || \
31346                                                       ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S) || \
31347                                                       ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
31348 
31349 /*********************** UART Instances : IRDA mode ***************************/
31350 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
31351                                     ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
31352                                     ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \
31353                                     ((INSTANCE) == UART4_NS)  || ((INSTANCE) == UART4_S)  || \
31354                                     ((INSTANCE) == UART5_NS)  || ((INSTANCE) == UART5_S)) || \
31355                                     ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)
31356 
31357 /********************* USART Instances : Smard card mode ***********************/
31358 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \
31359                                          ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \
31360                                          ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \
31361                                          ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)
31362 
31363 /******************** LPUART Instance *****************************************/
31364 #define IS_LPUART_INSTANCE(INSTANCE)    (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
31365 
31366 /*********************** UART Instances : AUTONOMOUS mode ***************************/
31367 #define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || ((INSTANCE) == USART1_S) || \
31368                                                ((INSTANCE) == USART2_NS)  || ((INSTANCE) == USART2_S) || \
31369                                                ((INSTANCE) == USART3_NS)  || ((INSTANCE) == USART3_S) || \
31370                                                ((INSTANCE) == UART4_NS)   || ((INSTANCE) == UART4_S)  || \
31371                                                ((INSTANCE) == UART5_NS)   || ((INSTANCE) == UART5_S)  || \
31372                                                ((INSTANCE) == USART6_NS)  || ((INSTANCE) == USART6_S) || \
31373                                                ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S))
31374 
31375 /****************************** IWDG Instances ********************************/
31376 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S))
31377 
31378 /****************************** WWDG Instances ********************************/
31379 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S))
31380 
31381 /****************************** UCPD Instances ********************************/
31382 #define IS_UCPD_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S))
31383 
31384 /******************************* OTG FS HCD Instances *************************/
31385 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S))
31386 
31387 /******************************* OTG FS PCD Instances *************************/
31388 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S))
31389 
31390 /******************************* MDF/ADF Instances ****************************/
31391 #define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS)  || ((INSTANCE) == MDF1_Filter0_S) || \
31392                                        ((INSTANCE) == MDF1_Filter1_NS)  || ((INSTANCE) == MDF1_Filter1_S) || \
31393                                        ((INSTANCE) == MDF1_Filter2_NS)  || ((INSTANCE) == MDF1_Filter2_S) || \
31394                                        ((INSTANCE) == MDF1_Filter3_NS)  || ((INSTANCE) == MDF1_Filter3_S) || \
31395                                        ((INSTANCE) == MDF1_Filter4_NS)  || ((INSTANCE) == MDF1_Filter4_S) || \
31396                                        ((INSTANCE) == MDF1_Filter5_NS)  || ((INSTANCE) == MDF1_Filter5_S) || \
31397                                        ((INSTANCE) == ADF1_Filter0_NS)  || ((INSTANCE) == ADF1_Filter0_S))
31398 
31399 /******************************* GPU2D Instances *******************************/
31400 #define IS_GPU2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPU2D_BASE_NS) || ((__INSTANCE__) == GPU2D_BASE_S))
31401 
31402 /****************************** JPEG Instances ********************************/
31403 #define IS_JPEG_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == JPEG_NS) || ((__INSTANCE__) == JPEG_S))
31404 
31405 /****************************** GFXTIM Instances ********************************/
31406 #define IS_GFXTIM_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == GFXTIM_NS) || ((__INSTANCE__) == GFXTIM_S))
31407 
31408 
31409 /** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */
31410 
31411 /** @} */ /* End of group STM32U5G9xx */
31412 
31413 /** @} */ /* End of group ST */
31414 
31415 #ifdef __cplusplus
31416 }
31417 #endif
31418 
31419 #endif  /* STM32U5G9xx_H */
31420