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Searched refs:XSPI_CCR_ISIZE_0 (Results 1 – 25 of 29) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_xspi.h514 #define HAL_XSPI_INSTRUCTION_16_BITS ((uint32_t)XSPI_CCR_ISIZE_0) /*!< 16-bit instruction …
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_xspi.h549 #define HAL_XSPI_INSTRUCTION_16_BITS ((uint32_t)XSPI_CCR_ISIZE_0) /*!< 16-bit instruction …
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_xspi.h567 #define HAL_XSPI_INSTRUCTION_16_BITS ((uint32_t)XSPI_CCR_ISIZE_0) /*!< 16-bit instruction …
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_xspi.h574 #define HAL_XSPI_INSTRUCTION_16_BITS ((uint32_t)XSPI_CCR_ISIZE_0) /*!< 16-bit instruction …
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u595xx.h13021 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00… macro
13474 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
13885 #define HSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32u5a5xx.h13470 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00… macro
13923 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
14334 #define HSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32u5f7xx.h14519 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00… macro
14972 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
15383 #define HSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32u599xx.h16740 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00… macro
17193 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
17604 #define HSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32u5g7xx.h14968 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00… macro
15421 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
15832 #define HSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32u5f9xx.h17645 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00… macro
18098 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
18509 #define HSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32u5a9xx.h17189 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00… macro
17642 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
18053 #define HSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32u5g9xx.h18094 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00… macro
18547 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
18958 #define HSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32u545xx.h12071 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00… macro
12490 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32u535xx.h11671 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00… macro
12090 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32u575xx.h12706 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00… macro
13125 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32u585xx.h13155 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00… macro
13574 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h10979 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x000… macro
11391 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32h562xx.h11705 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x000… macro
12117 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32h533xx.h11388 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x000… macro
11800 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32h573xx.h14198 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x000… macro
14610 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
Dstm32h563xx.h13789 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x000… macro
14201 #define OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 /*!< 0x00…
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13317 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */ macro
Dstm32h7s7xx.h14351 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */ macro
Dstm32h7s3xx.h13949 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */ macro
Dstm32h7r7xx.h13717 #define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */ macro

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