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Searched refs:TIM_ECR_FIDX (Results 1 – 25 of 56) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_tim.h1532 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only …
4796 SET_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_EnableFirstIndex()
4809 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_DisableFirstIndex()
4822 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); in LL_TIM_IsEnabledFirstIndex()
4882 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_tim.h1448 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only …
4658 SET_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_EnableFirstIndex()
4671 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_DisableFirstIndex()
4684 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); in LL_TIM_IsEnabledFirstIndex()
4744 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_tim.h1435 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only …
4598 SET_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_EnableFirstIndex()
4611 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_DisableFirstIndex()
4624 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); in LL_TIM_IsEnabledFirstIndex()
4684 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_tim.h1744 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only …
4983 SET_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_EnableFirstIndex()
4996 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_DisableFirstIndex()
5009 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); in LL_TIM_IsEnabledFirstIndex()
5069 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_tim.h1675 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only …
4934 SET_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_EnableFirstIndex()
4947 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_DisableFirstIndex()
4960 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); in LL_TIM_IsEnabledFirstIndex()
5020 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_tim.h1799 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only …
5066 SET_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_EnableFirstIndex()
5079 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_DisableFirstIndex()
5092 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); in LL_TIM_IsEnabledFirstIndex()
5150 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); in LL_TIM_ConfigIDX()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_tim_ex.c2973 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
2987 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_tim_ex.c3114 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
3128 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_tim_ex.c3018 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
3032 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_tim_ex.c2948 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
2962 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_tim_ex.c3096 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
3110 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_tim_ex.c3288 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
3302 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9081 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index… macro
Dstm32wba52xx.h13249 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index… macro
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h10258 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g411xc.h10476 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g441xx.h11042 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32gbk1cb.h10784 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g431xx.h10812 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g4a1xx.h11552 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g491xx.h11322 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g473xx.h12113 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g471xx.h11545 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
Dstm32g483xx.h12343 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h7523 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index… macro

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