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Searched refs:TIM_DTR2_DTAE (Results 1 – 25 of 56) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_tim.h4485 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime()
4498 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime()
4511 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_tim.h4347 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime()
4360 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime()
4373 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_tim.h4286 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime()
4299 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime()
4312 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_tim.h4671 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime()
4684 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime()
4697 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_tim.h4622 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime()
4635 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime()
4648 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_tim.h4798 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime()
4811 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime()
4824 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_tim_ex.c2872 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime()
2886 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_tim_ex.c2991 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime()
3005 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_tim_ex.c2917 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime()
2931 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_tim_ex.c2847 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime()
2861 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_tim_ex.c2995 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime()
3009 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_tim_ex.c3189 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime()
3203 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9060 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime as… macro
Dstm32wba52xx.h13228 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime as… macro
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h10240 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric… macro
Dstm32g411xc.h10458 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric… macro
Dstm32g441xx.h11024 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric… macro
Dstm32gbk1cb.h10766 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric… macro
Dstm32g431xx.h10794 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric… macro
Dstm32g4a1xx.h11534 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric… macro
Dstm32g491xx.h11304 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric… macro
Dstm32g473xx.h12095 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric… macro
Dstm32g471xx.h11527 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric… macro
Dstm32g483xx.h12325 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric… macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h7502 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime as… macro

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