Home
last modified time | relevance | path

Searched refs:TIM_CR2_OIS4N (Results 1 – 25 of 56) sorted by relevance

123

/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_tim.c1060 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); in OC4Config()
Dstm32wbaxx_hal_tim.c7602 tmpcr2 &= ~TIM_CR2_OIS4N; in TIM_OC4_SetConfig()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_tim.c1101 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); in OC4Config()
Dstm32h7rsxx_hal_tim.c7566 tmpcr2 &= ~TIM_CR2_OIS4N; in TIM_OC4_SetConfig()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_tim.c1097 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); in OC4Config()
Dstm32u5xx_hal_tim.c7590 tmpcr2 &= ~TIM_CR2_OIS4N; in TIM_OC4_SetConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_tim.c1138 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); in OC4Config()
Dstm32n6xx_hal_tim.c7566 tmpcr2 &= ~TIM_CR2_OIS4N; in TIM_OC4_SetConfig()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_tim.c1095 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); in OC4Config()
Dstm32g4xx_hal_tim.c7441 tmpcr2 &= ~TIM_CR2_OIS4N; in TIM_OC4_SetConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_tim.c1132 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); in OC4Config()
Dstm32h5xx_hal_tim.c7599 tmpcr2 &= ~TIM_CR2_OIS4N; in TIM_OC4_SetConfig()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h8314 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle… macro
Dstm32wba52xx.h12482 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle… macro
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h9492 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle stat… macro
Dstm32g411xc.h9710 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle stat… macro
Dstm32g441xx.h10264 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle stat… macro
Dstm32gbk1cb.h10006 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle stat… macro
Dstm32g431xx.h10034 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle stat… macro
Dstm32g4a1xx.h10774 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle stat… macro
Dstm32g491xx.h10544 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle stat… macro
Dstm32g473xx.h11317 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle stat… macro
Dstm32g471xx.h10767 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle stat… macro
Dstm32g483xx.h11547 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle stat… macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h6800 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle… macro

123