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Searched refs:RI_ICR_IC1OS_Pos (Results 1 – 22 of 22) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l152xb.h5471 #define RI_ICR_IC1OS_Pos (0U) macro
5472 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
5474 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
5475 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
5476 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
5477 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l152xba.h5532 #define RI_ICR_IC1OS_Pos (0U) macro
5533 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
5535 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
5536 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
5537 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
5538 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l100xba.h5517 #define RI_ICR_IC1OS_Pos (0U) macro
5518 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
5520 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
5521 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
5522 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
5523 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l100xb.h5369 #define RI_ICR_IC1OS_Pos (0U) macro
5370 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
5372 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
5373 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
5374 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
5375 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l151xb.h5321 #define RI_ICR_IC1OS_Pos (0U) macro
5322 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
5324 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
5325 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
5326 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
5327 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l151xba.h5397 #define RI_ICR_IC1OS_Pos (0U) macro
5398 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
5400 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
5401 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
5402 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
5403 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l100xc.h5722 #define RI_ICR_IC1OS_Pos (0U) macro
5723 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
5725 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
5726 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
5727 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
5728 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l151xc.h5911 #define RI_ICR_IC1OS_Pos (0U) macro
5912 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
5914 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
5915 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
5916 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
5917 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l151xca.h5945 #define RI_ICR_IC1OS_Pos (0U) macro
5946 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
5948 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
5949 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
5950 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
5951 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l151xdx.h6010 #define RI_ICR_IC1OS_Pos (0U) macro
6011 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6013 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6014 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6015 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6016 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l151xe.h6010 #define RI_ICR_IC1OS_Pos (0U) macro
6011 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6013 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6014 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6015 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6016 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l152xc.h6040 #define RI_ICR_IC1OS_Pos (0U) macro
6041 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6043 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6044 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6045 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6046 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l152xca.h6095 #define RI_ICR_IC1OS_Pos (0U) macro
6096 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6098 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6099 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6100 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6101 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l152xdx.h6160 #define RI_ICR_IC1OS_Pos (0U) macro
6161 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6163 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6164 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6165 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6166 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l152xe.h6160 #define RI_ICR_IC1OS_Pos (0U) macro
6161 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6163 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6164 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6165 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6166 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l162xc.h6179 #define RI_ICR_IC1OS_Pos (0U) macro
6180 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6182 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6183 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6184 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6185 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l162xca.h6234 #define RI_ICR_IC1OS_Pos (0U) macro
6235 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6237 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6238 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6239 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6240 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l162xdx.h6299 #define RI_ICR_IC1OS_Pos (0U) macro
6300 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6302 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6303 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6304 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6305 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l162xe.h6299 #define RI_ICR_IC1OS_Pos (0U) macro
6300 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6302 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6303 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6304 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6305 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l151xd.h6645 #define RI_ICR_IC1OS_Pos (0U) macro
6646 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6648 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6649 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6650 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6651 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l152xd.h6795 #define RI_ICR_IC1OS_Pos (0U) macro
6796 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6798 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6799 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6800 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6801 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
Dstm32l162xd.h6934 #define RI_ICR_IC1OS_Pos (0U) macro
6935 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
6937 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
6938 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
6939 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
6940 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */