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Searched refs:RCC_CFGR_PLLXTPRE_Pos (Results 1 – 25 of 48) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_hal_rcc_ex.c426 … prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; in HAL_RCCEx_GetPeriphCLKFreq()
Dstm32f1xx_ll_utils.c549 …PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UT… in UTILS_GetPLLOutputFrequency()
Dstm32f1xx_hal_rcc.c1118 … prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; in HAL_RCC_GetSysClockFreq()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_rcc.h1587 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos); in LL_RCC_PLL_GetPrediv()
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h896 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
897 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f101xb.h911 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
912 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f100xb.h971 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
972 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f102x6.h936 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
937 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f100xe.h1240 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
1241 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f101xg.h1265 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
1266 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f101xe.h1240 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
1241 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f102xb.h949 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
950 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f103x6.h1011 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
1012 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h2861 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
2862 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f030x8.h2891 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
2892 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f070x6.h2916 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
2917 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f031x6.h2987 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
2988 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f030xc.h3148 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
3149 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f038xx.h2962 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
2963 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f070xb.h3008 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
3009 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f058xx.h3411 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
3412 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f051x8.h3436 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
3437 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f071xb.h3832 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
3833 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h4830 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
4831 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Dstm32f318xx.h4823 #define RCC_CFGR_PLLXTPRE_Pos (17U) macro
4824 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */

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