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Searched refs:RCC_CFGR3_TIMSW_Msk (Results 1 – 12 of 12) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h5311 #define RCC_CFGR3_TIMSW_Msk (0x2DUL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00002D00 */ macro
5312 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
Dstm32f318xx.h5301 #define RCC_CFGR3_TIMSW_Msk (0x2DUL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00002D00 */ macro
5302 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
Dstm32f302x8.h8939 #define RCC_CFGR3_TIMSW_Msk (0x2DUL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00002D00 */ macro
8940 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
Dstm32f328xx.h8870 #define RCC_CFGR3_TIMSW_Msk (0x1UL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00000100 */ macro
8871 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
Dstm32f302xc.h9196 #define RCC_CFGR3_TIMSW_Msk (0x3UL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00000300 */ macro
9197 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
Dstm32f303x8.h8897 #define RCC_CFGR3_TIMSW_Msk (0x1UL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00000100 */ macro
8898 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
Dstm32f358xx.h9723 #define RCC_CFGR3_TIMSW_Msk (0x3UL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00000300 */ macro
9724 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
Dstm32f303xc.h9826 #define RCC_CFGR3_TIMSW_Msk (0x3UL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00000300 */ macro
9827 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
Dstm32f302xe.h10837 #define RCC_CFGR3_TIMSW_Msk (0xAFUL << RCC_CFGR3_TIMSW_Pos) /*!< 0x0000AF00 */ macro
10838 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
Dstm32f303xe.h11445 #define RCC_CFGR3_TIMSW_Msk (0xAFUL << RCC_CFGR3_TIMSW_Pos) /*!< 0x0000AF00 */ macro
11446 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
Dstm32f398xx.h11340 #define RCC_CFGR3_TIMSW_Msk (0xAFUL << RCC_CFGR3_TIMSW_Pos) /*!< 0x0000AF00 */ macro
11341 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */
Dstm32f334x8.h11999 #define RCC_CFGR3_TIMSW_Msk (0x1UL << RCC_CFGR3_TIMSW_Pos) /*!< 0x00000100 */ macro
12000 #define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk /*!< TIMSW bits */