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Searched refs:RCC_APBENR1_TIM2EN (Results 1 – 18 of 18) sorted by relevance

/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_rcc.h799 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
801 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
902 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN)
1062 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U)
1085 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U)
Dstm32c0xx_ll_bus.h89 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APBENR1_TIM2EN
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h857 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
859 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
1073 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN)
1282 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0…
1344 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0…
Dstm32u0xx_ll_bus.h101 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APBENR1_TIM2EN
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h1012 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
1014 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
1369 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN)
1531 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U)
1595 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U)
Dstm32g0xx_ll_bus.h98 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APBENR1_TIM2EN
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c071xx.h4700 #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk macro
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g031xx.h4519 #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk macro
Dstm32g041xx.h4767 #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk macro
Dstm32g051xx.h4867 #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk macro
Dstm32g061xx.h5115 #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk macro
Dstm32g071xx.h5217 #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk macro
Dstm32g081xx.h5465 #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk macro
Dstm32g0c1xx.h6796 #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk macro
Dstm32g0b1xx.h6548 #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h5369 #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk macro
Dstm32u083xx.h6182 #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk macro
Dstm32u073xx.h5918 #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk macro