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Searched refs:RCC_APB1ENR_SPI3EN (Results 1 – 25 of 89) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_bus.h138 RCC_APB1ENR_SPI3EN |\
147 RCC_APB1ENR_SPI3EN |\
156 RCC_APB1ENR_SPI3EN |\
162 RCC_APB1ENR_SPI3EN |\
175 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc_ex.h2020 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2022 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2041 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2071 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2073 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2101 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2187 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2189 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2222 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2516 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
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Dstm32f3xx_ll_bus.h146 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc_ex.h873 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
875 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
906 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
986 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
988 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1012 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
1102 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1103 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
1130 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1131 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Dstm32f1xx_ll_bus.h127 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h1435 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1437 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1450 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
1479 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1498 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
2450 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2452 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2465 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2492 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
2509 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
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Dstm32f4xx_ll_bus.h221 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc_ex.h284 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
286 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
289 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
689 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != 0U)
690 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == 0U)
Dstm32l1xx_ll_bus.h122 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h733 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
735 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
827 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
861 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))!= RESET)
885 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))== RESET)
Dstm32f2xx_ll_bus.h141 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h1030 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1032 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
1180 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
1597 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1624 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Dstm32f7xx_ll_bus.h160 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f100xe.h1651 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock ena… macro
Dstm32f101xg.h1659 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock ena… macro
Dstm32f101xe.h1607 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock ena… macro
/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l100xc.h4447 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock ena… macro
Dstm32l151xc.h4506 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock ena… macro
Dstm32l151xca.h4534 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock ena… macro
Dstm32l151xdx.h4587 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock ena… macro
Dstm32l151xe.h4587 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock ena… macro
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h5099 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI3 clock enab… macro
Dstm32f318xx.h5092 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI3 clock enab… macro
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f401xc.h4323 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk macro
Dstm32f401xe.h4323 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk macro

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