Home
last modified time | relevance | path

Searched refs:RCC_APB1ENR_CRSEN (Results 1 – 19 of 19) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc_ex.h1201 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
1203 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
1207 #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
1654 #define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET)
1655 #define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET)
Dstm32f0xx_ll_bus.h139 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc_ex.h680 #define __HAL_RCC_CRS_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN))
681 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR,(RCC_APB1ENR_CRSEN))
683 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) != 0U)
684 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) == 0U)
Dstm32l0xx_ll_bus.h128 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l052xx.h4115 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32l062xx.h4249 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32l053xx.h4265 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32l072xx.h4306 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32l073xx.h4454 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32l083xx.h4588 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32l063xx.h4397 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32l082xx.h4440 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f071xb.h4178 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32f042x6.h7473 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32f048xx.h7449 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32f072xb.h7965 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32f091xc.h8436 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32f098xx.h8412 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro
Dstm32f078xx.h7941 #define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enabl… macro