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Searched refs:RCC_AHBENR_CRCEN (Results 1 – 25 of 124) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc.h347 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
349 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
356 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
376 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
377 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
Dstm32f1xx_ll_bus.h76 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc.h694 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
696 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
703 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
800 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != 0U)
803 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == 0U)
Dstm32l0xx_ll_bus.h76 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc.h650 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
652 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
681 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
700 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
708 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
Dstm32f0xx_ll_bus.h79 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc.h717 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
719 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
756 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
905 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
916 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
Dstm32f3xx_ll_bus.h82 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_bus.h78 RCC_AHBENR_CRCEN| \
84 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc.h678 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
680 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
704 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
1117 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != 0U)
1125 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == 0U)
Dstm32l1xx_ll_bus.h88 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_rcc.h714 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
716 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
723 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
1019 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != 0U)
1023 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == 0U)
Dstm32c0xx_ll_bus.h78 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h727 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
729 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
764 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
1243 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != 0U)
1261 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == 0U)
Dstm32u0xx_ll_bus.h86 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h889 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
891 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
920 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
1468 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)
1481 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET)
Dstm32g0xx_ll_bus.h80 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h1115 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enabl… macro
Dstm32f101xb.h1145 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enabl… macro
Dstm32f100xb.h1226 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enabl… macro
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h3059 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enabl… macro
Dstm32f030x8.h3088 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enabl… macro
Dstm32f070x6.h3125 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enabl… macro
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h3756 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enabl… macro
Dstm32l010x8.h3461 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enabl… macro

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