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Searched refs:OCState (Results 1 – 25 of 48) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32wb0x/drivers/src/
Dstm32wb0x_ll_tim.c349 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
686 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
711 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
765 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
790 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
846 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
871 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
927 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
952 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
996 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_tim.c406 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
824 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
849 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
903 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
928 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
982 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1007 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1061 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1086 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1127 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_ll_tim.c359 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
783 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
808 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
862 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
887 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
941 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
966 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1020 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1045 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1086 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_ll_tim.c338 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
763 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
790 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
842 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
869 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
921 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
948 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1000 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1027 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1069 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_tim.c355 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
779 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
804 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
858 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
883 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
937 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
962 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1016 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1041 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1094 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_ll_tim.c350 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
774 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
799 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
853 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
878 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
932 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
957 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1011 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1036 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1077 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_ll_tim.c342 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
766 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
791 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
845 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
870 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
924 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
949 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1003 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1028 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1069 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_tim.c373 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
797 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
822 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
876 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
901 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
955 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
980 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1034 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1059 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1100 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_tim.c379 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
797 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
822 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
876 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
901 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
955 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
980 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1034 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1059 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1100 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_ll_tim.c382 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
806 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
831 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
885 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
910 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
964 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
989 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1043 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1068 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1109 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_tim.c396 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
820 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
845 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
899 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
924 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
978 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1003 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1057 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1082 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1135 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_tim.c450 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
885 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
910 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
964 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
989 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
1046 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1071 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1128 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1153 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1199 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_tim.c392 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
816 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
841 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
895 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
920 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
974 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
999 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1053 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1078 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1131 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_tim.c414 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
833 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
860 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
912 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
939 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
991 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1018 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1070 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1097 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1139 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_tim.c433 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
857 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
882 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
936 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
961 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
1015 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1040 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1094 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1119 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1172 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_tim.c418 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
854 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
879 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
933 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
958 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
1012 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1037 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1091 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1116 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1157 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_tim.c390 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
814 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
839 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
893 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
918 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
972 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
997 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1051 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1076 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1129 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_tim.c427 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
851 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
876 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
930 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
955 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
1009 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
1034 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1088 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1113 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1166 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/src/
Dstm32l0xx_ll_tim.c271 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
484 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
509 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
543 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
568 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
602 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
627 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
661 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
686 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_tim.c294 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
507 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
532 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
566 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
591 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
625 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
650 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
684 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
709 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_tim.c360 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
749 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
774 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
828 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
853 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
907 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
932 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
986 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1011 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_tim.c360 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
749 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
774 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
828 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
853 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
907 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
932 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
986 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1011 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/src/
Dstm32f0xx_ll_tim.c339 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
728 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
753 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
807 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
832 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
886 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
911 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
965 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
990 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_tim.c380 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; in LL_TIM_OC_StructInit()
767 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC1Config()
792 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
846 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC2Config()
871 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
925 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC3Config()
950 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1004 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); in OC4Config()
1029 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_tim.h188 uint32_t OCState; /*!< Specifies the TIM Output Compare state. member

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