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Searched refs:LPTIM_CFGR2_IC1SEL_1 (Results 1 – 25 of 42) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_lptim.h414 #define LL_LPTIM_LPTIM1_IC1_RMP_EVENTOUT LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to EVENTO…
415 #define LL_LPTIM_LPTIM1_IC1_RMP_MCO1 (LPTIM_CFGR2_IC1SEL_0 | LPTIM_CFGR2_IC1SEL_1) /*!< IC1 c…
440 #define LL_LPTIM_LPTIM2_IC1_RMP_EVENTOUT LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to EVENTO…
441 #define LL_LPTIM_LPTIM2_IC1_RMP_MCO2 (LPTIM_CFGR2_IC1SEL_0 | LPTIM_CFGR2_IC1SEL_1) /*!< IC1 c…
Dstm32h5xx_hal_lptim.h528 #define LPTIM_IC1SOURCE_EVENTOUT LPTIM_CFGR2_IC1SEL_1 /*!…
529 #define LPTIM_IC1SOURCE_MCO1 (LPTIM_CFGR2_IC1SEL_0 | LPTIM_CFGR2_IC1SEL_1)/*!…
530 #define LPTIM_IC1SOURCE_MCO2 (LPTIM_CFGR2_IC1SEL_0 | LPTIM_CFGR2_IC1SEL_1)/*!…
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_lptim.h419 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
441 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
464 #define LL_LPTIM_LPTIM3_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 con…
Dstm32u5xx_hal_lptim.h526 #define LPTIM_IC1SOURCE_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< …
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_lptim.h436 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
482 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
504 #define LL_LPTIM_LPTIM3_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 con…
Dstm32u0xx_hal_lptim.h550 #define LPTIM_IC1SOURCE_COMP2 LPTIM_CFGR2_IC1SEL_1 /*…
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_lptim.h408 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
432 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
Dstm32wbaxx_hal_lptim.h530 #define LPTIM_IC1SOURCE_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< …
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h4884 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000… macro
Dstm32wba52xx.h8485 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000… macro
Dstm32wba54xx.h8719 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000… macro
Dstm32wba5mxx.h8719 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000… macro
Dstm32wba55xx.h8719 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000… macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8250 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000 */ macro
Dstm32u083xx.h9187 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000 */ macro
Dstm32u073xx.h8917 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000 */ macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h7799 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000… macro
Dstm32h523xx.h10238 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000… macro
Dstm32h562xx.h10964 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000… macro
Dstm32h533xx.h10647 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h11330 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000… macro
Dstm32u535xx.h10930 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000… macro
Dstm32u575xx.h11965 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000… macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h12733 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000 */ macro
Dstm32h7s7xx.h13322 #define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000 */ macro

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