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Searched refs:ECR (Results 1 – 25 of 107) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_tim.h3166 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler); in LL_TIM_OC_SetPulseWidthPrescaler()
3188 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC)); in LL_TIM_OC_GetPulseWidthPrescaler()
3203 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos); in LL_TIM_OC_SetPulseWidth()
3217 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW)); in LL_TIM_OC_GetPulseWidth()
4690 SET_BIT(TIMx->ECR, TIM_ECR_IE); in LL_TIM_EnableEncoderIndex()
4703 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE); in LL_TIM_DisableEncoderIndex()
4716 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U); in LL_TIM_IsEnabledEncoderIndex()
4733 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection); in LL_TIM_SetIndexDirection()
4749 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR)); in LL_TIM_GetIndexDirection()
4766 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking); in LL_TIM_SetIndexblanking()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_tim.h3082 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler); in LL_TIM_OC_SetPulseWidthPrescaler()
3104 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC)); in LL_TIM_OC_GetPulseWidthPrescaler()
3119 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos); in LL_TIM_OC_SetPulseWidth()
3133 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW)); in LL_TIM_OC_GetPulseWidth()
4552 SET_BIT(TIMx->ECR, TIM_ECR_IE); in LL_TIM_EnableEncoderIndex()
4565 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE); in LL_TIM_DisableEncoderIndex()
4578 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U); in LL_TIM_IsEnabledEncoderIndex()
4595 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection); in LL_TIM_SetIndexDirection()
4611 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR)); in LL_TIM_GetIndexDirection()
4628 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking); in LL_TIM_SetIndexblanking()
[all …]
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_tim.h3069 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler); in LL_TIM_OC_SetPulseWidthPrescaler()
3091 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC)); in LL_TIM_OC_GetPulseWidthPrescaler()
3106 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos); in LL_TIM_OC_SetPulseWidth()
3120 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW)); in LL_TIM_OC_GetPulseWidth()
4492 SET_BIT(TIMx->ECR, TIM_ECR_IE); in LL_TIM_EnableEncoderIndex()
4505 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE); in LL_TIM_DisableEncoderIndex()
4518 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U); in LL_TIM_IsEnabledEncoderIndex()
4535 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection); in LL_TIM_SetIndexDirection()
4551 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR)); in LL_TIM_GetIndexDirection()
4568 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking); in LL_TIM_SetIndexblanking()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_tim.h3378 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler); in LL_TIM_OC_SetPulseWidthPrescaler()
3400 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC)); in LL_TIM_OC_GetPulseWidthPrescaler()
3415 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos); in LL_TIM_OC_SetPulseWidth()
3429 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW)); in LL_TIM_OC_GetPulseWidth()
4877 SET_BIT(TIMx->ECR, TIM_ECR_IE); in LL_TIM_EnableEncoderIndex()
4890 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE); in LL_TIM_DisableEncoderIndex()
4903 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U); in LL_TIM_IsEnabledEncoderIndex()
4920 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection); in LL_TIM_SetIndexDirection()
4936 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR)); in LL_TIM_GetIndexDirection()
4953 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking); in LL_TIM_SetIndexblanking()
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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_tim.h3309 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler); in LL_TIM_OC_SetPulseWidthPrescaler()
3331 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC)); in LL_TIM_OC_GetPulseWidthPrescaler()
3346 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos); in LL_TIM_OC_SetPulseWidth()
3360 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW)); in LL_TIM_OC_GetPulseWidth()
4828 SET_BIT(TIMx->ECR, TIM_ECR_IE); in LL_TIM_EnableEncoderIndex()
4841 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE); in LL_TIM_DisableEncoderIndex()
4854 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U); in LL_TIM_IsEnabledEncoderIndex()
4871 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection); in LL_TIM_SetIndexDirection()
4887 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR)); in LL_TIM_GetIndexDirection()
4904 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking); in LL_TIM_SetIndexblanking()
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_tim.h3442 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler); in LL_TIM_OC_SetPulseWidthPrescaler()
3464 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC)); in LL_TIM_OC_GetPulseWidthPrescaler()
3479 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos); in LL_TIM_OC_SetPulseWidth()
3493 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW)); in LL_TIM_OC_GetPulseWidth()
4994 SET_BIT(TIMx->ECR, TIM_ECR_IE); in LL_TIM_EnableEncoderIndex()
5007 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE); in LL_TIM_DisableEncoderIndex()
5020 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U); in LL_TIM_IsEnabledEncoderIndex()
5037 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection); in LL_TIM_SetIndexDirection()
5053 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR)); in LL_TIM_GetIndexDirection()
5066 SET_BIT(TIMx->ECR, TIM_ECR_FIDX); in LL_TIM_EnableFirstIndex()
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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_tim_ex.c2854 tmpecr = htim->Instance->ECR; in HAL_TIMEx_OC_ConfigPulseOnCompare()
2861 htim->Instance->ECR = tmpecr; in HAL_TIMEx_OC_ConfigPulseOnCompare()
3044 MODIFY_REG(htim->Instance->ECR, in HAL_TIMEx_ConfigEncoderIndex()
3054 MODIFY_REG(htim->Instance->ECR, in HAL_TIMEx_ConfigEncoderIndex()
3062 MODIFY_REG(htim->Instance->ECR, in HAL_TIMEx_ConfigEncoderIndex()
3086 SET_BIT(htim->Instance->ECR, TIM_ECR_IE); in HAL_TIMEx_EnableEncoderIndex()
3100 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE); in HAL_TIMEx_DisableEncoderIndex()
3114 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
3128 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
Dstm32u5xx_hal_fdcan.c2506 CountersReg = READ_REG(hfdcan->Instance->ECR); in HAL_FDCAN_GetErrorCounters()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_tim_ex.c2735 tmpecr = htim->Instance->ECR; in HAL_TIMEx_OC_ConfigPulseOnCompare()
2742 htim->Instance->ECR = tmpecr; in HAL_TIMEx_OC_ConfigPulseOnCompare()
2922 MODIFY_REG(htim->Instance->ECR, in HAL_TIMEx_ConfigEncoderIndex()
2945 SET_BIT(htim->Instance->ECR, TIM_ECR_IE); in HAL_TIMEx_EnableEncoderIndex()
2959 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE); in HAL_TIMEx_DisableEncoderIndex()
2973 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
2987 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
Dstm32h7rsxx_hal_fdcan.c2513 CountersReg = READ_REG(hfdcan->Instance->ECR); in HAL_FDCAN_GetErrorCounters()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_tim_ex.c2780 tmpecr = htim->Instance->ECR; in HAL_TIMEx_OC_ConfigPulseOnCompare()
2787 htim->Instance->ECR = tmpecr; in HAL_TIMEx_OC_ConfigPulseOnCompare()
2967 MODIFY_REG(htim->Instance->ECR, in HAL_TIMEx_ConfigEncoderIndex()
2990 SET_BIT(htim->Instance->ECR, TIM_ECR_IE); in HAL_TIMEx_EnableEncoderIndex()
3004 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE); in HAL_TIMEx_DisableEncoderIndex()
3018 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
3032 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
Dstm32n6xx_hal_fdcan.c3292 CountersReg = READ_REG(hfdcan->Instance->ECR); in HAL_FDCAN_GetErrorCounters()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_tim_ex.c2710 tmpecr = htim->Instance->ECR; in HAL_TIMEx_OC_ConfigPulseOnCompare()
2717 htim->Instance->ECR = tmpecr; in HAL_TIMEx_OC_ConfigPulseOnCompare()
2897 MODIFY_REG(htim->Instance->ECR, in HAL_TIMEx_ConfigEncoderIndex()
2920 SET_BIT(htim->Instance->ECR, TIM_ECR_IE); in HAL_TIMEx_EnableEncoderIndex()
2934 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE); in HAL_TIMEx_DisableEncoderIndex()
2948 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
2962 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_tim_ex.c2858 tmpecr = htim->Instance->ECR; in HAL_TIMEx_OC_ConfigPulseOnCompare()
2865 htim->Instance->ECR = tmpecr; in HAL_TIMEx_OC_ConfigPulseOnCompare()
3045 MODIFY_REG(htim->Instance->ECR, in HAL_TIMEx_ConfigEncoderIndex()
3068 SET_BIT(htim->Instance->ECR, TIM_ECR_IE); in HAL_TIMEx_EnableEncoderIndex()
3082 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE); in HAL_TIMEx_DisableEncoderIndex()
3096 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
3110 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
Dstm32h5xx_hal_fdcan.c2513 CountersReg = READ_REG(hfdcan->Instance->ECR); in HAL_FDCAN_GetErrorCounters()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_tim_ex.c3052 tmpecr = htim->Instance->ECR; in HAL_TIMEx_OC_ConfigPulseOnCompare()
3059 htim->Instance->ECR = tmpecr; in HAL_TIMEx_OC_ConfigPulseOnCompare()
3238 MODIFY_REG(htim->Instance->ECR, in HAL_TIMEx_ConfigEncoderIndex()
3260 SET_BIT(htim->Instance->ECR, TIM_ECR_IE); in HAL_TIMEx_EnableEncoderIndex()
3274 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE); in HAL_TIMEx_DisableEncoderIndex()
3288 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_EnableEncoderFirstIndex()
3302 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); in HAL_TIMEx_DisableEncoderFirstIndex()
Dstm32g4xx_hal_fdcan.c2513 CountersReg = READ_REG(hfdcan->Instance->ECR); in HAL_FDCAN_GetErrorCounters()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_hal_fdcan.c2513 CountersReg = READ_REG(hfdcan->Instance->ECR); in HAL_FDCAN_GetErrorCounters()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_fdcan.c2506 CountersReg = READ_REG(hfdcan->Instance->ECR); in HAL_FDCAN_GetErrorCounters()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_fdcan.c2236 CountersReg = READ_REG(hfdcan->Instance->ECR); in HAL_FDCAN_GetErrorCounters()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_fdcan.c3292 CountersReg = READ_REG(hfdcan->Instance->ECR); in HAL_FDCAN_GetErrorCounters()
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h227 …__IO uint32_t ECR; /*!< FDCAN Error Counter register, … member
748 __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ member
Dstm32g411xc.h236 …__IO uint32_t ECR; /*!< FDCAN Error Counter register, … member
763 __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ member
Dstm32g441xx.h237 …__IO uint32_t ECR; /*!< FDCAN Error Counter register, … member
780 __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ member
Dstm32gbk1cb.h235 …__IO uint32_t ECR; /*!< FDCAN Error Counter register, … member
778 __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ member

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