3309   MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);  in LL_TIM_OC_SetPulseWidthPrescaler()
3331   return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));  in LL_TIM_OC_GetPulseWidthPrescaler()
3346   MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);  in LL_TIM_OC_SetPulseWidth()
3360   return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));  in LL_TIM_OC_GetPulseWidth()
4828   SET_BIT(TIMx->ECR, TIM_ECR_IE);  in LL_TIM_EnableEncoderIndex()
4841   CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);  in LL_TIM_DisableEncoderIndex()
4854   return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);  in LL_TIM_IsEnabledEncoderIndex()
4871   MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);  in LL_TIM_SetIndexDirection()
4887   return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));  in LL_TIM_GetIndexDirection()
4904   MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);  in LL_TIM_SetIndexblanking()
4920   return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));  in LL_TIM_GetIndexblanking()
4934   SET_BIT(TIMx->ECR, TIM_ECR_FIDX);  in LL_TIM_EnableFirstIndex()
4947   CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);  in LL_TIM_DisableFirstIndex()
4960   return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);  in LL_TIM_IsEnabledFirstIndex()
4980   MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);  in LL_TIM_SetIndexPositionning()
4999   return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));  in LL_TIM_GetIndexPositionning()
5020   MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);  in LL_TIM_ConfigIDX()