/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/ |
D | stm32n6xx_ll_tim.h | 4485 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime() 4498 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime() 4511 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime() 4529 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); in LL_TIM_SetFallingDeadTime() 4545 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); in LL_TIM_GetFallingDeadTime() 4558 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_EnableDeadTimePreload() 4571 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_DisableDeadTimePreload() 4584 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDeadTimePreload()
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/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/ |
D | stm32h7rsxx_ll_tim.h | 4347 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime() 4360 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime() 4373 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime() 4391 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); in LL_TIM_SetFallingDeadTime() 4407 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); in LL_TIM_GetFallingDeadTime() 4420 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_EnableDeadTimePreload() 4433 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_DisableDeadTimePreload() 4446 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDeadTimePreload()
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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/ |
D | stm32wbaxx_ll_tim.h | 4286 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime() 4299 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime() 4312 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime() 4330 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); in LL_TIM_SetFallingDeadTime() 4346 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); in LL_TIM_GetFallingDeadTime() 4359 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_EnableDeadTimePreload() 4372 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_DisableDeadTimePreload() 4385 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDeadTimePreload()
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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/ |
D | stm32h5xx_ll_tim.h | 4671 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime() 4684 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime() 4697 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime() 4715 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); in LL_TIM_SetFallingDeadTime() 4731 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); in LL_TIM_GetFallingDeadTime() 4744 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_EnableDeadTimePreload() 4757 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_DisableDeadTimePreload() 4770 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDeadTimePreload()
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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/ |
D | stm32u5xx_ll_tim.h | 4622 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime() 4635 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime() 4648 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime() 4666 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); in LL_TIM_SetFallingDeadTime() 4682 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); in LL_TIM_GetFallingDeadTime() 4695 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_EnableDeadTimePreload() 4708 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_DisableDeadTimePreload() 4721 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDeadTimePreload()
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/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/ |
D | stm32g4xx_ll_tim.h | 4798 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime() 4811 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime() 4824 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime() 4842 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); in LL_TIM_SetFallingDeadTime() 4858 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); in LL_TIM_GetFallingDeadTime() 4871 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_EnableDeadTimePreload() 4884 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_DisableDeadTimePreload() 4897 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDeadTimePreload()
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/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/ |
D | stm32h7rsxx_hal_tim_ex.c | 2810 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_EnableDeadTimePreload() 2824 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_DisableDeadTimePreload() 2858 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); in HAL_TIMEx_ConfigAsymmetricalDeadTime() 2872 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime() 2886 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/ |
D | stm32u5xx_hal_tim_ex.c | 2929 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_EnableDeadTimePreload() 2943 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_DisableDeadTimePreload() 2977 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); in HAL_TIMEx_ConfigAsymmetricalDeadTime() 2991 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime() 3005 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
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/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/ |
D | stm32n6xx_hal_tim_ex.c | 2855 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_EnableDeadTimePreload() 2869 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_DisableDeadTimePreload() 2903 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); in HAL_TIMEx_ConfigAsymmetricalDeadTime() 2917 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime() 2931 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/ |
D | stm32wbaxx_hal_tim_ex.c | 2785 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_EnableDeadTimePreload() 2799 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_DisableDeadTimePreload() 2833 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); in HAL_TIMEx_ConfigAsymmetricalDeadTime() 2847 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime() 2861 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/ |
D | stm32h5xx_hal_tim_ex.c | 2933 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_EnableDeadTimePreload() 2947 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_DisableDeadTimePreload() 2981 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); in HAL_TIMEx_ConfigAsymmetricalDeadTime() 2995 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime() 3009 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
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/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/ |
D | stm32g4xx_hal_tim_ex.c | 3127 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_EnableDeadTimePreload() 3141 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_DisableDeadTimePreload() 3175 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); in HAL_TIMEx_ConfigAsymmetricalDeadTime() 3189 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime() 3203 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 791 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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D | stm32wba52xx.h | 889 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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/hal_stm32-latest/stm32cube/stm32g4xx/soc/ |
D | stm32g411xb.h | 747 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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D | stm32g411xc.h | 762 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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D | stm32g441xx.h | 779 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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D | stm32gbk1cb.h | 777 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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D | stm32g431xx.h | 778 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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D | stm32g4a1xx.h | 828 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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D | stm32g491xx.h | 827 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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D | stm32g473xx.h | 875 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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D | stm32g471xx.h | 836 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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D | stm32g483xx.h | 876 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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/hal_stm32-latest/stm32cube/stm32h5xx/soc/ |
D | stm32h503xx.h | 586 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
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