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Searched refs:DTR2 (Results 1 – 25 of 56) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_tim.h4485 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime()
4498 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime()
4511 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime()
4529 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); in LL_TIM_SetFallingDeadTime()
4545 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); in LL_TIM_GetFallingDeadTime()
4558 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_EnableDeadTimePreload()
4571 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_DisableDeadTimePreload()
4584 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDeadTimePreload()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_tim.h4347 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime()
4360 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime()
4373 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime()
4391 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); in LL_TIM_SetFallingDeadTime()
4407 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); in LL_TIM_GetFallingDeadTime()
4420 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_EnableDeadTimePreload()
4433 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_DisableDeadTimePreload()
4446 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDeadTimePreload()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_tim.h4286 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime()
4299 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime()
4312 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime()
4330 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); in LL_TIM_SetFallingDeadTime()
4346 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); in LL_TIM_GetFallingDeadTime()
4359 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_EnableDeadTimePreload()
4372 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_DisableDeadTimePreload()
4385 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDeadTimePreload()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_tim.h4671 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime()
4684 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime()
4697 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime()
4715 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); in LL_TIM_SetFallingDeadTime()
4731 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); in LL_TIM_GetFallingDeadTime()
4744 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_EnableDeadTimePreload()
4757 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_DisableDeadTimePreload()
4770 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDeadTimePreload()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_tim.h4622 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime()
4635 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime()
4648 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime()
4666 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); in LL_TIM_SetFallingDeadTime()
4682 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); in LL_TIM_GetFallingDeadTime()
4695 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_EnableDeadTimePreload()
4708 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_DisableDeadTimePreload()
4721 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDeadTimePreload()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_tim.h4798 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_EnableAsymmetricalDeadTime()
4811 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); in LL_TIM_DisableAsymmetricalDeadTime()
4824 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAsymmetricalDeadTime()
4842 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); in LL_TIM_SetFallingDeadTime()
4858 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); in LL_TIM_GetFallingDeadTime()
4871 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_EnableDeadTimePreload()
4884 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); in LL_TIM_DisableDeadTimePreload()
4897 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDeadTimePreload()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_tim_ex.c2810 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_EnableDeadTimePreload()
2824 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_DisableDeadTimePreload()
2858 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); in HAL_TIMEx_ConfigAsymmetricalDeadTime()
2872 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime()
2886 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_tim_ex.c2929 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_EnableDeadTimePreload()
2943 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_DisableDeadTimePreload()
2977 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); in HAL_TIMEx_ConfigAsymmetricalDeadTime()
2991 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime()
3005 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_tim_ex.c2855 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_EnableDeadTimePreload()
2869 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_DisableDeadTimePreload()
2903 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); in HAL_TIMEx_ConfigAsymmetricalDeadTime()
2917 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime()
2931 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_tim_ex.c2785 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_EnableDeadTimePreload()
2799 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_DisableDeadTimePreload()
2833 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); in HAL_TIMEx_ConfigAsymmetricalDeadTime()
2847 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime()
2861 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_tim_ex.c2933 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_EnableDeadTimePreload()
2947 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_DisableDeadTimePreload()
2981 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); in HAL_TIMEx_ConfigAsymmetricalDeadTime()
2995 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime()
3009 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_tim_ex.c3127 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_EnableDeadTimePreload()
3141 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); in HAL_TIMEx_DisableDeadTimePreload()
3175 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); in HAL_TIMEx_ConfigAsymmetricalDeadTime()
3189 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_EnableAsymmetricalDeadTime()
3203 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); in HAL_TIMEx_DisableAsymmetricalDeadTime()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h791 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
Dstm32wba52xx.h889 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h747 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
Dstm32g411xc.h762 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
Dstm32g441xx.h779 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
Dstm32gbk1cb.h777 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
Dstm32g431xx.h778 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
Dstm32g4a1xx.h828 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
Dstm32g491xx.h827 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
Dstm32g473xx.h875 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
Dstm32g471xx.h836 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
Dstm32g483xx.h876 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h586 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ member

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