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Searched refs:DMA2D_AMTCR_EN (Results 1 – 25 of 79) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_dma2d.h817 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_EnableDeadTime()
828 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_DisableDeadTime()
839 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); in LL_DMA2D_IsEnabledDeadTime()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_dma2d.h1012 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_EnableDeadTime()
1023 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_DisableDeadTime()
1034 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); in LL_DMA2D_IsEnabledDeadTime()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_dma2d.h921 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_EnableDeadTime()
932 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_DisableDeadTime()
943 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); in LL_DMA2D_IsEnabledDeadTime()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_dma2d.h1012 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_EnableDeadTime()
1023 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_DisableDeadTime()
1034 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); in LL_DMA2D_IsEnabledDeadTime()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_dma2d.h1025 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_EnableDeadTime()
1036 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_DisableDeadTime()
1047 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); in LL_DMA2D_IsEnabledDeadTime()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_dma2d.h1012 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_EnableDeadTime()
1023 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_DisableDeadTime()
1034 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); in LL_DMA2D_IsEnabledDeadTime()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma2d.h1018 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_EnableDeadTime()
1029 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); in LL_DMA2D_DisableDeadTime()
1040 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); in LL_DMA2D_IsEnabledDeadTime()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_dma2d.c1924 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_EnableDeadTime()
1947 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_DisableDeadTime()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_dma2d.c1980 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_EnableDeadTime()
2003 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_DisableDeadTime()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_dma2d.c1980 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_EnableDeadTime()
2003 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_DisableDeadTime()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_dma2d.c1944 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_EnableDeadTime()
1967 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_DisableDeadTime()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_dma2d.c1980 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_EnableDeadTime()
2003 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_DisableDeadTime()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dma2d.c1984 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_EnableDeadTime()
2007 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_DisableDeadTime()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_dma2d.c2000 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_EnableDeadTime()
2023 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); in HAL_DMA2D_DisableDeadTime()
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f427xx.h6555 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ macro
Dstm32f429xx.h6614 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ macro
Dstm32f439xx.h6801 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ macro
Dstm32f437xx.h6747 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ macro
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f750xx.h6889 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ macro
Dstm32f745xx.h6646 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ macro
Dstm32f756xx.h6889 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ macro
Dstm32f746xx.h6701 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ macro
Dstm32f765xx.h7124 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ macro
Dstm32f777xx.h7406 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ macro
Dstm32f767xx.h7218 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ macro

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