1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_dma2d.h
4 * @author MCD Application Team
5 * @brief Header file of DMA2D LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_DMA2D_H
21 #define STM32L4xx_LL_DMA2D_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA2D)
35
36 /** @defgroup DMA2D_LL DMA2D
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 #if defined(USE_FULL_LL_DRIVER)
45 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
46 * @{
47 */
48
49 /**
50 * @}
51 */
52 #endif /*USE_FULL_LL_DRIVER*/
53
54 /* Exported types ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
57 * @{
58 */
59
60 /**
61 * @brief LL DMA2D Init Structure Definition
62 */
63 typedef struct
64 {
65 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
66 - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
67
68 This parameter can be modified afterwards,
69 using unitary function @ref LL_DMA2D_SetMode(). */
70
71 uint32_t ColorMode; /*!< Specifies the color format of the output image.
72 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
73
74 This parameter can be modified afterwards using,
75 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
76
77 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
78 - This parameter must be a number between:
79 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
80 - This parameter must be a number between:
81 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
82 - This parameter must be a number between:
83 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
84 - This parameter must be a number between:
85 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
86 - This parameter must be a number between:
87 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
88
89 This parameter can be modified afterwards,
90 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
91 function @ref LL_DMA2D_ConfigOutputColor(). */
92
93 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
94 - This parameter must be a number between:
95 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
96 - This parameter must be a number between:
97 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
98 - This parameter must be a number between:
99 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
100 - This parameter must be a number between:
101 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
102 - This parameter must be a number between:
103 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
104
105 This parameter can be modified afterwards
106 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
107 function @ref LL_DMA2D_ConfigOutputColor(). */
108
109 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
110 - This parameter must be a number between:
111 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
112 - This parameter must be a number between:
113 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
114 - This parameter must be a number between:
115 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
116 - This parameter must be a number between:
117 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
118 - This parameter must be a number between:
119 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
120
121 This parameter can be modified afterwards
122 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
123 function @ref LL_DMA2D_ConfigOutputColor(). */
124
125 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
126 - This parameter must be a number between:
127 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
128 - This parameter must be a number between:
129 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
130 - This parameter must be a number between:
131 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
132 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
133
134 This parameter can be modified afterwards using,
135 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
136 function @ref LL_DMA2D_ConfigOutputColor(). */
137
138 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
139 - This parameter must be a number between:
140 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
141
142 This parameter can be modified afterwards,
143 using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
144
145 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
146 uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image.
147 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
148
149 This parameter can be modified afterwards,
150 using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
151 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
152
153 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
154 uint32_t LineOffsetMode; /*!< Specifies the output line offset mode.
155 - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
156
157 This parameter can be modified afterwards,
158 using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
159 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
160
161 uint32_t LineOffset; /*!< Specifies the output line offset value.
162 - This parameter must be a number between:
163 Min_Data = 0x0000 and Max_Data = 0x3FFF on devices
164 where the Line Offset Mode feature is available.
165 else between Min_Data = 0x0000 and Max_Data = 0xFFFF on other devices.
166
167 This parameter can be modified afterwards,
168 using unitary function @ref LL_DMA2D_SetLineOffset(). */
169
170 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
171 - This parameter must be a number between:
172 Min_Data = 0x0000 and Max_Data = 0xFFFF.
173
174 This parameter can be modified afterwards,
175 using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
176
177 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
178 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
179
180 This parameter can be modified afterwards using,
181 unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
182
183 uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
184 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
185
186 This parameter can be modified afterwards,
187 using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
188
189 uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
190 - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
191
192 This parameter can be modified afterwards,
193 using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
194
195 } LL_DMA2D_InitTypeDef;
196
197 /**
198 * @brief LL DMA2D Layer Configuration Structure Definition
199 */
200 typedef struct
201 {
202 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
203 - This parameter must be a number between:
204 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
205
206 This parameter can be modified afterwards using unitary functions
207 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
208 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
209
210 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
211 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
212
213 This parameter can be modified afterwards using unitary functions
214 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
215 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
216
217 uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
218 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
219
220 This parameter can be modified afterwards using unitary functions
221 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
222 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
223
224 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
225 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
226
227 This parameter can be modified afterwards using unitary functions
228 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
229 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
230
231 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
232 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
233
234 This parameter can be modified afterwards using unitary functions
235 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
236 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
237
238 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
239 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
240
241 This parameter can be modified afterwards using unitary functions
242 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
243 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
244
245 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
246 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
247
248 This parameter can be modified afterwards using unitary functions
249 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
250 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
251
252 uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
253 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
254
255 This parameter can be modified afterwards using unitary functions
256 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
257 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
258
259 uint32_t Green; /*!< Specifies the foreground or background Green color value.
260 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
261
262 This parameter can be modified afterwards using unitary functions
263 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
264 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
265
266 uint32_t Red; /*!< Specifies the foreground or background Red color value.
267 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
268
269 This parameter can be modified afterwards using unitary functions
270 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
271 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
272
273 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
274 - This parameter must be a number between:
275 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
276
277 This parameter can be modified afterwards using unitary functions
278 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
279 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
280
281 uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
282 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
283
284 This parameter can be modified afterwards using unitary functions
285 - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
286 - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
287
288 uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
289 This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
290
291 This parameter can be modified afterwards using unitary functions
292 - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
293 - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
294
295
296 } LL_DMA2D_LayerCfgTypeDef;
297
298 /**
299 * @brief LL DMA2D Output Color Structure Definition
300 */
301 typedef struct
302 {
303 uint32_t ColorMode; /*!< Specifies the color format of the output image.
304 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
305
306 This parameter can be modified afterwards using
307 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
308
309 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
310 - This parameter must be a number between:
311 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
312 - This parameter must be a number between:
313 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
314 - This parameter must be a number between:
315 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
316 - This parameter must be a number between:
317 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
318 - This parameter must be a number between:
319 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
320
321 This parameter can be modified afterwards using,
322 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
323 function @ref LL_DMA2D_ConfigOutputColor(). */
324
325 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
326 - This parameter must be a number between:
327 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
328 - This parameter must be a number between
329 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
330 - This parameter must be a number between:
331 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
332 - This parameter must be a number between:
333 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
334 - This parameter must be a number between:
335 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
336
337 This parameter can be modified afterwards,
338 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
339 function @ref LL_DMA2D_ConfigOutputColor(). */
340
341 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
342 - This parameter must be a number between:
343 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
344 - This parameter must be a number between:
345 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
346 - This parameter must be a number between:
347 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
348 - This parameter must be a number between:
349 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
350 - This parameter must be a number between:
351 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
352
353 This parameter can be modified afterwards,
354 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
355 function @ref LL_DMA2D_ConfigOutputColor(). */
356
357 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
358 - This parameter must be a number between:
359 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
360 - This parameter must be a number between:
361 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
362 - This parameter must be a number between:
363 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
364 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
365
366 This parameter can be modified afterwards,
367 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
368 function @ref LL_DMA2D_ConfigOutputColor(). */
369
370 } LL_DMA2D_ColorTypeDef;
371
372 /**
373 * @}
374 */
375 #endif /* USE_FULL_LL_DRIVER */
376
377 /* Exported constants --------------------------------------------------------*/
378 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
379 * @{
380 */
381
382 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
383 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
384 * @{
385 */
386 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
387 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
388 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
389 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
390 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
391 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
392 /**
393 * @}
394 */
395
396 /** @defgroup DMA2D_LL_EC_IT IT Defines
397 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
398 * @{
399 */
400 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
401 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
402 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
403 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
404 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
405 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
406 /**
407 * @}
408 */
409
410 /** @defgroup DMA2D_LL_EC_MODE Mode
411 * @{
412 */
413 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
414 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
415 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
416 #define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */
417 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
418 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */
419 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */
420 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */
421 /**
422 * @}
423 */
424
425 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
426 * @{
427 */
428 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
429 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
430 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
431 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
432 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
433 /**
434 * @}
435 */
436
437 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
438 * @{
439 */
440 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
441 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
442 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
443 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
444 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
445 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
446 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
447 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
448 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
449 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
450 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
451 /**
452 * @}
453 */
454
455 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
456 * @{
457 */
458 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
459 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
460 programmed alpha value */
461 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
462 programmed alpha value with,
463 original alpha channel value */
464 /**
465 * @}
466 */
467
468 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
469 /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode
470 * @{
471 */
472 #define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */
473 #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */
474 /**
475 * @}
476 */
477 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
478
479 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
480 * @{
481 */
482 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */
483 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */
484 /**
485 * @}
486 */
487
488 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
489 * @{
490 */
491 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */
492 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */
493 /**
494 * @}
495 */
496
497
498 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
499 /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode
500 * @{
501 */
502 #define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */
503 #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */
504 /**
505 * @}
506 */
507 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
508
509 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
510 * @{
511 */
512 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
513 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
514 /**
515 * @}
516 */
517
518
519 /**
520 * @}
521 */
522
523 /* Exported macro ------------------------------------------------------------*/
524 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
525 * @{
526 */
527
528 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
529 * @{
530 */
531
532 /**
533 * @brief Write a value in DMA2D register.
534 * @param __INSTANCE__ DMA2D Instance
535 * @param __REG__ Register to be written
536 * @param __VALUE__ Value to be written in the register
537 * @retval None
538 */
539 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
540
541 /**
542 * @brief Read a value in DMA2D register.
543 * @param __INSTANCE__ DMA2D Instance
544 * @param __REG__ Register to be read
545 * @retval Register value
546 */
547 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
548 /**
549 * @}
550 */
551
552 /**
553 * @}
554 */
555
556 /* Exported functions --------------------------------------------------------*/
557 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
558 * @{
559 */
560
561 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
562 * @{
563 */
564
565 /**
566 * @brief Start a DMA2D transfer.
567 * @rmtoll CR START LL_DMA2D_Start
568 * @param DMA2Dx DMA2D Instance
569 * @retval None
570 */
LL_DMA2D_Start(DMA2D_TypeDef * DMA2Dx)571 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
572 {
573 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
574 }
575
576 /**
577 * @brief Indicate if a DMA2D transfer is ongoing.
578 * @rmtoll CR START LL_DMA2D_IsTransferOngoing
579 * @param DMA2Dx DMA2D Instance
580 * @retval State of bit (1 or 0).
581 */
LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef * DMA2Dx)582 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef *DMA2Dx)
583 {
584 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
585 }
586
587 /**
588 * @brief Suspend DMA2D transfer.
589 * @note This API can be used to suspend automatic foreground or background CLUT loading.
590 * @rmtoll CR SUSP LL_DMA2D_Suspend
591 * @param DMA2Dx DMA2D Instance
592 * @retval None
593 */
LL_DMA2D_Suspend(DMA2D_TypeDef * DMA2Dx)594 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
595 {
596 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
597 }
598
599 /**
600 * @brief Resume DMA2D transfer.
601 * @note This API can be used to resume automatic foreground or background CLUT loading.
602 * @rmtoll CR SUSP LL_DMA2D_Resume
603 * @param DMA2Dx DMA2D Instance
604 * @retval None
605 */
LL_DMA2D_Resume(DMA2D_TypeDef * DMA2Dx)606 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
607 {
608 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
609 }
610
611 /**
612 * @brief Indicate if DMA2D transfer is suspended.
613 * @note This API can be used to indicate whether or not automatic foreground or
614 * background CLUT loading is suspended.
615 * @rmtoll CR SUSP LL_DMA2D_IsSuspended
616 * @param DMA2Dx DMA2D Instance
617 * @retval State of bit (1 or 0).
618 */
LL_DMA2D_IsSuspended(const DMA2D_TypeDef * DMA2Dx)619 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(const DMA2D_TypeDef *DMA2Dx)
620 {
621 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
622 }
623
624 /**
625 * @brief Abort DMA2D transfer.
626 * @note This API can be used to abort automatic foreground or background CLUT loading.
627 * @rmtoll CR ABORT LL_DMA2D_Abort
628 * @param DMA2Dx DMA2D Instance
629 * @retval None
630 */
LL_DMA2D_Abort(DMA2D_TypeDef * DMA2Dx)631 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
632 {
633 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
634 }
635
636 /**
637 * @brief Indicate if DMA2D transfer is aborted.
638 * @note This API can be used to indicate whether or not automatic foreground or
639 * background CLUT loading is aborted.
640 * @rmtoll CR ABORT LL_DMA2D_IsAborted
641 * @param DMA2Dx DMA2D Instance
642 * @retval State of bit (1 or 0).
643 */
LL_DMA2D_IsAborted(const DMA2D_TypeDef * DMA2Dx)644 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(const DMA2D_TypeDef *DMA2Dx)
645 {
646 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
647 }
648
649 /**
650 * @brief Set DMA2D mode.
651 * @rmtoll CR MODE LL_DMA2D_SetMode
652 * @param DMA2Dx DMA2D Instance
653 * @param Mode This parameter can be one of the following values:
654 * @arg @ref LL_DMA2D_MODE_M2M
655 * @arg @ref LL_DMA2D_MODE_M2M_PFC
656 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
657 * @arg @ref LL_DMA2D_MODE_R2M
658 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG (*)
659 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (*)
660 *
661 * (*) value not defined in all devices.
662 * @retval None
663 */
LL_DMA2D_SetMode(DMA2D_TypeDef * DMA2Dx,uint32_t Mode)664 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
665 {
666 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
667 }
668
669 /**
670 * @brief Return DMA2D mode
671 * @rmtoll CR MODE LL_DMA2D_GetMode
672 * @param DMA2Dx DMA2D Instance
673 * @retval Returned value can be one of the following values:
674 * @arg @ref LL_DMA2D_MODE_M2M
675 * @arg @ref LL_DMA2D_MODE_M2M_PFC
676 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
677 * @arg @ref LL_DMA2D_MODE_R2M
678 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG (*)
679 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (*)
680 *
681 * (*) value not defined in all devices.
682 */
LL_DMA2D_GetMode(const DMA2D_TypeDef * DMA2Dx)683 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(const DMA2D_TypeDef *DMA2Dx)
684 {
685 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
686 }
687
688 /**
689 * @brief Set DMA2D output color mode.
690 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
691 * @param DMA2Dx DMA2D Instance
692 * @param ColorMode This parameter can be one of the following values:
693 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
694 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
695 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
696 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
697 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
698 * @retval None
699 */
LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)700 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
701 {
702 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
703 }
704
705 /**
706 * @brief Return DMA2D output color mode.
707 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
708 * @param DMA2Dx DMA2D Instance
709 * @retval Returned value can be one of the following values:
710 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
711 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
712 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
713 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
714 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
715 */
LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef * DMA2Dx)716 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef *DMA2Dx)
717 {
718 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
719 }
720
721 /**
722 * @brief Set DMA2D output Red Blue swap mode.
723 * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
724 * @param DMA2Dx DMA2D Instance
725 * @param RBSwapMode This parameter can be one of the following values:
726 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
727 * @arg @ref LL_DMA2D_RB_MODE_SWAP
728 * @retval None
729 */
LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)730 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
731 {
732 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
733 }
734
735 /**
736 * @brief Return DMA2D output Red Blue swap mode.
737 * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
738 * @param DMA2Dx DMA2D Instance
739 * @retval Returned value can be one of the following values:
740 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
741 * @arg @ref LL_DMA2D_RB_MODE_SWAP
742 */
LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef * DMA2Dx)743 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef *DMA2Dx)
744 {
745 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
746 }
747
748 /**
749 * @brief Set DMA2D output alpha inversion mode.
750 * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
751 * @param DMA2Dx DMA2D Instance
752 * @param AlphaInversionMode This parameter can be one of the following values:
753 * @arg @ref LL_DMA2D_ALPHA_REGULAR
754 * @arg @ref LL_DMA2D_ALPHA_INVERTED
755 * @retval None
756 */
LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)757 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
758 {
759 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
760 }
761
762 /**
763 * @brief Return DMA2D output alpha inversion mode.
764 * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
765 * @param DMA2Dx DMA2D Instance
766 * @retval Returned value can be one of the following values:
767 * @arg @ref LL_DMA2D_ALPHA_REGULAR
768 * @arg @ref LL_DMA2D_ALPHA_INVERTED
769 */
LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef * DMA2Dx)770 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef *DMA2Dx)
771 {
772 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
773 }
774
775
776 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
777 /**
778 * @brief Set DMA2D output swap mode.
779 * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode
780 * @param DMA2Dx DMA2D Instance
781 * @param OutputSwapMode This parameter can be one of the following values:
782 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
783 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
784 * @retval None
785 */
LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t OutputSwapMode)786 __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
787 {
788 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
789 }
790
791 /**
792 * @brief Return DMA2D output swap mode.
793 * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode
794 * @param DMA2Dx DMA2D Instance
795 * @retval Returned value can be one of the following values:
796 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
797 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
798 */
LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef * DMA2Dx)799 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx)
800 {
801 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
802 }
803 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
804
805 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
806 /**
807 * @brief Set DMA2D line offset mode.
808 * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode
809 * @param DMA2Dx DMA2D Instance
810 * @param LineOffsetMode This parameter can be one of the following values:
811 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
812 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
813 * @retval None
814 */
LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffsetMode)815 __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
816 {
817 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
818 }
819
820 /**
821 * @brief Return DMA2D line offset mode.
822 * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode
823 * @param DMA2Dx DMA2D Instance
824 * @retval Returned value can be one of the following values:
825 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
826 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
827 */
LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef * DMA2Dx)828 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef *DMA2Dx)
829 {
830 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
831 }
832 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
833
834 /**
835 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
836 * @rmtoll OOR LO LL_DMA2D_SetLineOffset
837 * @param DMA2Dx DMA2D Instance
838 @if DMA2D_LINE_OFFSET_MODE_SUPPORT
839 * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF
840 @else
841 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF
842 @endif
843 * @retval None
844 */
LL_DMA2D_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)845 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
846 {
847 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
848 }
849
850 /**
851 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
852 * @rmtoll OOR LO LL_DMA2D_GetLineOffset
853 * @param DMA2Dx DMA2D Instance
854 @if DMA2D_LINE_OFFSET_MODE_SUPPORT
855 * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF
856 @else
857 * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
858 @endif
859 */
LL_DMA2D_GetLineOffset(const DMA2D_TypeDef * DMA2Dx)860 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
861 {
862 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
863 }
864
865 /**
866 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
867 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
868 * @param DMA2Dx DMA2D Instance
869 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
870 * @retval None
871 */
LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfPixelsPerLines)872 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
873 {
874 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
875 }
876
877 /**
878 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
879 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
880 * @param DMA2Dx DMA2D Instance
881 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
882 */
LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef * DMA2Dx)883 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef *DMA2Dx)
884 {
885 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
886 }
887
888 /**
889 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
890 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
891 * @param DMA2Dx DMA2D Instance
892 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
893 * @retval None
894 */
LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfLines)895 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
896 {
897 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
898 }
899
900 /**
901 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
902 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
903 * @param DMA2Dx DMA2D Instance
904 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
905 */
LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef * DMA2Dx)906 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef *DMA2Dx)
907 {
908 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
909 }
910
911 /**
912 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
913 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
914 * @param DMA2Dx DMA2D Instance
915 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
916 * @retval None
917 */
LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t OutputMemoryAddress)918 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
919 {
920 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
921 }
922
923 /**
924 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
925 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
926 * @param DMA2Dx DMA2D Instance
927 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
928 */
LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef * DMA2Dx)929 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx)
930 {
931 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
932 }
933
934 /**
935 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
936 * @note Output color format depends on output color mode, ARGB8888, RGB888,
937 * RGB565, ARGB1555 or ARGB4444.
938 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
939 * with respect to color mode is not done by the user code.
940 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
941 * OCOLR GREEN LL_DMA2D_SetOutputColor\n
942 * OCOLR RED LL_DMA2D_SetOutputColor\n
943 * OCOLR ALPHA LL_DMA2D_SetOutputColor
944 * @param DMA2Dx DMA2D Instance
945 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
946 * @retval None
947 */
LL_DMA2D_SetOutputColor(DMA2D_TypeDef * DMA2Dx,uint32_t OutputColor)948 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
949 {
950 WRITE_REG(DMA2Dx->OCOLR, OutputColor);
951 }
952
953 /**
954 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
955 * @note Alpha channel and red, green, blue color values must be retrieved from the returned
956 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
957 * as set by @ref LL_DMA2D_SetOutputColorMode.
958 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
959 * OCOLR GREEN LL_DMA2D_GetOutputColor\n
960 * OCOLR RED LL_DMA2D_GetOutputColor\n
961 * OCOLR ALPHA LL_DMA2D_GetOutputColor
962 * @param DMA2Dx DMA2D Instance
963 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
964 */
LL_DMA2D_GetOutputColor(const DMA2D_TypeDef * DMA2Dx)965 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(const DMA2D_TypeDef *DMA2Dx)
966 {
967 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
968 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
969 }
970
971 /**
972 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
973 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
974 * @param DMA2Dx DMA2D Instance
975 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
976 * @retval None
977 */
LL_DMA2D_SetLineWatermark(DMA2D_TypeDef * DMA2Dx,uint32_t LineWatermark)978 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
979 {
980 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
981 }
982
983 /**
984 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
985 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
986 * @param DMA2Dx DMA2D Instance
987 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
988 */
LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef * DMA2Dx)989 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef *DMA2Dx)
990 {
991 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
992 }
993
994 /**
995 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
996 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
997 * @param DMA2Dx DMA2D Instance
998 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
999 * @retval None
1000 */
LL_DMA2D_SetDeadTime(DMA2D_TypeDef * DMA2Dx,uint32_t DeadTime)1001 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
1002 {
1003 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
1004 }
1005
1006 /**
1007 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
1008 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
1009 * @param DMA2Dx DMA2D Instance
1010 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
1011 */
LL_DMA2D_GetDeadTime(const DMA2D_TypeDef * DMA2Dx)1012 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(const DMA2D_TypeDef *DMA2Dx)
1013 {
1014 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
1015 }
1016
1017 /**
1018 * @brief Enable DMA2D dead time functionality.
1019 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
1020 * @param DMA2Dx DMA2D Instance
1021 * @retval None
1022 */
LL_DMA2D_EnableDeadTime(DMA2D_TypeDef * DMA2Dx)1023 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
1024 {
1025 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
1026 }
1027
1028 /**
1029 * @brief Disable DMA2D dead time functionality.
1030 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
1031 * @param DMA2Dx DMA2D Instance
1032 * @retval None
1033 */
LL_DMA2D_DisableDeadTime(DMA2D_TypeDef * DMA2Dx)1034 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
1035 {
1036 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
1037 }
1038
1039 /**
1040 * @brief Indicate if DMA2D dead time functionality is enabled.
1041 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
1042 * @param DMA2Dx DMA2D Instance
1043 * @retval State of bit (1 or 0).
1044 */
LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef * DMA2Dx)1045 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef *DMA2Dx)
1046 {
1047 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
1048 }
1049
1050 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
1051 * @{
1052 */
1053
1054 /**
1055 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
1056 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
1057 * @param DMA2Dx DMA2D Instance
1058 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1059 * @retval None
1060 */
LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)1061 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1062 {
1063 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
1064 }
1065
1066 /**
1067 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
1068 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
1069 * @param DMA2Dx DMA2D Instance
1070 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1071 */
LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef * DMA2Dx)1072 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx)
1073 {
1074 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
1075 }
1076
1077 /**
1078 * @brief Enable DMA2D foreground CLUT loading.
1079 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
1080 * @param DMA2Dx DMA2D Instance
1081 * @retval None
1082 */
LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)1083 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1084 {
1085 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
1086 }
1087
1088 /**
1089 * @brief Indicate if DMA2D foreground CLUT loading is enabled.
1090 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
1091 * @param DMA2Dx DMA2D Instance
1092 * @retval State of bit (1 or 0).
1093 */
LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef * DMA2Dx)1094 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx)
1095 {
1096 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
1097 }
1098
1099 /**
1100 * @brief Set DMA2D foreground color mode.
1101 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
1102 * @param DMA2Dx DMA2D Instance
1103 * @param ColorMode This parameter can be one of the following values:
1104 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1105 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1106 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1107 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1108 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1109 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1110 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1111 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1112 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1113 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1114 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1115 * @retval None
1116 */
LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1117 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1118 {
1119 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
1120 }
1121
1122 /**
1123 * @brief Return DMA2D foreground color mode.
1124 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
1125 * @param DMA2Dx DMA2D Instance
1126 * @retval Returned value can be one of the following values:
1127 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1128 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1129 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1130 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1131 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1132 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1133 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1134 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1135 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1136 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1137 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1138 */
LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef * DMA2Dx)1139 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx)
1140 {
1141 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
1142 }
1143
1144 /**
1145 * @brief Set DMA2D foreground alpha mode.
1146 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
1147 * @param DMA2Dx DMA2D Instance
1148 * @param AphaMode This parameter can be one of the following values:
1149 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1150 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1151 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1152 * @retval None
1153 */
LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1154 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1155 {
1156 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
1157 }
1158
1159 /**
1160 * @brief Return DMA2D foreground alpha mode.
1161 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
1162 * @param DMA2Dx DMA2D Instance
1163 * @retval Returned value can be one of the following values:
1164 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1165 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1166 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1167 */
LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef * DMA2Dx)1168 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx)
1169 {
1170 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
1171 }
1172
1173 /**
1174 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1175 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
1176 * @param DMA2Dx DMA2D Instance
1177 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1178 * @retval None
1179 */
LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1180 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1181 {
1182 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
1183 }
1184
1185 /**
1186 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1187 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
1188 * @param DMA2Dx DMA2D Instance
1189 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1190 */
LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef * DMA2Dx)1191 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx)
1192 {
1193 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
1194 }
1195
1196 /**
1197 * @brief Set DMA2D foreground Red Blue swap mode.
1198 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
1199 * @param DMA2Dx DMA2D Instance
1200 * @param RBSwapMode This parameter can be one of the following values:
1201 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1202 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1203 * @retval None
1204 */
LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)1205 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1206 {
1207 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
1208 }
1209
1210 /**
1211 * @brief Return DMA2D foreground Red Blue swap mode.
1212 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
1213 * @param DMA2Dx DMA2D Instance
1214 * @retval Returned value can be one of the following values:
1215 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1216 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1217 */
LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef * DMA2Dx)1218 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx)
1219 {
1220 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
1221 }
1222
1223 /**
1224 * @brief Set DMA2D foreground alpha inversion mode.
1225 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
1226 * @param DMA2Dx DMA2D Instance
1227 * @param AlphaInversionMode This parameter can be one of the following values:
1228 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1229 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1230 * @retval None
1231 */
LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)1232 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1233 {
1234 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
1235 }
1236
1237 /**
1238 * @brief Return DMA2D foreground alpha inversion mode.
1239 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
1240 * @param DMA2Dx DMA2D Instance
1241 * @retval Returned value can be one of the following values:
1242 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1243 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1244 */
LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef * DMA2Dx)1245 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx)
1246 {
1247 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
1248 }
1249
1250 /**
1251 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1252 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
1253 * @param DMA2Dx DMA2D Instance
1254 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1255 * @retval None
1256 */
LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1257 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1258 {
1259 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1260 }
1261
1262 /**
1263 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1264 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
1265 * @param DMA2Dx DMA2D Instance
1266 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
1267 */
LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef * DMA2Dx)1268 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
1269 {
1270 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1271 }
1272
1273 /**
1274 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
1275 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
1276 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
1277 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
1278 * @param DMA2Dx DMA2D Instance
1279 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1280 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1281 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1282 * @retval None
1283 */
LL_DMA2D_FGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1284 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1285 {
1286 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1287 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1288 }
1289
1290 /**
1291 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1292 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
1293 * @param DMA2Dx DMA2D Instance
1294 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1295 * @retval None
1296 */
LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1297 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1298 {
1299 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1300 }
1301
1302 /**
1303 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1304 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
1305 * @param DMA2Dx DMA2D Instance
1306 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1307 */
LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef * DMA2Dx)1308 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx)
1309 {
1310 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1311 }
1312
1313 /**
1314 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1315 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
1316 * @param DMA2Dx DMA2D Instance
1317 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1318 * @retval None
1319 */
LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1320 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1321 {
1322 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1323 }
1324
1325 /**
1326 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1327 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
1328 * @param DMA2Dx DMA2D Instance
1329 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1330 */
LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef * DMA2Dx)1331 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx)
1332 {
1333 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1334 }
1335
1336 /**
1337 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1338 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
1339 * @param DMA2Dx DMA2D Instance
1340 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1341 * @retval None
1342 */
LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1343 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1344 {
1345 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1346 }
1347
1348 /**
1349 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1350 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
1351 * @param DMA2Dx DMA2D Instance
1352 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1353 */
LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef * DMA2Dx)1354 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx)
1355 {
1356 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1357 }
1358
1359 /**
1360 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1361 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
1362 * @param DMA2Dx DMA2D Instance
1363 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1364 * @retval None
1365 */
LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1366 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1367 {
1368 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1369 }
1370
1371 /**
1372 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1373 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
1374 * @param DMA2Dx DMA2D Instance
1375 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1376 */
LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef * DMA2Dx)1377 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx)
1378 {
1379 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1380 }
1381
1382 /**
1383 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1384 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
1385 * @param DMA2Dx DMA2D Instance
1386 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1387 * @retval None
1388 */
LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1389 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1390 {
1391 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1392 }
1393
1394 /**
1395 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1396 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
1397 * @param DMA2Dx DMA2D Instance
1398 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
1399 */
LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef * DMA2Dx)1400 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx)
1401 {
1402 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1403 }
1404
1405 /**
1406 * @brief Set DMA2D foreground CLUT color mode.
1407 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
1408 * @param DMA2Dx DMA2D Instance
1409 * @param CLUTColorMode This parameter can be one of the following values:
1410 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1411 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1412 * @retval None
1413 */
LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1414 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1415 {
1416 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1417 }
1418
1419 /**
1420 * @brief Return DMA2D foreground CLUT color mode.
1421 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
1422 * @param DMA2Dx DMA2D Instance
1423 * @retval Returned value can be one of the following values:
1424 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1425 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1426 */
LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef * DMA2Dx)1427 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx)
1428 {
1429 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1430 }
1431
1432 /**
1433 * @}
1434 */
1435
1436 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
1437 * @{
1438 */
1439
1440 /**
1441 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1442 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
1443 * @param DMA2Dx DMA2D Instance
1444 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1445 * @retval None
1446 */
LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)1447 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1448 {
1449 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1450 }
1451
1452 /**
1453 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1454 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
1455 * @param DMA2Dx DMA2D Instance
1456 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1457 */
LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef * DMA2Dx)1458 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx)
1459 {
1460 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1461 }
1462
1463 /**
1464 * @brief Enable DMA2D background CLUT loading.
1465 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
1466 * @param DMA2Dx DMA2D Instance
1467 * @retval None
1468 */
LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)1469 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1470 {
1471 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1472 }
1473
1474 /**
1475 * @brief Indicate if DMA2D background CLUT loading is enabled.
1476 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
1477 * @param DMA2Dx DMA2D Instance
1478 * @retval State of bit (1 or 0).
1479 */
LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef * DMA2Dx)1480 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx)
1481 {
1482 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1483 }
1484
1485 /**
1486 * @brief Set DMA2D background color mode.
1487 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
1488 * @param DMA2Dx DMA2D Instance
1489 * @param ColorMode This parameter can be one of the following values:
1490 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1491 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1492 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1493 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1494 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1495 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1496 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1497 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1498 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1499 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1500 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1501 * @retval None
1502 */
LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1503 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1504 {
1505 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1506 }
1507
1508 /**
1509 * @brief Return DMA2D background color mode.
1510 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
1511 * @param DMA2Dx DMA2D Instance
1512 * @retval Returned value can be one of the following values:
1513 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1514 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1515 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1516 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1517 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1518 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1519 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1520 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1521 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1522 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1523 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1524 */
LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef * DMA2Dx)1525 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx)
1526 {
1527 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1528 }
1529
1530 /**
1531 * @brief Set DMA2D background alpha mode.
1532 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
1533 * @param DMA2Dx DMA2D Instance
1534 * @param AphaMode This parameter can be one of the following values:
1535 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1536 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1537 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1538 * @retval None
1539 */
LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1540 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1541 {
1542 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1543 }
1544
1545 /**
1546 * @brief Return DMA2D background alpha mode.
1547 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
1548 * @param DMA2Dx DMA2D Instance
1549 * @retval Returned value can be one of the following values:
1550 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1551 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1552 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1553 */
LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef * DMA2Dx)1554 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx)
1555 {
1556 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1557 }
1558
1559 /**
1560 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1561 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
1562 * @param DMA2Dx DMA2D Instance
1563 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1564 * @retval None
1565 */
LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1566 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1567 {
1568 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1569 }
1570
1571 /**
1572 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1573 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
1574 * @param DMA2Dx DMA2D Instance
1575 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1576 */
LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef * DMA2Dx)1577 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx)
1578 {
1579 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1580 }
1581
1582 /**
1583 * @brief Set DMA2D background Red Blue swap mode.
1584 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
1585 * @param DMA2Dx DMA2D Instance
1586 * @param RBSwapMode This parameter can be one of the following values:
1587 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1588 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1589 * @retval None
1590 */
LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)1591 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1592 {
1593 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
1594 }
1595
1596 /**
1597 * @brief Return DMA2D background Red Blue swap mode.
1598 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
1599 * @param DMA2Dx DMA2D Instance
1600 * @retval Returned value can be one of the following values:
1601 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1602 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1603 */
LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef * DMA2Dx)1604 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx)
1605 {
1606 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
1607 }
1608
1609 /**
1610 * @brief Set DMA2D background alpha inversion mode.
1611 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
1612 * @param DMA2Dx DMA2D Instance
1613 * @param AlphaInversionMode This parameter can be one of the following values:
1614 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1615 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1616 * @retval None
1617 */
LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)1618 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1619 {
1620 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
1621 }
1622
1623 /**
1624 * @brief Return DMA2D background alpha inversion mode.
1625 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
1626 * @param DMA2Dx DMA2D Instance
1627 * @retval Returned value can be one of the following values:
1628 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1629 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1630 */
LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef * DMA2Dx)1631 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx)
1632 {
1633 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
1634 }
1635
1636 /**
1637 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1638 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
1639 * @param DMA2Dx DMA2D Instance
1640 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1641 * @retval None
1642 */
LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1643 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1644 {
1645 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1646 }
1647
1648 /**
1649 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1650 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
1651 * @param DMA2Dx DMA2D Instance
1652 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
1653 */
LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef * DMA2Dx)1654 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
1655 {
1656 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1657 }
1658
1659 /**
1660 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
1661 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
1662 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
1663 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
1664 * @param DMA2Dx DMA2D Instance
1665 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1666 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1667 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1668 * @retval None
1669 */
LL_DMA2D_BGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1670 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1671 {
1672 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1673 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1674 }
1675
1676 /**
1677 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1678 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
1679 * @param DMA2Dx DMA2D Instance
1680 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1681 * @retval None
1682 */
LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1683 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1684 {
1685 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1686 }
1687
1688 /**
1689 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1690 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
1691 * @param DMA2Dx DMA2D Instance
1692 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1693 */
LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef * DMA2Dx)1694 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx)
1695 {
1696 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1697 }
1698
1699 /**
1700 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1701 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
1702 * @param DMA2Dx DMA2D Instance
1703 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1704 * @retval None
1705 */
LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1706 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1707 {
1708 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1709 }
1710
1711 /**
1712 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1713 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
1714 * @param DMA2Dx DMA2D Instance
1715 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1716 */
LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef * DMA2Dx)1717 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx)
1718 {
1719 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1720 }
1721
1722 /**
1723 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1724 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
1725 * @param DMA2Dx DMA2D Instance
1726 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1727 * @retval None
1728 */
LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1729 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1730 {
1731 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1732 }
1733
1734 /**
1735 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1736 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
1737 * @param DMA2Dx DMA2D Instance
1738 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1739 */
LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef * DMA2Dx)1740 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx)
1741 {
1742 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1743 }
1744
1745 /**
1746 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1747 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
1748 * @param DMA2Dx DMA2D Instance
1749 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1750 * @retval None
1751 */
LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1752 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1753 {
1754 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1755 }
1756
1757 /**
1758 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1759 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
1760 * @param DMA2Dx DMA2D Instance
1761 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1762 */
LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef * DMA2Dx)1763 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx)
1764 {
1765 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1766 }
1767
1768 /**
1769 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1770 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
1771 * @param DMA2Dx DMA2D Instance
1772 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1773 * @retval None
1774 */
LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1775 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1776 {
1777 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1778 }
1779
1780 /**
1781 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1782 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
1783 * @param DMA2Dx DMA2D Instance
1784 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
1785 */
LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef * DMA2Dx)1786 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx)
1787 {
1788 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1789 }
1790
1791 /**
1792 * @brief Set DMA2D background CLUT color mode.
1793 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
1794 * @param DMA2Dx DMA2D Instance
1795 * @param CLUTColorMode This parameter can be one of the following values:
1796 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1797 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1798 * @retval None
1799 */
LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1800 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1801 {
1802 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1803 }
1804
1805 /**
1806 * @brief Return DMA2D background CLUT color mode.
1807 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
1808 * @param DMA2Dx DMA2D Instance
1809 * @retval Returned value can be one of the following values:
1810 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1811 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1812 */
LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef * DMA2Dx)1813 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx)
1814 {
1815 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1816 }
1817
1818 /**
1819 * @}
1820 */
1821
1822 /**
1823 * @}
1824 */
1825
1826
1827 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
1828 * @{
1829 */
1830
1831 /**
1832 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
1833 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
1834 * @param DMA2Dx DMA2D Instance
1835 * @retval State of bit (1 or 0).
1836 */
LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef * DMA2Dx)1837 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef *DMA2Dx)
1838 {
1839 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1840 }
1841
1842 /**
1843 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
1844 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
1845 * @param DMA2Dx DMA2D Instance
1846 * @retval State of bit (1 or 0).
1847 */
LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef * DMA2Dx)1848 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef *DMA2Dx)
1849 {
1850 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1851 }
1852
1853 /**
1854 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
1855 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
1856 * @param DMA2Dx DMA2D Instance
1857 * @retval State of bit (1 or 0).
1858 */
LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef * DMA2Dx)1859 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef *DMA2Dx)
1860 {
1861 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1862 }
1863
1864 /**
1865 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
1866 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
1867 * @param DMA2Dx DMA2D Instance
1868 * @retval State of bit (1 or 0).
1869 */
LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef * DMA2Dx)1870 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef *DMA2Dx)
1871 {
1872 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1873 }
1874
1875 /**
1876 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
1877 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
1878 * @param DMA2Dx DMA2D Instance
1879 * @retval State of bit (1 or 0).
1880 */
LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef * DMA2Dx)1881 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef *DMA2Dx)
1882 {
1883 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1884 }
1885
1886 /**
1887 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
1888 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
1889 * @param DMA2Dx DMA2D Instance
1890 * @retval State of bit (1 or 0).
1891 */
LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef * DMA2Dx)1892 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef *DMA2Dx)
1893 {
1894 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1895 }
1896
1897 /**
1898 * @brief Clear DMA2D Configuration Error Interrupt Flag
1899 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
1900 * @param DMA2Dx DMA2D Instance
1901 * @retval None
1902 */
LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef * DMA2Dx)1903 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1904 {
1905 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1906 }
1907
1908 /**
1909 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
1910 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
1911 * @param DMA2Dx DMA2D Instance
1912 * @retval None
1913 */
LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef * DMA2Dx)1914 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1915 {
1916 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1917 }
1918
1919 /**
1920 * @brief Clear DMA2D CLUT Access Error Interrupt Flag
1921 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
1922 * @param DMA2Dx DMA2D Instance
1923 * @retval None
1924 */
LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef * DMA2Dx)1925 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1926 {
1927 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1928 }
1929
1930 /**
1931 * @brief Clear DMA2D Transfer Watermark Interrupt Flag
1932 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
1933 * @param DMA2Dx DMA2D Instance
1934 * @retval None
1935 */
LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef * DMA2Dx)1936 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1937 {
1938 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1939 }
1940
1941 /**
1942 * @brief Clear DMA2D Transfer Complete Interrupt Flag
1943 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
1944 * @param DMA2Dx DMA2D Instance
1945 * @retval None
1946 */
LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef * DMA2Dx)1947 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1948 {
1949 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1950 }
1951
1952 /**
1953 * @brief Clear DMA2D Transfer Error Interrupt Flag
1954 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
1955 * @param DMA2Dx DMA2D Instance
1956 * @retval None
1957 */
LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef * DMA2Dx)1958 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1959 {
1960 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1961 }
1962
1963 /**
1964 * @}
1965 */
1966
1967 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
1968 * @{
1969 */
1970
1971 /**
1972 * @brief Enable Configuration Error Interrupt
1973 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
1974 * @param DMA2Dx DMA2D Instance
1975 * @retval None
1976 */
LL_DMA2D_EnableIT_CE(DMA2D_TypeDef * DMA2Dx)1977 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
1978 {
1979 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1980 }
1981
1982 /**
1983 * @brief Enable CLUT Transfer Complete Interrupt
1984 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
1985 * @param DMA2Dx DMA2D Instance
1986 * @retval None
1987 */
LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef * DMA2Dx)1988 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1989 {
1990 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1991 }
1992
1993 /**
1994 * @brief Enable CLUT Access Error Interrupt
1995 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
1996 * @param DMA2Dx DMA2D Instance
1997 * @retval None
1998 */
LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef * DMA2Dx)1999 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2000 {
2001 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2002 }
2003
2004 /**
2005 * @brief Enable Transfer Watermark Interrupt
2006 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
2007 * @param DMA2Dx DMA2D Instance
2008 * @retval None
2009 */
LL_DMA2D_EnableIT_TW(DMA2D_TypeDef * DMA2Dx)2010 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
2011 {
2012 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2013 }
2014
2015 /**
2016 * @brief Enable Transfer Complete Interrupt
2017 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
2018 * @param DMA2Dx DMA2D Instance
2019 * @retval None
2020 */
LL_DMA2D_EnableIT_TC(DMA2D_TypeDef * DMA2Dx)2021 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
2022 {
2023 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2024 }
2025
2026 /**
2027 * @brief Enable Transfer Error Interrupt
2028 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
2029 * @param DMA2Dx DMA2D Instance
2030 * @retval None
2031 */
LL_DMA2D_EnableIT_TE(DMA2D_TypeDef * DMA2Dx)2032 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
2033 {
2034 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2035 }
2036
2037 /**
2038 * @brief Disable Configuration Error Interrupt
2039 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
2040 * @param DMA2Dx DMA2D Instance
2041 * @retval None
2042 */
LL_DMA2D_DisableIT_CE(DMA2D_TypeDef * DMA2Dx)2043 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
2044 {
2045 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
2046 }
2047
2048 /**
2049 * @brief Disable CLUT Transfer Complete Interrupt
2050 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
2051 * @param DMA2Dx DMA2D Instance
2052 * @retval None
2053 */
LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef * DMA2Dx)2054 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
2055 {
2056 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
2057 }
2058
2059 /**
2060 * @brief Disable CLUT Access Error Interrupt
2061 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
2062 * @param DMA2Dx DMA2D Instance
2063 * @retval None
2064 */
LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef * DMA2Dx)2065 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2066 {
2067 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2068 }
2069
2070 /**
2071 * @brief Disable Transfer Watermark Interrupt
2072 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
2073 * @param DMA2Dx DMA2D Instance
2074 * @retval None
2075 */
LL_DMA2D_DisableIT_TW(DMA2D_TypeDef * DMA2Dx)2076 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
2077 {
2078 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2079 }
2080
2081 /**
2082 * @brief Disable Transfer Complete Interrupt
2083 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
2084 * @param DMA2Dx DMA2D Instance
2085 * @retval None
2086 */
LL_DMA2D_DisableIT_TC(DMA2D_TypeDef * DMA2Dx)2087 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
2088 {
2089 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2090 }
2091
2092 /**
2093 * @brief Disable Transfer Error Interrupt
2094 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
2095 * @param DMA2Dx DMA2D Instance
2096 * @retval None
2097 */
LL_DMA2D_DisableIT_TE(DMA2D_TypeDef * DMA2Dx)2098 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
2099 {
2100 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2101 }
2102
2103 /**
2104 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
2105 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
2106 * @param DMA2Dx DMA2D Instance
2107 * @retval State of bit (1 or 0).
2108 */
LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef * DMA2Dx)2109 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef *DMA2Dx)
2110 {
2111 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
2112 }
2113
2114 /**
2115 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
2116 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
2117 * @param DMA2Dx DMA2D Instance
2118 * @retval State of bit (1 or 0).
2119 */
LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef * DMA2Dx)2120 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef *DMA2Dx)
2121 {
2122 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
2123 }
2124
2125 /**
2126 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
2127 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
2128 * @param DMA2Dx DMA2D Instance
2129 * @retval State of bit (1 or 0).
2130 */
LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef * DMA2Dx)2131 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef *DMA2Dx)
2132 {
2133 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
2134 }
2135
2136 /**
2137 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
2138 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
2139 * @param DMA2Dx DMA2D Instance
2140 * @retval State of bit (1 or 0).
2141 */
LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef * DMA2Dx)2142 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef *DMA2Dx)
2143 {
2144 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
2145 }
2146
2147 /**
2148 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
2149 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
2150 * @param DMA2Dx DMA2D Instance
2151 * @retval State of bit (1 or 0).
2152 */
LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef * DMA2Dx)2153 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef *DMA2Dx)
2154 {
2155 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
2156 }
2157
2158 /**
2159 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
2160 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
2161 * @param DMA2Dx DMA2D Instance
2162 * @retval State of bit (1 or 0).
2163 */
LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef * DMA2Dx)2164 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef *DMA2Dx)
2165 {
2166 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
2167 }
2168
2169
2170
2171 /**
2172 * @}
2173 */
2174
2175 #if defined(USE_FULL_LL_DRIVER)
2176 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
2177 * @{
2178 */
2179
2180 ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx);
2181 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2182 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2183 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
2184 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
2185 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
2186 uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2187 uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2188 uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2189 uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2190 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
2191
2192 /**
2193 * @}
2194 */
2195 #endif /* USE_FULL_LL_DRIVER */
2196
2197 /**
2198 * @}
2199 */
2200
2201 /**
2202 * @}
2203 */
2204
2205 #endif /* defined (DMA2D) */
2206
2207 /**
2208 * @}
2209 */
2210
2211 #ifdef __cplusplus
2212 }
2213 #endif
2214
2215 #endif /* STM32L4xx_LL_DMA2D_H */
2216
