1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_dma2d.h
4 * @author MCD Application Team
5 * @brief Header file of DMA2D LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_LL_DMA2D_H
21 #define STM32U5xx_LL_DMA2D_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA2D)
35
36 /** @defgroup DMA2D_LL DMA2D
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 #if defined(USE_FULL_LL_DRIVER)
45 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
46 * @{
47 */
48
49 /**
50 * @}
51 */
52 #endif /*USE_FULL_LL_DRIVER*/
53
54 /* Exported types ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
57 * @{
58 */
59
60 /**
61 * @brief LL DMA2D Init Structure Definition
62 */
63 typedef struct
64 {
65 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
66 - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
67
68 This parameter can be modified afterwards,
69 using unitary function @ref LL_DMA2D_SetMode(). */
70
71 uint32_t ColorMode; /*!< Specifies the color format of the output image.
72 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
73
74 This parameter can be modified afterwards using,
75 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
76
77 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
78 - This parameter must be a number between:
79 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
80 - This parameter must be a number between:
81 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
82 - This parameter must be a number between:
83 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
84 - This parameter must be a number between:
85 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
86 - This parameter must be a number between:
87 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
88
89 This parameter can be modified afterwards,
90 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
91 function @ref LL_DMA2D_ConfigOutputColor(). */
92
93 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
94 - This parameter must be a number between:
95 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
96 - This parameter must be a number between:
97 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
98 - This parameter must be a number between:
99 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
100 - This parameter must be a number between:
101 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
102 - This parameter must be a number between:
103 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
104
105 This parameter can be modified afterwards
106 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
107 function @ref LL_DMA2D_ConfigOutputColor(). */
108
109 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
110 - This parameter must be a number between:
111 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
112 - This parameter must be a number between:
113 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
114 - This parameter must be a number between:
115 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
116 - This parameter must be a number between:
117 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
118 - This parameter must be a number between:
119 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
120
121 This parameter can be modified afterwards
122 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
123 function @ref LL_DMA2D_ConfigOutputColor(). */
124
125 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
126 - This parameter must be a number between:
127 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
128 - This parameter must be a number between:
129 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
130 - This parameter must be a number between:
131 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
132 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
133
134 This parameter can be modified afterwards using,
135 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
136 function @ref LL_DMA2D_ConfigOutputColor(). */
137
138 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
139 - This parameter must be a number between:
140 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
141
142 This parameter can be modified afterwards,
143 using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
144
145 uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image.
146 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
147
148 This parameter can be modified afterwards,
149 using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
150
151 uint32_t LineOffsetMode; /*!< Specifies the output line offset mode.
152 - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
153
154 This parameter can be modified afterwards,
155 using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
156
157 uint32_t LineOffset; /*!< Specifies the output line offset value.
158 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
159
160 This parameter can be modified afterwards,
161 using unitary function @ref LL_DMA2D_SetLineOffset(). */
162
163 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
164 - This parameter must be a number between:
165 Min_Data = 0x0000 and Max_Data = 0xFFFF.
166
167 This parameter can be modified afterwards,
168 using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
169
170 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
171 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
172
173 This parameter can be modified afterwards using,
174 unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
175
176 uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
177 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
178
179 This parameter can be modified afterwards,
180 using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
181
182 uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
183 - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
184
185 This parameter can be modified afterwards,
186 using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
187
188 } LL_DMA2D_InitTypeDef;
189
190 /**
191 * @brief LL DMA2D Layer Configuration Structure Definition
192 */
193 typedef struct
194 {
195 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
196 - This parameter must be a number between:
197 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
198
199 This parameter can be modified afterwards using unitary functions
200 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
201 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
202
203 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
204 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
205
206 This parameter can be modified afterwards using unitary functions
207 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
208 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
209
210 uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
211 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
212
213 This parameter can be modified afterwards using unitary functions
214 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
215 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
216
217 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
218 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
219
220 This parameter can be modified afterwards using unitary functions
221 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
222 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
223
224 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
225 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
226
227 This parameter can be modified afterwards using unitary functions
228 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
229 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
230
231 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
232 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
233
234 This parameter can be modified afterwards using unitary functions
235 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
236 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
237
238 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
239 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
240
241 This parameter can be modified afterwards using unitary functions
242 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
243 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
244
245 uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
246 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
247
248 This parameter can be modified afterwards using unitary functions
249 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
250 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
251
252 uint32_t Green; /*!< Specifies the foreground or background Green color value.
253 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
254
255 This parameter can be modified afterwards using unitary functions
256 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
257 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
258
259 uint32_t Red; /*!< Specifies the foreground or background Red color value.
260 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
261
262 This parameter can be modified afterwards using unitary functions
263 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
264 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
265
266 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
267 - This parameter must be a number between:
268 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
269
270 This parameter can be modified afterwards using unitary functions
271 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
272 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
273
274 uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
275 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
276
277 This parameter can be modified afterwards using unitary functions
278 - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
279 - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
280
281 uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
282 This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
283
284 This parameter can be modified afterwards using unitary functions
285 - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
286 - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
287
288 #if defined(DMA2D_FGPFCCR_CSS)
289 uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
290 This parameter is applicable for foreground layer only.
291 This parameter can be one value of @ref DMA2D_LL_CHROMA_SUB_SAMPLING
292
293 This parameter can be modified afterwards using unitary functions
294 - @ref LL_DMA2D_FGND_SetChrSubSampling() for foreground layer. */
295 #endif /* DMA2D_FGPFCCR_CSS */
296
297 } LL_DMA2D_LayerCfgTypeDef;
298
299 /**
300 * @brief LL DMA2D Output Color Structure Definition
301 */
302 typedef struct
303 {
304 uint32_t ColorMode; /*!< Specifies the color format of the output image.
305 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
306
307 This parameter can be modified afterwards using
308 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
309
310 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
311 - This parameter must be a number between:
312 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
313 - This parameter must be a number between:
314 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
315 - This parameter must be a number between:
316 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
317 - This parameter must be a number between:
318 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
319 - This parameter must be a number between:
320 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
321
322 This parameter can be modified afterwards using,
323 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
324 function @ref LL_DMA2D_ConfigOutputColor(). */
325
326 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
327 - This parameter must be a number between:
328 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
329 - This parameter must be a number between
330 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
331 - This parameter must be a number between:
332 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
333 - This parameter must be a number between:
334 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
335 - This parameter must be a number between:
336 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
337
338 This parameter can be modified afterwards,
339 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
340 function @ref LL_DMA2D_ConfigOutputColor(). */
341
342 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
343 - This parameter must be a number between:
344 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
345 - This parameter must be a number between:
346 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
347 - This parameter must be a number between:
348 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
349 - This parameter must be a number between:
350 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
351 - This parameter must be a number between:
352 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
353
354 This parameter can be modified afterwards,
355 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
356 function @ref LL_DMA2D_ConfigOutputColor(). */
357
358 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
359 - This parameter must be a number between:
360 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
361 - This parameter must be a number between:
362 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
363 - This parameter must be a number between:
364 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
365 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
366
367 This parameter can be modified afterwards,
368 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
369 function @ref LL_DMA2D_ConfigOutputColor(). */
370
371 } LL_DMA2D_ColorTypeDef;
372
373 /**
374 * @}
375 */
376 #endif /* USE_FULL_LL_DRIVER */
377
378 /* Exported constants --------------------------------------------------------*/
379 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
380 * @{
381 */
382
383 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
384 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
385 * @{
386 */
387 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
388 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
389 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
390 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
391 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
392 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
393 /**
394 * @}
395 */
396
397 /** @defgroup DMA2D_LL_EC_IT IT Defines
398 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
399 * @{
400 */
401 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
402 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
403 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
404 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
405 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
406 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
407 /**
408 * @}
409 */
410
411 /** @defgroup DMA2D_LL_EC_MODE Mode
412 * @{
413 */
414 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
415 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
416 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
417 #define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */
418 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */
419 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */
420 /**
421 * @}
422 */
423
424 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
425 * @{
426 */
427 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
428 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
429 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
430 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
431 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
432 /**
433 * @}
434 */
435
436 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
437 * @{
438 */
439 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
440 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
441 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
442 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
443 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
444 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
445 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
446 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
447 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
448 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
449 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
450 #if defined(DMA2D_FGPFCCR_CSS)
451 #define LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< YCbCr */
452 #endif /* DMA2D_FGPFCCR_CSS */
453 /**
454 * @}
455 */
456
457 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
458 * @{
459 */
460 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
461 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
462 programmed alpha value */
463 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
464 programmed alpha value with,
465 original alpha channel value */
466 /**
467 * @}
468 */
469
470 /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode
471 * @{
472 */
473 #define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */
474 #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */
475 /**
476 * @}
477 */
478
479 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
480 * @{
481 */
482 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */
483 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */
484 /**
485 * @}
486 */
487
488 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
489 * @{
490 */
491 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */
492 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */
493 /**
494 * @}
495 */
496
497
498 /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode
499 * @{
500 */
501 #define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */
502 #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */
503 /**
504 * @}
505 */
506
507 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
508 * @{
509 */
510 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
511 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
512 /**
513 * @}
514 */
515
516 #if defined(DMA2D_FGPFCCR_CSS)
517 /** @defgroup DMA2D_LL_CHROMA_SUB_SAMPLING Chroma Sub Sampling
518 * @{
519 */
520 #define LL_DMA2D_CSS_444 0x00000000U /*!< No chroma sub-sampling 4:4:4 */
521 #define LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0 /*!< chroma sub-sampling 4:2:2 */
522 #define LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1 /*!< chroma sub-sampling 4:2:0 */
523 /**
524 * @}
525 */
526 #endif /* DMA2D_FGPFCCR_CSS */
527
528 /**
529 * @}
530 */
531
532 /* Exported macro ------------------------------------------------------------*/
533 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
534 * @{
535 */
536
537 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
538 * @{
539 */
540
541 /**
542 * @brief Write a value in DMA2D register.
543 * @param __INSTANCE__ DMA2D Instance
544 * @param __REG__ Register to be written
545 * @param __VALUE__ Value to be written in the register
546 * @retval None
547 */
548 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
549
550 /**
551 * @brief Read a value in DMA2D register.
552 * @param __INSTANCE__ DMA2D Instance
553 * @param __REG__ Register to be read
554 * @retval Register value
555 */
556 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
557 /**
558 * @}
559 */
560
561 /**
562 * @}
563 */
564
565 /* Exported functions --------------------------------------------------------*/
566 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
567 * @{
568 */
569
570 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
571 * @{
572 */
573
574 /**
575 * @brief Start a DMA2D transfer.
576 * @rmtoll CR START LL_DMA2D_Start
577 * @param DMA2Dx DMA2D Instance
578 * @retval None
579 */
LL_DMA2D_Start(DMA2D_TypeDef * DMA2Dx)580 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
581 {
582 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
583 }
584
585 /**
586 * @brief Indicate if a DMA2D transfer is ongoing.
587 * @rmtoll CR START LL_DMA2D_IsTransferOngoing
588 * @param DMA2Dx DMA2D Instance
589 * @retval State of bit (1 or 0).
590 */
LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef * DMA2Dx)591 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef *DMA2Dx)
592 {
593 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
594 }
595
596 /**
597 * @brief Suspend DMA2D transfer.
598 * @note This API can be used to suspend automatic foreground or background CLUT loading.
599 * @rmtoll CR SUSP LL_DMA2D_Suspend
600 * @param DMA2Dx DMA2D Instance
601 * @retval None
602 */
LL_DMA2D_Suspend(DMA2D_TypeDef * DMA2Dx)603 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
604 {
605 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
606 }
607
608 /**
609 * @brief Resume DMA2D transfer.
610 * @note This API can be used to resume automatic foreground or background CLUT loading.
611 * @rmtoll CR SUSP LL_DMA2D_Resume
612 * @param DMA2Dx DMA2D Instance
613 * @retval None
614 */
LL_DMA2D_Resume(DMA2D_TypeDef * DMA2Dx)615 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
616 {
617 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
618 }
619
620 /**
621 * @brief Indicate if DMA2D transfer is suspended.
622 * @note This API can be used to indicate whether or not automatic foreground or
623 * background CLUT loading is suspended.
624 * @rmtoll CR SUSP LL_DMA2D_IsSuspended
625 * @param DMA2Dx DMA2D Instance
626 * @retval State of bit (1 or 0).
627 */
LL_DMA2D_IsSuspended(const DMA2D_TypeDef * DMA2Dx)628 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(const DMA2D_TypeDef *DMA2Dx)
629 {
630 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
631 }
632
633 /**
634 * @brief Abort DMA2D transfer.
635 * @note This API can be used to abort automatic foreground or background CLUT loading.
636 * @rmtoll CR ABORT LL_DMA2D_Abort
637 * @param DMA2Dx DMA2D Instance
638 * @retval None
639 */
LL_DMA2D_Abort(DMA2D_TypeDef * DMA2Dx)640 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
641 {
642 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
643 }
644
645 /**
646 * @brief Indicate if DMA2D transfer is aborted.
647 * @note This API can be used to indicate whether or not automatic foreground or
648 * background CLUT loading is aborted.
649 * @rmtoll CR ABORT LL_DMA2D_IsAborted
650 * @param DMA2Dx DMA2D Instance
651 * @retval State of bit (1 or 0).
652 */
LL_DMA2D_IsAborted(const DMA2D_TypeDef * DMA2Dx)653 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(const DMA2D_TypeDef *DMA2Dx)
654 {
655 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
656 }
657
658 /**
659 * @brief Set DMA2D mode.
660 * @rmtoll CR MODE LL_DMA2D_SetMode
661 * @param DMA2Dx DMA2D Instance
662 * @param Mode This parameter can be one of the following values:
663 * @arg @ref LL_DMA2D_MODE_M2M
664 * @arg @ref LL_DMA2D_MODE_M2M_PFC
665 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
666 * @arg @ref LL_DMA2D_MODE_R2M
667 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
668 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
669 * @retval None
670 */
LL_DMA2D_SetMode(DMA2D_TypeDef * DMA2Dx,uint32_t Mode)671 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
672 {
673 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
674 }
675
676 /**
677 * @brief Return DMA2D mode
678 * @rmtoll CR MODE LL_DMA2D_GetMode
679 * @param DMA2Dx DMA2D Instance
680 * @retval Returned value can be one of the following values:
681 * @arg @ref LL_DMA2D_MODE_M2M
682 * @arg @ref LL_DMA2D_MODE_M2M_PFC
683 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
684 * @arg @ref LL_DMA2D_MODE_R2M
685 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
686 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
687 */
LL_DMA2D_GetMode(const DMA2D_TypeDef * DMA2Dx)688 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(const DMA2D_TypeDef *DMA2Dx)
689 {
690 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
691 }
692
693 /**
694 * @brief Set DMA2D output color mode.
695 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
696 * @param DMA2Dx DMA2D Instance
697 * @param ColorMode This parameter can be one of the following values:
698 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
699 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
700 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
701 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
702 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
703 * @retval None
704 */
LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)705 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
706 {
707 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
708 }
709
710 /**
711 * @brief Return DMA2D output color mode.
712 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
713 * @param DMA2Dx DMA2D Instance
714 * @retval Returned value can be one of the following values:
715 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
716 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
717 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
718 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
719 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
720 */
LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef * DMA2Dx)721 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef *DMA2Dx)
722 {
723 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
724 }
725
726 /**
727 * @brief Set DMA2D output Red Blue swap mode.
728 * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
729 * @param DMA2Dx DMA2D Instance
730 * @param RBSwapMode This parameter can be one of the following values:
731 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
732 * @arg @ref LL_DMA2D_RB_MODE_SWAP
733 * @retval None
734 */
LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)735 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
736 {
737 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
738 }
739
740 /**
741 * @brief Return DMA2D output Red Blue swap mode.
742 * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
743 * @param DMA2Dx DMA2D Instance
744 * @retval Returned value can be one of the following values:
745 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
746 * @arg @ref LL_DMA2D_RB_MODE_SWAP
747 */
LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef * DMA2Dx)748 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef *DMA2Dx)
749 {
750 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
751 }
752
753 /**
754 * @brief Set DMA2D output alpha inversion mode.
755 * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
756 * @param DMA2Dx DMA2D Instance
757 * @param AlphaInversionMode This parameter can be one of the following values:
758 * @arg @ref LL_DMA2D_ALPHA_REGULAR
759 * @arg @ref LL_DMA2D_ALPHA_INVERTED
760 * @retval None
761 */
LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)762 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
763 {
764 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
765 }
766
767 /**
768 * @brief Return DMA2D output alpha inversion mode.
769 * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
770 * @param DMA2Dx DMA2D Instance
771 * @retval Returned value can be one of the following values:
772 * @arg @ref LL_DMA2D_ALPHA_REGULAR
773 * @arg @ref LL_DMA2D_ALPHA_INVERTED
774 */
LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef * DMA2Dx)775 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef *DMA2Dx)
776 {
777 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
778 }
779
780
781 /**
782 * @brief Set DMA2D output swap mode.
783 * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode
784 * @param DMA2Dx DMA2D Instance
785 * @param OutputSwapMode This parameter can be one of the following values:
786 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
787 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
788 * @retval None
789 */
LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t OutputSwapMode)790 __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
791 {
792 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
793 }
794
795 /**
796 * @brief Return DMA2D output swap mode.
797 * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode
798 * @param DMA2Dx DMA2D Instance
799 * @retval Returned value can be one of the following values:
800 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
801 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
802 */
LL_DMA2D_GetOutputSwapMode(const DMA2D_TypeDef * DMA2Dx)803 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(const DMA2D_TypeDef *DMA2Dx)
804 {
805 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
806 }
807
808 /**
809 * @brief Set DMA2D line offset mode.
810 * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode
811 * @param DMA2Dx DMA2D Instance
812 * @param LineOffsetMode This parameter can be one of the following values:
813 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
814 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
815 * @retval None
816 */
LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffsetMode)817 __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
818 {
819 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
820 }
821
822 /**
823 * @brief Return DMA2D line offset mode.
824 * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode
825 * @param DMA2Dx DMA2D Instance
826 * @retval Returned value can be one of the following values:
827 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
828 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
829 */
LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef * DMA2Dx)830 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef *DMA2Dx)
831 {
832 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
833 }
834
835 /**
836 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
837 * @rmtoll OOR LO LL_DMA2D_SetLineOffset
838 * @param DMA2Dx DMA2D Instance
839 * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF
840 * @retval None
841 */
LL_DMA2D_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)842 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
843 {
844 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
845 }
846
847 /**
848 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
849 * @rmtoll OOR LO LL_DMA2D_GetLineOffset
850 * @param DMA2Dx DMA2D Instance
851 * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF
852 */
LL_DMA2D_GetLineOffset(const DMA2D_TypeDef * DMA2Dx)853 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
854 {
855 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
856 }
857
858 /**
859 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
860 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
861 * @param DMA2Dx DMA2D Instance
862 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
863 * @retval None
864 */
LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfPixelsPerLines)865 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
866 {
867 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
868 }
869
870 /**
871 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
872 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
873 * @param DMA2Dx DMA2D Instance
874 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
875 */
LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef * DMA2Dx)876 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef *DMA2Dx)
877 {
878 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
879 }
880
881 /**
882 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
883 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
884 * @param DMA2Dx DMA2D Instance
885 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
886 * @retval None
887 */
LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef * DMA2Dx,uint32_t NbrOfLines)888 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
889 {
890 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
891 }
892
893 /**
894 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
895 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
896 * @param DMA2Dx DMA2D Instance
897 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
898 */
LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef * DMA2Dx)899 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef *DMA2Dx)
900 {
901 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
902 }
903
904 /**
905 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
906 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
907 * @param DMA2Dx DMA2D Instance
908 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
909 * @retval None
910 */
LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t OutputMemoryAddress)911 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
912 {
913 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
914 }
915
916 /**
917 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
918 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
919 * @param DMA2Dx DMA2D Instance
920 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
921 */
LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef * DMA2Dx)922 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx)
923 {
924 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
925 }
926
927 /**
928 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
929 * @note Output color format depends on output color mode, ARGB8888, RGB888,
930 * RGB565, ARGB1555 or ARGB4444.
931 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
932 * with respect to color mode is not done by the user code.
933 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
934 * OCOLR GREEN LL_DMA2D_SetOutputColor\n
935 * OCOLR RED LL_DMA2D_SetOutputColor\n
936 * OCOLR ALPHA LL_DMA2D_SetOutputColor
937 * @param DMA2Dx DMA2D Instance
938 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
939 * @retval None
940 */
LL_DMA2D_SetOutputColor(DMA2D_TypeDef * DMA2Dx,uint32_t OutputColor)941 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
942 {
943 WRITE_REG(DMA2Dx->OCOLR, OutputColor);
944 }
945
946 /**
947 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
948 * @note Alpha channel and red, green, blue color values must be retrieved from the returned
949 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
950 * as set by @ref LL_DMA2D_SetOutputColorMode.
951 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
952 * OCOLR GREEN LL_DMA2D_GetOutputColor\n
953 * OCOLR RED LL_DMA2D_GetOutputColor\n
954 * OCOLR ALPHA LL_DMA2D_GetOutputColor
955 * @param DMA2Dx DMA2D Instance
956 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
957 */
LL_DMA2D_GetOutputColor(const DMA2D_TypeDef * DMA2Dx)958 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(const DMA2D_TypeDef *DMA2Dx)
959 {
960 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
961 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
962 }
963
964 /**
965 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
966 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
967 * @param DMA2Dx DMA2D Instance
968 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
969 * @retval None
970 */
LL_DMA2D_SetLineWatermark(DMA2D_TypeDef * DMA2Dx,uint32_t LineWatermark)971 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
972 {
973 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
974 }
975
976 /**
977 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
978 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
979 * @param DMA2Dx DMA2D Instance
980 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
981 */
LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef * DMA2Dx)982 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef *DMA2Dx)
983 {
984 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
985 }
986
987 /**
988 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
989 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
990 * @param DMA2Dx DMA2D Instance
991 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
992 * @retval None
993 */
LL_DMA2D_SetDeadTime(DMA2D_TypeDef * DMA2Dx,uint32_t DeadTime)994 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
995 {
996 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
997 }
998
999 /**
1000 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
1001 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
1002 * @param DMA2Dx DMA2D Instance
1003 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
1004 */
LL_DMA2D_GetDeadTime(const DMA2D_TypeDef * DMA2Dx)1005 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(const DMA2D_TypeDef *DMA2Dx)
1006 {
1007 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
1008 }
1009
1010 /**
1011 * @brief Enable DMA2D dead time functionality.
1012 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
1013 * @param DMA2Dx DMA2D Instance
1014 * @retval None
1015 */
LL_DMA2D_EnableDeadTime(DMA2D_TypeDef * DMA2Dx)1016 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
1017 {
1018 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
1019 }
1020
1021 /**
1022 * @brief Disable DMA2D dead time functionality.
1023 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
1024 * @param DMA2Dx DMA2D Instance
1025 * @retval None
1026 */
LL_DMA2D_DisableDeadTime(DMA2D_TypeDef * DMA2Dx)1027 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
1028 {
1029 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
1030 }
1031
1032 /**
1033 * @brief Indicate if DMA2D dead time functionality is enabled.
1034 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
1035 * @param DMA2Dx DMA2D Instance
1036 * @retval State of bit (1 or 0).
1037 */
LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef * DMA2Dx)1038 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef *DMA2Dx)
1039 {
1040 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
1041 }
1042
1043 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
1044 * @{
1045 */
1046
1047 /**
1048 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
1049 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
1050 * @param DMA2Dx DMA2D Instance
1051 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1052 * @retval None
1053 */
LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)1054 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1055 {
1056 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
1057 }
1058
1059 /**
1060 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
1061 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
1062 * @param DMA2Dx DMA2D Instance
1063 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1064 */
LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef * DMA2Dx)1065 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx)
1066 {
1067 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
1068 }
1069
1070 /**
1071 * @brief Enable DMA2D foreground CLUT loading.
1072 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
1073 * @param DMA2Dx DMA2D Instance
1074 * @retval None
1075 */
LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)1076 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1077 {
1078 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
1079 }
1080
1081 /**
1082 * @brief Indicate if DMA2D foreground CLUT loading is enabled.
1083 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
1084 * @param DMA2Dx DMA2D Instance
1085 * @retval State of bit (1 or 0).
1086 */
LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef * DMA2Dx)1087 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx)
1088 {
1089 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
1090 }
1091
1092 /**
1093 * @brief Set DMA2D foreground color mode.
1094 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
1095 * @param DMA2Dx DMA2D Instance
1096 * @param ColorMode This parameter can be one of the following values:
1097 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1098 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1099 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1100 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1101 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1102 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1103 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1104 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1105 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1106 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1107 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1108 * @retval None
1109 */
LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1110 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1111 {
1112 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
1113 }
1114
1115 /**
1116 * @brief Return DMA2D foreground color mode.
1117 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
1118 * @param DMA2Dx DMA2D Instance
1119 * @retval Returned value can be one of the following values:
1120 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1121 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1122 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1123 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1124 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1125 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1126 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1127 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1128 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1129 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1130 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1131 */
LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef * DMA2Dx)1132 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx)
1133 {
1134 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
1135 }
1136
1137 /**
1138 * @brief Set DMA2D foreground alpha mode.
1139 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
1140 * @param DMA2Dx DMA2D Instance
1141 * @param AphaMode This parameter can be one of the following values:
1142 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1143 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1144 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1145 * @retval None
1146 */
LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1147 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1148 {
1149 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
1150 }
1151
1152 /**
1153 * @brief Return DMA2D foreground alpha mode.
1154 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
1155 * @param DMA2Dx DMA2D Instance
1156 * @retval Returned value can be one of the following values:
1157 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1158 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1159 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1160 */
LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef * DMA2Dx)1161 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx)
1162 {
1163 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
1164 }
1165
1166 /**
1167 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1168 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
1169 * @param DMA2Dx DMA2D Instance
1170 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1171 * @retval None
1172 */
LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1173 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1174 {
1175 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
1176 }
1177
1178 /**
1179 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1180 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
1181 * @param DMA2Dx DMA2D Instance
1182 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1183 */
LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef * DMA2Dx)1184 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx)
1185 {
1186 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
1187 }
1188
1189 /**
1190 * @brief Set DMA2D foreground Red Blue swap mode.
1191 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
1192 * @param DMA2Dx DMA2D Instance
1193 * @param RBSwapMode This parameter can be one of the following values:
1194 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1195 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1196 * @retval None
1197 */
LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)1198 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1199 {
1200 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
1201 }
1202
1203 /**
1204 * @brief Return DMA2D foreground Red Blue swap mode.
1205 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
1206 * @param DMA2Dx DMA2D Instance
1207 * @retval Returned value can be one of the following values:
1208 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1209 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1210 */
LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef * DMA2Dx)1211 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx)
1212 {
1213 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
1214 }
1215
1216 /**
1217 * @brief Set DMA2D foreground alpha inversion mode.
1218 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
1219 * @param DMA2Dx DMA2D Instance
1220 * @param AlphaInversionMode This parameter can be one of the following values:
1221 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1222 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1223 * @retval None
1224 */
LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)1225 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1226 {
1227 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
1228 }
1229
1230 /**
1231 * @brief Return DMA2D foreground alpha inversion mode.
1232 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
1233 * @param DMA2Dx DMA2D Instance
1234 * @retval Returned value can be one of the following values:
1235 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1236 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1237 */
LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef * DMA2Dx)1238 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx)
1239 {
1240 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
1241 }
1242
1243 /**
1244 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1245 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
1246 * @param DMA2Dx DMA2D Instance
1247 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1248 * @retval None
1249 */
LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1250 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1251 {
1252 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1253 }
1254
1255 /**
1256 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1257 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
1258 * @param DMA2Dx DMA2D Instance
1259 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
1260 */
LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef * DMA2Dx)1261 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
1262 {
1263 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1264 }
1265
1266 /**
1267 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
1268 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
1269 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
1270 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
1271 * @param DMA2Dx DMA2D Instance
1272 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1273 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1274 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1275 * @retval None
1276 */
LL_DMA2D_FGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1277 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1278 {
1279 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1280 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1281 }
1282
1283 /**
1284 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1285 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
1286 * @param DMA2Dx DMA2D Instance
1287 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1288 * @retval None
1289 */
LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1290 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1291 {
1292 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1293 }
1294
1295 /**
1296 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1297 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
1298 * @param DMA2Dx DMA2D Instance
1299 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1300 */
LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef * DMA2Dx)1301 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx)
1302 {
1303 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1304 }
1305
1306 /**
1307 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1308 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
1309 * @param DMA2Dx DMA2D Instance
1310 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1311 * @retval None
1312 */
LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1313 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1314 {
1315 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1316 }
1317
1318 /**
1319 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1320 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
1321 * @param DMA2Dx DMA2D Instance
1322 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1323 */
LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef * DMA2Dx)1324 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx)
1325 {
1326 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1327 }
1328
1329 /**
1330 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1331 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
1332 * @param DMA2Dx DMA2D Instance
1333 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1334 * @retval None
1335 */
LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1336 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1337 {
1338 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1339 }
1340
1341 /**
1342 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1343 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
1344 * @param DMA2Dx DMA2D Instance
1345 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1346 */
LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef * DMA2Dx)1347 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx)
1348 {
1349 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1350 }
1351
1352 /**
1353 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1354 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
1355 * @param DMA2Dx DMA2D Instance
1356 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1357 * @retval None
1358 */
LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1359 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1360 {
1361 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1362 }
1363
1364 /**
1365 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1366 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
1367 * @param DMA2Dx DMA2D Instance
1368 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1369 */
LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef * DMA2Dx)1370 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx)
1371 {
1372 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1373 }
1374
1375 /**
1376 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1377 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
1378 * @param DMA2Dx DMA2D Instance
1379 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1380 * @retval None
1381 */
LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1382 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1383 {
1384 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1385 }
1386
1387 /**
1388 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1389 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
1390 * @param DMA2Dx DMA2D Instance
1391 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
1392 */
LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef * DMA2Dx)1393 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx)
1394 {
1395 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1396 }
1397
1398 /**
1399 * @brief Set DMA2D foreground CLUT color mode.
1400 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
1401 * @param DMA2Dx DMA2D Instance
1402 * @param CLUTColorMode This parameter can be one of the following values:
1403 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1404 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1405 * @retval None
1406 */
LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1407 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1408 {
1409 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1410 }
1411
1412 /**
1413 * @brief Return DMA2D foreground CLUT color mode.
1414 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
1415 * @param DMA2Dx DMA2D Instance
1416 * @retval Returned value can be one of the following values:
1417 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1418 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1419 */
LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef * DMA2Dx)1420 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx)
1421 {
1422 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1423 }
1424
1425 #if defined(DMA2D_FGPFCCR_CSS)
1426 /**
1427 * @brief Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
1428 * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_SetChrSubSampling
1429 * @param DMA2Dx DMA2D Instance
1430 * @param ChromaSubSampling This parameter can be one of the following values:
1431 * @arg @ref LL_DMA2D_CSS_444
1432 * @arg @ref LL_DMA2D_CSS_422
1433 * @arg @ref LL_DMA2D_CSS_420
1434 * @retval None
1435 */
LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef * DMA2Dx,uint32_t ChromaSubSampling)1436 __STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling)
1437 {
1438 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling);
1439 }
1440
1441 /**
1442 * @brief Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
1443 * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_GetChrSubSampling
1444 * @param DMA2Dx DMA2D Instance
1445 * @retval Returned value can be one of the following values:
1446 * @arg @ref LL_DMA2D_CSS_444
1447 * @arg @ref LL_DMA2D_CSS_422
1448 * @arg @ref LL_DMA2D_CSS_420
1449 */
LL_DMA2D_FGND_GetChrSubSampling(const DMA2D_TypeDef * DMA2Dx)1450 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(const DMA2D_TypeDef *DMA2Dx)
1451 {
1452 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS));
1453 }
1454 #endif /* DMA2D_FGPFCCR_CSS */
1455 /**
1456 * @}
1457 */
1458
1459 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
1460 * @{
1461 */
1462
1463 /**
1464 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1465 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
1466 * @param DMA2Dx DMA2D Instance
1467 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1468 * @retval None
1469 */
LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t MemoryAddress)1470 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1471 {
1472 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1473 }
1474
1475 /**
1476 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1477 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
1478 * @param DMA2Dx DMA2D Instance
1479 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1480 */
LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef * DMA2Dx)1481 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx)
1482 {
1483 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1484 }
1485
1486 /**
1487 * @brief Enable DMA2D background CLUT loading.
1488 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
1489 * @param DMA2Dx DMA2D Instance
1490 * @retval None
1491 */
LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef * DMA2Dx)1492 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1493 {
1494 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1495 }
1496
1497 /**
1498 * @brief Indicate if DMA2D background CLUT loading is enabled.
1499 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
1500 * @param DMA2Dx DMA2D Instance
1501 * @retval State of bit (1 or 0).
1502 */
LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef * DMA2Dx)1503 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx)
1504 {
1505 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1506 }
1507
1508 /**
1509 * @brief Set DMA2D background color mode.
1510 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
1511 * @param DMA2Dx DMA2D Instance
1512 * @param ColorMode This parameter can be one of the following values:
1513 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1514 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1515 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1516 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1517 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1518 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1519 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1520 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1521 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1522 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1523 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1524 * @retval None
1525 */
LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t ColorMode)1526 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1527 {
1528 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1529 }
1530
1531 /**
1532 * @brief Return DMA2D background color mode.
1533 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
1534 * @param DMA2Dx DMA2D Instance
1535 * @retval Returned value can be one of the following values:
1536 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1537 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1538 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1539 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1540 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1541 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1542 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1543 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1544 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1545 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1546 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1547 */
LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef * DMA2Dx)1548 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx)
1549 {
1550 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1551 }
1552
1553 /**
1554 * @brief Set DMA2D background alpha mode.
1555 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
1556 * @param DMA2Dx DMA2D Instance
1557 * @param AphaMode This parameter can be one of the following values:
1558 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1559 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1560 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1561 * @retval None
1562 */
LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef * DMA2Dx,uint32_t AphaMode)1563 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1564 {
1565 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1566 }
1567
1568 /**
1569 * @brief Return DMA2D background alpha mode.
1570 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
1571 * @param DMA2Dx DMA2D Instance
1572 * @retval Returned value can be one of the following values:
1573 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1574 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1575 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1576 */
LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef * DMA2Dx)1577 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx)
1578 {
1579 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1580 }
1581
1582 /**
1583 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1584 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
1585 * @param DMA2Dx DMA2D Instance
1586 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1587 * @retval None
1588 */
LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef * DMA2Dx,uint32_t Alpha)1589 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1590 {
1591 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1592 }
1593
1594 /**
1595 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1596 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
1597 * @param DMA2Dx DMA2D Instance
1598 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1599 */
LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef * DMA2Dx)1600 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx)
1601 {
1602 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1603 }
1604
1605 /**
1606 * @brief Set DMA2D background Red Blue swap mode.
1607 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
1608 * @param DMA2Dx DMA2D Instance
1609 * @param RBSwapMode This parameter can be one of the following values:
1610 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1611 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1612 * @retval None
1613 */
LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef * DMA2Dx,uint32_t RBSwapMode)1614 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1615 {
1616 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
1617 }
1618
1619 /**
1620 * @brief Return DMA2D background Red Blue swap mode.
1621 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
1622 * @param DMA2Dx DMA2D Instance
1623 * @retval Returned value can be one of the following values:
1624 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1625 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1626 */
LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef * DMA2Dx)1627 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx)
1628 {
1629 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
1630 }
1631
1632 /**
1633 * @brief Set DMA2D background alpha inversion mode.
1634 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
1635 * @param DMA2Dx DMA2D Instance
1636 * @param AlphaInversionMode This parameter can be one of the following values:
1637 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1638 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1639 * @retval None
1640 */
LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef * DMA2Dx,uint32_t AlphaInversionMode)1641 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1642 {
1643 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
1644 }
1645
1646 /**
1647 * @brief Return DMA2D background alpha inversion mode.
1648 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
1649 * @param DMA2Dx DMA2D Instance
1650 * @retval Returned value can be one of the following values:
1651 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1652 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1653 */
LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef * DMA2Dx)1654 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx)
1655 {
1656 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
1657 }
1658
1659 /**
1660 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1661 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
1662 * @param DMA2Dx DMA2D Instance
1663 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1664 * @retval None
1665 */
LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef * DMA2Dx,uint32_t LineOffset)1666 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1667 {
1668 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1669 }
1670
1671 /**
1672 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1673 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
1674 * @param DMA2Dx DMA2D Instance
1675 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
1676 */
LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef * DMA2Dx)1677 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
1678 {
1679 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1680 }
1681
1682 /**
1683 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
1684 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
1685 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
1686 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
1687 * @param DMA2Dx DMA2D Instance
1688 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1689 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1690 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1691 * @retval None
1692 */
LL_DMA2D_BGND_SetColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red,uint32_t Green,uint32_t Blue)1693 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1694 {
1695 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1696 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1697 }
1698
1699 /**
1700 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1701 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
1702 * @param DMA2Dx DMA2D Instance
1703 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1704 * @retval None
1705 */
LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef * DMA2Dx,uint32_t Red)1706 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1707 {
1708 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1709 }
1710
1711 /**
1712 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1713 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
1714 * @param DMA2Dx DMA2D Instance
1715 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1716 */
LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef * DMA2Dx)1717 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx)
1718 {
1719 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1720 }
1721
1722 /**
1723 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1724 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
1725 * @param DMA2Dx DMA2D Instance
1726 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1727 * @retval None
1728 */
LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef * DMA2Dx,uint32_t Green)1729 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1730 {
1731 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1732 }
1733
1734 /**
1735 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1736 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
1737 * @param DMA2Dx DMA2D Instance
1738 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1739 */
LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef * DMA2Dx)1740 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx)
1741 {
1742 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1743 }
1744
1745 /**
1746 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1747 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
1748 * @param DMA2Dx DMA2D Instance
1749 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1750 * @retval None
1751 */
LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef * DMA2Dx,uint32_t Blue)1752 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1753 {
1754 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1755 }
1756
1757 /**
1758 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1759 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
1760 * @param DMA2Dx DMA2D Instance
1761 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1762 */
LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef * DMA2Dx)1763 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx)
1764 {
1765 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1766 }
1767
1768 /**
1769 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1770 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
1771 * @param DMA2Dx DMA2D Instance
1772 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1773 * @retval None
1774 */
LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTMemoryAddress)1775 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1776 {
1777 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1778 }
1779
1780 /**
1781 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1782 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
1783 * @param DMA2Dx DMA2D Instance
1784 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1785 */
LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef * DMA2Dx)1786 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx)
1787 {
1788 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1789 }
1790
1791 /**
1792 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1793 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
1794 * @param DMA2Dx DMA2D Instance
1795 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1796 * @retval None
1797 */
LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTSize)1798 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1799 {
1800 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1801 }
1802
1803 /**
1804 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1805 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
1806 * @param DMA2Dx DMA2D Instance
1807 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
1808 */
LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef * DMA2Dx)1809 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx)
1810 {
1811 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1812 }
1813
1814 /**
1815 * @brief Set DMA2D background CLUT color mode.
1816 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
1817 * @param DMA2Dx DMA2D Instance
1818 * @param CLUTColorMode This parameter can be one of the following values:
1819 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1820 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1821 * @retval None
1822 */
LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef * DMA2Dx,uint32_t CLUTColorMode)1823 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1824 {
1825 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1826 }
1827
1828 /**
1829 * @brief Return DMA2D background CLUT color mode.
1830 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
1831 * @param DMA2Dx DMA2D Instance
1832 * @retval Returned value can be one of the following values:
1833 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1834 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1835 */
LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef * DMA2Dx)1836 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx)
1837 {
1838 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1839 }
1840
1841 /**
1842 * @}
1843 */
1844
1845 /**
1846 * @}
1847 */
1848
1849
1850 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
1851 * @{
1852 */
1853
1854 /**
1855 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
1856 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
1857 * @param DMA2Dx DMA2D Instance
1858 * @retval State of bit (1 or 0).
1859 */
LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef * DMA2Dx)1860 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef *DMA2Dx)
1861 {
1862 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1863 }
1864
1865 /**
1866 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
1867 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
1868 * @param DMA2Dx DMA2D Instance
1869 * @retval State of bit (1 or 0).
1870 */
LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef * DMA2Dx)1871 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef *DMA2Dx)
1872 {
1873 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1874 }
1875
1876 /**
1877 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
1878 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
1879 * @param DMA2Dx DMA2D Instance
1880 * @retval State of bit (1 or 0).
1881 */
LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef * DMA2Dx)1882 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef *DMA2Dx)
1883 {
1884 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1885 }
1886
1887 /**
1888 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
1889 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
1890 * @param DMA2Dx DMA2D Instance
1891 * @retval State of bit (1 or 0).
1892 */
LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef * DMA2Dx)1893 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef *DMA2Dx)
1894 {
1895 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1896 }
1897
1898 /**
1899 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
1900 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
1901 * @param DMA2Dx DMA2D Instance
1902 * @retval State of bit (1 or 0).
1903 */
LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef * DMA2Dx)1904 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef *DMA2Dx)
1905 {
1906 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1907 }
1908
1909 /**
1910 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
1911 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
1912 * @param DMA2Dx DMA2D Instance
1913 * @retval State of bit (1 or 0).
1914 */
LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef * DMA2Dx)1915 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef *DMA2Dx)
1916 {
1917 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1918 }
1919
1920 /**
1921 * @brief Clear DMA2D Configuration Error Interrupt Flag
1922 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
1923 * @param DMA2Dx DMA2D Instance
1924 * @retval None
1925 */
LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef * DMA2Dx)1926 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1927 {
1928 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1929 }
1930
1931 /**
1932 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
1933 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
1934 * @param DMA2Dx DMA2D Instance
1935 * @retval None
1936 */
LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef * DMA2Dx)1937 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1938 {
1939 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1940 }
1941
1942 /**
1943 * @brief Clear DMA2D CLUT Access Error Interrupt Flag
1944 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
1945 * @param DMA2Dx DMA2D Instance
1946 * @retval None
1947 */
LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef * DMA2Dx)1948 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1949 {
1950 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1951 }
1952
1953 /**
1954 * @brief Clear DMA2D Transfer Watermark Interrupt Flag
1955 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
1956 * @param DMA2Dx DMA2D Instance
1957 * @retval None
1958 */
LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef * DMA2Dx)1959 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1960 {
1961 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1962 }
1963
1964 /**
1965 * @brief Clear DMA2D Transfer Complete Interrupt Flag
1966 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
1967 * @param DMA2Dx DMA2D Instance
1968 * @retval None
1969 */
LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef * DMA2Dx)1970 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1971 {
1972 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1973 }
1974
1975 /**
1976 * @brief Clear DMA2D Transfer Error Interrupt Flag
1977 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
1978 * @param DMA2Dx DMA2D Instance
1979 * @retval None
1980 */
LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef * DMA2Dx)1981 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1982 {
1983 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1984 }
1985
1986 /**
1987 * @}
1988 */
1989
1990 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
1991 * @{
1992 */
1993
1994 /**
1995 * @brief Enable Configuration Error Interrupt
1996 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
1997 * @param DMA2Dx DMA2D Instance
1998 * @retval None
1999 */
LL_DMA2D_EnableIT_CE(DMA2D_TypeDef * DMA2Dx)2000 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
2001 {
2002 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
2003 }
2004
2005 /**
2006 * @brief Enable CLUT Transfer Complete Interrupt
2007 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
2008 * @param DMA2Dx DMA2D Instance
2009 * @retval None
2010 */
LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef * DMA2Dx)2011 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
2012 {
2013 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
2014 }
2015
2016 /**
2017 * @brief Enable CLUT Access Error Interrupt
2018 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
2019 * @param DMA2Dx DMA2D Instance
2020 * @retval None
2021 */
LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef * DMA2Dx)2022 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2023 {
2024 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2025 }
2026
2027 /**
2028 * @brief Enable Transfer Watermark Interrupt
2029 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
2030 * @param DMA2Dx DMA2D Instance
2031 * @retval None
2032 */
LL_DMA2D_EnableIT_TW(DMA2D_TypeDef * DMA2Dx)2033 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
2034 {
2035 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2036 }
2037
2038 /**
2039 * @brief Enable Transfer Complete Interrupt
2040 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
2041 * @param DMA2Dx DMA2D Instance
2042 * @retval None
2043 */
LL_DMA2D_EnableIT_TC(DMA2D_TypeDef * DMA2Dx)2044 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
2045 {
2046 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2047 }
2048
2049 /**
2050 * @brief Enable Transfer Error Interrupt
2051 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
2052 * @param DMA2Dx DMA2D Instance
2053 * @retval None
2054 */
LL_DMA2D_EnableIT_TE(DMA2D_TypeDef * DMA2Dx)2055 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
2056 {
2057 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2058 }
2059
2060 /**
2061 * @brief Disable Configuration Error Interrupt
2062 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
2063 * @param DMA2Dx DMA2D Instance
2064 * @retval None
2065 */
LL_DMA2D_DisableIT_CE(DMA2D_TypeDef * DMA2Dx)2066 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
2067 {
2068 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
2069 }
2070
2071 /**
2072 * @brief Disable CLUT Transfer Complete Interrupt
2073 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
2074 * @param DMA2Dx DMA2D Instance
2075 * @retval None
2076 */
LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef * DMA2Dx)2077 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
2078 {
2079 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
2080 }
2081
2082 /**
2083 * @brief Disable CLUT Access Error Interrupt
2084 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
2085 * @param DMA2Dx DMA2D Instance
2086 * @retval None
2087 */
LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef * DMA2Dx)2088 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2089 {
2090 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2091 }
2092
2093 /**
2094 * @brief Disable Transfer Watermark Interrupt
2095 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
2096 * @param DMA2Dx DMA2D Instance
2097 * @retval None
2098 */
LL_DMA2D_DisableIT_TW(DMA2D_TypeDef * DMA2Dx)2099 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
2100 {
2101 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2102 }
2103
2104 /**
2105 * @brief Disable Transfer Complete Interrupt
2106 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
2107 * @param DMA2Dx DMA2D Instance
2108 * @retval None
2109 */
LL_DMA2D_DisableIT_TC(DMA2D_TypeDef * DMA2Dx)2110 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
2111 {
2112 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2113 }
2114
2115 /**
2116 * @brief Disable Transfer Error Interrupt
2117 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
2118 * @param DMA2Dx DMA2D Instance
2119 * @retval None
2120 */
LL_DMA2D_DisableIT_TE(DMA2D_TypeDef * DMA2Dx)2121 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
2122 {
2123 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2124 }
2125
2126 /**
2127 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
2128 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
2129 * @param DMA2Dx DMA2D Instance
2130 * @retval State of bit (1 or 0).
2131 */
LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef * DMA2Dx)2132 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef *DMA2Dx)
2133 {
2134 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
2135 }
2136
2137 /**
2138 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
2139 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
2140 * @param DMA2Dx DMA2D Instance
2141 * @retval State of bit (1 or 0).
2142 */
LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef * DMA2Dx)2143 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef *DMA2Dx)
2144 {
2145 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
2146 }
2147
2148 /**
2149 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
2150 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
2151 * @param DMA2Dx DMA2D Instance
2152 * @retval State of bit (1 or 0).
2153 */
LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef * DMA2Dx)2154 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef *DMA2Dx)
2155 {
2156 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
2157 }
2158
2159 /**
2160 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
2161 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
2162 * @param DMA2Dx DMA2D Instance
2163 * @retval State of bit (1 or 0).
2164 */
LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef * DMA2Dx)2165 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef *DMA2Dx)
2166 {
2167 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
2168 }
2169
2170 /**
2171 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
2172 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
2173 * @param DMA2Dx DMA2D Instance
2174 * @retval State of bit (1 or 0).
2175 */
LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef * DMA2Dx)2176 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef *DMA2Dx)
2177 {
2178 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
2179 }
2180
2181 /**
2182 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
2183 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
2184 * @param DMA2Dx DMA2D Instance
2185 * @retval State of bit (1 or 0).
2186 */
LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef * DMA2Dx)2187 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef *DMA2Dx)
2188 {
2189 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
2190 }
2191
2192
2193
2194 /**
2195 * @}
2196 */
2197
2198 #if defined(USE_FULL_LL_DRIVER)
2199 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
2200 * @{
2201 */
2202
2203 ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx);
2204 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2205 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2206 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
2207 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
2208 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
2209 uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2210 uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2211 uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2212 uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2213 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
2214
2215 /**
2216 * @}
2217 */
2218 #endif /* USE_FULL_LL_DRIVER */
2219
2220 /**
2221 * @}
2222 */
2223
2224 /**
2225 * @}
2226 */
2227
2228 #endif /* defined (DMA2D) */
2229
2230 /**
2231 * @}
2232 */
2233
2234 #ifdef __cplusplus
2235 }
2236 #endif
2237
2238 #endif /* STM32U5xx_LL_DMA2D_H */
2239
