1 /**
2   ******************************************************************************
3   * @file    stm32l4xx_hal_dma2d.c
4   * @author  MCD Application Team
5   * @brief   DMA2D HAL module driver.
6   *          This file provides firmware functions to manage the following
7   *          functionalities of the DMA2D peripheral:
8   *           + Initialization and de-initialization functions
9   *           + IO operation functions
10   *           + Peripheral Control functions
11   *           + Peripheral State and Errors functions
12   *
13   ******************************************************************************
14   * @attention
15   *
16   * Copyright (c) 2017 STMicroelectronics.
17   * All rights reserved.
18   *
19   * This software is licensed under terms that can be found in the LICENSE file
20   * in the root directory of this software component.
21   * If no LICENSE file comes with this software, it is provided AS-IS.
22   *
23   ******************************************************************************
24   @verbatim
25   ==============================================================================
26                         ##### How to use this driver #####
27   ==============================================================================
28     [..]
29       (#) Program the required configuration through the following parameters:
30           the transfer mode, the output color mode and the output offset using
31           HAL_DMA2D_Init() function.
32 
33       (#) Program the required configuration through the following parameters:
34           the input color mode, the input color, the input alpha value, the alpha mode,
35           the red/blue swap mode, the inverted alpha mode and the input offset using
36           HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
37 
38      *** Polling mode IO operation ***
39      =================================
40     [..]
41        (#) Configure pdata parameter (explained hereafter), destination and data length
42            and enable the transfer using HAL_DMA2D_Start().
43        (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
44            user can specify the value of timeout according to his end application.
45 
46      *** Interrupt mode IO operation ***
47      ===================================
48      [..]
49        (#) Configure pdata parameter, destination and data length and enable
50            the transfer using HAL_DMA2D_Start_IT().
51        (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
52        (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
53            add his own function by customization of function pointer XferCpltCallback (member
54            of DMA2D handle structure).
55        (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
56            XferErrorCallback.
57 
58          -@-   In Register-to-Memory transfer mode, pdata parameter is the register
59                color, in Memory-to-memory or Memory-to-Memory with pixel format
60                conversion pdata is the source address.
61 
62          -@-   Configure the foreground source address, the background source address,
63                the destination and data length then Enable the transfer using
64                HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
65                in interrupt mode.
66 
67          -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
68                are used if the memory to memory with blending transfer mode is selected.
69 
70       (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
71           mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
72 
73       (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
74 
75       (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
76           consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
77           and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or
78           HAL_DMA2D_DisableDeadTime().
79 
80       (#) The transfer can be suspended, resumed and aborted using the following
81           functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
82 
83       (#) The CLUT loading can be suspended, resumed and aborted using the following
84           functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
85           HAL_DMA2D_CLUTLoading_Abort().
86 
87       (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
88 
89       (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
90 
91      *** DMA2D HAL driver macros list ***
92      =============================================
93      [..]
94        Below the list of most used macros in DMA2D HAL driver :
95 
96       (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
97       (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
98       (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
99       (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
100       (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
101       (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
102 
103      *** Callback registration ***
104      ===================================
105      [..]
106       (#) The compilation define  USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
107           allows the user to configure dynamically the driver callbacks.
108           Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
109 
110       (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
111             (+) XferCpltCallback : callback for transfer complete.
112             (+) XferErrorCallback : callback for transfer error.
113             (+) LineEventCallback : callback for line event.
114             (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
115             (+) MspInitCallback    : DMA2D MspInit.
116             (+) MspDeInitCallback  : DMA2D MspDeInit.
117           This function takes as parameters the HAL peripheral handle, the Callback ID
118           and a pointer to the user callback function.
119 
120       (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
121           weak (surcharged) function.
122           @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
123           and the Callback ID.
124           This function allows to reset following callbacks:
125             (+) XferCpltCallback : callback for transfer complete.
126             (+) XferErrorCallback : callback for transfer error.
127             (+) LineEventCallback : callback for line event.
128             (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
129             (+) MspInitCallback    : DMA2D MspInit.
130             (+) MspDeInitCallback  : DMA2D MspDeInit.
131 
132       (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
133           all callbacks are reset to the corresponding legacy weak (surcharged) functions:
134           examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
135           Exception done for MspInit and MspDeInit callbacks that are respectively
136           reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
137           and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
138           If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
139           keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
140 
141           Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
142           as weak (surcharged) functions. They must be defined by the user to be resorted to.
143 
144           Callbacks can be registered/unregistered in READY state only.
145           Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
146           in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
147           during the Init/DeInit.
148           In that case first register the MspInit/MspDeInit user callbacks
149           using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
150           or @ref HAL_DMA2D_Init function.
151 
152           When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
153           not defined, the callback registering feature is not available
154           and weak (surcharged) callbacks are used.
155 
156      [..]
157       (@) You can refer to the DMA2D HAL driver header file for more useful macros
158 
159   @endverbatim
160   ******************************************************************************
161   */
162 
163 /* Includes ------------------------------------------------------------------*/
164 #include "stm32l4xx_hal.h"
165 
166 #ifdef HAL_DMA2D_MODULE_ENABLED
167 #if defined (DMA2D)
168 
169 /** @addtogroup STM32L4xx_HAL_Driver
170   * @{
171   */
172 
173 /** @defgroup DMA2D  DMA2D
174   * @brief DMA2D HAL module driver
175   * @{
176   */
177 
178 /* Private types -------------------------------------------------------------*/
179 /* Private define ------------------------------------------------------------*/
180 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
181   * @{
182   */
183 
184 /** @defgroup DMA2D_TimeOut DMA2D Time Out
185   * @{
186   */
187 #define DMA2D_TIMEOUT_ABORT           (1000U)  /*!<  1s  */
188 #define DMA2D_TIMEOUT_SUSPEND         (1000U)  /*!<  1s  */
189 /**
190   * @}
191   */
192 
193 /**
194   * @}
195   */
196 
197 /* Private variables ---------------------------------------------------------*/
198 /* Private constants ---------------------------------------------------------*/
199 /* Private macro -------------------------------------------------------------*/
200 /* Private function prototypes -----------------------------------------------*/
201 /** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
202   * @{
203   */
204 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
205                             uint32_t Height);
206 /**
207   * @}
208   */
209 
210 /* Private functions ---------------------------------------------------------*/
211 /* Exported functions --------------------------------------------------------*/
212 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
213   * @{
214   */
215 
216 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
217   *  @brief   Initialization and Configuration functions
218   *
219 @verbatim
220  ===============================================================================
221                 ##### Initialization and Configuration functions #####
222  ===============================================================================
223     [..]  This section provides functions allowing to:
224       (+) Initialize and configure the DMA2D
225       (+) De-initialize the DMA2D
226 
227 @endverbatim
228   * @{
229   */
230 
231 /**
232   * @brief  Initialize the DMA2D according to the specified
233   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
234   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
235   *                 the configuration information for the DMA2D.
236   * @retval HAL status
237   */
HAL_DMA2D_Init(DMA2D_HandleTypeDef * hdma2d)238 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
239 {
240   /* Check the DMA2D peripheral state */
241   if (hdma2d == NULL)
242   {
243     return HAL_ERROR;
244   }
245 
246   /* Check the parameters */
247   assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
248   assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
249   assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
250   assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
251   assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
252   assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
253 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
254   assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode));
255 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
256 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
257   assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap));
258 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
259 
260 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
261   if (hdma2d->State == HAL_DMA2D_STATE_RESET)
262   {
263     /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
264     hdma2d->LineEventCallback       = HAL_DMA2D_LineEventCallback;
265     hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
266     if (hdma2d->MspInitCallback == NULL)
267     {
268       hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
269     }
270 
271     /* Init the low level hardware */
272     hdma2d->MspInitCallback(hdma2d);
273   }
274 #else
275   if (hdma2d->State == HAL_DMA2D_STATE_RESET)
276   {
277     /* Allocate lock resource and initialize it */
278     hdma2d->Lock = HAL_UNLOCKED;
279     /* Init the low level hardware */
280     HAL_DMA2D_MspInit(hdma2d);
281   }
282 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
283 
284   /* Change DMA2D peripheral state */
285   hdma2d->State = HAL_DMA2D_STATE_BUSY;
286 
287   /* DMA2D CR register configuration -------------------------------------------*/
288 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
289   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode);
290 #else
291   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
292 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
293 
294   /* DMA2D OPFCCR register configuration ---------------------------------------*/
295 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
296   MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB,
297              hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
298 #else
299   MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
300 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
301 
302   /* DMA2D OOR register configuration ------------------------------------------*/
303   MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
304   /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
305   MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS),
306              ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | \
307               (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
308 
309 
310   /* Update error code */
311   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
312 
313   /* Initialize the DMA2D state*/
314   hdma2d->State  = HAL_DMA2D_STATE_READY;
315 
316   return HAL_OK;
317 }
318 
319 /**
320   * @brief  Deinitializes the DMA2D peripheral registers to their default reset
321   *         values.
322   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
323   *                 the configuration information for the DMA2D.
324   * @retval None
325   */
326 
HAL_DMA2D_DeInit(DMA2D_HandleTypeDef * hdma2d)327 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
328 {
329 
330   /* Check the DMA2D peripheral state */
331   if (hdma2d == NULL)
332   {
333     return HAL_ERROR;
334   }
335 
336   /* Before aborting any DMA2D transfer or CLUT loading, check
337      first whether or not DMA2D clock is enabled */
338   if (__HAL_RCC_DMA2D_IS_CLK_ENABLED() == 1U)
339   {
340     /* Abort DMA2D transfer if any */
341     if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
342     {
343       if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
344       {
345         /* Issue when aborting DMA2D transfer */
346         return HAL_ERROR;
347       }
348     }
349     else
350     {
351       /* Abort background CLUT loading if any */
352       if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
353       {
354         if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
355         {
356           /* Issue when aborting background CLUT loading */
357           return HAL_ERROR;
358         }
359       }
360       else
361       {
362         /* Abort foreground CLUT loading if any */
363         if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
364         {
365           if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
366           {
367             /* Issue when aborting foreground CLUT loading */
368             return HAL_ERROR;
369           }
370         }
371       }
372     }
373   }
374 
375   /* Reset DMA2D control registers*/
376   hdma2d->Instance->CR       =    0U;
377   hdma2d->Instance->IFCR     = 0x3FU;
378   hdma2d->Instance->FGOR     =    0U;
379   hdma2d->Instance->BGOR     =    0U;
380   hdma2d->Instance->FGPFCCR  =    0U;
381   hdma2d->Instance->BGPFCCR  =    0U;
382   hdma2d->Instance->OPFCCR   =    0U;
383 
384 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
385 
386   if (hdma2d->MspDeInitCallback == NULL)
387   {
388     hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
389   }
390 
391   /* DeInit the low level hardware */
392   hdma2d->MspDeInitCallback(hdma2d);
393 
394 #else
395   /* Carry on with de-initialization of low level hardware */
396   HAL_DMA2D_MspDeInit(hdma2d);
397 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
398 
399   /* Update error code */
400   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
401 
402   /* Initialize the DMA2D state*/
403   hdma2d->State  = HAL_DMA2D_STATE_RESET;
404 
405   /* Release Lock */
406   __HAL_UNLOCK(hdma2d);
407 
408   return HAL_OK;
409 }
410 
411 /**
412   * @brief  Initializes the DMA2D MSP.
413   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
414   *                 the configuration information for the DMA2D.
415   * @retval None
416   */
HAL_DMA2D_MspInit(DMA2D_HandleTypeDef * hdma2d)417 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d)
418 {
419   /* Prevent unused argument(s) compilation warning */
420   UNUSED(hdma2d);
421 
422   /* NOTE : This function should not be modified; when the callback is needed,
423             the HAL_DMA2D_MspInit can be implemented in the user file.
424    */
425 }
426 
427 /**
428   * @brief  DeInitializes the DMA2D MSP.
429   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
430   *                 the configuration information for the DMA2D.
431   * @retval None
432   */
HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef * hdma2d)433 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
434 {
435   /* Prevent unused argument(s) compilation warning */
436   UNUSED(hdma2d);
437 
438   /* NOTE : This function should not be modified; when the callback is needed,
439             the HAL_DMA2D_MspDeInit can be implemented in the user file.
440    */
441 }
442 
443 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
444 /**
445   * @brief  Register a User DMA2D Callback
446   *         To be used instead of the weak (surcharged) predefined callback
447   * @param hdma2d DMA2D handle
448   * @param CallbackID ID of the callback to be registered
449   *        This parameter can be one of the following values:
450   *          @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
451   *          @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
452   *          @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
453   *          @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
454   *          @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
455   *          @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
456   * @param pCallback pointer to the Callback function
457   * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
458   * @retval status
459   */
HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef * hdma2d,HAL_DMA2D_CallbackIDTypeDef CallbackID,pDMA2D_CallbackTypeDef pCallback)460 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
461                                              pDMA2D_CallbackTypeDef pCallback)
462 {
463   HAL_StatusTypeDef status = HAL_OK;
464 
465   if (pCallback == NULL)
466   {
467     /* Update the error code */
468     hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
469     return HAL_ERROR;
470   }
471   /* Process locked */
472   __HAL_LOCK(hdma2d);
473 
474   if (HAL_DMA2D_STATE_READY == hdma2d->State)
475   {
476     switch (CallbackID)
477     {
478       case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
479         hdma2d->XferCpltCallback = pCallback;
480         break;
481 
482       case HAL_DMA2D_TRANSFERERROR_CB_ID :
483         hdma2d->XferErrorCallback = pCallback;
484         break;
485 
486       case HAL_DMA2D_LINEEVENT_CB_ID :
487         hdma2d->LineEventCallback = pCallback;
488         break;
489 
490       case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
491         hdma2d->CLUTLoadingCpltCallback = pCallback;
492         break;
493 
494       case HAL_DMA2D_MSPINIT_CB_ID :
495         hdma2d->MspInitCallback = pCallback;
496         break;
497 
498       case HAL_DMA2D_MSPDEINIT_CB_ID :
499         hdma2d->MspDeInitCallback = pCallback;
500         break;
501 
502       default :
503         /* Update the error code */
504         hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
505         /* update return status */
506         status =  HAL_ERROR;
507         break;
508     }
509   }
510   else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
511   {
512     switch (CallbackID)
513     {
514       case HAL_DMA2D_MSPINIT_CB_ID :
515         hdma2d->MspInitCallback = pCallback;
516         break;
517 
518       case HAL_DMA2D_MSPDEINIT_CB_ID :
519         hdma2d->MspDeInitCallback = pCallback;
520         break;
521 
522       default :
523         /* Update the error code */
524         hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
525         /* update return status */
526         status =  HAL_ERROR;
527         break;
528     }
529   }
530   else
531   {
532     /* Update the error code */
533     hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
534     /* update return status */
535     status =  HAL_ERROR;
536   }
537 
538   /* Release Lock */
539   __HAL_UNLOCK(hdma2d);
540   return status;
541 }
542 
543 /**
544   * @brief  Unregister a DMA2D Callback
545   *         DMA2D Callback is redirected to the weak (surcharged) predefined callback
546   * @param hdma2d DMA2D handle
547   * @param CallbackID ID of the callback to be unregistered
548   *        This parameter can be one of the following values:
549   *          @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
550   *          @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
551   *          @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
552   *          @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
553   *          @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
554   *          @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
555   * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
556   * @retval status
557   */
HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef * hdma2d,HAL_DMA2D_CallbackIDTypeDef CallbackID)558 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
559 {
560   HAL_StatusTypeDef status = HAL_OK;
561 
562   /* Process locked */
563   __HAL_LOCK(hdma2d);
564 
565   if (HAL_DMA2D_STATE_READY == hdma2d->State)
566   {
567     switch (CallbackID)
568     {
569       case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
570         hdma2d->XferCpltCallback = NULL;
571         break;
572 
573       case HAL_DMA2D_TRANSFERERROR_CB_ID :
574         hdma2d->XferErrorCallback = NULL;
575         break;
576 
577       case HAL_DMA2D_LINEEVENT_CB_ID :
578         hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
579         break;
580 
581       case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
582         hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
583         break;
584 
585       case HAL_DMA2D_MSPINIT_CB_ID :
586         hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
587         break;
588 
589       case HAL_DMA2D_MSPDEINIT_CB_ID :
590         hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
591         break;
592 
593       default :
594         /* Update the error code */
595         hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
596         /* update return status */
597         status =  HAL_ERROR;
598         break;
599     }
600   }
601   else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
602   {
603     switch (CallbackID)
604     {
605       case HAL_DMA2D_MSPINIT_CB_ID :
606         hdma2d->MspInitCallback = HAL_DMA2D_MspInit;   /* Legacy weak (surcharged) Msp Init */
607         break;
608 
609       case HAL_DMA2D_MSPDEINIT_CB_ID :
610         hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;  /* Legacy weak (surcharged) Msp DeInit */
611         break;
612 
613       default :
614         /* Update the error code */
615         hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
616         /* update return status */
617         status =  HAL_ERROR;
618         break;
619     }
620   }
621   else
622   {
623     /* Update the error code */
624     hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
625     /* update return status */
626     status =  HAL_ERROR;
627   }
628 
629   /* Release Lock */
630   __HAL_UNLOCK(hdma2d);
631   return status;
632 }
633 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
634 
635 /**
636   * @}
637   */
638 
639 
640 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
641   *  @brief   IO operation functions
642   *
643 @verbatim
644  ===============================================================================
645                       #####  IO operation functions  #####
646  ===============================================================================
647     [..]  This section provides functions allowing to:
648       (+) Configure the pdata, destination address and data size then
649           start the DMA2D transfer.
650       (+) Configure the source for foreground and background, destination address
651           and data size then start a MultiBuffer DMA2D transfer.
652       (+) Configure the pdata, destination address and data size then
653           start the DMA2D transfer with interrupt.
654       (+) Configure the source for foreground and background, destination address
655           and data size then start a MultiBuffer DMA2D transfer with interrupt.
656       (+) Abort DMA2D transfer.
657       (+) Suspend DMA2D transfer.
658       (+) Resume DMA2D transfer.
659       (+) Enable CLUT transfer.
660       (+) Configure CLUT loading then start transfer in polling mode.
661       (+) Configure CLUT loading then start transfer in interrupt mode.
662       (+) Abort DMA2D CLUT loading.
663       (+) Suspend DMA2D CLUT loading.
664       (+) Resume DMA2D CLUT loading.
665       (+) Poll for transfer complete.
666       (+) handle DMA2D interrupt request.
667       (+) Transfer watermark callback.
668       (+) CLUT Transfer Complete callback.
669 
670 
671 @endverbatim
672   * @{
673   */
674 
675 /**
676   * @brief  Start the DMA2D Transfer.
677   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
678   *                     the configuration information for the DMA2D.
679   * @param  pdata      Configure the source memory Buffer address if
680   *                     Memory-to-Memory or Memory-to-Memory with pixel format
681   *                     conversion mode is selected, or configure
682   *                     the color value if Register-to-Memory mode is selected.
683   * @param  DstAddress The destination memory Buffer address.
684   * @param  Width      The width of data to be transferred from source
685   *                    to destination (expressed in number of pixels per line).
686   * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).
687   * @retval HAL status
688   */
HAL_DMA2D_Start(DMA2D_HandleTypeDef * hdma2d,uint32_t pdata,uint32_t DstAddress,uint32_t Width,uint32_t Height)689 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
690                                   uint32_t Height)
691 {
692   /* Check the parameters */
693   assert_param(IS_DMA2D_LINE(Height));
694   assert_param(IS_DMA2D_PIXEL(Width));
695 
696   /* Process locked */
697   __HAL_LOCK(hdma2d);
698 
699   /* Change DMA2D peripheral state */
700   hdma2d->State = HAL_DMA2D_STATE_BUSY;
701 
702   /* Configure the source, destination address and the data size */
703   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
704 
705   /* Enable the Peripheral */
706   __HAL_DMA2D_ENABLE(hdma2d);
707 
708   return HAL_OK;
709 }
710 
711 /**
712   * @brief  Start the DMA2D Transfer with interrupt enabled.
713   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
714   *                     the configuration information for the DMA2D.
715   * @param  pdata      Configure the source memory Buffer address if
716   *                     the Memory-to-Memory or Memory-to-Memory with pixel format
717   *                     conversion mode is selected, or configure
718   *                     the color value if Register-to-Memory mode is selected.
719   * @param  DstAddress The destination memory Buffer address.
720   * @param  Width      The width of data to be transferred from source
721   *                    to destination (expressed in number of pixels per line).
722   * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).
723   * @retval HAL status
724   */
HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef * hdma2d,uint32_t pdata,uint32_t DstAddress,uint32_t Width,uint32_t Height)725 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
726                                      uint32_t Height)
727 {
728   /* Check the parameters */
729   assert_param(IS_DMA2D_LINE(Height));
730   assert_param(IS_DMA2D_PIXEL(Width));
731 
732   /* Process locked */
733   __HAL_LOCK(hdma2d);
734 
735   /* Change DMA2D peripheral state */
736   hdma2d->State = HAL_DMA2D_STATE_BUSY;
737 
738   /* Configure the source, destination address and the data size */
739   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
740 
741   /* Enable the transfer complete, transfer error and configuration error interrupts */
742   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
743 
744   /* Enable the Peripheral */
745   __HAL_DMA2D_ENABLE(hdma2d);
746 
747   return HAL_OK;
748 }
749 
750 /**
751   * @brief  Start the multi-source DMA2D Transfer.
752   * @param  hdma2d      Pointer to a DMA2D_HandleTypeDef structure that contains
753   *                      the configuration information for the DMA2D.
754   * @param  SrcAddress1 The source memory Buffer address for the foreground layer.
755   * @param  SrcAddress2 The source memory Buffer address for the background layer.
756   * @param  DstAddress  The destination memory Buffer address.
757   * @param  Width       The width of data to be transferred from source
758   *                     to destination (expressed in number of pixels per line).
759   * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).
760   * @retval HAL status
761   */
HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef * hdma2d,uint32_t SrcAddress1,uint32_t SrcAddress2,uint32_t DstAddress,uint32_t Width,uint32_t Height)762 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2,
763                                           uint32_t DstAddress, uint32_t Width,  uint32_t Height)
764 {
765   /* Check the parameters */
766   assert_param(IS_DMA2D_LINE(Height));
767   assert_param(IS_DMA2D_PIXEL(Width));
768 
769   /* Process locked */
770   __HAL_LOCK(hdma2d);
771 
772   /* Change DMA2D peripheral state */
773   hdma2d->State = HAL_DMA2D_STATE_BUSY;
774 
775 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
776   if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
777   {
778     /*blending & fixed FG*/
779     WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
780     /* Configure the source, destination address and the data size */
781     DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
782   }
783   else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
784   {
785     /*blending & fixed BG*/
786     WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
787     /* Configure the source, destination address and the data size */
788     DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
789   }
790   else
791   {
792     /* Configure DMA2D Stream source2 address */
793     WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
794 
795     /* Configure the source, destination address and the data size */
796     DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
797   }
798 
799 #else
800   /* Configure DMA2D Stream source2 address */
801   WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
802 
803   /* Configure the source, destination address and the data size */
804   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
805 
806 #endif /*DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT*/
807   /* Enable the Peripheral */
808   __HAL_DMA2D_ENABLE(hdma2d);
809 
810   return HAL_OK;
811 }
812 
813 /**
814   * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.
815   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
816   *                     the configuration information for the DMA2D.
817   * @param  SrcAddress1 The source memory Buffer address for the foreground layer.
818   * @param  SrcAddress2 The source memory Buffer address for the background layer.
819   * @param  DstAddress  The destination memory Buffer address.
820   * @param  Width       The width of data to be transferred from source
821   *                     to destination (expressed in number of pixels per line).
822   * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).
823   * @retval HAL status
824   */
HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef * hdma2d,uint32_t SrcAddress1,uint32_t SrcAddress2,uint32_t DstAddress,uint32_t Width,uint32_t Height)825 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2,
826                                              uint32_t DstAddress, uint32_t Width,  uint32_t Height)
827 {
828   /* Check the parameters */
829   assert_param(IS_DMA2D_LINE(Height));
830   assert_param(IS_DMA2D_PIXEL(Width));
831 
832   /* Process locked */
833   __HAL_LOCK(hdma2d);
834 
835   /* Change DMA2D peripheral state */
836   hdma2d->State = HAL_DMA2D_STATE_BUSY;
837 
838 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
839   if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
840   {
841     /*blending & fixed FG*/
842     WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
843     /* Configure the source, destination address and the data size */
844     DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
845   }
846   else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
847   {
848     /*blending & fixed BG*/
849     WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
850     /* Configure the source, destination address and the data size */
851     DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
852   }
853   else
854   {
855     WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
856 
857     /* Configure the source, destination address and the data size */
858     DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
859   }
860 
861 #else
862   /* Configure DMA2D Stream source2 address */
863   WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
864 
865   /* Configure the source, destination address and the data size */
866   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
867 
868 #endif /*DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT*/
869   /* Enable the transfer complete, transfer error and configuration error interrupts */
870   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
871 
872   /* Enable the Peripheral */
873   __HAL_DMA2D_ENABLE(hdma2d);
874 
875   return HAL_OK;
876 }
877 
878 /**
879   * @brief  Abort the DMA2D Transfer.
880   * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains
881   *                  the configuration information for the DMA2D.
882   * @retval HAL status
883   */
HAL_DMA2D_Abort(DMA2D_HandleTypeDef * hdma2d)884 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
885 {
886   uint32_t tickstart;
887 
888   /* Abort the DMA2D transfer */
889   /* START bit is reset to make sure not to set it again, in the event the HW clears it
890      between the register read and the register write by the CPU (writing 0 has no
891      effect on START bitvalue) */
892   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
893 
894   /* Get tick */
895   tickstart = HAL_GetTick();
896 
897   /* Check if the DMA2D is effectively disabled */
898   while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
899   {
900     if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
901     {
902       /* Update error code */
903       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
904 
905       /* Change the DMA2D state */
906       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
907 
908       /* Process Unlocked */
909       __HAL_UNLOCK(hdma2d);
910 
911       return HAL_TIMEOUT;
912     }
913   }
914 
915   /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
916   __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
917 
918   /* Change the DMA2D state*/
919   hdma2d->State = HAL_DMA2D_STATE_READY;
920 
921   /* Process Unlocked */
922   __HAL_UNLOCK(hdma2d);
923 
924   return HAL_OK;
925 }
926 
927 /**
928   * @brief  Suspend the DMA2D Transfer.
929   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
930   *                 the configuration information for the DMA2D.
931   * @retval HAL status
932   */
HAL_DMA2D_Suspend(DMA2D_HandleTypeDef * hdma2d)933 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
934 {
935   uint32_t tickstart;
936 
937   /* Suspend the DMA2D transfer */
938   /* START bit is reset to make sure not to set it again, in the event the HW clears it
939      between the register read and the register write by the CPU (writing 0 has no
940      effect on START bitvalue). */
941   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
942 
943   /* Get tick */
944   tickstart = HAL_GetTick();
945 
946   /* Check if the DMA2D is effectively suspended */
947   while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
948   {
949     if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
950     {
951       /* Update error code */
952       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
953 
954       /* Change the DMA2D state */
955       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
956 
957       return HAL_TIMEOUT;
958     }
959   }
960 
961   /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
962   if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
963   {
964     hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
965   }
966   else
967   {
968     /* Make sure SUSP bit is cleared since it is meaningless
969        when no transfer is on-going */
970     CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
971   }
972 
973   return HAL_OK;
974 }
975 
976 /**
977   * @brief  Resume the DMA2D Transfer.
978   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
979   *                 the configuration information for the DMA2D.
980   * @retval HAL status
981   */
HAL_DMA2D_Resume(DMA2D_HandleTypeDef * hdma2d)982 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
983 {
984   /* Check the SUSP and START bits */
985   if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
986   {
987     /* Ongoing transfer is suspended: change the DMA2D state before resuming */
988     hdma2d->State = HAL_DMA2D_STATE_BUSY;
989   }
990 
991   /* Resume the DMA2D transfer */
992   /* START bit is reset to make sure not to set it again, in the event the HW clears it
993      between the register read and the register write by the CPU (writing 0 has no
994      effect on START bitvalue). */
995   CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START));
996 
997   return HAL_OK;
998 }
999 
1000 
1001 /**
1002   * @brief  Enable the DMA2D CLUT Transfer.
1003   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
1004   *                   the configuration information for the DMA2D.
1005   * @param  LayerIdx DMA2D Layer index.
1006   *                   This parameter can be one of the following values:
1007   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1008   * @retval HAL status
1009   */
HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1010 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1011 {
1012   /* Check the parameters */
1013   assert_param(IS_DMA2D_LAYER(LayerIdx));
1014 
1015   /* Process locked */
1016   __HAL_LOCK(hdma2d);
1017 
1018   /* Change DMA2D peripheral state */
1019   hdma2d->State = HAL_DMA2D_STATE_BUSY;
1020 
1021   if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1022   {
1023     /* Enable the background CLUT loading */
1024     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1025   }
1026   else
1027   {
1028     /* Enable the foreground CLUT loading */
1029     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1030   }
1031 
1032   return HAL_OK;
1033 }
1034 
1035 /**
1036   * @brief  Start DMA2D CLUT Loading.
1037   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
1038   *                   the configuration information for the DMA2D.
1039   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1040   *                   the configuration information for the color look up table.
1041   * @param  LayerIdx DMA2D Layer index.
1042   *                   This parameter can be one of the following values:
1043   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1044   * @retval HAL status
1045   */
HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef * hdma2d,const DMA2D_CLUTCfgTypeDef * CLUTCfg,uint32_t LayerIdx)1046 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
1047                                           uint32_t LayerIdx)
1048 {
1049   /* Check the parameters */
1050   assert_param(IS_DMA2D_LAYER(LayerIdx));
1051   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
1052   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
1053 
1054   /* Process locked */
1055   __HAL_LOCK(hdma2d);
1056 
1057   /* Change DMA2D peripheral state */
1058   hdma2d->State = HAL_DMA2D_STATE_BUSY;
1059 
1060   /* Configure the CLUT of the background DMA2D layer */
1061   if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1062   {
1063     /* Write background CLUT memory address */
1064     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
1065 
1066     /* Write background CLUT size and CLUT color mode */
1067     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1068                ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1069 
1070     /* Enable the CLUT loading for the background */
1071     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1072   }
1073   /* Configure the CLUT of the foreground DMA2D layer */
1074   else
1075   {
1076     /* Write foreground CLUT memory address */
1077     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
1078 
1079     /* Write foreground CLUT size and CLUT color mode */
1080     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1081                ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1082 
1083     /* Enable the CLUT loading for the foreground */
1084     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1085   }
1086 
1087   return HAL_OK;
1088 }
1089 
1090 /**
1091   * @brief  Start DMA2D CLUT Loading with interrupt enabled.
1092   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
1093   *                   the configuration information for the DMA2D.
1094   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1095   *                   the configuration information for the color look up table.
1096   * @param  LayerIdx DMA2D Layer index.
1097   *                   This parameter can be one of the following values:
1098   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1099   * @retval HAL status
1100   */
HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef * hdma2d,const DMA2D_CLUTCfgTypeDef * CLUTCfg,uint32_t LayerIdx)1101 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
1102                                              uint32_t LayerIdx)
1103 {
1104   /* Check the parameters */
1105   assert_param(IS_DMA2D_LAYER(LayerIdx));
1106   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
1107   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
1108 
1109   /* Process locked */
1110   __HAL_LOCK(hdma2d);
1111 
1112   /* Change DMA2D peripheral state */
1113   hdma2d->State = HAL_DMA2D_STATE_BUSY;
1114 
1115   /* Configure the CLUT of the background DMA2D layer */
1116   if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1117   {
1118     /* Write background CLUT memory address */
1119     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
1120 
1121     /* Write background CLUT size and CLUT color mode */
1122     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1123                ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1124 
1125     /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1126     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1127 
1128     /* Enable the CLUT loading for the background */
1129     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1130   }
1131   /* Configure the CLUT of the foreground DMA2D layer */
1132   else
1133   {
1134     /* Write foreground CLUT memory address */
1135     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
1136 
1137     /* Write foreground CLUT size and CLUT color mode */
1138     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1139                ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1140 
1141     /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1142     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1143 
1144     /* Enable the CLUT loading for the foreground */
1145     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1146   }
1147 
1148   return HAL_OK;
1149 }
1150 
1151 /**
1152   * @brief  Start DMA2D CLUT Loading.
1153   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
1154   *                   the configuration information for the DMA2D.
1155   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1156   *                   the configuration information for the color look up table.
1157   * @param  LayerIdx DMA2D Layer index.
1158   *                   This parameter can be one of the following values:
1159   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1160   * @note API obsolete and maintained for compatibility with legacy. User is
1161   *      invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from
1162   *      code compactness, code size and improved heap usage.
1163   * @retval HAL status
1164   */
HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef CLUTCfg,uint32_t LayerIdx)1165 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1166 {
1167   /* Check the parameters */
1168   assert_param(IS_DMA2D_LAYER(LayerIdx));
1169   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1170   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1171 
1172   /* Process locked */
1173   __HAL_LOCK(hdma2d);
1174 
1175   /* Change DMA2D peripheral state */
1176   hdma2d->State = HAL_DMA2D_STATE_BUSY;
1177 
1178   /* Configure the CLUT of the background DMA2D layer */
1179   if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1180   {
1181     /* Write background CLUT memory address */
1182     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1183 
1184     /* Write background CLUT size and CLUT color mode */
1185     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1186                ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1187 
1188     /* Enable the CLUT loading for the background */
1189     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1190   }
1191   /* Configure the CLUT of the foreground DMA2D layer */
1192   else
1193   {
1194     /* Write foreground CLUT memory address */
1195     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1196 
1197     /* Write foreground CLUT size and CLUT color mode */
1198     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1199                ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1200 
1201     /* Enable the CLUT loading for the foreground */
1202     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1203   }
1204 
1205   return HAL_OK;
1206 }
1207 
1208 /**
1209   * @brief  Start DMA2D CLUT Loading with interrupt enabled.
1210   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
1211   *                   the configuration information for the DMA2D.
1212   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1213   *                   the configuration information for the color look up table.
1214   * @param  LayerIdx DMA2D Layer index.
1215   *                   This parameter can be one of the following values:
1216   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1217   * @note API obsolete and maintained for compatibility with legacy. User is
1218   *      invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit
1219   *      from code compactness, code size and improved heap usage.
1220   * @retval HAL status
1221   */
HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef CLUTCfg,uint32_t LayerIdx)1222 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1223 {
1224   /* Check the parameters */
1225   assert_param(IS_DMA2D_LAYER(LayerIdx));
1226   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1227   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1228 
1229   /* Process locked */
1230   __HAL_LOCK(hdma2d);
1231 
1232   /* Change DMA2D peripheral state */
1233   hdma2d->State = HAL_DMA2D_STATE_BUSY;
1234 
1235   /* Configure the CLUT of the background DMA2D layer */
1236   if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1237   {
1238     /* Write background CLUT memory address */
1239     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1240 
1241     /* Write background CLUT size and CLUT color mode */
1242     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1243                ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1244 
1245     /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1246     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1247 
1248     /* Enable the CLUT loading for the background */
1249     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1250   }
1251   /* Configure the CLUT of the foreground DMA2D layer */
1252   else
1253   {
1254     /* Write foreground CLUT memory address */
1255     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1256 
1257     /* Write foreground CLUT size and CLUT color mode */
1258     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1259                ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1260 
1261     /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1262     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1263 
1264     /* Enable the CLUT loading for the foreground */
1265     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1266   }
1267 
1268   return HAL_OK;
1269 }
1270 
1271 /**
1272   * @brief  Abort the DMA2D CLUT loading.
1273   * @param  hdma2d  Pointer to a DMA2D_HandleTypeDef structure that contains
1274   *                  the configuration information for the DMA2D.
1275   * @param  LayerIdx DMA2D Layer index.
1276   *                   This parameter can be one of the following values:
1277   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1278   * @retval HAL status
1279   */
HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1280 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1281 {
1282   uint32_t tickstart;
1283   const __IO uint32_t *reg =  &(hdma2d->Instance->BGPFCCR);  /* by default, point at background register */
1284 
1285   /* Abort the CLUT loading */
1286   SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
1287 
1288   /* If foreground CLUT loading is considered, update local variables */
1289   if (LayerIdx == DMA2D_FOREGROUND_LAYER)
1290   {
1291     reg  = &(hdma2d->Instance->FGPFCCR);
1292   }
1293 
1294 
1295   /* Get tick */
1296   tickstart = HAL_GetTick();
1297 
1298   /* Check if the CLUT loading is aborted */
1299   while ((*reg & DMA2D_BGPFCCR_START) != 0U)
1300   {
1301     if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
1302     {
1303       /* Update error code */
1304       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1305 
1306       /* Change the DMA2D state */
1307       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1308 
1309       /* Process Unlocked */
1310       __HAL_UNLOCK(hdma2d);
1311 
1312       return HAL_TIMEOUT;
1313     }
1314   }
1315 
1316   /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
1317   __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1318 
1319   /* Change the DMA2D state*/
1320   hdma2d->State = HAL_DMA2D_STATE_READY;
1321 
1322   /* Process Unlocked */
1323   __HAL_UNLOCK(hdma2d);
1324 
1325   return HAL_OK;
1326 }
1327 
1328 /**
1329   * @brief  Suspend the DMA2D CLUT loading.
1330   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1331   *                 the configuration information for the DMA2D.
1332   * @param  LayerIdx DMA2D Layer index.
1333   *                   This parameter can be one of the following values:
1334   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1335   * @retval HAL status
1336   */
HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1337 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1338 {
1339   uint32_t tickstart;
1340   uint32_t loadsuspended;
1341   const __IO uint32_t *reg =  &(hdma2d->Instance->BGPFCCR);  /* by default, point at background register */
1342 
1343   /* Suspend the CLUT loading */
1344   SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1345 
1346   /* If foreground CLUT loading is considered, update local variables */
1347   if (LayerIdx == DMA2D_FOREGROUND_LAYER)
1348   {
1349     reg  = &(hdma2d->Instance->FGPFCCR);
1350   }
1351 
1352   /* Get tick */
1353   tickstart = HAL_GetTick();
1354 
1355   /* Check if the CLUT loading is suspended */
1356   /* 1st condition: Suspend Check */
1357   loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
1358   /* 2nd condition: Not Start Check */
1359   loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
1360   while (loadsuspended == 0UL)
1361   {
1362     if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
1363     {
1364       /* Update error code */
1365       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1366 
1367       /* Change the DMA2D state */
1368       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1369 
1370       return HAL_TIMEOUT;
1371     }
1372     /* 1st condition: Suspend Check */
1373     loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
1374     /* 2nd condition: Not Start Check */
1375     loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
1376   }
1377 
1378   /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
1379   if ((*reg & DMA2D_BGPFCCR_START) != 0U)
1380   {
1381     hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
1382   }
1383   else
1384   {
1385     /* Make sure SUSP bit is cleared since it is meaningless
1386        when no transfer is on-going */
1387     CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1388   }
1389 
1390   return HAL_OK;
1391 }
1392 
1393 /**
1394   * @brief  Resume the DMA2D CLUT loading.
1395   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1396   *                 the configuration information for the DMA2D.
1397   * @param  LayerIdx DMA2D Layer index.
1398   *                   This parameter can be one of the following values:
1399   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1400   * @retval HAL status
1401   */
HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1402 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1403 {
1404   /* Check the SUSP and START bits for background or foreground CLUT loading */
1405   if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1406   {
1407     /* Background CLUT loading suspension check */
1408     if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1409     {
1410       if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
1411       {
1412         /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1413         hdma2d->State = HAL_DMA2D_STATE_BUSY;
1414       }
1415     }
1416   }
1417   else
1418   {
1419     /* Foreground CLUT loading suspension check */
1420     if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1421     {
1422       if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
1423       {
1424         /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1425         hdma2d->State = HAL_DMA2D_STATE_BUSY;
1426       }
1427     }
1428   }
1429 
1430   /* Resume the CLUT loading */
1431   CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1432 
1433   return HAL_OK;
1434 }
1435 
1436 
1437 /**
1438 
1439   * @brief  Polling for transfer complete or CLUT loading.
1440   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1441   *                 the configuration information for the DMA2D.
1442   * @param  Timeout Timeout duration
1443   * @retval HAL status
1444   */
HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef * hdma2d,uint32_t Timeout)1445 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
1446 {
1447   uint32_t tickstart;
1448   uint32_t layer_start;
1449   __IO uint32_t isrflags = 0x0U;
1450 
1451   /* Polling for DMA2D transfer */
1452   if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
1453   {
1454     /* Get tick */
1455     tickstart = HAL_GetTick();
1456 
1457     while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
1458     {
1459       isrflags = READ_REG(hdma2d->Instance->ISR);
1460       if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
1461       {
1462         if ((isrflags & DMA2D_FLAG_CE) != 0U)
1463         {
1464           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1465         }
1466         if ((isrflags & DMA2D_FLAG_TE) != 0U)
1467         {
1468           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1469         }
1470         /* Clear the transfer and configuration error flags */
1471         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1472 
1473         /* Change DMA2D state */
1474         hdma2d->State = HAL_DMA2D_STATE_ERROR;
1475 
1476         /* Process unlocked */
1477         __HAL_UNLOCK(hdma2d);
1478 
1479         return HAL_ERROR;
1480       }
1481       /* Check for the Timeout */
1482       if (Timeout != HAL_MAX_DELAY)
1483       {
1484         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
1485         {
1486           /* Update error code */
1487           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1488 
1489           /* Change the DMA2D state */
1490           hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1491 
1492           /* Process unlocked */
1493           __HAL_UNLOCK(hdma2d);
1494 
1495           return HAL_TIMEOUT;
1496         }
1497       }
1498     }
1499   }
1500   /* Polling for CLUT loading (foreground or background) */
1501   layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
1502   layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
1503   if (layer_start != 0U)
1504   {
1505     /* Get tick */
1506     tickstart = HAL_GetTick();
1507 
1508     while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
1509     {
1510       isrflags = READ_REG(hdma2d->Instance->ISR);
1511       if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
1512       {
1513         if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1514         {
1515           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1516         }
1517         if ((isrflags & DMA2D_FLAG_CE) != 0U)
1518         {
1519           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1520         }
1521         if ((isrflags & DMA2D_FLAG_TE) != 0U)
1522         {
1523           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1524         }
1525         /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
1526         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1527 
1528         /* Change DMA2D state */
1529         hdma2d->State = HAL_DMA2D_STATE_ERROR;
1530 
1531         /* Process unlocked */
1532         __HAL_UNLOCK(hdma2d);
1533 
1534         return HAL_ERROR;
1535       }
1536       /* Check for the Timeout */
1537       if (Timeout != HAL_MAX_DELAY)
1538       {
1539         if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
1540         {
1541           /* Update error code */
1542           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1543 
1544           /* Change the DMA2D state */
1545           hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1546 
1547           /* Process unlocked */
1548           __HAL_UNLOCK(hdma2d);
1549 
1550           return HAL_TIMEOUT;
1551         }
1552       }
1553     }
1554   }
1555 
1556   /* Clear the transfer complete and CLUT loading flags */
1557   __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC);
1558 
1559   /* Change DMA2D state */
1560   hdma2d->State = HAL_DMA2D_STATE_READY;
1561 
1562   /* Process unlocked */
1563   __HAL_UNLOCK(hdma2d);
1564 
1565   return HAL_OK;
1566 }
1567 /**
1568   * @brief  Handle DMA2D interrupt request.
1569   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1570   *                 the configuration information for the DMA2D.
1571   * @retval HAL status
1572   */
HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef * hdma2d)1573 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
1574 {
1575   uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
1576   uint32_t crflags = READ_REG(hdma2d->Instance->CR);
1577 
1578   /* Transfer Error Interrupt management ***************************************/
1579   if ((isrflags & DMA2D_FLAG_TE) != 0U)
1580   {
1581     if ((crflags & DMA2D_IT_TE) != 0U)
1582     {
1583       /* Disable the transfer Error interrupt */
1584       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
1585 
1586       /* Update error code */
1587       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1588 
1589       /* Clear the transfer error flag */
1590       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
1591 
1592       /* Change DMA2D state */
1593       hdma2d->State = HAL_DMA2D_STATE_ERROR;
1594 
1595       /* Process Unlocked */
1596       __HAL_UNLOCK(hdma2d);
1597 
1598       if (hdma2d->XferErrorCallback != NULL)
1599       {
1600         /* Transfer error Callback */
1601         hdma2d->XferErrorCallback(hdma2d);
1602       }
1603     }
1604   }
1605   /* Configuration Error Interrupt management **********************************/
1606   if ((isrflags & DMA2D_FLAG_CE) != 0U)
1607   {
1608     if ((crflags & DMA2D_IT_CE) != 0U)
1609     {
1610       /* Disable the Configuration Error interrupt */
1611       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
1612 
1613       /* Clear the Configuration error flag */
1614       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
1615 
1616       /* Update error code */
1617       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1618 
1619       /* Change DMA2D state */
1620       hdma2d->State = HAL_DMA2D_STATE_ERROR;
1621 
1622       /* Process Unlocked */
1623       __HAL_UNLOCK(hdma2d);
1624 
1625       if (hdma2d->XferErrorCallback != NULL)
1626       {
1627         /* Transfer error Callback */
1628         hdma2d->XferErrorCallback(hdma2d);
1629       }
1630     }
1631   }
1632   /* CLUT access Error Interrupt management ***********************************/
1633   if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1634   {
1635     if ((crflags & DMA2D_IT_CAE) != 0U)
1636     {
1637       /* Disable the CLUT access error interrupt */
1638       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
1639 
1640       /* Clear the CLUT access error flag */
1641       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
1642 
1643       /* Update error code */
1644       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1645 
1646       /* Change DMA2D state */
1647       hdma2d->State = HAL_DMA2D_STATE_ERROR;
1648 
1649       /* Process Unlocked */
1650       __HAL_UNLOCK(hdma2d);
1651 
1652       if (hdma2d->XferErrorCallback != NULL)
1653       {
1654         /* Transfer error Callback */
1655         hdma2d->XferErrorCallback(hdma2d);
1656       }
1657     }
1658   }
1659   /* Transfer watermark Interrupt management **********************************/
1660   if ((isrflags & DMA2D_FLAG_TW) != 0U)
1661   {
1662     if ((crflags & DMA2D_IT_TW) != 0U)
1663     {
1664       /* Disable the transfer watermark interrupt */
1665       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
1666 
1667       /* Clear the transfer watermark flag */
1668       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
1669 
1670       /* Transfer watermark Callback */
1671 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1672       hdma2d->LineEventCallback(hdma2d);
1673 #else
1674       HAL_DMA2D_LineEventCallback(hdma2d);
1675 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1676 
1677     }
1678   }
1679   /* Transfer Complete Interrupt management ************************************/
1680   if ((isrflags & DMA2D_FLAG_TC) != 0U)
1681   {
1682     if ((crflags & DMA2D_IT_TC) != 0U)
1683     {
1684       /* Disable the transfer complete interrupt */
1685       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
1686 
1687       /* Clear the transfer complete flag */
1688       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
1689 
1690       /* Update error code */
1691       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1692 
1693       /* Change DMA2D state */
1694       hdma2d->State = HAL_DMA2D_STATE_READY;
1695 
1696       /* Process Unlocked */
1697       __HAL_UNLOCK(hdma2d);
1698 
1699       if (hdma2d->XferCpltCallback != NULL)
1700       {
1701         /* Transfer complete Callback */
1702         hdma2d->XferCpltCallback(hdma2d);
1703       }
1704     }
1705   }
1706   /* CLUT Transfer Complete Interrupt management ******************************/
1707   if ((isrflags & DMA2D_FLAG_CTC) != 0U)
1708   {
1709     if ((crflags & DMA2D_IT_CTC) != 0U)
1710     {
1711       /* Disable the CLUT transfer complete interrupt */
1712       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
1713 
1714       /* Clear the CLUT transfer complete flag */
1715       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
1716 
1717       /* Update error code */
1718       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1719 
1720       /* Change DMA2D state */
1721       hdma2d->State = HAL_DMA2D_STATE_READY;
1722 
1723       /* Process Unlocked */
1724       __HAL_UNLOCK(hdma2d);
1725 
1726       /* CLUT Transfer complete Callback */
1727 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1728       hdma2d->CLUTLoadingCpltCallback(hdma2d);
1729 #else
1730       HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
1731 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1732     }
1733   }
1734 
1735 }
1736 
1737 /**
1738   * @brief  Transfer watermark callback.
1739   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1740   *                 the configuration information for the DMA2D.
1741   * @retval None
1742   */
HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef * hdma2d)1743 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
1744 {
1745   /* Prevent unused argument(s) compilation warning */
1746   UNUSED(hdma2d);
1747 
1748   /* NOTE : This function should not be modified; when the callback is needed,
1749             the HAL_DMA2D_LineEventCallback can be implemented in the user file.
1750    */
1751 }
1752 
1753 /**
1754   * @brief  CLUT Transfer Complete callback.
1755   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1756   *                 the configuration information for the DMA2D.
1757   * @retval None
1758   */
HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef * hdma2d)1759 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
1760 {
1761   /* Prevent unused argument(s) compilation warning */
1762   UNUSED(hdma2d);
1763 
1764   /* NOTE : This function should not be modified; when the callback is needed,
1765             the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
1766    */
1767 }
1768 
1769 /**
1770   * @}
1771   */
1772 
1773 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
1774   *  @brief    Peripheral Control functions
1775   *
1776 @verbatim
1777  ===============================================================================
1778                     ##### Peripheral Control functions #####
1779  ===============================================================================
1780     [..]  This section provides functions allowing to:
1781       (+) Configure the DMA2D foreground or background layer parameters.
1782       (+) Configure the DMA2D CLUT transfer.
1783       (+) Configure the line watermark
1784       (+) Configure the dead time value.
1785       (+) Enable or disable the dead time value functionality.
1786 
1787 
1788 @endverbatim
1789   * @{
1790   */
1791 
1792 /**
1793   * @brief  Configure the DMA2D Layer according to the specified
1794   *         parameters in the DMA2D_HandleTypeDef.
1795   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1796   *                 the configuration information for the DMA2D.
1797   * @param  LayerIdx DMA2D Layer index.
1798   *                   This parameter can be one of the following values:
1799   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1800   * @retval HAL status
1801   */
HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1802 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1803 {
1804   const DMA2D_LayerCfgTypeDef *pLayerCfg;
1805   uint32_t regMask;
1806   uint32_t regValue;
1807 
1808   /* Check the parameters */
1809   assert_param(IS_DMA2D_LAYER(LayerIdx));
1810   assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
1811   if (hdma2d->Init.Mode != DMA2D_R2M)
1812   {
1813     assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
1814     if (hdma2d->Init.Mode != DMA2D_M2M)
1815     {
1816       assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
1817     }
1818   }
1819   assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
1820   assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
1821 
1822   /* Process locked */
1823   __HAL_LOCK(hdma2d);
1824 
1825   /* Change DMA2D peripheral state */
1826   hdma2d->State = HAL_DMA2D_STATE_BUSY;
1827 
1828   pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
1829 
1830   /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
1831   regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \
1832              (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
1833   regMask  = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
1834 
1835 
1836   if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1837   {
1838     regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
1839   }
1840   else
1841   {
1842     regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
1843   }
1844 
1845   /* Configure the background DMA2D layer */
1846   if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1847   {
1848     /* Write DMA2D BGPFCCR register */
1849     MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
1850 
1851     /* DMA2D BGOR register configuration -------------------------------------*/
1852     WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
1853 
1854     /* DMA2D BGCOLR register configuration -------------------------------------*/
1855     if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1856     {
1857       WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
1858                                                                    DMA2D_BGCOLR_RED));
1859     }
1860   }
1861   /* Configure the foreground DMA2D layer */
1862   else
1863   {
1864 
1865 
1866     /* Write DMA2D FGPFCCR register */
1867     MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
1868 
1869     /* DMA2D FGOR register configuration -------------------------------------*/
1870     WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
1871 
1872     /* DMA2D FGCOLR register configuration -------------------------------------*/
1873     if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1874     {
1875       WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
1876                                                                    DMA2D_FGCOLR_RED));
1877     }
1878   }
1879   /* Initialize the DMA2D state*/
1880   hdma2d->State = HAL_DMA2D_STATE_READY;
1881 
1882   /* Process unlocked */
1883   __HAL_UNLOCK(hdma2d);
1884 
1885   return HAL_OK;
1886 }
1887 
1888 /**
1889   * @brief  Configure the DMA2D CLUT Transfer.
1890   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
1891   *                   the configuration information for the DMA2D.
1892   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1893   *                   the configuration information for the color look up table.
1894   * @param  LayerIdx DMA2D Layer index.
1895   *                   This parameter can be one of the following values:
1896   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1897   * @note API obsolete and maintained for compatibility with legacy. User is invited
1898   *      to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness,
1899   *      code size and improved heap usage.
1900   * @retval HAL status
1901   */
HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef CLUTCfg,uint32_t LayerIdx)1902 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1903 {
1904   /* Check the parameters */
1905   assert_param(IS_DMA2D_LAYER(LayerIdx));
1906   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1907   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1908 
1909   /* Process locked */
1910   __HAL_LOCK(hdma2d);
1911 
1912   /* Change DMA2D peripheral state */
1913   hdma2d->State = HAL_DMA2D_STATE_BUSY;
1914 
1915   /* Configure the CLUT of the background DMA2D layer */
1916   if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1917   {
1918     /* Write background CLUT memory address */
1919     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1920 
1921     /* Write background CLUT size and CLUT color mode */
1922     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1923                ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1924   }
1925   /* Configure the CLUT of the foreground DMA2D layer */
1926   else
1927   {
1928     /* Write foreground CLUT memory address */
1929     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1930 
1931     /* Write foreground CLUT size and CLUT color mode */
1932     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1933                ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1934   }
1935 
1936   /* Set the DMA2D state to Ready*/
1937   hdma2d->State = HAL_DMA2D_STATE_READY;
1938 
1939   /* Process unlocked */
1940   __HAL_UNLOCK(hdma2d);
1941 
1942   return HAL_OK;
1943 }
1944 
1945 
1946 /**
1947   * @brief  Configure the line watermark.
1948   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1949   *                 the configuration information for the DMA2D.
1950   * @param  Line   Line Watermark configuration (maximum 16-bit long value expected).
1951   * @note   HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
1952   * @note   The transfer watermark interrupt is disabled once it has occurred.
1953   * @retval HAL status
1954   */
1955 
HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef * hdma2d,uint32_t Line)1956 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
1957 {
1958   /* Check the parameters */
1959   if (Line > DMA2D_LWR_LW)
1960   {
1961     return HAL_ERROR;
1962   }
1963   else
1964   {
1965     /* Process locked */
1966     __HAL_LOCK(hdma2d);
1967 
1968     /* Change DMA2D peripheral state */
1969     hdma2d->State = HAL_DMA2D_STATE_BUSY;
1970 
1971     /* Sets the Line watermark configuration */
1972     WRITE_REG(hdma2d->Instance->LWR, Line);
1973 
1974     /* Enable the Line interrupt */
1975     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
1976 
1977     /* Initialize the DMA2D state*/
1978     hdma2d->State = HAL_DMA2D_STATE_READY;
1979 
1980     /* Process unlocked */
1981     __HAL_UNLOCK(hdma2d);
1982 
1983     return HAL_OK;
1984   }
1985 }
1986 
1987 /**
1988   * @brief Enable DMA2D dead time feature.
1989   * @param hdma2d DMA2D handle.
1990   * @retval HAL status
1991   */
HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef * hdma2d)1992 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1993 {
1994   /* Process Locked */
1995   __HAL_LOCK(hdma2d);
1996 
1997   hdma2d->State = HAL_DMA2D_STATE_BUSY;
1998 
1999   /* Set DMA2D_AMTCR EN bit */
2000   SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
2001 
2002   hdma2d->State = HAL_DMA2D_STATE_READY;
2003 
2004   /* Process Unlocked */
2005   __HAL_UNLOCK(hdma2d);
2006 
2007   return HAL_OK;
2008 }
2009 
2010 /**
2011   * @brief Disable DMA2D dead time feature.
2012   * @param hdma2d DMA2D handle.
2013   * @retval HAL status
2014   */
HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef * hdma2d)2015 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
2016 {
2017   /* Process Locked */
2018   __HAL_LOCK(hdma2d);
2019 
2020   hdma2d->State = HAL_DMA2D_STATE_BUSY;
2021 
2022   /* Clear DMA2D_AMTCR EN bit */
2023   CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
2024 
2025   hdma2d->State = HAL_DMA2D_STATE_READY;
2026 
2027   /* Process Unlocked */
2028   __HAL_UNLOCK(hdma2d);
2029 
2030   return HAL_OK;
2031 }
2032 
2033 /**
2034   * @brief Configure dead time.
2035   * @note The dead time value represents the guaranteed minimum number of cycles between
2036   *       two consecutive transactions on the AHB bus.
2037   * @param hdma2d DMA2D handle.
2038   * @param DeadTime dead time value.
2039   * @retval HAL status
2040   */
HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef * hdma2d,uint8_t DeadTime)2041 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
2042 {
2043   /* Process Locked */
2044   __HAL_LOCK(hdma2d);
2045 
2046   hdma2d->State = HAL_DMA2D_STATE_BUSY;
2047 
2048   /* Set DMA2D_AMTCR DT field */
2049   MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
2050 
2051   hdma2d->State = HAL_DMA2D_STATE_READY;
2052 
2053   /* Process Unlocked */
2054   __HAL_UNLOCK(hdma2d);
2055 
2056   return HAL_OK;
2057 }
2058 
2059 /**
2060   * @}
2061   */
2062 
2063 
2064 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
2065   *  @brief    Peripheral State functions
2066   *
2067 @verbatim
2068  ===============================================================================
2069                   ##### Peripheral State and Errors functions #####
2070  ===============================================================================
2071     [..]
2072     This subsection provides functions allowing to:
2073       (+) Get the DMA2D state
2074       (+) Get the DMA2D error code
2075 
2076 @endverbatim
2077   * @{
2078   */
2079 
2080 /**
2081   * @brief  Return the DMA2D state
2082   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
2083   *                 the configuration information for the DMA2D.
2084   * @retval HAL state
2085   */
HAL_DMA2D_GetState(const DMA2D_HandleTypeDef * hdma2d)2086 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d)
2087 {
2088   return hdma2d->State;
2089 }
2090 
2091 /**
2092   * @brief  Return the DMA2D error code
2093   * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains
2094   *               the configuration information for DMA2D.
2095   * @retval DMA2D Error Code
2096   */
HAL_DMA2D_GetError(const DMA2D_HandleTypeDef * hdma2d)2097 uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d)
2098 {
2099   return hdma2d->ErrorCode;
2100 }
2101 
2102 /**
2103   * @}
2104   */
2105 
2106 /**
2107   * @}
2108   */
2109 
2110 
2111 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
2112   * @{
2113   */
2114 
2115 /**
2116   * @brief  Set the DMA2D transfer parameters.
2117   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
2118   *                     the configuration information for the specified DMA2D.
2119   * @param  pdata      The source memory Buffer address
2120   * @param  DstAddress The destination memory Buffer address
2121   * @param  Width      The width of data to be transferred from source to destination.
2122   * @param  Height     The height of data to be transferred from source to destination.
2123   * @retval HAL status
2124   */
DMA2D_SetConfig(DMA2D_HandleTypeDef * hdma2d,uint32_t pdata,uint32_t DstAddress,uint32_t Width,uint32_t Height)2125 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
2126                             uint32_t Height)
2127 {
2128   uint32_t tmp;
2129   uint32_t tmp1;
2130   uint32_t tmp2;
2131   uint32_t tmp3;
2132   uint32_t tmp4;
2133 
2134   /* Configure DMA2D data size */
2135   MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos)));
2136 
2137   /* Configure DMA2D destination address */
2138   WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
2139 
2140   /* Register to memory DMA2D mode selected */
2141   if (hdma2d->Init.Mode == DMA2D_R2M)
2142   {
2143     tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
2144     tmp2 = pdata & DMA2D_OCOLR_RED_1;
2145     tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
2146     tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
2147 
2148     /* Prepare the value to be written to the OCOLR register according to the color mode */
2149     if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
2150     {
2151       tmp = (tmp3 | tmp2 | tmp1 | tmp4);
2152     }
2153     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
2154     {
2155       tmp = (tmp3 | tmp2 | tmp4);
2156     }
2157     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
2158     {
2159       tmp2 = (tmp2 >> 19U);
2160       tmp3 = (tmp3 >> 10U);
2161       tmp4 = (tmp4 >> 3U);
2162       tmp  = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
2163     }
2164     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
2165     {
2166       tmp1 = (tmp1 >> 31U);
2167       tmp2 = (tmp2 >> 19U);
2168       tmp3 = (tmp3 >> 11U);
2169       tmp4 = (tmp4 >> 3U);
2170       tmp  = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
2171     }
2172     else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
2173     {
2174       tmp1 = (tmp1 >> 28U);
2175       tmp2 = (tmp2 >> 20U);
2176       tmp3 = (tmp3 >> 12U);
2177       tmp4 = (tmp4 >> 4U);
2178       tmp  = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
2179     }
2180     /* Write to DMA2D OCOLR register */
2181     WRITE_REG(hdma2d->Instance->OCOLR, tmp);
2182   }
2183 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
2184   else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
2185   {
2186     WRITE_REG(hdma2d->Instance->BGMAR, pdata);
2187   }
2188   else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */
2189 #else
2190   else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
2191 #endif /*DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT*/
2192   {
2193     /* Configure DMA2D source address */
2194     WRITE_REG(hdma2d->Instance->FGMAR, pdata);
2195   }
2196 }
2197 
2198 /**
2199   * @}
2200   */
2201 
2202 /**
2203   * @}
2204   */
2205 
2206 /**
2207   * @}
2208   */
2209 #endif /* DMA2D */
2210 #endif /* HAL_DMA2D_MODULE_ENABLED */
2211