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Searched refs:DCACHE_CR_CACHECMD_1 (Results 1 – 21 of 21) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dcache.h51 #define LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR DCACHE_CR_CACHECMD_1
52 …efine LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR (DCACHE_CR_CACHECMD_0|DCACHE_CR_CACHECMD_1)
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dcache.h51 #define LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR DCACHE_CR_CACHECMD_1
52 …efine LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR (DCACHE_CR_CACHECMD_0|DCACHE_CR_CACHECMD_1)
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_dcache.c130 #define DCACHE_COMMAND_INVALIDATE DCACHE_CR_CACHECMD_1
132 #define DCACHE_COMMAND_CLEAN_INVALIDATE (DCACHE_CR_CACHECMD_0|DCACHE_CR_CACHECMD_1)
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dcache.c130 #define DCACHE_COMMAND_INVALIDATE DCACHE_CR_CACHECMD_1
132 #define DCACHE_COMMAND_CLEAN_INVALIDATE (DCACHE_CR_CACHECMD_0|DCACHE_CR_CACHECMD_1)
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h8927 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32h562xx.h9653 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32h533xx.h9336 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32h573xx.h12146 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32h563xx.h11737 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h9632 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32u535xx.h9232 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32u575xx.h10254 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32u585xx.h10703 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32u595xx.h10564 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32u5a5xx.h11013 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32u5f7xx.h12062 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32u599xx.h14283 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32u5g7xx.h12511 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32u5f9xx.h15188 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32u5a9xx.h14732 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro
Dstm32u5g9xx.h15637 #define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200… macro