1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_dcache.h
4 * @author MCD Application Team
5 * @brief Header file of DCACHE LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion ------------------------------------*/
20 #ifndef STM32U5xx_LL_DCACHE_H
21 #define STM32U5xx_LL_DCACHE_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes -----------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DCACHE1) || defined (DCACHE2)
35
36 /** @defgroup DCACHE_LL DCACHE
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup DCACHE_Exported_Constants DCACHE Exported Constants
44 * @{
45 */
46 /** @defgroup DCACHE_Command_Operation Command Operation
47 * @{
48 */
49 #define LL_DCACHE_COMMAND_NO_OPERATION (0x00000000)
50 #define LL_DCACHE_COMMAND_CLEAN_BY_ADDR DCACHE_CR_CACHECMD_0
51 #define LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR DCACHE_CR_CACHECMD_1
52 #define LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR (DCACHE_CR_CACHECMD_0|DCACHE_CR_CACHECMD_1)
53 /**
54 * @}
55 */
56
57 /** @defgroup DCACHE_Read_Burst_Type Remapped Output burst type
58 * @{
59 */
60 #define LL_DCACHE_READ_BURST_WRAP 0U /*!< WRAP */
61 #define LL_DCACHE_READ_BURST_INCR DCACHE_CR_HBURST /*!< INCR */
62 /**
63 * @}
64 */
65
66 /** @defgroup DCACHE_LL_EC_GET_FLAG Get Flags Defines
67 * @brief Flags defines which can be used with LL_DCACHE_ReadReg function
68 * @{
69 */
70 #define LL_DCACHE_SR_ERRF DCACHE_SR_ERRF /*!< Cache error flag */
71 #define LL_DCACHE_SR_BUSYF DCACHE_SR_BUSYF /*!< Busy flag */
72 #define LL_DCACHE_SR_CMDENDF DCACHE_SR_CMDENDF /*!< Command end flag */
73 #define LL_DCACHE_SR_BSYENDF DCACHE_SR_BSYENDF /*!< Full invalidate busy end flag */
74 #define LL_DCACHE_SR_BUSYCMDF DCACHE_SR_BUSYCMDF /*!< Command busy flag */
75 /**
76 * @}
77 */
78
79 /** @defgroup DCACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
80 * @brief Flags defines which can be used with LL_DCACHE_WriteReg function
81 * @{
82 */
83 #define LL_DCACHE_FCR_CERRF DCACHE_FCR_CERRF /*!< Cache error flag */
84 #define LL_DCACHE_FCR_CBSYENDF DCACHE_FCR_CBSYENDF /*!< Full invalidate busy end flag */
85 #define LL_DCACHE_FCR_CCMDENDF DCACHE_FCR_CCMDENDF /*!< Command end flag*/
86 /**
87 * @}
88 */
89
90 /** @defgroup DCACHE_LL_EC_IT IT Defines
91 * @brief IT defines which can be used with LL_DCACHE_ReadReg and LL_DCACHE_WriteReg functions
92 * @{
93 */
94 #define LL_DCACHE_IER_BSYENDIE DCACHE_IER_BSYENDIE /*!< Busy end interrupt */
95 #define LL_DCACHE_IER_ERRIE DCACHE_IER_ERRIE /*!< Cache error interrupt */
96 #define LL_DCACHE_IER_CMDENDIE DCACHE_IER_CMDENDIE /*!< Command end interrupt */
97 /**
98 * @}
99 */
100
101 /** @defgroup DCACHE_Monitor_Type Monitor type
102 * @{
103 */
104 #define LL_DCACHE_MONITOR_READ_HIT DCACHE_CR_RHITMEN /*!< Read Hit monitoring */
105 #define LL_DCACHE_MONITOR_READ_MISS DCACHE_CR_RMISSMEN /*!< Read Miss monitoring */
106 #define LL_DCACHE_MONITOR_WRITE_HIT DCACHE_CR_WHITMEN /*!< Write Hit monitoring */
107 #define LL_DCACHE_MONITOR_WRITE_MISS DCACHE_CR_WMISSMEN /*!< Write Miss monitoring */
108 #define LL_DCACHE_MONITOR_ALL (DCACHE_CR_RHITMEN | DCACHE_CR_RMISSMEN \
109 | DCACHE_CR_WHITMEN | DCACHE_CR_WMISSMEN)
110 /**
111 * @}
112 */
113
114 /**
115 * @}
116 */
117
118 /* Exported macros --------------------------------------------------------*/
119 /** @defgroup DCACHE_LL_Exported_Macros DCACHE Exported Macros
120 * @{
121 */
122
123 /** @defgroup DCACHE_LL_EM_WRITE_READ Common write and read registers Macros
124 * @{
125 */
126
127 /**
128 * @brief Write a value in DCACHE register
129 * @param __INSTANCE__ DCACHE Instance
130 * @param __REG__ Register to be written
131 * @param __VALUE__ Value to be written in the register
132 * @retval None
133 */
134 #define LL_DCACHE_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
135
136 /**
137 * @brief Read a value in DCACHE register
138 * @param __INSTANCE__ DCACHE Instance
139 * @param __REG__ Register to be read
140 * @retval Register value
141 */
142 #define LL_DCACHE_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
143 /**
144 * @}
145 */
146
147 /**
148 * @}
149 */
150
151 /* Exported functions --------------------------------------------------------*/
152 /** @defgroup DCACHE_LL_Exported_Functions DCACHE Exported Functions
153 * @{
154 */
155
156 /** @defgroup DCACHE_LL_EF_Configuration Configuration
157 * @{
158 */
159
160 /**
161 * @brief Enable the selected DCACHE instance.
162 * @rmtoll CR EN LL_DCACHE_Enable
163 * @param DCACHEx DCACHE instance
164 * @retval None
165 */
LL_DCACHE_Enable(DCACHE_TypeDef * DCACHEx)166 __STATIC_INLINE void LL_DCACHE_Enable(DCACHE_TypeDef *DCACHEx)
167 {
168 SET_BIT(DCACHEx->CR, DCACHE_CR_EN);
169 }
170
171 /**
172 * @brief Disable the selected DCACHE instance.
173 * @rmtoll CR EN LL_DCACHE_Disable
174 * @param DCACHEx DCACHE instance
175 * @retval None
176 */
LL_DCACHE_Disable(DCACHE_TypeDef * DCACHEx)177 __STATIC_INLINE void LL_DCACHE_Disable(DCACHE_TypeDef *DCACHEx)
178 {
179 CLEAR_BIT(DCACHEx->CR, DCACHE_CR_EN);
180 }
181
182 /**
183 * @brief Get the selected DCACHE instance enable state.
184 * @rmtoll CR EN LL_DCACHE_IsEnabled
185 * @param DCACHEx DCACHE instance
186 * @retval 0: DCACHE is disabled, 1: DCACHE is enabled.
187 */
LL_DCACHE_IsEnabled(const DCACHE_TypeDef * DCACHEx)188 __STATIC_INLINE uint32_t LL_DCACHE_IsEnabled(const DCACHE_TypeDef *DCACHEx)
189 {
190 return ((READ_BIT(DCACHEx->CR, DCACHE_CR_EN) == (DCACHE_CR_EN)) ? 1UL : 0UL);
191 }
192
193 /**
194 * @brief Set the dcache instance start command address.
195 * @rmtoll CR CMDRSADDRR LL_DCACHE_SetStartAddress
196 * @param addr dcache command start address(Clean, Invalidate or Clean and Invalidate).
197 * @param DCACHEx DCACHE instance
198 * @retval None
199 */
LL_DCACHE_SetStartAddress(DCACHE_TypeDef * DCACHEx,uint32_t addr)200 __STATIC_INLINE void LL_DCACHE_SetStartAddress(DCACHE_TypeDef *DCACHEx, uint32_t addr)
201 {
202 WRITE_REG(DCACHEx->CMDRSADDRR, addr);
203 }
204
205 /**
206 * @brief Get the dcache command start address.
207 * @rmtoll CR CMDRSADDRR LL_DCACHE_GetStartAddress
208 * @param DCACHEx DCACHE instance
209 * @retval Start address of dcache command
210 */
LL_DCACHE_GetStartAddress(const DCACHE_TypeDef * DCACHEx)211 __STATIC_INLINE uint32_t LL_DCACHE_GetStartAddress(const DCACHE_TypeDef *DCACHEx)
212 {
213 return (uint32_t)(READ_REG(DCACHEx->CMDRSADDRR));
214 }
215
216 /**
217 * @brief Set the dcache instance End command address.
218 * @rmtoll CR CMDREADDRR LL_DCACHE_SetEndAddress
219 * @param DCACHEx DCACHE instance
220 * @param addr dcache command end address(Clean, Invalidate or Clean and Invalidate).
221 * @retval None
222 */
LL_DCACHE_SetEndAddress(DCACHE_TypeDef * DCACHEx,uint32_t addr)223 __STATIC_INLINE void LL_DCACHE_SetEndAddress(DCACHE_TypeDef *DCACHEx, uint32_t addr)
224 {
225 WRITE_REG(DCACHEx->CMDREADDRR, addr);
226 }
227
228 /**
229 * @brief Get the dcache command End address.
230 * @rmtoll CR CMDREADDRR LL_DCACHE_GetEndAddress
231 * @param DCACHEx DCACHE instance
232 * @retval End address of dcache command
233 */
LL_DCACHE_GetEndAddress(const DCACHE_TypeDef * DCACHEx)234 __STATIC_INLINE uint32_t LL_DCACHE_GetEndAddress(const DCACHE_TypeDef *DCACHEx)
235 {
236 return (uint32_t)(READ_REG(DCACHEx->CMDREADDRR));
237 }
238
239 /**
240 * @brief Set Dcache command.
241 * @rmtoll CR CACHECMD LL_DCACHE_SetCommand
242 * @param DCACHEx DCACHE instance
243 * @param Command command to be applied for the dcache
244 * Command can be one of the following values:
245 * @arg @ref LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR
246 * @arg @ref LL_DCACHE_COMMAND_CLEAN_BY_ADDR
247 * @arg @ref LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR
248 * @arg @ref LL_DCACHE_COMMAND_NO_OPERATION
249 * @retval None
250 */
LL_DCACHE_SetCommand(DCACHE_TypeDef * DCACHEx,uint32_t Command)251 __STATIC_INLINE void LL_DCACHE_SetCommand(DCACHE_TypeDef *DCACHEx, uint32_t Command)
252 {
253 /* Set dcache command */
254 MODIFY_REG(DCACHEx->CR, DCACHE_CR_CACHECMD, Command);
255 }
256
257 /**
258 * @brief Set Dcache command.
259 * @rmtoll CR CACHECMD LL_DCACHE_GetCommand
260 * @param DCACHEx DCACHE instance
261 * @retval Returned value can be one of the following values:
262 * @arg @ref LL_DCACHE_COMMAND_NO_OPERATION
263 * @arg @ref LL_DCACHE_COMMAND_CLEAN_BY_ADDR
264 * @arg @ref LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR
265 * @arg @ref LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR
266 */
LL_DCACHE_GetCommand(const DCACHE_TypeDef * DCACHEx)267 __STATIC_INLINE uint32_t LL_DCACHE_GetCommand(const DCACHE_TypeDef *DCACHEx)
268 {
269 /*Get Dcache Command */
270 return (uint32_t)(READ_BIT(DCACHEx->CR, DCACHE_CR_CACHECMD));
271 }
272
273 /**
274 * @brief Launch Dcache Command.
275 * @rmtoll CR CACHECMD LL_DCACHE_StartCommand
276 * @param DCACHEx DCACHE instance
277 * @retval None
278 */
LL_DCACHE_StartCommand(DCACHE_TypeDef * DCACHEx)279 __STATIC_INLINE void LL_DCACHE_StartCommand(DCACHE_TypeDef *DCACHEx)
280 {
281 SET_BIT(DCACHEx->CR, DCACHE_CR_STARTCMD);
282 }
283
284 /**
285 * @brief Set requested read burst type.
286 * @rmtoll CR HBURST LL_DCACHE_SetReadBurstType
287 * @param DCACHEx DCACHE instance
288 * @param ReadBurstType Burst type to be applied for Data Cache
289 * Burst type can be one of the following values:
290 * @arg @ref LL_DCACHE_READ_BURST_WRAP
291 * @arg @ref LL_DCACHE_READ_BURST_INCR
292 * @retval None
293 */
LL_DCACHE_SetReadBurstType(DCACHE_TypeDef * DCACHEx,uint32_t ReadBurstType)294 __STATIC_INLINE void LL_DCACHE_SetReadBurstType(DCACHE_TypeDef *DCACHEx, uint32_t ReadBurstType)
295 {
296 MODIFY_REG(DCACHEx->CR, DCACHE_CR_HBURST, ReadBurstType);
297 }
298
299 /**
300 * @brief Get requested read burst type.
301 * @rmtoll CR HBURST LL_DCACHE_GetReadBurstType
302 * @param DCACHEx DCACHE instance
303 * @retval Returned value can be one of the following values:
304 * @arg @ref LL_DCACHE_READ_BURST_WRAP
305 * @arg @ref LL_DCACHE_READ_BURST_INCR
306 */
LL_DCACHE_GetReadBurstType(const DCACHE_TypeDef * DCACHEx)307 __STATIC_INLINE uint32_t LL_DCACHE_GetReadBurstType(const DCACHE_TypeDef *DCACHEx)
308 {
309 return (uint32_t)(READ_BIT(DCACHEx->CR, DCACHE_CR_HBURST));
310 }
311
312 /**
313 * @brief Invalidate the Data cache.
314 * @rmtoll CR CACHEINV LL_DCACHE_Invalidate
315 * @param DCACHEx DCACHE instance
316 * @retval None
317 */
LL_DCACHE_Invalidate(DCACHE_TypeDef * DCACHEx)318 __STATIC_INLINE void LL_DCACHE_Invalidate(DCACHE_TypeDef *DCACHEx)
319 {
320 SET_BIT(DCACHEx->CR, DCACHE_CR_CACHEINV);
321 }
322
323 /**
324 * @}
325 */
326
327
328 /** @defgroup DCACHE_LL_EF_Monitor Monitor
329 * @{
330 */
331
332 /**
333 * @brief Enable the hit/miss monitor(s).
334 * @rmtoll CR (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN) LL_DCACHE_EnableMonitors
335 * @param DCACHEx DCACHE instance
336 * @param Monitors This parameter can be one or a combination of the following values:
337 * @arg LL_DCACHE_MONITOR_READ_HIT
338 * @arg LL_DCACHE_MONITOR_READ_MISS
339 * @arg LL_DCACHE_MONITOR_WRITE_HIT
340 * @arg LL_DCACHE_MONITOR_WRITE_MISS
341 * @arg LL_DCACHE_MONITOR_ALL
342 * @retval None
343 */
LL_DCACHE_EnableMonitors(DCACHE_TypeDef * DCACHEx,uint32_t Monitors)344 __STATIC_INLINE void LL_DCACHE_EnableMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
345 {
346 SET_BIT(DCACHEx->CR, Monitors);
347 }
348
349 /**
350 * @brief Disable the hit/miss monitor(s).
351 * @rmtoll CR (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN) LL_DCACHE_DisableMonitors
352 * @param DCACHEx DCACHE instance
353 * @param Monitors This parameter can be one or a combination of the following values:
354 * @arg LL_DCACHE_MONITOR_READ_HIT
355 * @arg LL_DCACHE_MONITOR_READ_MISS
356 * @arg LL_DCACHE_MONITOR_WRITE_HIT
357 * @arg LL_DCACHE_MONITOR_WRITE_MISS
358 * @arg LL_DCACHE_MONITOR_ALL
359 * @retval None
360 */
LL_DCACHE_DisableMonitors(DCACHE_TypeDef * DCACHEx,uint32_t Monitors)361 __STATIC_INLINE void LL_DCACHE_DisableMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
362 {
363 CLEAR_BIT(DCACHEx->CR, Monitors);
364 }
365
366 /**
367 * @brief Return the hit/miss monitor(s) enable state.
368 * @rmtoll CR (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN) LL_DCACHE_IsEnabledMonitors
369 * @param DCACHEx DCACHE instance
370 * @param Monitors This parameter can be one or a combination of the following values:
371 * @arg LL_DCACHE_MONITOR_READ_HIT
372 * @arg LL_DCACHE_MONITOR_READ_MISS
373 * @arg LL_DCACHE_MONITOR_WRITE_HIT
374 * @arg LL_DCACHE_MONITOR_WRITE_MISS
375 * @arg LL_DCACHE_MONITOR_ALL
376 * @retval State of parameter value (1 or 0).
377 */
LL_DCACHE_IsEnabledMonitors(const DCACHE_TypeDef * DCACHEx,uint32_t Monitors)378 __STATIC_INLINE uint32_t LL_DCACHE_IsEnabledMonitors(const DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
379 {
380 return (((READ_BIT(DCACHEx->CR, (DCACHE_CR_WMISSMEN | DCACHE_CR_WHITMEN | DCACHE_CR_RMISSMEN | DCACHE_CR_RHITMEN))\
381 & Monitors) == (Monitors)) ? 1UL : 0UL);
382 }
383
384 /**
385 * @brief Reset the Data Cache performance monitoring.
386 * @rmtoll CR (RHITMRST/RMISSMRST/WHITMRST/WMISSMRST) LL_DCACHE_ResetMonitors
387 * @param DCACHEx DCACHE instance
388 * @param Monitors Monitoring type
389 * This parameter can be a combination of the following values:
390 * @arg LL_DCACHE_MONITOR_READ_HIT
391 * @arg LL_DCACHE_MONITOR_READ_MISS
392 * @arg LL_DCACHE_MONITOR_WRITE_HIT
393 * @arg LL_DCACHE_MONITOR_WRITE_MISS
394 * @arg LL_DCACHE_MONITOR_ALL
395 * @retval None
396 */
LL_DCACHE_ResetMonitors(DCACHE_TypeDef * DCACHEx,uint32_t Monitors)397 __STATIC_INLINE void LL_DCACHE_ResetMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
398 {
399 /* Reset */
400 SET_BIT(DCACHEx->CR, (Monitors << 2U));
401
402 /* Release reset */
403 CLEAR_BIT(DCACHEx->CR, (Monitors << 2U));
404 }
405
406 /**
407 * @brief Get the Read Hit monitor Value
408 * @rmtoll RHMONR RHITMON LL_DCACHE_Monitor_GetReadHitValue
409 * @param DCACHEx DCACHE instance
410 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
411 */
LL_DCACHE_Monitor_GetReadHitValue(const DCACHE_TypeDef * DCACHEx)412 __STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadHitValue(const DCACHE_TypeDef *DCACHEx)
413 {
414 return DCACHEx->RHMONR;
415 }
416
417 /**
418 * @brief Get the Read Miss monitor Value
419 * @rmtoll RMMONR RMISSMON LL_DCACHE_Monitor_GetReadMissValue
420 * @param DCACHEx DCACHE instance
421 * @retval Value between Min_Data=0 and Max_Data=0xFFFF
422 */
LL_DCACHE_Monitor_GetReadMissValue(const DCACHE_TypeDef * DCACHEx)423 __STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadMissValue(const DCACHE_TypeDef *DCACHEx)
424 {
425 return DCACHEx->RMMONR;
426 }
427
428 /**
429 * @brief Get the Write Hit monitor Value
430 * @rmtoll WHMONR WHITMON LL_DCACHE_Monitor_GetWriteHitValue
431 * @param DCACHEx DCACHE instance
432 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
433 */
LL_DCACHE_Monitor_GetWriteHitValue(const DCACHE_TypeDef * DCACHEx)434 __STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteHitValue(const DCACHE_TypeDef *DCACHEx)
435 {
436 return DCACHEx->WHMONR;
437 }
438
439 /**
440 * @brief Get the Write Miss monitor Value
441 * @rmtoll WMMONR WMISSMON LL_DCACHE_Monitor_GetWriteMissValue
442 * @param DCACHEx DCACHE instance
443 * @retval Value between Min_Data=0 and Max_Data=0xFFFF
444 */
LL_DCACHE_Monitor_GetWriteMissValue(const DCACHE_TypeDef * DCACHEx)445 __STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteMissValue(const DCACHE_TypeDef *DCACHEx)
446 {
447 return DCACHEx->WMMONR;
448 }
449
450 /**
451 * @}
452 */
453
454 /** @defgroup DCACHE_LL_EF_IT_Management IT-Management
455 * @{
456 */
457
458 /**
459 * @brief Enable BusyEnd interrupt.
460 * @rmtoll IER BSYENDIE LL_DCACHE_EnableIT_BSYEND
461 * @param DCACHEx DCACHE instance
462 * @retval None
463 */
LL_DCACHE_EnableIT_BSYEND(DCACHE_TypeDef * DCACHEx)464 __STATIC_INLINE void LL_DCACHE_EnableIT_BSYEND(DCACHE_TypeDef *DCACHEx)
465 {
466 SET_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE);
467 }
468
469 /**
470 * @brief Disable BusyEnd interrupt.
471 * @rmtoll IER BSYENDIE LL_DCACHE_DisableIT_BSYEND
472 * @param DCACHEx DCACHE instance
473 * @retval None
474 */
LL_DCACHE_DisableIT_BSYEND(DCACHE_TypeDef * DCACHEx)475 __STATIC_INLINE void LL_DCACHE_DisableIT_BSYEND(DCACHE_TypeDef *DCACHEx)
476 {
477 CLEAR_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE);
478 }
479
480 /**
481 * @brief Indicates whether the Busyend interrupt is enabled.
482 * @rmtoll IER BSYENDIE LL_DCACHE_IsEnabledIT_BSYEND
483 * @param DCACHEx DCACHE instance
484 * @retval State of bit (1 or 0).
485 */
LL_DCACHE_IsEnabledIT_BSYEND(const DCACHE_TypeDef * DCACHEx)486 __STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_BSYEND(const DCACHE_TypeDef *DCACHEx)
487 {
488 return ((READ_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE) == (DCACHE_IER_BSYENDIE)) ? 1UL : 0UL);
489 }
490
491 /**
492 * @brief Enable Error interrupt.
493 * @rmtoll IER ERRIE LL_DCACHE_EnableIT_ERR
494 * @param DCACHEx DCACHE instance
495 * @retval None
496 */
LL_DCACHE_EnableIT_ERR(DCACHE_TypeDef * DCACHEx)497 __STATIC_INLINE void LL_DCACHE_EnableIT_ERR(DCACHE_TypeDef *DCACHEx)
498 {
499 SET_BIT(DCACHEx->IER, DCACHE_IER_ERRIE);
500 }
501
502 /**
503 * @brief Disable Error interrupt.
504 * @rmtoll IER ERRIE LL_DCACHE_DisableIT_ERR
505 * @param DCACHEx DCACHE instance
506 * @retval None
507 */
LL_DCACHE_DisableIT_ERR(DCACHE_TypeDef * DCACHEx)508 __STATIC_INLINE void LL_DCACHE_DisableIT_ERR(DCACHE_TypeDef *DCACHEx)
509 {
510 CLEAR_BIT(DCACHEx->IER, DCACHE_IER_ERRIE);
511 }
512
513 /**
514 * @brief Indicates whether the Error interrupt is enabled.
515 * @rmtoll IER ERRIE LL_DCACHE_IsEnabledIT_ERR
516 * @param DCACHEx DCACHE instance
517 * @retval State of bit (1 or 0).
518 */
LL_DCACHE_IsEnabledIT_ERR(const DCACHE_TypeDef * DCACHEx)519 __STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_ERR(const DCACHE_TypeDef *DCACHEx)
520 {
521 return ((READ_BIT(DCACHEx->IER, DCACHE_IER_ERRIE) == (DCACHE_IER_ERRIE)) ? 1UL : 0UL);
522 }
523
524 /**
525 * @brief Enable command end interrupt.
526 * @rmtoll IER CMDENDIE LL_DCACHE_EnableIT_CMDEND
527 * @param DCACHEx DCACHE instance
528 * @retval None
529 */
LL_DCACHE_EnableIT_CMDEND(DCACHE_TypeDef * DCACHEx)530 __STATIC_INLINE void LL_DCACHE_EnableIT_CMDEND(DCACHE_TypeDef *DCACHEx)
531 {
532 SET_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE);
533 }
534
535 /**
536 * @brief Disable command end interrupt.
537 * @rmtoll IER CMDENDIE LL_DCACHE_DisableIT_CMDEND
538 * @param DCACHEx DCACHE instance
539 * @retval None
540 */
LL_DCACHE_DisableIT_CMDEND(DCACHE_TypeDef * DCACHEx)541 __STATIC_INLINE void LL_DCACHE_DisableIT_CMDEND(DCACHE_TypeDef *DCACHEx)
542 {
543 CLEAR_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE);
544 }
545
546 /**
547 * @brief Indicates whether the command end interrupt is enabled.
548 * @rmtoll IER CMDENDIE LL_DCACHE_IsEnabledIT_CMDEND
549 * @param DCACHEx DCACHE instance
550 * @retval State of bit (1 or 0).
551 */
LL_DCACHE_IsEnabledIT_CMDEND(const DCACHE_TypeDef * DCACHEx)552 __STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_CMDEND(const DCACHE_TypeDef *DCACHEx)
553 {
554 return ((READ_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE) == (DCACHE_IER_CMDENDIE)) ? 1UL : 0UL);
555 }
556
557 /**
558 * @brief Clear full invalidate busy end flag.
559 * @rmtoll FCR CBSYENDF LL_DCACHE_ClearFlag_BSYEND
560 * @param DCACHEx DCACHE instance
561 * @retval None
562 */
LL_DCACHE_ClearFlag_BSYEND(DCACHE_TypeDef * DCACHEx)563 __STATIC_INLINE void LL_DCACHE_ClearFlag_BSYEND(DCACHE_TypeDef *DCACHEx)
564 {
565 WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CBSYENDF);
566 }
567
568 /**
569 * @brief Clear cache error flag.
570 * @rmtoll FCR CERRF LL_DCACHE_ClearFlag_ERR
571 * @param DCACHEx DCACHE instance
572 * @retval None
573 */
LL_DCACHE_ClearFlag_ERR(DCACHE_TypeDef * DCACHEx)574 __STATIC_INLINE void LL_DCACHE_ClearFlag_ERR(DCACHE_TypeDef *DCACHEx)
575 {
576 WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CERRF);
577 }
578
579 /**
580 * @brief Clear command end flag.
581 * @rmtoll FCR CCMDENDF LL_DCACHE_ClearFlag_CMDEND
582 * @param DCACHEx DCACHE instance
583 * @retval None
584 */
LL_DCACHE_ClearFlag_CMDEND(DCACHE_TypeDef * DCACHEx)585 __STATIC_INLINE void LL_DCACHE_ClearFlag_CMDEND(DCACHE_TypeDef *DCACHEx)
586 {
587 WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CCMDENDF);
588 }
589
590 /**
591 * @brief Get flag Dcache BUSY.
592 * @rmtoll SR BUSYF LL_DCACHE_IsActiveFlag_BUSY
593 * @param DCACHEx DCACHE instance
594 * @retval State of bit (1 or 0).
595 */
LL_DCACHE_IsActiveFlag_BUSY(const DCACHE_TypeDef * DCACHEx)596 __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSY(const DCACHE_TypeDef *DCACHEx)
597 {
598 return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BUSYF) == (DCACHE_SR_BUSYF)) ? 1UL : 0UL);
599 }
600
601 /**
602 * @brief Get flag Dcache Busyend.
603 * @rmtoll SR BSYENDF LL_DCACHE_IsActiveFlag_BSYEND
604 * @param DCACHEx DCACHE instance
605 * @retval State of bit (1 or 0).
606 */
LL_DCACHE_IsActiveFlag_BSYEND(const DCACHE_TypeDef * DCACHEx)607 __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BSYEND(const DCACHE_TypeDef *DCACHEx)
608 {
609 return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BSYENDF) == (DCACHE_SR_BSYENDF)) ? 1UL : 0UL);
610 }
611
612 /**
613 * @brief Get flag Dcache Error.
614 * @rmtoll SR ERRF LL_DCACHE_IsActiveFlag_ERR
615 * @param DCACHEx DCACHE instance
616 * @retval State of bit (1 or 0).
617 */
LL_DCACHE_IsActiveFlag_ERR(const DCACHE_TypeDef * DCACHEx)618 __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_ERR(const DCACHE_TypeDef *DCACHEx)
619 {
620 return ((READ_BIT(DCACHEx->SR, DCACHE_SR_ERRF) == (DCACHE_SR_ERRF)) ? 1UL : 0UL);
621 }
622
623 /**
624 * @brief Get flag Dcache Busy command.
625 * @rmtoll SR BUSYCMDF LL_DCACHE_IsActiveFlag_BUSYCMD
626 * @param DCACHEx DCACHE instance
627 * @retval State of bit (1 or 0).
628 */
LL_DCACHE_IsActiveFlag_BUSYCMD(const DCACHE_TypeDef * DCACHEx)629 __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSYCMD(const DCACHE_TypeDef *DCACHEx)
630 {
631 return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BUSYCMDF) == (DCACHE_SR_BUSYCMDF)) ? 1UL : 0UL);
632 }
633
634 /**
635 * @brief Get flag Dcache command end.
636 * @rmtoll SR CMDENDF LL_DCACHE_IsActiveFlag_CMDEND
637 * @param DCACHEx DCACHE instance
638 * @retval State of bit (1 or 0).
639 */
LL_DCACHE_IsActiveFlag_CMDEND(const DCACHE_TypeDef * DCACHEx)640 __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_CMDEND(const DCACHE_TypeDef *DCACHEx)
641 {
642 return ((READ_BIT(DCACHEx->SR, DCACHE_SR_CMDENDF) == (DCACHE_SR_CMDENDF)) ? 1UL : 0UL);
643 }
644
645 /**
646 * @}
647 */
648
649 /**
650 * @}
651 */
652
653 /**
654 * @}
655 */
656
657 #endif /* DCACHE1 || DCACHE2 */
658
659 /**
660 * @}
661 */
662
663 #ifdef __cplusplus
664 }
665 #endif
666
667 #endif /* STM32U5xx_LL_DCACHE_H */
668
