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Searched refs:COMP_CSR_INSEL_Pos (Results 1 – 22 of 22) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l152xb.h1534 #define COMP_CSR_INSEL_Pos (18U) macro
1535 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1537 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1538 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1539 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l152xba.h1519 #define COMP_CSR_INSEL_Pos (18U) macro
1520 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1522 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1523 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1524 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l100xba.h1516 #define COMP_CSR_INSEL_Pos (18U) macro
1517 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1519 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1520 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1521 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l100xb.h1516 #define COMP_CSR_INSEL_Pos (18U) macro
1517 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1519 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1520 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1521 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l151xb.h1517 #define COMP_CSR_INSEL_Pos (18U) macro
1518 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1520 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1521 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1522 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l151xba.h1517 #define COMP_CSR_INSEL_Pos (18U) macro
1518 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1520 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1521 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1522 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l100xc.h1570 #define COMP_CSR_INSEL_Pos (18U) macro
1571 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1573 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1574 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1575 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l151xc.h1628 #define COMP_CSR_INSEL_Pos (18U) macro
1629 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1631 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1632 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1633 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l151xca.h1647 #define COMP_CSR_INSEL_Pos (18U) macro
1648 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1650 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1651 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1652 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l151xdx.h1664 #define COMP_CSR_INSEL_Pos (18U) macro
1665 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1667 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1668 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1669 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l151xe.h1664 #define COMP_CSR_INSEL_Pos (18U) macro
1665 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1667 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1668 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1669 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l152xc.h1624 #define COMP_CSR_INSEL_Pos (18U) macro
1625 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1627 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1628 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1629 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l152xca.h1664 #define COMP_CSR_INSEL_Pos (18U) macro
1665 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1667 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1668 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1669 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l152xdx.h1681 #define COMP_CSR_INSEL_Pos (18U) macro
1682 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1684 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1685 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1686 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l152xe.h1681 #define COMP_CSR_INSEL_Pos (18U) macro
1682 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1684 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1685 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1686 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l162xc.h1754 #define COMP_CSR_INSEL_Pos (18U) macro
1755 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1757 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1758 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1759 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l162xca.h1794 #define COMP_CSR_INSEL_Pos (18U) macro
1795 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1797 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1798 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1799 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l162xdx.h1811 #define COMP_CSR_INSEL_Pos (18U) macro
1812 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1814 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1815 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1816 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l162xe.h1811 #define COMP_CSR_INSEL_Pos (18U) macro
1812 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1814 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1815 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1816 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l151xd.h1721 #define COMP_CSR_INSEL_Pos (18U) macro
1722 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1724 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1725 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1726 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l152xd.h1738 #define COMP_CSR_INSEL_Pos (18U) macro
1739 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1741 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1742 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1743 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
Dstm32l162xd.h1868 #define COMP_CSR_INSEL_Pos (18U) macro
1869 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
1871 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
1872 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
1873 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */