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Searched refs:AHB3PERIPH_BASE (Results 1 – 25 of 34) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wl5mxx.h960 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x18000000UL) macro
1046 #define PWR_BASE (AHB3PERIPH_BASE + 0x00000400UL)
1047 #define EXTI_BASE (AHB3PERIPH_BASE + 0x00000800UL)
1048 #define IPCC_BASE (AHB3PERIPH_BASE + 0x00000C00UL)
1049 #define RCC_BASE (AHB3PERIPH_BASE + 0x00000000UL)
1050 #define RNG_BASE (AHB3PERIPH_BASE + 0x00001000UL)
1051 #define HSEM_BASE (AHB3PERIPH_BASE + 0x00001400UL)
1052 #define AES_BASE (AHB3PERIPH_BASE + 0x00001800UL)
1053 #define PKA_BASE (AHB3PERIPH_BASE + 0x00002000UL)
1054 #define FLASH_REG_BASE (AHB3PERIPH_BASE + 0x00004000UL)
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Dstm32wl54xx.h960 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x18000000UL) macro
1046 #define PWR_BASE (AHB3PERIPH_BASE + 0x00000400UL)
1047 #define EXTI_BASE (AHB3PERIPH_BASE + 0x00000800UL)
1048 #define IPCC_BASE (AHB3PERIPH_BASE + 0x00000C00UL)
1049 #define RCC_BASE (AHB3PERIPH_BASE + 0x00000000UL)
1050 #define RNG_BASE (AHB3PERIPH_BASE + 0x00001000UL)
1051 #define HSEM_BASE (AHB3PERIPH_BASE + 0x00001400UL)
1052 #define AES_BASE (AHB3PERIPH_BASE + 0x00001800UL)
1053 #define PKA_BASE (AHB3PERIPH_BASE + 0x00002000UL)
1054 #define FLASH_REG_BASE (AHB3PERIPH_BASE + 0x00004000UL)
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Dstm32wl55xx.h960 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x18000000UL) macro
1046 #define PWR_BASE (AHB3PERIPH_BASE + 0x00000400UL)
1047 #define EXTI_BASE (AHB3PERIPH_BASE + 0x00000800UL)
1048 #define IPCC_BASE (AHB3PERIPH_BASE + 0x00000C00UL)
1049 #define RCC_BASE (AHB3PERIPH_BASE + 0x00000000UL)
1050 #define RNG_BASE (AHB3PERIPH_BASE + 0x00001000UL)
1051 #define HSEM_BASE (AHB3PERIPH_BASE + 0x00001400UL)
1052 #define AES_BASE (AHB3PERIPH_BASE + 0x00001800UL)
1053 #define PKA_BASE (AHB3PERIPH_BASE + 0x00002000UL)
1054 #define FLASH_REG_BASE (AHB3PERIPH_BASE + 0x00004000UL)
[all …]
Dstm32wle4xx.h796 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x18000000UL) macro
882 #define PWR_BASE (AHB3PERIPH_BASE + 0x00000400UL)
883 #define EXTI_BASE (AHB3PERIPH_BASE + 0x00000800UL)
884 #define RCC_BASE (AHB3PERIPH_BASE + 0x00000000UL)
885 #define RNG_BASE (AHB3PERIPH_BASE + 0x00001000UL)
886 #define HSEM_BASE (AHB3PERIPH_BASE + 0x00001400UL)
887 #define AES_BASE (AHB3PERIPH_BASE + 0x00001800UL)
888 #define PKA_BASE (AHB3PERIPH_BASE + 0x00002000UL)
889 #define FLASH_REG_BASE (AHB3PERIPH_BASE + 0x00004000UL)
Dstm32wle5xx.h796 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x18000000UL) macro
882 #define PWR_BASE (AHB3PERIPH_BASE + 0x00000400UL)
883 #define EXTI_BASE (AHB3PERIPH_BASE + 0x00000800UL)
884 #define RCC_BASE (AHB3PERIPH_BASE + 0x00000000UL)
885 #define RNG_BASE (AHB3PERIPH_BASE + 0x00001000UL)
886 #define HSEM_BASE (AHB3PERIPH_BASE + 0x00001400UL)
887 #define AES_BASE (AHB3PERIPH_BASE + 0x00001800UL)
888 #define PKA_BASE (AHB3PERIPH_BASE + 0x00002000UL)
889 #define FLASH_REG_BASE (AHB3PERIPH_BASE + 0x00004000UL)
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f358xx.h671 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) macro
753 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
754 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)
755 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
756 #define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400UL)
757 #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500UL)
758 #define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700UL)
Dstm32f303xc.h710 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) macro
794 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
795 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)
796 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
797 #define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400UL)
798 #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500UL)
799 #define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700UL)
Dstm32f303xe.h790 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) macro
879 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
880 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)
881 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
882 #define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400UL)
883 #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500UL)
884 #define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700UL)
Dstm32f398xx.h749 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) macro
836 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
837 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)
838 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
839 #define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400UL)
840 #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500UL)
841 #define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700UL)
Dstm32f301x8.h593 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) macro
654 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
655 #define ADC1_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
Dstm32f318xx.h594 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) macro
655 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
656 #define ADC1_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
Dstm32f328xx.h651 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) macro
711 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
712 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)
713 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
Dstm32f302xc.h701 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) macro
778 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
779 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)
780 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
Dstm32f303x8.h652 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) macro
712 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
713 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)
714 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
Dstm32f302xe.h763 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) macro
844 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
845 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)
846 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
Dstm32f334x8.h755 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) macro
822 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
823 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)
824 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
Dstm32f302x8.h697 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) macro
761 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
762 #define ADC1_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7s7xx.h2180 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x08020000UL) macro
2272 #define RNG_BASE AHB3PERIPH_BASE
2273 #define HASH_BASE (AHB3PERIPH_BASE + 0x0400UL)
2274 #define HASH_DIGEST_BASE (AHB3PERIPH_BASE + 0x0710UL)
2275 #define CRYP_BASE (AHB3PERIPH_BASE + 0x0800UL)
2276 #define SAES_BASE (AHB3PERIPH_BASE + 0x1000UL)
2277 #define PKA_BASE (AHB3PERIPH_BASE + 0x2000UL)
Dstm32h7s3xx.h2111 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x08020000UL) macro
2203 #define RNG_BASE AHB3PERIPH_BASE
2204 #define HASH_BASE (AHB3PERIPH_BASE + 0x0400UL)
2205 #define HASH_DIGEST_BASE (AHB3PERIPH_BASE + 0x0710UL)
2206 #define CRYP_BASE (AHB3PERIPH_BASE + 0x0800UL)
2207 #define SAES_BASE (AHB3PERIPH_BASE + 0x1000UL)
2208 #define PKA_BASE (AHB3PERIPH_BASE + 0x2000UL)
Dstm32h7r3xx.h1983 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x08020000UL) macro
2075 #define RNG_BASE AHB3PERIPH_BASE
2076 #define HASH_BASE (AHB3PERIPH_BASE + 0x0400UL)
2077 #define HASH_DIGEST_BASE (AHB3PERIPH_BASE + 0x0710UL)
2078 #define PKA_BASE (AHB3PERIPH_BASE + 0x2000UL)
Dstm32h7r7xx.h2050 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x08020000UL) macro
2142 #define RNG_BASE AHB3PERIPH_BASE
2143 #define HASH_BASE (AHB3PERIPH_BASE + 0x0400UL)
2144 #define HASH_DIGEST_BASE (AHB3PERIPH_BASE + 0x0710UL)
2145 #define PKA_BASE (AHB3PERIPH_BASE + 0x2000UL)
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb35xx.h919 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x50000000UL) macro
1023 #define QUADSPI_BASE (AHB3PERIPH_BASE + 0x00000000UL) /*!< QUADSPI memories accessible ov…
1024 #define QUADSPI_R_BASE (AHB3PERIPH_BASE + 0x10001000UL) /*!< QUADSPI control registers base…
Dstm32wb55xx.h957 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x50000000UL) macro
1065 #define QUADSPI_BASE (AHB3PERIPH_BASE + 0x00000000UL) /*!< QUADSPI memories accessible ov…
1066 #define QUADSPI_R_BASE (AHB3PERIPH_BASE + 0x10001000UL) /*!< QUADSPI control registers base…
Dstm32wb5mxx.h957 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x50000000UL) macro
1065 #define QUADSPI_BASE (AHB3PERIPH_BASE + 0x00000000UL) /*!< QUADSPI memories accessible ov…
1066 #define QUADSPI_R_BASE (AHB3PERIPH_BASE + 0x10001000UL) /*!< QUADSPI control registers base…
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h2083 #define AHB3PERIPH_BASE AHB3PERIPH_BASE_S macro
2497 #define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS macro

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