Home
last modified time | relevance | path

Searched refs:ADC_SQR5_SQ2_Pos (Results 1 – 22 of 22) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l152xb.h1355 #define ADC_SQR5_SQ2_Pos (5U) macro
1356 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1358 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1359 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1360 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1361 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1362 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l152xba.h1340 #define ADC_SQR5_SQ2_Pos (5U) macro
1341 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1343 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1344 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1345 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1346 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1347 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l100xba.h1337 #define ADC_SQR5_SQ2_Pos (5U) macro
1338 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1340 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1341 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1342 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1343 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1344 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l100xb.h1337 #define ADC_SQR5_SQ2_Pos (5U) macro
1338 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1340 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1341 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1342 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1343 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1344 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l151xb.h1338 #define ADC_SQR5_SQ2_Pos (5U) macro
1339 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1341 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1342 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1343 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1344 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1345 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l151xba.h1338 #define ADC_SQR5_SQ2_Pos (5U) macro
1339 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1341 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1342 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1343 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1344 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1345 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l100xc.h1391 #define ADC_SQR5_SQ2_Pos (5U) macro
1392 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1394 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1395 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1396 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1397 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1398 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l151xc.h1449 #define ADC_SQR5_SQ2_Pos (5U) macro
1450 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1452 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1453 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1454 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1455 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1456 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l151xca.h1453 #define ADC_SQR5_SQ2_Pos (5U) macro
1454 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1456 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1457 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1458 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1459 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1460 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l151xdx.h1470 #define ADC_SQR5_SQ2_Pos (5U) macro
1471 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1473 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1474 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1475 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1476 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1477 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l151xe.h1470 #define ADC_SQR5_SQ2_Pos (5U) macro
1471 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1473 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1474 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1475 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1476 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1477 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l152xc.h1445 #define ADC_SQR5_SQ2_Pos (5U) macro
1446 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1448 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1449 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1450 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1451 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1452 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l152xca.h1470 #define ADC_SQR5_SQ2_Pos (5U) macro
1471 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1473 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1474 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1475 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1476 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1477 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l152xdx.h1487 #define ADC_SQR5_SQ2_Pos (5U) macro
1488 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1490 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1491 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1492 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1493 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1494 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l152xe.h1487 #define ADC_SQR5_SQ2_Pos (5U) macro
1488 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1490 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1491 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1492 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1493 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1494 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l162xc.h1468 #define ADC_SQR5_SQ2_Pos (5U) macro
1469 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1471 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1472 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1473 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1474 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1475 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l162xca.h1493 #define ADC_SQR5_SQ2_Pos (5U) macro
1494 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1496 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1497 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1498 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1499 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1500 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l162xdx.h1510 #define ADC_SQR5_SQ2_Pos (5U) macro
1511 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1513 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1514 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1515 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1516 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1517 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l162xe.h1510 #define ADC_SQR5_SQ2_Pos (5U) macro
1511 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1513 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1514 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1515 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1516 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1517 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l151xd.h1527 #define ADC_SQR5_SQ2_Pos (5U) macro
1528 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1530 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1531 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1532 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1533 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1534 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l152xd.h1544 #define ADC_SQR5_SQ2_Pos (5U) macro
1545 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1547 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1548 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1549 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1550 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1551 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
Dstm32l162xd.h1567 #define ADC_SQR5_SQ2_Pos (5U) macro
1568 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
1570 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
1571 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
1572 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
1573 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
1574 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */