Home
last modified time | relevance | path

Searched refs:ADC_SMPR3_SMP2_Pos (Results 1 – 22 of 22) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l152xb.h1057 #define ADC_SMPR3_SMP2_Pos (6U) macro
1058 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1060 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1061 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1062 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l152xba.h1042 #define ADC_SMPR3_SMP2_Pos (6U) macro
1043 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1045 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1046 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1047 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l100xba.h1039 #define ADC_SMPR3_SMP2_Pos (6U) macro
1040 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1042 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1043 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1044 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l100xb.h1039 #define ADC_SMPR3_SMP2_Pos (6U) macro
1040 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1042 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1043 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1044 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l151xb.h1040 #define ADC_SMPR3_SMP2_Pos (6U) macro
1041 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1043 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1044 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1045 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l151xba.h1040 #define ADC_SMPR3_SMP2_Pos (6U) macro
1041 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1043 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1044 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1045 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l100xc.h1084 #define ADC_SMPR3_SMP2_Pos (6U) macro
1085 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1087 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1088 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1089 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l151xc.h1142 #define ADC_SMPR3_SMP2_Pos (6U) macro
1143 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1145 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1146 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1147 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l151xca.h1146 #define ADC_SMPR3_SMP2_Pos (6U) macro
1147 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1149 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1150 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1151 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l151xdx.h1163 #define ADC_SMPR3_SMP2_Pos (6U) macro
1164 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1166 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1167 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1168 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l151xe.h1163 #define ADC_SMPR3_SMP2_Pos (6U) macro
1164 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1166 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1167 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1168 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l152xc.h1138 #define ADC_SMPR3_SMP2_Pos (6U) macro
1139 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1141 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1142 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1143 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l152xca.h1163 #define ADC_SMPR3_SMP2_Pos (6U) macro
1164 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1166 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1167 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1168 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l152xdx.h1180 #define ADC_SMPR3_SMP2_Pos (6U) macro
1181 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1183 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1184 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1185 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l152xe.h1180 #define ADC_SMPR3_SMP2_Pos (6U) macro
1181 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1183 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1184 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1185 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l162xc.h1161 #define ADC_SMPR3_SMP2_Pos (6U) macro
1162 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1164 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1165 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1166 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l162xca.h1186 #define ADC_SMPR3_SMP2_Pos (6U) macro
1187 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1189 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1190 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1191 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l162xdx.h1203 #define ADC_SMPR3_SMP2_Pos (6U) macro
1204 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1206 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1207 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1208 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l162xe.h1203 #define ADC_SMPR3_SMP2_Pos (6U) macro
1204 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1206 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1207 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1208 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l151xd.h1220 #define ADC_SMPR3_SMP2_Pos (6U) macro
1221 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1223 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1224 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1225 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l152xd.h1237 #define ADC_SMPR3_SMP2_Pos (6U) macro
1238 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1240 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1241 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1242 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
Dstm32l162xd.h1260 #define ADC_SMPR3_SMP2_Pos (6U) macro
1261 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
1263 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
1264 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
1265 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */