Searched refs:ADC_CHSELR_SQ5 (Results 1 – 25 of 58) sorted by relevance
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556 …ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | ADC_CHSELR_SQ5\
789 …ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | ADC_CHSELR_SQ5\
1356 #define LL_ADC4_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer…
326 … ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
318 … ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
713 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer …
319 … ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
818 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular se…
857 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular se…
876 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular se…
877 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular se…
345 …TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | ADC_CHSELR_SQ5 | ADC_CHSELR_S…
1017 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer …
1150 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regul… macro
1154 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regul… macro
1231 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regul… macro
1183 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regul… macro
1202 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regul… macro
1205 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regul… macro
1226 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regul… macro
1273 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regul… macro
1289 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regul… macro
1336 #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regul… macro