1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32N6xx_HAL_ADC_H 21 #define STM32N6xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32n6xx_ll_adc.h" 32 33 /** @addtogroup STM32N6xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief ADC group regular oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 This parameter can be a value from 1 to 1024 */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 57 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 59 60 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 61 The oversampling is either temporary stopped or reset upon an injected 62 sequence interruption. 63 If oversampling is enabled on both regular and injected groups, 64 this parameter is discarded and forced to setting 65 "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed 66 during injection sequence). 67 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 68 69 } ADC_OversamplingTypeDef; 70 71 /** 72 * @brief Structure definition of ADC instance and ADC group regular. 73 * @note ADC clock prescaler (init structure "ClockPrescaler" in other ADC IP versions FW drivers) 74 * is moved on RCC side on this STM32 series (rational: for feature "fixed trigger latency"). 75 * Refer to RCC FW drivers to configure ADC clock prescaler. 76 * @note Parameters of this structure are shared within 2 scopes: 77 * - Scope entire ADC (affects ADC groups regular and injected): Resolution, 78 * GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait. 79 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, 80 * NbrOfDiscConversion, ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, 81 * OversamplingMode, Oversampling, SamplingMode. 82 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 83 * ADC state can be either: 84 * - For all parameters: ADC disabled 85 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': 86 * ADC enabled without conversion on going on group regular. 87 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going 88 * on groups regular and injected. 89 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 90 * without error reporting (as it can be the expected behavior in case of intended action to update another 91 * parameter (which fulfills the ADC state condition) on the fly). 92 */ 93 typedef struct 94 { 95 uint32_t Resolution; /*!< Configure the ADC resolution. 96 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 97 98 uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw 99 conversion data, based on following formula: 100 DATA = DATA(raw) * (gain compensation coef) / 4096 101 12 bit format, unsigned: 2 bits exponents / 12 bits mantissa 102 Gain step is 1/4096 = 0.000244 103 Gain range is 0.0000 to 3.999756 104 This parameter value can be: 105 - value "0": Gain compensation will be disabled and coefficient set to 0 106 - value in range [0x0001; 0x3FFF]: Gain compensation will enabled 107 and coefficient set to specified value */ 108 109 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 110 This parameter can be associated to parameter 'DiscontinuousConvMode' 111 to have main sequence subdivided in successive parts. 112 If disabled: Conversion is performed in single mode (one channel converted, 113 the one defined in rank 1). 114 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' 115 are discarded (equivalent to set to 1). 116 If enabled: Conversions are performed in sequence mode (multiple ranks defined 117 by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of 118 each channel in sequencer). 119 Scan direction is upward: from rank 1 to rank 'n'. 120 This parameter can be a value of @ref ADC_Scan_mode */ 121 122 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and 123 interruption: end of unitary conversion or end of sequence conversions. 124 This parameter can be a value of @ref ADC_EOCSelection. */ 125 126 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the 127 previous conversion (for ADC group regular) or previous sequence (for ADC group 128 injected) has been retrieved by user software, using function HAL_ADC_GetValue() 129 or HAL_ADCEx_InjectedGetValue(). 130 This feature automatically adapts the frequency of ADC conversions triggers to 131 the speed of the system that reads the data. Moreover, this avoids risk of 132 overrun for low frequency applications. 133 This parameter can be set to ENABLE or DISABLE. 134 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), 135 HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC 136 flag (by CPU to free the IRQ pending event or by DMA). 137 Auto wait will work but fort a very short time, discarding its intended 138 benefit (except specific case of high load of CPU or DMA transfers which 139 can justify usage of auto wait). 140 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, 141 when ADC conversion data is needed: 142 use HAL_ADC_PollForConversion() to ensure that conversion is completed and 143 HAL_ADC_GetValue() to retrieve conversion result and trig another 144 conversion start. (in case of usage of ADC group injected, use the 145 equivalent functions HAL_ADCExInjected_Start(), 146 HAL_ADCEx_InjectedGetValue(), ...). */ 147 148 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) 149 or continuous mode for ADC group regular, after the first ADC conversion 150 start trigger occurred (software start or external trigger). This parameter 151 can be set to ENABLE or DISABLE. */ 152 153 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group 154 sequencer. 155 To use the regular group sequencer and convert several ranks, 156 parameter 'ScanConvMode' must be enabled. 157 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 158 Note: This parameter must be modified when no conversion is on going on 159 regular group (ADC disabled, or ADC enabled without continuous mode 160 or external trigger that could launch a conversion). */ 161 162 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed 163 in Complete-sequence/Discontinuous-sequence (main sequence subdivided in 164 successive parts). 165 Discontinuous mode is used only if sequencer is enabled (parameter 166 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 167 Discontinuous mode can be enabled only if continuous mode is disabled. 168 If continuous mode is enabled, this parameter setting is discarded. 169 This parameter can be set to ENABLE or DISABLE. */ 170 171 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence 172 of ADC group regular (parameter NbrOfConversion) will be subdivided. 173 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 174 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 175 176 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion 177 start. 178 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger 179 is used instead. 180 This parameter can be a value of @ref ADC_regular_external_trigger_source. 181 Caution: external trigger source is common to all ADC instances. */ 182 183 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular 184 conversion start. 185 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 186 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 187 188 uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. 189 This parameter can be a value of @ref ADC_regular_sampling_mode */ 190 191 uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA 192 (oneshot or circular), or stored in the DR register or 193 transferred to MDF register. 194 Note: In continuous mode, DMA must be configured in circular mode. 195 Otherwise an overrun will be triggered when DMA buffer maximum pointer 196 is reached. 197 This parameter can be a value of @ref ADC_ConversionDataManagement. 198 Note: This parameter must be modified when no conversion is on going on both 199 regular and injected groups (ADC disabled, or ADC enabled without 200 continuous mode or external trigger that could launch a conversion). */ 201 202 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 203 This parameter applies to ADC group regular only. 204 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 205 Note: In case of overrun set to data preserved and usage with programming model 206 with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of 207 conversion flags, this induces the release of the preserved data. 208 If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), 209 placed in user program code (called before end of conversion flags clear). 210 Note: Error reporting with respect to the conversion mode: 211 - Usage with ADC conversion by polling for event or interruption: 212 Error is reported only if overrun is set to data preserved. 213 If overrun is set to data overwritten, user can willingly not read 214 all the converted data, this is not considered as an erroneous case. 215 - Usage with ADC conversion by DMA: Error is reported whatever overrun 216 setting (DMA is expected to process all data from data register). */ 217 218 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without 219 oversampling. 220 This parameter can be a value of @ref ADCEx_Left_Bit_Shift */ 221 222 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 223 This parameter can be set to ENABLE or DISABLE. 224 Note: This parameter can be modified only if there is no conversion 225 is ongoing on ADC groups regular and injected */ 226 227 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 228 Caution: this setting overwrites the previous oversampling configuration 229 if oversampling is already enabled. */ 230 231 } ADC_InitTypeDef; 232 233 /** 234 * @brief Structure definition of ADC channel for regular group 235 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 236 * ADC state can be either: 237 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 238 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion 239 * on going on regular group. 240 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on 241 * regular and injected groups. 242 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 243 * without error reporting (as it can be the expected behavior in case of intended action to update another 244 * parameter (which fulfills the ADC state condition) on the fly. 245 */ 246 typedef struct 247 { 248 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 249 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 250 Note: Depending on devices and ADC instances, some channels may not be available 251 on device package pins. Refer to device datasheet for channels 252 availability. */ 253 254 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 255 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 256 Note: to disable a channel or change order of conversion sequencer, rank 257 containing a previous channel setting can be overwritten by 258 the new channel setting (or parameter number of conversions adjusted) */ 259 260 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 261 Unit: ADC clock cycles 262 Conversion time is the addition of sampling time and processing time 263 (13.5 ADC clock cycles at ADC resolution 12 bits, 11.5 cycles at 10 bits, 264 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 265 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 266 Caution: This parameter applies to a channel that can be used into regular 267 and/or injected group. It overwrites the last setting. 268 Note: In case of usage of internal measurement channels 269 (VrefInt/Vbat/TempSensor), sampling time constraints must be respected 270 (sampling time can be adjusted in function of ADC clock frequency 271 and sampling time setting). 272 Refer to device datasheet for timings values. */ 273 274 uint32_t SingleDiff; /*!< Select single-ended or differential input. 275 In differential mode: Differential measurement is carried out between 276 the selected channel (positive input) and 277 another channel (negative input). Refer to 278 reference manual for corresponding channel. 279 Only channel of positive input has to be 280 configured, the other channel is configured 281 automatically. 282 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 283 Caution: This parameter applies to a channel that can be used in a regular 284 and/or injected group. It overwrites the last setting. 285 Note: Refer to Reference Manual to ensure the selected channel is available 286 in differential mode. 287 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' 288 is not usable separately. 289 Note: This parameter must be modified when ADC is disabled (before ADC start 290 conversion or after ADC stop conversion). 291 If ADC is enabled, this parameter setting is bypassed without error 292 reporting (as it can be the expected behavior in case of another parameter 293 update on the fly) */ 294 295 uint32_t OffsetNumber; /*!< Select the offset number 296 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 297 Caution: Only one offset is allowed per channel. This parameter overwrites the 298 last setting. */ 299 300 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. 301 Offset value must be a positive number. 302 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter 303 must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 304 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 305 Note: This parameter must be modified when no conversion is on going on both 306 regular and injected groups (ADC disabled, or ADC enabled without 307 continuous mode or external trigger that could launch a conversion). */ 308 309 FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not. 310 This parameter is applied only for 16-bit or 8-bit resolution. 311 This parameter can be set to ENABLE or DISABLE. */ 312 313 FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 314 This parameter value can be ENABLE or DISABLE. 315 Note: 316 - This parameter must be modified when no conversion is on going on 317 both regular and injected groups (ADC disabled, or ADC enabled without 318 continuous mode or external trigger that could launch a conversion).*/ 319 320 uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added 321 (positive sign) from or to the raw converted data. 322 This parameter can be a value of @ref ADCEx_OffsetSign. 323 Note: 324 - This parameter must be modified when no conversion is on going on 325 both regular and injected groups (ADC disabled, or ADC enabled without 326 continuous mode or external trigger that could launch a conversion).*/ 327 328 329 } ADC_ChannelConfTypeDef; 330 331 /** 332 * @brief Structure definition of ADC analog watchdog 333 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 334 * ADC state can be either: 335 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular 336 * and injected. 337 */ 338 typedef struct 339 { 340 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 341 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels 342 by setting parameter 'WatchdogMode') 343 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls 344 of 'HAL_ADC_AnalogWDGConfig()' for each channel) 345 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 346 347 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 348 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all 349 channels, ADC groups regular and-or injected. 350 For Analog Watchdog 2 and 3: Several channels can be monitored by applying 351 successively the AWD init structure. 352 Channels on ADC group regular and injected are not differentiated: 353 Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, 354 value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 355 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. 356 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 357 358 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 359 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' 360 is configured on single channel (only 1 channel can be 361 monitored). 362 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, 363 call successively the function HAL_ADC_AnalogWDGConfig() 364 for each channel to be added (or removed with value 365 'ADC_ANALOGWATCHDOG_NONE'). 366 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 367 368 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 369 This parameter can be set to ENABLE or DISABLE */ 370 371 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 372 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter 373 must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF 374 or 0x3F respectively. */ 375 376 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 377 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter 378 must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF 379 or 0x3F respectively. */ 380 381 uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. 382 Before setting flag or raising interrupt, analog watchdog can wait to have several 383 consecutive out-of-window samples. This parameter allows to configure this number. 384 This parameter only applies to Analog watchdog 1. For others, use value 385 ADC_AWD_FILTERING_NONE. 386 This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */ 387 388 } ADC_AnalogWDGConfTypeDef; 389 390 /** @defgroup ADC_States ADC States 391 * @{ 392 */ 393 394 /** 395 * @brief HAL ADC state machine: ADC states definition (bitfields) 396 * @note ADC state machine is managed by bitfields, state must be compared 397 * with bit by bit. 398 * For example: 399 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 400 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 401 */ 402 /* States of ADC global scope */ 403 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 404 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 405 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, 406 calibration, ...) */ 407 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 408 409 /* States of ADC errors */ 410 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 411 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 412 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 413 414 /* States of ADC group regular */ 415 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur 416 (either by continuous mode, external trigger, low power 417 auto power-on (if feature available), multimode ADC master 418 control (if feature available)) */ 419 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 420 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 421 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag 422 raised */ 423 424 /* States of ADC group injected */ 425 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur 426 (either by auto-injection mode, external trigger, low 427 power auto power-on (if feature available), multimode 428 ADC master control (if feature available)) */ 429 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 430 431 /* States of ADC analog watchdogs */ 432 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 433 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 434 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 435 436 /* States of ADC multi-mode */ 437 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another 438 ADC master (when feature available) */ 439 440 /** 441 * @} 442 */ 443 444 /** 445 * @brief ADC handle Structure definition 446 */ 447 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 448 typedef struct __ADC_HandleTypeDef 449 #else 450 typedef struct 451 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 452 { 453 ADC_TypeDef *Instance; /*!< Register base address */ 454 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular 455 conversions setting */ 456 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 457 HAL_LockTypeDef Lock; /*!< ADC locking object */ 458 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 459 __IO uint32_t ErrorCode; /*!< ADC Error code */ 460 461 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 462 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 463 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer 464 callback */ 465 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 466 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 467 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete 468 callback */ 469 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 470 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 471 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 472 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 473 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 474 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 475 } ADC_HandleTypeDef; 476 477 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 478 /** 479 * @brief HAL ADC Callback ID enumeration definition 480 */ 481 typedef enum 482 { 483 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 484 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 485 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 486 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 487 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 488 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 489 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 490 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 491 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 492 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 493 } HAL_ADC_CallbackIDTypeDef; 494 495 /** 496 * @brief HAL ADC Callback pointer definition 497 */ 498 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 499 500 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 501 502 /** 503 * @} 504 */ 505 506 507 /* Exported constants --------------------------------------------------------*/ 508 509 /** @defgroup ADC_Exported_Constants ADC Exported Constants 510 * @{ 511 */ 512 513 /** @defgroup ADC_Error_Code ADC Error Code 514 * @{ 515 */ 516 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 517 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 518 enable/disable, erroneous state, ...) */ 519 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 520 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 521 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 522 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 523 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 529 * @{ 530 */ 531 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 532 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 533 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 534 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 535 /** 536 * @} 537 */ 538 539 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 540 * @{ 541 */ 542 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 543 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 544 545 /** @defgroup ADC_Private_Constants ADC Private Constants 546 * @{ 547 */ 548 549 /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ 550 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) 551 /** 552 * @} 553 */ 554 555 /* Combination of all CHSELR bits: SQ2...SQ8 */ 556 #define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | ADC_CHSELR_SQ5\ 557 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8) 558 /** 559 * @} 560 */ 561 562 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 563 * @{ 564 */ 565 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion 566 trigger internal: SW start. */ 567 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion 568 trigger from external peripheral: external interrupt line 11. */ 569 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion 570 trigger from external peripheral: TIM1 channel 1 event (capture compare). */ 571 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion 572 trigger from external peripheral: TIM1 channel 2 event (capture compare). */ 573 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion 574 trigger from external peripheral: TIM1 channel 3 event (capture compare). */ 575 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion 576 trigger from external peripheral: TIM1 TRGO event. */ 577 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion 578 trigger from external peripheral: TIM1 TRGO2 event. */ 579 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion 580 trigger from external peripheral: TIM2 channel 2 event (capture compare). */ 581 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion 582 trigger from external peripheral: TIM2 TRGO event. */ 583 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion 584 trigger from external peripheral: TIM3 channel 4 event (capture compare). */ 585 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion 586 trigger from external peripheral: TIM3 TRGO event. */ 587 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion 588 trigger from external peripheral: TIM4 channel 4 event (capture compare). */ 589 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion 590 trigger from external peripheral: TIM4 TRGO event. */ 591 #define ADC_EXTERNALTRIG_T5_TRGO (LL_ADC_REG_TRIG_EXT_TIM5_TRGO) /*!< ADC group regular conversion 592 trigger from external peripheral: TIM5 TRGO event. */ 593 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion 594 trigger from external peripheral: TIM6 TRGO event. */ 595 #define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion 596 trigger from external peripheral: TIM7 TRGO event. */ 597 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion 598 trigger from external peripheral: TIM8 TRGO event. */ 599 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion 600 trigger from external peripheral: TIM8 TRGO2 event. */ 601 #define ADC_EXTERNALTRIG_T9_CC1 (LL_ADC_REG_TRIG_EXT_TIM9_CH1) /*!< ADC group regular conversion 602 trigger from external peripheral: TIM9 channel 1 event (capture compare). */ 603 #define ADC_EXTERNALTRIG_T9_TRGO (LL_ADC_REG_TRIG_EXT_TIM9_TRGO) /*!< ADC group regular conversion 604 trigger from external peripheral: TIM9 TRGO event. */ 605 #define ADC_EXTERNALTRIG_T12_TRGO (LL_ADC_REG_TRIG_EXT_TIM12_TRGO) /*!< ADC group regular conversion 606 trigger from external peripheral: TIM12 TRGO event. */ 607 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion 608 trigger from external peripheral: TIM15 TRGO event. */ 609 #define ADC_EXTERNALTRIG_T18_TRGO (LL_ADC_REG_TRIG_EXT_TIM18_TRGO) /*!< ADC group regular conversion 610 trigger from external peripheral: TIM18 TRGO event. */ 611 #define ADC_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion 612 trigger from external peripheral: LPTIM1 channel 1 event. */ 613 #define ADC_EXTERNALTRIG_LPTIM2_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) /*!< ADC group regular conversion 614 trigger from external peripheral: LPTIM2 channel 2 event. */ 615 #define ADC_EXTERNALTRIG_LPTIM3_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) /*!< ADC group regular conversion 616 trigger from external peripheral: LPTIM3 channel 3 event. */ 617 /** 618 * @} 619 */ 620 621 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 622 * @{ 623 */ 624 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger 625 disabled (SW start)*/ 626 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion 627 trigger polarity set to rising edge */ 628 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion 629 trigger polarity set to falling edge */ 630 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion 631 trigger polarity set to both rising and falling edges */ 632 /** 633 * @} 634 */ 635 636 /** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode 637 * @{ 638 */ 639 #define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is 640 defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ 641 #define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts 642 immediately after end of conversion, and stops upon trigger event. 643 Note: First conversion is using minimal sampling time 644 (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */ 645 #define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled 646 by trigger events: 647 Trigger rising edge = start sampling 648 Trigger falling edge = stop sampling and start conversion */ 649 /** 650 * @} 651 */ 652 653 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 654 * @{ 655 */ 656 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 657 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 658 /** 659 * @} 660 */ 661 662 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 663 * @{ 664 */ 665 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case 666 of overrun: data preserved */ 667 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case 668 of overrun: data overwritten */ 669 /** 670 * @} 671 */ 672 673 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 674 * @{ 675 */ 676 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 677 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 678 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 679 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 680 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 681 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 682 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 683 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 684 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 685 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 686 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 687 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 688 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 689 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 690 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 691 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 692 /** 693 * @} 694 */ 695 696 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 697 * @{ 698 */ 699 #define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ 700 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 701 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ 702 #define ADC_SAMPLETIME_11CYCLES_5 (LL_ADC_SAMPLINGTIME_11CYCLES_5) /*!< Sampling time 11.5 ADC clock cycles */ 703 #define ADC_SAMPLETIME_23CYCLES_5 (LL_ADC_SAMPLINGTIME_23CYCLES_5) /*!< Sampling time 23.5 ADC clock cycles */ 704 #define ADC_SAMPLETIME_46CYCLES_5 (LL_ADC_SAMPLINGTIME_46CYCLES_5) /*!< Sampling time 46.5 ADC clock cycles */ 705 #define ADC_SAMPLETIME_246CYCLES_5 (LL_ADC_SAMPLINGTIME_246CYCLES_5) /*!< Sampling time 246.5 ADC clock cycles */ 706 #define ADC_SAMPLETIME_1499CYCLES_5 (LL_ADC_SAMPLINGTIME_1499CYCLES_5) /*!< Sampling time 1499.5 ADC clock cycles*/ 707 /** 708 * @} 709 */ 710 711 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 712 * @{ 713 */ 714 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 715 /* all ADC instances (refer to Reference Manual). */ 716 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (connected to GPIO 717 pin) ADCx_IN0 */ 718 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (connected to GPIO 719 pin) ADCx_IN1 */ 720 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (connected to GPIO 721 pin) ADCx_IN2 */ 722 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (connected to GPIO 723 pin) ADCx_IN3 */ 724 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (connected to GPIO 725 pin) ADCx_IN4 */ 726 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (connected to GPIO 727 pin) ADCx_IN5 */ 728 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (connected to GPIO 729 pin) ADCx_IN6 */ 730 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (connected to GPIO 731 pin) ADCx_IN7 */ 732 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (connected to GPIO 733 pin) ADCx_IN8 */ 734 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (connected to GPIO 735 pin) ADCx_IN9 */ 736 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (connected to GPIO 737 pin) ADCx_IN10 */ 738 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (connected to GPIO 739 pin) ADCx_IN11 */ 740 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (connected to GPIO 741 pin) ADCx_IN12 */ 742 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (connected to GPIO 743 pin) ADCx_IN13 */ 744 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (connected to GPIO 745 pin) ADCx_IN14 */ 746 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (connected to GPIO 747 pin) ADCx_IN15 */ 748 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (connected to GPIO 749 pin) ADCx_IN16 */ 750 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (connected to GPIO 751 pin) ADCx_IN17 */ 752 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (connected to GPIO 753 pin) ADCx_IN18 */ 754 #define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (connected to GPIO 755 pin) ADCx_IN19 */ 756 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to 757 VrefInt: Internal voltage reference. 758 On this STM32 series, ADC channel available only on ADC instance: ADC1. */ 759 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to 760 Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat 761 always below Vdda. 762 On this STM32 series, ADC channel available only on ADC instance: ADC2. */ 763 #define ADC_CHANNEL_VDDCORE (LL_ADC_CHANNEL_VDDCORE) /*!< ADC internal channel connected to 764 VddCore. 765 On this STM32 series, ADC channel available only on ADC instance: ADC2. */ 766 /** 767 * @} 768 */ 769 770 /** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management 771 * @{ 772 */ 773 #define ADC_CONVERSIONDATA_DR (LL_ADC_REG_DR_TRANSFER) /*!< ADC conversions data are available 774 in ADC data register only */ 775 #define ADC_CONVERSIONDATA_DMA_ONESHOT (LL_ADC_REG_DMA_TRANSFER_LIMITED) /*!< ADC conversion data are transferred 776 by DMA, in limited mode (one shot mode): DMA transfer requests are stopped 777 when number of DMA data transfers (number of ADC conversions) is reached. 778 This ADC mode is intended to be used with DMA mode non-circular. */ 779 #define ADC_CONVERSIONDATA_DMA_CIRCULAR (LL_ADC_REG_DMA_TRANSFER_UNLIMITED) /*!< ADC conversion data are transferred 780 by DMA, in unlimited mode: DMA transfer requests are unlimited, 781 whatever number of DMA data transferred (number of ADC conversions). 782 This ADC mode is intended to be used with DMA mode circular. */ 783 #define ADC_CONVERSIONDATA_MDF (LL_ADC_REG_MDF_TRANSFER) /*!< ADC conversion data are transferred 784 to MDF */ 785 786 /** 787 * @} 788 */ 789 790 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number 791 * @{ 792 */ 793 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 794 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 795 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 796 /** 797 * @} 798 */ 799 800 /** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration 801 * @{ 802 */ 803 #define ADC_AWD_FILTERING_NONE LL_ADC_AWD_FILTERING_NONE /*!< ADC analog watchdog no filtering, 804 one out-of-window sample is needed to raise flag or interrupt */ 805 #define ADC_AWD_FILTERING_2SAMPLES LL_ADC_AWD_FILTERING_2SAMPLES /*!< ADC analog watchdog 2 consecutives 806 out-of-window samples are needed to raise flag or interrupt */ 807 #define ADC_AWD_FILTERING_3SAMPLES LL_ADC_AWD_FILTERING_3SAMPLES /*!< ADC analog watchdog 3 consecutives 808 out-of-window samples are needed to raise flag or interrupt */ 809 #define ADC_AWD_FILTERING_4SAMPLES LL_ADC_AWD_FILTERING_4SAMPLES /*!< ADC analog watchdog 4 consecutives 810 out-of-window samples are needed to raise flag or interrupt */ 811 #define ADC_AWD_FILTERING_5SAMPLES LL_ADC_AWD_FILTERING_5SAMPLES /*!< ADC analog watchdog 5 consecutives 812 out-of-window samples are needed to raise flag or interrupt */ 813 #define ADC_AWD_FILTERING_6SAMPLES LL_ADC_AWD_FILTERING_6SAMPLES /*!< ADC analog watchdog 6 consecutives 814 out-of-window samples are needed to raise flag or interrupt */ 815 #define ADC_AWD_FILTERING_7SAMPLES LL_ADC_AWD_FILTERING_7SAMPLES /*!< ADC analog watchdog 7 consecutives 816 out-of-window samples are needed to raise flag or interrupt */ 817 #define ADC_AWD_FILTERING_8SAMPLES LL_ADC_AWD_FILTERING_8SAMPLES /*!< ADC analog watchdog 8 consecutives 818 out-of-window samples are needed to raise flag or interrupt */ 819 /** 820 * @} 821 */ 822 823 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode 824 * @{ 825 */ 826 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ 827 828 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to a 829 regular group single channel */ 830 831 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR1_AWD1SGL | ADC_CFGR1_JAWD1EN) /*!< ADC AWD applied to an 832 injected group single channel */ 833 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN \ 834 | ADC_CFGR1_JAWD1EN) /*!< ADC AWD applied to a 835 regular and injected groups single channel */ 836 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to regular 837 group all channels */ 838 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR1_JAWD1EN) /*!< ADC AWD applied to injected 839 group all channels */ 840 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR1_AWD1EN | ADC_CFGR1_JAWD1EN) /*!< ADC AWD applied to regular 841 and injected groups all channels */ 842 /** 843 * @} 844 */ 845 846 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 847 * @{ 848 */ 849 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ 850 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ 851 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ 852 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ 853 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ 854 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ 855 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ 856 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ 857 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ 858 #define ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling right shift of 9 ranks */ 859 #define ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling right shift of 10 ranks */ 860 /** 861 * @} 862 */ 863 864 /** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift 865 * @{ 866 */ 867 #define ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE) /*!< ADC No bit shift */ 868 #define ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1) /*!< ADC 1 bit shift */ 869 #define ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2) /*!< ADC 2 bits shift */ 870 #define ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3) /*!< ADC 3 bits shift */ 871 #define ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4) /*!< ADC 4 bits shift */ 872 #define ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5) /*!< ADC 5 bits shift */ 873 #define ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6) /*!< ADC 6 bits shift */ 874 #define ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7) /*!< ADC 7 bits shift */ 875 #define ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8) /*!< ADC 8 bits shift */ 876 #define ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9) /*!< ADC 9 bits shift */ 877 #define ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10) /*!< ADC 10 bits shift */ 878 #define ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11) /*!< ADC 11 bits shift */ 879 #define ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12) /*!< ADC 12 bits shift */ 880 #define ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13) /*!< ADC 13 bits shift */ 881 #define ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14) /*!< ADC 14 bits shift */ 882 #define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15) /*!< ADC 15 bits shift */ 883 /** 884 * @} 885 */ 886 887 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 888 * @{ 889 */ 890 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: 891 continuous mode (all conversions of OVS ratio are done from 1 trigger) */ 892 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: 893 discontinuous mode (each conversion of OVS ratio needs a trigger) */ 894 /** 895 * @} 896 */ 897 898 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 899 * @{ 900 */ 901 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained 902 during injection sequence */ 903 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during 904 injection sequence */ 905 /** 906 * @} 907 */ 908 909 /** @defgroup ADC_Event_type ADC Event type 910 * @{ 911 */ 912 /** 913 * @note Analog watchdog 1 is available on all stm32 series 914 * Analog watchdog 2 and 3 are not available on all series 915 */ 916 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 917 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ 918 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ 919 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ 920 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 921 /** 922 * @} 923 */ 924 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility 925 with other STM32 devices having only one analog watchdog */ 926 927 /** @defgroup ADC_interrupts_definition ADC interrupts definition 928 * @{ 929 */ 930 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 931 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 932 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 933 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 934 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 935 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 936 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 937 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 938 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog 939 watchdog) */ 940 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog 941 watchdog) */ 942 /** 943 * @} 944 */ 945 946 /** @defgroup ADC_flags_definition ADC flags definition 947 * @{ 948 */ 949 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 950 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 951 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 952 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 953 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 954 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 955 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 956 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 957 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 958 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 959 /** 960 * @} 961 */ 962 963 /** 964 * @} 965 */ 966 967 /* Private macro -------------------------------------------------------------*/ 968 969 /** @defgroup ADC_Private_Macros ADC Private Macros 970 * @{ 971 */ 972 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 973 /* code of final user. */ 974 975 /** 976 * @brief Verify the ADC data conversion setting. 977 * @param DATA : programmed DATA conversion mode. 978 * @retval SET (DATA is a valid value) or RESET (DATA is invalid) 979 */ 980 #define IS_ADC_CONVERSIONDATAMGT(DATA) \ 981 ((((DATA) == ADC_CONVERSIONDATA_DR)) || \ 982 (((DATA) == ADC_CONVERSIONDATA_MDF)) || \ 983 (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \ 984 (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR))) 985 986 /** 987 * @brief Return resolution bits in CFGR register RES[1:0] field. 988 * @param __HANDLE__ ADC handle 989 * @retval Value of bitfield RES in CFGR register. 990 */ 991 #define ADC_GET_RESOLUTION(__HANDLE__) \ 992 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 993 994 /** 995 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 996 * @param __HANDLE__ ADC handle 997 * @retval None 998 */ 999 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 1000 1001 /** 1002 * @brief Verification of ADC state: enabled or disabled. 1003 * @param __HANDLE__ ADC handle 1004 * @retval SET (ADC enabled) or RESET (ADC disabled) 1005 */ 1006 #define ADC_IS_ENABLE(__HANDLE__) \ 1007 ((((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 1008 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 1009 ) ? SET : RESET) 1010 1011 /** 1012 * @brief Check if conversion is on going on regular group. 1013 * @param __HANDLE__ ADC handle 1014 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 1015 */ 1016 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 1017 (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) 1018 1019 1020 /** 1021 * @brief Simultaneously clear and set specific bits of the handle State. 1022 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 1023 * the first parameter is the ADC handle State, the second parameter is the 1024 * bit field to clear, the third and last parameter is the bit field to set. 1025 * @retval None 1026 */ 1027 #define ADC_STATE_CLR_SET MODIFY_REG 1028 1029 /** 1030 * @brief Verify that a given value is aligned with the ADC resolution range. 1031 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 1032 * @param __ADC_VALUE__ value checked against the resolution. 1033 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 1034 */ 1035 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 1036 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 1037 1038 /** 1039 * @brief Verify the length of the scheduled regular conversions group. 1040 * @param __LENGTH__ number of programmed conversions. 1041 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) 1042 * or RESET (__LENGTH__ is null or too large) 1043 */ 1044 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 1045 1046 1047 /** 1048 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 1049 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 1050 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) 1051 * or RESET (NUMBER is null or too large) 1052 */ 1053 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 1054 1055 /** 1056 * @brief Verify the ADC resolution setting. 1057 * @param __RESOLUTION__ programmed ADC resolution. 1058 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1059 */ 1060 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 1061 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 1062 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 1063 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 1064 1065 /** 1066 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 1067 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. 1068 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1069 */ 1070 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 1071 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 1072 1073 /** 1074 * @brief Verify the ADC gain compensation. 1075 * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient. 1076 * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid) 1077 */ 1078 #define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 0x3FFFUL) 1079 1080 /** 1081 * @brief Verify the ADC offset. 1082 * @param __OFFSET__ programmed ADC offset. 1083 * @retval SET (__OFFSET__ is a valid value) or RESET (__OFFSET__ is invalid) 1084 */ 1085 #define IS_ADC_OFFSET(__OFFSET__) ((__OFFSET__) <= 0x3FFFFFUL) 1086 1087 /** 1088 * @brief Verify the ADC scan mode. 1089 * @param __SCAN_MODE__ programmed ADC scan mode. 1090 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 1091 */ 1092 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 1093 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 1094 1095 /** 1096 * @brief Verify the ADC edge trigger setting for regular group. 1097 * @param __EDGE__ programmed ADC edge trigger setting. 1098 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1099 */ 1100 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 1101 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 1102 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1103 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1104 1105 /** 1106 * @brief Verify the ADC regular conversions external trigger. 1107 * @param __ADC_INSTANCE__ ADC instance 1108 * @param __REG_TRIG_SOURCE__ programmed ADC regular conversions external trigger. 1109 * @retval SET (__REG_TRIG_SOURCE__ is a valid value) or RESET (__REG_TRIG_SOURCE__ is invalid) 1110 */ 1111 #define IS_ADC_EXTTRIG(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ 1112 (((__REG_TRIG_SOURCE__) == ADC_SOFTWARE_START) \ 1113 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_EXT_IT11) \ 1114 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_CC1) \ 1115 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_CC2) \ 1116 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_CC3) \ 1117 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_TRGO) \ 1118 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T1_TRGO2) \ 1119 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T2_CC2) \ 1120 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T2_TRGO) \ 1121 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T3_CC4) \ 1122 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T3_TRGO) \ 1123 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T4_CC4) \ 1124 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T4_TRGO) \ 1125 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T5_TRGO) \ 1126 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T6_TRGO) \ 1127 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T7_TRGO) \ 1128 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T8_TRGO) \ 1129 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T8_TRGO2) \ 1130 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T9_CC1) \ 1131 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T9_TRGO) \ 1132 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T12_TRGO) \ 1133 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T15_TRGO) \ 1134 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_T18_TRGO) \ 1135 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_LPTIM1_CH1) \ 1136 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_LPTIM2_CH1) \ 1137 || ((__REG_TRIG_SOURCE__) == ADC_EXTERNALTRIG_LPTIM3_CH1) \ 1138 ) 1139 1140 1141 /** 1142 * @brief Verify the ADC regular conversions external trigger. 1143 * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger. 1144 * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid) 1145 */ 1146 #define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \ 1147 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \ 1148 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) ) 1149 1150 /** 1151 * @brief Verify the ADC regular conversions check for converted data availability. 1152 * @param __EOC_SELECTION__ converted data availability check. 1153 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 1154 */ 1155 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 1156 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 1157 1158 /** 1159 * @brief Verify the ADC regular conversions overrun handling. 1160 * @param __OVR__ ADC regular conversions overrun handling. 1161 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 1162 */ 1163 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 1164 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 1165 1166 /** 1167 * @brief Verify the ADC conversions sampling time. 1168 * @param __SAMPLING_TIME__ ADC conversions sampling time. 1169 * @retval SET (__SAMPLING_TIME__ is a valid value) or RESET (__SAMPLING_TIME__ is invalid) 1170 */ 1171 #define IS_ADC_SAMPLING_TIME(__SAMPLING_TIME__) (((__SAMPLING_TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \ 1172 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 1173 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 1174 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_11CYCLES_5) || \ 1175 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_23CYCLES_5) || \ 1176 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_46CYCLES_5) || \ 1177 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_246CYCLES_5) || \ 1178 ((__SAMPLING_TIME__) == ADC_SAMPLETIME_1499CYCLES_5) ) 1179 1180 /** 1181 * @brief Verify the ADC regular channel setting. 1182 * @param __CHANNEL__ programmed ADC regular channel. 1183 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1184 */ 1185 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 1186 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 1187 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 1188 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 1189 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 1190 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 1191 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 1192 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 1193 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 1194 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 1195 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 1196 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 1197 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 1198 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 1199 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 1200 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 1201 1202 /** 1203 * @} 1204 */ 1205 1206 1207 /* Private constants ---------------------------------------------------------*/ 1208 1209 /** @defgroup ADC_Private_Constants ADC Private Constants 1210 * @{ 1211 */ 1212 1213 /* Fixed timeout values for ADC conversion (including sampling time) */ 1214 /* Maximum sampling time is 1499.5 ADC clock cycle (SMPx[2:0] = 0b111) */ 1215 /* Maximum conversion time is 12.5 + Maximum samling time */ 1216 /* or 12.5 + 1499.5 = 1512 ADC clock cycles */ 1217 /* Minimum ADC Clock frequency is 0.7 MHz */ 1218 /* (refer to device datasheet, parameter "fADC") */ 1219 /* Maximum conversion time is */ 1220 /* = 1512 / 0.7MHz = 2.16 ms */ 1221 /* Used timeout value includes a margin versus theoretical max value */ 1222 #define ADC_STOP_CONVERSION_TIMEOUT (5UL) /*!< ADC stop time-out value */ 1223 1224 /* Delay for temperature sensor stabilization time. */ 1225 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1226 /* Unit: us */ 1227 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1228 1229 /* Delay for ADC voltage regulator startup time */ 1230 /* Maximum delay is 10 microseconds */ 1231 /* (refer device RM, parameter Tadcvreg_stup). */ 1232 #define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */ 1233 1234 /** 1235 * @} 1236 */ 1237 1238 /* Exported macro ------------------------------------------------------------*/ 1239 1240 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1241 * @{ 1242 */ 1243 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1244 /* final user. */ 1245 1246 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1247 * @{ 1248 */ 1249 1250 /** @brief Reset ADC handle state. 1251 * @param __HANDLE__ ADC handle 1252 * @retval None 1253 */ 1254 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1255 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1256 do{ \ 1257 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1258 (__HANDLE__)->MspInitCallback = NULL; \ 1259 (__HANDLE__)->MspDeInitCallback = NULL; \ 1260 } while(0) 1261 #else 1262 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1263 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1264 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1265 1266 /** 1267 * @brief Enable ADC interrupt. 1268 * @param __HANDLE__ ADC handle 1269 * @param __INTERRUPT__ ADC Interrupt 1270 * This parameter can be one of the following values: 1271 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1272 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1273 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1274 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1275 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1276 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1277 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1278 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1279 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1280 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1281 * @retval None 1282 */ 1283 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1284 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1285 1286 /** 1287 * @brief Disable ADC interrupt. 1288 * @param __HANDLE__ ADC handle 1289 * @param __INTERRUPT__ ADC Interrupt 1290 * This parameter can be one of the following values: 1291 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1292 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1293 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1294 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1295 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1296 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1297 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1298 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1299 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1300 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1301 * @retval None 1302 */ 1303 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1304 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1305 1306 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1307 * @param __HANDLE__ ADC handle 1308 * @param __INTERRUPT__ ADC interrupt source to check 1309 * This parameter can be one of the following values: 1310 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1311 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1312 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1313 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1314 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1315 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1316 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1317 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1318 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1319 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1320 * @retval State of interruption (SET or RESET) 1321 */ 1322 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1323 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1324 1325 /** 1326 * @brief Check whether the specified ADC flag is set or not. 1327 * @param __HANDLE__ ADC handle 1328 * @param __FLAG__ ADC flag 1329 * This parameter can be one of the following values: 1330 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1331 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1332 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1333 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1334 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1335 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1336 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1337 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1338 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1339 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1340 * @retval State of flag (TRUE or FALSE). 1341 */ 1342 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1343 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1344 1345 /** 1346 * @brief Clear the specified ADC flag. 1347 * @param __HANDLE__ ADC handle 1348 * @param __FLAG__ ADC flag 1349 * This parameter can be one of the following values: 1350 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1351 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1352 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1353 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1354 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1355 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1356 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1357 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1358 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1359 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1360 * @retval None 1361 */ 1362 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1363 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1364 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1365 1366 /** 1367 * @} 1368 */ 1369 1370 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1371 * @{ 1372 */ 1373 1374 /** 1375 * @brief Helper macro to get ADC channel number in decimal format 1376 * from literals ADC_CHANNEL_x. 1377 * @note Example: 1378 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1379 * will return decimal number "4". 1380 * @note The input can be a value from functions where a channel 1381 * number is returned, either defined with number 1382 * or with bitfield (only one bit must be set). 1383 * @param __CHANNEL__ This parameter can be one of the following values: 1384 * @arg @ref ADC_CHANNEL_0 1385 * @arg @ref ADC_CHANNEL_1 1386 * @arg @ref ADC_CHANNEL_2 1387 * @arg @ref ADC_CHANNEL_3 1388 * @arg @ref ADC_CHANNEL_4 1389 * @arg @ref ADC_CHANNEL_5 1390 * @arg @ref ADC_CHANNEL_6 1391 * @arg @ref ADC_CHANNEL_7 1392 * @arg @ref ADC_CHANNEL_8 1393 * @arg @ref ADC_CHANNEL_9 1394 * @arg @ref ADC_CHANNEL_10 1395 * @arg @ref ADC_CHANNEL_11 1396 * @arg @ref ADC_CHANNEL_12 1397 * @arg @ref ADC_CHANNEL_13 1398 * @arg @ref ADC_CHANNEL_14 1399 * @arg @ref ADC_CHANNEL_15 1400 * @arg @ref ADC_CHANNEL_16 1401 * @arg @ref ADC_CHANNEL_17 1402 * @arg @ref ADC_CHANNEL_18 1403 * @arg @ref ADC_CHANNEL_19 1404 * @arg @ref ADC_CHANNEL_VREFINT (1)(4) 1405 * @arg @ref ADC_CHANNEL_VBAT (2)(4) 1406 * @arg @ref ADC_CHANNEL_VDDCORE (2)(4) 1407 * 1408 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n 1409 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n 1410 * @retval Value between Min_Data=0 and Max_Data=18 1411 */ 1412 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1413 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1414 1415 /** 1416 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1417 * from number in decimal format. 1418 * @note Example: 1419 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1420 * will return a data equivalent to "ADC_CHANNEL_4". 1421 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1422 * @retval Returned value can be one of the following values: 1423 * @arg @ref ADC_CHANNEL_0 1424 * @arg @ref ADC_CHANNEL_1 1425 * @arg @ref ADC_CHANNEL_2 1426 * @arg @ref ADC_CHANNEL_3 1427 * @arg @ref ADC_CHANNEL_4 1428 * @arg @ref ADC_CHANNEL_5 1429 * @arg @ref ADC_CHANNEL_6 1430 * @arg @ref ADC_CHANNEL_7 1431 * @arg @ref ADC_CHANNEL_8 1432 * @arg @ref ADC_CHANNEL_9 1433 * @arg @ref ADC_CHANNEL_10 1434 * @arg @ref ADC_CHANNEL_11 1435 * @arg @ref ADC_CHANNEL_12 1436 * @arg @ref ADC_CHANNEL_13 1437 * @arg @ref ADC_CHANNEL_14 1438 * @arg @ref ADC_CHANNEL_15 1439 * @arg @ref ADC_CHANNEL_16 1440 * @arg @ref ADC_CHANNEL_17 1441 * @arg @ref ADC_CHANNEL_18 1442 * @arg @ref ADC_CHANNEL_19 1443 * @arg @ref ADC_CHANNEL_VREFINT (1)(3) 1444 * @arg @ref ADC_CHANNEL_VBAT (2)(3) 1445 * @arg @ref ADC_CHANNEL_VDDCORE (2)(3) 1446 * 1447 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n 1448 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n 1449 * (3) For ADC channel read back from ADC register, 1450 * comparison with internal channel parameter to be done 1451 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1452 */ 1453 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1454 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1455 1456 /** 1457 * @brief Helper macro to determine whether the selected channel 1458 * corresponds to literal definitions of driver. 1459 * @note The different literal definitions of ADC channels are: 1460 * - ADC internal channel: 1461 * ADC_CHANNEL_VREFINT, ... 1462 * - ADC external channel (channel connected to a GPIO pin): 1463 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1464 * @note The channel parameter must be a value defined from literal 1465 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ...), 1466 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1467 * must not be a value from functions where a channel number is 1468 * returned from ADC registers, 1469 * because internal and external channels share the same channel 1470 * number in ADC registers. The differentiation is made only with 1471 * parameters definitions of driver. 1472 * @param __CHANNEL__ This parameter can be one of the following values: 1473 * @arg @ref ADC_CHANNEL_0 1474 * @arg @ref ADC_CHANNEL_1 1475 * @arg @ref ADC_CHANNEL_2 1476 * @arg @ref ADC_CHANNEL_3 1477 * @arg @ref ADC_CHANNEL_4 1478 * @arg @ref ADC_CHANNEL_5 1479 * @arg @ref ADC_CHANNEL_6 1480 * @arg @ref ADC_CHANNEL_7 1481 * @arg @ref ADC_CHANNEL_8 1482 * @arg @ref ADC_CHANNEL_9 1483 * @arg @ref ADC_CHANNEL_10 1484 * @arg @ref ADC_CHANNEL_11 1485 * @arg @ref ADC_CHANNEL_12 1486 * @arg @ref ADC_CHANNEL_13 1487 * @arg @ref ADC_CHANNEL_14 1488 * @arg @ref ADC_CHANNEL_15 1489 * @arg @ref ADC_CHANNEL_16 1490 * @arg @ref ADC_CHANNEL_17 1491 * @arg @ref ADC_CHANNEL_18 1492 * @arg @ref ADC_CHANNEL_19 1493 * @arg @ref ADC_CHANNEL_VREFINT (1)(4) 1494 * @arg @ref ADC_CHANNEL_VBAT (2)(4) 1495 * @arg @ref ADC_CHANNEL_VDDCORE (2)(4) 1496 * 1497 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n 1498 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n 1499 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel 1500 * (channel connected to a GPIO pin). 1501 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1502 */ 1503 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1504 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1505 1506 /** 1507 * @brief Helper macro to convert a channel defined from parameter 1508 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ...), 1509 * to its equivalent parameter definition of a ADC external channel 1510 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1511 * @note The channel parameter can be, additionally to a value 1512 * defined from parameter definition of a ADC internal channel 1513 * (ADC_CHANNEL_VREFINT, ...), 1514 * a value defined from parameter definition of 1515 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1516 * or a value from functions where a channel number is returned 1517 * from ADC registers. 1518 * @param __CHANNEL__ This parameter can be one of the following values: 1519 * @arg @ref ADC_CHANNEL_0 1520 * @arg @ref ADC_CHANNEL_1 1521 * @arg @ref ADC_CHANNEL_2 1522 * @arg @ref ADC_CHANNEL_3 1523 * @arg @ref ADC_CHANNEL_4 1524 * @arg @ref ADC_CHANNEL_5 1525 * @arg @ref ADC_CHANNEL_6 1526 * @arg @ref ADC_CHANNEL_7 1527 * @arg @ref ADC_CHANNEL_8 1528 * @arg @ref ADC_CHANNEL_9 1529 * @arg @ref ADC_CHANNEL_10 1530 * @arg @ref ADC_CHANNEL_11 1531 * @arg @ref ADC_CHANNEL_12 1532 * @arg @ref ADC_CHANNEL_13 1533 * @arg @ref ADC_CHANNEL_14 1534 * @arg @ref ADC_CHANNEL_15 1535 * @arg @ref ADC_CHANNEL_16 1536 * @arg @ref ADC_CHANNEL_17 1537 * @arg @ref ADC_CHANNEL_18 1538 * @arg @ref ADC_CHANNEL_19 1539 * @arg @ref ADC_CHANNEL_VREFINT (1)(4) 1540 * @arg @ref ADC_CHANNEL_VBAT (2)(4) 1541 * @arg @ref ADC_CHANNEL_VDDCORE (2)(4) 1542 * 1543 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n 1544 * (2) On this STM32 series, parameter available only on ADC instance: ADC2.\n 1545 * @retval Returned value can be one of the following values: 1546 * @arg @ref ADC_CHANNEL_0 1547 * @arg @ref ADC_CHANNEL_1 1548 * @arg @ref ADC_CHANNEL_2 1549 * @arg @ref ADC_CHANNEL_3 1550 * @arg @ref ADC_CHANNEL_4 1551 * @arg @ref ADC_CHANNEL_5 1552 * @arg @ref ADC_CHANNEL_6 1553 * @arg @ref ADC_CHANNEL_7 1554 * @arg @ref ADC_CHANNEL_8 1555 * @arg @ref ADC_CHANNEL_9 1556 * @arg @ref ADC_CHANNEL_10 1557 * @arg @ref ADC_CHANNEL_11 1558 * @arg @ref ADC_CHANNEL_12 1559 * @arg @ref ADC_CHANNEL_13 1560 * @arg @ref ADC_CHANNEL_14 1561 * @arg @ref ADC_CHANNEL_15 1562 * @arg @ref ADC_CHANNEL_16 1563 * @arg @ref ADC_CHANNEL_17 1564 * @arg @ref ADC_CHANNEL_18 1565 * @arg @ref ADC_CHANNEL_19 1566 */ 1567 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1568 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1569 1570 /** 1571 * @brief Helper macro to determine whether the internal channel 1572 * selected is available on the ADC instance selected. 1573 * @note The channel parameter must be a value defined from parameter 1574 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, ...), 1575 * must not be a value defined from parameter definition of 1576 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1577 * or a value from functions where a channel number is 1578 * returned from ADC registers, 1579 * because internal and external channels share the same channel 1580 * number in ADC registers. The differentiation is made only with 1581 * parameters definitions of driver. 1582 * @param __ADC_INSTANCE__ ADC instance 1583 * @param __CHANNEL__ This parameter can be one of the following values: 1584 * @arg @ref ADC_CHANNEL_VREFINT (1) 1585 * @arg @ref ADC_CHANNEL_VBAT (2) 1586 * @arg @ref ADC_CHANNEL_VDDCORE (2) 1587 * 1588 * (1) On this STM32 series, parameter available only on ADC instance: ADC1.\n 1589 * (2) On this STM32 series, parameter available only on ADC instance: ADC2. 1590 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1591 * Value "1" if the internal channel selected is available on the ADC instance selected. 1592 */ 1593 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1594 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1595 1596 #if defined(ADC_MULTIMODE_SUPPORT) 1597 /** 1598 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1599 * or ADC slave from raw value with both ADC conversion data concatenated. 1600 * @note This macro is intended to be used when multimode transfer by DMA 1601 * is enabled: refer to function @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 1602 * In this case the transferred data need to processed with this macro 1603 * to separate the conversion data of ADC master and ADC slave. 1604 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1605 * @arg @ref LL_ADC_MULTI_MASTER 1606 * @arg @ref LL_ADC_MULTI_SLAVE 1607 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1608 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1609 */ 1610 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1611 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 1612 #endif /* ADC_MULTIMODE_SUPPORT */ 1613 1614 /** 1615 * @brief Helper macro to select the ADC common instance 1616 * to which is belonging the selected ADC instance. 1617 * @note ADC common register instance can be used for: 1618 * - Set parameters common to several ADC instances 1619 * - Multimode (for devices with several ADC instances) 1620 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1621 * @param __ADCx__ ADC instance 1622 * @retval ADC common register instance 1623 */ 1624 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1625 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1626 1627 /** 1628 * @brief Helper macro to check if all ADC instances sharing the same 1629 * ADC common instance are disabled. 1630 * @note This check is required by functions with setting conditioned to 1631 * ADC state: 1632 * All ADC instances of the ADC common group must be disabled. 1633 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1634 * @note On devices with only 1 ADC common instance, parameter of this macro 1635 * is useless and can be ignored (parameter kept for compatibility 1636 * with devices featuring several ADC common instances). 1637 * @param __ADCXY_COMMON__ ADC common instance 1638 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1639 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1640 * are disabled. 1641 * Value "1" if at least one ADC instance sharing the same ADC common instance 1642 * is enabled. 1643 */ 1644 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1645 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1646 1647 /** 1648 * @brief Helper macro to define the ADC conversion data full-scale digital 1649 * value corresponding to the selected ADC resolution. 1650 * @note ADC conversion data full-scale corresponds to voltage range 1651 * determined by analog voltage references Vref+ and Vref- 1652 * (refer to reference manual). 1653 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1654 * @arg @ref ADC_RESOLUTION_12B 1655 * @arg @ref ADC_RESOLUTION_10B 1656 * @arg @ref ADC_RESOLUTION_8B 1657 * @arg @ref ADC_RESOLUTION_6B 1658 * @retval ADC conversion data full-scale digital value 1659 */ 1660 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1661 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1662 1663 /** 1664 * @brief Helper macro to convert the ADC conversion data from 1665 * a resolution to another resolution. 1666 * @param __DATA__ ADC conversion data to be converted 1667 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1668 * This parameter can be one of the following values: 1669 * @arg @ref ADC_RESOLUTION_12B 1670 * @arg @ref ADC_RESOLUTION_10B 1671 * @arg @ref ADC_RESOLUTION_8B 1672 * @arg @ref ADC_RESOLUTION_6B 1673 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1674 * This parameter can be one of the following values: 1675 * @arg @ref ADC_RESOLUTION_12B 1676 * @arg @ref ADC_RESOLUTION_10B 1677 * @arg @ref ADC_RESOLUTION_8B 1678 * @arg @ref ADC_RESOLUTION_6B 1679 * @retval ADC conversion data to the requested resolution 1680 */ 1681 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1682 __ADC_RESOLUTION_CURRENT__,\ 1683 __ADC_RESOLUTION_TARGET__) \ 1684 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1685 (__ADC_RESOLUTION_CURRENT__),\ 1686 (__ADC_RESOLUTION_TARGET__)) 1687 1688 /** 1689 * @brief Helper macro to calculate the voltage (unit: mVolt) 1690 * corresponding to a ADC conversion data (unit: digital value). 1691 * @note Analog reference voltage (Vref+) must be either known from 1692 * user board environment or can be calculated using ADC measurement 1693 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1694 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1695 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1696 * (unit: digital value). 1697 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1698 * @arg @ref ADC_RESOLUTION_12B 1699 * @arg @ref ADC_RESOLUTION_10B 1700 * @arg @ref ADC_RESOLUTION_8B 1701 * @arg @ref ADC_RESOLUTION_6B 1702 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1703 */ 1704 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1705 __ADC_DATA__,\ 1706 __ADC_RESOLUTION__) \ 1707 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1708 (__ADC_DATA__),\ 1709 (__ADC_RESOLUTION__)) 1710 1711 /** 1712 * @brief Helper macro to calculate the voltage (unit: mVolt) 1713 * corresponding to a ADC conversion data (unit: digital value) 1714 * in differential ended mode. 1715 * @note Analog reference voltage (Vref+) must be either known from 1716 * user board environment or can be calculated using ADC measurement 1717 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1718 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1719 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1720 * (unit: digital value). 1721 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1722 * @arg @ref ADC_RESOLUTION_12B 1723 * @arg @ref ADC_RESOLUTION_10B 1724 * @arg @ref ADC_RESOLUTION_8B 1725 * @arg @ref ADC_RESOLUTION_6B 1726 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1727 */ 1728 #define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1729 __ADC_DATA__,\ 1730 __ADC_RESOLUTION__) \ 1731 __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1732 (__ADC_DATA__),\ 1733 (__ADC_RESOLUTION__)) 1734 1735 /** 1736 * @brief Helper macro to calculate analog reference voltage (Vref+) 1737 * (unit: mVolt) from ADC conversion data of internal voltage 1738 * reference VrefInt. 1739 * @note Computation is using VrefInt calibration value 1740 * stored in system memory for each device during production. 1741 * @note This voltage depends on user board environment: voltage level 1742 * connected to pin Vref+. 1743 * On devices with small package, the pin Vref+ is not present 1744 * and internally bonded to pin Vdda. 1745 * @note On this STM32 series, calibration data of internal voltage reference 1746 * VrefInt corresponds to a resolution of 12 bits, 1747 * this is the recommended ADC resolution to convert voltage of 1748 * internal voltage reference VrefInt. 1749 * Otherwise, this macro performs the processing to scale 1750 * ADC conversion data to 12 bits. 1751 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1752 * of internal voltage reference VrefInt (unit: digital value). 1753 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1754 * @arg @ref ADC_RESOLUTION_12B 1755 * @arg @ref ADC_RESOLUTION_10B 1756 * @arg @ref ADC_RESOLUTION_8B 1757 * @arg @ref ADC_RESOLUTION_6B 1758 * @retval Analog reference voltage (unit: mV) 1759 */ 1760 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1761 __ADC_RESOLUTION__) \ 1762 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1763 (__ADC_RESOLUTION__)) 1764 1765 1766 /** 1767 * @} 1768 */ 1769 1770 /** 1771 * @} 1772 */ 1773 1774 /* Include ADC HAL Extended module */ 1775 #include "stm32n6xx_hal_adc_ex.h" 1776 1777 /* Exported functions --------------------------------------------------------*/ 1778 /** @addtogroup ADC_Exported_Functions 1779 * @{ 1780 */ 1781 1782 /** @addtogroup ADC_Exported_Functions_Group1 1783 * @brief Initialization and Configuration functions 1784 * @{ 1785 */ 1786 /* Initialization and de-initialization functions ****************************/ 1787 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1788 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1789 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1790 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1791 1792 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1793 /* Callbacks Register/UnRegister functions ***********************************/ 1794 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 1795 pADC_CallbackTypeDef pCallback); 1796 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1797 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1798 /** 1799 * @} 1800 */ 1801 1802 /** @addtogroup ADC_Exported_Functions_Group2 1803 * @brief IO operation functions 1804 * @{ 1805 */ 1806 /* IO operation functions *****************************************************/ 1807 1808 /* Blocking mode: Polling */ 1809 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1810 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1811 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1812 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1813 1814 /* Non-blocking mode: Interruption */ 1815 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1816 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1817 1818 /* Non-blocking mode: DMA */ 1819 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length); 1820 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1821 1822 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1823 uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); 1824 int32_t HAL_ADC_GetSignedValue(const ADC_HandleTypeDef *hadc); 1825 1826 /* ADC sampling control */ 1827 HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc); 1828 HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc); 1829 1830 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1831 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1832 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1833 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1834 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1835 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1836 /** 1837 * @} 1838 */ 1839 1840 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1841 * @brief Peripheral Control functions 1842 * @{ 1843 */ 1844 /* Peripheral Control functions ***********************************************/ 1845 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig); 1846 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, 1847 const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); 1848 1849 /** 1850 * @} 1851 */ 1852 1853 /* Peripheral State functions *************************************************/ 1854 /** @addtogroup ADC_Exported_Functions_Group4 1855 * @{ 1856 */ 1857 uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); 1858 uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); 1859 1860 /** 1861 * @} 1862 */ 1863 1864 /** 1865 * @} 1866 */ 1867 1868 /* Private functions -----------------------------------------------------------*/ 1869 /** @addtogroup ADC_Private_Functions ADC Private Functions 1870 * @{ 1871 */ 1872 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 1873 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 1874 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 1875 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 1876 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 1877 void ADC_DMAError(DMA_HandleTypeDef *hdma); 1878 void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc); 1879 1880 /** 1881 * @} 1882 */ 1883 1884 /** 1885 * @} 1886 */ 1887 1888 /** 1889 * @} 1890 */ 1891 1892 #ifdef __cplusplus 1893 } 1894 #endif 1895 1896 #endif /* STM32N6xx_HAL_ADC_H */ 1897
