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Searched refs:ADC_CFGR2_CKMODE_0 (Results 1 – 25 of 70) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_adc.h455 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*…
456 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*…
Dstm32l0xx_hal_adc.h379 #define ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided …
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_adc.h287 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock de…
Dstm32f0xx_ll_adc.h382 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*…
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_adc.h553 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*…
554 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*…
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_adc.h601 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived …
604 … | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_adc.h612 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived …
615 … | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_adc.h612 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived …
615 … | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_adc.h783 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*…
784 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*…
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h701 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
705 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f030x8.h717 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
721 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f070x6.h746 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
750 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f031x6.h711 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
715 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f030xc.h733 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
737 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f038xx.h710 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
714 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f070xb.h769 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
773 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f058xx.h816 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
820 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f051x8.h817 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
821 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f071xb.h851 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
855 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f042x6.h880 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
884 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f048xx.h880 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
884 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f072xb.h955 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
959 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f091xc.h937 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
941 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f098xx.h937 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
941 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Dstm32f078xx.h955 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ macro
959 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */

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