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Searched refs:APB1ENR (Results 1 – 25 of 152) sorted by relevance

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/hal_stm32-3.6.0/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h1316 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
1318 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
1323 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
1325 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
1330 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1332 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1337 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1339 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1344 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1346 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
[all …]
Dstm32f4xx_hal_rcc.h470 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
472 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
477 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
479 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
484 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
486 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
491 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
493 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
498 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
500 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
[all …]
Dstm32f4xx_ll_bus.h1188 SET_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
1190 tmpreg = READ_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
1265 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); in LL_APB1_GRP1_IsEnabledClock()
1339 CLEAR_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_DisableClock()
/hal_stm32-3.6.0/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc_ex.h781 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
783 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
787 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
796 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
798 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
804 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
806 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
812 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
814 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
820 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
[all …]
Dstm32f1xx_hal_rcc.h392 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
394 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
400 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
402 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
408 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
410 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
416 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
418 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
424 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
426 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
[all …]
Dstm32f1xx_ll_bus.h448 SET_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
450 tmpreg = READ_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
513 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); in LL_APB1_GRP1_IsEnabledClock()
575 CLEAR_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_DisableClock()
/hal_stm32-3.6.0/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc_ex.h674 #define __HAL_RCC_USB_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
675 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
677 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN) != 0U)
678 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN) == 0U)
680 #define __HAL_RCC_CRS_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN))
681 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR,(RCC_APB1ENR_CRSEN))
683 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) != 0U)
684 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN) == 0U)
690 #define __HAL_RCC_LCD_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
691 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
[all …]
Dstm32l0xx_hal_rcc.h765 #define __HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
766 #define __HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
768 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
769 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
837 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != 0U)
838 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != 0U)
839 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) == 0U)
840 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) == 0U)
Dstm32l0xx_ll_bus.h441 SET_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
443 tmpreg = READ_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
494 return ((READ_BIT(RCC->APB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_APB1_GRP1_IsEnabledClock()
544 CLEAR_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_DisableClock()
/hal_stm32-3.6.0/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc_ex.h2013 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
2015 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
2020 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2022 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2027 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2029 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2034 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2036 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2040 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
2041 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
[all …]
Dstm32f3xx_hal_rcc.h774 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
776 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
781 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
783 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
788 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
790 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
795 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
797 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
802 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
804 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
[all …]
Dstm32f3xx_ll_bus.h538 SET_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
540 tmpreg = READ_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
605 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); in LL_APB1_GRP1_IsEnabledClock()
669 CLEAR_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_DisableClock()
/hal_stm32-3.6.0/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h656 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
658 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
663 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
665 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
670 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
672 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
677 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
679 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
684 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
686 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
[all …]
Dstm32f2xx_ll_bus.h883 SET_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
885 tmpreg = READ_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
942 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); in LL_APB1_GRP1_IsEnabledClock()
998 CLEAR_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_DisableClock()
/hal_stm32-3.6.0/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc_ex.h1012 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
1014 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
1018 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
1033 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
1035 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
1039 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
1054 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
1056 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
1060 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
1075 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
[all …]
Dstm32f0xx_hal_rcc.h725 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
727 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
732 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
734 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
739 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
741 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
746 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
748 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
753 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
755 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
[all …]
Dstm32f0xx_ll_bus.h416 SET_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
418 tmpreg = READ_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
469 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); in LL_APB1_GRP1_IsEnabledClock()
519 CLEAR_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_DisableClock()
/hal_stm32-3.6.0/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc.h721 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
723 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
728 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
730 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
735 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
737 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
742 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
744 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
749 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
751 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
[all …]
Dstm32l1xx_hal_rcc_ex.h246 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
248 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
251 #define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))
267 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
269 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
272 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
284 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
286 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
289 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
298 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
[all …]
Dstm32l1xx_ll_bus.h532 SET_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
534 tmpreg = READ_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
588 return ((READ_BIT(RCC->APB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL); in LL_APB1_GRP1_IsEnabledClock()
641 CLEAR_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_DisableClock()
/hal_stm32-3.6.0/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h919 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
921 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
927 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
929 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
935 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
937 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
943 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
945 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
951 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
953 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
[all …]
Dstm32f7xx_hal_rcc.h439 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
441 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
447 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
449 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
453 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
454 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
503 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
504 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
506 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
507 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Dstm32f7xx_ll_bus.h1074 SET_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
1076 tmpreg = READ_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
1151 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); in LL_APB1_GRP1_IsEnabledClock()
1225 CLEAR_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_DisableClock()
/hal_stm32-3.6.0/stm32cube/stm32l1xx/soc/
Dsystem_stm32l1xx.c278 RCC->APB1ENR |= RCC_APB1ENR_PWREN; in SystemInit_ExtMemCtl()
281 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); in SystemInit_ExtMemCtl()
/hal_stm32-3.6.0/stm32cube/stm32l0xx/drivers/src/
Dstm32l0xx_hal_rcc_ex.c689 if (READ_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))==RCC_APB1ENR_I2C2EN) in HAL_RCCEx_GetPeriphCLKFreq()

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