1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F1xx_HAL_RCC_EX_H 20 #define __STM32F1xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f1xx_hal_def.h" 28 29 /** @addtogroup STM32F1xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /** @addtogroup RCCEx_Private_Constants 38 * @{ 39 */ 40 41 #if defined(STM32F105xC) || defined(STM32F107xC) 42 43 /* Alias word address of PLLI2SON bit */ 44 #define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos 45 #define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U))) 46 /* Alias word address of PLL2ON bit */ 47 #define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos 48 #define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U))) 49 50 #define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */ 51 #define PLL2_TIMEOUT_VALUE 100U /* 100 ms */ 52 53 #endif /* STM32F105xC || STM32F107xC */ 54 55 56 #define CR_REG_INDEX ((uint8_t)1) 57 58 /** 59 * @} 60 */ 61 62 /** @addtogroup RCCEx_Private_Macros 63 * @{ 64 */ 65 66 #if defined(STM32F105xC) || defined(STM32F107xC) 67 #define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \ 68 ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2)) 69 #endif /* STM32F105xC || STM32F107xC */ 70 71 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 72 || defined(STM32F100xE) 73 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \ 74 ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \ 75 ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \ 76 ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \ 77 ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \ 78 ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \ 79 ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \ 80 ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16)) 81 82 #else 83 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2)) 84 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 85 86 #if defined(STM32F105xC) || defined(STM32F107xC) 87 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ 88 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ 89 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ 90 ((__MUL__) == RCC_PLL_MUL6_5)) 91 92 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ 93 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ 94 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \ 95 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \ 96 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) 97 98 #else 99 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ 100 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ 101 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ 102 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ 103 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ 104 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ 105 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ 106 ((__MUL__) == RCC_PLL_MUL16)) 107 108 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ 109 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ 110 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) 111 112 #endif /* STM32F105xC || STM32F107xC*/ 113 114 #define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \ 115 ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8)) 116 117 #if defined(STM32F105xC) || defined(STM32F107xC) 118 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO)) 119 120 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO)) 121 122 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3)) 123 124 #define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \ 125 ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \ 126 ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \ 127 ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \ 128 ((__MUL__) == RCC_PLLI2S_MUL20)) 129 130 #define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \ 131 ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \ 132 ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \ 133 ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \ 134 ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \ 135 ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \ 136 ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \ 137 ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16)) 138 139 #define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \ 140 ((__PLL__) == RCC_PLL2_ON)) 141 142 #define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \ 143 ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \ 144 ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \ 145 ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \ 146 ((__MUL__) == RCC_PLL2_MUL20)) 147 148 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 149 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 150 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 151 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ 152 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ 153 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 154 155 #elif defined(STM32F103xE) || defined(STM32F103xG) 156 157 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) 158 159 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) 160 161 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 162 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 163 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 164 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ 165 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ 166 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 167 168 169 #elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 170 || defined(STM32F103xB) 171 172 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 173 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 174 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 175 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 176 177 #else 178 179 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 180 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 181 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)) 182 183 #endif /* STM32F105xC || STM32F107xC */ 184 185 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 186 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 187 188 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5)) 189 190 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 191 192 /** 193 * @} 194 */ 195 196 /* Exported types ------------------------------------------------------------*/ 197 198 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 199 * @{ 200 */ 201 202 #if defined(STM32F105xC) || defined(STM32F107xC) 203 /** 204 * @brief RCC PLL2 configuration structure definition 205 */ 206 typedef struct 207 { 208 uint32_t PLL2State; /*!< The new state of the PLL2. 209 This parameter can be a value of @ref RCCEx_PLL2_Config */ 210 211 uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock 212 This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ 213 214 #if defined(STM32F105xC) || defined(STM32F107xC) 215 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. 216 This parameter can be a value of @ref RCCEx_Prediv2_Factor */ 217 218 #endif /* STM32F105xC || STM32F107xC */ 219 } RCC_PLL2InitTypeDef; 220 221 #endif /* STM32F105xC || STM32F107xC */ 222 223 /** 224 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 225 */ 226 typedef struct 227 { 228 uint32_t OscillatorType; /*!< The oscillators to be configured. 229 This parameter can be a value of @ref RCC_Oscillator_Type */ 230 231 #if defined(STM32F105xC) || defined(STM32F107xC) 232 uint32_t Prediv1Source; /*!< The Prediv1 source value. 233 This parameter can be a value of @ref RCCEx_Prediv1_Source */ 234 #endif /* STM32F105xC || STM32F107xC */ 235 236 uint32_t HSEState; /*!< The new state of the HSE. 237 This parameter can be a value of @ref RCC_HSE_Config */ 238 239 uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) 240 This parameter can be a value of @ref RCCEx_Prediv1_Factor */ 241 242 uint32_t LSEState; /*!< The new state of the LSE. 243 This parameter can be a value of @ref RCC_LSE_Config */ 244 245 uint32_t HSIState; /*!< The new state of the HSI. 246 This parameter can be a value of @ref RCC_HSI_Config */ 247 248 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 249 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 250 251 uint32_t LSIState; /*!< The new state of the LSI. 252 This parameter can be a value of @ref RCC_LSI_Config */ 253 254 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 255 256 #if defined(STM32F105xC) || defined(STM32F107xC) 257 RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ 258 #endif /* STM32F105xC || STM32F107xC */ 259 } RCC_OscInitTypeDef; 260 261 #if defined(STM32F105xC) || defined(STM32F107xC) 262 /** 263 * @brief RCC PLLI2S configuration structure definition 264 */ 265 typedef struct 266 { 267 uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock 268 This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ 269 270 #if defined(STM32F105xC) || defined(STM32F107xC) 271 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. 272 This parameter can be a value of @ref RCCEx_Prediv2_Factor */ 273 274 #endif /* STM32F105xC || STM32F107xC */ 275 } RCC_PLLI2SInitTypeDef; 276 #endif /* STM32F105xC || STM32F107xC */ 277 278 /** 279 * @brief RCC extended clocks structure definition 280 */ 281 typedef struct 282 { 283 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 284 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 285 286 uint32_t RTCClockSelection; /*!< specifies the RTC clock source. 287 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 288 289 uint32_t AdcClockSelection; /*!< ADC clock source 290 This parameter can be a value of @ref RCCEx_ADC_Prescaler */ 291 292 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 293 || defined(STM32F107xC) 294 uint32_t I2s2ClockSelection; /*!< I2S2 clock source 295 This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ 296 297 uint32_t I2s3ClockSelection; /*!< I2S3 clock source 298 This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ 299 300 #if defined(STM32F105xC) || defined(STM32F107xC) 301 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters 302 This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ 303 304 #endif /* STM32F105xC || STM32F107xC */ 305 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 306 307 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 308 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 309 || defined(STM32F105xC) || defined(STM32F107xC) 310 uint32_t UsbClockSelection; /*!< USB clock source 311 This parameter can be a value of @ref RCCEx_USB_Prescaler */ 312 313 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 314 } RCC_PeriphCLKInitTypeDef; 315 316 /** 317 * @} 318 */ 319 320 /* Exported constants --------------------------------------------------------*/ 321 322 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 323 * @{ 324 */ 325 326 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 327 * @{ 328 */ 329 #define RCC_PERIPHCLK_RTC 0x00000001U 330 #define RCC_PERIPHCLK_ADC 0x00000002U 331 #if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\ 332 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 333 #define RCC_PERIPHCLK_I2S2 0x00000004U 334 #define RCC_PERIPHCLK_I2S3 0x00000008U 335 #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 336 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 337 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 338 || defined(STM32F105xC) || defined(STM32F107xC) 339 #define RCC_PERIPHCLK_USB 0x00000010U 340 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 341 342 /** 343 * @} 344 */ 345 346 /** @defgroup RCCEx_ADC_Prescaler ADC Prescaler 347 * @{ 348 */ 349 #define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 350 #define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 351 #define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 352 #define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 353 354 /** 355 * @} 356 */ 357 358 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 359 || defined(STM32F107xC) 360 /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source 361 * @{ 362 */ 363 #define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U 364 #if defined(STM32F105xC) || defined(STM32F107xC) 365 #define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC 366 #endif /* STM32F105xC || STM32F107xC */ 367 368 /** 369 * @} 370 */ 371 372 /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source 373 * @{ 374 */ 375 #define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U 376 #if defined(STM32F105xC) || defined(STM32F107xC) 377 #define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC 378 #endif /* STM32F105xC || STM32F107xC */ 379 380 /** 381 * @} 382 */ 383 384 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 385 386 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 387 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 388 389 /** @defgroup RCCEx_USB_Prescaler USB Prescaler 390 * @{ 391 */ 392 #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE 393 #define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U 394 395 /** 396 * @} 397 */ 398 399 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 400 401 402 #if defined(STM32F105xC) || defined(STM32F107xC) 403 /** @defgroup RCCEx_USB_Prescaler USB Prescaler 404 * @{ 405 */ 406 #define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE 407 #define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U 408 409 /** 410 * @} 411 */ 412 413 /** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor 414 * @{ 415 */ 416 417 #define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ 418 #define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ 419 #define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ 420 #define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ 421 #define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ 422 #define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ 423 #define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ 424 #define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ 425 #define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ 426 427 /** 428 * @} 429 */ 430 #endif /* STM32F105xC || STM32F107xC */ 431 432 #if defined(STM32F105xC) || defined(STM32F107xC) 433 /** @defgroup RCCEx_Prediv1_Source Prediv1 Source 434 * @{ 435 */ 436 437 #define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE 438 #define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 439 440 /** 441 * @} 442 */ 443 #endif /* STM32F105xC || STM32F107xC */ 444 445 /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor 446 * @{ 447 */ 448 449 #define RCC_HSE_PREDIV_DIV1 0x00000000U 450 451 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 452 || defined(STM32F100xE) 453 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 454 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 455 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 456 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 457 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 458 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 459 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 460 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 461 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 462 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 463 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 464 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 465 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 466 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 467 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 468 #else 469 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE 470 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 471 472 /** 473 * @} 474 */ 475 476 #if defined(STM32F105xC) || defined(STM32F107xC) 477 /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor 478 * @{ 479 */ 480 481 #define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ 482 #define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ 483 #define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ 484 #define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ 485 #define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ 486 #define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ 487 #define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ 488 #define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ 489 #define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ 490 #define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ 491 #define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ 492 #define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ 493 #define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ 494 #define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ 495 #define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ 496 #define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ 497 498 /** 499 * @} 500 */ 501 502 /** @defgroup RCCEx_PLL2_Config PLL Config 503 * @{ 504 */ 505 #define RCC_PLL2_NONE 0x00000000U 506 #define RCC_PLL2_OFF 0x00000001U 507 #define RCC_PLL2_ON 0x00000002U 508 509 /** 510 * @} 511 */ 512 513 /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor 514 * @{ 515 */ 516 517 #define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ 518 #define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ 519 #define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ 520 #define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ 521 #define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ 522 #define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ 523 #define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ 524 #define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ 525 #define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ 526 527 /** 528 * @} 529 */ 530 531 #endif /* STM32F105xC || STM32F107xC */ 532 533 /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor 534 * @{ 535 */ 536 537 #if defined(STM32F105xC) || defined(STM32F107xC) 538 #else 539 #define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 540 #define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 541 #endif /* STM32F105xC || STM32F107xC */ 542 #define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 543 #define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 544 #define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 545 #define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 546 #define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 547 #define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 548 #if defined(STM32F105xC) || defined(STM32F107xC) 549 #define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 550 #else 551 #define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 552 #define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 553 #define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 554 #define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 555 #define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 556 #define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 557 #define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 558 #endif /* STM32F105xC || STM32F107xC */ 559 560 /** 561 * @} 562 */ 563 564 /** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source 565 * @{ 566 */ 567 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) 568 #define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) 569 #define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) 570 #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) 571 #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2) 572 #if defined(STM32F105xC) || defined(STM32F107xC) 573 #define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK) 574 #define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2) 575 #define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE) 576 #define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK) 577 #endif /* STM32F105xC || STM32F107xC*/ 578 /** 579 * @} 580 */ 581 582 #if defined(STM32F105xC) || defined(STM32F107xC) 583 /** @defgroup RCCEx_Interrupt RCCEx Interrupt 584 * @{ 585 */ 586 #define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF) 587 #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) 588 /** 589 * @} 590 */ 591 592 /** @defgroup RCCEx_Flag RCCEx Flag 593 * Elements values convention: 0XXYYYYYb 594 * - YYYYY : Flag position in the register 595 * - XX : Register index 596 * - 01: CR register 597 * @{ 598 */ 599 /* Flags in the CR register */ 600 #define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) 601 #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) 602 /** 603 * @} 604 */ 605 #endif /* STM32F105xC || STM32F107xC*/ 606 607 /** 608 * @} 609 */ 610 611 /* Exported macro ------------------------------------------------------------*/ 612 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 613 * @{ 614 */ 615 616 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable 617 * @brief Enable or disable the AHB1 peripheral clock. 618 * @note After reset, the peripheral clock (used for registers read/write access) 619 * is disabled and the application software has to enable this clock before 620 * using it. 621 * @{ 622 */ 623 624 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 625 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ 626 || defined (STM32F100xE) 627 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 628 __IO uint32_t tmpreg; \ 629 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 630 /* Delay after an RCC peripheral clock enabling */ \ 631 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 632 UNUSED(tmpreg); \ 633 } while(0U) 634 635 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) 636 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ 637 638 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 639 || defined(STM32F103xG) || defined (STM32F100xE) 640 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 641 __IO uint32_t tmpreg; \ 642 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ 643 /* Delay after an RCC peripheral clock enabling */ \ 644 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ 645 UNUSED(tmpreg); \ 646 } while(0U) 647 648 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) 649 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ 650 651 #if defined(STM32F103xE) || defined(STM32F103xG) 652 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 653 __IO uint32_t tmpreg; \ 654 SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ 655 /* Delay after an RCC peripheral clock enabling */ \ 656 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ 657 UNUSED(tmpreg); \ 658 } while(0U) 659 660 661 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) 662 #endif /* STM32F103xE || STM32F103xG */ 663 664 #if defined(STM32F105xC) || defined(STM32F107xC) 665 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ 666 __IO uint32_t tmpreg; \ 667 SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ 668 /* Delay after an RCC peripheral clock enabling */ \ 669 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ 670 UNUSED(tmpreg); \ 671 } while(0U) 672 673 674 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) 675 #endif /* STM32F105xC || STM32F107xC*/ 676 677 #if defined(STM32F107xC) 678 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 679 __IO uint32_t tmpreg; \ 680 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ 681 /* Delay after an RCC peripheral clock enabling */ \ 682 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ 683 UNUSED(tmpreg); \ 684 } while(0U) 685 686 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 687 __IO uint32_t tmpreg; \ 688 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ 689 /* Delay after an RCC peripheral clock enabling */ \ 690 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ 691 UNUSED(tmpreg); \ 692 } while(0U) 693 694 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 695 __IO uint32_t tmpreg; \ 696 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ 697 /* Delay after an RCC peripheral clock enabling */ \ 698 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ 699 UNUSED(tmpreg); \ 700 } while(0U) 701 702 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) 703 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) 704 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN)) 705 706 /** 707 * @brief Enable ETHERNET clock. 708 */ 709 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 710 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 711 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 712 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 713 } while(0U) 714 /** 715 * @brief Disable ETHERNET clock. 716 */ 717 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 718 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 719 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 720 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 721 } while(0U) 722 723 #endif /* STM32F107xC*/ 724 725 /** 726 * @} 727 */ 728 729 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 730 * @brief Get the enable or disable status of the AHB1 peripheral clock. 731 * @note After reset, the peripheral clock (used for registers read/write access) 732 * is disabled and the application software has to enable this clock before 733 * using it. 734 * @{ 735 */ 736 737 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 738 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ 739 || defined (STM32F100xE) 740 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) 741 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) 742 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ 743 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 744 || defined(STM32F103xG) || defined (STM32F100xE) 745 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) 746 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) 747 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ 748 #if defined(STM32F103xE) || defined(STM32F103xG) 749 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET) 750 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET) 751 #endif /* STM32F103xE || STM32F103xG */ 752 #if defined(STM32F105xC) || defined(STM32F107xC) 753 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET) 754 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET) 755 #endif /* STM32F105xC || STM32F107xC*/ 756 #if defined(STM32F107xC) 757 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET) 758 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET) 759 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET) 760 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET) 761 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET) 762 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET) 763 #endif /* STM32F107xC*/ 764 765 /** 766 * @} 767 */ 768 769 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable 770 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 771 * @note After reset, the peripheral clock (used for registers read/write access) 772 * is disabled and the application software has to enable this clock before 773 * using it. 774 * @{ 775 */ 776 777 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ 778 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) 779 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 780 __IO uint32_t tmpreg; \ 781 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 782 /* Delay after an RCC peripheral clock enabling */ \ 783 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 784 UNUSED(tmpreg); \ 785 } while(0U) 786 787 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 788 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 789 790 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ 791 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ 792 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 793 || defined(STM32F105xC) || defined(STM32F107xC) 794 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 795 __IO uint32_t tmpreg; \ 796 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 797 /* Delay after an RCC peripheral clock enabling */ \ 798 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 799 UNUSED(tmpreg); \ 800 } while(0U) 801 802 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 803 __IO uint32_t tmpreg; \ 804 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 805 /* Delay after an RCC peripheral clock enabling */ \ 806 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 807 UNUSED(tmpreg); \ 808 } while(0U) 809 810 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 811 __IO uint32_t tmpreg; \ 812 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 813 /* Delay after an RCC peripheral clock enabling */ \ 814 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 815 UNUSED(tmpreg); \ 816 } while(0U) 817 818 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 819 __IO uint32_t tmpreg; \ 820 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 821 /* Delay after an RCC peripheral clock enabling */ \ 822 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 823 UNUSED(tmpreg); \ 824 } while(0U) 825 826 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 827 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 828 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 829 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 830 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 831 832 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 833 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 834 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 835 __IO uint32_t tmpreg; \ 836 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 837 /* Delay after an RCC peripheral clock enabling */ \ 838 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 839 UNUSED(tmpreg); \ 840 } while(0U) 841 842 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) 843 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 844 845 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 846 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 847 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 848 __IO uint32_t tmpreg; \ 849 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 850 /* Delay after an RCC peripheral clock enabling */ \ 851 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 852 UNUSED(tmpreg); \ 853 } while(0U) 854 855 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 856 __IO uint32_t tmpreg; \ 857 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 858 /* Delay after an RCC peripheral clock enabling */ \ 859 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 860 UNUSED(tmpreg); \ 861 } while(0U) 862 863 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 864 __IO uint32_t tmpreg; \ 865 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 866 /* Delay after an RCC peripheral clock enabling */ \ 867 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 868 UNUSED(tmpreg); \ 869 } while(0U) 870 871 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 872 __IO uint32_t tmpreg; \ 873 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 874 /* Delay after an RCC peripheral clock enabling */ \ 875 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 876 UNUSED(tmpreg); \ 877 } while(0U) 878 879 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 880 __IO uint32_t tmpreg; \ 881 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 882 /* Delay after an RCC peripheral clock enabling */ \ 883 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 884 UNUSED(tmpreg); \ 885 } while(0U) 886 887 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 888 __IO uint32_t tmpreg; \ 889 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 890 /* Delay after an RCC peripheral clock enabling */ \ 891 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 892 UNUSED(tmpreg); \ 893 } while(0U) 894 895 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 896 __IO uint32_t tmpreg; \ 897 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 898 /* Delay after an RCC peripheral clock enabling */ \ 899 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 900 UNUSED(tmpreg); \ 901 } while(0U) 902 903 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 904 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 905 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 906 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 907 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 908 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 909 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 910 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ 911 912 #if defined(STM32F100xB) || defined (STM32F100xE) 913 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 914 __IO uint32_t tmpreg; \ 915 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 916 /* Delay after an RCC peripheral clock enabling */ \ 917 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 918 UNUSED(tmpreg); \ 919 } while(0U) 920 921 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 922 __IO uint32_t tmpreg; \ 923 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 924 /* Delay after an RCC peripheral clock enabling */ \ 925 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 926 UNUSED(tmpreg); \ 927 } while(0U) 928 929 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 930 __IO uint32_t tmpreg; \ 931 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 932 /* Delay after an RCC peripheral clock enabling */ \ 933 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 934 UNUSED(tmpreg); \ 935 } while(0U) 936 937 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 938 __IO uint32_t tmpreg; \ 939 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 940 /* Delay after an RCC peripheral clock enabling */ \ 941 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 942 UNUSED(tmpreg); \ 943 } while(0U) 944 945 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 946 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 947 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 948 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 949 #endif /* STM32F100xB || STM32F100xE */ 950 951 #ifdef STM32F100xE 952 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 953 __IO uint32_t tmpreg; \ 954 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 955 /* Delay after an RCC peripheral clock enabling */ \ 956 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 957 UNUSED(tmpreg); \ 958 } while(0U) 959 960 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 961 __IO uint32_t tmpreg; \ 962 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 963 /* Delay after an RCC peripheral clock enabling */ \ 964 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 965 UNUSED(tmpreg); \ 966 } while(0U) 967 968 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 969 __IO uint32_t tmpreg; \ 970 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 971 /* Delay after an RCC peripheral clock enabling */ \ 972 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 973 UNUSED(tmpreg); \ 974 } while(0U) 975 976 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 977 __IO uint32_t tmpreg; \ 978 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 979 /* Delay after an RCC peripheral clock enabling */ \ 980 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 981 UNUSED(tmpreg); \ 982 } while(0U) 983 984 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 985 __IO uint32_t tmpreg; \ 986 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 987 /* Delay after an RCC peripheral clock enabling */ \ 988 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 989 UNUSED(tmpreg); \ 990 } while(0U) 991 992 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 993 __IO uint32_t tmpreg; \ 994 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 995 /* Delay after an RCC peripheral clock enabling */ \ 996 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 997 UNUSED(tmpreg); \ 998 } while(0U) 999 1000 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1001 __IO uint32_t tmpreg; \ 1002 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 1003 /* Delay after an RCC peripheral clock enabling */ \ 1004 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 1005 UNUSED(tmpreg); \ 1006 } while(0U) 1007 1008 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 1009 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 1010 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 1011 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 1012 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 1013 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 1014 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 1015 #endif /* STM32F100xE */ 1016 1017 #if defined(STM32F105xC) || defined(STM32F107xC) 1018 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 1019 __IO uint32_t tmpreg; \ 1020 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 1021 /* Delay after an RCC peripheral clock enabling */ \ 1022 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 1023 UNUSED(tmpreg); \ 1024 } while(0U) 1025 1026 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 1027 #endif /* STM32F105xC || STM32F107xC */ 1028 1029 #if defined(STM32F101xG) || defined(STM32F103xG) 1030 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 1031 __IO uint32_t tmpreg; \ 1032 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 1033 /* Delay after an RCC peripheral clock enabling */ \ 1034 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 1035 UNUSED(tmpreg); \ 1036 } while(0U) 1037 1038 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 1039 __IO uint32_t tmpreg; \ 1040 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 1041 /* Delay after an RCC peripheral clock enabling */ \ 1042 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 1043 UNUSED(tmpreg); \ 1044 } while(0U) 1045 1046 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1047 __IO uint32_t tmpreg; \ 1048 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1049 /* Delay after an RCC peripheral clock enabling */ \ 1050 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1051 UNUSED(tmpreg); \ 1052 } while(0U) 1053 1054 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 1055 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 1056 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 1057 #endif /* STM32F101xG || STM32F103xG*/ 1058 1059 /** 1060 * @} 1061 */ 1062 1063 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 1064 * @brief Get the enable or disable status of the APB1 peripheral clock. 1065 * @note After reset, the peripheral clock (used for registers read/write access) 1066 * is disabled and the application software has to enable this clock before 1067 * using it. 1068 * @{ 1069 */ 1070 1071 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ 1072 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) 1073 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 1074 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 1075 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 1076 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ 1077 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ 1078 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 1079 || defined(STM32F105xC) || defined(STM32F107xC) 1080 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 1081 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 1082 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 1083 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 1084 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 1085 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 1086 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 1087 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 1088 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 1089 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 1090 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 1091 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) 1092 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) 1093 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 1094 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 1095 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 1096 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 1097 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 1098 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 1099 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 1100 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 1101 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 1102 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 1103 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 1104 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 1105 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 1106 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 1107 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 1108 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 1109 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 1110 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ 1111 #if defined(STM32F100xB) || defined (STM32F100xE) 1112 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 1113 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 1114 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 1115 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 1116 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 1117 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 1118 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 1119 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 1120 #endif /* STM32F100xB || STM32F100xE */ 1121 #ifdef STM32F100xE 1122 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 1123 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 1124 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 1125 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 1126 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 1127 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 1128 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 1129 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 1130 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 1131 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 1132 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 1133 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 1134 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 1135 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 1136 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 1137 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 1138 #endif /* STM32F100xE */ 1139 #if defined(STM32F105xC) || defined(STM32F107xC) 1140 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 1141 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 1142 #endif /* STM32F105xC || STM32F107xC */ 1143 #if defined(STM32F101xG) || defined(STM32F103xG) 1144 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 1145 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 1146 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 1147 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 1148 #endif /* STM32F101xG || STM32F103xG*/ 1149 1150 /** 1151 * @} 1152 */ 1153 1154 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable 1155 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 1156 * @note After reset, the peripheral clock (used for registers read/write access) 1157 * is disabled and the application software has to enable this clock before 1158 * using it. 1159 * @{ 1160 */ 1161 1162 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ 1163 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ 1164 || defined(STM32F103xG) 1165 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 1166 __IO uint32_t tmpreg; \ 1167 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 1168 /* Delay after an RCC peripheral clock enabling */ \ 1169 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 1170 UNUSED(tmpreg); \ 1171 } while(0U) 1172 1173 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 1174 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ 1175 1176 #if defined(STM32F100xB) || defined(STM32F100xE) 1177 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1178 __IO uint32_t tmpreg; \ 1179 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 1180 /* Delay after an RCC peripheral clock enabling */ \ 1181 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 1182 UNUSED(tmpreg); \ 1183 } while(0U) 1184 1185 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1186 __IO uint32_t tmpreg; \ 1187 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 1188 /* Delay after an RCC peripheral clock enabling */ \ 1189 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 1190 UNUSED(tmpreg); \ 1191 } while(0U) 1192 1193 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1194 __IO uint32_t tmpreg; \ 1195 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 1196 /* Delay after an RCC peripheral clock enabling */ \ 1197 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 1198 UNUSED(tmpreg); \ 1199 } while(0U) 1200 1201 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) 1202 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) 1203 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) 1204 #endif /* STM32F100xB || STM32F100xE */ 1205 1206 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ 1207 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ 1208 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 1209 || defined(STM32F107xC) 1210 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 1211 __IO uint32_t tmpreg; \ 1212 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ 1213 /* Delay after an RCC peripheral clock enabling */ \ 1214 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ 1215 UNUSED(tmpreg); \ 1216 } while(0U) 1217 1218 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) 1219 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 1220 1221 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 1222 || defined(STM32F103xG) 1223 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 1224 __IO uint32_t tmpreg; \ 1225 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 1226 /* Delay after an RCC peripheral clock enabling */ \ 1227 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 1228 UNUSED(tmpreg); \ 1229 } while(0U) 1230 1231 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 1232 __IO uint32_t tmpreg; \ 1233 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 1234 /* Delay after an RCC peripheral clock enabling */ \ 1235 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 1236 UNUSED(tmpreg); \ 1237 } while(0U) 1238 1239 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) 1240 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) 1241 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ 1242 1243 #if defined(STM32F103xE) || defined(STM32F103xG) 1244 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1245 __IO uint32_t tmpreg; \ 1246 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 1247 /* Delay after an RCC peripheral clock enabling */ \ 1248 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 1249 UNUSED(tmpreg); \ 1250 } while(0U) 1251 1252 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 1253 __IO uint32_t tmpreg; \ 1254 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 1255 /* Delay after an RCC peripheral clock enabling */ \ 1256 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 1257 UNUSED(tmpreg); \ 1258 } while(0U) 1259 1260 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 1261 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 1262 #endif /* STM32F103xE || STM32F103xG */ 1263 1264 #if defined(STM32F100xE) 1265 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 1266 __IO uint32_t tmpreg; \ 1267 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 1268 /* Delay after an RCC peripheral clock enabling */ \ 1269 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 1270 UNUSED(tmpreg); \ 1271 } while(0U) 1272 1273 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 1274 __IO uint32_t tmpreg; \ 1275 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 1276 /* Delay after an RCC peripheral clock enabling */ \ 1277 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 1278 UNUSED(tmpreg); \ 1279 } while(0U) 1280 1281 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) 1282 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) 1283 #endif /* STM32F100xE */ 1284 1285 #if defined(STM32F101xG) || defined(STM32F103xG) 1286 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ 1287 __IO uint32_t tmpreg; \ 1288 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 1289 /* Delay after an RCC peripheral clock enabling */ \ 1290 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 1291 UNUSED(tmpreg); \ 1292 } while(0U) 1293 1294 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 1295 __IO uint32_t tmpreg; \ 1296 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 1297 /* Delay after an RCC peripheral clock enabling */ \ 1298 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 1299 UNUSED(tmpreg); \ 1300 } while(0U) 1301 1302 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ 1303 __IO uint32_t tmpreg; \ 1304 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 1305 /* Delay after an RCC peripheral clock enabling */ \ 1306 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 1307 UNUSED(tmpreg); \ 1308 } while(0U) 1309 1310 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) 1311 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 1312 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) 1313 #endif /* STM32F101xG || STM32F103xG */ 1314 1315 /** 1316 * @} 1317 */ 1318 1319 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 1320 * @brief Get the enable or disable status of the APB2 peripheral clock. 1321 * @note After reset, the peripheral clock (used for registers read/write access) 1322 * is disabled and the application software has to enable this clock before 1323 * using it. 1324 * @{ 1325 */ 1326 1327 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ 1328 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ 1329 || defined(STM32F103xG) 1330 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 1331 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 1332 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ 1333 #if defined(STM32F100xB) || defined(STM32F100xE) 1334 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) 1335 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) 1336 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) 1337 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) 1338 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) 1339 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) 1340 #endif /* STM32F100xB || STM32F100xE */ 1341 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ 1342 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ 1343 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 1344 || defined(STM32F107xC) 1345 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET) 1346 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET) 1347 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 1348 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 1349 || defined(STM32F103xG) 1350 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) 1351 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) 1352 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) 1353 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) 1354 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ 1355 #if defined(STM32F103xE) || defined(STM32F103xG) 1356 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 1357 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 1358 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 1359 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 1360 #endif /* STM32F103xE || STM32F103xG */ 1361 #if defined(STM32F100xE) 1362 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) 1363 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) 1364 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) 1365 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) 1366 #endif /* STM32F100xE */ 1367 #if defined(STM32F101xG) || defined(STM32F103xG) 1368 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) 1369 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) 1370 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 1371 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 1372 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) 1373 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) 1374 #endif /* STM32F101xG || STM32F103xG */ 1375 1376 /** 1377 * @} 1378 */ 1379 1380 #if defined(STM32F105xC) || defined(STM32F107xC) 1381 /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release 1382 * @brief Force or release AHB peripheral reset. 1383 * @{ 1384 */ 1385 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) 1386 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) 1387 #if defined(STM32F107xC) 1388 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST)) 1389 #endif /* STM32F107xC */ 1390 1391 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) 1392 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST)) 1393 #if defined(STM32F107xC) 1394 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST)) 1395 #endif /* STM32F107xC */ 1396 1397 /** 1398 * @} 1399 */ 1400 #endif /* STM32F105xC || STM32F107xC */ 1401 1402 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 1403 * @brief Force or release APB1 peripheral reset. 1404 * @{ 1405 */ 1406 1407 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ 1408 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) 1409 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 1410 1411 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 1412 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 1413 1414 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ 1415 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ 1416 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 1417 || defined(STM32F105xC) || defined(STM32F107xC) 1418 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 1419 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 1420 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 1421 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 1422 1423 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 1424 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 1425 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 1426 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 1427 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 1428 1429 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 1430 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 1431 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) 1432 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) 1433 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 1434 1435 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 1436 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 1437 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 1438 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 1439 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 1440 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 1441 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 1442 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 1443 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 1444 1445 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 1446 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 1447 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 1448 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 1449 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 1450 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 1451 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 1452 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ 1453 1454 #if defined(STM32F100xB) || defined (STM32F100xE) 1455 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 1456 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 1457 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 1458 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 1459 1460 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 1461 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 1462 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 1463 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 1464 #endif /* STM32F100xB || STM32F100xE */ 1465 1466 #if defined (STM32F100xE) 1467 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 1468 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 1469 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 1470 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 1471 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 1472 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 1473 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 1474 1475 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 1476 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 1477 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 1478 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 1479 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 1480 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 1481 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 1482 #endif /* STM32F100xE */ 1483 1484 #if defined(STM32F105xC) || defined(STM32F107xC) 1485 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 1486 1487 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 1488 #endif /* STM32F105xC || STM32F107xC */ 1489 1490 #if defined(STM32F101xG) || defined(STM32F103xG) 1491 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 1492 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 1493 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 1494 1495 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 1496 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 1497 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 1498 #endif /* STM32F101xG || STM32F103xG */ 1499 1500 /** 1501 * @} 1502 */ 1503 1504 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 1505 * @brief Force or release APB2 peripheral reset. 1506 * @{ 1507 */ 1508 1509 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ 1510 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ 1511 || defined(STM32F103xG) 1512 #define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST)) 1513 1514 #define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST)) 1515 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ 1516 1517 #if defined(STM32F100xB) || defined(STM32F100xE) 1518 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) 1519 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) 1520 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) 1521 1522 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) 1523 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) 1524 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) 1525 #endif /* STM32F100xB || STM32F100xE */ 1526 1527 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ 1528 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ 1529 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 1530 || defined(STM32F107xC) 1531 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST)) 1532 1533 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST)) 1534 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 1535 1536 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 1537 || defined(STM32F103xG) 1538 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) 1539 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) 1540 1541 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) 1542 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) 1543 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ 1544 1545 #if defined(STM32F103xE) || defined(STM32F103xG) 1546 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 1547 #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST)) 1548 1549 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 1550 #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST)) 1551 #endif /* STM32F103xE || STM32F103xG */ 1552 1553 #if defined(STM32F100xE) 1554 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) 1555 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) 1556 1557 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) 1558 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) 1559 #endif /* STM32F100xE */ 1560 1561 #if defined(STM32F101xG) || defined(STM32F103xG) 1562 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) 1563 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 1564 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) 1565 1566 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) 1567 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 1568 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) 1569 #endif /* STM32F101xG || STM32F103xG*/ 1570 1571 /** 1572 * @} 1573 */ 1574 1575 /** @defgroup RCCEx_HSE_Configuration HSE Configuration 1576 * @{ 1577 */ 1578 1579 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 1580 || defined(STM32F100xE) 1581 /** 1582 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. 1583 * @note Predivision factor can not be changed if PLL is used as system clock 1584 * In this case, you have to select another source of the system clock, disable the PLL and 1585 * then change the HSE predivision factor. 1586 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. 1587 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. 1588 */ 1589 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__)) 1590 #else 1591 /** 1592 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. 1593 * @note Predivision factor can not be changed if PLL is used as system clock 1594 * In this case, you have to select another source of the system clock, disable the PLL and 1595 * then change the HSE predivision factor. 1596 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. 1597 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2. 1598 */ 1599 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ 1600 MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__)) 1601 1602 #endif /* STM32F105xC || STM32F107xC */ 1603 1604 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 1605 || defined(STM32F100xE) 1606 /** 1607 * @brief Macro to get prediv1 factor for PLL. 1608 */ 1609 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1) 1610 1611 #else 1612 /** 1613 * @brief Macro to get prediv1 factor for PLL. 1614 */ 1615 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) 1616 1617 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 1618 1619 /** 1620 * @} 1621 */ 1622 1623 #if defined(STM32F105xC) || defined(STM32F107xC) 1624 /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration 1625 * @{ 1626 */ 1627 1628 /** @brief Macros to enable the main PLLI2S. 1629 * @note After enabling the main PLLI2S, the application software should wait on 1630 * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can 1631 * be used as system clock source. 1632 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 1633 */ 1634 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) 1635 1636 /** @brief Macros to disable the main PLLI2S. 1637 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 1638 */ 1639 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) 1640 1641 /** @brief macros to configure the main PLLI2S multiplication factor. 1642 * @note This function must be used only when the main PLLI2S is disabled. 1643 * 1644 * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock 1645 * This parameter can be one of the following values: 1646 * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 1647 * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9 1648 * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10 1649 * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11 1650 * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12 1651 * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13 1652 * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 1653 * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 1654 * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 1655 * 1656 */ 1657 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\ 1658 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__)) 1659 1660 /** 1661 * @} 1662 */ 1663 1664 #endif /* STM32F105xC || STM32F107xC */ 1665 1666 /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration 1667 * @brief Macros to configure clock source of different peripherals. 1668 * @{ 1669 */ 1670 1671 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 1672 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 1673 /** @brief Macro to configure the USB clock. 1674 * @param __USBCLKSOURCE__ specifies the USB clock source. 1675 * This parameter can be one of the following values: 1676 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock 1677 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock 1678 */ 1679 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ 1680 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__)) 1681 1682 /** @brief Macro to get the USB clock (USBCLK). 1683 * @retval The clock source can be one of the following values: 1684 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock 1685 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock 1686 */ 1687 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) 1688 1689 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 1690 1691 #if defined(STM32F105xC) || defined(STM32F107xC) 1692 1693 /** @brief Macro to configure the USB OTSclock. 1694 * @param __USBCLKSOURCE__ specifies the USB clock source. 1695 * This parameter can be one of the following values: 1696 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock 1697 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock 1698 */ 1699 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ 1700 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__)) 1701 1702 /** @brief Macro to get the USB clock (USBCLK). 1703 * @retval The clock source can be one of the following values: 1704 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock 1705 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock 1706 */ 1707 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE))) 1708 1709 #endif /* STM32F105xC || STM32F107xC */ 1710 1711 /** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices). 1712 * @param __ADCCLKSOURCE__ specifies the ADC clock source. 1713 * This parameter can be one of the following values: 1714 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock 1715 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock 1716 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock 1717 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock 1718 */ 1719 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \ 1720 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__)) 1721 1722 /** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices). 1723 * @retval The clock source can be one of the following values: 1724 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock 1725 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock 1726 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock 1727 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock 1728 */ 1729 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) 1730 1731 /** 1732 * @} 1733 */ 1734 1735 #if defined(STM32F105xC) || defined(STM32F107xC) 1736 1737 /** @addtogroup RCCEx_HSE_Configuration 1738 * @{ 1739 */ 1740 1741 /** 1742 * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. 1743 * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock 1744 * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and 1745 * then change the PREDIV2 factor. 1746 * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S. 1747 * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16. 1748 */ 1749 #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \ 1750 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) 1751 1752 /** 1753 * @brief Macro to get prediv2 factor for PLL2 & PLL3. 1754 */ 1755 #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2) 1756 1757 /** 1758 * @} 1759 */ 1760 1761 /** @addtogroup RCCEx_PLLI2S_Configuration 1762 * @{ 1763 */ 1764 1765 /** @brief Macros to enable the main PLL2. 1766 * @note After enabling the main PLL2, the application software should wait on 1767 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 1768 * be used as system clock source. 1769 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. 1770 */ 1771 #define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE) 1772 1773 /** @brief Macros to disable the main PLL2. 1774 * @note The main PLL2 can not be disabled if it is used indirectly as system clock source 1775 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. 1776 */ 1777 #define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE) 1778 1779 /** @brief macros to configure the main PLL2 multiplication factor. 1780 * @note This function must be used only when the main PLL2 is disabled. 1781 * 1782 * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock 1783 * This parameter can be one of the following values: 1784 * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 1785 * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9 1786 * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10 1787 * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11 1788 * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12 1789 * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13 1790 * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 1791 * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 1792 * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 1793 * 1794 */ 1795 #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\ 1796 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__)) 1797 1798 /** 1799 * @} 1800 */ 1801 1802 /** @defgroup RCCEx_I2S_Configuration I2S Configuration 1803 * @brief Macros to configure clock source of I2S peripherals. 1804 * @{ 1805 */ 1806 1807 /** @brief Macro to configure the I2S2 clock. 1808 * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. 1809 * This parameter can be one of the following values: 1810 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 1811 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 1812 */ 1813 #define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \ 1814 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__)) 1815 1816 /** @brief Macro to get the I2S2 clock (I2S2CLK). 1817 * @retval The clock source can be one of the following values: 1818 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 1819 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 1820 */ 1821 #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC))) 1822 1823 /** @brief Macro to configure the I2S3 clock. 1824 * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source. 1825 * This parameter can be one of the following values: 1826 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 1827 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 1828 */ 1829 #define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \ 1830 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__)) 1831 1832 /** @brief Macro to get the I2S3 clock (I2S3CLK). 1833 * @retval The clock source can be one of the following values: 1834 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 1835 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 1836 */ 1837 #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC))) 1838 1839 /** 1840 * @} 1841 */ 1842 1843 #endif /* STM32F105xC || STM32F107xC */ 1844 /** 1845 * @} 1846 */ 1847 1848 /* Exported functions --------------------------------------------------------*/ 1849 /** @addtogroup RCCEx_Exported_Functions 1850 * @{ 1851 */ 1852 1853 /** @addtogroup RCCEx_Exported_Functions_Group1 1854 * @{ 1855 */ 1856 1857 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1858 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1859 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1860 1861 /** 1862 * @} 1863 */ 1864 1865 #if defined(STM32F105xC) || defined(STM32F107xC) 1866 /** @addtogroup RCCEx_Exported_Functions_Group2 1867 * @{ 1868 */ 1869 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); 1870 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); 1871 1872 /** 1873 * @} 1874 */ 1875 1876 /** @addtogroup RCCEx_Exported_Functions_Group3 1877 * @{ 1878 */ 1879 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); 1880 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); 1881 1882 /** 1883 * @} 1884 */ 1885 #endif /* STM32F105xC || STM32F107xC */ 1886 1887 /** 1888 * @} 1889 */ 1890 1891 /** 1892 * @} 1893 */ 1894 1895 /** 1896 * @} 1897 */ 1898 1899 #ifdef __cplusplus 1900 } 1901 #endif 1902 1903 #endif /* __STM32F1xx_HAL_RCC_EX_H */ 1904 1905 1906
