1 /** 2 ****************************************************************************** 3 * @file stm32f3xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F3xx_HAL_RCC_H 20 #define __STM32F3xx_HAL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f3xx_hal_def.h" 28 29 /** @addtogroup STM32F3xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCC 34 * @{ 35 */ 36 37 /** @addtogroup RCC_Private_Constants 38 * @{ 39 */ 40 41 /** @defgroup RCC_Timeout RCC Timeout 42 * @{ 43 */ 44 45 /* Disable Backup domain write protection state change timeout */ 46 #define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ 47 /* LSE state change timeout */ 48 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 49 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ 50 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 51 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ 52 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ 53 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ 54 /** 55 * @} 56 */ 57 58 /** @defgroup RCC_Register_Offset Register offsets 59 * @{ 60 */ 61 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 62 #define RCC_CR_OFFSET 0x00 63 #define RCC_CFGR_OFFSET 0x04 64 #define RCC_CIR_OFFSET 0x08 65 #define RCC_BDCR_OFFSET 0x20 66 #define RCC_CSR_OFFSET 0x24 67 68 /** 69 * @} 70 */ 71 72 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion 73 * @brief RCC registers bit address in the alias region 74 * @{ 75 */ 76 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) 77 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) 78 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) 79 #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) 80 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) 81 82 /* --- CR Register ---*/ 83 /* Alias word address of HSION bit */ 84 #define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION) 85 #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) 86 /* Alias word address of HSEON bit */ 87 #define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON) 88 #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) 89 /* Alias word address of CSSON bit */ 90 #define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON) 91 #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) 92 /* Alias word address of PLLON bit */ 93 #define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON) 94 #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) 95 96 /* --- CSR Register ---*/ 97 /* Alias word address of LSION bit */ 98 #define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION) 99 #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) 100 101 /* Alias word address of RMVF bit */ 102 #define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF) 103 #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) 104 105 /* --- BDCR Registers ---*/ 106 /* Alias word address of LSEON bit */ 107 #define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON) 108 #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) 109 110 /* Alias word address of LSEON bit */ 111 #define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP) 112 #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) 113 114 /* Alias word address of RTCEN bit */ 115 #define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN) 116 #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) 117 118 /* Alias word address of BDRST bit */ 119 #define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST) 120 #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) 121 122 /** 123 * @} 124 */ 125 126 /* CR register byte 2 (Bits[23:16]) base address */ 127 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) 128 129 /* CIR register byte 1 (Bits[15:8]) base address */ 130 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) 131 132 /* CIR register byte 2 (Bits[23:16]) base address */ 133 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) 134 135 /* Defines used for Flags */ 136 #define CR_REG_INDEX ((uint8_t)1U) 137 #define BDCR_REG_INDEX ((uint8_t)2U) 138 #define CSR_REG_INDEX ((uint8_t)3U) 139 #define CFGR_REG_INDEX ((uint8_t)4U) 140 141 #define RCC_FLAG_MASK ((uint8_t)0x1FU) 142 143 /** 144 * @} 145 */ 146 147 /** @addtogroup RCC_Private_Macros 148 * @{ 149 */ 150 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 151 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 152 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 153 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 154 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 155 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 156 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 157 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 158 ((__HSE__) == RCC_HSE_BYPASS)) 159 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 160 ((__LSE__) == RCC_LSE_BYPASS)) 161 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 162 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) 163 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 164 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ 165 ((__PLL__) == RCC_PLL_ON)) 166 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) 167 #define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \ 168 ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \ 169 ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \ 170 ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \ 171 ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \ 172 ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \ 173 ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \ 174 ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16)) 175 #else 176 #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ 177 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) 178 #endif 179 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) 180 #define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \ 181 ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \ 182 ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \ 183 ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \ 184 ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \ 185 ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \ 186 ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \ 187 ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16)) 188 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ 189 190 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ 191 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ 192 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ 193 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ 194 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ 195 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ 196 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ 197 ((__MUL__) == RCC_PLL_MUL16)) 198 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ 199 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ 200 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ 201 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) 202 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 203 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 204 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 205 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ 206 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ 207 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) 208 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 209 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 210 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 211 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 212 ((__HCLK__) == RCC_SYSCLK_DIV512)) 213 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 214 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 215 ((__PCLK__) == RCC_HCLK_DIV16)) 216 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) 217 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ 218 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 219 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 220 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 221 #if defined(RCC_CFGR3_USART2SW) 222 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 223 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 224 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 225 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 226 #endif /* RCC_CFGR3_USART2SW */ 227 #if defined(RCC_CFGR3_USART3SW) 228 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 229 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ 230 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ 231 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) 232 #endif /* RCC_CFGR3_USART3SW */ 233 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ 234 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)) 235 236 /** 237 * @} 238 */ 239 240 /* Exported types ------------------------------------------------------------*/ 241 242 /** @defgroup RCC_Exported_Types RCC Exported Types 243 * @{ 244 */ 245 246 /** 247 * @brief RCC PLL configuration structure definition 248 */ 249 typedef struct 250 { 251 uint32_t PLLState; /*!< PLLState: The new state of the PLL. 252 This parameter can be a value of @ref RCC_PLL_Config */ 253 254 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. 255 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 256 257 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock 258 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ 259 260 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) 261 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock 262 This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ 263 264 #endif 265 } RCC_PLLInitTypeDef; 266 267 /** 268 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 269 */ 270 typedef struct 271 { 272 uint32_t OscillatorType; /*!< The oscillators to be configured. 273 This parameter can be a value of @ref RCC_Oscillator_Type */ 274 275 uint32_t HSEState; /*!< The new state of the HSE. 276 This parameter can be a value of @ref RCC_HSE_Config */ 277 278 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) 279 uint32_t HSEPredivValue; /*!< The HSE predivision factor value. 280 This parameter can be a value of @ref RCC_PLL_HSE_Prediv_Factor */ 281 282 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ 283 uint32_t LSEState; /*!< The new state of the LSE. 284 This parameter can be a value of @ref RCC_LSE_Config */ 285 286 uint32_t HSIState; /*!< The new state of the HSI. 287 This parameter can be a value of @ref RCC_HSI_Config */ 288 289 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 290 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ 291 292 uint32_t LSIState; /*!< The new state of the LSI. 293 This parameter can be a value of @ref RCC_LSI_Config */ 294 295 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 296 297 } RCC_OscInitTypeDef; 298 299 /** 300 * @brief RCC System, AHB and APB busses clock configuration structure definition 301 */ 302 typedef struct 303 { 304 uint32_t ClockType; /*!< The clock to be configured. 305 This parameter can be a value of @ref RCC_System_Clock_Type */ 306 307 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 308 This parameter can be a value of @ref RCC_System_Clock_Source */ 309 310 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 311 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 312 313 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 314 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 315 316 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 317 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 318 } RCC_ClkInitTypeDef; 319 320 /** 321 * @} 322 */ 323 324 /* Exported constants --------------------------------------------------------*/ 325 /** @defgroup RCC_Exported_Constants RCC Exported Constants 326 * @{ 327 */ 328 329 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 330 * @{ 331 */ 332 333 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) 334 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI clock selected as PLL entry clock source */ 335 #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ 336 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) 337 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ 338 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ 339 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */ 340 341 /** 342 * @} 343 */ 344 345 /** @defgroup RCC_Oscillator_Type Oscillator Type 346 * @{ 347 */ 348 #define RCC_OSCILLATORTYPE_NONE (0x00000000U) 349 #define RCC_OSCILLATORTYPE_HSE (0x00000001U) 350 #define RCC_OSCILLATORTYPE_HSI (0x00000002U) 351 #define RCC_OSCILLATORTYPE_LSE (0x00000004U) 352 #define RCC_OSCILLATORTYPE_LSI (0x00000008U) 353 /** 354 * @} 355 */ 356 357 /** @defgroup RCC_HSE_Config HSE Config 358 * @{ 359 */ 360 #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ 361 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 362 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 363 /** 364 * @} 365 */ 366 367 /** @defgroup RCC_LSE_Config LSE Config 368 * @{ 369 */ 370 #define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ 371 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 372 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 373 374 /** 375 * @} 376 */ 377 378 /** @defgroup RCC_HSI_Config HSI Config 379 * @{ 380 */ 381 #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ 382 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 383 384 #define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ 385 386 /** 387 * @} 388 */ 389 390 /** @defgroup RCC_LSI_Config LSI Config 391 * @{ 392 */ 393 #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ 394 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 395 396 /** 397 * @} 398 */ 399 400 /** @defgroup RCC_PLL_Config PLL Config 401 * @{ 402 */ 403 #define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ 404 #define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ 405 #define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ 406 407 /** 408 * @} 409 */ 410 411 /** @defgroup RCC_System_Clock_Type System Clock Type 412 * @{ 413 */ 414 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ 415 #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ 416 #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ 417 #define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */ 418 419 /** 420 * @} 421 */ 422 423 /** @defgroup RCC_System_Clock_Source System Clock Source 424 * @{ 425 */ 426 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ 427 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ 428 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ 429 430 /** 431 * @} 432 */ 433 434 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 435 * @{ 436 */ 437 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 438 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 439 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 440 441 /** 442 * @} 443 */ 444 445 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 446 * @{ 447 */ 448 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 449 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 450 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 451 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 452 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 453 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 454 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 455 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 456 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 457 458 /** 459 * @} 460 */ 461 462 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 463 * @{ 464 */ 465 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 466 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 467 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 468 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 469 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 470 471 /** 472 * @} 473 */ 474 475 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 476 * @{ 477 */ 478 #define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK /*!< No clock */ 479 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ 480 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ 481 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor 487 * @{ 488 */ 489 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 490 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 491 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 492 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 493 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 494 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 495 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 496 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 497 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 498 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 499 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 500 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 501 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 502 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 503 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 504 505 /** 506 * @} 507 */ 508 509 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) 510 /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor 511 * @{ 512 */ 513 514 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 515 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 516 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 517 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 518 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 519 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 520 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 521 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 522 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 523 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 524 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 525 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 526 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 527 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 528 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 529 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 530 531 /** 532 * @} 533 */ 534 535 #endif 536 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) 537 /** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor 538 * @{ 539 */ 540 541 #define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 542 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 543 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 544 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 545 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 546 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 547 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 548 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 549 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 550 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 551 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 552 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 553 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 554 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 555 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 556 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 557 558 /** 559 * @} 560 */ 561 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ 562 563 #if defined(RCC_CFGR3_USART2SW) 564 /** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source 565 * @{ 566 */ 567 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK 568 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK 569 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE 570 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI 571 572 /** 573 * @} 574 */ 575 #endif /* RCC_CFGR3_USART2SW */ 576 577 #if defined(RCC_CFGR3_USART3SW) 578 /** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source 579 * @{ 580 */ 581 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK 582 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK 583 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE 584 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI 585 586 /** 587 * @} 588 */ 589 #endif /* RCC_CFGR3_USART3SW */ 590 591 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source 592 * @{ 593 */ 594 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI 595 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK 596 597 /** 598 * @} 599 */ 600 /** @defgroup RCC_MCO_Index MCO Index 601 * @{ 602 */ 603 #define RCC_MCO1 (0x00000000U) 604 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 605 606 /** 607 * @} 608 */ 609 610 /** @defgroup RCC_Interrupt Interrupts 611 * @{ 612 */ 613 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ 614 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ 615 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ 616 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ 617 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ 618 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ 619 /** 620 * @} 621 */ 622 623 /** @defgroup RCC_Flag Flags 624 * Elements values convention: XXXYYYYYb 625 * - YYYYY : Flag position in the register 626 * - XXX : Register index 627 * - 001: CR register 628 * - 010: BDCR register 629 * - 011: CSR register 630 * - 100: CFGR register 631 * @{ 632 */ 633 /* Flags in the CR register */ 634 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */ 635 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */ 636 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */ 637 638 /* Flags in the CSR register */ 639 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */ 640 #if defined(RCC_CSR_V18PWRRSTF) 641 #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF))) 642 #endif 643 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */ 644 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ 645 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */ 646 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ 647 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ 648 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ 649 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ 650 651 /* Flags in the BDCR register */ 652 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */ 653 654 /* Flags in the CFGR register */ 655 #if defined(RCC_CFGR_MCOF) 656 #define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5U) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */ 657 #endif /* RCC_CFGR_MCOF */ 658 659 /** 660 * @} 661 */ 662 663 /** 664 * @} 665 */ 666 667 /* Exported macro ------------------------------------------------------------*/ 668 669 /** @defgroup RCC_Exported_Macros RCC Exported Macros 670 * @{ 671 */ 672 673 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable 674 * @brief Enable or disable the AHB peripheral clock. 675 * @note After reset, the peripheral clock (used for registers read/write access) 676 * is disabled and the application software has to enable this clock before 677 * using it. 678 * @{ 679 */ 680 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 681 __IO uint32_t tmpreg; \ 682 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ 683 /* Delay after an RCC peripheral clock enabling */ \ 684 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ 685 UNUSED(tmpreg); \ 686 } while(0U) 687 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 688 __IO uint32_t tmpreg; \ 689 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ 690 /* Delay after an RCC peripheral clock enabling */ \ 691 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ 692 UNUSED(tmpreg); \ 693 } while(0U) 694 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 695 __IO uint32_t tmpreg; \ 696 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ 697 /* Delay after an RCC peripheral clock enabling */ \ 698 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ 699 UNUSED(tmpreg); \ 700 } while(0U) 701 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 702 __IO uint32_t tmpreg; \ 703 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ 704 /* Delay after an RCC peripheral clock enabling */ \ 705 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ 706 UNUSED(tmpreg); \ 707 } while(0U) 708 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 709 __IO uint32_t tmpreg; \ 710 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ 711 /* Delay after an RCC peripheral clock enabling */ \ 712 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ 713 UNUSED(tmpreg); \ 714 } while(0U) 715 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 716 __IO uint32_t tmpreg; \ 717 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 718 /* Delay after an RCC peripheral clock enabling */ \ 719 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 720 UNUSED(tmpreg); \ 721 } while(0U) 722 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 723 __IO uint32_t tmpreg; \ 724 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 725 /* Delay after an RCC peripheral clock enabling */ \ 726 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 727 UNUSED(tmpreg); \ 728 } while(0U) 729 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ 730 __IO uint32_t tmpreg; \ 731 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 732 /* Delay after an RCC peripheral clock enabling */ \ 733 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 734 UNUSED(tmpreg); \ 735 } while(0U) 736 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ 737 __IO uint32_t tmpreg; \ 738 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 739 /* Delay after an RCC peripheral clock enabling */ \ 740 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 741 UNUSED(tmpreg); \ 742 } while(0U) 743 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 744 __IO uint32_t tmpreg; \ 745 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ 746 /* Delay after an RCC peripheral clock enabling */ \ 747 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ 748 UNUSED(tmpreg); \ 749 } while(0U) 750 751 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) 752 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) 753 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) 754 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) 755 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) 756 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) 757 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) 758 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) 759 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) 760 #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) 761 /** 762 * @} 763 */ 764 765 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable 766 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 767 * @note After reset, the peripheral clock (used for registers read/write access) 768 * is disabled and the application software has to enable this clock before 769 * using it. 770 * @{ 771 */ 772 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 773 __IO uint32_t tmpreg; \ 774 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 775 /* Delay after an RCC peripheral clock enabling */ \ 776 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 777 UNUSED(tmpreg); \ 778 } while(0U) 779 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 780 __IO uint32_t tmpreg; \ 781 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 782 /* Delay after an RCC peripheral clock enabling */ \ 783 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 784 UNUSED(tmpreg); \ 785 } while(0U) 786 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 787 __IO uint32_t tmpreg; \ 788 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 789 /* Delay after an RCC peripheral clock enabling */ \ 790 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 791 UNUSED(tmpreg); \ 792 } while(0U) 793 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 794 __IO uint32_t tmpreg; \ 795 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 796 /* Delay after an RCC peripheral clock enabling */ \ 797 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 798 UNUSED(tmpreg); \ 799 } while(0U) 800 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 801 __IO uint32_t tmpreg; \ 802 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 803 /* Delay after an RCC peripheral clock enabling */ \ 804 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 805 UNUSED(tmpreg); \ 806 } while(0U) 807 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 808 __IO uint32_t tmpreg; \ 809 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 810 /* Delay after an RCC peripheral clock enabling */ \ 811 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 812 UNUSED(tmpreg); \ 813 } while(0U) 814 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 815 __IO uint32_t tmpreg; \ 816 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 817 /* Delay after an RCC peripheral clock enabling */ \ 818 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 819 UNUSED(tmpreg); \ 820 } while(0U) 821 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 822 __IO uint32_t tmpreg; \ 823 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\ 824 /* Delay after an RCC peripheral clock enabling */ \ 825 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\ 826 UNUSED(tmpreg); \ 827 } while(0U) 828 829 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 830 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 831 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) 832 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) 833 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 834 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) 835 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 836 #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN)) 837 /** 838 * @} 839 */ 840 841 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable 842 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 843 * @note After reset, the peripheral clock (used for registers read/write access) 844 * is disabled and the application software has to enable this clock before 845 * using it. 846 * @{ 847 */ 848 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 849 __IO uint32_t tmpreg; \ 850 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 851 /* Delay after an RCC peripheral clock enabling */ \ 852 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 853 UNUSED(tmpreg); \ 854 } while(0U) 855 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 856 __IO uint32_t tmpreg; \ 857 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 858 /* Delay after an RCC peripheral clock enabling */ \ 859 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 860 UNUSED(tmpreg); \ 861 } while(0U) 862 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 863 __IO uint32_t tmpreg; \ 864 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 865 /* Delay after an RCC peripheral clock enabling */ \ 866 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 867 UNUSED(tmpreg); \ 868 } while(0U) 869 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 870 __IO uint32_t tmpreg; \ 871 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 872 /* Delay after an RCC peripheral clock enabling */ \ 873 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 874 UNUSED(tmpreg); \ 875 } while(0U) 876 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 877 __IO uint32_t tmpreg; \ 878 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 879 /* Delay after an RCC peripheral clock enabling */ \ 880 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 881 UNUSED(tmpreg); \ 882 } while(0U) 883 884 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) 885 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) 886 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) 887 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) 888 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) 889 /** 890 * @} 891 */ 892 893 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status 894 * @brief Get the enable or disable status of the AHB peripheral clock. 895 * @note After reset, the peripheral clock (used for registers read/write access) 896 * is disabled and the application software has to enable this clock before 897 * using it. 898 * @{ 899 */ 900 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) 901 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) 902 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) 903 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) 904 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) 905 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) 906 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) 907 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) 908 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) 909 #define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) 910 911 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) 912 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) 913 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) 914 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) 915 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) 916 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) 917 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) 918 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) 919 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) 920 #define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) 921 /** 922 * @} 923 */ 924 925 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 926 * @brief Get the enable or disable status of the APB1 peripheral clock. 927 * @note After reset, the peripheral clock (used for registers read/write access) 928 * is disabled and the application software has to enable this clock before 929 * using it. 930 * @{ 931 */ 932 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 933 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 934 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) 935 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) 936 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 937 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) 938 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) 939 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) 940 941 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 942 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 943 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) 944 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) 945 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 946 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) 947 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) 948 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) 949 /** 950 * @} 951 */ 952 953 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 954 * @brief EGet the enable or disable status of the APB2 peripheral clock. 955 * @note After reset, the peripheral clock (used for registers read/write access) 956 * is disabled and the application software has to enable this clock before 957 * using it. 958 * @{ 959 */ 960 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) 961 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) 962 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) 963 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) 964 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) 965 966 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) 967 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) 968 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) 969 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) 970 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) 971 /** 972 * @} 973 */ 974 975 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset 976 * @brief Force or release AHB peripheral reset. 977 * @{ 978 */ 979 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) 980 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) 981 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) 982 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) 983 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) 984 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) 985 #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) 986 987 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) 988 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) 989 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) 990 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) 991 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) 992 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) 993 #define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) 994 /** 995 * @} 996 */ 997 998 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset 999 * @brief Force or release APB1 peripheral reset. 1000 * @{ 1001 */ 1002 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 1003 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 1004 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 1005 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) 1006 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) 1007 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 1008 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) 1009 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) 1010 #define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST)) 1011 1012 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) 1013 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 1014 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 1015 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) 1016 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) 1017 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 1018 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) 1019 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) 1020 #define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST)) 1021 /** 1022 * @} 1023 */ 1024 1025 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset 1026 * @brief Force or release APB2 peripheral reset. 1027 * @{ 1028 */ 1029 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 1030 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) 1031 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) 1032 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) 1033 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) 1034 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) 1035 1036 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) 1037 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) 1038 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) 1039 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) 1040 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) 1041 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) 1042 /** 1043 * @} 1044 */ 1045 1046 /** @defgroup RCC_HSI_Configuration HSI Configuration 1047 * @{ 1048 */ 1049 1050 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 1051 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 1052 * It is used (enabled by hardware) as system clock source after startup 1053 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 1054 * of the HSE used directly or indirectly as system clock (if the Clock 1055 * Security System CSS is enabled). 1056 * @note HSI can not be stopped if it is used as system clock source. In this case, 1057 * you have to select another source of the system clock then stop the HSI. 1058 * @note After enabling the HSI, the application software should wait on HSIRDY 1059 * flag to be set indicating that HSI clock is stable and can be used as 1060 * system clock source. 1061 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 1062 * clock cycles. 1063 */ 1064 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) 1065 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) 1066 1067 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 1068 * @note The calibration is used to compensate for the variations in voltage 1069 * and temperature that influence the frequency of the internal HSI RC. 1070 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. 1071 * (default is RCC_HSICALIBRATION_DEFAULT). 1072 * This parameter must be a number between 0 and 0x1F. 1073 */ 1074 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ 1075 (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM))) 1076 1077 /** 1078 * @} 1079 */ 1080 1081 /** @defgroup RCC_LSI_Configuration LSI Configuration 1082 * @{ 1083 */ 1084 1085 /** @brief Macro to enable the Internal Low Speed oscillator (LSI). 1086 * @note After enabling the LSI, the application software should wait on 1087 * LSIRDY flag to be set indicating that LSI clock is stable and can 1088 * be used to clock the IWDG and/or the RTC. 1089 */ 1090 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) 1091 1092 /** @brief Macro to disable the Internal Low Speed oscillator (LSI). 1093 * @note LSI can not be disabled if the IWDG is running. 1094 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 1095 * clock cycles. 1096 */ 1097 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) 1098 1099 /** 1100 * @} 1101 */ 1102 1103 /** @defgroup RCC_HSE_Configuration HSE Configuration 1104 * @{ 1105 */ 1106 1107 /** 1108 * @brief Macro to configure the External High Speed oscillator (HSE). 1109 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 1110 * supported by this macro. User should request a transition to HSE Off 1111 * first and then HSE On or HSE Bypass. 1112 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 1113 * software should wait on HSERDY flag to be set indicating that HSE clock 1114 * is stable and can be used to clock the PLL and/or system clock. 1115 * @note HSE state can not be changed if it is used directly or through the 1116 * PLL as system clock. In this case, you have to select another source 1117 * of the system clock then change the HSE state (ex. disable it). 1118 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 1119 * @note This function reset the CSSON bit, so if the clock security system(CSS) 1120 * was previously enabled you have to enable it again after calling this 1121 * function. 1122 * @param __STATE__ specifies the new state of the HSE. 1123 * This parameter can be one of the following values: 1124 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 1125 * 6 HSE oscillator clock cycles. 1126 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator 1127 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock 1128 */ 1129 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 1130 do{ \ 1131 if ((__STATE__) == RCC_HSE_ON) \ 1132 { \ 1133 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1134 } \ 1135 else if ((__STATE__) == RCC_HSE_OFF) \ 1136 { \ 1137 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 1138 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1139 } \ 1140 else if ((__STATE__) == RCC_HSE_BYPASS) \ 1141 { \ 1142 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1143 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1144 } \ 1145 else \ 1146 { \ 1147 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 1148 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1149 } \ 1150 }while(0U) 1151 1152 /** 1153 * @} 1154 */ 1155 1156 /** @defgroup RCC_LSE_Configuration LSE Configuration 1157 * @{ 1158 */ 1159 1160 /** 1161 * @brief Macro to configure the External Low Speed oscillator (LSE). 1162 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 1163 * @note As the LSE is in the Backup domain and write access is denied to 1164 * this domain after reset, you have to enable write access using 1165 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE 1166 * (to be done once after reset). 1167 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 1168 * software should wait on LSERDY flag to be set indicating that LSE clock 1169 * is stable and can be used to clock the RTC. 1170 * @param __STATE__ specifies the new state of the LSE. 1171 * This parameter can be one of the following values: 1172 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 1173 * 6 LSE oscillator clock cycles. 1174 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. 1175 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 1176 */ 1177 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 1178 do{ \ 1179 if ((__STATE__) == RCC_LSE_ON) \ 1180 { \ 1181 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 1182 } \ 1183 else if ((__STATE__) == RCC_LSE_OFF) \ 1184 { \ 1185 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 1186 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 1187 } \ 1188 else if ((__STATE__) == RCC_LSE_BYPASS) \ 1189 { \ 1190 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 1191 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 1192 } \ 1193 else \ 1194 { \ 1195 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 1196 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 1197 } \ 1198 }while(0U) 1199 1200 /** 1201 * @} 1202 */ 1203 1204 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config 1205 * @{ 1206 */ 1207 1208 /** @brief Macro to configure the USART1 clock (USART1CLK). 1209 * @param __USART1CLKSOURCE__ specifies the USART1 clock source. 1210 * This parameter can be one of the following values: 1211 @if STM32F302xC 1212 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1213 @endif 1214 @if STM32F303xC 1215 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1216 @endif 1217 @if STM32F358xx 1218 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1219 @endif 1220 @if STM32F302xE 1221 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1222 @endif 1223 @if STM32F303xE 1224 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1225 @endif 1226 @if STM32F398xx 1227 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1228 @endif 1229 @if STM32F373xC 1230 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1231 @endif 1232 @if STM32F378xx 1233 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1234 @endif 1235 @if STM32F301x8 1236 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1237 @endif 1238 @if STM32F302x8 1239 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1240 @endif 1241 @if STM32F318xx 1242 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1243 @endif 1244 @if STM32F303x8 1245 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1246 @endif 1247 @if STM32F334x8 1248 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1249 @endif 1250 @if STM32F328xx 1251 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1252 @endif 1253 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1254 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1255 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1256 */ 1257 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \ 1258 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__)) 1259 1260 /** @brief Macro to get the USART1 clock source. 1261 * @retval The clock source can be one of the following values: 1262 @if STM32F302xC 1263 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1264 @endif 1265 @if STM32F303xC 1266 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1267 @endif 1268 @if STM32F358xx 1269 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1270 @endif 1271 @if STM32F302xE 1272 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1273 @endif 1274 @if STM32F303xE 1275 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1276 @endif 1277 @if STM32F398xx 1278 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1279 @endif 1280 @if STM32F373xC 1281 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1282 @endif 1283 @if STM32F378xx 1284 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 1285 @endif 1286 @if STM32F301x8 1287 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1288 @endif 1289 @if STM32F302x8 1290 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1291 @endif 1292 @if STM32F318xx 1293 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1294 @endif 1295 @if STM32F303x8 1296 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1297 @endif 1298 @if STM32F334x8 1299 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1300 @endif 1301 @if STM32F328xx 1302 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock 1303 @endif 1304 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 1305 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 1306 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 1307 */ 1308 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) 1309 1310 #if defined(RCC_CFGR3_USART2SW) 1311 /** @brief Macro to configure the USART2 clock (USART2CLK). 1312 * @param __USART2CLKSOURCE__ specifies the USART2 clock source. 1313 * This parameter can be one of the following values: 1314 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1315 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1316 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1317 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1318 */ 1319 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \ 1320 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__)) 1321 1322 /** @brief Macro to get the USART2 clock source. 1323 * @retval The clock source can be one of the following values: 1324 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 1325 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 1326 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 1327 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 1328 */ 1329 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) 1330 #endif /* RCC_CFGR3_USART2SW */ 1331 1332 #if defined(RCC_CFGR3_USART3SW) 1333 /** @brief Macro to configure the USART3 clock (USART3CLK). 1334 * @param __USART3CLKSOURCE__ specifies the USART3 clock source. 1335 * This parameter can be one of the following values: 1336 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1337 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1338 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1339 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1340 */ 1341 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \ 1342 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__)) 1343 1344 /** @brief Macro to get the USART3 clock source. 1345 * @retval The clock source can be one of the following values: 1346 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 1347 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 1348 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 1349 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 1350 */ 1351 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) 1352 #endif /* RCC_CFGR3_USART2SW */ 1353 /** 1354 * @} 1355 */ 1356 1357 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config 1358 * @{ 1359 */ 1360 1361 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 1362 * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source. 1363 * This parameter can be one of the following values: 1364 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1365 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1366 */ 1367 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \ 1368 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__)) 1369 1370 /** @brief Macro to get the I2C1 clock source. 1371 * @retval The clock source can be one of the following values: 1372 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 1373 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 1374 */ 1375 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) 1376 /** 1377 * @} 1378 */ 1379 1380 /** @defgroup RCC_PLL_Configuration PLL Configuration 1381 * @{ 1382 */ 1383 1384 /** @brief Macro to enable the main PLL. 1385 * @note After enabling the main PLL, the application software should wait on 1386 * PLLRDY flag to be set indicating that PLL clock is stable and can 1387 * be used as system clock source. 1388 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 1389 */ 1390 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) 1391 1392 /** @brief Macro to disable the main PLL. 1393 * @note The main PLL can not be disabled if it is used as system clock source 1394 */ 1395 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) 1396 1397 1398 /** @brief Get oscillator clock selected as PLL input clock 1399 * @retval The clock source used for PLL entry. The returned value can be one 1400 * of the following: 1401 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock 1402 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock 1403 */ 1404 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) 1405 1406 /** 1407 * @} 1408 */ 1409 1410 /** @defgroup RCC_Get_Clock_source Get Clock source 1411 * @{ 1412 */ 1413 1414 /** 1415 * @brief Macro to configure the system clock source. 1416 * @param __SYSCLKSOURCE__ specifies the system clock source. 1417 * This parameter can be one of the following values: 1418 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 1419 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 1420 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 1421 */ 1422 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 1423 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 1424 1425 /** @brief Macro to get the clock source used as system clock. 1426 * @retval The clock source used as system clock. The returned value can be one 1427 * of the following: 1428 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock 1429 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock 1430 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock 1431 */ 1432 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) 1433 1434 /** 1435 * @} 1436 */ 1437 1438 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 1439 * @{ 1440 */ 1441 1442 #if defined(RCC_CFGR_MCOPRE) 1443 /** @brief Macro to configure the MCO clock. 1444 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1445 * This parameter can be one of the following values: 1446 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 1447 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock 1448 * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock 1449 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 1450 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock 1451 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock 1452 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock 1453 * @param __MCODIV__ specifies the MCO clock prescaler. 1454 * This parameter can be one of the following values: 1455 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 1456 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 1457 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 1458 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 1459 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 1460 * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 1461 * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 1462 * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 1463 */ 1464 #else 1465 /** @brief Macro to configure the MCO clock. 1466 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1467 * This parameter can be one of the following values: 1468 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 1469 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock 1470 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 1471 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 1472 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock 1473 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock 1474 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock 1475 * @param __MCODIV__ specifies the MCO clock prescaler. 1476 * This parameter can be one of the following values: 1477 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source 1478 */ 1479 #endif 1480 #if defined(RCC_CFGR_MCOPRE) 1481 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1482 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 1483 #else 1484 1485 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1486 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) 1487 1488 #endif 1489 1490 /** 1491 * @} 1492 */ 1493 1494 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 1495 * @{ 1496 */ 1497 1498 /** @brief Macro to configure the RTC clock (RTCCLK). 1499 * @note As the RTC clock configuration bits are in the Backup domain and write 1500 * access is denied to this domain after reset, you have to enable write 1501 * access using the Power Backup Access macro before to configure 1502 * the RTC clock source (to be done once after reset). 1503 * @note Once the RTC clock is configured it cannot be changed unless the 1504 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 1505 * a Power On Reset (POR). 1506 * 1507 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 1508 * This parameter can be one of the following values: 1509 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 1510 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 1511 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 1512 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 1513 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 1514 * work in STOP and STANDBY modes, and can be used as wakeup source. 1515 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, 1516 * the RTC cannot be used in STOP and STANDBY modes. 1517 * @note The system must always be configured so as to get a PCLK frequency greater than or 1518 * equal to the RTCCLK frequency for a proper operation of the RTC. 1519 */ 1520 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 1521 1522 /** @brief Macro to get the RTC clock source. 1523 * @retval The clock source can be one of the following values: 1524 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 1525 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 1526 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 1527 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 1528 */ 1529 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 1530 1531 /** @brief Macro to enable the the RTC clock. 1532 * @note These macros must be used only after the RTC clock source was selected. 1533 */ 1534 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) 1535 1536 /** @brief Macro to disable the the RTC clock. 1537 * @note These macros must be used only after the RTC clock source was selected. 1538 */ 1539 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) 1540 1541 /** @brief Macro to force the Backup domain reset. 1542 * @note This function resets the RTC peripheral (including the backup registers) 1543 * and the RTC clock source selection in RCC_BDCR register. 1544 */ 1545 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) 1546 1547 /** @brief Macros to release the Backup domain reset. 1548 */ 1549 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) 1550 1551 /** 1552 * @} 1553 */ 1554 1555 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 1556 * @brief macros to manage the specified RCC Flags and interrupts. 1557 * @{ 1558 */ 1559 1560 /** @brief Enable RCC interrupt. 1561 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 1562 * This parameter can be any combination of the following values: 1563 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1564 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1565 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1566 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1567 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1568 */ 1569 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) 1570 1571 /** @brief Disable RCC interrupt. 1572 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 1573 * This parameter can be any combination of the following values: 1574 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1575 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1576 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1577 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1578 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1579 */ 1580 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) 1581 1582 /** @brief Clear the RCC's interrupt pending bits. 1583 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1584 * This parameter can be any combination of the following values: 1585 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 1586 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 1587 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 1588 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 1589 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 1590 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1591 */ 1592 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) 1593 1594 /** @brief Check the RCC's interrupt has occurred or not. 1595 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 1596 * This parameter can be one of the following values: 1597 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 1598 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 1599 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 1600 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 1601 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 1602 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1603 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 1604 */ 1605 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) 1606 1607 /** @brief Set RMVF bit to clear the reset flags. 1608 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, 1609 * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST 1610 */ 1611 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) 1612 1613 /** @brief Check RCC flag is set or not. 1614 * @param __FLAG__ specifies the flag to check. 1615 * This parameter can be one of the following values: 1616 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. 1617 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. 1618 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. 1619 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. 1620 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. 1621 * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset 1622 * @arg @ref RCC_FLAG_PINRST Pin reset. 1623 * @arg @ref RCC_FLAG_PORRST POR/PDR reset. 1624 * @arg @ref RCC_FLAG_SFTRST Software reset. 1625 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. 1626 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. 1627 * @arg @ref RCC_FLAG_LPWRRST Low Power reset. 1628 @if defined(STM32F301x8) 1629 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1630 @endif 1631 @if defined(STM32F302x8) 1632 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1633 @endif 1634 @if defined(STM32F302xC) 1635 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1636 * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output 1637 @endif 1638 @if defined(STM32F302xE) 1639 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1640 @endif 1641 @if defined(STM32F303x8) 1642 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1643 @endif 1644 @if defined(STM32F303xC) 1645 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1646 * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output 1647 @endif 1648 @if defined(STM32F303xE) 1649 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1650 @endif 1651 @if defined(STM32F334x8) 1652 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1653 @endif 1654 @if defined(STM32F358xx) 1655 * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output 1656 @endif 1657 @if defined(STM32F373xC) 1658 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain 1659 @endif 1660 * @retval The new state of __FLAG__ (TRUE or FALSE). 1661 */ 1662 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ 1663 (((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ 1664 (((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \ 1665 RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) 1666 1667 /** 1668 * @} 1669 */ 1670 1671 /** 1672 * @} 1673 */ 1674 1675 /* Include RCC HAL Extension module */ 1676 #include "stm32f3xx_hal_rcc_ex.h" 1677 1678 /* Exported functions --------------------------------------------------------*/ 1679 /** @addtogroup RCC_Exported_Functions 1680 * @{ 1681 */ 1682 1683 /** @addtogroup RCC_Exported_Functions_Group1 1684 * @{ 1685 */ 1686 1687 /* Initialization and de-initialization functions ******************************/ 1688 HAL_StatusTypeDef HAL_RCC_DeInit(void); 1689 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1690 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 1691 1692 /** 1693 * @} 1694 */ 1695 1696 /** @addtogroup RCC_Exported_Functions_Group2 1697 * @{ 1698 */ 1699 1700 /* Peripheral Control functions ************************************************/ 1701 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 1702 void HAL_RCC_EnableCSS(void); 1703 /* CSS NMI IRQ handler */ 1704 void HAL_RCC_NMI_IRQHandler(void); 1705 /* User Callbacks in non blocking mode (IT mode) */ 1706 void HAL_RCC_CSSCallback(void); 1707 void HAL_RCC_DisableCSS(void); 1708 uint32_t HAL_RCC_GetSysClockFreq(void); 1709 uint32_t HAL_RCC_GetHCLKFreq(void); 1710 uint32_t HAL_RCC_GetPCLK1Freq(void); 1711 uint32_t HAL_RCC_GetPCLK2Freq(void); 1712 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1713 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 1714 1715 /** 1716 * @} 1717 */ 1718 1719 /** 1720 * @} 1721 */ 1722 1723 /** 1724 * @} 1725 */ 1726 1727 /** 1728 * @} 1729 */ 1730 1731 #ifdef __cplusplus 1732 } 1733 #endif 1734 1735 #endif /* __STM32F3xx_HAL_RCC_H */ 1736 1737 1738
