1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2016 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef __STM32F3xx_LL_BUS_H
37 #define __STM32F3xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32f3xx.h"
45
46 /** @addtogroup STM32F3xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58
59 /* Private constants ---------------------------------------------------------*/
60
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
70 * @{
71 */
72 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
73 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
74 #if defined(DMA2)
75 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
76 #endif /*DMA2*/
77 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
78 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
79 #if defined(FMC_Bank1)
80 #define LL_AHB1_GRP1_PERIPH_FMC RCC_AHBENR_FMCEN
81 #endif /*FMC_Bank1*/
82 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
83 #if defined(GPIOH)
84 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN
85 #endif /*GPIOH*/
86 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
87 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
88 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
89 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
90 #if defined(GPIOE)
91 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
92 #endif /*GPIOE*/
93 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
94 #if defined(GPIOG)
95 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN
96 #endif /*GPIOH*/
97 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
98 #if defined(RCC_AHBENR_ADC1EN)
99 #define LL_AHB1_GRP1_PERIPH_ADC1 RCC_AHBENR_ADC1EN
100 #endif /*RCC_AHBENR_ADC1EN*/
101 #if defined(ADC1_2_COMMON)
102 #define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHBENR_ADC12EN
103 #endif /*ADC1_2_COMMON*/
104 #if defined(ADC3_4_COMMON)
105 #define LL_AHB1_GRP1_PERIPH_ADC34 RCC_AHBENR_ADC34EN
106 #endif /*ADC3_4_COMMON*/
107 /**
108 * @}
109 */
110
111 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
112 * @{
113 */
114 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
115 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
116 #if defined(TIM3)
117 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
118 #endif /*TIM3*/
119 #if defined(TIM4)
120 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
121 #endif /*TIM4*/
122 #if defined(TIM5)
123 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
124 #endif /*TIM5*/
125 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
126 #if defined(TIM7)
127 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
128 #endif /*TIM7*/
129 #if defined(TIM12)
130 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
131 #endif /*TIM12*/
132 #if defined(TIM13)
133 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
134 #endif /*TIM13*/
135 #if defined(TIM14)
136 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
137 #endif /*TIM14*/
138 #if defined(TIM18)
139 #define LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN
140 #endif /*TIM18*/
141 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
142 #if defined(SPI2)
143 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
144 #endif /*SPI2*/
145 #if defined(SPI3)
146 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
147 #endif /*SPI3*/
148 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
149 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
150 #if defined(UART4)
151 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
152 #endif /*UART4*/
153 #if defined(UART5)
154 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
155 #endif /*UART5*/
156 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
157 #if defined(I2C2)
158 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
159 #endif /*I2C2*/
160 #if defined(USB)
161 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
162 #endif /*USB*/
163 #if defined(CAN)
164 #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
165 #endif /*CAN*/
166 #if defined(DAC2)
167 #define LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN
168 #endif /*DAC2*/
169 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
170 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN
171 #if defined(CEC)
172 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
173 #endif /*CEC*/
174 #if defined(I2C3)
175 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
176 #endif /*I2C3*/
177 /**
178 * @}
179 */
180
181 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
182 * @{
183 */
184 #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
185 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
186 #if defined(RCC_APB2ENR_ADC1EN)
187 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
188 #endif /*RCC_APB2ENR_ADC1EN*/
189 #if defined(TIM1)
190 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
191 #endif /*TIM1*/
192 #if defined(SPI1)
193 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
194 #endif /*SPI1*/
195 #if defined(TIM8)
196 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
197 #endif /*TIM8*/
198 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
199 #if defined(SPI4)
200 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
201 #endif /*SPI4*/
202 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
203 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
204 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
205 #if defined(TIM19)
206 #define LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN
207 #endif /*TIM19*/
208 #if defined(TIM20)
209 #define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN
210 #endif /*TIM20*/
211 #if defined(HRTIM1)
212 #define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN
213 #endif /*HRTIM1*/
214 #if defined(SDADC1)
215 #define LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN
216 #endif /*SDADC1*/
217 #if defined(SDADC2)
218 #define LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN
219 #endif /*SDADC2*/
220 #if defined(SDADC3)
221 #define LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN
222 #endif /*SDADC3*/
223 /**
224 * @}
225 */
226
227 /**
228 * @}
229 */
230
231 /* Exported macro ------------------------------------------------------------*/
232
233 /* Exported functions --------------------------------------------------------*/
234 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
235 * @{
236 */
237
238 /** @defgroup BUS_LL_EF_AHB1 AHB1
239 * @{
240 */
241
242 /**
243 * @brief Enable AHB1 peripherals clock.
244 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
245 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
246 * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
247 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
248 * AHBENR FMCEN LL_AHB1_GRP1_EnableClock\n
249 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
250 * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
251 * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
252 * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
253 * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
254 * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
255 * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
256 * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
257 * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
258 * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n
259 * AHBENR ADC1EN LL_AHB1_GRP1_EnableClock\n
260 * AHBENR ADC12EN LL_AHB1_GRP1_EnableClock\n
261 * AHBENR ADC34EN LL_AHB1_GRP1_EnableClock
262 * @param Periphs This parameter can be a combination of the following values:
263 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
264 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
265 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
266 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
267 * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
268 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
269 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
270 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
271 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
272 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
273 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
274 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
275 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
276 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
277 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
278 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
279 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
280 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
281 *
282 * (*) value not defined in all devices.
283 * @retval None
284 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)285 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
286 {
287 __IO uint32_t tmpreg;
288 SET_BIT(RCC->AHBENR, Periphs);
289 /* Delay after an RCC peripheral clock enabling */
290 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
291 (void)tmpreg;
292 }
293
294 /**
295 * @brief Check if AHB1 peripheral clock is enabled or not
296 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
297 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
298 * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
299 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
300 * AHBENR FMCEN LL_AHB1_GRP1_IsEnabledClock\n
301 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
302 * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
303 * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
304 * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
305 * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
306 * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
307 * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
308 * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
309 * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
310 * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
311 * AHBENR ADC1EN LL_AHB1_GRP1_IsEnabledClock\n
312 * AHBENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n
313 * AHBENR ADC34EN LL_AHB1_GRP1_IsEnabledClock
314 * @param Periphs This parameter can be a combination of the following values:
315 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
316 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
317 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
318 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
319 * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
320 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
321 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
322 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
323 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
324 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
325 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
326 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
327 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
328 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
329 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
330 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
331 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
332 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
333 *
334 * (*) value not defined in all devices.
335 * @retval State of Periphs (1 or 0).
336 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)337 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
338 {
339 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
340 }
341
342 /**
343 * @brief Disable AHB1 peripherals clock.
344 * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
345 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
346 * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
347 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
348 * AHBENR FMCEN LL_AHB1_GRP1_DisableClock\n
349 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
350 * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
351 * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
352 * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
353 * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
354 * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
355 * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
356 * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
357 * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
358 * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n
359 * AHBENR ADC1EN LL_AHB1_GRP1_DisableClock\n
360 * AHBENR ADC12EN LL_AHB1_GRP1_DisableClock\n
361 * AHBENR ADC34EN LL_AHB1_GRP1_DisableClock
362 * @param Periphs This parameter can be a combination of the following values:
363 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
364 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
365 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
366 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
367 * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
368 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
369 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
370 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
371 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
372 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
373 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
374 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
375 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
376 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
377 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
378 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
379 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
380 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
381 *
382 * (*) value not defined in all devices.
383 * @retval None
384 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)385 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
386 {
387 CLEAR_BIT(RCC->AHBENR, Periphs);
388 }
389
390 /**
391 * @brief Force AHB1 peripherals reset.
392 * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ForceReset\n
393 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
394 * AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
395 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
396 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
397 * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
398 * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
399 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
400 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
401 * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n
402 * AHBRSTR ADC1RST LL_AHB1_GRP1_ForceReset\n
403 * AHBRSTR ADC12RST LL_AHB1_GRP1_ForceReset\n
404 * AHBRSTR ADC34RST LL_AHB1_GRP1_ForceReset
405 * @param Periphs This parameter can be a combination of the following values:
406 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
407 * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
408 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
409 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
410 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
411 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
412 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
413 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
414 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
415 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
416 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
417 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
418 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
419 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
420 *
421 * (*) value not defined in all devices.
422 * @retval None
423 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)424 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
425 {
426 SET_BIT(RCC->AHBRSTR, Periphs);
427 }
428
429 /**
430 * @brief Release AHB1 peripherals reset.
431 * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ReleaseReset\n
432 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
433 * AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
434 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
435 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
436 * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
437 * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
438 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
439 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
440 * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
441 * AHBRSTR ADC1RST LL_AHB1_GRP1_ReleaseReset\n
442 * AHBRSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n
443 * AHBRSTR ADC34RST LL_AHB1_GRP1_ReleaseReset
444 * @param Periphs This parameter can be a combination of the following values:
445 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
446 * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
447 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
448 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
449 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
450 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
451 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
452 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
453 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
454 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
455 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
456 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
457 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
458 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
459 *
460 * (*) value not defined in all devices.
461 * @retval None
462 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)463 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
464 {
465 CLEAR_BIT(RCC->AHBRSTR, Periphs);
466 }
467
468 /**
469 * @}
470 */
471
472 /** @defgroup BUS_LL_EF_APB1 APB1
473 * @{
474 */
475
476 /**
477 * @brief Enable APB1 peripherals clock.
478 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
479 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
480 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
481 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
482 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
483 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
484 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
485 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
486 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
487 * APB1ENR TIM18EN LL_APB1_GRP1_EnableClock\n
488 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
489 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
490 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
491 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
492 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
493 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
494 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
495 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
496 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
497 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
498 * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
499 * APB1ENR DAC2EN LL_APB1_GRP1_EnableClock\n
500 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
501 * APB1ENR DAC1EN LL_APB1_GRP1_EnableClock\n
502 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
503 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock
504 * @param Periphs This parameter can be a combination of the following values:
505 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
506 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
507 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
508 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
509 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
510 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
511 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
512 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
513 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
514 * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
515 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
516 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
517 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
518 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
519 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
520 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
521 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
522 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
523 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
524 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
525 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
526 * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
527 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
528 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
529 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
530 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
531 *
532 * (*) value not defined in all devices.
533 * @retval None
534 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)535 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
536 {
537 __IO uint32_t tmpreg;
538 SET_BIT(RCC->APB1ENR, Periphs);
539 /* Delay after an RCC peripheral clock enabling */
540 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
541 (void)tmpreg;
542 }
543
544 /**
545 * @brief Check if APB1 peripheral clock is enabled or not
546 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
547 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
548 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
549 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
550 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
551 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
552 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
553 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
554 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
555 * APB1ENR TIM18EN LL_APB1_GRP1_IsEnabledClock\n
556 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
557 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
558 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
559 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
560 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
561 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
562 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
563 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
564 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
565 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
566 * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
567 * APB1ENR DAC2EN LL_APB1_GRP1_IsEnabledClock\n
568 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
569 * APB1ENR DAC1EN LL_APB1_GRP1_IsEnabledClock\n
570 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
571 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock
572 * @param Periphs This parameter can be a combination of the following values:
573 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
574 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
575 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
576 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
577 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
578 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
579 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
580 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
581 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
582 * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
583 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
584 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
585 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
586 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
587 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
588 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
589 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
590 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
591 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
592 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
593 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
594 * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
595 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
596 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
597 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
598 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
599 *
600 * (*) value not defined in all devices.
601 * @retval State of Periphs (1 or 0).
602 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)603 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
604 {
605 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
606 }
607
608 /**
609 * @brief Disable APB1 peripherals clock.
610 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
611 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
612 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
613 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
614 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
615 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
616 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
617 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
618 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
619 * APB1ENR TIM18EN LL_APB1_GRP1_DisableClock\n
620 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
621 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
622 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
623 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
624 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
625 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
626 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
627 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
628 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
629 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
630 * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
631 * APB1ENR DAC2EN LL_APB1_GRP1_DisableClock\n
632 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
633 * APB1ENR DAC1EN LL_APB1_GRP1_DisableClock\n
634 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
635 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock
636 * @param Periphs This parameter can be a combination of the following values:
637 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
638 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
639 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
640 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
641 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
642 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
643 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
644 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
645 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
646 * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
647 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
648 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
649 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
650 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
651 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
652 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
653 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
654 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
655 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
656 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
657 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
658 * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
659 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
660 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
661 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
662 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
663 *
664 * (*) value not defined in all devices.
665 * @retval None
666 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)667 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
668 {
669 CLEAR_BIT(RCC->APB1ENR, Periphs);
670 }
671
672 /**
673 * @brief Force APB1 peripherals reset.
674 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
675 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
676 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
677 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
678 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
679 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
680 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
681 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
682 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
683 * APB1RSTR TIM18RST LL_APB1_GRP1_ForceReset\n
684 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
685 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
686 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
687 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
688 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
689 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
690 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
691 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
692 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
693 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
694 * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
695 * APB1RSTR DAC2RST LL_APB1_GRP1_ForceReset\n
696 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
697 * APB1RSTR DAC1RST LL_APB1_GRP1_ForceReset\n
698 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
699 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset
700 * @param Periphs This parameter can be a combination of the following values:
701 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
702 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
703 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
704 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
705 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
706 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
707 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
708 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
709 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
710 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
711 * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
712 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
713 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
714 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
715 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
716 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
717 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
718 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
719 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
720 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
721 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
722 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
723 * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
724 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
725 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
726 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
727 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
728 *
729 * (*) value not defined in all devices.
730 * @retval None
731 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)732 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
733 {
734 SET_BIT(RCC->APB1RSTR, Periphs);
735 }
736
737 /**
738 * @brief Release APB1 peripherals reset.
739 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
740 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
741 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
742 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
743 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
744 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
745 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
746 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
747 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
748 * APB1RSTR TIM18RST LL_APB1_GRP1_ReleaseReset\n
749 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
750 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
751 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
752 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
753 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
754 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
755 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
756 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
757 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
758 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
759 * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
760 * APB1RSTR DAC2RST LL_APB1_GRP1_ReleaseReset\n
761 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
762 * APB1RSTR DAC1RST LL_APB1_GRP1_ReleaseReset\n
763 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
764 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset
765 * @param Periphs This parameter can be a combination of the following values:
766 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
767 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
768 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
769 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
770 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
771 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
772 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
773 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
774 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
775 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
776 * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
777 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
778 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
779 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
780 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
781 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
782 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
783 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
784 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
785 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
786 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
787 * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
788 * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
789 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
790 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
791 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
792 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
793 *
794 * (*) value not defined in all devices.
795 * @retval None
796 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)797 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
798 {
799 CLEAR_BIT(RCC->APB1RSTR, Periphs);
800 }
801
802 /**
803 * @}
804 */
805
806 /** @defgroup BUS_LL_EF_APB2 APB2
807 * @{
808 */
809
810 /**
811 * @brief Enable APB2 peripherals clock.
812 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
813 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
814 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
815 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
816 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
817 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
818 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
819 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
820 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
821 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
822 * APB2ENR TIM19EN LL_APB2_GRP1_EnableClock\n
823 * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n
824 * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock\n
825 * APB2ENR SDADC1EN LL_APB2_GRP1_EnableClock\n
826 * APB2ENR SDADC2EN LL_APB2_GRP1_EnableClock\n
827 * APB2ENR SDADC3EN LL_APB2_GRP1_EnableClock
828 * @param Periphs This parameter can be a combination of the following values:
829 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
830 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
831 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
832 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
833 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
834 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
835 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
836 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
837 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
838 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
839 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
840 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
841 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
842 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
843 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
844 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
845 *
846 * (*) value not defined in all devices.
847 * @retval None
848 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)849 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
850 {
851 __IO uint32_t tmpreg;
852 SET_BIT(RCC->APB2ENR, Periphs);
853 /* Delay after an RCC peripheral clock enabling */
854 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
855 (void)tmpreg;
856 }
857
858 /**
859 * @brief Check if APB2 peripheral clock is enabled or not
860 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
861 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
862 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
863 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
864 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
865 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
866 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
867 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
868 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
869 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
870 * APB2ENR TIM19EN LL_APB2_GRP1_IsEnabledClock\n
871 * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n
872 * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock\n
873 * APB2ENR SDADC1EN LL_APB2_GRP1_IsEnabledClock\n
874 * APB2ENR SDADC2EN LL_APB2_GRP1_IsEnabledClock\n
875 * APB2ENR SDADC3EN LL_APB2_GRP1_IsEnabledClock
876 * @param Periphs This parameter can be a combination of the following values:
877 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
878 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
879 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
880 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
881 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
882 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
883 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
884 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
885 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
886 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
887 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
888 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
889 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
890 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
891 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
892 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
893 *
894 * (*) value not defined in all devices.
895 * @retval State of Periphs (1 or 0).
896 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)897 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
898 {
899 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
900 }
901
902 /**
903 * @brief Disable APB2 peripherals clock.
904 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
905 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
906 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
907 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
908 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
909 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
910 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
911 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
912 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
913 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
914 * APB2ENR TIM19EN LL_APB2_GRP1_DisableClock\n
915 * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n
916 * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock\n
917 * APB2ENR SDADC1EN LL_APB2_GRP1_DisableClock\n
918 * APB2ENR SDADC2EN LL_APB2_GRP1_DisableClock\n
919 * APB2ENR SDADC3EN LL_APB2_GRP1_DisableClock
920 * @param Periphs This parameter can be a combination of the following values:
921 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
922 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
923 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
924 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
925 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
926 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
927 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
928 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
929 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
930 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
931 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
932 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
933 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
934 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
935 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
936 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
937 *
938 * (*) value not defined in all devices.
939 * @retval None
940 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)941 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
942 {
943 CLEAR_BIT(RCC->APB2ENR, Periphs);
944 }
945
946 /**
947 * @brief Force APB2 peripherals reset.
948 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
949 * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
950 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
951 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
952 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
953 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
954 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
955 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
956 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
957 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
958 * APB2RSTR TIM19RST LL_APB2_GRP1_ForceReset\n
959 * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
960 * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset\n
961 * APB2RSTR SDADC1RST LL_APB2_GRP1_ForceReset\n
962 * APB2RSTR SDADC2RST LL_APB2_GRP1_ForceReset\n
963 * APB2RSTR SDADC3RST LL_APB2_GRP1_ForceReset
964 * @param Periphs This parameter can be a combination of the following values:
965 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
966 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
967 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
968 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
969 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
970 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
971 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
972 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
973 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
974 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
975 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
976 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
977 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
978 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
979 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
980 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
981 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
982 *
983 * (*) value not defined in all devices.
984 * @retval None
985 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)986 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
987 {
988 SET_BIT(RCC->APB2RSTR, Periphs);
989 }
990
991 /**
992 * @brief Release APB2 peripherals reset.
993 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
994 * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
995 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
996 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
997 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
998 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
999 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
1000 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
1001 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
1002 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
1003 * APB2RSTR TIM19RST LL_APB2_GRP1_ReleaseReset\n
1004 * APB2RSTR TIM20RST LL_APB2_GRP1_ReleaseReset\n
1005 * APB2RSTR HRTIM1RST LL_APB2_GRP1_ReleaseReset\n
1006 * APB2RSTR SDADC1RST LL_APB2_GRP1_ReleaseReset\n
1007 * APB2RSTR SDADC2RST LL_APB2_GRP1_ReleaseReset\n
1008 * APB2RSTR SDADC3RST LL_APB2_GRP1_ReleaseReset
1009 * @param Periphs This parameter can be a combination of the following values:
1010 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1011 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1012 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
1013 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
1014 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
1015 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1016 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1017 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1018 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1019 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1020 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1021 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
1022 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1023 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1024 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
1025 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
1026 * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
1027 *
1028 * (*) value not defined in all devices.
1029 * @retval None
1030 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1031 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1032 {
1033 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1034 }
1035
1036 /**
1037 * @}
1038 */
1039
1040
1041 /**
1042 * @}
1043 */
1044
1045 /**
1046 * @}
1047 */
1048
1049 #endif /* defined(RCC) */
1050
1051 /**
1052 * @}
1053 */
1054
1055 #ifdef __cplusplus
1056 }
1057 #endif
1058
1059 #endif /* __STM32F3xx_LL_BUS_H */
1060
1061
