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Searched refs:DMA_MISR_MIS0 (Results 1 – 23 of 23) sorted by relevance

/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_dma.h4004 return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU))) in LL_DMA_IsActiveFlag_MIS()
4005 == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_MIS()
/hal_stm32-3.5.0/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dma.h6250 return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU))) in LL_DMA_IsActiveFlag_MIS()
6251 == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_MIS()
/hal_stm32-3.5.0/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dma.h6768 return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU))) in LL_DMA_IsActiveFlag_MIS()
6769 == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL); in LL_DMA_IsActiveFlag_MIS()
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h2105 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32wba52xx.h2688 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32wba54xx.h2870 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32wba55xx.h2870 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
/hal_stm32-3.5.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h3756 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32h562xx.h5435 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32h563xx.h7519 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32h573xx.h7954 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
/hal_stm32-3.5.0/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h6092 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32u535xx.h5692 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32u575xx.h6091 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32u5a5xx.h6794 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32u585xx.h6540 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32u5f7xx.h6641 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32u595xx.h6345 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32u599xx.h6633 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32u5g7xx.h7090 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32u5a9xx.h7082 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32u5g9xx.h7210 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro
Dstm32u5f9xx.h6761 #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Int… macro